2 * Marvell Wireless LAN device driver: SDIO specific definitions
4 * Copyright (C) 2011-2014, Marvell International Ltd.
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
20 #ifndef _MWIFIEX_SDIO_H
21 #define _MWIFIEX_SDIO_H
24 #include <linux/mmc/sdio.h>
25 #include <linux/mmc/sdio_ids.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/mmc/host.h>
32 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
33 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
34 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
35 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
36 #define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
37 #define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin"
44 #define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
46 #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
48 #define MWIFIEX_MAX_FUNC2_REG_NUM 13
49 #define MWIFIEX_SDIO_SCRATCH_SIZE 10
51 #define SDIO_MPA_ADDR_BASE 0x1000
53 #define CTRL_PORT_MASK 0x0001
55 #define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
56 #define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
57 #define HOST_TERM_CMD53 (0x1U << 2)
59 #define MEM_PORT 0x10000
61 #define CMD53_NEW_MODE (0x1U << 0)
62 #define CMD_PORT_RD_LEN_EN (0x1U << 2)
63 #define CMD_PORT_AUTO_EN (0x1U << 0)
64 #define CMD_PORT_SLCT 0x8000
65 #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
66 #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
68 #define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384)
69 #define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768)
70 /* we leave one block of 256 bytes for DMA alignment*/
71 #define MWIFIEX_MP_AGGR_BUF_SIZE_MAX (65280)
73 /* Misc. Config Register : Auto Re-enable interrupts */
74 #define AUTO_RE_ENABLE_INT BIT(4)
76 /* Host Control Registers : Configuration */
77 #define CONFIGURATION_REG 0x00
78 /* Host Control Registers : Host power up */
79 #define HOST_POWER_UP (0x1U << 1)
81 /* Host Control Registers : Upload host interrupt mask */
82 #define UP_LD_HOST_INT_MASK (0x1U)
83 /* Host Control Registers : Download host interrupt mask */
84 #define DN_LD_HOST_INT_MASK (0x2U)
86 /* Host Control Registers : Upload host interrupt status */
87 #define UP_LD_HOST_INT_STATUS (0x1U)
88 /* Host Control Registers : Download host interrupt status */
89 #define DN_LD_HOST_INT_STATUS (0x2U)
91 /* Host Control Registers : Host interrupt status */
92 #define CARD_INT_STATUS_REG 0x28
94 /* Card Control Registers : Card I/O ready */
95 #define CARD_IO_READY (0x1U << 3)
96 /* Card Control Registers : Download card ready */
97 #define DN_LD_CARD_RDY (0x1U << 0)
99 /* Max retry number of CMD53 write */
100 #define MAX_WRITE_IOMEM_RETRY 2
102 /* SDIO Tx aggregation in progress ? */
103 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
105 /* SDIO Tx aggregation buffer room for next packet ? */
106 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
107 <= a->mpa_tx.buf_size)
109 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
110 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
111 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
113 a->mpa_tx.buf_len += pkt_len; \
114 if (!a->mpa_tx.pkt_cnt) \
115 a->mpa_tx.start_port = port; \
116 if (a->mpa_tx.start_port <= port) \
117 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
119 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \
122 a->mpa_tx.pkt_cnt++; \
125 /* SDIO Tx aggregation limit ? */
126 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
127 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
129 /* Reset SDIO Tx aggregation buffer parameters */
130 #define MP_TX_AGGR_BUF_RESET(a) do { \
131 a->mpa_tx.pkt_cnt = 0; \
132 a->mpa_tx.buf_len = 0; \
133 a->mpa_tx.ports = 0; \
134 a->mpa_tx.start_port = 0; \
137 /* SDIO Rx aggregation limit ? */
138 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
139 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
141 /* SDIO Rx aggregation in progress ? */
142 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
144 /* SDIO Rx aggregation buffer room for next packet ? */
145 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
146 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
148 /* Reset SDIO Rx aggregation buffer parameters */
149 #define MP_RX_AGGR_BUF_RESET(a) do { \
150 a->mpa_rx.pkt_cnt = 0; \
151 a->mpa_rx.buf_len = 0; \
152 a->mpa_rx.ports = 0; \
153 a->mpa_rx.start_port = 0; \
156 /* data structure for SDIO MPA TX */
157 struct mwifiex_sdio_mpa_tx {
158 /* multiport tx aggregation buffer pointer */
169 struct mwifiex_sdio_mpa_rx {
176 struct sk_buff **skb_arr;
184 int mwifiex_bus_register(void);
185 void mwifiex_bus_unregister(void);
187 struct mwifiex_sdio_card_reg {
195 u8 host_int_status_reg;
196 u8 host_int_mask_reg;
215 u8 card_misc_cfg_reg;
228 u8 func1_dump_reg_start;
229 u8 func1_dump_reg_end;
230 u8 func1_scratch_reg;
231 u8 func1_spec_reg_num;
232 u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM];
235 struct sdio_mmc_card {
236 struct sdio_func *func;
237 struct mwifiex_adapter *adapter;
239 const char *firmware;
240 const struct mwifiex_sdio_card_reg *reg;
244 u32 mp_tx_agg_buf_size;
245 u32 mp_rx_agg_buf_size;
251 u32 mp_data_port_mask;
257 bool supports_sdio_new_mode;
258 bool has_control_mask;
263 struct mwifiex_sdio_mpa_tx mpa_tx;
264 struct mwifiex_sdio_mpa_rx mpa_rx;
267 struct mwifiex_sdio_device {
268 const char *firmware;
269 const struct mwifiex_sdio_card_reg *reg;
273 u32 mp_tx_agg_buf_size;
274 u32 mp_rx_agg_buf_size;
275 bool supports_sdio_new_mode;
276 bool has_control_mask;
282 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
285 .base_0_reg = 0x0040,
286 .base_1_reg = 0x0041,
288 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
289 .host_int_rsr_reg = 0x1,
290 .host_int_mask_reg = 0x02,
291 .host_int_status_reg = 0x03,
292 .status_reg_0 = 0x60,
293 .status_reg_1 = 0x61,
294 .sdio_int_mask = 0x3f,
295 .data_port_mask = 0x0000fffe,
296 .io_port_0_reg = 0x78,
297 .io_port_1_reg = 0x79,
298 .io_port_2_reg = 0x7A,
306 .card_misc_cfg_reg = 0x6c,
307 .func1_dump_reg_start = 0x0,
308 .func1_dump_reg_end = 0x9,
309 .func1_scratch_reg = 0x60,
310 .func1_spec_reg_num = 5,
311 .func1_spec_reg_table = {0x28, 0x30, 0x34, 0x38, 0x3c},
314 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
320 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
321 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
322 .host_int_rsr_reg = 0x1,
323 .host_int_status_reg = 0x03,
324 .host_int_mask_reg = 0x02,
325 .status_reg_0 = 0xc0,
326 .status_reg_1 = 0xc1,
327 .sdio_int_mask = 0xff,
328 .data_port_mask = 0xffffffff,
329 .io_port_0_reg = 0xD8,
330 .io_port_1_reg = 0xD9,
331 .io_port_2_reg = 0xDA,
335 .rd_bitmap_1l = 0x06,
336 .rd_bitmap_1u = 0x07,
339 .wr_bitmap_1l = 0x0a,
340 .wr_bitmap_1u = 0x0b,
343 .card_misc_cfg_reg = 0xcc,
344 .card_cfg_2_1_reg = 0xcd,
345 .cmd_rd_len_0 = 0xb4,
346 .cmd_rd_len_1 = 0xb5,
347 .cmd_rd_len_2 = 0xb6,
348 .cmd_rd_len_3 = 0xb7,
353 .fw_dump_ctrl = 0xe2,
354 .fw_dump_start = 0xe3,
356 .func1_dump_reg_start = 0x0,
357 .func1_dump_reg_end = 0xb,
358 .func1_scratch_reg = 0xc0,
359 .func1_spec_reg_num = 8,
360 .func1_spec_reg_table = {0x4C, 0x50, 0x54, 0x55, 0x58,
364 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = {
370 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
371 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
372 .host_int_rsr_reg = 0x4,
373 .host_int_status_reg = 0x0C,
374 .host_int_mask_reg = 0x08,
375 .status_reg_0 = 0x90,
376 .status_reg_1 = 0x91,
377 .sdio_int_mask = 0xff,
378 .data_port_mask = 0xffffffff,
379 .io_port_0_reg = 0xE4,
380 .io_port_1_reg = 0xE5,
381 .io_port_2_reg = 0xE6,
385 .rd_bitmap_1l = 0x12,
386 .rd_bitmap_1u = 0x13,
389 .wr_bitmap_1l = 0x16,
390 .wr_bitmap_1u = 0x17,
393 .card_misc_cfg_reg = 0xd8,
394 .card_cfg_2_1_reg = 0xd9,
395 .cmd_rd_len_0 = 0xc0,
396 .cmd_rd_len_1 = 0xc1,
397 .cmd_rd_len_2 = 0xc2,
398 .cmd_rd_len_3 = 0xc3,
403 .func1_dump_reg_start = 0x10,
404 .func1_dump_reg_end = 0x17,
405 .func1_scratch_reg = 0x90,
406 .func1_spec_reg_num = 13,
407 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60,
408 0x61, 0x62, 0x64, 0x65, 0x66,
412 static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
413 .firmware = SD8786_DEFAULT_FW_NAME,
414 .reg = &mwifiex_reg_sd87xx,
416 .mp_agg_pkt_limit = 8,
417 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
418 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
419 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
420 .supports_sdio_new_mode = false,
421 .has_control_mask = true,
422 .can_dump_fw = false,
423 .can_auto_tdls = false,
424 .can_ext_scan = false,
427 static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
428 .firmware = SD8787_DEFAULT_FW_NAME,
429 .reg = &mwifiex_reg_sd87xx,
431 .mp_agg_pkt_limit = 8,
432 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
433 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
434 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
435 .supports_sdio_new_mode = false,
436 .has_control_mask = true,
437 .can_dump_fw = false,
438 .can_auto_tdls = false,
439 .can_ext_scan = true,
442 static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
443 .firmware = SD8797_DEFAULT_FW_NAME,
444 .reg = &mwifiex_reg_sd87xx,
446 .mp_agg_pkt_limit = 8,
447 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
448 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
449 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
450 .supports_sdio_new_mode = false,
451 .has_control_mask = true,
452 .can_dump_fw = false,
453 .can_auto_tdls = false,
454 .can_ext_scan = true,
457 static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
458 .firmware = SD8897_DEFAULT_FW_NAME,
459 .reg = &mwifiex_reg_sd8897,
461 .mp_agg_pkt_limit = 16,
462 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
463 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
464 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
465 .supports_sdio_new_mode = true,
466 .has_control_mask = false,
468 .can_auto_tdls = false,
469 .can_ext_scan = true,
472 static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = {
473 .firmware = SD8887_DEFAULT_FW_NAME,
474 .reg = &mwifiex_reg_sd8887,
476 .mp_agg_pkt_limit = 16,
477 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
478 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
479 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
480 .supports_sdio_new_mode = true,
481 .has_control_mask = false,
482 .can_dump_fw = false,
483 .can_auto_tdls = true,
484 .can_ext_scan = true,
487 static const struct mwifiex_sdio_device mwifiex_sdio_sd8801 = {
488 .firmware = SD8801_DEFAULT_FW_NAME,
489 .reg = &mwifiex_reg_sd87xx,
491 .mp_agg_pkt_limit = 8,
492 .supports_sdio_new_mode = false,
493 .has_control_mask = true,
494 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
495 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
496 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
497 .can_dump_fw = false,
498 .can_auto_tdls = false,
499 .can_ext_scan = true,
503 * .cmdrsp_complete handler
505 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
508 dev_kfree_skb_any(skb);
513 * .event_complete handler
515 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
518 dev_kfree_skb_any(skb);
523 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
527 if (card->curr_rd_port < card->mpa_rx.start_port) {
528 if (card->supports_sdio_new_mode)
529 tmp = card->mp_end_port >> 1;
531 tmp = card->mp_agg_pkt_limit;
533 if (((card->max_ports - card->mpa_rx.start_port) +
534 card->curr_rd_port) >= tmp)
538 if (!card->supports_sdio_new_mode)
541 if ((card->curr_rd_port - card->mpa_rx.start_port) >=
542 (card->mp_end_port >> 1))
549 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
553 if (card->curr_wr_port < card->mpa_tx.start_port) {
554 if (card->supports_sdio_new_mode)
555 tmp = card->mp_end_port >> 1;
557 tmp = card->mp_agg_pkt_limit;
559 if (((card->max_ports - card->mpa_tx.start_port) +
560 card->curr_wr_port) >= tmp)
564 if (!card->supports_sdio_new_mode)
567 if ((card->curr_wr_port - card->mpa_tx.start_port) >=
568 (card->mp_end_port >> 1))
574 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
575 static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
578 card->mpa_rx.buf_len += rx_len;
580 if (!card->mpa_rx.pkt_cnt)
581 card->mpa_rx.start_port = port;
583 if (card->supports_sdio_new_mode) {
584 card->mpa_rx.ports |= (1 << port);
586 if (card->mpa_rx.start_port <= port)
587 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
589 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
591 card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL;
592 card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len;
593 card->mpa_rx.pkt_cnt++;
595 #endif /* _MWIFIEX_SDIO_H */