kernel/drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
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   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 Intel Deutschland GmbH
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
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  34  *
  35  * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
  36  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37  * Copyright(c) 2016 Intel Deutschland GmbH
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  51  *    contributors may be used to endorse or promote products derived
  52  *    from this software without specific prior written permission.
  53  *
  54  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  55  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  56  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  57  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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  64  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  65  *
  66  *****************************************************************************/
  67 #include <linux/pci.h>
  68 #include <linux/pci-aspm.h>
  69 #include <linux/interrupt.h>
  70 #include <linux/debugfs.h>
  71 #include <linux/sched.h>
  72 #include <linux/bitops.h>
  73 #include <linux/gfp.h>
  74 #include <linux/vmalloc.h>
  75
  76 #include "iwl-drv.h"
  77 #include "iwl-trans.h"
  78 #include "iwl-csr.h"
  79 #include "iwl-prph.h"
  80 #include "iwl-scd.h"
  81 #include "iwl-agn-hw.h"
  82 #include "iwl-fw-error-dump.h"
  83 #include "internal.h"
  84 #include "iwl-fh.h"
  85
  86 /* extended range in FW SRAM */
  87 #define IWL_FW_MEM_EXTENDED_START       0x40000
  88 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  89
  90 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  91 {
  92         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  93
  94         if (!trans_pcie->fw_mon_page)
  95                 return;
  96
  97         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  98                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
  99         __free_pages(trans_pcie->fw_mon_page,
 100                      get_order(trans_pcie->fw_mon_size));
 101         trans_pcie->fw_mon_page = NULL;
 102         trans_pcie->fw_mon_phys = 0;
 103         trans_pcie->fw_mon_size = 0;
 104 }
 105
 106 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 107 {
 108         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 109         struct page *page = NULL;
 110         dma_addr_t phys;
 111         u32 size = 0;
 112         u8 power;
 113
 114         if (!max_power) {
 115                 /* default max_power is maximum */
 116                 max_power = 26;
 117         } else {
 118                 max_power += 11;
 119         }
 120
 121         if (WARN(max_power > 26,
 122                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 123                  max_power))
 124                 return;
 125
 126         if (trans_pcie->fw_mon_page) {
 127                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 128                                            trans_pcie->fw_mon_size,
 129                                            DMA_FROM_DEVICE);
 130                 return;
 131         }
 132
 133         phys = 0;
 134         for (power = max_power; power >= 11; power--) {
 135                 int order;
 136
 137                 size = BIT(power);
 138                 order = get_order(size);
 139                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 140                                    order);
 141                 if (!page)
 142                         continue;
 143
 144                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 145                                     DMA_FROM_DEVICE);
 146                 if (dma_mapping_error(trans->dev, phys)) {
 147                         __free_pages(page, order);
 148                         page = NULL;
 149                         continue;
 150                 }
 151                 IWL_INFO(trans,
 152                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 153                          size, order);
 154                 break;
 155         }
 156
 157         if (WARN_ON_ONCE(!page))
 158                 return;
 159
 160         if (power != max_power)
 161                 IWL_ERR(trans,
 162                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 163                         (unsigned long)BIT(power - 10),
 164                         (unsigned long)BIT(max_power - 10));
 165
 166         trans_pcie->fw_mon_page = page;
 167         trans_pcie->fw_mon_phys = phys;
 168         trans_pcie->fw_mon_size = size;
 169 }
 170
 171 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 172 {
 173         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 174                     ((reg & 0x0000ffff) | (2 << 28)));
 175         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 176 }
 177
 178 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 179 {
 180         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 181         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 182                     ((reg & 0x0000ffff) | (3 << 28)));
 183 }
 184
 185 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 186 {
 187         if (trans->cfg->apmg_not_supported)
 188                 return;
 189
 190         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 191                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 192                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 193                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 194         else
 195                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 196                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 197                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 198 }
 199
 200 /* PCI registers */
 201 #define PCI_CFG_RETRY_TIMEOUT   0x041
 202
 203 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 204 {
 205         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 206         u16 lctl;
 207         u16 cap;
 208
 209         /*
 210          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 211          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 212          * If so (likely), disable L0S, so device moves directly L0->L1;
 213          *    costs negligible amount of power savings.
 214          * If not (unlikely), enable L0S, so there is at least some
 215          *    power savings, even without L1.
 216          */
 217         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 218         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 219                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 220         else
 221                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 222         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 223
 224         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 225         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 226         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 227                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 228                  trans->ltr_enabled ? "En" : "Dis");
 229 }
 230
 231 /*
 232  * Start up NIC's basic functionality after it has been reset
 233  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 234  * NOTE:  This does not load uCode nor start the embedded processor
 235  */
 236 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 237 {
 238         int ret = 0;
 239         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 240
 241         /*
 242          * Use "set_bit" below rather than "write", to preserve any hardware
 243          * bits already set by default after reset.
 244          */
 245
 246         /* Disable L0S exit timer (platform NMI Work/Around) */
 247         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 248                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 249                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 250
 251         /*
 252          * Disable L0s without affecting L1;
 253          *  don't wait for ICH L0s (ICH bug W/A)
 254          */
 255         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 256                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 257
 258         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 259         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 260
 261         /*
 262          * Enable HAP INTA (interrupt from management bus) to
 263          * wake device's PCI Express link L1a -> L0s
 264          */
 265         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 266                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 267
 268         iwl_pcie_apm_config(trans);
 269
 270         /* Configure analog phase-lock-loop before activating to D0A */
 271         if (trans->cfg->base_params->pll_cfg_val)
 272                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 273                             trans->cfg->base_params->pll_cfg_val);
 274
 275         /*
 276          * Set "initialization complete" bit to move adapter from
 277          * D0U* --> D0A* (powered-up active) state.
 278          */
 279         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 280
 281         /*
 282          * Wait for clock stabilization; once stabilized, access to
 283          * device-internal resources is supported, e.g. iwl_write_prph()
 284          * and accesses to uCode SRAM.
 285          */
 286         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 287                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 288                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 289         if (ret < 0) {
 290                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 291                 goto out;
 292         }
 293
 294         if (trans->cfg->host_interrupt_operation_mode) {
 295                 /*
 296                  * This is a bit of an abuse - This is needed for 7260 / 3160
 297                  * only check host_interrupt_operation_mode even if this is
 298                  * not related to host_interrupt_operation_mode.
 299                  *
 300                  * Enable the oscillator to count wake up time for L1 exit. This
 301                  * consumes slightly more power (100uA) - but allows to be sure
 302                  * that we wake up from L1 on time.
 303                  *
 304                  * This looks weird: read twice the same register, discard the
 305                  * value, set a bit, and yet again, read that same register
 306                  * just to discard the value. But that's the way the hardware
 307                  * seems to like it.
 308                  */
 309                 iwl_read_prph(trans, OSC_CLK);
 310                 iwl_read_prph(trans, OSC_CLK);
 311                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 312                 iwl_read_prph(trans, OSC_CLK);
 313                 iwl_read_prph(trans, OSC_CLK);
 314         }
 315
 316         /*
 317          * Enable DMA clock and wait for it to stabilize.
 318          *
 319          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 320          * bits do not disable clocks.  This preserves any hardware
 321          * bits already set by default in "CLK_CTRL_REG" after reset.
 322          */
 323         if (!trans->cfg->apmg_not_supported) {
 324                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 325                                APMG_CLK_VAL_DMA_CLK_RQT);
 326                 udelay(20);
 327
 328                 /* Disable L1-Active */
 329                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 330                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 331
 332                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 333                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 334                                APMG_RTC_INT_STT_RFKILL);
 335         }
 336
 337         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 338
 339 out:
 340         return ret;
 341 }
 342
 343 /*
 344  * Enable LP XTAL to avoid HW bug where device may consume much power if
 345  * FW is not loaded after device reset. LP XTAL is disabled by default
 346  * after device HW reset. Do it only if XTAL is fed by internal source.
 347  * Configure device's "persistence" mode to avoid resetting XTAL again when
 348  * SHRD_HW_RST occurs in S3.
 349  */
 350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 351 {
 352         int ret;
 353         u32 apmg_gp1_reg;
 354         u32 apmg_xtal_cfg_reg;
 355         u32 dl_cfg_reg;
 356
 357         /* Force XTAL ON */
 358         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 359                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 360
 361         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 362         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 363
 364         udelay(10);
 365
 366         /*
 367          * Set "initialization complete" bit to move adapter from
 368          * D0U* --> D0A* (powered-up active) state.
 369          */
 370         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 371
 372         /*
 373          * Wait for clock stabilization; once stabilized, access to
 374          * device-internal resources is possible.
 375          */
 376         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 377                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 378                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 379                            25000);
 380         if (WARN_ON(ret < 0)) {
 381                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 382                 /* Release XTAL ON request */
 383                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 384                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 385                 return;
 386         }
 387
 388         /*
 389          * Clear "disable persistence" to avoid LP XTAL resetting when
 390          * SHRD_HW_RST is applied in S3.
 391          */
 392         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 393                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 394
 395         /*
 396          * Force APMG XTAL to be active to prevent its disabling by HW
 397          * caused by APMG idle state.
 398          */
 399         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 400                                                     SHR_APMG_XTAL_CFG_REG);
 401         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 402                                  apmg_xtal_cfg_reg |
 403                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 404
 405         /*
 406          * Reset entire device again - do controller reset (results in
 407          * SHRD_HW_RST). Turn MAC off before proceeding.
 408          */
 409         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 410
 411         udelay(10);
 412
 413         /* Enable LP XTAL by indirect access through CSR */
 414         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 415         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 416                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 417                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 418
 419         /* Clear delay line clock power up */
 420         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 421         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 422                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 423
 424         /*
 425          * Enable persistence mode to avoid LP XTAL resetting when
 426          * SHRD_HW_RST is applied in S3.
 427          */
 428         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 429                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 430
 431         /*
 432          * Clear "initialization complete" bit to move adapter from
 433          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 434          */
 435         iwl_clear_bit(trans, CSR_GP_CNTRL,
 436                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 437
 438         /* Activates XTAL resources monitor */
 439         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 440                                  CSR_MONITOR_XTAL_RESOURCES);
 441
 442         /* Release XTAL ON request */
 443         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 444                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 445         udelay(10);
 446
 447         /* Release APMG XTAL */
 448         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 449                                  apmg_xtal_cfg_reg &
 450                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 451 }
 452
 453 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 454 {
 455         int ret = 0;
 456
 457         /* stop device's busmaster DMA activity */
 458         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 459
 460         ret = iwl_poll_bit(trans, CSR_RESET,
 461                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 462                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 463         if (ret < 0)
 464                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 465
 466         IWL_DEBUG_INFO(trans, "stop master\n");
 467
 468         return ret;
 469 }
 470
 471 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 472 {
 473         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 474
 475         if (op_mode_leave) {
 476                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 477                         iwl_pcie_apm_init(trans);
 478
 479                 /* inform ME that we are leaving */
 480                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 481                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 482                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 483                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
 484                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 485                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 486                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 487                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 488                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 489                         mdelay(1);
 490                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 491                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 492                 }
 493                 mdelay(5);
 494         }
 495
 496         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 497
 498         /* Stop device's DMA activity */
 499         iwl_pcie_apm_stop_master(trans);
 500
 501         if (trans->cfg->lp_xtal_workaround) {
 502                 iwl_pcie_apm_lp_xtal_enable(trans);
 503                 return;
 504         }
 505
 506         /* Reset the entire device */
 507         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 508
 509         udelay(10);
 510
 511         /*
 512          * Clear "initialization complete" bit to move adapter from
 513          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 514          */
 515         iwl_clear_bit(trans, CSR_GP_CNTRL,
 516                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 517 }
 518
 519 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 520 {
 521         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 522
 523         /* nic_init */
 524         spin_lock(&trans_pcie->irq_lock);
 525         iwl_pcie_apm_init(trans);
 526
 527         spin_unlock(&trans_pcie->irq_lock);
 528
 529         iwl_pcie_set_pwr(trans, false);
 530
 531         iwl_op_mode_nic_config(trans->op_mode);
 532
 533         /* Allocate the RX queue, or reset if it is already allocated */
 534         iwl_pcie_rx_init(trans);
 535
 536         /* Allocate or reset and init all Tx and Command queues */
 537         if (iwl_pcie_tx_init(trans))
 538                 return -ENOMEM;
 539
 540         if (trans->cfg->base_params->shadow_reg_enable) {
 541                 /* enable shadow regs in HW */
 542                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 543                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 544         }
 545
 546         return 0;
 547 }
 548
 549 #define HW_READY_TIMEOUT (50)
 550
 551 /* Note: returns poll_bit return value, which is >= 0 if success */
 552 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 553 {
 554         int ret;
 555
 556         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 557                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 558
 559         /* See if we got it */
 560         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 561                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 562                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 563                            HW_READY_TIMEOUT);
 564
 565         if (ret >= 0)
 566                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 567
 568         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 569         return ret;
 570 }
 571
 572 /* Note: returns standard 0/-ERROR code */
 573 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 574 {
 575         int ret;
 576         int t = 0;
 577         int iter;
 578
 579         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 580
 581         ret = iwl_pcie_set_hw_ready(trans);
 582         /* If the card is ready, exit 0 */
 583         if (ret >= 0)
 584                 return 0;
 585
 586         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 587                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 588         msleep(1);
 589
 590         for (iter = 0; iter < 10; iter++) {
 591                 /* If HW is not ready, prepare the conditions to check again */
 592                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 593                             CSR_HW_IF_CONFIG_REG_PREPARE);
 594
 595                 do {
 596                         ret = iwl_pcie_set_hw_ready(trans);
 597                         if (ret >= 0)
 598                                 return 0;
 599
 600                         usleep_range(200, 1000);
 601                         t += 200;
 602                 } while (t < 150000);
 603                 msleep(25);
 604         }
 605
 606         IWL_ERR(trans, "Couldn't prepare the card\n");
 607
 608         return ret;
 609 }
 610
 611 /*
 612  * ucode
 613  */
 614 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 615                                    dma_addr_t phy_addr, u32 byte_cnt)
 616 {
 617         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 618         int ret;
 619
 620         trans_pcie->ucode_write_complete = false;
 621
 622         iwl_write_direct32(trans,
 623                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 624                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 625
 626         iwl_write_direct32(trans,
 627                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 628                            dst_addr);
 629
 630         iwl_write_direct32(trans,
 631                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 632                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 633
 634         iwl_write_direct32(trans,
 635                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 636                            (iwl_get_dma_hi_addr(phy_addr)
 637                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 638
 639         iwl_write_direct32(trans,
 640                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 641                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 642                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 643                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 644
 645         iwl_write_direct32(trans,
 646                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 647                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 648                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 649                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 650
 651         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 652                                  trans_pcie->ucode_write_complete, 5 * HZ);
 653         if (!ret) {
 654                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 655                 return -ETIMEDOUT;
 656         }
 657
 658         return 0;
 659 }
 660
 661 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 662                             const struct fw_desc *section)
 663 {
 664         u8 *v_addr;
 665         dma_addr_t p_addr;
 666         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 667         int ret = 0;
 668
 669         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 670                      section_num);
 671
 672         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 673                                     GFP_KERNEL | __GFP_NOWARN);
 674         if (!v_addr) {
 675                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 676                 chunk_sz = PAGE_SIZE;
 677                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 678                                             &p_addr, GFP_KERNEL);
 679                 if (!v_addr)
 680                         return -ENOMEM;
 681         }
 682
 683         for (offset = 0; offset < section->len; offset += chunk_sz) {
 684                 u32 copy_size, dst_addr;
 685                 bool extended_addr = false;
 686
 687                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 688                 dst_addr = section->offset + offset;
 689
 690                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 691                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 692                         extended_addr = true;
 693
 694                 if (extended_addr)
 695                         iwl_set_bits_prph(trans, LMPM_CHICK,
 696                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 697
 698                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 699                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 700                                                    copy_size);
 701
 702                 if (extended_addr)
 703                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 704                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 705
 706                 if (ret) {
 707                         IWL_ERR(trans,
 708                                 "Could not load the [%d] uCode section\n",
 709                                 section_num);
 710                         break;
 711                 }
 712         }
 713
 714         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 715         return ret;
 716 }
 717
 718 /*
 719  * Driver Takes the ownership on secure machine before FW load
 720  * and prevent race with the BT load.
 721  * W/A for ROM bug. (should be remove in the next Si step)
 722  */
 723 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
 724 {
 725         u32 val, loop = 1000;
 726
 727         /*
 728          * Check the RSA semaphore is accessible.
 729          * If the HW isn't locked and the rsa semaphore isn't accessible,
 730          * we are in trouble.
 731          */
 732         val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
 733         if (val & (BIT(1) | BIT(17))) {
 734                 IWL_INFO(trans,
 735                          "can't access the RSA semaphore it is write protected\n");
 736                 return 0;
 737         }
 738
 739         /* take ownership on the AUX IF */
 740         iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
 741         iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
 742
 743         do {
 744                 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
 745                 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
 746                 if (val == 0x1) {
 747                         iwl_write_prph(trans, RSA_ENABLE, 0);
 748                         return 0;
 749                 }
 750
 751                 udelay(10);
 752                 loop--;
 753         } while (loop > 0);
 754
 755         IWL_ERR(trans, "Failed to take ownership on secure machine\n");
 756         return -EIO;
 757 }
 758
 759 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 760                                            const struct fw_img *image,
 761                                            int cpu,
 762                                            int *first_ucode_section)
 763 {
 764         int shift_param;
 765         int i, ret = 0, sec_num = 0x1;
 766         u32 val, last_read_idx = 0;
 767
 768         if (cpu == 1) {
 769                 shift_param = 0;
 770                 *first_ucode_section = 0;
 771         } else {
 772                 shift_param = 16;
 773                 (*first_ucode_section)++;
 774         }
 775
 776         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 777                 last_read_idx = i;
 778
 779                 /*
 780                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 781                  * CPU1 to CPU2.
 782                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 783                  * CPU2 non paged to CPU2 paging sec.
 784                  */
 785                 if (!image->sec[i].data ||
 786                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 787                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 788                         IWL_DEBUG_FW(trans,
 789                                      "Break since Data not valid or Empty section, sec = %d\n",
 790                                      i);
 791                         break;
 792                 }
 793
 794                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 795                 if (ret)
 796                         return ret;
 797
 798                 /* Notify the ucode of the loaded section number and status */
 799                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 800                 val = val | (sec_num << shift_param);
 801                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 802                 sec_num = (sec_num << 1) | 0x1;
 803         }
 804
 805         *first_ucode_section = last_read_idx;
 806
 807         if (cpu == 1)
 808                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
 809         else
 810                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 811
 812         return 0;
 813 }
 814
 815 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 816                                       const struct fw_img *image,
 817                                       int cpu,
 818                                       int *first_ucode_section)
 819 {
 820         int shift_param;
 821         int i, ret = 0;
 822         u32 last_read_idx = 0;
 823
 824         if (cpu == 1) {
 825                 shift_param = 0;
 826                 *first_ucode_section = 0;
 827         } else {
 828                 shift_param = 16;
 829                 (*first_ucode_section)++;
 830         }
 831
 832         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 833                 last_read_idx = i;
 834
 835                 /*
 836                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 837                  * CPU1 to CPU2.
 838                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 839                  * CPU2 non paged to CPU2 paging sec.
 840                  */
 841                 if (!image->sec[i].data ||
 842                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 843                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 844                         IWL_DEBUG_FW(trans,
 845                                      "Break since Data not valid or Empty section, sec = %d\n",
 846                                      i);
 847                         break;
 848                 }
 849
 850                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 851                 if (ret)
 852                         return ret;
 853         }
 854
 855         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 856                 iwl_set_bits_prph(trans,
 857                                   CSR_UCODE_LOAD_STATUS_ADDR,
 858                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 859                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 860                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 861                                         shift_param);
 862
 863         *first_ucode_section = last_read_idx;
 864
 865         return 0;
 866 }
 867
 868 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 869 {
 870         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 871         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 872         int i;
 873
 874         if (dest->version)
 875                 IWL_ERR(trans,
 876                         "DBG DEST version is %d - expect issues\n",
 877                         dest->version);
 878
 879         IWL_INFO(trans, "Applying debug destination %s\n",
 880                  get_fw_dbg_mode_string(dest->monitor_mode));
 881
 882         if (dest->monitor_mode == EXTERNAL_MODE)
 883                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 884         else
 885                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 886
 887         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 888                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 889                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 890
 891                 switch (dest->reg_ops[i].op) {
 892                 case CSR_ASSIGN:
 893                         iwl_write32(trans, addr, val);
 894                         break;
 895                 case CSR_SETBIT:
 896                         iwl_set_bit(trans, addr, BIT(val));
 897                         break;
 898                 case CSR_CLEARBIT:
 899                         iwl_clear_bit(trans, addr, BIT(val));
 900                         break;
 901                 case PRPH_ASSIGN:
 902                         iwl_write_prph(trans, addr, val);
 903                         break;
 904                 case PRPH_SETBIT:
 905                         iwl_set_bits_prph(trans, addr, BIT(val));
 906                         break;
 907                 case PRPH_CLEARBIT:
 908                         iwl_clear_bits_prph(trans, addr, BIT(val));
 909                         break;
 910                 case PRPH_BLOCKBIT:
 911                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 912                                 IWL_ERR(trans,
 913                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 914                                         val, addr);
 915                                 goto monitor;
 916                         }
 917                         break;
 918                 default:
 919                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 920                                 dest->reg_ops[i].op);
 921                         break;
 922                 }
 923         }
 924
 925 monitor:
 926         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 927                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 928                                trans_pcie->fw_mon_phys >> dest->base_shift);
 929                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 930                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 931                                        (trans_pcie->fw_mon_phys +
 932                                         trans_pcie->fw_mon_size - 256) >>
 933                                                 dest->end_shift);
 934                 else
 935                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 936                                        (trans_pcie->fw_mon_phys +
 937                                         trans_pcie->fw_mon_size) >>
 938                                                 dest->end_shift);
 939         }
 940 }
 941
 942 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 943                                 const struct fw_img *image)
 944 {
 945         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 946         int ret = 0;
 947         int first_ucode_section;
 948
 949         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 950                      image->is_dual_cpus ? "Dual" : "Single");
 951
 952         /* load to FW the binary non secured sections of CPU1 */
 953         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 954         if (ret)
 955                 return ret;
 956
 957         if (image->is_dual_cpus) {
 958                 /* set CPU2 header address */
 959                 iwl_write_prph(trans,
 960                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 961                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 962
 963                 /* load to FW the binary sections of CPU2 */
 964                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 965                                                  &first_ucode_section);
 966                 if (ret)
 967                         return ret;
 968         }
 969
 970         /* supported for 7000 only for the moment */
 971         if (iwlwifi_mod_params.fw_monitor &&
 972             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 973                 iwl_pcie_alloc_fw_monitor(trans, 0);
 974
 975                 if (trans_pcie->fw_mon_size) {
 976                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 977                                        trans_pcie->fw_mon_phys >> 4);
 978                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 979                                        (trans_pcie->fw_mon_phys +
 980                                         trans_pcie->fw_mon_size) >> 4);
 981                 }
 982         } else if (trans->dbg_dest_tlv) {
 983                 iwl_pcie_apply_destination(trans);
 984         }
 985
 986         /* release CPU reset */
 987         iwl_write32(trans, CSR_RESET, 0);
 988
 989         return 0;
 990 }
 991
 992 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
 993                                           const struct fw_img *image)
 994 {
 995         int ret = 0;
 996         int first_ucode_section;
 997
 998         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 999                      image->is_dual_cpus ? "Dual" : "Single");
1000
1001         if (trans->dbg_dest_tlv)
1002                 iwl_pcie_apply_destination(trans);
1003
1004         /* TODO: remove in the next Si step */
1005         ret = iwl_pcie_rsa_race_bug_wa(trans);
1006         if (ret)
1007                 return ret;
1008
1009         /* configure the ucode to be ready to get the secured image */
1010         /* release CPU reset */
1011         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1012
1013         /* load to FW the binary Secured sections of CPU1 */
1014         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1015                                               &first_ucode_section);
1016         if (ret)
1017                 return ret;
1018
1019         /* load to FW the binary sections of CPU2 */
1020         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1021                                                &first_ucode_section);
1022 }
1023
1024 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1025                                    const struct fw_img *fw, bool run_in_rfkill)
1026 {
1027         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1028         bool hw_rfkill;
1029         int ret;
1030
1031         mutex_lock(&trans_pcie->mutex);
1032
1033         /* Someone called stop_device, don't try to start_fw */
1034         if (trans_pcie->is_down) {
1035                 IWL_WARN(trans,
1036                          "Can't start_fw since the HW hasn't been started\n");
1037                 ret = EIO;
1038                 goto out;
1039         }
1040
1041         /* This may fail if AMT took ownership of the device */
1042         if (iwl_pcie_prepare_card_hw(trans)) {
1043                 IWL_WARN(trans, "Exit HW not ready\n");
1044                 ret = -EIO;
1045                 goto out;
1046         }
1047
1048         iwl_enable_rfkill_int(trans);
1049
1050         /* If platform's RF_KILL switch is NOT set to KILL */
1051         hw_rfkill = iwl_is_rfkill_set(trans);
1052         if (hw_rfkill)
1053                 set_bit(STATUS_RFKILL, &trans->status);
1054         else
1055                 clear_bit(STATUS_RFKILL, &trans->status);
1056         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1057         if (hw_rfkill && !run_in_rfkill) {
1058                 ret = -ERFKILL;
1059                 goto out;
1060         }
1061
1062         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1063
1064         ret = iwl_pcie_nic_init(trans);
1065         if (ret) {
1066                 IWL_ERR(trans, "Unable to init nic\n");
1067                 goto out;
1068         }
1069
1070         /* make sure rfkill handshake bits are cleared */
1071         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1072         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1073                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1074
1075         /* clear (again), then enable host interrupts */
1076         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1077         iwl_enable_interrupts(trans);
1078
1079         /* really make sure rfkill handshake bits are cleared */
1080         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1081         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1082
1083         /* Load the given image to the HW */
1084         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1085                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1086         else
1087                 ret = iwl_pcie_load_given_ucode(trans, fw);
1088
1089 out:
1090         mutex_unlock(&trans_pcie->mutex);
1091         return ret;
1092 }
1093
1094 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1095 {
1096         iwl_pcie_reset_ict(trans);
1097         iwl_pcie_tx_start(trans, scd_addr);
1098 }
1099
1100 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1101 {
1102         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1103         bool hw_rfkill, was_hw_rfkill;
1104
1105         lockdep_assert_held(&trans_pcie->mutex);
1106
1107         if (trans_pcie->is_down)
1108                 return;
1109
1110         trans_pcie->is_down = true;
1111
1112         was_hw_rfkill = iwl_is_rfkill_set(trans);
1113
1114         /* tell the device to stop sending interrupts */
1115         spin_lock(&trans_pcie->irq_lock);
1116         iwl_disable_interrupts(trans);
1117         spin_unlock(&trans_pcie->irq_lock);
1118
1119         /* device going down, Stop using ICT table */
1120         iwl_pcie_disable_ict(trans);
1121
1122         /*
1123          * If a HW restart happens during firmware loading,
1124          * then the firmware loading might call this function
1125          * and later it might be called again due to the
1126          * restart. So don't process again if the device is
1127          * already dead.
1128          */
1129         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1130                 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1131                 iwl_pcie_tx_stop(trans);
1132                 iwl_pcie_rx_stop(trans);
1133
1134                 /* Power-down device's busmaster DMA clocks */
1135                 if (!trans->cfg->apmg_not_supported) {
1136                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1137                                        APMG_CLK_VAL_DMA_CLK_RQT);
1138                         udelay(5);
1139                 }
1140         }
1141
1142         /* Make sure (redundant) we've released our request to stay awake */
1143         iwl_clear_bit(trans, CSR_GP_CNTRL,
1144                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1145
1146         /* Stop the device, and put it in low power state */
1147         iwl_pcie_apm_stop(trans, false);
1148
1149         /* stop and reset the on-board processor */
1150         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1151         udelay(20);
1152
1153         /*
1154          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1155          * This is a bug in certain verions of the hardware.
1156          * Certain devices also keep sending HW RF kill interrupt all
1157          * the time, unless the interrupt is ACKed even if the interrupt
1158          * should be masked. Re-ACK all the interrupts here.
1159          */
1160         spin_lock(&trans_pcie->irq_lock);
1161         iwl_disable_interrupts(trans);
1162         spin_unlock(&trans_pcie->irq_lock);
1163
1164
1165         /* clear all status bits */
1166         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1167         clear_bit(STATUS_INT_ENABLED, &trans->status);
1168         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1169         clear_bit(STATUS_RFKILL, &trans->status);
1170
1171         /*
1172          * Even if we stop the HW, we still want the RF kill
1173          * interrupt
1174          */
1175         iwl_enable_rfkill_int(trans);
1176
1177         /*
1178          * Check again since the RF kill state may have changed while
1179          * all the interrupts were disabled, in this case we couldn't
1180          * receive the RF kill interrupt and update the state in the
1181          * op_mode.
1182          * Don't call the op_mode if the rkfill state hasn't changed.
1183          * This allows the op_mode to call stop_device from the rfkill
1184          * notification without endless recursion. Under very rare
1185          * circumstances, we might have a small recursion if the rfkill
1186          * state changed exactly now while we were called from stop_device.
1187          * This is very unlikely but can happen and is supported.
1188          */
1189         hw_rfkill = iwl_is_rfkill_set(trans);
1190         if (hw_rfkill)
1191                 set_bit(STATUS_RFKILL, &trans->status);
1192         else
1193                 clear_bit(STATUS_RFKILL, &trans->status);
1194         if (hw_rfkill != was_hw_rfkill)
1195                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1196
1197         /* re-take ownership to prevent other users from stealing the deivce */
1198         iwl_pcie_prepare_card_hw(trans);
1199 }
1200
1201 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1202 {
1203         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1204
1205         mutex_lock(&trans_pcie->mutex);
1206         _iwl_trans_pcie_stop_device(trans, low_power);
1207         mutex_unlock(&trans_pcie->mutex);
1208 }
1209
1210 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1211 {
1212         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1213                 IWL_TRANS_GET_PCIE_TRANS(trans);
1214
1215         lockdep_assert_held(&trans_pcie->mutex);
1216
1217         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1218                 _iwl_trans_pcie_stop_device(trans, true);
1219 }
1220
1221 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1222 {
1223         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1224
1225         if (trans->wowlan_d0i3) {
1226                 /* Enable persistence mode to avoid reset */
1227                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1228                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1229         }
1230
1231         iwl_disable_interrupts(trans);
1232
1233         /*
1234          * in testing mode, the host stays awake and the
1235          * hardware won't be reset (not even partially)
1236          */
1237         if (test)
1238                 return;
1239
1240         iwl_pcie_disable_ict(trans);
1241
1242         synchronize_irq(trans_pcie->pci_dev->irq);
1243
1244         iwl_clear_bit(trans, CSR_GP_CNTRL,
1245                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1246         iwl_clear_bit(trans, CSR_GP_CNTRL,
1247                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1248
1249         if (!trans->wowlan_d0i3) {
1250                 /*
1251                  * reset TX queues -- some of their registers reset during S3
1252                  * so if we don't reset everything here the D3 image would try
1253                  * to execute some invalid memory upon resume
1254                  */
1255                 iwl_trans_pcie_tx_reset(trans);
1256         }
1257
1258         iwl_pcie_set_pwr(trans, true);
1259 }
1260
1261 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1262                                     enum iwl_d3_status *status,
1263                                     bool test)
1264 {
1265         u32 val;
1266         int ret;
1267
1268         if (test) {
1269                 iwl_enable_interrupts(trans);
1270                 *status = IWL_D3_STATUS_ALIVE;
1271                 return 0;
1272         }
1273
1274         /*
1275          * Also enables interrupts - none will happen as the device doesn't
1276          * know we're waking it up, only when the opmode actually tells it
1277          * after this call.
1278          */
1279         iwl_pcie_reset_ict(trans);
1280
1281         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1282         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1283
1284         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1285                 udelay(2);
1286
1287         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1288                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1289                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1290                            25000);
1291         if (ret < 0) {
1292                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1293                 return ret;
1294         }
1295
1296         iwl_pcie_set_pwr(trans, false);
1297
1298         if (trans->wowlan_d0i3) {
1299                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1300                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1301         } else {
1302                 iwl_trans_pcie_tx_reset(trans);
1303
1304                 ret = iwl_pcie_rx_init(trans);
1305                 if (ret) {
1306                         IWL_ERR(trans,
1307                                 "Failed to resume the device (RX reset)\n");
1308                         return ret;
1309                 }
1310         }
1311
1312         val = iwl_read32(trans, CSR_RESET);
1313         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1314                 *status = IWL_D3_STATUS_RESET;
1315         else
1316                 *status = IWL_D3_STATUS_ALIVE;
1317
1318         return 0;
1319 }
1320
1321 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1322 {
1323         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1324         bool hw_rfkill;
1325         int err;
1326
1327         lockdep_assert_held(&trans_pcie->mutex);
1328
1329         err = iwl_pcie_prepare_card_hw(trans);
1330         if (err) {
1331                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1332                 return err;
1333         }
1334
1335         /* Reset the entire device */
1336         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1337
1338         usleep_range(10, 15);
1339
1340         iwl_pcie_apm_init(trans);
1341
1342         /* From now on, the op_mode will be kept updated about RF kill state */
1343         iwl_enable_rfkill_int(trans);
1344
1345         /* Set is_down to false here so that...*/
1346         trans_pcie->is_down = false;
1347
1348         hw_rfkill = iwl_is_rfkill_set(trans);
1349         if (hw_rfkill)
1350                 set_bit(STATUS_RFKILL, &trans->status);
1351         else
1352                 clear_bit(STATUS_RFKILL, &trans->status);
1353         /* ... rfkill can call stop_device and set it false if needed */
1354         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1355
1356         return 0;
1357 }
1358
1359 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1360 {
1361         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1362         int ret;
1363
1364         mutex_lock(&trans_pcie->mutex);
1365         ret = _iwl_trans_pcie_start_hw(trans, low_power);
1366         mutex_unlock(&trans_pcie->mutex);
1367
1368         return ret;
1369 }
1370
1371 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1372 {
1373         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1374
1375         mutex_lock(&trans_pcie->mutex);
1376
1377         /* disable interrupts - don't enable HW RF kill interrupt */
1378         spin_lock(&trans_pcie->irq_lock);
1379         iwl_disable_interrupts(trans);
1380         spin_unlock(&trans_pcie->irq_lock);
1381
1382         iwl_pcie_apm_stop(trans, true);
1383
1384         spin_lock(&trans_pcie->irq_lock);
1385         iwl_disable_interrupts(trans);
1386         spin_unlock(&trans_pcie->irq_lock);
1387
1388         iwl_pcie_disable_ict(trans);
1389
1390         mutex_unlock(&trans_pcie->mutex);
1391
1392         synchronize_irq(trans_pcie->pci_dev->irq);
1393 }
1394
1395 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1396 {
1397         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1398 }
1399
1400 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1401 {
1402         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1403 }
1404
1405 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1406 {
1407         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1408 }
1409
1410 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1411 {
1412         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1413                                ((reg & 0x000FFFFF) | (3 << 24)));
1414         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1415 }
1416
1417 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1418                                       u32 val)
1419 {
1420         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1421                                ((addr & 0x000FFFFF) | (3 << 24)));
1422         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1423 }
1424
1425 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1426 {
1427         WARN_ON(1);
1428         return 0;
1429 }
1430
1431 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1432                                      const struct iwl_trans_config *trans_cfg)
1433 {
1434         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1435
1436         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1437         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1438         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1439         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1440                 trans_pcie->n_no_reclaim_cmds = 0;
1441         else
1442                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1443         if (trans_pcie->n_no_reclaim_cmds)
1444                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1445                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1446
1447         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1448         if (trans_pcie->rx_buf_size_8k)
1449                 trans_pcie->rx_page_order = get_order(8 * 1024);
1450         else
1451                 trans_pcie->rx_page_order = get_order(4 * 1024);
1452
1453         trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
1454         trans_pcie->command_names = trans_cfg->command_names;
1455         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1456         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1457
1458         /* init ref_count to 1 (should be cleared when ucode is loaded) */
1459         trans_pcie->ref_count = 1;
1460
1461         /* Initialize NAPI here - it should be before registering to mac80211
1462          * in the opmode but after the HW struct is allocated.
1463          * As this function may be called again in some corner cases don't
1464          * do anything if NAPI was already initialized.
1465          */
1466         if (!trans_pcie->napi.poll) {
1467                 init_dummy_netdev(&trans_pcie->napi_dev);
1468                 netif_napi_add(&trans_pcie->napi_dev, &trans_pcie->napi,
1469                                iwl_pcie_dummy_napi_poll, 64);
1470         }
1471 }
1472
1473 void iwl_trans_pcie_free(struct iwl_trans *trans)
1474 {
1475         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1476
1477         synchronize_irq(trans_pcie->pci_dev->irq);
1478
1479         iwl_pcie_tx_free(trans);
1480         iwl_pcie_rx_free(trans);
1481
1482         free_irq(trans_pcie->pci_dev->irq, trans);
1483         iwl_pcie_free_ict(trans);
1484
1485         pci_disable_msi(trans_pcie->pci_dev);
1486         iounmap(trans_pcie->hw_base);
1487         pci_release_regions(trans_pcie->pci_dev);
1488         pci_disable_device(trans_pcie->pci_dev);
1489
1490         if (trans_pcie->napi.poll)
1491                 netif_napi_del(&trans_pcie->napi);
1492
1493         iwl_pcie_free_fw_monitor(trans);
1494
1495         iwl_trans_free(trans);
1496 }
1497
1498 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1499 {
1500         if (state)
1501                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1502         else
1503                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1504 }
1505
1506 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1507                                                 unsigned long *flags)
1508 {
1509         int ret;
1510         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1511
1512         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1513
1514         if (trans_pcie->cmd_hold_nic_awake)
1515                 goto out;
1516
1517         /* this bit wakes up the NIC */
1518         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1519                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1520         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1521                 udelay(2);
1522
1523         /*
1524          * These bits say the device is running, and should keep running for
1525          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1526          * but they do not indicate that embedded SRAM is restored yet;
1527          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1528          * to/from host DRAM when sleeping/waking for power-saving.
1529          * Each direction takes approximately 1/4 millisecond; with this
1530          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1531          * series of register accesses are expected (e.g. reading Event Log),
1532          * to keep device from sleeping.
1533          *
1534          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1535          * SRAM is okay/restored.  We don't check that here because this call
1536          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1537          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1538          *
1539          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1540          * and do not save/restore SRAM when power cycling.
1541          */
1542         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1543                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1544                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1545                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1546         if (unlikely(ret < 0)) {
1547                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1548                 if (!silent) {
1549                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1550                         WARN_ONCE(1,
1551                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1552                                   val);
1553                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1554                         return false;
1555                 }
1556         }
1557
1558 out:
1559         /*
1560          * Fool sparse by faking we release the lock - sparse will
1561          * track nic_access anyway.
1562          */
1563         __release(&trans_pcie->reg_lock);
1564         return true;
1565 }
1566
1567 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1568                                               unsigned long *flags)
1569 {
1570         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1571
1572         lockdep_assert_held(&trans_pcie->reg_lock);
1573
1574         /*
1575          * Fool sparse by faking we acquiring the lock - sparse will
1576          * track nic_access anyway.
1577          */
1578         __acquire(&trans_pcie->reg_lock);
1579
1580         if (trans_pcie->cmd_hold_nic_awake)
1581                 goto out;
1582
1583         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1584                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1585         /*
1586          * Above we read the CSR_GP_CNTRL register, which will flush
1587          * any previous writes, but we need the write that clears the
1588          * MAC_ACCESS_REQ bit to be performed before any other writes
1589          * scheduled on different CPUs (after we drop reg_lock).
1590          */
1591         mmiowb();
1592 out:
1593         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1594 }
1595
1596 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1597                                    void *buf, int dwords)
1598 {
1599         unsigned long flags;
1600         int offs, ret = 0;
1601         u32 *vals = buf;
1602
1603         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1604                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1605                 for (offs = 0; offs < dwords; offs++)
1606                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1607                 iwl_trans_release_nic_access(trans, &flags);
1608         } else {
1609                 ret = -EBUSY;
1610         }
1611         return ret;
1612 }
1613
1614 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1615                                     const void *buf, int dwords)
1616 {
1617         unsigned long flags;
1618         int offs, ret = 0;
1619         const u32 *vals = buf;
1620
1621         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1622                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1623                 for (offs = 0; offs < dwords; offs++)
1624                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1625                                     vals ? vals[offs] : 0);
1626                 iwl_trans_release_nic_access(trans, &flags);
1627         } else {
1628                 ret = -EBUSY;
1629         }
1630         return ret;
1631 }
1632
1633 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1634                                             unsigned long txqs,
1635                                             bool freeze)
1636 {
1637         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1638         int queue;
1639
1640         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1641                 struct iwl_txq *txq = &trans_pcie->txq[queue];
1642                 unsigned long now;
1643
1644                 spin_lock_bh(&txq->lock);
1645
1646                 now = jiffies;
1647
1648                 if (txq->frozen == freeze)
1649                         goto next_queue;
1650
1651                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1652                                     freeze ? "Freezing" : "Waking", queue);
1653
1654                 txq->frozen = freeze;
1655
1656                 if (txq->q.read_ptr == txq->q.write_ptr)
1657                         goto next_queue;
1658
1659                 if (freeze) {
1660                         if (unlikely(time_after(now,
1661                                                 txq->stuck_timer.expires))) {
1662                                 /*
1663                                  * The timer should have fired, maybe it is
1664                                  * spinning right now on the lock.
1665                                  */
1666                                 goto next_queue;
1667                         }
1668                         /* remember how long until the timer fires */
1669                         txq->frozen_expiry_remainder =
1670                                 txq->stuck_timer.expires - now;
1671                         del_timer(&txq->stuck_timer);
1672                         goto next_queue;
1673                 }
1674
1675                 /*
1676                  * Wake a non-empty queue -> arm timer with the
1677                  * remainder before it froze
1678                  */
1679                 mod_timer(&txq->stuck_timer,
1680                           now + txq->frozen_expiry_remainder);
1681
1682 next_queue:
1683                 spin_unlock_bh(&txq->lock);
1684         }
1685 }
1686
1687 #define IWL_FLUSH_WAIT_MS       2000
1688
1689 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1690 {
1691         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1692         struct iwl_txq *txq;
1693         struct iwl_queue *q;
1694         int cnt;
1695         unsigned long now = jiffies;
1696         u32 scd_sram_addr;
1697         u8 buf[16];
1698         int ret = 0;
1699
1700         /* waiting for all the tx frames complete might take a while */
1701         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1702                 u8 wr_ptr;
1703
1704                 if (cnt == trans_pcie->cmd_queue)
1705                         continue;
1706                 if (!test_bit(cnt, trans_pcie->queue_used))
1707                         continue;
1708                 if (!(BIT(cnt) & txq_bm))
1709                         continue;
1710
1711                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1712                 txq = &trans_pcie->txq[cnt];
1713                 q = &txq->q;
1714                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1715
1716                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1717                        !time_after(jiffies,
1718                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1719                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1720
1721                         if (WARN_ONCE(wr_ptr != write_ptr,
1722                                       "WR pointer moved while flushing %d -> %d\n",
1723                                       wr_ptr, write_ptr))
1724                                 return -ETIMEDOUT;
1725                         msleep(1);
1726                 }
1727
1728                 if (q->read_ptr != q->write_ptr) {
1729                         IWL_ERR(trans,
1730                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1731                         ret = -ETIMEDOUT;
1732                         break;
1733                 }
1734                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1735         }
1736
1737         if (!ret)
1738                 return 0;
1739
1740         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1741                 txq->q.read_ptr, txq->q.write_ptr);
1742
1743         scd_sram_addr = trans_pcie->scd_base_addr +
1744                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1745         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1746
1747         iwl_print_hex_error(trans, buf, sizeof(buf));
1748
1749         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1750                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1751                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1752
1753         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1754                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1755                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1756                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1757                 u32 tbl_dw =
1758                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1759                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1760
1761                 if (cnt & 0x1)
1762                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1763                 else
1764                         tbl_dw = tbl_dw & 0x0000FFFF;
1765
1766                 IWL_ERR(trans,
1767                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1768                         cnt, active ? "" : "in", fifo, tbl_dw,
1769                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1770                                 (TFD_QUEUE_SIZE_MAX - 1),
1771                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1772         }
1773
1774         return ret;
1775 }
1776
1777 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1778                                          u32 mask, u32 value)
1779 {
1780         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1781         unsigned long flags;
1782
1783         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1784         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1785         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1786 }
1787
1788 void iwl_trans_pcie_ref(struct iwl_trans *trans)
1789 {
1790         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1791         unsigned long flags;
1792
1793         if (iwlwifi_mod_params.d0i3_disable)
1794                 return;
1795
1796         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1797         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1798         trans_pcie->ref_count++;
1799         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1800 }
1801
1802 void iwl_trans_pcie_unref(struct iwl_trans *trans)
1803 {
1804         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1805         unsigned long flags;
1806
1807         if (iwlwifi_mod_params.d0i3_disable)
1808                 return;
1809
1810         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1811         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1812         if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1813                 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1814                 return;
1815         }
1816         trans_pcie->ref_count--;
1817         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1818 }
1819
1820 static const char *get_csr_string(int cmd)
1821 {
1822 #define IWL_CMD(x) case x: return #x
1823         switch (cmd) {
1824         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1825         IWL_CMD(CSR_INT_COALESCING);
1826         IWL_CMD(CSR_INT);
1827         IWL_CMD(CSR_INT_MASK);
1828         IWL_CMD(CSR_FH_INT_STATUS);
1829         IWL_CMD(CSR_GPIO_IN);
1830         IWL_CMD(CSR_RESET);
1831         IWL_CMD(CSR_GP_CNTRL);
1832         IWL_CMD(CSR_HW_REV);
1833         IWL_CMD(CSR_EEPROM_REG);
1834         IWL_CMD(CSR_EEPROM_GP);
1835         IWL_CMD(CSR_OTP_GP_REG);
1836         IWL_CMD(CSR_GIO_REG);
1837         IWL_CMD(CSR_GP_UCODE_REG);
1838         IWL_CMD(CSR_GP_DRIVER_REG);
1839         IWL_CMD(CSR_UCODE_DRV_GP1);
1840         IWL_CMD(CSR_UCODE_DRV_GP2);
1841         IWL_CMD(CSR_LED_REG);
1842         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1843         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1844         IWL_CMD(CSR_ANA_PLL_CFG);
1845         IWL_CMD(CSR_HW_REV_WA_REG);
1846         IWL_CMD(CSR_MONITOR_STATUS_REG);
1847         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1848         default:
1849                 return "UNKNOWN";
1850         }
1851 #undef IWL_CMD
1852 }
1853
1854 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1855 {
1856         int i;
1857         static const u32 csr_tbl[] = {
1858                 CSR_HW_IF_CONFIG_REG,
1859                 CSR_INT_COALESCING,
1860                 CSR_INT,
1861                 CSR_INT_MASK,
1862                 CSR_FH_INT_STATUS,
1863                 CSR_GPIO_IN,
1864                 CSR_RESET,
1865                 CSR_GP_CNTRL,
1866                 CSR_HW_REV,
1867                 CSR_EEPROM_REG,
1868                 CSR_EEPROM_GP,
1869                 CSR_OTP_GP_REG,
1870                 CSR_GIO_REG,
1871                 CSR_GP_UCODE_REG,
1872                 CSR_GP_DRIVER_REG,
1873                 CSR_UCODE_DRV_GP1,
1874                 CSR_UCODE_DRV_GP2,
1875                 CSR_LED_REG,
1876                 CSR_DRAM_INT_TBL_REG,
1877                 CSR_GIO_CHICKEN_BITS,
1878                 CSR_ANA_PLL_CFG,
1879                 CSR_MONITOR_STATUS_REG,
1880                 CSR_HW_REV_WA_REG,
1881                 CSR_DBG_HPET_MEM_REG
1882         };
1883         IWL_ERR(trans, "CSR values:\n");
1884         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1885                 "CSR_INT_PERIODIC_REG)\n");
1886         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1887                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1888                         get_csr_string(csr_tbl[i]),
1889                         iwl_read32(trans, csr_tbl[i]));
1890         }
1891 }
1892
1893 #ifdef CONFIG_IWLWIFI_DEBUGFS
1894 /* create and remove of files */
1895 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1896         if (!debugfs_create_file(#name, mode, parent, trans,            \
1897                                  &iwl_dbgfs_##name##_ops))              \
1898                 goto err;                                               \
1899 } while (0)
1900
1901 /* file operation */
1902 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1903 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1904         .read = iwl_dbgfs_##name##_read,                                \
1905         .open = simple_open,                                            \
1906         .llseek = generic_file_llseek,                                  \
1907 };
1908
1909 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1910 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1911         .write = iwl_dbgfs_##name##_write,                              \
1912         .open = simple_open,                                            \
1913         .llseek = generic_file_llseek,                                  \
1914 };
1915
1916 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1917 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1918         .write = iwl_dbgfs_##name##_write,                              \
1919         .read = iwl_dbgfs_##name##_read,                                \
1920         .open = simple_open,                                            \
1921         .llseek = generic_file_llseek,                                  \
1922 };
1923
1924 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1925                                        char __user *user_buf,
1926                                        size_t count, loff_t *ppos)
1927 {
1928         struct iwl_trans *trans = file->private_data;
1929         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1930         struct iwl_txq *txq;
1931         struct iwl_queue *q;
1932         char *buf;
1933         int pos = 0;
1934         int cnt;
1935         int ret;
1936         size_t bufsz;
1937
1938         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
1939
1940         if (!trans_pcie->txq)
1941                 return -EAGAIN;
1942
1943         buf = kzalloc(bufsz, GFP_KERNEL);
1944         if (!buf)
1945                 return -ENOMEM;
1946
1947         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1948                 txq = &trans_pcie->txq[cnt];
1949                 q = &txq->q;
1950                 pos += scnprintf(buf + pos, bufsz - pos,
1951                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
1952                                 cnt, q->read_ptr, q->write_ptr,
1953                                 !!test_bit(cnt, trans_pcie->queue_used),
1954                                  !!test_bit(cnt, trans_pcie->queue_stopped),
1955                                  txq->need_update, txq->frozen,
1956                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1957         }
1958         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1959         kfree(buf);
1960         return ret;
1961 }
1962
1963 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1964                                        char __user *user_buf,
1965                                        size_t count, loff_t *ppos)
1966 {
1967         struct iwl_trans *trans = file->private_data;
1968         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1969         struct iwl_rxq *rxq = &trans_pcie->rxq;
1970         char buf[256];
1971         int pos = 0;
1972         const size_t bufsz = sizeof(buf);
1973
1974         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1975                                                 rxq->read);
1976         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1977                                                 rxq->write);
1978         pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1979                                                 rxq->write_actual);
1980         pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1981                                                 rxq->need_update);
1982         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1983                                                 rxq->free_count);
1984         if (rxq->rb_stts) {
1985                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1986                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1987         } else {
1988                 pos += scnprintf(buf + pos, bufsz - pos,
1989                                         "closed_rb_num: Not Allocated\n");
1990         }
1991         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1992 }
1993
1994 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1995                                         char __user *user_buf,
1996                                         size_t count, loff_t *ppos)
1997 {
1998         struct iwl_trans *trans = file->private_data;
1999         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2000         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2001
2002         int pos = 0;
2003         char *buf;
2004         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2005         ssize_t ret;
2006
2007         buf = kzalloc(bufsz, GFP_KERNEL);
2008         if (!buf)
2009                 return -ENOMEM;
2010
2011         pos += scnprintf(buf + pos, bufsz - pos,
2012                         "Interrupt Statistics Report:\n");
2013
2014         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2015                 isr_stats->hw);
2016         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2017                 isr_stats->sw);
2018         if (isr_stats->sw || isr_stats->hw) {
2019                 pos += scnprintf(buf + pos, bufsz - pos,
2020                         "\tLast Restarting Code:  0x%X\n",
2021                         isr_stats->err_code);
2022         }
2023 #ifdef CONFIG_IWLWIFI_DEBUG
2024         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2025                 isr_stats->sch);
2026         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2027                 isr_stats->alive);
2028 #endif
2029         pos += scnprintf(buf + pos, bufsz - pos,
2030                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2031
2032         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2033                 isr_stats->ctkill);
2034
2035         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2036                 isr_stats->wakeup);
2037
2038         pos += scnprintf(buf + pos, bufsz - pos,
2039                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2040
2041         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2042                 isr_stats->tx);
2043
2044         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2045                 isr_stats->unhandled);
2046
2047         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2048         kfree(buf);
2049         return ret;
2050 }
2051
2052 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2053                                          const char __user *user_buf,
2054                                          size_t count, loff_t *ppos)
2055 {
2056         struct iwl_trans *trans = file->private_data;
2057         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2058         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2059
2060         char buf[8];
2061         int buf_size;
2062         u32 reset_flag;
2063
2064         memset(buf, 0, sizeof(buf));
2065         buf_size = min(count, sizeof(buf) -  1);
2066         if (copy_from_user(buf, user_buf, buf_size))
2067                 return -EFAULT;
2068         if (sscanf(buf, "%x", &reset_flag) != 1)
2069                 return -EFAULT;
2070         if (reset_flag == 0)
2071                 memset(isr_stats, 0, sizeof(*isr_stats));
2072
2073         return count;
2074 }
2075
2076 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2077                                    const char __user *user_buf,
2078                                    size_t count, loff_t *ppos)
2079 {
2080         struct iwl_trans *trans = file->private_data;
2081         char buf[8];
2082         int buf_size;
2083         int csr;
2084
2085         memset(buf, 0, sizeof(buf));
2086         buf_size = min(count, sizeof(buf) -  1);
2087         if (copy_from_user(buf, user_buf, buf_size))
2088                 return -EFAULT;
2089         if (sscanf(buf, "%d", &csr) != 1)
2090                 return -EFAULT;
2091
2092         iwl_pcie_dump_csr(trans);
2093
2094         return count;
2095 }
2096
2097 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2098                                      char __user *user_buf,
2099                                      size_t count, loff_t *ppos)
2100 {
2101         struct iwl_trans *trans = file->private_data;
2102         char *buf = NULL;
2103         ssize_t ret;
2104
2105         ret = iwl_dump_fh(trans, &buf);
2106         if (ret < 0)
2107                 return ret;
2108         if (!buf)
2109                 return -EINVAL;
2110         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2111         kfree(buf);
2112         return ret;
2113 }
2114
2115 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2116 DEBUGFS_READ_FILE_OPS(fh_reg);
2117 DEBUGFS_READ_FILE_OPS(rx_queue);
2118 DEBUGFS_READ_FILE_OPS(tx_queue);
2119 DEBUGFS_WRITE_FILE_OPS(csr);
2120
2121 /*
2122  * Create the debugfs files and directories
2123  *
2124  */
2125 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2126                                          struct dentry *dir)
2127 {
2128         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2129         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2130         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2131         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2132         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2133         return 0;
2134
2135 err:
2136         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2137         return -ENOMEM;
2138 }
2139 #else
2140 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2141                                          struct dentry *dir)
2142 {
2143         return 0;
2144 }
2145 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2146
2147 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2148 {
2149         u32 cmdlen = 0;
2150         int i;
2151
2152         for (i = 0; i < IWL_NUM_OF_TBS; i++)
2153                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2154
2155         return cmdlen;
2156 }
2157
2158 static const struct {
2159         u32 start, end;
2160 } iwl_prph_dump_addr[] = {
2161         { .start = 0x00a00000, .end = 0x00a00000 },
2162         { .start = 0x00a0000c, .end = 0x00a00024 },
2163         { .start = 0x00a0002c, .end = 0x00a0003c },
2164         { .start = 0x00a00410, .end = 0x00a00418 },
2165         { .start = 0x00a00420, .end = 0x00a00420 },
2166         { .start = 0x00a00428, .end = 0x00a00428 },
2167         { .start = 0x00a00430, .end = 0x00a0043c },
2168         { .start = 0x00a00444, .end = 0x00a00444 },
2169         { .start = 0x00a004c0, .end = 0x00a004cc },
2170         { .start = 0x00a004d8, .end = 0x00a004d8 },
2171         { .start = 0x00a004e0, .end = 0x00a004f0 },
2172         { .start = 0x00a00840, .end = 0x00a00840 },
2173         { .start = 0x00a00850, .end = 0x00a00858 },
2174         { .start = 0x00a01004, .end = 0x00a01008 },
2175         { .start = 0x00a01010, .end = 0x00a01010 },
2176         { .start = 0x00a01018, .end = 0x00a01018 },
2177         { .start = 0x00a01024, .end = 0x00a01024 },
2178         { .start = 0x00a0102c, .end = 0x00a01034 },
2179         { .start = 0x00a0103c, .end = 0x00a01040 },
2180         { .start = 0x00a01048, .end = 0x00a01094 },
2181         { .start = 0x00a01c00, .end = 0x00a01c20 },
2182         { .start = 0x00a01c58, .end = 0x00a01c58 },
2183         { .start = 0x00a01c7c, .end = 0x00a01c7c },
2184         { .start = 0x00a01c28, .end = 0x00a01c54 },
2185         { .start = 0x00a01c5c, .end = 0x00a01c5c },
2186         { .start = 0x00a01c60, .end = 0x00a01cdc },
2187         { .start = 0x00a01ce0, .end = 0x00a01d0c },
2188         { .start = 0x00a01d18, .end = 0x00a01d20 },
2189         { .start = 0x00a01d2c, .end = 0x00a01d30 },
2190         { .start = 0x00a01d40, .end = 0x00a01d5c },
2191         { .start = 0x00a01d80, .end = 0x00a01d80 },
2192         { .start = 0x00a01d98, .end = 0x00a01d9c },
2193         { .start = 0x00a01da8, .end = 0x00a01da8 },
2194         { .start = 0x00a01db8, .end = 0x00a01df4 },
2195         { .start = 0x00a01dc0, .end = 0x00a01dfc },
2196         { .start = 0x00a01e00, .end = 0x00a01e2c },
2197         { .start = 0x00a01e40, .end = 0x00a01e60 },
2198         { .start = 0x00a01e68, .end = 0x00a01e6c },
2199         { .start = 0x00a01e74, .end = 0x00a01e74 },
2200         { .start = 0x00a01e84, .end = 0x00a01e90 },
2201         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
2202         { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2203         { .start = 0x00a01f00, .end = 0x00a01f1c },
2204         { .start = 0x00a01f44, .end = 0x00a01ffc },
2205         { .start = 0x00a02000, .end = 0x00a02048 },
2206         { .start = 0x00a02068, .end = 0x00a020f0 },
2207         { .start = 0x00a02100, .end = 0x00a02118 },
2208         { .start = 0x00a02140, .end = 0x00a0214c },
2209         { .start = 0x00a02168, .end = 0x00a0218c },
2210         { .start = 0x00a021c0, .end = 0x00a021c0 },
2211         { .start = 0x00a02400, .end = 0x00a02410 },
2212         { .start = 0x00a02418, .end = 0x00a02420 },
2213         { .start = 0x00a02428, .end = 0x00a0242c },
2214         { .start = 0x00a02434, .end = 0x00a02434 },
2215         { .start = 0x00a02440, .end = 0x00a02460 },
2216         { .start = 0x00a02468, .end = 0x00a024b0 },
2217         { .start = 0x00a024c8, .end = 0x00a024cc },
2218         { .start = 0x00a02500, .end = 0x00a02504 },
2219         { .start = 0x00a0250c, .end = 0x00a02510 },
2220         { .start = 0x00a02540, .end = 0x00a02554 },
2221         { .start = 0x00a02580, .end = 0x00a025f4 },
2222         { .start = 0x00a02600, .end = 0x00a0260c },
2223         { .start = 0x00a02648, .end = 0x00a02650 },
2224         { .start = 0x00a02680, .end = 0x00a02680 },
2225         { .start = 0x00a026c0, .end = 0x00a026d0 },
2226         { .start = 0x00a02700, .end = 0x00a0270c },
2227         { .start = 0x00a02804, .end = 0x00a02804 },
2228         { .start = 0x00a02818, .end = 0x00a0281c },
2229         { .start = 0x00a02c00, .end = 0x00a02db4 },
2230         { .start = 0x00a02df4, .end = 0x00a02fb0 },
2231         { .start = 0x00a03000, .end = 0x00a03014 },
2232         { .start = 0x00a0301c, .end = 0x00a0302c },
2233         { .start = 0x00a03034, .end = 0x00a03038 },
2234         { .start = 0x00a03040, .end = 0x00a03048 },
2235         { .start = 0x00a03060, .end = 0x00a03068 },
2236         { .start = 0x00a03070, .end = 0x00a03074 },
2237         { .start = 0x00a0307c, .end = 0x00a0307c },
2238         { .start = 0x00a03080, .end = 0x00a03084 },
2239         { .start = 0x00a0308c, .end = 0x00a03090 },
2240         { .start = 0x00a03098, .end = 0x00a03098 },
2241         { .start = 0x00a030a0, .end = 0x00a030a0 },
2242         { .start = 0x00a030a8, .end = 0x00a030b4 },
2243         { .start = 0x00a030bc, .end = 0x00a030bc },
2244         { .start = 0x00a030c0, .end = 0x00a0312c },
2245         { .start = 0x00a03c00, .end = 0x00a03c5c },
2246         { .start = 0x00a04400, .end = 0x00a04454 },
2247         { .start = 0x00a04460, .end = 0x00a04474 },
2248         { .start = 0x00a044c0, .end = 0x00a044ec },
2249         { .start = 0x00a04500, .end = 0x00a04504 },
2250         { .start = 0x00a04510, .end = 0x00a04538 },
2251         { .start = 0x00a04540, .end = 0x00a04548 },
2252         { .start = 0x00a04560, .end = 0x00a0457c },
2253         { .start = 0x00a04590, .end = 0x00a04598 },
2254         { .start = 0x00a045c0, .end = 0x00a045f4 },
2255 };
2256
2257 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2258                                     struct iwl_fw_error_dump_data **data)
2259 {
2260         struct iwl_fw_error_dump_prph *prph;
2261         unsigned long flags;
2262         u32 prph_len = 0, i;
2263
2264         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2265                 return 0;
2266
2267         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2268                 /* The range includes both boundaries */
2269                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2270                          iwl_prph_dump_addr[i].start + 4;
2271                 int reg;
2272                 __le32 *val;
2273
2274                 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
2275
2276                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2277                 (*data)->len = cpu_to_le32(sizeof(*prph) +
2278                                         num_bytes_in_chunk);
2279                 prph = (void *)(*data)->data;
2280                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2281                 val = (void *)prph->data;
2282
2283                 for (reg = iwl_prph_dump_addr[i].start;
2284                      reg <= iwl_prph_dump_addr[i].end;
2285                      reg += 4)
2286                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2287                                                                       reg));
2288                 *data = iwl_fw_error_next_data(*data);
2289         }
2290
2291         iwl_trans_release_nic_access(trans, &flags);
2292
2293         return prph_len;
2294 }
2295
2296 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2297                                    struct iwl_fw_error_dump_data **data,
2298                                    int allocated_rb_nums)
2299 {
2300         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2301         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2302         struct iwl_rxq *rxq = &trans_pcie->rxq;
2303         u32 i, r, j, rb_len = 0;
2304
2305         spin_lock(&rxq->lock);
2306
2307         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2308
2309         for (i = rxq->read, j = 0;
2310              i != r && j < allocated_rb_nums;
2311              i = (i + 1) & RX_QUEUE_MASK, j++) {
2312                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2313                 struct iwl_fw_error_dump_rb *rb;
2314
2315                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2316                                DMA_FROM_DEVICE);
2317
2318                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2319
2320                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2321                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2322                 rb = (void *)(*data)->data;
2323                 rb->index = cpu_to_le32(i);
2324                 memcpy(rb->data, page_address(rxb->page), max_len);
2325                 /* remap the page for the free benefit */
2326                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2327                                                      max_len,
2328                                                      DMA_FROM_DEVICE);
2329
2330                 *data = iwl_fw_error_next_data(*data);
2331         }
2332
2333         spin_unlock(&rxq->lock);
2334
2335         return rb_len;
2336 }
2337 #define IWL_CSR_TO_DUMP (0x250)
2338
2339 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2340                                    struct iwl_fw_error_dump_data **data)
2341 {
2342         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2343         __le32 *val;
2344         int i;
2345
2346         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2347         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2348         val = (void *)(*data)->data;
2349
2350         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2351                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2352
2353         *data = iwl_fw_error_next_data(*data);
2354
2355         return csr_len;
2356 }
2357
2358 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2359                                        struct iwl_fw_error_dump_data **data)
2360 {
2361         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2362         unsigned long flags;
2363         __le32 *val;
2364         int i;
2365
2366         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2367                 return 0;
2368
2369         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2370         (*data)->len = cpu_to_le32(fh_regs_len);
2371         val = (void *)(*data)->data;
2372
2373         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2374                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2375
2376         iwl_trans_release_nic_access(trans, &flags);
2377
2378         *data = iwl_fw_error_next_data(*data);
2379
2380         return sizeof(**data) + fh_regs_len;
2381 }
2382
2383 static u32
2384 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2385                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2386                                  u32 monitor_len)
2387 {
2388         u32 buf_size_in_dwords = (monitor_len >> 2);
2389         u32 *buffer = (u32 *)fw_mon_data->data;
2390         unsigned long flags;
2391         u32 i;
2392
2393         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2394                 return 0;
2395
2396         __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2397         for (i = 0; i < buf_size_in_dwords; i++)
2398                 buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR);
2399         __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2400
2401         iwl_trans_release_nic_access(trans, &flags);
2402
2403         return monitor_len;
2404 }
2405
2406 static u32
2407 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2408                             struct iwl_fw_error_dump_data **data,
2409                             u32 monitor_len)
2410 {
2411         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2412         u32 len = 0;
2413
2414         if ((trans_pcie->fw_mon_page &&
2415              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2416             trans->dbg_dest_tlv) {
2417                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2418                 u32 base, write_ptr, wrap_cnt;
2419
2420                 /* If there was a dest TLV - use the values from there */
2421                 if (trans->dbg_dest_tlv) {
2422                         write_ptr =
2423                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2424                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2425                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2426                 } else {
2427                         base = MON_BUFF_BASE_ADDR;
2428                         write_ptr = MON_BUFF_WRPTR;
2429                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2430                 }
2431
2432                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2433                 fw_mon_data = (void *)(*data)->data;
2434                 fw_mon_data->fw_mon_wr_ptr =
2435                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2436                 fw_mon_data->fw_mon_cycle_cnt =
2437                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2438                 fw_mon_data->fw_mon_base_ptr =
2439                         cpu_to_le32(iwl_read_prph(trans, base));
2440
2441                 len += sizeof(**data) + sizeof(*fw_mon_data);
2442                 if (trans_pcie->fw_mon_page) {
2443                         /*
2444                          * The firmware is now asserted, it won't write anything
2445                          * to the buffer. CPU can take ownership to fetch the
2446                          * data. The buffer will be handed back to the device
2447                          * before the firmware will be restarted.
2448                          */
2449                         dma_sync_single_for_cpu(trans->dev,
2450                                                 trans_pcie->fw_mon_phys,
2451                                                 trans_pcie->fw_mon_size,
2452                                                 DMA_FROM_DEVICE);
2453                         memcpy(fw_mon_data->data,
2454                                page_address(trans_pcie->fw_mon_page),
2455                                trans_pcie->fw_mon_size);
2456
2457                         monitor_len = trans_pcie->fw_mon_size;
2458                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2459                         /*
2460                          * Update pointers to reflect actual values after
2461                          * shifting
2462                          */
2463                         base = iwl_read_prph(trans, base) <<
2464                                trans->dbg_dest_tlv->base_shift;
2465                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2466                                            monitor_len / sizeof(u32));
2467                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2468                         monitor_len =
2469                                 iwl_trans_pci_dump_marbh_monitor(trans,
2470                                                                  fw_mon_data,
2471                                                                  monitor_len);
2472                 } else {
2473                         /* Didn't match anything - output no monitor data */
2474                         monitor_len = 0;
2475                 }
2476
2477                 len += monitor_len;
2478                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2479         }
2480
2481         return len;
2482 }
2483
2484 static struct iwl_trans_dump_data
2485 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2486                           struct iwl_fw_dbg_trigger_tlv *trigger)
2487 {
2488         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2489         struct iwl_fw_error_dump_data *data;
2490         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2491         struct iwl_fw_error_dump_txcmd *txcmd;
2492         struct iwl_trans_dump_data *dump_data;
2493         u32 len, num_rbs;
2494         u32 monitor_len;
2495         int i, ptr;
2496         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status);
2497
2498         /* transport dump header */
2499         len = sizeof(*dump_data);
2500
2501         /* host commands */
2502         len += sizeof(*data) +
2503                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2504
2505         /* FW monitor */
2506         if (trans_pcie->fw_mon_page) {
2507                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2508                        trans_pcie->fw_mon_size;
2509                 monitor_len = trans_pcie->fw_mon_size;
2510         } else if (trans->dbg_dest_tlv) {
2511                 u32 base, end;
2512
2513                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2514                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2515
2516                 base = iwl_read_prph(trans, base) <<
2517                        trans->dbg_dest_tlv->base_shift;
2518                 end = iwl_read_prph(trans, end) <<
2519                       trans->dbg_dest_tlv->end_shift;
2520
2521                 /* Make "end" point to the actual end */
2522                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2523                     trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2524                         end += (1 << trans->dbg_dest_tlv->end_shift);
2525                 monitor_len = end - base;
2526                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2527                        monitor_len;
2528         } else {
2529                 monitor_len = 0;
2530         }
2531
2532         if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2533                 dump_data = vzalloc(len);
2534                 if (!dump_data)
2535                         return NULL;
2536
2537                 data = (void *)dump_data->data;
2538                 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2539                 dump_data->len = len;
2540
2541                 return dump_data;
2542         }
2543
2544         /* CSR registers */
2545         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2546
2547         /* PRPH registers */
2548         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2549                 /* The range includes both boundaries */
2550                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2551                         iwl_prph_dump_addr[i].start + 4;
2552
2553                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2554                        num_bytes_in_chunk;
2555         }
2556
2557         /* FH registers */
2558         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2559
2560         if (dump_rbs) {
2561                 /* RBs */
2562                 num_rbs = le16_to_cpu(ACCESS_ONCE(
2563                                       trans_pcie->rxq.rb_stts->closed_rb_num))
2564                                       & 0x0FFF;
2565                 num_rbs = (num_rbs - trans_pcie->rxq.read) & RX_QUEUE_MASK;
2566                 len += num_rbs * (sizeof(*data) +
2567                                   sizeof(struct iwl_fw_error_dump_rb) +
2568                                   (PAGE_SIZE << trans_pcie->rx_page_order));
2569         }
2570
2571         dump_data = vzalloc(len);
2572         if (!dump_data)
2573                 return NULL;
2574
2575         len = 0;
2576         data = (void *)dump_data->data;
2577         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2578         txcmd = (void *)data->data;
2579         spin_lock_bh(&cmdq->lock);
2580         ptr = cmdq->q.write_ptr;
2581         for (i = 0; i < cmdq->q.n_window; i++) {
2582                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2583                 u32 caplen, cmdlen;
2584
2585                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2586                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2587
2588                 if (cmdlen) {
2589                         len += sizeof(*txcmd) + caplen;
2590                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2591                         txcmd->caplen = cpu_to_le32(caplen);
2592                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2593                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2594                 }
2595
2596                 ptr = iwl_queue_dec_wrap(ptr);
2597         }
2598         spin_unlock_bh(&cmdq->lock);
2599
2600         data->len = cpu_to_le32(len);
2601         len += sizeof(*data);
2602         data = iwl_fw_error_next_data(data);
2603
2604         len += iwl_trans_pcie_dump_prph(trans, &data);
2605         len += iwl_trans_pcie_dump_csr(trans, &data);
2606         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2607         if (dump_rbs)
2608                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2609
2610         len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2611
2612         dump_data->len = len;
2613
2614         return dump_data;
2615 }
2616
2617 static const struct iwl_trans_ops trans_ops_pcie = {
2618         .start_hw = iwl_trans_pcie_start_hw,
2619         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2620         .fw_alive = iwl_trans_pcie_fw_alive,
2621         .start_fw = iwl_trans_pcie_start_fw,
2622         .stop_device = iwl_trans_pcie_stop_device,
2623
2624         .d3_suspend = iwl_trans_pcie_d3_suspend,
2625         .d3_resume = iwl_trans_pcie_d3_resume,
2626
2627         .send_cmd = iwl_trans_pcie_send_hcmd,
2628
2629         .tx = iwl_trans_pcie_tx,
2630         .reclaim = iwl_trans_pcie_reclaim,
2631
2632         .txq_disable = iwl_trans_pcie_txq_disable,
2633         .txq_enable = iwl_trans_pcie_txq_enable,
2634
2635         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2636
2637         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2638         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2639
2640         .write8 = iwl_trans_pcie_write8,
2641         .write32 = iwl_trans_pcie_write32,
2642         .read32 = iwl_trans_pcie_read32,
2643         .read_prph = iwl_trans_pcie_read_prph,
2644         .write_prph = iwl_trans_pcie_write_prph,
2645         .read_mem = iwl_trans_pcie_read_mem,
2646         .write_mem = iwl_trans_pcie_write_mem,
2647         .configure = iwl_trans_pcie_configure,
2648         .set_pmi = iwl_trans_pcie_set_pmi,
2649         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2650         .release_nic_access = iwl_trans_pcie_release_nic_access,
2651         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2652
2653         .ref = iwl_trans_pcie_ref,
2654         .unref = iwl_trans_pcie_unref,
2655
2656         .dump_data = iwl_trans_pcie_dump_data,
2657 };
2658
2659 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2660                                        const struct pci_device_id *ent,
2661                                        const struct iwl_cfg *cfg)
2662 {
2663         struct iwl_trans_pcie *trans_pcie;
2664         struct iwl_trans *trans;
2665         u16 pci_cmd;
2666         int ret;
2667
2668         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2669                                 &pdev->dev, cfg, &trans_ops_pcie, 0);
2670         if (!trans)
2671                 return ERR_PTR(-ENOMEM);
2672
2673         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;
2674
2675         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2676
2677         trans_pcie->trans = trans;
2678         spin_lock_init(&trans_pcie->irq_lock);
2679         spin_lock_init(&trans_pcie->reg_lock);
2680         spin_lock_init(&trans_pcie->ref_lock);
2681         mutex_init(&trans_pcie->mutex);
2682         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2683
2684         ret = pci_enable_device(pdev);
2685         if (ret)
2686                 goto out_no_pci;
2687
2688         if (!cfg->base_params->pcie_l1_allowed) {
2689                 /*
2690                  * W/A - seems to solve weird behavior. We need to remove this
2691                  * if we don't want to stay in L1 all the time. This wastes a
2692                  * lot of power.
2693                  */
2694                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2695                                        PCIE_LINK_STATE_L1 |
2696                                        PCIE_LINK_STATE_CLKPM);
2697         }
2698
2699         pci_set_master(pdev);
2700
2701         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2702         if (!ret)
2703                 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2704         if (ret) {
2705                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2706                 if (!ret)
2707                         ret = pci_set_consistent_dma_mask(pdev,
2708                                                           DMA_BIT_MASK(32));
2709                 /* both attempts failed: */
2710                 if (ret) {
2711                         dev_err(&pdev->dev, "No suitable DMA available\n");
2712                         goto out_pci_disable_device;
2713                 }
2714         }
2715
2716         ret = pci_request_regions(pdev, DRV_NAME);
2717         if (ret) {
2718                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2719                 goto out_pci_disable_device;
2720         }
2721
2722         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2723         if (!trans_pcie->hw_base) {
2724                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2725                 ret = -ENODEV;
2726                 goto out_pci_release_regions;
2727         }
2728
2729         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2730          * PCI Tx retries from interfering with C3 CPU state */
2731         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2732
2733         trans->dev = &pdev->dev;
2734         trans_pcie->pci_dev = pdev;
2735         iwl_disable_interrupts(trans);
2736
2737         ret = pci_enable_msi(pdev);
2738         if (ret) {
2739                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
2740                 /* enable rfkill interrupt: hw bug w/a */
2741                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2742                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2743                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2744                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2745                 }
2746         }
2747
2748         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2749         /*
2750          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2751          * changed, and now the revision step also includes bit 0-1 (no more
2752          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2753          * in the old format.
2754          */
2755         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2756                 unsigned long flags;
2757
2758                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2759                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2760
2761                 ret = iwl_pcie_prepare_card_hw(trans);
2762                 if (ret) {
2763                         IWL_WARN(trans, "Exit HW not ready\n");
2764                         goto out_pci_disable_msi;
2765                 }
2766
2767                 /*
2768                  * in-order to recognize C step driver should read chip version
2769                  * id located at the AUX bus MISC address space.
2770                  */
2771                 iwl_set_bit(trans, CSR_GP_CNTRL,
2772                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2773                 udelay(2);
2774
2775                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2776                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2777                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2778                                    25000);
2779                 if (ret < 0) {
2780                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2781                         goto out_pci_disable_msi;
2782                 }
2783
2784                 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2785                         u32 hw_step;
2786
2787                         hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2788                         hw_step |= ENABLE_WFPM;
2789                         __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2790                         hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2791                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2792                         if (hw_step == 0x3)
2793                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2794                                                 (SILICON_C_STEP << 2);
2795                         iwl_trans_release_nic_access(trans, &flags);
2796                 }
2797         }
2798
2799         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2800         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2801                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2802
2803         /* Initialize the wait queue for commands */
2804         init_waitqueue_head(&trans_pcie->wait_command_queue);
2805
2806         ret = iwl_pcie_alloc_ict(trans);
2807         if (ret)
2808                 goto out_pci_disable_msi;
2809
2810         ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2811                                    iwl_pcie_irq_handler,
2812                                    IRQF_SHARED, DRV_NAME, trans);
2813         if (ret) {
2814                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2815                 goto out_free_ict;
2816         }
2817
2818         trans_pcie->inta_mask = CSR_INI_SET_MASK;
2819         trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
2820
2821         return trans;
2822
2823 out_free_ict:
2824         iwl_pcie_free_ict(trans);
2825 out_pci_disable_msi:
2826         pci_disable_msi(pdev);
2827 out_pci_release_regions:
2828         pci_release_regions(pdev);
2829 out_pci_disable_device:
2830         pci_disable_device(pdev);
2831 out_no_pci:
2832         iwl_trans_free(trans);
2833         return ERR_PTR(ret);
2834 }