kernel/drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
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  14  *
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  49  *    contributors may be used to endorse or promote products derived
  50  *    from this software without specific prior written permission.
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  52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  62  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63  *
  64  *****************************************************************************/
  65 #include <linux/pci.h>
  66 #include <linux/pci-aspm.h>
  67 #include <linux/interrupt.h>
  68 #include <linux/debugfs.h>
  69 #include <linux/sched.h>
  70 #include <linux/bitops.h>
  71 #include <linux/gfp.h>
  72 #include <linux/vmalloc.h>
  73
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-scd.h"
  79 #include "iwl-agn-hw.h"
  80 #include "iwl-fw-error-dump.h"
  81 #include "internal.h"
  82 #include "iwl-fh.h"
  83
  84 /* extended range in FW SRAM */
  85 #define IWL_FW_MEM_EXTENDED_START       0x40000
  86 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  87
  88 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  89 {
  90         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  91
  92         if (!trans_pcie->fw_mon_page)
  93                 return;
  94
  95         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  96                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
  97         __free_pages(trans_pcie->fw_mon_page,
  98                      get_order(trans_pcie->fw_mon_size));
  99         trans_pcie->fw_mon_page = NULL;
 100         trans_pcie->fw_mon_phys = 0;
 101         trans_pcie->fw_mon_size = 0;
 102 }
 103
 104 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
 105 {
 106         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 107         struct page *page = NULL;
 108         dma_addr_t phys;
 109         u32 size;
 110         u8 power;
 111
 112         if (trans_pcie->fw_mon_page) {
 113                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 114                                            trans_pcie->fw_mon_size,
 115                                            DMA_FROM_DEVICE);
 116                 return;
 117         }
 118
 119         phys = 0;
 120         for (power = 26; power >= 11; power--) {
 121                 int order;
 122
 123                 size = BIT(power);
 124                 order = get_order(size);
 125                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 126                                    order);
 127                 if (!page)
 128                         continue;
 129
 130                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 131                                     DMA_FROM_DEVICE);
 132                 if (dma_mapping_error(trans->dev, phys)) {
 133                         __free_pages(page, order);
 134                         page = NULL;
 135                         continue;
 136                 }
 137                 IWL_INFO(trans,
 138                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 139                          size, order);
 140                 break;
 141         }
 142
 143         if (WARN_ON_ONCE(!page))
 144                 return;
 145
 146         trans_pcie->fw_mon_page = page;
 147         trans_pcie->fw_mon_phys = phys;
 148         trans_pcie->fw_mon_size = size;
 149 }
 150
 151 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 152 {
 153         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 154                     ((reg & 0x0000ffff) | (2 << 28)));
 155         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 156 }
 157
 158 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 159 {
 160         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 161         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 162                     ((reg & 0x0000ffff) | (3 << 28)));
 163 }
 164
 165 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 166 {
 167         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 168                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 169                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 170                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 171         else
 172                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 173                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 174                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 175 }
 176
 177 /* PCI registers */
 178 #define PCI_CFG_RETRY_TIMEOUT   0x041
 179
 180 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 181 {
 182         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 183         u16 lctl;
 184         u16 cap;
 185
 186         /*
 187          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 188          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 189          * If so (likely), disable L0S, so device moves directly L0->L1;
 190          *    costs negligible amount of power savings.
 191          * If not (unlikely), enable L0S, so there is at least some
 192          *    power savings, even without L1.
 193          */
 194         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 195         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 196                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 197         else
 198                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 199         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 200
 201         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 202         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 203         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 204                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 205                  trans->ltr_enabled ? "En" : "Dis");
 206 }
 207
 208 /*
 209  * Start up NIC's basic functionality after it has been reset
 210  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 211  * NOTE:  This does not load uCode nor start the embedded processor
 212  */
 213 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 214 {
 215         int ret = 0;
 216         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 217
 218         /*
 219          * Use "set_bit" below rather than "write", to preserve any hardware
 220          * bits already set by default after reset.
 221          */
 222
 223         /* Disable L0S exit timer (platform NMI Work/Around) */
 224         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 225                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 226                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 227
 228         /*
 229          * Disable L0s without affecting L1;
 230          *  don't wait for ICH L0s (ICH bug W/A)
 231          */
 232         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 233                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 234
 235         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 236         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 237
 238         /*
 239          * Enable HAP INTA (interrupt from management bus) to
 240          * wake device's PCI Express link L1a -> L0s
 241          */
 242         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 243                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 244
 245         iwl_pcie_apm_config(trans);
 246
 247         /* Configure analog phase-lock-loop before activating to D0A */
 248         if (trans->cfg->base_params->pll_cfg_val)
 249                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 250                             trans->cfg->base_params->pll_cfg_val);
 251
 252         /*
 253          * Set "initialization complete" bit to move adapter from
 254          * D0U* --> D0A* (powered-up active) state.
 255          */
 256         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 257
 258         /*
 259          * Wait for clock stabilization; once stabilized, access to
 260          * device-internal resources is supported, e.g. iwl_write_prph()
 261          * and accesses to uCode SRAM.
 262          */
 263         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 264                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 265                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 266         if (ret < 0) {
 267                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 268                 goto out;
 269         }
 270
 271         if (trans->cfg->host_interrupt_operation_mode) {
 272                 /*
 273                  * This is a bit of an abuse - This is needed for 7260 / 3160
 274                  * only check host_interrupt_operation_mode even if this is
 275                  * not related to host_interrupt_operation_mode.
 276                  *
 277                  * Enable the oscillator to count wake up time for L1 exit. This
 278                  * consumes slightly more power (100uA) - but allows to be sure
 279                  * that we wake up from L1 on time.
 280                  *
 281                  * This looks weird: read twice the same register, discard the
 282                  * value, set a bit, and yet again, read that same register
 283                  * just to discard the value. But that's the way the hardware
 284                  * seems to like it.
 285                  */
 286                 iwl_read_prph(trans, OSC_CLK);
 287                 iwl_read_prph(trans, OSC_CLK);
 288                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 289                 iwl_read_prph(trans, OSC_CLK);
 290                 iwl_read_prph(trans, OSC_CLK);
 291         }
 292
 293         /*
 294          * Enable DMA clock and wait for it to stabilize.
 295          *
 296          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 297          * bits do not disable clocks.  This preserves any hardware
 298          * bits already set by default in "CLK_CTRL_REG" after reset.
 299          */
 300         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
 301                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 302                                APMG_CLK_VAL_DMA_CLK_RQT);
 303                 udelay(20);
 304
 305                 /* Disable L1-Active */
 306                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 307                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 308
 309                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 310                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 311                                APMG_RTC_INT_STT_RFKILL);
 312         }
 313
 314         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 315
 316 out:
 317         return ret;
 318 }
 319
 320 /*
 321  * Enable LP XTAL to avoid HW bug where device may consume much power if
 322  * FW is not loaded after device reset. LP XTAL is disabled by default
 323  * after device HW reset. Do it only if XTAL is fed by internal source.
 324  * Configure device's "persistence" mode to avoid resetting XTAL again when
 325  * SHRD_HW_RST occurs in S3.
 326  */
 327 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 328 {
 329         int ret;
 330         u32 apmg_gp1_reg;
 331         u32 apmg_xtal_cfg_reg;
 332         u32 dl_cfg_reg;
 333
 334         /* Force XTAL ON */
 335         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 336                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 337
 338         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 339         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 340
 341         udelay(10);
 342
 343         /*
 344          * Set "initialization complete" bit to move adapter from
 345          * D0U* --> D0A* (powered-up active) state.
 346          */
 347         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 348
 349         /*
 350          * Wait for clock stabilization; once stabilized, access to
 351          * device-internal resources is possible.
 352          */
 353         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 354                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 355                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 356                            25000);
 357         if (WARN_ON(ret < 0)) {
 358                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 359                 /* Release XTAL ON request */
 360                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 361                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 362                 return;
 363         }
 364
 365         /*
 366          * Clear "disable persistence" to avoid LP XTAL resetting when
 367          * SHRD_HW_RST is applied in S3.
 368          */
 369         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 370                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 371
 372         /*
 373          * Force APMG XTAL to be active to prevent its disabling by HW
 374          * caused by APMG idle state.
 375          */
 376         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 377                                                     SHR_APMG_XTAL_CFG_REG);
 378         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 379                                  apmg_xtal_cfg_reg |
 380                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 381
 382         /*
 383          * Reset entire device again - do controller reset (results in
 384          * SHRD_HW_RST). Turn MAC off before proceeding.
 385          */
 386         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 387
 388         udelay(10);
 389
 390         /* Enable LP XTAL by indirect access through CSR */
 391         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 392         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 393                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 394                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 395
 396         /* Clear delay line clock power up */
 397         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 398         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 399                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 400
 401         /*
 402          * Enable persistence mode to avoid LP XTAL resetting when
 403          * SHRD_HW_RST is applied in S3.
 404          */
 405         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 406                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 407
 408         /*
 409          * Clear "initialization complete" bit to move adapter from
 410          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 411          */
 412         iwl_clear_bit(trans, CSR_GP_CNTRL,
 413                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 414
 415         /* Activates XTAL resources monitor */
 416         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 417                                  CSR_MONITOR_XTAL_RESOURCES);
 418
 419         /* Release XTAL ON request */
 420         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 421                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 422         udelay(10);
 423
 424         /* Release APMG XTAL */
 425         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 426                                  apmg_xtal_cfg_reg &
 427                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 428 }
 429
 430 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 431 {
 432         int ret = 0;
 433
 434         /* stop device's busmaster DMA activity */
 435         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 436
 437         ret = iwl_poll_bit(trans, CSR_RESET,
 438                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 439                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 440         if (ret < 0)
 441                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 442
 443         IWL_DEBUG_INFO(trans, "stop master\n");
 444
 445         return ret;
 446 }
 447
 448 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 449 {
 450         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 451
 452         if (op_mode_leave) {
 453                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 454                         iwl_pcie_apm_init(trans);
 455
 456                 /* inform ME that we are leaving */
 457                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 458                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 459                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 460                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
 461                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 462                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 463                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 464                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 465                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 466                         mdelay(1);
 467                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 468                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 469                 }
 470                 mdelay(5);
 471         }
 472
 473         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 474
 475         /* Stop device's DMA activity */
 476         iwl_pcie_apm_stop_master(trans);
 477
 478         if (trans->cfg->lp_xtal_workaround) {
 479                 iwl_pcie_apm_lp_xtal_enable(trans);
 480                 return;
 481         }
 482
 483         /* Reset the entire device */
 484         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 485
 486         udelay(10);
 487
 488         /*
 489          * Clear "initialization complete" bit to move adapter from
 490          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 491          */
 492         iwl_clear_bit(trans, CSR_GP_CNTRL,
 493                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 494 }
 495
 496 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 497 {
 498         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 499
 500         /* nic_init */
 501         spin_lock(&trans_pcie->irq_lock);
 502         iwl_pcie_apm_init(trans);
 503
 504         spin_unlock(&trans_pcie->irq_lock);
 505
 506         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 507                 iwl_pcie_set_pwr(trans, false);
 508
 509         iwl_op_mode_nic_config(trans->op_mode);
 510
 511         /* Allocate the RX queue, or reset if it is already allocated */
 512         iwl_pcie_rx_init(trans);
 513
 514         /* Allocate or reset and init all Tx and Command queues */
 515         if (iwl_pcie_tx_init(trans))
 516                 return -ENOMEM;
 517
 518         if (trans->cfg->base_params->shadow_reg_enable) {
 519                 /* enable shadow regs in HW */
 520                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 521                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 522         }
 523
 524         return 0;
 525 }
 526
 527 #define HW_READY_TIMEOUT (50)
 528
 529 /* Note: returns poll_bit return value, which is >= 0 if success */
 530 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 531 {
 532         int ret;
 533
 534         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 535                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 536
 537         /* See if we got it */
 538         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 539                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 540                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 541                            HW_READY_TIMEOUT);
 542
 543         if (ret >= 0)
 544                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 545
 546         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 547         return ret;
 548 }
 549
 550 /* Note: returns standard 0/-ERROR code */
 551 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 552 {
 553         int ret;
 554         int t = 0;
 555         int iter;
 556
 557         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 558
 559         ret = iwl_pcie_set_hw_ready(trans);
 560         /* If the card is ready, exit 0 */
 561         if (ret >= 0)
 562                 return 0;
 563
 564         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 565                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 566         msleep(1);
 567
 568         for (iter = 0; iter < 10; iter++) {
 569                 /* If HW is not ready, prepare the conditions to check again */
 570                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 571                             CSR_HW_IF_CONFIG_REG_PREPARE);
 572
 573                 do {
 574                         ret = iwl_pcie_set_hw_ready(trans);
 575                         if (ret >= 0) {
 576                                 ret = 0;
 577                                 goto out;
 578                         }
 579
 580                         usleep_range(200, 1000);
 581                         t += 200;
 582                 } while (t < 150000);
 583                 msleep(25);
 584         }
 585
 586         IWL_ERR(trans, "Couldn't prepare the card\n");
 587
 588 out:
 589         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 590                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 591
 592         return ret;
 593 }
 594
 595 /*
 596  * ucode
 597  */
 598 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 599                                    dma_addr_t phy_addr, u32 byte_cnt)
 600 {
 601         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 602         int ret;
 603
 604         trans_pcie->ucode_write_complete = false;
 605
 606         iwl_write_direct32(trans,
 607                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 608                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 609
 610         iwl_write_direct32(trans,
 611                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 612                            dst_addr);
 613
 614         iwl_write_direct32(trans,
 615                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 616                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 617
 618         iwl_write_direct32(trans,
 619                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 620                            (iwl_get_dma_hi_addr(phy_addr)
 621                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 622
 623         iwl_write_direct32(trans,
 624                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 625                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 626                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 627                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 628
 629         iwl_write_direct32(trans,
 630                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 631                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 632                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 633                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 634
 635         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 636                                  trans_pcie->ucode_write_complete, 5 * HZ);
 637         if (!ret) {
 638                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 639                 return -ETIMEDOUT;
 640         }
 641
 642         return 0;
 643 }
 644
 645 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 646                             const struct fw_desc *section)
 647 {
 648         u8 *v_addr;
 649         dma_addr_t p_addr;
 650         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 651         int ret = 0;
 652
 653         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 654                      section_num);
 655
 656         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 657                                     GFP_KERNEL | __GFP_NOWARN);
 658         if (!v_addr) {
 659                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 660                 chunk_sz = PAGE_SIZE;
 661                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 662                                             &p_addr, GFP_KERNEL);
 663                 if (!v_addr)
 664                         return -ENOMEM;
 665         }
 666
 667         for (offset = 0; offset < section->len; offset += chunk_sz) {
 668                 u32 copy_size, dst_addr;
 669                 bool extended_addr = false;
 670
 671                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 672                 dst_addr = section->offset + offset;
 673
 674                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 675                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 676                         extended_addr = true;
 677
 678                 if (extended_addr)
 679                         iwl_set_bits_prph(trans, LMPM_CHICK,
 680                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 681
 682                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 683                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 684                                                    copy_size);
 685
 686                 if (extended_addr)
 687                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 688                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 689
 690                 if (ret) {
 691                         IWL_ERR(trans,
 692                                 "Could not load the [%d] uCode section\n",
 693                                 section_num);
 694                         break;
 695                 }
 696         }
 697
 698         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 699         return ret;
 700 }
 701
 702 /*
 703  * Driver Takes the ownership on secure machine before FW load
 704  * and prevent race with the BT load.
 705  * W/A for ROM bug. (should be remove in the next Si step)
 706  */
 707 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
 708 {
 709         u32 val, loop = 1000;
 710
 711         /*
 712          * Check the RSA semaphore is accessible.
 713          * If the HW isn't locked and the rsa semaphore isn't accessible,
 714          * we are in trouble.
 715          */
 716         val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
 717         if (val & (BIT(1) | BIT(17))) {
 718                 IWL_INFO(trans,
 719                          "can't access the RSA semaphore it is write protected\n");
 720                 return 0;
 721         }
 722
 723         /* take ownership on the AUX IF */
 724         iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
 725         iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
 726
 727         do {
 728                 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
 729                 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
 730                 if (val == 0x1) {
 731                         iwl_write_prph(trans, RSA_ENABLE, 0);
 732                         return 0;
 733                 }
 734
 735                 udelay(10);
 736                 loop--;
 737         } while (loop > 0);
 738
 739         IWL_ERR(trans, "Failed to take ownership on secure machine\n");
 740         return -EIO;
 741 }
 742
 743 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 744                                            const struct fw_img *image,
 745                                            int cpu,
 746                                            int *first_ucode_section)
 747 {
 748         int shift_param;
 749         int i, ret = 0, sec_num = 0x1;
 750         u32 val, last_read_idx = 0;
 751
 752         if (cpu == 1) {
 753                 shift_param = 0;
 754                 *first_ucode_section = 0;
 755         } else {
 756                 shift_param = 16;
 757                 (*first_ucode_section)++;
 758         }
 759
 760         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 761                 last_read_idx = i;
 762
 763                 if (!image->sec[i].data ||
 764                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 765                         IWL_DEBUG_FW(trans,
 766                                      "Break since Data not valid or Empty section, sec = %d\n",
 767                                      i);
 768                         break;
 769                 }
 770
 771                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 772                 if (ret)
 773                         return ret;
 774
 775                 /* Notify the ucode of the loaded section number and status */
 776                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 777                 val = val | (sec_num << shift_param);
 778                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 779                 sec_num = (sec_num << 1) | 0x1;
 780         }
 781
 782         *first_ucode_section = last_read_idx;
 783
 784         if (cpu == 1)
 785                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
 786         else
 787                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 788
 789         return 0;
 790 }
 791
 792 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 793                                       const struct fw_img *image,
 794                                       int cpu,
 795                                       int *first_ucode_section)
 796 {
 797         int shift_param;
 798         int i, ret = 0;
 799         u32 last_read_idx = 0;
 800
 801         if (cpu == 1) {
 802                 shift_param = 0;
 803                 *first_ucode_section = 0;
 804         } else {
 805                 shift_param = 16;
 806                 (*first_ucode_section)++;
 807         }
 808
 809         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 810                 last_read_idx = i;
 811
 812                 if (!image->sec[i].data ||
 813                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 814                         IWL_DEBUG_FW(trans,
 815                                      "Break since Data not valid or Empty section, sec = %d\n",
 816                                      i);
 817                         break;
 818                 }
 819
 820                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 821                 if (ret)
 822                         return ret;
 823         }
 824
 825         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 826                 iwl_set_bits_prph(trans,
 827                                   CSR_UCODE_LOAD_STATUS_ADDR,
 828                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 829                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 830                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 831                                         shift_param);
 832
 833         *first_ucode_section = last_read_idx;
 834
 835         return 0;
 836 }
 837
 838 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 839 {
 840         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 841         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 842         int i;
 843
 844         if (dest->version)
 845                 IWL_ERR(trans,
 846                         "DBG DEST version is %d - expect issues\n",
 847                         dest->version);
 848
 849         IWL_INFO(trans, "Applying debug destination %s\n",
 850                  get_fw_dbg_mode_string(dest->monitor_mode));
 851
 852         if (dest->monitor_mode == EXTERNAL_MODE)
 853                 iwl_pcie_alloc_fw_monitor(trans);
 854         else
 855                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 856
 857         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 858                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 859                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 860
 861                 switch (dest->reg_ops[i].op) {
 862                 case CSR_ASSIGN:
 863                         iwl_write32(trans, addr, val);
 864                         break;
 865                 case CSR_SETBIT:
 866                         iwl_set_bit(trans, addr, BIT(val));
 867                         break;
 868                 case CSR_CLEARBIT:
 869                         iwl_clear_bit(trans, addr, BIT(val));
 870                         break;
 871                 case PRPH_ASSIGN:
 872                         iwl_write_prph(trans, addr, val);
 873                         break;
 874                 case PRPH_SETBIT:
 875                         iwl_set_bits_prph(trans, addr, BIT(val));
 876                         break;
 877                 case PRPH_CLEARBIT:
 878                         iwl_clear_bits_prph(trans, addr, BIT(val));
 879                         break;
 880                 default:
 881                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 882                                 dest->reg_ops[i].op);
 883                         break;
 884                 }
 885         }
 886
 887         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 888                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 889                                trans_pcie->fw_mon_phys >> dest->base_shift);
 890                 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 891                                (trans_pcie->fw_mon_phys +
 892                                 trans_pcie->fw_mon_size) >> dest->end_shift);
 893         }
 894 }
 895
 896 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 897                                 const struct fw_img *image)
 898 {
 899         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 900         int ret = 0;
 901         int first_ucode_section;
 902
 903         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 904                      image->is_dual_cpus ? "Dual" : "Single");
 905
 906         /* load to FW the binary non secured sections of CPU1 */
 907         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 908         if (ret)
 909                 return ret;
 910
 911         if (image->is_dual_cpus) {
 912                 /* set CPU2 header address */
 913                 iwl_write_prph(trans,
 914                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 915                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 916
 917                 /* load to FW the binary sections of CPU2 */
 918                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 919                                                  &first_ucode_section);
 920                 if (ret)
 921                         return ret;
 922         }
 923
 924         /* supported for 7000 only for the moment */
 925         if (iwlwifi_mod_params.fw_monitor &&
 926             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 927                 iwl_pcie_alloc_fw_monitor(trans);
 928
 929                 if (trans_pcie->fw_mon_size) {
 930                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 931                                        trans_pcie->fw_mon_phys >> 4);
 932                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 933                                        (trans_pcie->fw_mon_phys +
 934                                         trans_pcie->fw_mon_size) >> 4);
 935                 }
 936         } else if (trans->dbg_dest_tlv) {
 937                 iwl_pcie_apply_destination(trans);
 938         }
 939
 940         /* release CPU reset */
 941         iwl_write32(trans, CSR_RESET, 0);
 942
 943         return 0;
 944 }
 945
 946 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
 947                                           const struct fw_img *image)
 948 {
 949         int ret = 0;
 950         int first_ucode_section;
 951
 952         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 953                      image->is_dual_cpus ? "Dual" : "Single");
 954
 955         if (trans->dbg_dest_tlv)
 956                 iwl_pcie_apply_destination(trans);
 957
 958         /* TODO: remove in the next Si step */
 959         ret = iwl_pcie_rsa_race_bug_wa(trans);
 960         if (ret)
 961                 return ret;
 962
 963         /* configure the ucode to be ready to get the secured image */
 964         /* release CPU reset */
 965         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 966
 967         /* load to FW the binary Secured sections of CPU1 */
 968         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
 969                                               &first_ucode_section);
 970         if (ret)
 971                 return ret;
 972
 973         /* load to FW the binary sections of CPU2 */
 974         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 2,
 975                                               &first_ucode_section);
 976         if (ret)
 977                 return ret;
 978
 979         return 0;
 980 }
 981
 982 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 983                                    const struct fw_img *fw, bool run_in_rfkill)
 984 {
 985         int ret;
 986         bool hw_rfkill;
 987
 988         /* This may fail if AMT took ownership of the device */
 989         if (iwl_pcie_prepare_card_hw(trans)) {
 990                 IWL_WARN(trans, "Exit HW not ready\n");
 991                 return -EIO;
 992         }
 993
 994         iwl_enable_rfkill_int(trans);
 995
 996         /* If platform's RF_KILL switch is NOT set to KILL */
 997         hw_rfkill = iwl_is_rfkill_set(trans);
 998         if (hw_rfkill)
 999                 set_bit(STATUS_RFKILL, &trans->status);
1000         else
1001                 clear_bit(STATUS_RFKILL, &trans->status);
1002         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1003         if (hw_rfkill && !run_in_rfkill)
1004                 return -ERFKILL;
1005
1006         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1007
1008         ret = iwl_pcie_nic_init(trans);
1009         if (ret) {
1010                 IWL_ERR(trans, "Unable to init nic\n");
1011                 return ret;
1012         }
1013
1014         /* make sure rfkill handshake bits are cleared */
1015         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1016         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1017                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1018
1019         /* clear (again), then enable host interrupts */
1020         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1021         iwl_enable_interrupts(trans);
1022
1023         /* really make sure rfkill handshake bits are cleared */
1024         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1025         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1026
1027         /* Load the given image to the HW */
1028         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1029                 return iwl_pcie_load_given_ucode_8000(trans, fw);
1030         else
1031                 return iwl_pcie_load_given_ucode(trans, fw);
1032 }
1033
1034 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1035 {
1036         iwl_pcie_reset_ict(trans);
1037         iwl_pcie_tx_start(trans, scd_addr);
1038 }
1039
1040 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1041 {
1042         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1043         bool hw_rfkill, was_hw_rfkill;
1044
1045         was_hw_rfkill = iwl_is_rfkill_set(trans);
1046
1047         /* tell the device to stop sending interrupts */
1048         spin_lock(&trans_pcie->irq_lock);
1049         iwl_disable_interrupts(trans);
1050         spin_unlock(&trans_pcie->irq_lock);
1051
1052         /* device going down, Stop using ICT table */
1053         iwl_pcie_disable_ict(trans);
1054
1055         /*
1056          * If a HW restart happens during firmware loading,
1057          * then the firmware loading might call this function
1058          * and later it might be called again due to the
1059          * restart. So don't process again if the device is
1060          * already dead.
1061          */
1062         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1063                 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1064                 iwl_pcie_tx_stop(trans);
1065                 iwl_pcie_rx_stop(trans);
1066
1067                 /* Power-down device's busmaster DMA clocks */
1068                 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
1069                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1070                                        APMG_CLK_VAL_DMA_CLK_RQT);
1071                         udelay(5);
1072                 }
1073         }
1074
1075         /* Make sure (redundant) we've released our request to stay awake */
1076         iwl_clear_bit(trans, CSR_GP_CNTRL,
1077                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1078
1079         /* Stop the device, and put it in low power state */
1080         iwl_pcie_apm_stop(trans, false);
1081
1082         /* stop and reset the on-board processor */
1083         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1084         udelay(20);
1085
1086         /*
1087          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1088          * This is a bug in certain verions of the hardware.
1089          * Certain devices also keep sending HW RF kill interrupt all
1090          * the time, unless the interrupt is ACKed even if the interrupt
1091          * should be masked. Re-ACK all the interrupts here.
1092          */
1093         spin_lock(&trans_pcie->irq_lock);
1094         iwl_disable_interrupts(trans);
1095         spin_unlock(&trans_pcie->irq_lock);
1096
1097
1098         /* clear all status bits */
1099         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1100         clear_bit(STATUS_INT_ENABLED, &trans->status);
1101         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1102         clear_bit(STATUS_RFKILL, &trans->status);
1103
1104         /*
1105          * Even if we stop the HW, we still want the RF kill
1106          * interrupt
1107          */
1108         iwl_enable_rfkill_int(trans);
1109
1110         /*
1111          * Check again since the RF kill state may have changed while
1112          * all the interrupts were disabled, in this case we couldn't
1113          * receive the RF kill interrupt and update the state in the
1114          * op_mode.
1115          * Don't call the op_mode if the rkfill state hasn't changed.
1116          * This allows the op_mode to call stop_device from the rfkill
1117          * notification without endless recursion. Under very rare
1118          * circumstances, we might have a small recursion if the rfkill
1119          * state changed exactly now while we were called from stop_device.
1120          * This is very unlikely but can happen and is supported.
1121          */
1122         hw_rfkill = iwl_is_rfkill_set(trans);
1123         if (hw_rfkill)
1124                 set_bit(STATUS_RFKILL, &trans->status);
1125         else
1126                 clear_bit(STATUS_RFKILL, &trans->status);
1127         if (hw_rfkill != was_hw_rfkill)
1128                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1129
1130         /* re-take ownership to prevent other users from stealing the deivce */
1131         iwl_pcie_prepare_card_hw(trans);
1132 }
1133
1134 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1135 {
1136         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1137                 iwl_trans_pcie_stop_device(trans, true);
1138 }
1139
1140 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1141 {
1142         iwl_disable_interrupts(trans);
1143
1144         /*
1145          * in testing mode, the host stays awake and the
1146          * hardware won't be reset (not even partially)
1147          */
1148         if (test)
1149                 return;
1150
1151         iwl_pcie_disable_ict(trans);
1152
1153         iwl_clear_bit(trans, CSR_GP_CNTRL,
1154                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1155         iwl_clear_bit(trans, CSR_GP_CNTRL,
1156                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1157
1158         /*
1159          * reset TX queues -- some of their registers reset during S3
1160          * so if we don't reset everything here the D3 image would try
1161          * to execute some invalid memory upon resume
1162          */
1163         iwl_trans_pcie_tx_reset(trans);
1164
1165         iwl_pcie_set_pwr(trans, true);
1166 }
1167
1168 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1169                                     enum iwl_d3_status *status,
1170                                     bool test)
1171 {
1172         u32 val;
1173         int ret;
1174
1175         if (test) {
1176                 iwl_enable_interrupts(trans);
1177                 *status = IWL_D3_STATUS_ALIVE;
1178                 return 0;
1179         }
1180
1181         /*
1182          * Also enables interrupts - none will happen as the device doesn't
1183          * know we're waking it up, only when the opmode actually tells it
1184          * after this call.
1185          */
1186         iwl_pcie_reset_ict(trans);
1187
1188         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1189         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1190
1191         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1192                 udelay(2);
1193
1194         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1195                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1196                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1197                            25000);
1198         if (ret < 0) {
1199                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1200                 return ret;
1201         }
1202
1203         iwl_pcie_set_pwr(trans, false);
1204
1205         iwl_trans_pcie_tx_reset(trans);
1206
1207         ret = iwl_pcie_rx_init(trans);
1208         if (ret) {
1209                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1210                 return ret;
1211         }
1212
1213         val = iwl_read32(trans, CSR_RESET);
1214         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1215                 *status = IWL_D3_STATUS_RESET;
1216         else
1217                 *status = IWL_D3_STATUS_ALIVE;
1218
1219         return 0;
1220 }
1221
1222 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1223 {
1224         bool hw_rfkill;
1225         int err;
1226
1227         err = iwl_pcie_prepare_card_hw(trans);
1228         if (err) {
1229                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1230                 return err;
1231         }
1232
1233         /* Reset the entire device */
1234         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1235
1236         usleep_range(10, 15);
1237
1238         iwl_pcie_apm_init(trans);
1239
1240         /* From now on, the op_mode will be kept updated about RF kill state */
1241         iwl_enable_rfkill_int(trans);
1242
1243         hw_rfkill = iwl_is_rfkill_set(trans);
1244         if (hw_rfkill)
1245                 set_bit(STATUS_RFKILL, &trans->status);
1246         else
1247                 clear_bit(STATUS_RFKILL, &trans->status);
1248         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1249
1250         return 0;
1251 }
1252
1253 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1254 {
1255         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1256
1257         /* disable interrupts - don't enable HW RF kill interrupt */
1258         spin_lock(&trans_pcie->irq_lock);
1259         iwl_disable_interrupts(trans);
1260         spin_unlock(&trans_pcie->irq_lock);
1261
1262         iwl_pcie_apm_stop(trans, true);
1263
1264         spin_lock(&trans_pcie->irq_lock);
1265         iwl_disable_interrupts(trans);
1266         spin_unlock(&trans_pcie->irq_lock);
1267
1268         iwl_pcie_disable_ict(trans);
1269 }
1270
1271 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1272 {
1273         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1274 }
1275
1276 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1277 {
1278         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1279 }
1280
1281 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1282 {
1283         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1284 }
1285
1286 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1287 {
1288         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1289                                ((reg & 0x000FFFFF) | (3 << 24)));
1290         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1291 }
1292
1293 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1294                                       u32 val)
1295 {
1296         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1297                                ((addr & 0x000FFFFF) | (3 << 24)));
1298         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1299 }
1300
1301 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1302 {
1303         WARN_ON(1);
1304         return 0;
1305 }
1306
1307 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1308                                      const struct iwl_trans_config *trans_cfg)
1309 {
1310         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1311
1312         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1313         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1314         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1315         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1316                 trans_pcie->n_no_reclaim_cmds = 0;
1317         else
1318                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1319         if (trans_pcie->n_no_reclaim_cmds)
1320                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1321                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1322
1323         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1324         if (trans_pcie->rx_buf_size_8k)
1325                 trans_pcie->rx_page_order = get_order(8 * 1024);
1326         else
1327                 trans_pcie->rx_page_order = get_order(4 * 1024);
1328
1329         trans_pcie->command_names = trans_cfg->command_names;
1330         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1331         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1332
1333         /* init ref_count to 1 (should be cleared when ucode is loaded) */
1334         trans_pcie->ref_count = 1;
1335
1336         /* Initialize NAPI here - it should be before registering to mac80211
1337          * in the opmode but after the HW struct is allocated.
1338          * As this function may be called again in some corner cases don't
1339          * do anything if NAPI was already initialized.
1340          */
1341         if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1342                 init_dummy_netdev(&trans_pcie->napi_dev);
1343                 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1344                                      &trans_pcie->napi_dev,
1345                                      iwl_pcie_dummy_napi_poll, 64);
1346         }
1347 }
1348
1349 void iwl_trans_pcie_free(struct iwl_trans *trans)
1350 {
1351         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1352
1353         synchronize_irq(trans_pcie->pci_dev->irq);
1354
1355         iwl_pcie_tx_free(trans);
1356         iwl_pcie_rx_free(trans);
1357
1358         free_irq(trans_pcie->pci_dev->irq, trans);
1359         iwl_pcie_free_ict(trans);
1360
1361         pci_disable_msi(trans_pcie->pci_dev);
1362         iounmap(trans_pcie->hw_base);
1363         pci_release_regions(trans_pcie->pci_dev);
1364         pci_disable_device(trans_pcie->pci_dev);
1365         kmem_cache_destroy(trans->dev_cmd_pool);
1366
1367         if (trans_pcie->napi.poll)
1368                 netif_napi_del(&trans_pcie->napi);
1369
1370         iwl_pcie_free_fw_monitor(trans);
1371
1372         kfree(trans);
1373 }
1374
1375 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1376 {
1377         if (state)
1378                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1379         else
1380                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1381 }
1382
1383 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1384                                                 unsigned long *flags)
1385 {
1386         int ret;
1387         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1388
1389         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1390
1391         if (trans_pcie->cmd_hold_nic_awake)
1392                 goto out;
1393
1394         /* this bit wakes up the NIC */
1395         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1396                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1397         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1398                 udelay(2);
1399
1400         /*
1401          * These bits say the device is running, and should keep running for
1402          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1403          * but they do not indicate that embedded SRAM is restored yet;
1404          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1405          * to/from host DRAM when sleeping/waking for power-saving.
1406          * Each direction takes approximately 1/4 millisecond; with this
1407          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1408          * series of register accesses are expected (e.g. reading Event Log),
1409          * to keep device from sleeping.
1410          *
1411          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1412          * SRAM is okay/restored.  We don't check that here because this call
1413          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1414          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1415          *
1416          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1417          * and do not save/restore SRAM when power cycling.
1418          */
1419         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1420                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1421                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1422                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1423         if (unlikely(ret < 0)) {
1424                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1425                 if (!silent) {
1426                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1427                         WARN_ONCE(1,
1428                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1429                                   val);
1430                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1431                         return false;
1432                 }
1433         }
1434
1435 out:
1436         /*
1437          * Fool sparse by faking we release the lock - sparse will
1438          * track nic_access anyway.
1439          */
1440         __release(&trans_pcie->reg_lock);
1441         return true;
1442 }
1443
1444 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1445                                               unsigned long *flags)
1446 {
1447         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1448
1449         lockdep_assert_held(&trans_pcie->reg_lock);
1450
1451         /*
1452          * Fool sparse by faking we acquiring the lock - sparse will
1453          * track nic_access anyway.
1454          */
1455         __acquire(&trans_pcie->reg_lock);
1456
1457         if (trans_pcie->cmd_hold_nic_awake)
1458                 goto out;
1459
1460         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1461                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1462         /*
1463          * Above we read the CSR_GP_CNTRL register, which will flush
1464          * any previous writes, but we need the write that clears the
1465          * MAC_ACCESS_REQ bit to be performed before any other writes
1466          * scheduled on different CPUs (after we drop reg_lock).
1467          */
1468         mmiowb();
1469 out:
1470         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1471 }
1472
1473 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1474                                    void *buf, int dwords)
1475 {
1476         unsigned long flags;
1477         int offs, ret = 0;
1478         u32 *vals = buf;
1479
1480         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1481                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1482                 for (offs = 0; offs < dwords; offs++)
1483                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1484                 iwl_trans_release_nic_access(trans, &flags);
1485         } else {
1486                 ret = -EBUSY;
1487         }
1488         return ret;
1489 }
1490
1491 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1492                                     const void *buf, int dwords)
1493 {
1494         unsigned long flags;
1495         int offs, ret = 0;
1496         const u32 *vals = buf;
1497
1498         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1499                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1500                 for (offs = 0; offs < dwords; offs++)
1501                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1502                                     vals ? vals[offs] : 0);
1503                 iwl_trans_release_nic_access(trans, &flags);
1504         } else {
1505                 ret = -EBUSY;
1506         }
1507         return ret;
1508 }
1509
1510 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1511                                             unsigned long txqs,
1512                                             bool freeze)
1513 {
1514         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1515         int queue;
1516
1517         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1518                 struct iwl_txq *txq = &trans_pcie->txq[queue];
1519                 unsigned long now;
1520
1521                 spin_lock_bh(&txq->lock);
1522
1523                 now = jiffies;
1524
1525                 if (txq->frozen == freeze)
1526                         goto next_queue;
1527
1528                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1529                                     freeze ? "Freezing" : "Waking", queue);
1530
1531                 txq->frozen = freeze;
1532
1533                 if (txq->q.read_ptr == txq->q.write_ptr)
1534                         goto next_queue;
1535
1536                 if (freeze) {
1537                         if (unlikely(time_after(now,
1538                                                 txq->stuck_timer.expires))) {
1539                                 /*
1540                                  * The timer should have fired, maybe it is
1541                                  * spinning right now on the lock.
1542                                  */
1543                                 goto next_queue;
1544                         }
1545                         /* remember how long until the timer fires */
1546                         txq->frozen_expiry_remainder =
1547                                 txq->stuck_timer.expires - now;
1548                         del_timer(&txq->stuck_timer);
1549                         goto next_queue;
1550                 }
1551
1552                 /*
1553                  * Wake a non-empty queue -> arm timer with the
1554                  * remainder before it froze
1555                  */
1556                 mod_timer(&txq->stuck_timer,
1557                           now + txq->frozen_expiry_remainder);
1558
1559 next_queue:
1560                 spin_unlock_bh(&txq->lock);
1561         }
1562 }
1563
1564 #define IWL_FLUSH_WAIT_MS       2000
1565
1566 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1567 {
1568         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1569         struct iwl_txq *txq;
1570         struct iwl_queue *q;
1571         int cnt;
1572         unsigned long now = jiffies;
1573         u32 scd_sram_addr;
1574         u8 buf[16];
1575         int ret = 0;
1576
1577         /* waiting for all the tx frames complete might take a while */
1578         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1579                 u8 wr_ptr;
1580
1581                 if (cnt == trans_pcie->cmd_queue)
1582                         continue;
1583                 if (!test_bit(cnt, trans_pcie->queue_used))
1584                         continue;
1585                 if (!(BIT(cnt) & txq_bm))
1586                         continue;
1587
1588                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1589                 txq = &trans_pcie->txq[cnt];
1590                 q = &txq->q;
1591                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1592
1593                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1594                        !time_after(jiffies,
1595                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1596                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1597
1598                         if (WARN_ONCE(wr_ptr != write_ptr,
1599                                       "WR pointer moved while flushing %d -> %d\n",
1600                                       wr_ptr, write_ptr))
1601                                 return -ETIMEDOUT;
1602                         msleep(1);
1603                 }
1604
1605                 if (q->read_ptr != q->write_ptr) {
1606                         IWL_ERR(trans,
1607                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1608                         ret = -ETIMEDOUT;
1609                         break;
1610                 }
1611                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1612         }
1613
1614         if (!ret)
1615                 return 0;
1616
1617         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1618                 txq->q.read_ptr, txq->q.write_ptr);
1619
1620         scd_sram_addr = trans_pcie->scd_base_addr +
1621                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1622         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1623
1624         iwl_print_hex_error(trans, buf, sizeof(buf));
1625
1626         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1627                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1628                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1629
1630         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1631                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1632                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1633                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1634                 u32 tbl_dw =
1635                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1636                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1637
1638                 if (cnt & 0x1)
1639                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1640                 else
1641                         tbl_dw = tbl_dw & 0x0000FFFF;
1642
1643                 IWL_ERR(trans,
1644                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1645                         cnt, active ? "" : "in", fifo, tbl_dw,
1646                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1647                                 (TFD_QUEUE_SIZE_MAX - 1),
1648                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1649         }
1650
1651         return ret;
1652 }
1653
1654 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1655                                          u32 mask, u32 value)
1656 {
1657         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1658         unsigned long flags;
1659
1660         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1661         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1662         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1663 }
1664
1665 void iwl_trans_pcie_ref(struct iwl_trans *trans)
1666 {
1667         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1668         unsigned long flags;
1669
1670         if (iwlwifi_mod_params.d0i3_disable)
1671                 return;
1672
1673         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1674         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1675         trans_pcie->ref_count++;
1676         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1677 }
1678
1679 void iwl_trans_pcie_unref(struct iwl_trans *trans)
1680 {
1681         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1682         unsigned long flags;
1683
1684         if (iwlwifi_mod_params.d0i3_disable)
1685                 return;
1686
1687         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1688         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1689         if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1690                 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1691                 return;
1692         }
1693         trans_pcie->ref_count--;
1694         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1695 }
1696
1697 static const char *get_csr_string(int cmd)
1698 {
1699 #define IWL_CMD(x) case x: return #x
1700         switch (cmd) {
1701         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1702         IWL_CMD(CSR_INT_COALESCING);
1703         IWL_CMD(CSR_INT);
1704         IWL_CMD(CSR_INT_MASK);
1705         IWL_CMD(CSR_FH_INT_STATUS);
1706         IWL_CMD(CSR_GPIO_IN);
1707         IWL_CMD(CSR_RESET);
1708         IWL_CMD(CSR_GP_CNTRL);
1709         IWL_CMD(CSR_HW_REV);
1710         IWL_CMD(CSR_EEPROM_REG);
1711         IWL_CMD(CSR_EEPROM_GP);
1712         IWL_CMD(CSR_OTP_GP_REG);
1713         IWL_CMD(CSR_GIO_REG);
1714         IWL_CMD(CSR_GP_UCODE_REG);
1715         IWL_CMD(CSR_GP_DRIVER_REG);
1716         IWL_CMD(CSR_UCODE_DRV_GP1);
1717         IWL_CMD(CSR_UCODE_DRV_GP2);
1718         IWL_CMD(CSR_LED_REG);
1719         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1720         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1721         IWL_CMD(CSR_ANA_PLL_CFG);
1722         IWL_CMD(CSR_HW_REV_WA_REG);
1723         IWL_CMD(CSR_MONITOR_STATUS_REG);
1724         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1725         default:
1726                 return "UNKNOWN";
1727         }
1728 #undef IWL_CMD
1729 }
1730
1731 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1732 {
1733         int i;
1734         static const u32 csr_tbl[] = {
1735                 CSR_HW_IF_CONFIG_REG,
1736                 CSR_INT_COALESCING,
1737                 CSR_INT,
1738                 CSR_INT_MASK,
1739                 CSR_FH_INT_STATUS,
1740                 CSR_GPIO_IN,
1741                 CSR_RESET,
1742                 CSR_GP_CNTRL,
1743                 CSR_HW_REV,
1744                 CSR_EEPROM_REG,
1745                 CSR_EEPROM_GP,
1746                 CSR_OTP_GP_REG,
1747                 CSR_GIO_REG,
1748                 CSR_GP_UCODE_REG,
1749                 CSR_GP_DRIVER_REG,
1750                 CSR_UCODE_DRV_GP1,
1751                 CSR_UCODE_DRV_GP2,
1752                 CSR_LED_REG,
1753                 CSR_DRAM_INT_TBL_REG,
1754                 CSR_GIO_CHICKEN_BITS,
1755                 CSR_ANA_PLL_CFG,
1756                 CSR_MONITOR_STATUS_REG,
1757                 CSR_HW_REV_WA_REG,
1758                 CSR_DBG_HPET_MEM_REG
1759         };
1760         IWL_ERR(trans, "CSR values:\n");
1761         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1762                 "CSR_INT_PERIODIC_REG)\n");
1763         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1764                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1765                         get_csr_string(csr_tbl[i]),
1766                         iwl_read32(trans, csr_tbl[i]));
1767         }
1768 }
1769
1770 #ifdef CONFIG_IWLWIFI_DEBUGFS
1771 /* create and remove of files */
1772 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1773         if (!debugfs_create_file(#name, mode, parent, trans,            \
1774                                  &iwl_dbgfs_##name##_ops))              \
1775                 goto err;                                               \
1776 } while (0)
1777
1778 /* file operation */
1779 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1780 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1781         .read = iwl_dbgfs_##name##_read,                                \
1782         .open = simple_open,                                            \
1783         .llseek = generic_file_llseek,                                  \
1784 };
1785
1786 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1787 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1788         .write = iwl_dbgfs_##name##_write,                              \
1789         .open = simple_open,                                            \
1790         .llseek = generic_file_llseek,                                  \
1791 };
1792
1793 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1794 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1795         .write = iwl_dbgfs_##name##_write,                              \
1796         .read = iwl_dbgfs_##name##_read,                                \
1797         .open = simple_open,                                            \
1798         .llseek = generic_file_llseek,                                  \
1799 };
1800
1801 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1802                                        char __user *user_buf,
1803                                        size_t count, loff_t *ppos)
1804 {
1805         struct iwl_trans *trans = file->private_data;
1806         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1807         struct iwl_txq *txq;
1808         struct iwl_queue *q;
1809         char *buf;
1810         int pos = 0;
1811         int cnt;
1812         int ret;
1813         size_t bufsz;
1814
1815         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
1816
1817         if (!trans_pcie->txq)
1818                 return -EAGAIN;
1819
1820         buf = kzalloc(bufsz, GFP_KERNEL);
1821         if (!buf)
1822                 return -ENOMEM;
1823
1824         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1825                 txq = &trans_pcie->txq[cnt];
1826                 q = &txq->q;
1827                 pos += scnprintf(buf + pos, bufsz - pos,
1828                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
1829                                 cnt, q->read_ptr, q->write_ptr,
1830                                 !!test_bit(cnt, trans_pcie->queue_used),
1831                                  !!test_bit(cnt, trans_pcie->queue_stopped),
1832                                  txq->need_update, txq->frozen,
1833                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1834         }
1835         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1836         kfree(buf);
1837         return ret;
1838 }
1839
1840 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1841                                        char __user *user_buf,
1842                                        size_t count, loff_t *ppos)
1843 {
1844         struct iwl_trans *trans = file->private_data;
1845         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1846         struct iwl_rxq *rxq = &trans_pcie->rxq;
1847         char buf[256];
1848         int pos = 0;
1849         const size_t bufsz = sizeof(buf);
1850
1851         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1852                                                 rxq->read);
1853         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1854                                                 rxq->write);
1855         pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1856                                                 rxq->write_actual);
1857         pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1858                                                 rxq->need_update);
1859         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1860                                                 rxq->free_count);
1861         if (rxq->rb_stts) {
1862                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1863                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1864         } else {
1865                 pos += scnprintf(buf + pos, bufsz - pos,
1866                                         "closed_rb_num: Not Allocated\n");
1867         }
1868         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1869 }
1870
1871 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1872                                         char __user *user_buf,
1873                                         size_t count, loff_t *ppos)
1874 {
1875         struct iwl_trans *trans = file->private_data;
1876         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1877         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1878
1879         int pos = 0;
1880         char *buf;
1881         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1882         ssize_t ret;
1883
1884         buf = kzalloc(bufsz, GFP_KERNEL);
1885         if (!buf)
1886                 return -ENOMEM;
1887
1888         pos += scnprintf(buf + pos, bufsz - pos,
1889                         "Interrupt Statistics Report:\n");
1890
1891         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1892                 isr_stats->hw);
1893         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1894                 isr_stats->sw);
1895         if (isr_stats->sw || isr_stats->hw) {
1896                 pos += scnprintf(buf + pos, bufsz - pos,
1897                         "\tLast Restarting Code:  0x%X\n",
1898                         isr_stats->err_code);
1899         }
1900 #ifdef CONFIG_IWLWIFI_DEBUG
1901         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1902                 isr_stats->sch);
1903         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1904                 isr_stats->alive);
1905 #endif
1906         pos += scnprintf(buf + pos, bufsz - pos,
1907                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1908
1909         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1910                 isr_stats->ctkill);
1911
1912         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1913                 isr_stats->wakeup);
1914
1915         pos += scnprintf(buf + pos, bufsz - pos,
1916                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1917
1918         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1919                 isr_stats->tx);
1920
1921         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1922                 isr_stats->unhandled);
1923
1924         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1925         kfree(buf);
1926         return ret;
1927 }
1928
1929 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1930                                          const char __user *user_buf,
1931                                          size_t count, loff_t *ppos)
1932 {
1933         struct iwl_trans *trans = file->private_data;
1934         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1935         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1936
1937         char buf[8];
1938         int buf_size;
1939         u32 reset_flag;
1940
1941         memset(buf, 0, sizeof(buf));
1942         buf_size = min(count, sizeof(buf) -  1);
1943         if (copy_from_user(buf, user_buf, buf_size))
1944                 return -EFAULT;
1945         if (sscanf(buf, "%x", &reset_flag) != 1)
1946                 return -EFAULT;
1947         if (reset_flag == 0)
1948                 memset(isr_stats, 0, sizeof(*isr_stats));
1949
1950         return count;
1951 }
1952
1953 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1954                                    const char __user *user_buf,
1955                                    size_t count, loff_t *ppos)
1956 {
1957         struct iwl_trans *trans = file->private_data;
1958         char buf[8];
1959         int buf_size;
1960         int csr;
1961
1962         memset(buf, 0, sizeof(buf));
1963         buf_size = min(count, sizeof(buf) -  1);
1964         if (copy_from_user(buf, user_buf, buf_size))
1965                 return -EFAULT;
1966         if (sscanf(buf, "%d", &csr) != 1)
1967                 return -EFAULT;
1968
1969         iwl_pcie_dump_csr(trans);
1970
1971         return count;
1972 }
1973
1974 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1975                                      char __user *user_buf,
1976                                      size_t count, loff_t *ppos)
1977 {
1978         struct iwl_trans *trans = file->private_data;
1979         char *buf = NULL;
1980         ssize_t ret;
1981
1982         ret = iwl_dump_fh(trans, &buf);
1983         if (ret < 0)
1984                 return ret;
1985         if (!buf)
1986                 return -EINVAL;
1987         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1988         kfree(buf);
1989         return ret;
1990 }
1991
1992 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1993 DEBUGFS_READ_FILE_OPS(fh_reg);
1994 DEBUGFS_READ_FILE_OPS(rx_queue);
1995 DEBUGFS_READ_FILE_OPS(tx_queue);
1996 DEBUGFS_WRITE_FILE_OPS(csr);
1997
1998 /*
1999  * Create the debugfs files and directories
2000  *
2001  */
2002 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2003                                          struct dentry *dir)
2004 {
2005         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2006         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2007         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2008         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2009         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2010         return 0;
2011
2012 err:
2013         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2014         return -ENOMEM;
2015 }
2016 #else
2017 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2018                                          struct dentry *dir)
2019 {
2020         return 0;
2021 }
2022 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2023
2024 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2025 {
2026         u32 cmdlen = 0;
2027         int i;
2028
2029         for (i = 0; i < IWL_NUM_OF_TBS; i++)
2030                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2031
2032         return cmdlen;
2033 }
2034
2035 static const struct {
2036         u32 start, end;
2037 } iwl_prph_dump_addr[] = {
2038         { .start = 0x00a00000, .end = 0x00a00000 },
2039         { .start = 0x00a0000c, .end = 0x00a00024 },
2040         { .start = 0x00a0002c, .end = 0x00a0003c },
2041         { .start = 0x00a00410, .end = 0x00a00418 },
2042         { .start = 0x00a00420, .end = 0x00a00420 },
2043         { .start = 0x00a00428, .end = 0x00a00428 },
2044         { .start = 0x00a00430, .end = 0x00a0043c },
2045         { .start = 0x00a00444, .end = 0x00a00444 },
2046         { .start = 0x00a004c0, .end = 0x00a004cc },
2047         { .start = 0x00a004d8, .end = 0x00a004d8 },
2048         { .start = 0x00a004e0, .end = 0x00a004f0 },
2049         { .start = 0x00a00840, .end = 0x00a00840 },
2050         { .start = 0x00a00850, .end = 0x00a00858 },
2051         { .start = 0x00a01004, .end = 0x00a01008 },
2052         { .start = 0x00a01010, .end = 0x00a01010 },
2053         { .start = 0x00a01018, .end = 0x00a01018 },
2054         { .start = 0x00a01024, .end = 0x00a01024 },
2055         { .start = 0x00a0102c, .end = 0x00a01034 },
2056         { .start = 0x00a0103c, .end = 0x00a01040 },
2057         { .start = 0x00a01048, .end = 0x00a01094 },
2058         { .start = 0x00a01c00, .end = 0x00a01c20 },
2059         { .start = 0x00a01c58, .end = 0x00a01c58 },
2060         { .start = 0x00a01c7c, .end = 0x00a01c7c },
2061         { .start = 0x00a01c28, .end = 0x00a01c54 },
2062         { .start = 0x00a01c5c, .end = 0x00a01c5c },
2063         { .start = 0x00a01c60, .end = 0x00a01cdc },
2064         { .start = 0x00a01ce0, .end = 0x00a01d0c },
2065         { .start = 0x00a01d18, .end = 0x00a01d20 },
2066         { .start = 0x00a01d2c, .end = 0x00a01d30 },
2067         { .start = 0x00a01d40, .end = 0x00a01d5c },
2068         { .start = 0x00a01d80, .end = 0x00a01d80 },
2069         { .start = 0x00a01d98, .end = 0x00a01d9c },
2070         { .start = 0x00a01da8, .end = 0x00a01da8 },
2071         { .start = 0x00a01db8, .end = 0x00a01df4 },
2072         { .start = 0x00a01dc0, .end = 0x00a01dfc },
2073         { .start = 0x00a01e00, .end = 0x00a01e2c },
2074         { .start = 0x00a01e40, .end = 0x00a01e60 },
2075         { .start = 0x00a01e68, .end = 0x00a01e6c },
2076         { .start = 0x00a01e74, .end = 0x00a01e74 },
2077         { .start = 0x00a01e84, .end = 0x00a01e90 },
2078         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
2079         { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2080         { .start = 0x00a01f00, .end = 0x00a01f1c },
2081         { .start = 0x00a01f44, .end = 0x00a01ffc },
2082         { .start = 0x00a02000, .end = 0x00a02048 },
2083         { .start = 0x00a02068, .end = 0x00a020f0 },
2084         { .start = 0x00a02100, .end = 0x00a02118 },
2085         { .start = 0x00a02140, .end = 0x00a0214c },
2086         { .start = 0x00a02168, .end = 0x00a0218c },
2087         { .start = 0x00a021c0, .end = 0x00a021c0 },
2088         { .start = 0x00a02400, .end = 0x00a02410 },
2089         { .start = 0x00a02418, .end = 0x00a02420 },
2090         { .start = 0x00a02428, .end = 0x00a0242c },
2091         { .start = 0x00a02434, .end = 0x00a02434 },
2092         { .start = 0x00a02440, .end = 0x00a02460 },
2093         { .start = 0x00a02468, .end = 0x00a024b0 },
2094         { .start = 0x00a024c8, .end = 0x00a024cc },
2095         { .start = 0x00a02500, .end = 0x00a02504 },
2096         { .start = 0x00a0250c, .end = 0x00a02510 },
2097         { .start = 0x00a02540, .end = 0x00a02554 },
2098         { .start = 0x00a02580, .end = 0x00a025f4 },
2099         { .start = 0x00a02600, .end = 0x00a0260c },
2100         { .start = 0x00a02648, .end = 0x00a02650 },
2101         { .start = 0x00a02680, .end = 0x00a02680 },
2102         { .start = 0x00a026c0, .end = 0x00a026d0 },
2103         { .start = 0x00a02700, .end = 0x00a0270c },
2104         { .start = 0x00a02804, .end = 0x00a02804 },
2105         { .start = 0x00a02818, .end = 0x00a0281c },
2106         { .start = 0x00a02c00, .end = 0x00a02db4 },
2107         { .start = 0x00a02df4, .end = 0x00a02fb0 },
2108         { .start = 0x00a03000, .end = 0x00a03014 },
2109         { .start = 0x00a0301c, .end = 0x00a0302c },
2110         { .start = 0x00a03034, .end = 0x00a03038 },
2111         { .start = 0x00a03040, .end = 0x00a03048 },
2112         { .start = 0x00a03060, .end = 0x00a03068 },
2113         { .start = 0x00a03070, .end = 0x00a03074 },
2114         { .start = 0x00a0307c, .end = 0x00a0307c },
2115         { .start = 0x00a03080, .end = 0x00a03084 },
2116         { .start = 0x00a0308c, .end = 0x00a03090 },
2117         { .start = 0x00a03098, .end = 0x00a03098 },
2118         { .start = 0x00a030a0, .end = 0x00a030a0 },
2119         { .start = 0x00a030a8, .end = 0x00a030b4 },
2120         { .start = 0x00a030bc, .end = 0x00a030bc },
2121         { .start = 0x00a030c0, .end = 0x00a0312c },
2122         { .start = 0x00a03c00, .end = 0x00a03c5c },
2123         { .start = 0x00a04400, .end = 0x00a04454 },
2124         { .start = 0x00a04460, .end = 0x00a04474 },
2125         { .start = 0x00a044c0, .end = 0x00a044ec },
2126         { .start = 0x00a04500, .end = 0x00a04504 },
2127         { .start = 0x00a04510, .end = 0x00a04538 },
2128         { .start = 0x00a04540, .end = 0x00a04548 },
2129         { .start = 0x00a04560, .end = 0x00a0457c },
2130         { .start = 0x00a04590, .end = 0x00a04598 },
2131         { .start = 0x00a045c0, .end = 0x00a045f4 },
2132 };
2133
2134 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2135                                     struct iwl_fw_error_dump_data **data)
2136 {
2137         struct iwl_fw_error_dump_prph *prph;
2138         unsigned long flags;
2139         u32 prph_len = 0, i;
2140
2141         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2142                 return 0;
2143
2144         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2145                 /* The range includes both boundaries */
2146                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2147                          iwl_prph_dump_addr[i].start + 4;
2148                 int reg;
2149                 __le32 *val;
2150
2151                 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
2152
2153                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2154                 (*data)->len = cpu_to_le32(sizeof(*prph) +
2155                                         num_bytes_in_chunk);
2156                 prph = (void *)(*data)->data;
2157                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2158                 val = (void *)prph->data;
2159
2160                 for (reg = iwl_prph_dump_addr[i].start;
2161                      reg <= iwl_prph_dump_addr[i].end;
2162                      reg += 4)
2163                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2164                                                                       reg));
2165                 *data = iwl_fw_error_next_data(*data);
2166         }
2167
2168         iwl_trans_release_nic_access(trans, &flags);
2169
2170         return prph_len;
2171 }
2172
2173 #define IWL_CSR_TO_DUMP (0x250)
2174
2175 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2176                                    struct iwl_fw_error_dump_data **data)
2177 {
2178         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2179         __le32 *val;
2180         int i;
2181
2182         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2183         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2184         val = (void *)(*data)->data;
2185
2186         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2187                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2188
2189         *data = iwl_fw_error_next_data(*data);
2190
2191         return csr_len;
2192 }
2193
2194 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2195                                        struct iwl_fw_error_dump_data **data)
2196 {
2197         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2198         unsigned long flags;
2199         __le32 *val;
2200         int i;
2201
2202         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2203                 return 0;
2204
2205         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2206         (*data)->len = cpu_to_le32(fh_regs_len);
2207         val = (void *)(*data)->data;
2208
2209         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2210                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2211
2212         iwl_trans_release_nic_access(trans, &flags);
2213
2214         *data = iwl_fw_error_next_data(*data);
2215
2216         return sizeof(**data) + fh_regs_len;
2217 }
2218
2219 static
2220 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
2221 {
2222         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2223         struct iwl_fw_error_dump_data *data;
2224         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2225         struct iwl_fw_error_dump_txcmd *txcmd;
2226         struct iwl_trans_dump_data *dump_data;
2227         u32 len;
2228         u32 monitor_len;
2229         int i, ptr;
2230
2231         /* transport dump header */
2232         len = sizeof(*dump_data);
2233
2234         /* host commands */
2235         len += sizeof(*data) +
2236                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2237
2238         /* CSR registers */
2239         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2240
2241         /* PRPH registers */
2242         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2243                 /* The range includes both boundaries */
2244                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2245                         iwl_prph_dump_addr[i].start + 4;
2246
2247                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2248                         num_bytes_in_chunk;
2249         }
2250
2251         /* FH registers */
2252         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2253
2254         /* FW monitor */
2255         if (trans_pcie->fw_mon_page) {
2256                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2257                        trans_pcie->fw_mon_size;
2258                 monitor_len = trans_pcie->fw_mon_size;
2259         } else if (trans->dbg_dest_tlv) {
2260                 u32 base, end;
2261
2262                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2263                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2264
2265                 base = iwl_read_prph(trans, base) <<
2266                        trans->dbg_dest_tlv->base_shift;
2267                 end = iwl_read_prph(trans, end) <<
2268                       trans->dbg_dest_tlv->end_shift;
2269
2270                 /* Make "end" point to the actual end */
2271                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2272                         end += (1 << trans->dbg_dest_tlv->end_shift);
2273                 monitor_len = end - base;
2274                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2275                        monitor_len;
2276         } else {
2277                 monitor_len = 0;
2278         }
2279
2280         dump_data = vzalloc(len);
2281         if (!dump_data)
2282                 return NULL;
2283
2284         len = 0;
2285         data = (void *)dump_data->data;
2286         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2287         txcmd = (void *)data->data;
2288         spin_lock_bh(&cmdq->lock);
2289         ptr = cmdq->q.write_ptr;
2290         for (i = 0; i < cmdq->q.n_window; i++) {
2291                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2292                 u32 caplen, cmdlen;
2293
2294                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2295                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2296
2297                 if (cmdlen) {
2298                         len += sizeof(*txcmd) + caplen;
2299                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2300                         txcmd->caplen = cpu_to_le32(caplen);
2301                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2302                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2303                 }
2304
2305                 ptr = iwl_queue_dec_wrap(ptr);
2306         }
2307         spin_unlock_bh(&cmdq->lock);
2308
2309         data->len = cpu_to_le32(len);
2310         len += sizeof(*data);
2311         data = iwl_fw_error_next_data(data);
2312
2313         len += iwl_trans_pcie_dump_prph(trans, &data);
2314         len += iwl_trans_pcie_dump_csr(trans, &data);
2315         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2316         /* data is already pointing to the next section */
2317
2318         if ((trans_pcie->fw_mon_page &&
2319              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2320             trans->dbg_dest_tlv) {
2321                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2322                 u32 base, write_ptr, wrap_cnt;
2323
2324                 /* If there was a dest TLV - use the values from there */
2325                 if (trans->dbg_dest_tlv) {
2326                         write_ptr =
2327                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2328                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2329                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2330                 } else {
2331                         base = MON_BUFF_BASE_ADDR;
2332                         write_ptr = MON_BUFF_WRPTR;
2333                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2334                 }
2335
2336                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2337                 fw_mon_data = (void *)data->data;
2338                 fw_mon_data->fw_mon_wr_ptr =
2339                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2340                 fw_mon_data->fw_mon_cycle_cnt =
2341                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2342                 fw_mon_data->fw_mon_base_ptr =
2343                         cpu_to_le32(iwl_read_prph(trans, base));
2344
2345                 len += sizeof(*data) + sizeof(*fw_mon_data);
2346                 if (trans_pcie->fw_mon_page) {
2347                         data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2348                                                 sizeof(*fw_mon_data));
2349
2350                         /*
2351                          * The firmware is now asserted, it won't write anything
2352                          * to the buffer. CPU can take ownership to fetch the
2353                          * data. The buffer will be handed back to the device
2354                          * before the firmware will be restarted.
2355                          */
2356                         dma_sync_single_for_cpu(trans->dev,
2357                                                 trans_pcie->fw_mon_phys,
2358                                                 trans_pcie->fw_mon_size,
2359                                                 DMA_FROM_DEVICE);
2360                         memcpy(fw_mon_data->data,
2361                                page_address(trans_pcie->fw_mon_page),
2362                                trans_pcie->fw_mon_size);
2363
2364                         len += trans_pcie->fw_mon_size;
2365                 } else {
2366                         /* If we are here then the buffer is internal */
2367
2368                         /*
2369                          * Update pointers to reflect actual values after
2370                          * shifting
2371                          */
2372                         base = iwl_read_prph(trans, base) <<
2373                                trans->dbg_dest_tlv->base_shift;
2374                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2375                                            monitor_len / sizeof(u32));
2376                         data->len = cpu_to_le32(sizeof(*fw_mon_data) +
2377                                                 monitor_len);
2378                         len += monitor_len;
2379                 }
2380         }
2381
2382         dump_data->len = len;
2383
2384         return dump_data;
2385 }
2386
2387 static const struct iwl_trans_ops trans_ops_pcie = {
2388         .start_hw = iwl_trans_pcie_start_hw,
2389         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2390         .fw_alive = iwl_trans_pcie_fw_alive,
2391         .start_fw = iwl_trans_pcie_start_fw,
2392         .stop_device = iwl_trans_pcie_stop_device,
2393
2394         .d3_suspend = iwl_trans_pcie_d3_suspend,
2395         .d3_resume = iwl_trans_pcie_d3_resume,
2396
2397         .send_cmd = iwl_trans_pcie_send_hcmd,
2398
2399         .tx = iwl_trans_pcie_tx,
2400         .reclaim = iwl_trans_pcie_reclaim,
2401
2402         .txq_disable = iwl_trans_pcie_txq_disable,
2403         .txq_enable = iwl_trans_pcie_txq_enable,
2404
2405         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2406
2407         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2408         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2409
2410         .write8 = iwl_trans_pcie_write8,
2411         .write32 = iwl_trans_pcie_write32,
2412         .read32 = iwl_trans_pcie_read32,
2413         .read_prph = iwl_trans_pcie_read_prph,
2414         .write_prph = iwl_trans_pcie_write_prph,
2415         .read_mem = iwl_trans_pcie_read_mem,
2416         .write_mem = iwl_trans_pcie_write_mem,
2417         .configure = iwl_trans_pcie_configure,
2418         .set_pmi = iwl_trans_pcie_set_pmi,
2419         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2420         .release_nic_access = iwl_trans_pcie_release_nic_access,
2421         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2422
2423         .ref = iwl_trans_pcie_ref,
2424         .unref = iwl_trans_pcie_unref,
2425
2426         .dump_data = iwl_trans_pcie_dump_data,
2427 };
2428
2429 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2430                                        const struct pci_device_id *ent,
2431                                        const struct iwl_cfg *cfg)
2432 {
2433         struct iwl_trans_pcie *trans_pcie;
2434         struct iwl_trans *trans;
2435         u16 pci_cmd;
2436         int err;
2437
2438         trans = kzalloc(sizeof(struct iwl_trans) +
2439                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2440         if (!trans) {
2441                 err = -ENOMEM;
2442                 goto out;
2443         }
2444
2445         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2446
2447         trans->ops = &trans_ops_pcie;
2448         trans->cfg = cfg;
2449         trans_lockdep_init(trans);
2450         trans_pcie->trans = trans;
2451         spin_lock_init(&trans_pcie->irq_lock);
2452         spin_lock_init(&trans_pcie->reg_lock);
2453         spin_lock_init(&trans_pcie->ref_lock);
2454         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2455
2456         err = pci_enable_device(pdev);
2457         if (err)
2458                 goto out_no_pci;
2459
2460         if (!cfg->base_params->pcie_l1_allowed) {
2461                 /*
2462                  * W/A - seems to solve weird behavior. We need to remove this
2463                  * if we don't want to stay in L1 all the time. This wastes a
2464                  * lot of power.
2465                  */
2466                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2467                                        PCIE_LINK_STATE_L1 |
2468                                        PCIE_LINK_STATE_CLKPM);
2469         }
2470
2471         pci_set_master(pdev);
2472
2473         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2474         if (!err)
2475                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2476         if (err) {
2477                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2478                 if (!err)
2479                         err = pci_set_consistent_dma_mask(pdev,
2480                                                           DMA_BIT_MASK(32));
2481                 /* both attempts failed: */
2482                 if (err) {
2483                         dev_err(&pdev->dev, "No suitable DMA available\n");
2484                         goto out_pci_disable_device;
2485                 }
2486         }
2487
2488         err = pci_request_regions(pdev, DRV_NAME);
2489         if (err) {
2490                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2491                 goto out_pci_disable_device;
2492         }
2493
2494         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2495         if (!trans_pcie->hw_base) {
2496                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2497                 err = -ENODEV;
2498                 goto out_pci_release_regions;
2499         }
2500
2501         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2502          * PCI Tx retries from interfering with C3 CPU state */
2503         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2504
2505         trans->dev = &pdev->dev;
2506         trans_pcie->pci_dev = pdev;
2507         iwl_disable_interrupts(trans);
2508
2509         err = pci_enable_msi(pdev);
2510         if (err) {
2511                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2512                 /* enable rfkill interrupt: hw bug w/a */
2513                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2514                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2515                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2516                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2517                 }
2518         }
2519
2520         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2521         /*
2522          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2523          * changed, and now the revision step also includes bit 0-1 (no more
2524          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2525          * in the old format.
2526          */
2527         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2528                 unsigned long flags;
2529                 int ret;
2530
2531                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2532                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2533
2534                 ret = iwl_pcie_prepare_card_hw(trans);
2535                 if (ret) {
2536                         IWL_WARN(trans, "Exit HW not ready\n");
2537                         goto out_pci_disable_msi;
2538                 }
2539
2540                 /*
2541                  * in-order to recognize C step driver should read chip version
2542                  * id located at the AUX bus MISC address space.
2543                  */
2544                 iwl_set_bit(trans, CSR_GP_CNTRL,
2545                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2546                 udelay(2);
2547
2548                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2549                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2550                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2551                                    25000);
2552                 if (ret < 0) {
2553                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2554                         goto out_pci_disable_msi;
2555                 }
2556
2557                 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2558                         u32 hw_step;
2559
2560                         hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2561                         hw_step |= ENABLE_WFPM;
2562                         __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2563                         hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2564                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2565                         if (hw_step == 0x3)
2566                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2567                                                 (SILICON_C_STEP << 2);
2568                         iwl_trans_release_nic_access(trans, &flags);
2569                 }
2570         }
2571
2572         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2573         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2574                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2575
2576         /* Initialize the wait queue for commands */
2577         init_waitqueue_head(&trans_pcie->wait_command_queue);
2578
2579         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2580                  "iwl_cmd_pool:%s", dev_name(trans->dev));
2581
2582         trans->dev_cmd_headroom = 0;
2583         trans->dev_cmd_pool =
2584                 kmem_cache_create(trans->dev_cmd_pool_name,
2585                                   sizeof(struct iwl_device_cmd)
2586                                   + trans->dev_cmd_headroom,
2587                                   sizeof(void *),
2588                                   SLAB_HWCACHE_ALIGN,
2589                                   NULL);
2590
2591         if (!trans->dev_cmd_pool) {
2592                 err = -ENOMEM;
2593                 goto out_pci_disable_msi;
2594         }
2595
2596         if (iwl_pcie_alloc_ict(trans))
2597                 goto out_free_cmd_pool;
2598
2599         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2600                                    iwl_pcie_irq_handler,
2601                                    IRQF_SHARED, DRV_NAME, trans);
2602         if (err) {
2603                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2604                 goto out_free_ict;
2605         }
2606
2607         trans_pcie->inta_mask = CSR_INI_SET_MASK;
2608         trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
2609
2610         return trans;
2611
2612 out_free_ict:
2613         iwl_pcie_free_ict(trans);
2614 out_free_cmd_pool:
2615         kmem_cache_destroy(trans->dev_cmd_pool);
2616 out_pci_disable_msi:
2617         pci_disable_msi(pdev);
2618 out_pci_release_regions:
2619         pci_release_regions(pdev);
2620 out_pci_disable_device:
2621         pci_disable_device(pdev);
2622 out_no_pci:
2623         kfree(trans);
2624 out:
2625         return ERR_PTR(err);
2626 }