kernel/drivers/net/wireless/ath/ath9k/init.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/dma-mapping.h>
  20 #include <linux/slab.h>
  21 #include <linux/ath9k_platform.h>
  22 #include <linux/module.h>
  23 #include <linux/relay.h>
  24 #include <net/ieee80211_radiotap.h>
  25
  26 #include "ath9k.h"
  27
  28 struct ath9k_eeprom_ctx {
  29         struct completion complete;
  30         struct ath_hw *ah;
  31 };
  32
  33 static char *dev_info = "ath9k";
  34
  35 MODULE_AUTHOR("Atheros Communications");
  36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  38 MODULE_LICENSE("Dual BSD/GPL");
  39
  40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  41 module_param_named(debug, ath9k_debug, uint, 0);
  42 MODULE_PARM_DESC(debug, "Debugging mask");
  43
  44 int ath9k_modparam_nohwcrypt;
  45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
  46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  47
  48 int ath9k_led_blink;
  49 module_param_named(blink, ath9k_led_blink, int, 0444);
  50 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
  51
  52 static int ath9k_led_active_high = -1;
  53 module_param_named(led_active_high, ath9k_led_active_high, int, 0444);
  54 MODULE_PARM_DESC(led_active_high, "Invert LED polarity");
  55
  56 static int ath9k_btcoex_enable;
  57 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
  58 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
  59
  60 static int ath9k_bt_ant_diversity;
  61 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
  62 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
  63
  64 static int ath9k_ps_enable;
  65 module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
  66 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
  67
  68 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  69
  70 int ath9k_use_chanctx;
  71 module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);
  72 MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");
  73
  74 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
  75
  76 bool is_ath9k_unloaded;
  77
  78 #ifdef CONFIG_MAC80211_LEDS
  79 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
  80         { .throughput = 0 * 1024, .blink_time = 334 },
  81         { .throughput = 1 * 1024, .blink_time = 260 },
  82         { .throughput = 5 * 1024, .blink_time = 220 },
  83         { .throughput = 10 * 1024, .blink_time = 190 },
  84         { .throughput = 20 * 1024, .blink_time = 170 },
  85         { .throughput = 50 * 1024, .blink_time = 150 },
  86         { .throughput = 70 * 1024, .blink_time = 130 },
  87         { .throughput = 100 * 1024, .blink_time = 110 },
  88         { .throughput = 200 * 1024, .blink_time = 80 },
  89         { .throughput = 300 * 1024, .blink_time = 50 },
  90 };
  91 #endif
  92
  93 static void ath9k_deinit_softc(struct ath_softc *sc);
  94
  95 static void ath9k_op_ps_wakeup(struct ath_common *common)
  96 {
  97         ath9k_ps_wakeup((struct ath_softc *) common->priv);
  98 }
  99
 100 static void ath9k_op_ps_restore(struct ath_common *common)
 101 {
 102         ath9k_ps_restore((struct ath_softc *) common->priv);
 103 }
 104
 105 static struct ath_ps_ops ath9k_ps_ops = {
 106         .wakeup = ath9k_op_ps_wakeup,
 107         .restore = ath9k_op_ps_restore,
 108 };
 109
 110 /*
 111  * Read and write, they both share the same lock. We do this to serialize
 112  * reads and writes on Atheros 802.11n PCI devices only. This is required
 113  * as the FIFO on these devices can only accept sanely 2 requests.
 114  */
 115
 116 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
 117 {
 118         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 119         struct ath_common *common = ath9k_hw_common(ah);
 120         struct ath_softc *sc = (struct ath_softc *) common->priv;
 121
 122         if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
 123                 unsigned long flags;
 124                 spin_lock_irqsave(&sc->sc_serial_rw, flags);
 125                 iowrite32(val, sc->mem + reg_offset);
 126                 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
 127         } else
 128                 iowrite32(val, sc->mem + reg_offset);
 129 }
 130
 131 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
 132 {
 133         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 134         struct ath_common *common = ath9k_hw_common(ah);
 135         struct ath_softc *sc = (struct ath_softc *) common->priv;
 136         u32 val;
 137
 138         if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
 139                 unsigned long flags;
 140                 spin_lock_irqsave(&sc->sc_serial_rw, flags);
 141                 val = ioread32(sc->mem + reg_offset);
 142                 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
 143         } else
 144                 val = ioread32(sc->mem + reg_offset);
 145         return val;
 146 }
 147
 148 static void ath9k_multi_ioread32(void *hw_priv, u32 *addr,
 149                                 u32 *val, u16 count)
 150 {
 151         int i;
 152
 153         for (i = 0; i < count; i++)
 154                 val[i] = ath9k_ioread32(hw_priv, addr[i]);
 155 }
 156
 157
 158 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
 159                                     u32 set, u32 clr)
 160 {
 161         u32 val;
 162
 163         val = ioread32(sc->mem + reg_offset);
 164         val &= ~clr;
 165         val |= set;
 166         iowrite32(val, sc->mem + reg_offset);
 167
 168         return val;
 169 }
 170
 171 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
 172 {
 173         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 174         struct ath_common *common = ath9k_hw_common(ah);
 175         struct ath_softc *sc = (struct ath_softc *) common->priv;
 176         unsigned long uninitialized_var(flags);
 177         u32 val;
 178
 179         if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
 180                 spin_lock_irqsave(&sc->sc_serial_rw, flags);
 181                 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
 182                 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
 183         } else
 184                 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
 185
 186         return val;
 187 }
 188
 189 /**************************/
 190 /*     Initialization     */
 191 /**************************/
 192
 193 static void ath9k_reg_notifier(struct wiphy *wiphy,
 194                                struct regulatory_request *request)
 195 {
 196         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
 197         struct ath_softc *sc = hw->priv;
 198         struct ath_hw *ah = sc->sc_ah;
 199         struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
 200
 201         ath_reg_notifier_apply(wiphy, request, reg);
 202
 203         /* Set tx power */
 204         if (!ah->curchan)
 205                 return;
 206
 207         sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;
 208         ath9k_ps_wakeup(sc);
 209         ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
 210         ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
 211                                sc->cur_chan->txpower,
 212                                &sc->cur_chan->cur_txpower);
 213         /* synchronize DFS detector if regulatory domain changed */
 214         if (sc->dfs_detector != NULL)
 215                 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
 216                                                  request->dfs_region);
 217         ath9k_ps_restore(sc);
 218 }
 219
 220 /*
 221  *  This function will allocate both the DMA descriptor structure, and the
 222  *  buffers it contains.  These are used to contain the descriptors used
 223  *  by the system.
 224 */
 225 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 226                       struct list_head *head, const char *name,
 227                       int nbuf, int ndesc, bool is_tx)
 228 {
 229         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 230         u8 *ds;
 231         int i, bsize, desc_len;
 232
 233         ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
 234                 name, nbuf, ndesc);
 235
 236         INIT_LIST_HEAD(head);
 237
 238         if (is_tx)
 239                 desc_len = sc->sc_ah->caps.tx_desc_len;
 240         else
 241                 desc_len = sizeof(struct ath_desc);
 242
 243         /* ath_desc must be a multiple of DWORDs */
 244         if ((desc_len % 4) != 0) {
 245                 ath_err(common, "ath_desc not DWORD aligned\n");
 246                 BUG_ON((desc_len % 4) != 0);
 247                 return -ENOMEM;
 248         }
 249
 250         dd->dd_desc_len = desc_len * nbuf * ndesc;
 251
 252         /*
 253          * Need additional DMA memory because we can't use
 254          * descriptors that cross the 4K page boundary. Assume
 255          * one skipped descriptor per 4K page.
 256          */
 257         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
 258                 u32 ndesc_skipped =
 259                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
 260                 u32 dma_len;
 261
 262                 while (ndesc_skipped) {
 263                         dma_len = ndesc_skipped * desc_len;
 264                         dd->dd_desc_len += dma_len;
 265
 266                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
 267                 }
 268         }
 269
 270         /* allocate descriptors */
 271         dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
 272                                           &dd->dd_desc_paddr, GFP_KERNEL);
 273         if (!dd->dd_desc)
 274                 return -ENOMEM;
 275
 276         ds = (u8 *) dd->dd_desc;
 277         ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
 278                 name, ds, (u32) dd->dd_desc_len,
 279                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
 280
 281         /* allocate buffers */
 282         if (is_tx) {
 283                 struct ath_buf *bf;
 284
 285                 bsize = sizeof(struct ath_buf) * nbuf;
 286                 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
 287                 if (!bf)
 288                         return -ENOMEM;
 289
 290                 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
 291                         bf->bf_desc = ds;
 292                         bf->bf_daddr = DS2PHYS(dd, ds);
 293
 294                         if (!(sc->sc_ah->caps.hw_caps &
 295                                   ATH9K_HW_CAP_4KB_SPLITTRANS)) {
 296                                 /*
 297                                  * Skip descriptor addresses which can cause 4KB
 298                                  * boundary crossing (addr + length) with a 32 dword
 299                                  * descriptor fetch.
 300                                  */
 301                                 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
 302                                         BUG_ON((caddr_t) bf->bf_desc >=
 303                                                    ((caddr_t) dd->dd_desc +
 304                                                 dd->dd_desc_len));
 305
 306                                         ds += (desc_len * ndesc);
 307                                         bf->bf_desc = ds;
 308                                         bf->bf_daddr = DS2PHYS(dd, ds);
 309                                 }
 310                         }
 311                         list_add_tail(&bf->list, head);
 312                 }
 313         } else {
 314                 struct ath_rxbuf *bf;
 315
 316                 bsize = sizeof(struct ath_rxbuf) * nbuf;
 317                 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
 318                 if (!bf)
 319                         return -ENOMEM;
 320
 321                 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
 322                         bf->bf_desc = ds;
 323                         bf->bf_daddr = DS2PHYS(dd, ds);
 324
 325                         if (!(sc->sc_ah->caps.hw_caps &
 326                                   ATH9K_HW_CAP_4KB_SPLITTRANS)) {
 327                                 /*
 328                                  * Skip descriptor addresses which can cause 4KB
 329                                  * boundary crossing (addr + length) with a 32 dword
 330                                  * descriptor fetch.
 331                                  */
 332                                 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
 333                                         BUG_ON((caddr_t) bf->bf_desc >=
 334                                                    ((caddr_t) dd->dd_desc +
 335                                                 dd->dd_desc_len));
 336
 337                                         ds += (desc_len * ndesc);
 338                                         bf->bf_desc = ds;
 339                                         bf->bf_daddr = DS2PHYS(dd, ds);
 340                                 }
 341                         }
 342                         list_add_tail(&bf->list, head);
 343                 }
 344         }
 345         return 0;
 346 }
 347
 348 static int ath9k_init_queues(struct ath_softc *sc)
 349 {
 350         int i = 0;
 351
 352         sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
 353         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
 354         ath_cabq_update(sc);
 355
 356         sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
 357
 358         for (i = 0; i < IEEE80211_NUM_ACS; i++) {
 359                 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
 360                 sc->tx.txq_map[i]->mac80211_qnum = i;
 361                 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
 362         }
 363         return 0;
 364 }
 365
 366 static void ath9k_init_misc(struct ath_softc *sc)
 367 {
 368         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 369         int i = 0;
 370
 371         setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
 372
 373         common->last_rssi = ATH_RSSI_DUMMY_MARKER;
 374         memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
 375         sc->beacon.slottime = ATH9K_SLOT_TIME_9;
 376
 377         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
 378                 sc->beacon.bslot[i] = NULL;
 379
 380         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
 381                 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
 382
 383         sc->spec_priv.ah = sc->sc_ah;
 384         sc->spec_priv.spec_config.enabled = 0;
 385         sc->spec_priv.spec_config.short_repeat = true;
 386         sc->spec_priv.spec_config.count = 8;
 387         sc->spec_priv.spec_config.endless = false;
 388         sc->spec_priv.spec_config.period = 0xFF;
 389         sc->spec_priv.spec_config.fft_period = 0xF;
 390 }
 391
 392 static void ath9k_init_pcoem_platform(struct ath_softc *sc)
 393 {
 394         struct ath_hw *ah = sc->sc_ah;
 395         struct ath9k_hw_capabilities *pCap = &ah->caps;
 396         struct ath_common *common = ath9k_hw_common(ah);
 397
 398         if (!IS_ENABLED(CONFIG_ATH9K_PCOEM))
 399                 return;
 400
 401         if (common->bus_ops->ath_bus_type != ATH_PCI)
 402                 return;
 403
 404         if (sc->driver_data & (ATH9K_PCI_CUS198 |
 405                                ATH9K_PCI_CUS230)) {
 406                 ah->config.xlna_gpio = 9;
 407                 ah->config.xatten_margin_cfg = true;
 408                 ah->config.alt_mingainidx = true;
 409                 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
 410                 sc->ant_comb.low_rssi_thresh = 20;
 411                 sc->ant_comb.fast_div_bias = 3;
 412
 413                 ath_info(common, "Set parameters for %s\n",
 414                          (sc->driver_data & ATH9K_PCI_CUS198) ?
 415                          "CUS198" : "CUS230");
 416         }
 417
 418         if (sc->driver_data & ATH9K_PCI_CUS217)
 419                 ath_info(common, "CUS217 card detected\n");
 420
 421         if (sc->driver_data & ATH9K_PCI_CUS252)
 422                 ath_info(common, "CUS252 card detected\n");
 423
 424         if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
 425                 ath_info(common, "WB335 1-ANT card detected\n");
 426
 427         if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
 428                 ath_info(common, "WB335 2-ANT card detected\n");
 429
 430         if (sc->driver_data & ATH9K_PCI_KILLER)
 431                 ath_info(common, "Killer Wireless card detected\n");
 432
 433         /*
 434          * Some WB335 cards do not support antenna diversity. Since
 435          * we use a hardcoded value for AR9565 instead of using the
 436          * EEPROM/OTP data, remove the combining feature from
 437          * the HW capabilities bitmap.
 438          */
 439         if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
 440                 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
 441                         pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
 442         }
 443
 444         if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
 445                 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
 446                 ath_info(common, "Set BT/WLAN RX diversity capability\n");
 447         }
 448
 449         if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
 450                 ah->config.pcie_waen = 0x0040473b;
 451                 ath_info(common, "Enable WAR for ASPM D3/L1\n");
 452         }
 453
 454         /*
 455          * The default value of pll_pwrsave is 1.
 456          * For certain AR9485 cards, it is set to 0.
 457          * For AR9462, AR9565 it's set to 7.
 458          */
 459         ah->config.pll_pwrsave = 1;
 460
 461         if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
 462                 ah->config.pll_pwrsave = 0;
 463                 ath_info(common, "Disable PLL PowerSave\n");
 464         }
 465
 466         if (sc->driver_data & ATH9K_PCI_LED_ACT_HI)
 467                 ah->config.led_active_high = true;
 468 }
 469
 470 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
 471                                     void *ctx)
 472 {
 473         struct ath9k_eeprom_ctx *ec = ctx;
 474
 475         if (eeprom_blob)
 476                 ec->ah->eeprom_blob = eeprom_blob;
 477
 478         complete(&ec->complete);
 479 }
 480
 481 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
 482 {
 483         struct ath9k_eeprom_ctx ec;
 484         struct ath_hw *ah = ah = sc->sc_ah;
 485         int err;
 486
 487         /* try to load the EEPROM content asynchronously */
 488         init_completion(&ec.complete);
 489         ec.ah = sc->sc_ah;
 490
 491         err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
 492                                       &ec, ath9k_eeprom_request_cb);
 493         if (err < 0) {
 494                 ath_err(ath9k_hw_common(ah),
 495                         "EEPROM request failed\n");
 496                 return err;
 497         }
 498
 499         wait_for_completion(&ec.complete);
 500
 501         if (!ah->eeprom_blob) {
 502                 ath_err(ath9k_hw_common(ah),
 503                         "Unable to load EEPROM file %s\n", name);
 504                 return -EINVAL;
 505         }
 506
 507         return 0;
 508 }
 509
 510 static void ath9k_eeprom_release(struct ath_softc *sc)
 511 {
 512         release_firmware(sc->sc_ah->eeprom_blob);
 513 }
 514
 515 static int ath9k_init_soc_platform(struct ath_softc *sc)
 516 {
 517         struct ath9k_platform_data *pdata = sc->dev->platform_data;
 518         struct ath_hw *ah = sc->sc_ah;
 519         int ret = 0;
 520
 521         if (!pdata)
 522                 return 0;
 523
 524         if (pdata->eeprom_name) {
 525                 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
 526                 if (ret)
 527                         return ret;
 528         }
 529
 530         if (pdata->tx_gain_buffalo)
 531                 ah->config.tx_gain_buffalo = true;
 532
 533         return ret;
 534 }
 535
 536 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
 537                             const struct ath_bus_ops *bus_ops)
 538 {
 539         struct ath9k_platform_data *pdata = sc->dev->platform_data;
 540         struct ath_hw *ah = NULL;
 541         struct ath9k_hw_capabilities *pCap;
 542         struct ath_common *common;
 543         int ret = 0, i;
 544         int csz = 0;
 545
 546         ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
 547         if (!ah)
 548                 return -ENOMEM;
 549
 550         ah->dev = sc->dev;
 551         ah->hw = sc->hw;
 552         ah->hw_version.devid = devid;
 553         ah->reg_ops.read = ath9k_ioread32;
 554         ah->reg_ops.multi_read = ath9k_multi_ioread32;
 555         ah->reg_ops.write = ath9k_iowrite32;
 556         ah->reg_ops.rmw = ath9k_reg_rmw;
 557         pCap = &ah->caps;
 558
 559         common = ath9k_hw_common(ah);
 560
 561         /* Will be cleared in ath9k_start() */
 562         set_bit(ATH_OP_INVALID, &common->op_flags);
 563
 564         sc->sc_ah = ah;
 565         sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
 566         sc->tx99_power = MAX_RATE_POWER + 1;
 567         init_waitqueue_head(&sc->tx_wait);
 568         sc->cur_chan = &sc->chanctx[0];
 569         if (!ath9k_is_chanctx_enabled())
 570                 sc->cur_chan->hw_queue_base = 0;
 571
 572         if (!pdata || pdata->use_eeprom) {
 573                 ah->ah_flags |= AH_USE_EEPROM;
 574                 sc->sc_ah->led_pin = -1;
 575         } else {
 576                 sc->sc_ah->gpio_mask = pdata->gpio_mask;
 577                 sc->sc_ah->gpio_val = pdata->gpio_val;
 578                 sc->sc_ah->led_pin = pdata->led_pin;
 579                 ah->is_clk_25mhz = pdata->is_clk_25mhz;
 580                 ah->get_mac_revision = pdata->get_mac_revision;
 581                 ah->external_reset = pdata->external_reset;
 582                 ah->disable_2ghz = pdata->disable_2ghz;
 583                 ah->disable_5ghz = pdata->disable_5ghz;
 584                 if (!pdata->endian_check)
 585                         ah->ah_flags |= AH_NO_EEP_SWAP;
 586         }
 587
 588         common->ops = &ah->reg_ops;
 589         common->bus_ops = bus_ops;
 590         common->ps_ops = &ath9k_ps_ops;
 591         common->ah = ah;
 592         common->hw = sc->hw;
 593         common->priv = sc;
 594         common->debug_mask = ath9k_debug;
 595         common->btcoex_enabled = ath9k_btcoex_enable == 1;
 596         common->disable_ani = false;
 597
 598         /*
 599          * Platform quirks.
 600          */
 601         ath9k_init_pcoem_platform(sc);
 602
 603         ret = ath9k_init_soc_platform(sc);
 604         if (ret)
 605                 return ret;
 606
 607         if (ath9k_led_active_high != -1)
 608                 ah->config.led_active_high = ath9k_led_active_high == 1;
 609
 610         /*
 611          * Enable WLAN/BT RX Antenna diversity only when:
 612          *
 613          * - BTCOEX is disabled.
 614          * - the user manually requests the feature.
 615          * - the HW cap is set using the platform data.
 616          */
 617         if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
 618             (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
 619                 common->bt_ant_diversity = 1;
 620
 621         spin_lock_init(&common->cc_lock);
 622         spin_lock_init(&sc->sc_serial_rw);
 623         spin_lock_init(&sc->sc_pm_lock);
 624         spin_lock_init(&sc->chan_lock);
 625         mutex_init(&sc->mutex);
 626         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
 627         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
 628                      (unsigned long)sc);
 629
 630         setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
 631         INIT_WORK(&sc->hw_reset_work, ath_reset_work);
 632         INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
 633         INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
 634
 635         ath9k_init_channel_context(sc);
 636
 637         /*
 638          * Cache line size is used to size and align various
 639          * structures used to communicate with the hardware.
 640          */
 641         ath_read_cachesize(common, &csz);
 642         common->cachelsz = csz << 2; /* convert to bytes */
 643
 644         /* Initializes the hardware for all supported chipsets */
 645         ret = ath9k_hw_init(ah);
 646         if (ret)
 647                 goto err_hw;
 648
 649         if (pdata && pdata->macaddr)
 650                 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
 651
 652         ret = ath9k_init_queues(sc);
 653         if (ret)
 654                 goto err_queues;
 655
 656         ret =  ath9k_init_btcoex(sc);
 657         if (ret)
 658                 goto err_btcoex;
 659
 660         ret = ath9k_cmn_init_channels_rates(common);
 661         if (ret)
 662                 goto err_btcoex;
 663
 664         ret = ath9k_init_p2p(sc);
 665         if (ret)
 666                 goto err_btcoex;
 667
 668         ath9k_cmn_init_crypto(sc->sc_ah);
 669         ath9k_init_misc(sc);
 670         ath_fill_led_pin(sc);
 671         ath_chanctx_init(sc);
 672         ath9k_offchannel_init(sc);
 673
 674         if (common->bus_ops->aspm_init)
 675                 common->bus_ops->aspm_init(common);
 676
 677         return 0;
 678
 679 err_btcoex:
 680         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
 681                 if (ATH_TXQ_SETUP(sc, i))
 682                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
 683 err_queues:
 684         ath9k_hw_deinit(ah);
 685 err_hw:
 686         ath9k_eeprom_release(sc);
 687         dev_kfree_skb_any(sc->tx99_skb);
 688         return ret;
 689 }
 690
 691 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
 692 {
 693         struct ieee80211_supported_band *sband;
 694         struct ieee80211_channel *chan;
 695         struct ath_hw *ah = sc->sc_ah;
 696         struct ath_common *common = ath9k_hw_common(ah);
 697         struct cfg80211_chan_def chandef;
 698         int i;
 699
 700         sband = &common->sbands[band];
 701         for (i = 0; i < sband->n_channels; i++) {
 702                 chan = &sband->channels[i];
 703                 ah->curchan = &ah->channels[chan->hw_value];
 704                 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
 705                 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
 706                 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
 707         }
 708 }
 709
 710 static void ath9k_init_txpower_limits(struct ath_softc *sc)
 711 {
 712         struct ath_hw *ah = sc->sc_ah;
 713         struct ath9k_channel *curchan = ah->curchan;
 714
 715         if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 716                 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
 717         if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 718                 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
 719
 720         ah->curchan = curchan;
 721 }
 722
 723 static const struct ieee80211_iface_limit if_limits[] = {
 724         { .max = 2048,  .types = BIT(NL80211_IFTYPE_STATION) },
 725         { .max = 8,     .types =
 726 #ifdef CONFIG_MAC80211_MESH
 727                                  BIT(NL80211_IFTYPE_MESH_POINT) |
 728 #endif
 729                                  BIT(NL80211_IFTYPE_AP) },
 730         { .max = 1,     .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
 731                                  BIT(NL80211_IFTYPE_P2P_GO) },
 732 };
 733
 734 static const struct ieee80211_iface_limit wds_limits[] = {
 735         { .max = 2048,  .types = BIT(NL80211_IFTYPE_WDS) },
 736 };
 737
 738 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
 739
 740 static const struct ieee80211_iface_limit if_limits_multi[] = {
 741         { .max = 2,     .types = BIT(NL80211_IFTYPE_STATION) |
 742                                  BIT(NL80211_IFTYPE_AP) |
 743                                  BIT(NL80211_IFTYPE_P2P_CLIENT) |
 744                                  BIT(NL80211_IFTYPE_P2P_GO) },
 745         { .max = 1,     .types = BIT(NL80211_IFTYPE_ADHOC) },
 746         { .max = 1,     .types = BIT(NL80211_IFTYPE_P2P_DEVICE) },
 747 };
 748
 749 static const struct ieee80211_iface_combination if_comb_multi[] = {
 750         {
 751                 .limits = if_limits_multi,
 752                 .n_limits = ARRAY_SIZE(if_limits_multi),
 753                 .max_interfaces = 3,
 754                 .num_different_channels = 2,
 755                 .beacon_int_infra_match = true,
 756         },
 757 };
 758
 759 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
 760
 761 static const struct ieee80211_iface_limit if_dfs_limits[] = {
 762         { .max = 1,     .types = BIT(NL80211_IFTYPE_AP) |
 763 #ifdef CONFIG_MAC80211_MESH
 764                                  BIT(NL80211_IFTYPE_MESH_POINT) |
 765 #endif
 766                                  BIT(NL80211_IFTYPE_ADHOC) },
 767 };
 768
 769 static const struct ieee80211_iface_combination if_comb[] = {
 770         {
 771                 .limits = if_limits,
 772                 .n_limits = ARRAY_SIZE(if_limits),
 773                 .max_interfaces = 2048,
 774                 .num_different_channels = 1,
 775                 .beacon_int_infra_match = true,
 776         },
 777         {
 778                 .limits = wds_limits,
 779                 .n_limits = ARRAY_SIZE(wds_limits),
 780                 .max_interfaces = 2048,
 781                 .num_different_channels = 1,
 782                 .beacon_int_infra_match = true,
 783         },
 784 #ifdef CONFIG_ATH9K_DFS_CERTIFIED
 785         {
 786                 .limits = if_dfs_limits,
 787                 .n_limits = ARRAY_SIZE(if_dfs_limits),
 788                 .max_interfaces = 1,
 789                 .num_different_channels = 1,
 790                 .beacon_int_infra_match = true,
 791                 .radar_detect_widths =  BIT(NL80211_CHAN_WIDTH_20_NOHT) |
 792                                         BIT(NL80211_CHAN_WIDTH_20) |
 793                                         BIT(NL80211_CHAN_WIDTH_40),
 794         }
 795 #endif
 796 };
 797
 798 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
 799 static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
 800 {
 801         struct ath_hw *ah = sc->sc_ah;
 802         struct ath_common *common = ath9k_hw_common(ah);
 803
 804         if (!ath9k_is_chanctx_enabled())
 805                 return;
 806
 807         ieee80211_hw_set(hw, QUEUE_CONTROL);
 808         hw->queues = ATH9K_NUM_TX_QUEUES;
 809         hw->offchannel_tx_hw_queue = hw->queues - 1;
 810         hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS);
 811         hw->wiphy->iface_combinations = if_comb_multi;
 812         hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);
 813         hw->wiphy->max_scan_ssids = 255;
 814         hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
 815         hw->wiphy->max_remain_on_channel_duration = 10000;
 816         hw->chanctx_data_size = sizeof(void *);
 817         hw->extra_beacon_tailroom =
 818                 sizeof(struct ieee80211_p2p_noa_attr) + 9;
 819
 820         ath_dbg(common, CHAN_CTX, "Use channel contexts\n");
 821 }
 822 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
 823
 824 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
 825 {
 826         struct ath_hw *ah = sc->sc_ah;
 827         struct ath_common *common = ath9k_hw_common(ah);
 828
 829         ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
 830         ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
 831         ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
 832         ieee80211_hw_set(hw, SPECTRUM_MGMT);
 833         ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
 834         ieee80211_hw_set(hw, SIGNAL_DBM);
 835         ieee80211_hw_set(hw, RX_INCLUDES_FCS);
 836         ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
 837         ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
 838
 839         if (ath9k_ps_enable)
 840                 ieee80211_hw_set(hw, SUPPORTS_PS);
 841
 842         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
 843                 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
 844
 845                 if (AR_SREV_9280_20_OR_LATER(ah))
 846                         hw->radiotap_mcs_details |=
 847                                 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
 848         }
 849
 850         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
 851                 ieee80211_hw_set(hw, MFP_CAPABLE);
 852
 853         hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |
 854                                NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |
 855                                NL80211_FEATURE_P2P_GO_CTWIN;
 856
 857         if (!config_enabled(CONFIG_ATH9K_TX99)) {
 858                 hw->wiphy->interface_modes =
 859                         BIT(NL80211_IFTYPE_P2P_GO) |
 860                         BIT(NL80211_IFTYPE_P2P_CLIENT) |
 861                         BIT(NL80211_IFTYPE_AP) |
 862                         BIT(NL80211_IFTYPE_STATION) |
 863                         BIT(NL80211_IFTYPE_ADHOC) |
 864                         BIT(NL80211_IFTYPE_MESH_POINT) |
 865                         BIT(NL80211_IFTYPE_WDS) |
 866                         BIT(NL80211_IFTYPE_OCB);
 867
 868                 if (ath9k_is_chanctx_enabled())
 869                         hw->wiphy->interface_modes |=
 870                                         BIT(NL80211_IFTYPE_P2P_DEVICE);
 871
 872                 hw->wiphy->iface_combinations = if_comb;
 873                 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
 874         }
 875
 876         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
 877
 878         hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
 879         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
 880         hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
 881         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
 882         hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
 883         hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
 884
 885         hw->queues = 4;
 886         hw->max_rates = 4;
 887         hw->max_listen_interval = 10;
 888         hw->max_rate_tries = 10;
 889         hw->sta_data_size = sizeof(struct ath_node);
 890         hw->vif_data_size = sizeof(struct ath_vif);
 891         hw->extra_tx_headroom = 4;
 892
 893         hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
 894         hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
 895
 896         /* single chain devices with rx diversity */
 897         if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
 898                 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
 899
 900         sc->ant_rx = hw->wiphy->available_antennas_rx;
 901         sc->ant_tx = hw->wiphy->available_antennas_tx;
 902
 903         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 904                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
 905                         &common->sbands[IEEE80211_BAND_2GHZ];
 906         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 907                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
 908                         &common->sbands[IEEE80211_BAND_5GHZ];
 909
 910 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
 911         ath9k_set_mcc_capab(sc, hw);
 912 #endif
 913         ath9k_init_wow(hw);
 914         ath9k_cmn_reload_chainmask(ah);
 915
 916         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
 917 }
 918
 919 int ath9k_init_device(u16 devid, struct ath_softc *sc,
 920                     const struct ath_bus_ops *bus_ops)
 921 {
 922         struct ieee80211_hw *hw = sc->hw;
 923         struct ath_common *common;
 924         struct ath_hw *ah;
 925         int error = 0;
 926         struct ath_regulatory *reg;
 927
 928         /* Bring up device */
 929         error = ath9k_init_softc(devid, sc, bus_ops);
 930         if (error)
 931                 return error;
 932
 933         ah = sc->sc_ah;
 934         common = ath9k_hw_common(ah);
 935         ath9k_set_hw_capab(sc, hw);
 936
 937         /* Initialize regulatory */
 938         error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
 939                               ath9k_reg_notifier);
 940         if (error)
 941                 goto deinit;
 942
 943         reg = &common->regulatory;
 944
 945         /* Setup TX DMA */
 946         error = ath_tx_init(sc, ATH_TXBUF);
 947         if (error != 0)
 948                 goto deinit;
 949
 950         /* Setup RX DMA */
 951         error = ath_rx_init(sc, ATH_RXBUF);
 952         if (error != 0)
 953                 goto deinit;
 954
 955         ath9k_init_txpower_limits(sc);
 956
 957 #ifdef CONFIG_MAC80211_LEDS
 958         /* must be initialized before ieee80211_register_hw */
 959         sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
 960                 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
 961                 ARRAY_SIZE(ath9k_tpt_blink));
 962 #endif
 963
 964         /* Register with mac80211 */
 965         error = ieee80211_register_hw(hw);
 966         if (error)
 967                 goto rx_cleanup;
 968
 969         error = ath9k_init_debug(ah);
 970         if (error) {
 971                 ath_err(common, "Unable to create debugfs files\n");
 972                 goto unregister;
 973         }
 974
 975         /* Handle world regulatory */
 976         if (!ath_is_world_regd(reg)) {
 977                 error = regulatory_hint(hw->wiphy, reg->alpha2);
 978                 if (error)
 979                         goto debug_cleanup;
 980         }
 981
 982         ath_init_leds(sc);
 983         ath_start_rfkill_poll(sc);
 984
 985         return 0;
 986
 987 debug_cleanup:
 988         ath9k_deinit_debug(sc);
 989 unregister:
 990         ieee80211_unregister_hw(hw);
 991 rx_cleanup:
 992         ath_rx_cleanup(sc);
 993 deinit:
 994         ath9k_deinit_softc(sc);
 995         return error;
 996 }
 997
 998 /*****************************/
 999 /*     De-Initialization     */
1000 /*****************************/
1001
1002 static void ath9k_deinit_softc(struct ath_softc *sc)
1003 {
1004         int i = 0;
1005
1006         ath9k_deinit_p2p(sc);
1007         ath9k_deinit_btcoex(sc);
1008
1009         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1010                 if (ATH_TXQ_SETUP(sc, i))
1011                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1012
1013         del_timer_sync(&sc->sleep_timer);
1014         ath9k_hw_deinit(sc->sc_ah);
1015         if (sc->dfs_detector != NULL)
1016                 sc->dfs_detector->exit(sc->dfs_detector);
1017
1018         ath9k_eeprom_release(sc);
1019 }
1020
1021 void ath9k_deinit_device(struct ath_softc *sc)
1022 {
1023         struct ieee80211_hw *hw = sc->hw;
1024
1025         ath9k_ps_wakeup(sc);
1026
1027         wiphy_rfkill_stop_polling(sc->hw->wiphy);
1028         ath_deinit_leds(sc);
1029
1030         ath9k_ps_restore(sc);
1031
1032         ath9k_deinit_debug(sc);
1033         ath9k_deinit_wow(hw);
1034         ieee80211_unregister_hw(hw);
1035         ath_rx_cleanup(sc);
1036         ath9k_deinit_softc(sc);
1037 }
1038
1039 /************************/
1040 /*     Module Hooks     */
1041 /************************/
1042
1043 static int __init ath9k_init(void)
1044 {
1045         int error;
1046
1047         error = ath_pci_init();
1048         if (error < 0) {
1049                 pr_err("No PCI devices found, driver not installed\n");
1050                 error = -ENODEV;
1051                 goto err_out;
1052         }
1053
1054         error = ath_ahb_init();
1055         if (error < 0) {
1056                 error = -ENODEV;
1057                 goto err_pci_exit;
1058         }
1059
1060         return 0;
1061
1062  err_pci_exit:
1063         ath_pci_exit();
1064  err_out:
1065         return error;
1066 }
1067 module_init(ath9k_init);
1068
1069 static void __exit ath9k_exit(void)
1070 {
1071         is_ath9k_unloaded = true;
1072         ath_ahb_exit();
1073         ath_pci_exit();
1074         pr_info("%s: Driver unloaded\n", dev_info);
1075 }
1076 module_exit(ath9k_exit);