kernel/drivers/net/wireless/ath/ath9k/eeprom_def.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <asm/unaligned.h>
  18 #include "hw.h"
  19 #include "ar9002_phy.h"
  20
  21 static void ath9k_get_txgain_index(struct ath_hw *ah,
  22                 struct ath9k_channel *chan,
  23                 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
  24                 u8 *calChans,  u16 availPiers, u8 *pwr, u8 *pcdacIdx)
  25 {
  26         u8 pcdac, i = 0;
  27         u16 idxL = 0, idxR = 0, numPiers;
  28         bool match;
  29         struct chan_centers centers;
  30
  31         ath9k_hw_get_channel_centers(ah, chan, &centers);
  32
  33         for (numPiers = 0; numPiers < availPiers; numPiers++)
  34                 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
  35                         break;
  36
  37         match = ath9k_hw_get_lower_upper_index(
  38                         (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
  39                         calChans, numPiers, &idxL, &idxR);
  40         if (match) {
  41                 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
  42                 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
  43         } else {
  44                 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
  45                 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
  46                                 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
  47         }
  48
  49         while (pcdac > ah->originalGain[i] &&
  50                         i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
  51                 i++;
  52
  53         *pcdacIdx = i;
  54 }
  55
  56 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
  57                                 u32 initTxGain,
  58                                 int txPower,
  59                                 u8 *pPDADCValues)
  60 {
  61         u32 i;
  62         u32 offset;
  63
  64         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
  65                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
  66         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
  67                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
  68
  69         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
  70                         AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
  71
  72         offset = txPower;
  73         for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
  74                 if (i < offset)
  75                         pPDADCValues[i] = 0x0;
  76                 else
  77                         pPDADCValues[i] = 0xFF;
  78 }
  79
  80 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
  81 {
  82         return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
  83 }
  84
  85 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
  86 {
  87         return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
  88 }
  89
  90 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
  91
  92 static bool __ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
  93 {
  94         u16 *eep_data = (u16 *)&ah->eeprom.def;
  95         int addr, ar5416_eep_start_loc = 0x100;
  96
  97         for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
  98                 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
  99                                          eep_data))
 100                         return false;
 101                 eep_data++;
 102         }
 103         return true;
 104 }
 105
 106 static bool __ath9k_hw_usb_def_fill_eeprom(struct ath_hw *ah)
 107 {
 108         u16 *eep_data = (u16 *)&ah->eeprom.def;
 109
 110         ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
 111                                      0x100, SIZE_EEPROM_DEF);
 112         return true;
 113 }
 114
 115 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
 116 {
 117         struct ath_common *common = ath9k_hw_common(ah);
 118
 119         if (!ath9k_hw_use_flash(ah)) {
 120                 ath_dbg(common, EEPROM, "Reading from EEPROM, not flash\n");
 121         }
 122
 123         if (common->bus_ops->ath_bus_type == ATH_USB)
 124                 return __ath9k_hw_usb_def_fill_eeprom(ah);
 125         else
 126                 return __ath9k_hw_def_fill_eeprom(ah);
 127 }
 128
 129 #undef SIZE_EEPROM_DEF
 130
 131 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
 132 static u32 ath9k_def_dump_modal_eeprom(char *buf, u32 len, u32 size,
 133                                        struct modal_eep_header *modal_hdr)
 134 {
 135         PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
 136         PR_EEP("Chain1 Ant. Control", modal_hdr->antCtrlChain[1]);
 137         PR_EEP("Chain2 Ant. Control", modal_hdr->antCtrlChain[2]);
 138         PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
 139         PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
 140         PR_EEP("Chain1 Ant. Gain", modal_hdr->antennaGainCh[1]);
 141         PR_EEP("Chain2 Ant. Gain", modal_hdr->antennaGainCh[2]);
 142         PR_EEP("Switch Settle", modal_hdr->switchSettling);
 143         PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
 144         PR_EEP("Chain1 TxRxAtten", modal_hdr->txRxAttenCh[1]);
 145         PR_EEP("Chain2 TxRxAtten", modal_hdr->txRxAttenCh[2]);
 146         PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
 147         PR_EEP("Chain1 RxTxMargin", modal_hdr->rxTxMarginCh[1]);
 148         PR_EEP("Chain2 RxTxMargin", modal_hdr->rxTxMarginCh[2]);
 149         PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
 150         PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize);
 151         PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]);
 152         PR_EEP("Chain1 xlna Gain", modal_hdr->xlnaGainCh[1]);
 153         PR_EEP("Chain2 xlna Gain", modal_hdr->xlnaGainCh[2]);
 154         PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
 155         PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
 156         PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
 157         PR_EEP("CCA Threshold)", modal_hdr->thresh62);
 158         PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
 159         PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
 160         PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
 161         PR_EEP("xpdGain", modal_hdr->xpdGain);
 162         PR_EEP("External PD", modal_hdr->xpd);
 163         PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
 164         PR_EEP("Chain1 I Coefficient", modal_hdr->iqCalICh[1]);
 165         PR_EEP("Chain2 I Coefficient", modal_hdr->iqCalICh[2]);
 166         PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
 167         PR_EEP("Chain1 Q Coefficient", modal_hdr->iqCalQCh[1]);
 168         PR_EEP("Chain2 Q Coefficient", modal_hdr->iqCalQCh[2]);
 169         PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
 170         PR_EEP("Chain0 OutputBias", modal_hdr->ob);
 171         PR_EEP("Chain0 DriverBias", modal_hdr->db);
 172         PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
 173         PR_EEP("2chain pwr decrease", modal_hdr->pwrDecreaseFor2Chain);
 174         PR_EEP("3chain pwr decrease", modal_hdr->pwrDecreaseFor3Chain);
 175         PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
 176         PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
 177         PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
 178         PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
 179         PR_EEP("Chain1 bswAtten", modal_hdr->bswAtten[1]);
 180         PR_EEP("Chain2 bswAtten", modal_hdr->bswAtten[2]);
 181         PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
 182         PR_EEP("Chain1 bswMargin", modal_hdr->bswMargin[1]);
 183         PR_EEP("Chain2 bswMargin", modal_hdr->bswMargin[2]);
 184         PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
 185         PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]);
 186         PR_EEP("Chain1 xatten2Db", modal_hdr->xatten2Db[1]);
 187         PR_EEP("Chain2 xatten2Db", modal_hdr->xatten2Db[2]);
 188         PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]);
 189         PR_EEP("Chain1 xatten2Margin", modal_hdr->xatten2Margin[1]);
 190         PR_EEP("Chain2 xatten2Margin", modal_hdr->xatten2Margin[2]);
 191         PR_EEP("Chain1 OutputBias", modal_hdr->ob_ch1);
 192         PR_EEP("Chain1 DriverBias", modal_hdr->db_ch1);
 193         PR_EEP("LNA Control", modal_hdr->lna_ctl);
 194         PR_EEP("XPA Bias Freq0", modal_hdr->xpaBiasLvlFreq[0]);
 195         PR_EEP("XPA Bias Freq1", modal_hdr->xpaBiasLvlFreq[1]);
 196         PR_EEP("XPA Bias Freq2", modal_hdr->xpaBiasLvlFreq[2]);
 197
 198         return len;
 199 }
 200
 201 static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
 202                                     u8 *buf, u32 len, u32 size)
 203 {
 204         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 205         struct base_eep_header *pBase = &eep->baseEepHeader;
 206
 207         if (!dump_base_hdr) {
 208                 len += scnprintf(buf + len, size - len,
 209                                  "%20s :\n", "2GHz modal Header");
 210                 len = ath9k_def_dump_modal_eeprom(buf, len, size,
 211                                                    &eep->modalHeader[0]);
 212                 len += scnprintf(buf + len, size - len,
 213                                  "%20s :\n", "5GHz modal Header");
 214                 len = ath9k_def_dump_modal_eeprom(buf, len, size,
 215                                                    &eep->modalHeader[1]);
 216                 goto out;
 217         }
 218
 219         PR_EEP("Major Version", pBase->version >> 12);
 220         PR_EEP("Minor Version", pBase->version & 0xFFF);
 221         PR_EEP("Checksum", pBase->checksum);
 222         PR_EEP("Length", pBase->length);
 223         PR_EEP("RegDomain1", pBase->regDmn[0]);
 224         PR_EEP("RegDomain2", pBase->regDmn[1]);
 225         PR_EEP("TX Mask", pBase->txMask);
 226         PR_EEP("RX Mask", pBase->rxMask);
 227         PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
 228         PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
 229         PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
 230                                         AR5416_OPFLAGS_N_2G_HT20));
 231         PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
 232                                         AR5416_OPFLAGS_N_2G_HT40));
 233         PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
 234                                         AR5416_OPFLAGS_N_5G_HT20));
 235         PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
 236                                         AR5416_OPFLAGS_N_5G_HT40));
 237         PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
 238         PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
 239         PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
 240         PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
 241         PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl);
 242
 243         len += scnprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
 244                          pBase->macAddr);
 245
 246 out:
 247         if (len > size)
 248                 len = size;
 249
 250         return len;
 251 }
 252 #else
 253 static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
 254                                     u8 *buf, u32 len, u32 size)
 255 {
 256         return 0;
 257 }
 258 #endif
 259
 260
 261 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
 262 {
 263         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 264         struct ath_common *common = ath9k_hw_common(ah);
 265         u16 *eepdata, temp, magic;
 266         u32 sum = 0, el;
 267         bool need_swap = false;
 268         int i, addr, size;
 269
 270         if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
 271                 ath_err(common, "Reading Magic # failed\n");
 272                 return false;
 273         }
 274
 275         if (swab16(magic) == AR5416_EEPROM_MAGIC &&
 276             !(ah->ah_flags & AH_NO_EEP_SWAP)) {
 277                 size = sizeof(struct ar5416_eeprom_def);
 278                 need_swap = true;
 279                 eepdata = (u16 *) (&ah->eeprom);
 280
 281                 for (addr = 0; addr < size / sizeof(u16); addr++) {
 282                         temp = swab16(*eepdata);
 283                         *eepdata = temp;
 284                         eepdata++;
 285                 }
 286         }
 287
 288         ath_dbg(common, EEPROM, "need_swap = %s\n",
 289                 need_swap ? "True" : "False");
 290
 291         if (need_swap)
 292                 el = swab16(ah->eeprom.def.baseEepHeader.length);
 293         else
 294                 el = ah->eeprom.def.baseEepHeader.length;
 295
 296         if (el > sizeof(struct ar5416_eeprom_def))
 297                 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
 298         else
 299                 el = el / sizeof(u16);
 300
 301         eepdata = (u16 *)(&ah->eeprom);
 302
 303         for (i = 0; i < el; i++)
 304                 sum ^= *eepdata++;
 305
 306         if (need_swap) {
 307                 u32 integer, j;
 308                 u16 word;
 309
 310                 ath_dbg(common, EEPROM,
 311                         "EEPROM Endianness is not native.. Changing.\n");
 312
 313                 word = swab16(eep->baseEepHeader.length);
 314                 eep->baseEepHeader.length = word;
 315
 316                 word = swab16(eep->baseEepHeader.checksum);
 317                 eep->baseEepHeader.checksum = word;
 318
 319                 word = swab16(eep->baseEepHeader.version);
 320                 eep->baseEepHeader.version = word;
 321
 322                 word = swab16(eep->baseEepHeader.regDmn[0]);
 323                 eep->baseEepHeader.regDmn[0] = word;
 324
 325                 word = swab16(eep->baseEepHeader.regDmn[1]);
 326                 eep->baseEepHeader.regDmn[1] = word;
 327
 328                 word = swab16(eep->baseEepHeader.rfSilent);
 329                 eep->baseEepHeader.rfSilent = word;
 330
 331                 word = swab16(eep->baseEepHeader.blueToothOptions);
 332                 eep->baseEepHeader.blueToothOptions = word;
 333
 334                 word = swab16(eep->baseEepHeader.deviceCap);
 335                 eep->baseEepHeader.deviceCap = word;
 336
 337                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
 338                         struct modal_eep_header *pModal =
 339                                 &eep->modalHeader[j];
 340                         integer = swab32(pModal->antCtrlCommon);
 341                         pModal->antCtrlCommon = integer;
 342
 343                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 344                                 integer = swab32(pModal->antCtrlChain[i]);
 345                                 pModal->antCtrlChain[i] = integer;
 346                         }
 347                         for (i = 0; i < 3; i++) {
 348                                 word = swab16(pModal->xpaBiasLvlFreq[i]);
 349                                 pModal->xpaBiasLvlFreq[i] = word;
 350                         }
 351
 352                         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 353                                 word = swab16(pModal->spurChans[i].spurChan);
 354                                 pModal->spurChans[i].spurChan = word;
 355                         }
 356                 }
 357         }
 358
 359         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 360             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 361                 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 362                         sum, ah->eep_ops->get_eeprom_ver(ah));
 363                 return -EINVAL;
 364         }
 365
 366         /* Enable fixup for AR_AN_TOP2 if necessary */
 367         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 368             ((eep->baseEepHeader.version & 0xff) > 0x0a) &&
 369             (eep->baseEepHeader.pwdclkind == 0))
 370                 ah->need_an_top2_fixup = true;
 371
 372         if ((common->bus_ops->ath_bus_type == ATH_USB) &&
 373             (AR_SREV_9280(ah)))
 374                 eep->modalHeader[0].xpaBiasLvl = 0;
 375
 376         return 0;
 377 }
 378
 379 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
 380                                    enum eeprom_param param)
 381 {
 382         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 383         struct modal_eep_header *pModal = eep->modalHeader;
 384         struct base_eep_header *pBase = &eep->baseEepHeader;
 385         int band = 0;
 386
 387         switch (param) {
 388         case EEP_NFTHRESH_5:
 389                 return pModal[0].noiseFloorThreshCh[0];
 390         case EEP_NFTHRESH_2:
 391                 return pModal[1].noiseFloorThreshCh[0];
 392         case EEP_MAC_LSW:
 393                 return get_unaligned_be16(pBase->macAddr);
 394         case EEP_MAC_MID:
 395                 return get_unaligned_be16(pBase->macAddr + 2);
 396         case EEP_MAC_MSW:
 397                 return get_unaligned_be16(pBase->macAddr + 4);
 398         case EEP_REG_0:
 399                 return pBase->regDmn[0];
 400         case EEP_OP_CAP:
 401                 return pBase->deviceCap;
 402         case EEP_OP_MODE:
 403                 return pBase->opCapFlags;
 404         case EEP_RF_SILENT:
 405                 return pBase->rfSilent;
 406         case EEP_OB_5:
 407                 return pModal[0].ob;
 408         case EEP_DB_5:
 409                 return pModal[0].db;
 410         case EEP_OB_2:
 411                 return pModal[1].ob;
 412         case EEP_DB_2:
 413                 return pModal[1].db;
 414         case EEP_MINOR_REV:
 415                 return AR5416_VER_MASK;
 416         case EEP_TX_MASK:
 417                 return pBase->txMask;
 418         case EEP_RX_MASK:
 419                 return pBase->rxMask;
 420         case EEP_FSTCLK_5G:
 421                 return pBase->fastClk5g;
 422         case EEP_RXGAIN_TYPE:
 423                 return pBase->rxGainType;
 424         case EEP_TXGAIN_TYPE:
 425                 return pBase->txGainType;
 426         case EEP_OL_PWRCTRL:
 427                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 428                         return pBase->openLoopPwrCntl ? true : false;
 429                 else
 430                         return false;
 431         case EEP_RC_CHAIN_MASK:
 432                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 433                         return pBase->rcChainMask;
 434                 else
 435                         return 0;
 436         case EEP_DAC_HPWR_5G:
 437                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
 438                         return pBase->dacHiPwrMode_5G;
 439                 else
 440                         return 0;
 441         case EEP_FRAC_N_5G:
 442                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
 443                         return pBase->frac_n_5g;
 444                 else
 445                         return 0;
 446         case EEP_PWR_TABLE_OFFSET:
 447                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
 448                         return pBase->pwr_table_offset;
 449                 else
 450                         return AR5416_PWR_TABLE_OFFSET_DB;
 451         case EEP_ANTENNA_GAIN_2G:
 452                 band = 1;
 453                 /* fall through */
 454         case EEP_ANTENNA_GAIN_5G:
 455                 return max_t(u8, max_t(u8,
 456                         pModal[band].antennaGainCh[0],
 457                         pModal[band].antennaGainCh[1]),
 458                         pModal[band].antennaGainCh[2]);
 459         default:
 460                 return 0;
 461         }
 462 }
 463
 464 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
 465                                   struct modal_eep_header *pModal,
 466                                   struct ar5416_eeprom_def *eep,
 467                                   u8 txRxAttenLocal, int regChainOffset, int i)
 468 {
 469         ENABLE_REG_RMW_BUFFER(ah);
 470         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
 471                 txRxAttenLocal = pModal->txRxAttenCh[i];
 472
 473                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 474                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 475                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 476                               pModal->bswMargin[i]);
 477                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 478                               AR_PHY_GAIN_2GHZ_XATTEN1_DB,
 479                               pModal->bswAtten[i]);
 480                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 481                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 482                               pModal->xatten2Margin[i]);
 483                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 484                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 485                               pModal->xatten2Db[i]);
 486                 } else {
 487                         REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 488                                 SM(pModal-> bswMargin[i], AR_PHY_GAIN_2GHZ_BSW_MARGIN),
 489                                 AR_PHY_GAIN_2GHZ_BSW_MARGIN);
 490                         REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 491                                 SM(pModal->bswAtten[i], AR_PHY_GAIN_2GHZ_BSW_ATTEN),
 492                                 AR_PHY_GAIN_2GHZ_BSW_ATTEN);
 493                 }
 494         }
 495
 496         if (AR_SREV_9280_20_OR_LATER(ah)) {
 497                 REG_RMW_FIELD(ah,
 498                       AR_PHY_RXGAIN + regChainOffset,
 499                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 500                 REG_RMW_FIELD(ah,
 501                       AR_PHY_RXGAIN + regChainOffset,
 502                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
 503         } else {
 504                 REG_RMW(ah, AR_PHY_RXGAIN + regChainOffset,
 505                         SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN),
 506                         AR_PHY_RXGAIN_TXRX_ATTEN);
 507                 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 508                         SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN),
 509                         AR_PHY_GAIN_2GHZ_RXTX_MARGIN);
 510         }
 511         REG_RMW_BUFFER_FLUSH(ah);
 512 }
 513
 514 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
 515                                           struct ath9k_channel *chan)
 516 {
 517         struct modal_eep_header *pModal;
 518         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 519         int i, regChainOffset;
 520         u8 txRxAttenLocal;
 521
 522         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 523         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
 524
 525         REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
 526
 527         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 528                 if (AR_SREV_9280(ah)) {
 529                         if (i >= 2)
 530                                 break;
 531                 }
 532
 533                 if ((ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
 534                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 535                 else
 536                         regChainOffset = i * 0x1000;
 537
 538                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
 539                           pModal->antCtrlChain[i]);
 540
 541                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
 542                           (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
 543                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 544                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 545                           SM(pModal->iqCalICh[i],
 546                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 547                           SM(pModal->iqCalQCh[i],
 548                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 549
 550                 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
 551                                       regChainOffset, i);
 552         }
 553
 554         if (AR_SREV_9280_20_OR_LATER(ah)) {
 555                 if (IS_CHAN_2GHZ(chan)) {
 556                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 557                                                   AR_AN_RF2G1_CH0_OB,
 558                                                   AR_AN_RF2G1_CH0_OB_S,
 559                                                   pModal->ob);
 560                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 561                                                   AR_AN_RF2G1_CH0_DB,
 562                                                   AR_AN_RF2G1_CH0_DB_S,
 563                                                   pModal->db);
 564                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 565                                                   AR_AN_RF2G1_CH1_OB,
 566                                                   AR_AN_RF2G1_CH1_OB_S,
 567                                                   pModal->ob_ch1);
 568                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 569                                                   AR_AN_RF2G1_CH1_DB,
 570                                                   AR_AN_RF2G1_CH1_DB_S,
 571                                                   pModal->db_ch1);
 572                 } else {
 573                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 574                                                   AR_AN_RF5G1_CH0_OB5,
 575                                                   AR_AN_RF5G1_CH0_OB5_S,
 576                                                   pModal->ob);
 577                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 578                                                   AR_AN_RF5G1_CH0_DB5,
 579                                                   AR_AN_RF5G1_CH0_DB5_S,
 580                                                   pModal->db);
 581                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 582                                                   AR_AN_RF5G1_CH1_OB5,
 583                                                   AR_AN_RF5G1_CH1_OB5_S,
 584                                                   pModal->ob_ch1);
 585                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 586                                                   AR_AN_RF5G1_CH1_DB5,
 587                                                   AR_AN_RF5G1_CH1_DB5_S,
 588                                                   pModal->db_ch1);
 589                 }
 590                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 591                                           AR_AN_TOP2_XPABIAS_LVL,
 592                                           AR_AN_TOP2_XPABIAS_LVL_S,
 593                                           pModal->xpaBiasLvl);
 594                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 595                                           AR_AN_TOP2_LOCALBIAS,
 596                                           AR_AN_TOP2_LOCALBIAS_S,
 597                                           !!(pModal->lna_ctl &
 598                                              LNA_CTL_LOCAL_BIAS));
 599                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
 600                               !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
 601         }
 602
 603         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
 604                       pModal->switchSettling);
 605         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
 606                       pModal->adcDesiredSize);
 607
 608         if (!AR_SREV_9280_20_OR_LATER(ah))
 609                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
 610                               AR_PHY_DESIRED_SZ_PGA,
 611                               pModal->pgaDesiredSize);
 612
 613         REG_WRITE(ah, AR_PHY_RF_CTL4,
 614                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
 615                   | SM(pModal->txEndToXpaOff,
 616                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
 617                   | SM(pModal->txFrameToXpaOn,
 618                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
 619                   | SM(pModal->txFrameToXpaOn,
 620                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 621
 622         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 623                       pModal->txEndToRxOn);
 624
 625         if (AR_SREV_9280_20_OR_LATER(ah)) {
 626                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
 627                               pModal->thresh62);
 628                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
 629                               AR_PHY_EXT_CCA0_THRESH62,
 630                               pModal->thresh62);
 631         } else {
 632                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
 633                               pModal->thresh62);
 634                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
 635                               AR_PHY_EXT_CCA_THRESH62,
 636                               pModal->thresh62);
 637         }
 638
 639         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
 640                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
 641                               AR_PHY_TX_END_DATA_START,
 642                               pModal->txFrameToDataStart);
 643                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
 644                               pModal->txFrameToPaOn);
 645         }
 646
 647         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
 648                 if (IS_CHAN_HT40(chan))
 649                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
 650                                       AR_PHY_SETTLING_SWITCH,
 651                                       pModal->swSettleHt40);
 652         }
 653
 654         if (AR_SREV_9280_20_OR_LATER(ah) &&
 655             AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 656                 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
 657                               AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
 658                               pModal->miscBits);
 659
 660
 661         if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
 662                 if (IS_CHAN_2GHZ(chan))
 663                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
 664                                         eep->baseEepHeader.dacLpMode);
 665                 else if (eep->baseEepHeader.dacHiPwrMode_5G)
 666                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
 667                 else
 668                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
 669                                       eep->baseEepHeader.dacLpMode);
 670
 671                 udelay(100);
 672
 673                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
 674                               pModal->miscBits >> 2);
 675
 676                 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
 677                               AR_PHY_TX_DESIRED_SCALE_CCK,
 678                               eep->baseEepHeader.desiredScaleCCK);
 679         }
 680 }
 681
 682 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
 683                                    struct ath9k_channel *chan)
 684 {
 685 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
 686         struct modal_eep_header *pModal;
 687         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 688         u8 biaslevel;
 689
 690         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
 691                 return;
 692
 693         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
 694                 return;
 695
 696         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 697
 698         if (pModal->xpaBiasLvl != 0xff) {
 699                 biaslevel = pModal->xpaBiasLvl;
 700         } else {
 701                 u16 resetFreqBin, freqBin, freqCount = 0;
 702                 struct chan_centers centers;
 703
 704                 ath9k_hw_get_channel_centers(ah, chan, &centers);
 705
 706                 resetFreqBin = FREQ2FBIN(centers.synth_center,
 707                                          IS_CHAN_2GHZ(chan));
 708                 freqBin = XPA_LVL_FREQ(0) & 0xff;
 709                 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
 710
 711                 freqCount++;
 712
 713                 while (freqCount < 3) {
 714                         if (XPA_LVL_FREQ(freqCount) == 0x0)
 715                                 break;
 716
 717                         freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
 718                         if (resetFreqBin >= freqBin)
 719                                 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
 720                         else
 721                                 break;
 722                         freqCount++;
 723                 }
 724         }
 725
 726         if (IS_CHAN_2GHZ(chan)) {
 727                 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
 728                                         7, 1) & (~0x18)) | biaslevel << 3;
 729         } else {
 730                 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
 731                                         6, 1) & (~0xc0)) | biaslevel << 6;
 732         }
 733 #undef XPA_LVL_FREQ
 734 }
 735
 736 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
 737                                 u16 *gb,
 738                                 u16 numXpdGain,
 739                                 u16 pdGainOverlap_t2,
 740                                 int8_t pwr_table_offset,
 741                                 int16_t *diff)
 742
 743 {
 744         u16 k;
 745
 746         /* Prior to writing the boundaries or the pdadc vs. power table
 747          * into the chip registers the default starting point on the pdadc
 748          * vs. power table needs to be checked and the curve boundaries
 749          * adjusted accordingly
 750          */
 751         if (AR_SREV_9280_20_OR_LATER(ah)) {
 752                 u16 gb_limit;
 753
 754                 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 755                         /* get the difference in dB */
 756                         *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
 757                         /* get the number of half dB steps */
 758                         *diff *= 2;
 759                         /* change the original gain boundary settings
 760                          * by the number of half dB steps
 761                          */
 762                         for (k = 0; k < numXpdGain; k++)
 763                                 gb[k] = (u16)(gb[k] - *diff);
 764                 }
 765                 /* Because of a hardware limitation, ensure the gain boundary
 766                  * is not larger than (63 - overlap)
 767                  */
 768                 gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
 769
 770                 for (k = 0; k < numXpdGain; k++)
 771                         gb[k] = (u16)min(gb_limit, gb[k]);
 772         }
 773
 774         return *diff;
 775 }
 776
 777 static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
 778                                       int8_t pwr_table_offset,
 779                                       int16_t diff,
 780                                       u8 *pdadcValues)
 781 {
 782 #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
 783         u16 k;
 784
 785         /* If this is a board that has a pwrTableOffset that differs from
 786          * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
 787          * pdadc vs pwr table needs to be adjusted prior to writing to the
 788          * chip.
 789          */
 790         if (AR_SREV_9280_20_OR_LATER(ah)) {
 791                 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 792                         /* shift the table to start at the new offset */
 793                         for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
 794                                 pdadcValues[k] = pdadcValues[k + diff];
 795                         }
 796
 797                         /* fill the back of the table */
 798                         for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
 799                                 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
 800                         }
 801                 }
 802         }
 803 #undef NUM_PDADC
 804 }
 805
 806 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
 807                                   struct ath9k_channel *chan)
 808 {
 809 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
 810 #define SM_PDGAIN_B(x, y) \
 811                 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
 812         struct ath_common *common = ath9k_hw_common(ah);
 813         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
 814         struct cal_data_per_freq *pRawDataset;
 815         u8 *pCalBChans = NULL;
 816         u16 pdGainOverlap_t2;
 817         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 818         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
 819         u16 numPiers, i, j;
 820         int16_t diff = 0;
 821         u16 numXpdGain, xpdMask;
 822         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
 823         u32 reg32, regOffset, regChainOffset;
 824         int16_t modalIdx;
 825         int8_t pwr_table_offset;
 826
 827         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
 828         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
 829
 830         pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
 831
 832         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 833             AR5416_EEP_MINOR_VER_2) {
 834                 pdGainOverlap_t2 =
 835                         pEepData->modalHeader[modalIdx].pdGainOverlap;
 836         } else {
 837                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 838                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 839         }
 840
 841         if (IS_CHAN_2GHZ(chan)) {
 842                 pCalBChans = pEepData->calFreqPier2G;
 843                 numPiers = AR5416_NUM_2G_CAL_PIERS;
 844         } else {
 845                 pCalBChans = pEepData->calFreqPier5G;
 846                 numPiers = AR5416_NUM_5G_CAL_PIERS;
 847         }
 848
 849         if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
 850                 pRawDataset = pEepData->calPierData2G[0];
 851                 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
 852                                  pRawDataset)->vpdPdg[0][0];
 853         }
 854
 855         numXpdGain = 0;
 856
 857         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 858                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
 859                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
 860                                 break;
 861                         xpdGainValues[numXpdGain] =
 862                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
 863                         numXpdGain++;
 864                 }
 865         }
 866
 867         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 868                       (numXpdGain - 1) & 0x3);
 869         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 870                       xpdGainValues[0]);
 871         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 872                       xpdGainValues[1]);
 873         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
 874                       xpdGainValues[2]);
 875
 876         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 877                 if ((ah->rxchainmask == 5 || ah->txchainmask == 5) &&
 878                     (i != 0)) {
 879                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 880                 } else
 881                         regChainOffset = i * 0x1000;
 882
 883                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 884                         if (IS_CHAN_2GHZ(chan))
 885                                 pRawDataset = pEepData->calPierData2G[i];
 886                         else
 887                                 pRawDataset = pEepData->calPierData5G[i];
 888
 889
 890                         if (OLC_FOR_AR9280_20_LATER) {
 891                                 u8 pcdacIdx;
 892                                 u8 txPower;
 893
 894                                 ath9k_get_txgain_index(ah, chan,
 895                                 (struct calDataPerFreqOpLoop *)pRawDataset,
 896                                 pCalBChans, numPiers, &txPower, &pcdacIdx);
 897                                 ath9k_olc_get_pdadcs(ah, pcdacIdx,
 898                                                      txPower/2, pdadcValues);
 899                         } else {
 900                                 ath9k_hw_get_gain_boundaries_pdadcs(ah,
 901                                                         chan, pRawDataset,
 902                                                         pCalBChans, numPiers,
 903                                                         pdGainOverlap_t2,
 904                                                         gainBoundaries,
 905                                                         pdadcValues,
 906                                                         numXpdGain);
 907                         }
 908
 909                         diff = ath9k_change_gain_boundary_setting(ah,
 910                                                            gainBoundaries,
 911                                                            numXpdGain,
 912                                                            pdGainOverlap_t2,
 913                                                            pwr_table_offset,
 914                                                            &diff);
 915
 916                         ENABLE_REGWRITE_BUFFER(ah);
 917
 918                         if (OLC_FOR_AR9280_20_LATER) {
 919                                 REG_WRITE(ah,
 920                                         AR_PHY_TPCRG5 + regChainOffset,
 921                                         SM(0x6,
 922                                         AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
 923                                         SM_PD_GAIN(1) | SM_PD_GAIN(2) |
 924                                         SM_PD_GAIN(3) | SM_PD_GAIN(4));
 925                         } else {
 926                                 REG_WRITE(ah,
 927                                         AR_PHY_TPCRG5 + regChainOffset,
 928                                         SM(pdGainOverlap_t2,
 929                                         AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
 930                                         SM_PDGAIN_B(0, 1) |
 931                                         SM_PDGAIN_B(1, 2) |
 932                                         SM_PDGAIN_B(2, 3) |
 933                                         SM_PDGAIN_B(3, 4));
 934                         }
 935
 936                         ath9k_adjust_pdadc_values(ah, pwr_table_offset,
 937                                                   diff, pdadcValues);
 938
 939                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 940                         for (j = 0; j < 32; j++) {
 941                                 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
 942                                 REG_WRITE(ah, regOffset, reg32);
 943
 944                                 ath_dbg(common, EEPROM,
 945                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
 946                                         i, regChainOffset, regOffset,
 947                                         reg32);
 948                                 ath_dbg(common, EEPROM,
 949                                         "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n",
 950                                         i, 4 * j, pdadcValues[4 * j],
 951                                         4 * j + 1, pdadcValues[4 * j + 1],
 952                                         4 * j + 2, pdadcValues[4 * j + 2],
 953                                         4 * j + 3, pdadcValues[4 * j + 3]);
 954
 955                                 regOffset += 4;
 956                         }
 957                         REGWRITE_BUFFER_FLUSH(ah);
 958                 }
 959         }
 960
 961 #undef SM_PD_GAIN
 962 #undef SM_PDGAIN_B
 963 }
 964
 965 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 966                                                   struct ath9k_channel *chan,
 967                                                   int16_t *ratesArray,
 968                                                   u16 cfgCtl,
 969                                                   u16 antenna_reduction,
 970                                                   u16 powerLimit)
 971 {
 972         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
 973         u16 twiceMaxEdgePower;
 974         int i;
 975         struct cal_ctl_data *rep;
 976         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
 977                 0, { 0, 0, 0, 0}
 978         };
 979         struct cal_target_power_leg targetPowerOfdmExt = {
 980                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
 981                 0, { 0, 0, 0, 0 }
 982         };
 983         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
 984                 0, {0, 0, 0, 0}
 985         };
 986         u16 scaledPower = 0, minCtlPower;
 987         static const u16 ctlModesFor11a[] = {
 988                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
 989         };
 990         static const u16 ctlModesFor11g[] = {
 991                 CTL_11B, CTL_11G, CTL_2GHT20,
 992                 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
 993         };
 994         u16 numCtlModes;
 995         const u16 *pCtlMode;
 996         u16 ctlMode, freq;
 997         struct chan_centers centers;
 998         int tx_chainmask;
 999         u16 twiceMinEdgePower;
1000
1001         tx_chainmask = ah->txchainmask;
1002
1003         ath9k_hw_get_channel_centers(ah, chan, &centers);
1004
1005         scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
1006                                                 antenna_reduction);
1007
1008         if (IS_CHAN_2GHZ(chan)) {
1009                 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
1010                         SUB_NUM_CTL_MODES_AT_2G_40;
1011                 pCtlMode = ctlModesFor11g;
1012
1013                 ath9k_hw_get_legacy_target_powers(ah, chan,
1014                         pEepData->calTargetPowerCck,
1015                         AR5416_NUM_2G_CCK_TARGET_POWERS,
1016                         &targetPowerCck, 4, false);
1017                 ath9k_hw_get_legacy_target_powers(ah, chan,
1018                         pEepData->calTargetPower2G,
1019                         AR5416_NUM_2G_20_TARGET_POWERS,
1020                         &targetPowerOfdm, 4, false);
1021                 ath9k_hw_get_target_powers(ah, chan,
1022                         pEepData->calTargetPower2GHT20,
1023                         AR5416_NUM_2G_20_TARGET_POWERS,
1024                         &targetPowerHt20, 8, false);
1025
1026                 if (IS_CHAN_HT40(chan)) {
1027                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1028                         ath9k_hw_get_target_powers(ah, chan,
1029                                 pEepData->calTargetPower2GHT40,
1030                                 AR5416_NUM_2G_40_TARGET_POWERS,
1031                                 &targetPowerHt40, 8, true);
1032                         ath9k_hw_get_legacy_target_powers(ah, chan,
1033                                 pEepData->calTargetPowerCck,
1034                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
1035                                 &targetPowerCckExt, 4, true);
1036                         ath9k_hw_get_legacy_target_powers(ah, chan,
1037                                 pEepData->calTargetPower2G,
1038                                 AR5416_NUM_2G_20_TARGET_POWERS,
1039                                 &targetPowerOfdmExt, 4, true);
1040                 }
1041         } else {
1042                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1043                         SUB_NUM_CTL_MODES_AT_5G_40;
1044                 pCtlMode = ctlModesFor11a;
1045
1046                 ath9k_hw_get_legacy_target_powers(ah, chan,
1047                         pEepData->calTargetPower5G,
1048                         AR5416_NUM_5G_20_TARGET_POWERS,
1049                         &targetPowerOfdm, 4, false);
1050                 ath9k_hw_get_target_powers(ah, chan,
1051                         pEepData->calTargetPower5GHT20,
1052                         AR5416_NUM_5G_20_TARGET_POWERS,
1053                         &targetPowerHt20, 8, false);
1054
1055                 if (IS_CHAN_HT40(chan)) {
1056                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1057                         ath9k_hw_get_target_powers(ah, chan,
1058                                 pEepData->calTargetPower5GHT40,
1059                                 AR5416_NUM_5G_40_TARGET_POWERS,
1060                                 &targetPowerHt40, 8, true);
1061                         ath9k_hw_get_legacy_target_powers(ah, chan,
1062                                 pEepData->calTargetPower5G,
1063                                 AR5416_NUM_5G_20_TARGET_POWERS,
1064                                 &targetPowerOfdmExt, 4, true);
1065                 }
1066         }
1067
1068         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1069                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1070                         (pCtlMode[ctlMode] == CTL_2GHT40);
1071                 if (isHt40CtlMode)
1072                         freq = centers.synth_center;
1073                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1074                         freq = centers.ext_center;
1075                 else
1076                         freq = centers.ctl_center;
1077
1078                 twiceMaxEdgePower = MAX_RATE_POWER;
1079
1080                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1081                         if ((((cfgCtl & ~CTL_MODE_M) |
1082                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1083                              pEepData->ctlIndex[i]) ||
1084                             (((cfgCtl & ~CTL_MODE_M) |
1085                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1086                              ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1087                                 rep = &(pEepData->ctlData[i]);
1088
1089                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1090                                 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1091                                 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1092
1093                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1094                                         twiceMaxEdgePower = min(twiceMaxEdgePower,
1095                                                                 twiceMinEdgePower);
1096                                 } else {
1097                                         twiceMaxEdgePower = twiceMinEdgePower;
1098                                         break;
1099                                 }
1100                         }
1101                 }
1102
1103                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1104
1105                 switch (pCtlMode[ctlMode]) {
1106                 case CTL_11B:
1107                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1108                                 targetPowerCck.tPow2x[i] =
1109                                         min((u16)targetPowerCck.tPow2x[i],
1110                                             minCtlPower);
1111                         }
1112                         break;
1113                 case CTL_11A:
1114                 case CTL_11G:
1115                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1116                                 targetPowerOfdm.tPow2x[i] =
1117                                         min((u16)targetPowerOfdm.tPow2x[i],
1118                                             minCtlPower);
1119                         }
1120                         break;
1121                 case CTL_5GHT20:
1122                 case CTL_2GHT20:
1123                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1124                                 targetPowerHt20.tPow2x[i] =
1125                                         min((u16)targetPowerHt20.tPow2x[i],
1126                                             minCtlPower);
1127                         }
1128                         break;
1129                 case CTL_11B_EXT:
1130                         targetPowerCckExt.tPow2x[0] = min((u16)
1131                                         targetPowerCckExt.tPow2x[0],
1132                                         minCtlPower);
1133                         break;
1134                 case CTL_11A_EXT:
1135                 case CTL_11G_EXT:
1136                         targetPowerOfdmExt.tPow2x[0] = min((u16)
1137                                         targetPowerOfdmExt.tPow2x[0],
1138                                         minCtlPower);
1139                         break;
1140                 case CTL_5GHT40:
1141                 case CTL_2GHT40:
1142                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1143                                 targetPowerHt40.tPow2x[i] =
1144                                         min((u16)targetPowerHt40.tPow2x[i],
1145                                             minCtlPower);
1146                         }
1147                         break;
1148                 default:
1149                         break;
1150                 }
1151         }
1152
1153         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1154                 ratesArray[rate18mb] = ratesArray[rate24mb] =
1155                 targetPowerOfdm.tPow2x[0];
1156         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1157         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1158         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1159         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1160
1161         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1162                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1163
1164         if (IS_CHAN_2GHZ(chan)) {
1165                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1166                 ratesArray[rate2s] = ratesArray[rate2l] =
1167                         targetPowerCck.tPow2x[1];
1168                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1169                         targetPowerCck.tPow2x[2];
1170                 ratesArray[rate11s] = ratesArray[rate11l] =
1171                         targetPowerCck.tPow2x[3];
1172         }
1173         if (IS_CHAN_HT40(chan)) {
1174                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1175                         ratesArray[rateHt40_0 + i] =
1176                                 targetPowerHt40.tPow2x[i];
1177                 }
1178                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1179                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1180                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1181                 if (IS_CHAN_2GHZ(chan)) {
1182                         ratesArray[rateExtCck] =
1183                                 targetPowerCckExt.tPow2x[0];
1184                 }
1185         }
1186 }
1187
1188 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1189                                     struct ath9k_channel *chan,
1190                                     u16 cfgCtl,
1191                                     u8 twiceAntennaReduction,
1192                                     u8 powerLimit, bool test)
1193 {
1194 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1195         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1196         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1197         struct modal_eep_header *pModal =
1198                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1199         int16_t ratesArray[Ar5416RateSize];
1200         u8 ht40PowerIncForPdadc = 2;
1201         int i, cck_ofdm_delta = 0;
1202
1203         memset(ratesArray, 0, sizeof(ratesArray));
1204
1205         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1206             AR5416_EEP_MINOR_VER_2) {
1207                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1208         }
1209
1210         ath9k_hw_set_def_power_per_rate_table(ah, chan,
1211                                                &ratesArray[0], cfgCtl,
1212                                                twiceAntennaReduction,
1213                                                powerLimit);
1214
1215         ath9k_hw_set_def_power_cal_table(ah, chan);
1216
1217         regulatory->max_power_level = 0;
1218         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1219                 if (ratesArray[i] > MAX_RATE_POWER)
1220                         ratesArray[i] = MAX_RATE_POWER;
1221                 if (ratesArray[i] > regulatory->max_power_level)
1222                         regulatory->max_power_level = ratesArray[i];
1223         }
1224
1225         ath9k_hw_update_regulatory_maxpower(ah);
1226
1227         if (test)
1228                 return;
1229
1230         if (AR_SREV_9280_20_OR_LATER(ah)) {
1231                 for (i = 0; i < Ar5416RateSize; i++) {
1232                         int8_t pwr_table_offset;
1233
1234                         pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1235                                                         EEP_PWR_TABLE_OFFSET);
1236                         ratesArray[i] -= pwr_table_offset * 2;
1237                 }
1238         }
1239
1240         ENABLE_REGWRITE_BUFFER(ah);
1241
1242         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1243                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
1244                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1245                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1246                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1247         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1248                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
1249                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1250                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1251                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1252
1253         if (IS_CHAN_2GHZ(chan)) {
1254                 if (OLC_FOR_AR9280_20_LATER) {
1255                         cck_ofdm_delta = 2;
1256                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1257                                 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1258                                 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1259                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1260                                 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1261                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1262                                 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1263                                 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1264                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1265                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1266                 } else {
1267                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1268                                 ATH9K_POW_SM(ratesArray[rate2s], 24)
1269                                 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1270                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1271                                 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1272                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1273                                 ATH9K_POW_SM(ratesArray[rate11s], 24)
1274                                 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1275                                 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1276                                 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1277                 }
1278         }
1279
1280         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1281                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1282                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1283                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1284                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1285         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1286                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1287                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1288                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1289                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1290
1291         if (IS_CHAN_HT40(chan)) {
1292                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1293                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
1294                                        ht40PowerIncForPdadc, 24)
1295                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1296                                          ht40PowerIncForPdadc, 16)
1297                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1298                                          ht40PowerIncForPdadc, 8)
1299                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1300                                          ht40PowerIncForPdadc, 0));
1301                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1302                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
1303                                        ht40PowerIncForPdadc, 24)
1304                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1305                                          ht40PowerIncForPdadc, 16)
1306                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1307                                          ht40PowerIncForPdadc, 8)
1308                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1309                                          ht40PowerIncForPdadc, 0));
1310                 if (OLC_FOR_AR9280_20_LATER) {
1311                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1312                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1313                                 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1314                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1315                                 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1316                 } else {
1317                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1318                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1319                                 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1320                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1321                                 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1322                 }
1323         }
1324
1325         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1326                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1327                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1328
1329         /* TPC initializations */
1330         if (ah->tpc_enabled) {
1331                 int ht40_delta;
1332
1333                 ht40_delta = (IS_CHAN_HT40(chan)) ? ht40PowerIncForPdadc : 0;
1334                 ar5008_hw_init_rate_txpower(ah, ratesArray, chan, ht40_delta);
1335                 /* Enable TPC */
1336                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX,
1337                         MAX_RATE_POWER | AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE);
1338         } else {
1339                 /* Disable TPC */
1340                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER);
1341         }
1342
1343         REGWRITE_BUFFER_FLUSH(ah);
1344 }
1345
1346 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1347 {
1348         return ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan;
1349 }
1350
1351 const struct eeprom_ops eep_def_ops = {
1352         .check_eeprom           = ath9k_hw_def_check_eeprom,
1353         .get_eeprom             = ath9k_hw_def_get_eeprom,
1354         .fill_eeprom            = ath9k_hw_def_fill_eeprom,
1355         .dump_eeprom            = ath9k_hw_def_dump_eeprom,
1356         .get_eeprom_ver         = ath9k_hw_def_get_eeprom_ver,
1357         .get_eeprom_rev         = ath9k_hw_def_get_eeprom_rev,
1358         .set_board_values       = ath9k_hw_def_set_board_values,
1359         .set_addac              = ath9k_hw_def_set_addac,
1360         .set_txpower            = ath9k_hw_def_set_txpower,
1361         .get_spur_channel       = ath9k_hw_def_get_spur_channel
1362 };