kernel/drivers/net/phy/marvell.c

   1 /*
   2  * drivers/net/phy/marvell.c
   3  *
   4  * Driver for Marvell PHYs
   5  *
   6  * Author: Andy Fleming
   7  *
   8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
   9  *
  10  * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  *
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/string.h>
  20 #include <linux/errno.h>
  21 #include <linux/unistd.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/init.h>
  24 #include <linux/delay.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/mm.h>
  30 #include <linux/module.h>
  31 #include <linux/mii.h>
  32 #include <linux/ethtool.h>
  33 #include <linux/phy.h>
  34 #include <linux/marvell_phy.h>
  35 #include <linux/of.h>
  36
  37 #include <linux/io.h>
  38 #include <asm/irq.h>
  39 #include <linux/uaccess.h>
  40
  41 #define MII_MARVELL_PHY_PAGE            22
  42
  43 #define MII_M1011_IEVENT                0x13
  44 #define MII_M1011_IEVENT_CLEAR          0x0000
  45
  46 #define MII_M1011_IMASK                 0x12
  47 #define MII_M1011_IMASK_INIT            0x6400
  48 #define MII_M1011_IMASK_CLEAR           0x0000
  49
  50 #define MII_M1011_PHY_SCR               0x10
  51 #define MII_M1011_PHY_SCR_AUTO_CROSS    0x0060
  52
  53 #define MII_M1145_PHY_EXT_SR            0x1b
  54 #define MII_M1145_PHY_EXT_CR            0x14
  55 #define MII_M1145_RGMII_RX_DELAY        0x0080
  56 #define MII_M1145_RGMII_TX_DELAY        0x0002
  57 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK       0x4
  58 #define MII_M1145_HWCFG_MODE_MASK               0xf
  59 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO       0x8000
  60
  61 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK       0x4
  62 #define MII_M1145_HWCFG_MODE_MASK               0xf
  63 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO       0x8000
  64
  65 #define MII_M1111_PHY_LED_CONTROL       0x18
  66 #define MII_M1111_PHY_LED_DIRECT        0x4100
  67 #define MII_M1111_PHY_LED_COMBINE       0x411c
  68 #define MII_M1111_PHY_EXT_CR            0x14
  69 #define MII_M1111_RX_DELAY              0x80
  70 #define MII_M1111_TX_DELAY              0x2
  71 #define MII_M1111_PHY_EXT_SR            0x1b
  72
  73 #define MII_M1111_HWCFG_MODE_MASK               0xf
  74 #define MII_M1111_HWCFG_MODE_COPPER_RGMII       0xb
  75 #define MII_M1111_HWCFG_MODE_FIBER_RGMII        0x3
  76 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK       0x4
  77 #define MII_M1111_HWCFG_MODE_COPPER_RTBI        0x9
  78 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO       0x8000
  79 #define MII_M1111_HWCFG_FIBER_COPPER_RES        0x2000
  80
  81 #define MII_M1111_COPPER                0
  82 #define MII_M1111_FIBER                 1
  83
  84 #define MII_88E1121_PHY_MSCR_PAGE       2
  85 #define MII_88E1121_PHY_MSCR_REG        21
  86 #define MII_88E1121_PHY_MSCR_RX_DELAY   BIT(5)
  87 #define MII_88E1121_PHY_MSCR_TX_DELAY   BIT(4)
  88 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
  89
  90 #define MII_88E1318S_PHY_MSCR1_REG      16
  91 #define MII_88E1318S_PHY_MSCR1_PAD_ODD  BIT(6)
  92
  93 /* Copper Specific Interrupt Enable Register */
  94 #define MII_88E1318S_PHY_CSIER                              0x12
  95 /* WOL Event Interrupt Enable */
  96 #define MII_88E1318S_PHY_CSIER_WOL_EIE                      BIT(7)
  97
  98 /* LED Timer Control Register */
  99 #define MII_88E1318S_PHY_LED_PAGE                           0x03
 100 #define MII_88E1318S_PHY_LED_TCR                            0x12
 101 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT                  BIT(15)
 102 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE                BIT(7)
 103 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW             BIT(11)
 104
 105 /* Magic Packet MAC address registers */
 106 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2                 0x17
 107 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1                 0x18
 108 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0                 0x19
 109
 110 #define MII_88E1318S_PHY_WOL_PAGE                           0x11
 111 #define MII_88E1318S_PHY_WOL_CTRL                           0x10
 112 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS          BIT(12)
 113 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
 114
 115 #define MII_88E1121_PHY_LED_CTRL        16
 116 #define MII_88E1121_PHY_LED_PAGE        3
 117 #define MII_88E1121_PHY_LED_DEF         0x0030
 118
 119 #define MII_M1011_PHY_STATUS            0x11
 120 #define MII_M1011_PHY_STATUS_1000       0x8000
 121 #define MII_M1011_PHY_STATUS_100        0x4000
 122 #define MII_M1011_PHY_STATUS_SPD_MASK   0xc000
 123 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
 124 #define MII_M1011_PHY_STATUS_RESOLVED   0x0800
 125 #define MII_M1011_PHY_STATUS_LINK       0x0400
 126
 127 #define MII_M1116R_CONTROL_REG_MAC      21
 128
 129 #define MII_88E3016_PHY_SPEC_CTRL       0x10
 130 #define MII_88E3016_DISABLE_SCRAMBLER   0x0200
 131 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
 132
 133 MODULE_DESCRIPTION("Marvell PHY driver");
 134 MODULE_AUTHOR("Andy Fleming");
 135 MODULE_LICENSE("GPL");
 136
 137 static int marvell_ack_interrupt(struct phy_device *phydev)
 138 {
 139         int err;
 140
 141         /* Clear the interrupts by reading the reg */
 142         err = phy_read(phydev, MII_M1011_IEVENT);
 143
 144         if (err < 0)
 145                 return err;
 146
 147         return 0;
 148 }
 149
 150 static int marvell_config_intr(struct phy_device *phydev)
 151 {
 152         int err;
 153
 154         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 155                 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
 156         else
 157                 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
 158
 159         return err;
 160 }
 161
 162 static int marvell_config_aneg(struct phy_device *phydev)
 163 {
 164         int err;
 165
 166         /* The Marvell PHY has an errata which requires
 167          * that certain registers get written in order
 168          * to restart autonegotiation */
 169         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 170
 171         if (err < 0)
 172                 return err;
 173
 174         err = phy_write(phydev, 0x1d, 0x1f);
 175         if (err < 0)
 176                 return err;
 177
 178         err = phy_write(phydev, 0x1e, 0x200c);
 179         if (err < 0)
 180                 return err;
 181
 182         err = phy_write(phydev, 0x1d, 0x5);
 183         if (err < 0)
 184                 return err;
 185
 186         err = phy_write(phydev, 0x1e, 0);
 187         if (err < 0)
 188                 return err;
 189
 190         err = phy_write(phydev, 0x1e, 0x100);
 191         if (err < 0)
 192                 return err;
 193
 194         err = phy_write(phydev, MII_M1011_PHY_SCR,
 195                         MII_M1011_PHY_SCR_AUTO_CROSS);
 196         if (err < 0)
 197                 return err;
 198
 199         err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
 200                         MII_M1111_PHY_LED_DIRECT);
 201         if (err < 0)
 202                 return err;
 203
 204         err = genphy_config_aneg(phydev);
 205         if (err < 0)
 206                 return err;
 207
 208         if (phydev->autoneg != AUTONEG_ENABLE) {
 209                 int bmcr;
 210
 211                 /*
 212                  * A write to speed/duplex bits (that is performed by
 213                  * genphy_config_aneg() call above) must be followed by
 214                  * a software reset. Otherwise, the write has no effect.
 215                  */
 216                 bmcr = phy_read(phydev, MII_BMCR);
 217                 if (bmcr < 0)
 218                         return bmcr;
 219
 220                 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
 221                 if (err < 0)
 222                         return err;
 223         }
 224
 225         return 0;
 226 }
 227
 228 #ifdef CONFIG_OF_MDIO
 229 /*
 230  * Set and/or override some configuration registers based on the
 231  * marvell,reg-init property stored in the of_node for the phydev.
 232  *
 233  * marvell,reg-init = <reg-page reg mask value>,...;
 234  *
 235  * There may be one or more sets of <reg-page reg mask value>:
 236  *
 237  * reg-page: which register bank to use.
 238  * reg: the register.
 239  * mask: if non-zero, ANDed with existing register value.
 240  * value: ORed with the masked value and written to the regiser.
 241  *
 242  */
 243 static int marvell_of_reg_init(struct phy_device *phydev)
 244 {
 245         const __be32 *paddr;
 246         int len, i, saved_page, current_page, page_changed, ret;
 247
 248         if (!phydev->dev.of_node)
 249                 return 0;
 250
 251         paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
 252         if (!paddr || len < (4 * sizeof(*paddr)))
 253                 return 0;
 254
 255         saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 256         if (saved_page < 0)
 257                 return saved_page;
 258         page_changed = 0;
 259         current_page = saved_page;
 260
 261         ret = 0;
 262         len /= sizeof(*paddr);
 263         for (i = 0; i < len - 3; i += 4) {
 264                 u16 reg_page = be32_to_cpup(paddr + i);
 265                 u16 reg = be32_to_cpup(paddr + i + 1);
 266                 u16 mask = be32_to_cpup(paddr + i + 2);
 267                 u16 val_bits = be32_to_cpup(paddr + i + 3);
 268                 int val;
 269
 270                 if (reg_page != current_page) {
 271                         current_page = reg_page;
 272                         page_changed = 1;
 273                         ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
 274                         if (ret < 0)
 275                                 goto err;
 276                 }
 277
 278                 val = 0;
 279                 if (mask) {
 280                         val = phy_read(phydev, reg);
 281                         if (val < 0) {
 282                                 ret = val;
 283                                 goto err;
 284                         }
 285                         val &= mask;
 286                 }
 287                 val |= val_bits;
 288
 289                 ret = phy_write(phydev, reg, val);
 290                 if (ret < 0)
 291                         goto err;
 292
 293         }
 294 err:
 295         if (page_changed) {
 296                 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
 297                 if (ret == 0)
 298                         ret = i;
 299         }
 300         return ret;
 301 }
 302 #else
 303 static int marvell_of_reg_init(struct phy_device *phydev)
 304 {
 305         return 0;
 306 }
 307 #endif /* CONFIG_OF_MDIO */
 308
 309 static int m88e1121_config_aneg(struct phy_device *phydev)
 310 {
 311         int err, oldpage, mscr;
 312
 313         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 314
 315         err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 316                         MII_88E1121_PHY_MSCR_PAGE);
 317         if (err < 0)
 318                 return err;
 319
 320         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
 321             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 322             (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 323             (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 324
 325                 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
 326                         MII_88E1121_PHY_MSCR_DELAY_MASK;
 327
 328                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 329                         mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
 330                                  MII_88E1121_PHY_MSCR_TX_DELAY);
 331                 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 332                         mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
 333                 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 334                         mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
 335
 336                 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
 337                 if (err < 0)
 338                         return err;
 339         }
 340
 341         phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 342
 343         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 344         if (err < 0)
 345                 return err;
 346
 347         err = phy_write(phydev, MII_M1011_PHY_SCR,
 348                         MII_M1011_PHY_SCR_AUTO_CROSS);
 349         if (err < 0)
 350                 return err;
 351
 352         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 353
 354         phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
 355         phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
 356         phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 357
 358         err = genphy_config_aneg(phydev);
 359
 360         return err;
 361 }
 362
 363 static int m88e1318_config_aneg(struct phy_device *phydev)
 364 {
 365         int err, oldpage, mscr;
 366
 367         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 368
 369         err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 370                         MII_88E1121_PHY_MSCR_PAGE);
 371         if (err < 0)
 372                 return err;
 373
 374         mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
 375         mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
 376
 377         err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
 378         if (err < 0)
 379                 return err;
 380
 381         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 382         if (err < 0)
 383                 return err;
 384
 385         return m88e1121_config_aneg(phydev);
 386 }
 387
 388 static int m88e1510_config_aneg(struct phy_device *phydev)
 389 {
 390         int err;
 391
 392         err = m88e1318_config_aneg(phydev);
 393         if (err < 0)
 394                 return err;
 395
 396         return marvell_of_reg_init(phydev);
 397 }
 398
 399 static int m88e1116r_config_init(struct phy_device *phydev)
 400 {
 401         int temp;
 402         int err;
 403
 404         temp = phy_read(phydev, MII_BMCR);
 405         temp |= BMCR_RESET;
 406         err = phy_write(phydev, MII_BMCR, temp);
 407         if (err < 0)
 408                 return err;
 409
 410         mdelay(500);
 411
 412         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
 413         if (err < 0)
 414                 return err;
 415
 416         temp = phy_read(phydev, MII_M1011_PHY_SCR);
 417         temp |= (7 << 12);      /* max number of gigabit attempts */
 418         temp |= (1 << 11);      /* enable downshift */
 419         temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
 420         err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
 421         if (err < 0)
 422                 return err;
 423
 424         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
 425         if (err < 0)
 426                 return err;
 427         temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
 428         temp |= (1 << 5);
 429         temp |= (1 << 4);
 430         err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
 431         if (err < 0)
 432                 return err;
 433         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
 434         if (err < 0)
 435                 return err;
 436
 437         temp = phy_read(phydev, MII_BMCR);
 438         temp |= BMCR_RESET;
 439         err = phy_write(phydev, MII_BMCR, temp);
 440         if (err < 0)
 441                 return err;
 442
 443         mdelay(500);
 444
 445         return 0;
 446 }
 447
 448 static int m88e3016_config_init(struct phy_device *phydev)
 449 {
 450         int reg;
 451
 452         /* Enable Scrambler and Auto-Crossover */
 453         reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
 454         if (reg < 0)
 455                 return reg;
 456
 457         reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
 458         reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
 459
 460         reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
 461         if (reg < 0)
 462                 return reg;
 463
 464         return 0;
 465 }
 466
 467 static int m88e1111_config_init(struct phy_device *phydev)
 468 {
 469         int err;
 470         int temp;
 471
 472         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
 473             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 474             (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 475             (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 476
 477                 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
 478                 if (temp < 0)
 479                         return temp;
 480
 481                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
 482                         temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
 483                 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 484                         temp &= ~MII_M1111_TX_DELAY;
 485                         temp |= MII_M1111_RX_DELAY;
 486                 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
 487                         temp &= ~MII_M1111_RX_DELAY;
 488                         temp |= MII_M1111_TX_DELAY;
 489                 }
 490
 491                 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
 492                 if (err < 0)
 493                         return err;
 494
 495                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 496                 if (temp < 0)
 497                         return temp;
 498
 499                 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
 500
 501                 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
 502                         temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
 503                 else
 504                         temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
 505
 506                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 507                 if (err < 0)
 508                         return err;
 509         }
 510
 511         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 512                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 513                 if (temp < 0)
 514                         return temp;
 515
 516                 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
 517                 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
 518                 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
 519
 520                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 521                 if (err < 0)
 522                         return err;
 523         }
 524
 525         if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
 526                 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
 527                 if (temp < 0)
 528                         return temp;
 529                 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
 530                 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
 531                 if (err < 0)
 532                         return err;
 533
 534                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 535                 if (temp < 0)
 536                         return temp;
 537                 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
 538                 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
 539                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 540                 if (err < 0)
 541                         return err;
 542
 543                 /* soft reset */
 544                 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 545                 if (err < 0)
 546                         return err;
 547                 do
 548                         temp = phy_read(phydev, MII_BMCR);
 549                 while (temp & BMCR_RESET);
 550
 551                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 552                 if (temp < 0)
 553                         return temp;
 554                 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
 555                 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
 556                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 557                 if (err < 0)
 558                         return err;
 559         }
 560
 561         err = marvell_of_reg_init(phydev);
 562         if (err < 0)
 563                 return err;
 564
 565         return phy_write(phydev, MII_BMCR, BMCR_RESET);
 566 }
 567
 568 static int m88e1118_config_aneg(struct phy_device *phydev)
 569 {
 570         int err;
 571
 572         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 573         if (err < 0)
 574                 return err;
 575
 576         err = phy_write(phydev, MII_M1011_PHY_SCR,
 577                         MII_M1011_PHY_SCR_AUTO_CROSS);
 578         if (err < 0)
 579                 return err;
 580
 581         err = genphy_config_aneg(phydev);
 582         return 0;
 583 }
 584
 585 static int m88e1118_config_init(struct phy_device *phydev)
 586 {
 587         int err;
 588
 589         /* Change address */
 590         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
 591         if (err < 0)
 592                 return err;
 593
 594         /* Enable 1000 Mbit */
 595         err = phy_write(phydev, 0x15, 0x1070);
 596         if (err < 0)
 597                 return err;
 598
 599         /* Change address */
 600         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
 601         if (err < 0)
 602                 return err;
 603
 604         /* Adjust LED Control */
 605         if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
 606                 err = phy_write(phydev, 0x10, 0x1100);
 607         else
 608                 err = phy_write(phydev, 0x10, 0x021e);
 609         if (err < 0)
 610                 return err;
 611
 612         err = marvell_of_reg_init(phydev);
 613         if (err < 0)
 614                 return err;
 615
 616         /* Reset address */
 617         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
 618         if (err < 0)
 619                 return err;
 620
 621         return phy_write(phydev, MII_BMCR, BMCR_RESET);
 622 }
 623
 624 static int m88e1149_config_init(struct phy_device *phydev)
 625 {
 626         int err;
 627
 628         /* Change address */
 629         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
 630         if (err < 0)
 631                 return err;
 632
 633         /* Enable 1000 Mbit */
 634         err = phy_write(phydev, 0x15, 0x1048);
 635         if (err < 0)
 636                 return err;
 637
 638         err = marvell_of_reg_init(phydev);
 639         if (err < 0)
 640                 return err;
 641
 642         /* Reset address */
 643         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
 644         if (err < 0)
 645                 return err;
 646
 647         return phy_write(phydev, MII_BMCR, BMCR_RESET);
 648 }
 649
 650 static int m88e1145_config_init(struct phy_device *phydev)
 651 {
 652         int err;
 653         int temp;
 654
 655         /* Take care of errata E0 & E1 */
 656         err = phy_write(phydev, 0x1d, 0x001b);
 657         if (err < 0)
 658                 return err;
 659
 660         err = phy_write(phydev, 0x1e, 0x418f);
 661         if (err < 0)
 662                 return err;
 663
 664         err = phy_write(phydev, 0x1d, 0x0016);
 665         if (err < 0)
 666                 return err;
 667
 668         err = phy_write(phydev, 0x1e, 0xa2da);
 669         if (err < 0)
 670                 return err;
 671
 672         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
 673                 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
 674                 if (temp < 0)
 675                         return temp;
 676
 677                 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
 678
 679                 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
 680                 if (err < 0)
 681                         return err;
 682
 683                 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
 684                         err = phy_write(phydev, 0x1d, 0x0012);
 685                         if (err < 0)
 686                                 return err;
 687
 688                         temp = phy_read(phydev, 0x1e);
 689                         if (temp < 0)
 690                                 return temp;
 691
 692                         temp &= 0xf03f;
 693                         temp |= 2 << 9; /* 36 ohm */
 694                         temp |= 2 << 6; /* 39 ohm */
 695
 696                         err = phy_write(phydev, 0x1e, temp);
 697                         if (err < 0)
 698                                 return err;
 699
 700                         err = phy_write(phydev, 0x1d, 0x3);
 701                         if (err < 0)
 702                                 return err;
 703
 704                         err = phy_write(phydev, 0x1e, 0x8000);
 705                         if (err < 0)
 706                                 return err;
 707                 }
 708         }
 709
 710         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 711                 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
 712                 if (temp < 0)
 713                         return temp;
 714
 715                 temp &= ~MII_M1145_HWCFG_MODE_MASK;
 716                 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
 717                 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
 718
 719                 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
 720                 if (err < 0)
 721                         return err;
 722         }
 723
 724         err = marvell_of_reg_init(phydev);
 725         if (err < 0)
 726                 return err;
 727
 728         return 0;
 729 }
 730
 731 /* marvell_read_status
 732  *
 733  * Generic status code does not detect Fiber correctly!
 734  * Description:
 735  *   Check the link, then figure out the current state
 736  *   by comparing what we advertise with what the link partner
 737  *   advertises.  Start by checking the gigabit possibilities,
 738  *   then move on to 10/100.
 739  */
 740 static int marvell_read_status(struct phy_device *phydev)
 741 {
 742         int adv;
 743         int err;
 744         int lpa;
 745         int status = 0;
 746
 747         /* Update the link, but return if there
 748          * was an error */
 749         err = genphy_update_link(phydev);
 750         if (err)
 751                 return err;
 752
 753         if (AUTONEG_ENABLE == phydev->autoneg) {
 754                 status = phy_read(phydev, MII_M1011_PHY_STATUS);
 755                 if (status < 0)
 756                         return status;
 757
 758                 lpa = phy_read(phydev, MII_LPA);
 759                 if (lpa < 0)
 760                         return lpa;
 761
 762                 adv = phy_read(phydev, MII_ADVERTISE);
 763                 if (adv < 0)
 764                         return adv;
 765
 766                 lpa &= adv;
 767
 768                 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
 769                         phydev->duplex = DUPLEX_FULL;
 770                 else
 771                         phydev->duplex = DUPLEX_HALF;
 772
 773                 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
 774                 phydev->pause = phydev->asym_pause = 0;
 775
 776                 switch (status) {
 777                 case MII_M1011_PHY_STATUS_1000:
 778                         phydev->speed = SPEED_1000;
 779                         break;
 780
 781                 case MII_M1011_PHY_STATUS_100:
 782                         phydev->speed = SPEED_100;
 783                         break;
 784
 785                 default:
 786                         phydev->speed = SPEED_10;
 787                         break;
 788                 }
 789
 790                 if (phydev->duplex == DUPLEX_FULL) {
 791                         phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
 792                         phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
 793                 }
 794         } else {
 795                 int bmcr = phy_read(phydev, MII_BMCR);
 796
 797                 if (bmcr < 0)
 798                         return bmcr;
 799
 800                 if (bmcr & BMCR_FULLDPLX)
 801                         phydev->duplex = DUPLEX_FULL;
 802                 else
 803                         phydev->duplex = DUPLEX_HALF;
 804
 805                 if (bmcr & BMCR_SPEED1000)
 806                         phydev->speed = SPEED_1000;
 807                 else if (bmcr & BMCR_SPEED100)
 808                         phydev->speed = SPEED_100;
 809                 else
 810                         phydev->speed = SPEED_10;
 811
 812                 phydev->pause = phydev->asym_pause = 0;
 813         }
 814
 815         return 0;
 816 }
 817
 818 static int marvell_aneg_done(struct phy_device *phydev)
 819 {
 820         int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
 821         return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
 822 }
 823
 824 static int m88e1121_did_interrupt(struct phy_device *phydev)
 825 {
 826         int imask;
 827
 828         imask = phy_read(phydev, MII_M1011_IEVENT);
 829
 830         if (imask & MII_M1011_IMASK_INIT)
 831                 return 1;
 832
 833         return 0;
 834 }
 835
 836 static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
 837 {
 838         wol->supported = WAKE_MAGIC;
 839         wol->wolopts = 0;
 840
 841         if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
 842                       MII_88E1318S_PHY_WOL_PAGE) < 0)
 843                 return;
 844
 845         if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
 846             MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
 847                 wol->wolopts |= WAKE_MAGIC;
 848
 849         if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
 850                 return;
 851 }
 852
 853 static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
 854 {
 855         int err, oldpage, temp;
 856
 857         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 858
 859         if (wol->wolopts & WAKE_MAGIC) {
 860                 /* Explicitly switch to page 0x00, just to be sure */
 861                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
 862                 if (err < 0)
 863                         return err;
 864
 865                 /* Enable the WOL interrupt */
 866                 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
 867                 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
 868                 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
 869                 if (err < 0)
 870                         return err;
 871
 872                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 873                                 MII_88E1318S_PHY_LED_PAGE);
 874                 if (err < 0)
 875                         return err;
 876
 877                 /* Setup LED[2] as interrupt pin (active low) */
 878                 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
 879                 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
 880                 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
 881                 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
 882                 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
 883                 if (err < 0)
 884                         return err;
 885
 886                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 887                                 MII_88E1318S_PHY_WOL_PAGE);
 888                 if (err < 0)
 889                         return err;
 890
 891                 /* Store the device address for the magic packet */
 892                 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
 893                                 ((phydev->attached_dev->dev_addr[5] << 8) |
 894                                  phydev->attached_dev->dev_addr[4]));
 895                 if (err < 0)
 896                         return err;
 897                 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
 898                                 ((phydev->attached_dev->dev_addr[3] << 8) |
 899                                  phydev->attached_dev->dev_addr[2]));
 900                 if (err < 0)
 901                         return err;
 902                 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
 903                                 ((phydev->attached_dev->dev_addr[1] << 8) |
 904                                  phydev->attached_dev->dev_addr[0]));
 905                 if (err < 0)
 906                         return err;
 907
 908                 /* Clear WOL status and enable magic packet matching */
 909                 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
 910                 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
 911                 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
 912                 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
 913                 if (err < 0)
 914                         return err;
 915         } else {
 916                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 917                                 MII_88E1318S_PHY_WOL_PAGE);
 918                 if (err < 0)
 919                         return err;
 920
 921                 /* Clear WOL status and disable magic packet matching */
 922                 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
 923                 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
 924                 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
 925                 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
 926                 if (err < 0)
 927                         return err;
 928         }
 929
 930         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 931         if (err < 0)
 932                 return err;
 933
 934         return 0;
 935 }
 936
 937 static struct phy_driver marvell_drivers[] = {
 938         {
 939                 .phy_id = MARVELL_PHY_ID_88E1101,
 940                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 941                 .name = "Marvell 88E1101",
 942                 .features = PHY_GBIT_FEATURES,
 943                 .flags = PHY_HAS_INTERRUPT,
 944                 .config_aneg = &marvell_config_aneg,
 945                 .read_status = &genphy_read_status,
 946                 .ack_interrupt = &marvell_ack_interrupt,
 947                 .config_intr = &marvell_config_intr,
 948                 .resume = &genphy_resume,
 949                 .suspend = &genphy_suspend,
 950                 .driver = { .owner = THIS_MODULE },
 951         },
 952         {
 953                 .phy_id = MARVELL_PHY_ID_88E1112,
 954                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 955                 .name = "Marvell 88E1112",
 956                 .features = PHY_GBIT_FEATURES,
 957                 .flags = PHY_HAS_INTERRUPT,
 958                 .config_init = &m88e1111_config_init,
 959                 .config_aneg = &marvell_config_aneg,
 960                 .read_status = &genphy_read_status,
 961                 .ack_interrupt = &marvell_ack_interrupt,
 962                 .config_intr = &marvell_config_intr,
 963                 .resume = &genphy_resume,
 964                 .suspend = &genphy_suspend,
 965                 .driver = { .owner = THIS_MODULE },
 966         },
 967         {
 968                 .phy_id = MARVELL_PHY_ID_88E1111,
 969                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 970                 .name = "Marvell 88E1111",
 971                 .features = PHY_GBIT_FEATURES,
 972                 .flags = PHY_HAS_INTERRUPT,
 973                 .config_init = &m88e1111_config_init,
 974                 .config_aneg = &marvell_config_aneg,
 975                 .read_status = &marvell_read_status,
 976                 .ack_interrupt = &marvell_ack_interrupt,
 977                 .config_intr = &marvell_config_intr,
 978                 .resume = &genphy_resume,
 979                 .suspend = &genphy_suspend,
 980                 .driver = { .owner = THIS_MODULE },
 981         },
 982         {
 983                 .phy_id = MARVELL_PHY_ID_88E1118,
 984                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 985                 .name = "Marvell 88E1118",
 986                 .features = PHY_GBIT_FEATURES,
 987                 .flags = PHY_HAS_INTERRUPT,
 988                 .config_init = &m88e1118_config_init,
 989                 .config_aneg = &m88e1118_config_aneg,
 990                 .read_status = &genphy_read_status,
 991                 .ack_interrupt = &marvell_ack_interrupt,
 992                 .config_intr = &marvell_config_intr,
 993                 .resume = &genphy_resume,
 994                 .suspend = &genphy_suspend,
 995                 .driver = {.owner = THIS_MODULE,},
 996         },
 997         {
 998                 .phy_id = MARVELL_PHY_ID_88E1121R,
 999                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1000                 .name = "Marvell 88E1121R",
1001                 .features = PHY_GBIT_FEATURES,
1002                 .flags = PHY_HAS_INTERRUPT,
1003                 .config_aneg = &m88e1121_config_aneg,
1004                 .read_status = &marvell_read_status,
1005                 .ack_interrupt = &marvell_ack_interrupt,
1006                 .config_intr = &marvell_config_intr,
1007                 .did_interrupt = &m88e1121_did_interrupt,
1008                 .resume = &genphy_resume,
1009                 .suspend = &genphy_suspend,
1010                 .driver = { .owner = THIS_MODULE },
1011         },
1012         {
1013                 .phy_id = MARVELL_PHY_ID_88E1318S,
1014                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1015                 .name = "Marvell 88E1318S",
1016                 .features = PHY_GBIT_FEATURES,
1017                 .flags = PHY_HAS_INTERRUPT,
1018                 .config_aneg = &m88e1318_config_aneg,
1019                 .read_status = &marvell_read_status,
1020                 .ack_interrupt = &marvell_ack_interrupt,
1021                 .config_intr = &marvell_config_intr,
1022                 .did_interrupt = &m88e1121_did_interrupt,
1023                 .get_wol = &m88e1318_get_wol,
1024                 .set_wol = &m88e1318_set_wol,
1025                 .resume = &genphy_resume,
1026                 .suspend = &genphy_suspend,
1027                 .driver = { .owner = THIS_MODULE },
1028         },
1029         {
1030                 .phy_id = MARVELL_PHY_ID_88E1145,
1031                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1032                 .name = "Marvell 88E1145",
1033                 .features = PHY_GBIT_FEATURES,
1034                 .flags = PHY_HAS_INTERRUPT,
1035                 .config_init = &m88e1145_config_init,
1036                 .config_aneg = &marvell_config_aneg,
1037                 .read_status = &genphy_read_status,
1038                 .ack_interrupt = &marvell_ack_interrupt,
1039                 .config_intr = &marvell_config_intr,
1040                 .resume = &genphy_resume,
1041                 .suspend = &genphy_suspend,
1042                 .driver = { .owner = THIS_MODULE },
1043         },
1044         {
1045                 .phy_id = MARVELL_PHY_ID_88E1149R,
1046                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1047                 .name = "Marvell 88E1149R",
1048                 .features = PHY_GBIT_FEATURES,
1049                 .flags = PHY_HAS_INTERRUPT,
1050                 .config_init = &m88e1149_config_init,
1051                 .config_aneg = &m88e1118_config_aneg,
1052                 .read_status = &genphy_read_status,
1053                 .ack_interrupt = &marvell_ack_interrupt,
1054                 .config_intr = &marvell_config_intr,
1055                 .resume = &genphy_resume,
1056                 .suspend = &genphy_suspend,
1057                 .driver = { .owner = THIS_MODULE },
1058         },
1059         {
1060                 .phy_id = MARVELL_PHY_ID_88E1240,
1061                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1062                 .name = "Marvell 88E1240",
1063                 .features = PHY_GBIT_FEATURES,
1064                 .flags = PHY_HAS_INTERRUPT,
1065                 .config_init = &m88e1111_config_init,
1066                 .config_aneg = &marvell_config_aneg,
1067                 .read_status = &genphy_read_status,
1068                 .ack_interrupt = &marvell_ack_interrupt,
1069                 .config_intr = &marvell_config_intr,
1070                 .resume = &genphy_resume,
1071                 .suspend = &genphy_suspend,
1072                 .driver = { .owner = THIS_MODULE },
1073         },
1074         {
1075                 .phy_id = MARVELL_PHY_ID_88E1116R,
1076                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1077                 .name = "Marvell 88E1116R",
1078                 .features = PHY_GBIT_FEATURES,
1079                 .flags = PHY_HAS_INTERRUPT,
1080                 .config_init = &m88e1116r_config_init,
1081                 .config_aneg = &genphy_config_aneg,
1082                 .read_status = &genphy_read_status,
1083                 .ack_interrupt = &marvell_ack_interrupt,
1084                 .config_intr = &marvell_config_intr,
1085                 .resume = &genphy_resume,
1086                 .suspend = &genphy_suspend,
1087                 .driver = { .owner = THIS_MODULE },
1088         },
1089         {
1090                 .phy_id = MARVELL_PHY_ID_88E1510,
1091                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1092                 .name = "Marvell 88E1510",
1093                 .features = PHY_GBIT_FEATURES,
1094                 .flags = PHY_HAS_INTERRUPT,
1095                 .config_aneg = &m88e1510_config_aneg,
1096                 .read_status = &marvell_read_status,
1097                 .ack_interrupt = &marvell_ack_interrupt,
1098                 .config_intr = &marvell_config_intr,
1099                 .did_interrupt = &m88e1121_did_interrupt,
1100                 .resume = &genphy_resume,
1101                 .suspend = &genphy_suspend,
1102                 .driver = { .owner = THIS_MODULE },
1103         },
1104         {
1105                 .phy_id = MARVELL_PHY_ID_88E3016,
1106                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1107                 .name = "Marvell 88E3016",
1108                 .features = PHY_BASIC_FEATURES,
1109                 .flags = PHY_HAS_INTERRUPT,
1110                 .config_aneg = &genphy_config_aneg,
1111                 .config_init = &m88e3016_config_init,
1112                 .aneg_done = &marvell_aneg_done,
1113                 .read_status = &marvell_read_status,
1114                 .ack_interrupt = &marvell_ack_interrupt,
1115                 .config_intr = &marvell_config_intr,
1116                 .did_interrupt = &m88e1121_did_interrupt,
1117                 .resume = &genphy_resume,
1118                 .suspend = &genphy_suspend,
1119                 .driver = { .owner = THIS_MODULE },
1120         },
1121 };
1122
1123 module_phy_driver(marvell_drivers);
1124
1125 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
1126         { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1127         { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1128         { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1129         { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1130         { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1131         { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1132         { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1133         { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1134         { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
1135         { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
1136         { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
1137         { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
1138         { }
1139 };
1140
1141 MODULE_DEVICE_TABLE(mdio, marvell_tbl);