kernel/drivers/net/phy/dp83640.c

   1 /*
   2  * Driver for the National Semiconductor DP83640 PHYTER
   3  *
   4  * Copyright (C) 2010 OMICRON electronics GmbH
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23 #include <linux/crc32.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/kernel.h>
  26 #include <linux/list.h>
  27 #include <linux/mii.h>
  28 #include <linux/module.h>
  29 #include <linux/net_tstamp.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/if_vlan.h>
  32 #include <linux/phy.h>
  33 #include <linux/ptp_classify.h>
  34 #include <linux/ptp_clock_kernel.h>
  35
  36 #include "dp83640_reg.h"
  37
  38 #define DP83640_PHY_ID  0x20005ce1
  39 #define PAGESEL         0x13
  40 #define MAX_RXTS        64
  41 #define N_EXT_TS        6
  42 #define N_PER_OUT       7
  43 #define PSF_PTPVER      2
  44 #define PSF_EVNT        0x4000
  45 #define PSF_RX          0x2000
  46 #define PSF_TX          0x1000
  47 #define EXT_EVENT       1
  48 #define CAL_EVENT       7
  49 #define CAL_TRIGGER     1
  50 #define DP83640_N_PINS  12
  51
  52 #define MII_DP83640_MICR 0x11
  53 #define MII_DP83640_MISR 0x12
  54
  55 #define MII_DP83640_MICR_OE 0x1
  56 #define MII_DP83640_MICR_IE 0x2
  57
  58 #define MII_DP83640_MISR_RHF_INT_EN 0x01
  59 #define MII_DP83640_MISR_FHF_INT_EN 0x02
  60 #define MII_DP83640_MISR_ANC_INT_EN 0x04
  61 #define MII_DP83640_MISR_DUP_INT_EN 0x08
  62 #define MII_DP83640_MISR_SPD_INT_EN 0x10
  63 #define MII_DP83640_MISR_LINK_INT_EN 0x20
  64 #define MII_DP83640_MISR_ED_INT_EN 0x40
  65 #define MII_DP83640_MISR_LQ_INT_EN 0x80
  66
  67 /* phyter seems to miss the mark by 16 ns */
  68 #define ADJTIME_FIX     16
  69
  70 #define SKB_TIMESTAMP_TIMEOUT   2 /* jiffies */
  71
  72 #if defined(__BIG_ENDIAN)
  73 #define ENDIAN_FLAG     0
  74 #elif defined(__LITTLE_ENDIAN)
  75 #define ENDIAN_FLAG     PSF_ENDIAN
  76 #endif
  77
  78 struct dp83640_skb_info {
  79         int ptp_type;
  80         unsigned long tmo;
  81 };
  82
  83 struct phy_rxts {
  84         u16 ns_lo;   /* ns[15:0] */
  85         u16 ns_hi;   /* overflow[1:0], ns[29:16] */
  86         u16 sec_lo;  /* sec[15:0] */
  87         u16 sec_hi;  /* sec[31:16] */
  88         u16 seqid;   /* sequenceId[15:0] */
  89         u16 msgtype; /* messageType[3:0], hash[11:0] */
  90 };
  91
  92 struct phy_txts {
  93         u16 ns_lo;   /* ns[15:0] */
  94         u16 ns_hi;   /* overflow[1:0], ns[29:16] */
  95         u16 sec_lo;  /* sec[15:0] */
  96         u16 sec_hi;  /* sec[31:16] */
  97 };
  98
  99 struct rxts {
 100         struct list_head list;
 101         unsigned long tmo;
 102         u64 ns;
 103         u16 seqid;
 104         u8  msgtype;
 105         u16 hash;
 106 };
 107
 108 struct dp83640_clock;
 109
 110 struct dp83640_private {
 111         struct list_head list;
 112         struct dp83640_clock *clock;
 113         struct phy_device *phydev;
 114         struct delayed_work ts_work;
 115         int hwts_tx_en;
 116         int hwts_rx_en;
 117         int layer;
 118         int version;
 119         /* remember state of cfg0 during calibration */
 120         int cfg0;
 121         /* remember the last event time stamp */
 122         struct phy_txts edata;
 123         /* list of rx timestamps */
 124         struct list_head rxts;
 125         struct list_head rxpool;
 126         struct rxts rx_pool_data[MAX_RXTS];
 127         /* protects above three fields from concurrent access */
 128         spinlock_t rx_lock;
 129         /* queues of incoming and outgoing packets */
 130         struct sk_buff_head rx_queue;
 131         struct sk_buff_head tx_queue;
 132 };
 133
 134 struct dp83640_clock {
 135         /* keeps the instance in the 'phyter_clocks' list */
 136         struct list_head list;
 137         /* we create one clock instance per MII bus */
 138         struct mii_bus *bus;
 139         /* protects extended registers from concurrent access */
 140         struct mutex extreg_lock;
 141         /* remembers which page was last selected */
 142         int page;
 143         /* our advertised capabilities */
 144         struct ptp_clock_info caps;
 145         /* protects the three fields below from concurrent access */
 146         struct mutex clock_lock;
 147         /* the one phyter from which we shall read */
 148         struct dp83640_private *chosen;
 149         /* list of the other attached phyters, not chosen */
 150         struct list_head phylist;
 151         /* reference to our PTP hardware clock */
 152         struct ptp_clock *ptp_clock;
 153 };
 154
 155 /* globals */
 156
 157 enum {
 158         CALIBRATE_GPIO,
 159         PEROUT_GPIO,
 160         EXTTS0_GPIO,
 161         EXTTS1_GPIO,
 162         EXTTS2_GPIO,
 163         EXTTS3_GPIO,
 164         EXTTS4_GPIO,
 165         EXTTS5_GPIO,
 166         GPIO_TABLE_SIZE
 167 };
 168
 169 static int chosen_phy = -1;
 170 static ushort gpio_tab[GPIO_TABLE_SIZE] = {
 171         1, 2, 3, 4, 8, 9, 10, 11
 172 };
 173
 174 module_param(chosen_phy, int, 0444);
 175 module_param_array(gpio_tab, ushort, NULL, 0444);
 176
 177 MODULE_PARM_DESC(chosen_phy, \
 178         "The address of the PHY to use for the ancillary clock features");
 179 MODULE_PARM_DESC(gpio_tab, \
 180         "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
 181
 182 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
 183 {
 184         int i, index;
 185
 186         for (i = 0; i < DP83640_N_PINS; i++) {
 187                 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
 188                 pd[i].index = i;
 189         }
 190
 191         for (i = 0; i < GPIO_TABLE_SIZE; i++) {
 192                 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
 193                         pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
 194                         return;
 195                 }
 196         }
 197
 198         index = gpio_tab[CALIBRATE_GPIO] - 1;
 199         pd[index].func = PTP_PF_PHYSYNC;
 200         pd[index].chan = 0;
 201
 202         index = gpio_tab[PEROUT_GPIO] - 1;
 203         pd[index].func = PTP_PF_PEROUT;
 204         pd[index].chan = 0;
 205
 206         for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
 207                 index = gpio_tab[i] - 1;
 208                 pd[index].func = PTP_PF_EXTTS;
 209                 pd[index].chan = i - EXTTS0_GPIO;
 210         }
 211 }
 212
 213 /* a list of clocks and a mutex to protect it */
 214 static LIST_HEAD(phyter_clocks);
 215 static DEFINE_MUTEX(phyter_clocks_lock);
 216
 217 static void rx_timestamp_work(struct work_struct *work);
 218
 219 /* extended register access functions */
 220
 221 #define BROADCAST_ADDR 31
 222
 223 static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
 224 {
 225         return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
 226 }
 227
 228 /* Caller must hold extreg_lock. */
 229 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
 230 {
 231         struct dp83640_private *dp83640 = phydev->priv;
 232         int val;
 233
 234         if (dp83640->clock->page != page) {
 235                 broadcast_write(phydev->bus, PAGESEL, page);
 236                 dp83640->clock->page = page;
 237         }
 238         val = phy_read(phydev, regnum);
 239
 240         return val;
 241 }
 242
 243 /* Caller must hold extreg_lock. */
 244 static void ext_write(int broadcast, struct phy_device *phydev,
 245                       int page, u32 regnum, u16 val)
 246 {
 247         struct dp83640_private *dp83640 = phydev->priv;
 248
 249         if (dp83640->clock->page != page) {
 250                 broadcast_write(phydev->bus, PAGESEL, page);
 251                 dp83640->clock->page = page;
 252         }
 253         if (broadcast)
 254                 broadcast_write(phydev->bus, regnum, val);
 255         else
 256                 phy_write(phydev, regnum, val);
 257 }
 258
 259 /* Caller must hold extreg_lock. */
 260 static int tdr_write(int bc, struct phy_device *dev,
 261                      const struct timespec64 *ts, u16 cmd)
 262 {
 263         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0]  */
 264         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16);   /* ns[31:16] */
 265         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
 266         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16);    /* sec[31:16]*/
 267
 268         ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
 269
 270         return 0;
 271 }
 272
 273 /* convert phy timestamps into driver timestamps */
 274
 275 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
 276 {
 277         u32 sec;
 278
 279         sec = p->sec_lo;
 280         sec |= p->sec_hi << 16;
 281
 282         rxts->ns = p->ns_lo;
 283         rxts->ns |= (p->ns_hi & 0x3fff) << 16;
 284         rxts->ns += ((u64)sec) * 1000000000ULL;
 285         rxts->seqid = p->seqid;
 286         rxts->msgtype = (p->msgtype >> 12) & 0xf;
 287         rxts->hash = p->msgtype & 0x0fff;
 288         rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
 289 }
 290
 291 static u64 phy2txts(struct phy_txts *p)
 292 {
 293         u64 ns;
 294         u32 sec;
 295
 296         sec = p->sec_lo;
 297         sec |= p->sec_hi << 16;
 298
 299         ns = p->ns_lo;
 300         ns |= (p->ns_hi & 0x3fff) << 16;
 301         ns += ((u64)sec) * 1000000000ULL;
 302
 303         return ns;
 304 }
 305
 306 static int periodic_output(struct dp83640_clock *clock,
 307                            struct ptp_clock_request *clkreq, bool on,
 308                            int trigger)
 309 {
 310         struct dp83640_private *dp83640 = clock->chosen;
 311         struct phy_device *phydev = dp83640->phydev;
 312         u32 sec, nsec, pwidth;
 313         u16 gpio, ptp_trig, val;
 314
 315         if (on) {
 316                 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
 317                                         trigger);
 318                 if (gpio < 1)
 319                         return -EINVAL;
 320         } else {
 321                 gpio = 0;
 322         }
 323
 324         ptp_trig = TRIG_WR |
 325                 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
 326                 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
 327                 TRIG_PER |
 328                 TRIG_PULSE;
 329
 330         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 331
 332         if (!on) {
 333                 val |= TRIG_DIS;
 334                 mutex_lock(&clock->extreg_lock);
 335                 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
 336                 ext_write(0, phydev, PAGE4, PTP_CTL, val);
 337                 mutex_unlock(&clock->extreg_lock);
 338                 return 0;
 339         }
 340
 341         sec = clkreq->perout.start.sec;
 342         nsec = clkreq->perout.start.nsec;
 343         pwidth = clkreq->perout.period.sec * 1000000000UL;
 344         pwidth += clkreq->perout.period.nsec;
 345         pwidth /= 2;
 346
 347         mutex_lock(&clock->extreg_lock);
 348
 349         ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
 350
 351         /*load trigger*/
 352         val |= TRIG_LOAD;
 353         ext_write(0, phydev, PAGE4, PTP_CTL, val);
 354         ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff);   /* ns[15:0] */
 355         ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16);      /* ns[31:16] */
 356         ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff);    /* sec[15:0] */
 357         ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16);       /* sec[31:16] */
 358         ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
 359         ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);    /* ns[31:16] */
 360         /* Triggers 0 and 1 has programmable pulsewidth2 */
 361         if (trigger < 2) {
 362                 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
 363                 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
 364         }
 365
 366         /*enable trigger*/
 367         val &= ~TRIG_LOAD;
 368         val |= TRIG_EN;
 369         ext_write(0, phydev, PAGE4, PTP_CTL, val);
 370
 371         mutex_unlock(&clock->extreg_lock);
 372         return 0;
 373 }
 374
 375 /* ptp clock methods */
 376
 377 static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 378 {
 379         struct dp83640_clock *clock =
 380                 container_of(ptp, struct dp83640_clock, caps);
 381         struct phy_device *phydev = clock->chosen->phydev;
 382         u64 rate;
 383         int neg_adj = 0;
 384         u16 hi, lo;
 385
 386         if (ppb < 0) {
 387                 neg_adj = 1;
 388                 ppb = -ppb;
 389         }
 390         rate = ppb;
 391         rate <<= 26;
 392         rate = div_u64(rate, 1953125);
 393
 394         hi = (rate >> 16) & PTP_RATE_HI_MASK;
 395         if (neg_adj)
 396                 hi |= PTP_RATE_DIR;
 397
 398         lo = rate & 0xffff;
 399
 400         mutex_lock(&clock->extreg_lock);
 401
 402         ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
 403         ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
 404
 405         mutex_unlock(&clock->extreg_lock);
 406
 407         return 0;
 408 }
 409
 410 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
 411 {
 412         struct dp83640_clock *clock =
 413                 container_of(ptp, struct dp83640_clock, caps);
 414         struct phy_device *phydev = clock->chosen->phydev;
 415         struct timespec64 ts;
 416         int err;
 417
 418         delta += ADJTIME_FIX;
 419
 420         ts = ns_to_timespec64(delta);
 421
 422         mutex_lock(&clock->extreg_lock);
 423
 424         err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
 425
 426         mutex_unlock(&clock->extreg_lock);
 427
 428         return err;
 429 }
 430
 431 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
 432                                struct timespec64 *ts)
 433 {
 434         struct dp83640_clock *clock =
 435                 container_of(ptp, struct dp83640_clock, caps);
 436         struct phy_device *phydev = clock->chosen->phydev;
 437         unsigned int val[4];
 438
 439         mutex_lock(&clock->extreg_lock);
 440
 441         ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
 442
 443         val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
 444         val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
 445         val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
 446         val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
 447
 448         mutex_unlock(&clock->extreg_lock);
 449
 450         ts->tv_nsec = val[0] | (val[1] << 16);
 451         ts->tv_sec  = val[2] | (val[3] << 16);
 452
 453         return 0;
 454 }
 455
 456 static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
 457                                const struct timespec64 *ts)
 458 {
 459         struct dp83640_clock *clock =
 460                 container_of(ptp, struct dp83640_clock, caps);
 461         struct phy_device *phydev = clock->chosen->phydev;
 462         int err;
 463
 464         mutex_lock(&clock->extreg_lock);
 465
 466         err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
 467
 468         mutex_unlock(&clock->extreg_lock);
 469
 470         return err;
 471 }
 472
 473 static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
 474                               struct ptp_clock_request *rq, int on)
 475 {
 476         struct dp83640_clock *clock =
 477                 container_of(ptp, struct dp83640_clock, caps);
 478         struct phy_device *phydev = clock->chosen->phydev;
 479         unsigned int index;
 480         u16 evnt, event_num, gpio_num;
 481
 482         switch (rq->type) {
 483         case PTP_CLK_REQ_EXTTS:
 484                 index = rq->extts.index;
 485                 if (index >= N_EXT_TS)
 486                         return -EINVAL;
 487                 event_num = EXT_EVENT + index;
 488                 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
 489                 if (on) {
 490                         gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
 491                                                     PTP_PF_EXTTS, index);
 492                         if (gpio_num < 1)
 493                                 return -EINVAL;
 494                         evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
 495                         if (rq->extts.flags & PTP_FALLING_EDGE)
 496                                 evnt |= EVNT_FALL;
 497                         else
 498                                 evnt |= EVNT_RISE;
 499                 }
 500                 mutex_lock(&clock->extreg_lock);
 501                 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
 502                 mutex_unlock(&clock->extreg_lock);
 503                 return 0;
 504
 505         case PTP_CLK_REQ_PEROUT:
 506                 if (rq->perout.index >= N_PER_OUT)
 507                         return -EINVAL;
 508                 return periodic_output(clock, rq, on, rq->perout.index);
 509
 510         default:
 511                 break;
 512         }
 513
 514         return -EOPNOTSUPP;
 515 }
 516
 517 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
 518                               enum ptp_pin_function func, unsigned int chan)
 519 {
 520         struct dp83640_clock *clock =
 521                 container_of(ptp, struct dp83640_clock, caps);
 522
 523         if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
 524             !list_empty(&clock->phylist))
 525                 return 1;
 526
 527         if (func == PTP_PF_PHYSYNC)
 528                 return 1;
 529
 530         return 0;
 531 }
 532
 533 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
 534 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
 535
 536 static void enable_status_frames(struct phy_device *phydev, bool on)
 537 {
 538         struct dp83640_private *dp83640 = phydev->priv;
 539         struct dp83640_clock *clock = dp83640->clock;
 540         u16 cfg0 = 0, ver;
 541
 542         if (on)
 543                 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
 544
 545         ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
 546
 547         mutex_lock(&clock->extreg_lock);
 548
 549         ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
 550         ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
 551
 552         mutex_unlock(&clock->extreg_lock);
 553
 554         if (!phydev->attached_dev) {
 555                 pr_warn("expected to find an attached netdevice\n");
 556                 return;
 557         }
 558
 559         if (on) {
 560                 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
 561                         pr_warn("failed to add mc address\n");
 562         } else {
 563                 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
 564                         pr_warn("failed to delete mc address\n");
 565         }
 566 }
 567
 568 static bool is_status_frame(struct sk_buff *skb, int type)
 569 {
 570         struct ethhdr *h = eth_hdr(skb);
 571
 572         if (PTP_CLASS_V2_L2 == type &&
 573             !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
 574                 return true;
 575         else
 576                 return false;
 577 }
 578
 579 static int expired(struct rxts *rxts)
 580 {
 581         return time_after(jiffies, rxts->tmo);
 582 }
 583
 584 /* Caller must hold rx_lock. */
 585 static void prune_rx_ts(struct dp83640_private *dp83640)
 586 {
 587         struct list_head *this, *next;
 588         struct rxts *rxts;
 589
 590         list_for_each_safe(this, next, &dp83640->rxts) {
 591                 rxts = list_entry(this, struct rxts, list);
 592                 if (expired(rxts)) {
 593                         list_del_init(&rxts->list);
 594                         list_add(&rxts->list, &dp83640->rxpool);
 595                 }
 596         }
 597 }
 598
 599 /* synchronize the phyters so they act as one clock */
 600
 601 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
 602 {
 603         int val;
 604         phy_write(phydev, PAGESEL, 0);
 605         val = phy_read(phydev, PHYCR2);
 606         if (on)
 607                 val |= BC_WRITE;
 608         else
 609                 val &= ~BC_WRITE;
 610         phy_write(phydev, PHYCR2, val);
 611         phy_write(phydev, PAGESEL, init_page);
 612 }
 613
 614 static void recalibrate(struct dp83640_clock *clock)
 615 {
 616         s64 now, diff;
 617         struct phy_txts event_ts;
 618         struct timespec64 ts;
 619         struct list_head *this;
 620         struct dp83640_private *tmp;
 621         struct phy_device *master = clock->chosen->phydev;
 622         u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
 623
 624         trigger = CAL_TRIGGER;
 625         cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
 626         if (cal_gpio < 1) {
 627                 pr_err("PHY calibration pin not available - PHY is not calibrated.");
 628                 return;
 629         }
 630
 631         mutex_lock(&clock->extreg_lock);
 632
 633         /*
 634          * enable broadcast, disable status frames, enable ptp clock
 635          */
 636         list_for_each(this, &clock->phylist) {
 637                 tmp = list_entry(this, struct dp83640_private, list);
 638                 enable_broadcast(tmp->phydev, clock->page, 1);
 639                 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
 640                 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
 641                 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
 642         }
 643         enable_broadcast(master, clock->page, 1);
 644         cfg0 = ext_read(master, PAGE5, PSF_CFG0);
 645         ext_write(0, master, PAGE5, PSF_CFG0, 0);
 646         ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
 647
 648         /*
 649          * enable an event timestamp
 650          */
 651         evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
 652         evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
 653         evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
 654
 655         list_for_each(this, &clock->phylist) {
 656                 tmp = list_entry(this, struct dp83640_private, list);
 657                 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
 658         }
 659         ext_write(0, master, PAGE5, PTP_EVNT, evnt);
 660
 661         /*
 662          * configure a trigger
 663          */
 664         ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
 665         ptp_trig |= (trigger  & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
 666         ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
 667         ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
 668
 669         /* load trigger */
 670         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 671         val |= TRIG_LOAD;
 672         ext_write(0, master, PAGE4, PTP_CTL, val);
 673
 674         /* enable trigger */
 675         val &= ~TRIG_LOAD;
 676         val |= TRIG_EN;
 677         ext_write(0, master, PAGE4, PTP_CTL, val);
 678
 679         /* disable trigger */
 680         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 681         val |= TRIG_DIS;
 682         ext_write(0, master, PAGE4, PTP_CTL, val);
 683
 684         /*
 685          * read out and correct offsets
 686          */
 687         val = ext_read(master, PAGE4, PTP_STS);
 688         pr_info("master PTP_STS  0x%04hx\n", val);
 689         val = ext_read(master, PAGE4, PTP_ESTS);
 690         pr_info("master PTP_ESTS 0x%04hx\n", val);
 691         event_ts.ns_lo  = ext_read(master, PAGE4, PTP_EDATA);
 692         event_ts.ns_hi  = ext_read(master, PAGE4, PTP_EDATA);
 693         event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
 694         event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
 695         now = phy2txts(&event_ts);
 696
 697         list_for_each(this, &clock->phylist) {
 698                 tmp = list_entry(this, struct dp83640_private, list);
 699                 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
 700                 pr_info("slave  PTP_STS  0x%04hx\n", val);
 701                 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
 702                 pr_info("slave  PTP_ESTS 0x%04hx\n", val);
 703                 event_ts.ns_lo  = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 704                 event_ts.ns_hi  = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 705                 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 706                 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 707                 diff = now - (s64) phy2txts(&event_ts);
 708                 pr_info("slave offset %lld nanoseconds\n", diff);
 709                 diff += ADJTIME_FIX;
 710                 ts = ns_to_timespec64(diff);
 711                 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
 712         }
 713
 714         /*
 715          * restore status frames
 716          */
 717         list_for_each(this, &clock->phylist) {
 718                 tmp = list_entry(this, struct dp83640_private, list);
 719                 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
 720         }
 721         ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
 722
 723         mutex_unlock(&clock->extreg_lock);
 724 }
 725
 726 /* time stamping methods */
 727
 728 static inline u16 exts_chan_to_edata(int ch)
 729 {
 730         return 1 << ((ch + EXT_EVENT) * 2);
 731 }
 732
 733 static int decode_evnt(struct dp83640_private *dp83640,
 734                        void *data, int len, u16 ests)
 735 {
 736         struct phy_txts *phy_txts;
 737         struct ptp_clock_event event;
 738         int i, parsed;
 739         int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
 740         u16 ext_status = 0;
 741
 742         /* calculate length of the event timestamp status message */
 743         if (ests & MULT_EVNT)
 744                 parsed = (words + 2) * sizeof(u16);
 745         else
 746                 parsed = (words + 1) * sizeof(u16);
 747
 748         /* check if enough data is available */
 749         if (len < parsed)
 750                 return len;
 751
 752         if (ests & MULT_EVNT) {
 753                 ext_status = *(u16 *) data;
 754                 data += sizeof(ext_status);
 755         }
 756
 757         phy_txts = data;
 758
 759         switch (words) { /* fall through in every case */
 760         case 3:
 761                 dp83640->edata.sec_hi = phy_txts->sec_hi;
 762         case 2:
 763                 dp83640->edata.sec_lo = phy_txts->sec_lo;
 764         case 1:
 765                 dp83640->edata.ns_hi = phy_txts->ns_hi;
 766         case 0:
 767                 dp83640->edata.ns_lo = phy_txts->ns_lo;
 768         }
 769
 770         if (!ext_status) {
 771                 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
 772                 ext_status = exts_chan_to_edata(i);
 773         }
 774
 775         event.type = PTP_CLOCK_EXTTS;
 776         event.timestamp = phy2txts(&dp83640->edata);
 777
 778         /* Compensate for input path and synchronization delays */
 779         event.timestamp -= 35;
 780
 781         for (i = 0; i < N_EXT_TS; i++) {
 782                 if (ext_status & exts_chan_to_edata(i)) {
 783                         event.index = i;
 784                         ptp_clock_event(dp83640->clock->ptp_clock, &event);
 785                 }
 786         }
 787
 788         return parsed;
 789 }
 790
 791 #define DP83640_PACKET_HASH_OFFSET      20
 792 #define DP83640_PACKET_HASH_LEN         10
 793
 794 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
 795 {
 796         u16 *seqid, hash;
 797         unsigned int offset = 0;
 798         u8 *msgtype, *data = skb_mac_header(skb);
 799
 800         /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
 801
 802         if (type & PTP_CLASS_VLAN)
 803                 offset += VLAN_HLEN;
 804
 805         switch (type & PTP_CLASS_PMASK) {
 806         case PTP_CLASS_IPV4:
 807                 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
 808                 break;
 809         case PTP_CLASS_IPV6:
 810                 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
 811                 break;
 812         case PTP_CLASS_L2:
 813                 offset += ETH_HLEN;
 814                 break;
 815         default:
 816                 return 0;
 817         }
 818
 819         if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
 820                 return 0;
 821
 822         if (unlikely(type & PTP_CLASS_V1))
 823                 msgtype = data + offset + OFF_PTP_CONTROL;
 824         else
 825                 msgtype = data + offset;
 826         if (rxts->msgtype != (*msgtype & 0xf))
 827                 return 0;
 828
 829         seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
 830         if (rxts->seqid != ntohs(*seqid))
 831                 return 0;
 832
 833         hash = ether_crc(DP83640_PACKET_HASH_LEN,
 834                          data + offset + DP83640_PACKET_HASH_OFFSET) >> 20;
 835         if (rxts->hash != hash)
 836                 return 0;
 837
 838         return 1;
 839 }
 840
 841 static void decode_rxts(struct dp83640_private *dp83640,
 842                         struct phy_rxts *phy_rxts)
 843 {
 844         struct rxts *rxts;
 845         struct skb_shared_hwtstamps *shhwtstamps = NULL;
 846         struct sk_buff *skb;
 847         unsigned long flags;
 848         u8 overflow;
 849
 850         overflow = (phy_rxts->ns_hi >> 14) & 0x3;
 851         if (overflow)
 852                 pr_debug("rx timestamp queue overflow, count %d\n", overflow);
 853
 854         spin_lock_irqsave(&dp83640->rx_lock, flags);
 855
 856         prune_rx_ts(dp83640);
 857
 858         if (list_empty(&dp83640->rxpool)) {
 859                 pr_debug("rx timestamp pool is empty\n");
 860                 goto out;
 861         }
 862         rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
 863         list_del_init(&rxts->list);
 864         phy2rxts(phy_rxts, rxts);
 865
 866         spin_lock(&dp83640->rx_queue.lock);
 867         skb_queue_walk(&dp83640->rx_queue, skb) {
 868                 struct dp83640_skb_info *skb_info;
 869
 870                 skb_info = (struct dp83640_skb_info *)skb->cb;
 871                 if (match(skb, skb_info->ptp_type, rxts)) {
 872                         __skb_unlink(skb, &dp83640->rx_queue);
 873                         shhwtstamps = skb_hwtstamps(skb);
 874                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 875                         shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
 876                         netif_rx_ni(skb);
 877                         list_add(&rxts->list, &dp83640->rxpool);
 878                         break;
 879                 }
 880         }
 881         spin_unlock(&dp83640->rx_queue.lock);
 882
 883         if (!shhwtstamps)
 884                 list_add_tail(&rxts->list, &dp83640->rxts);
 885 out:
 886         spin_unlock_irqrestore(&dp83640->rx_lock, flags);
 887 }
 888
 889 static void decode_txts(struct dp83640_private *dp83640,
 890                         struct phy_txts *phy_txts)
 891 {
 892         struct skb_shared_hwtstamps shhwtstamps;
 893         struct sk_buff *skb;
 894         u64 ns;
 895         u8 overflow;
 896
 897         /* We must already have the skb that triggered this. */
 898
 899         skb = skb_dequeue(&dp83640->tx_queue);
 900
 901         if (!skb) {
 902                 pr_debug("have timestamp but tx_queue empty\n");
 903                 return;
 904         }
 905
 906         overflow = (phy_txts->ns_hi >> 14) & 0x3;
 907         if (overflow) {
 908                 pr_debug("tx timestamp queue overflow, count %d\n", overflow);
 909                 while (skb) {
 910                         skb_complete_tx_timestamp(skb, NULL);
 911                         skb = skb_dequeue(&dp83640->tx_queue);
 912                 }
 913                 return;
 914         }
 915
 916         ns = phy2txts(phy_txts);
 917         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 918         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 919         skb_complete_tx_timestamp(skb, &shhwtstamps);
 920 }
 921
 922 static void decode_status_frame(struct dp83640_private *dp83640,
 923                                 struct sk_buff *skb)
 924 {
 925         struct phy_rxts *phy_rxts;
 926         struct phy_txts *phy_txts;
 927         u8 *ptr;
 928         int len, size;
 929         u16 ests, type;
 930
 931         ptr = skb->data + 2;
 932
 933         for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
 934
 935                 type = *(u16 *)ptr;
 936                 ests = type & 0x0fff;
 937                 type = type & 0xf000;
 938                 len -= sizeof(type);
 939                 ptr += sizeof(type);
 940
 941                 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
 942
 943                         phy_rxts = (struct phy_rxts *) ptr;
 944                         decode_rxts(dp83640, phy_rxts);
 945                         size = sizeof(*phy_rxts);
 946
 947                 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
 948
 949                         phy_txts = (struct phy_txts *) ptr;
 950                         decode_txts(dp83640, phy_txts);
 951                         size = sizeof(*phy_txts);
 952
 953                 } else if (PSF_EVNT == type) {
 954
 955                         size = decode_evnt(dp83640, ptr, len, ests);
 956
 957                 } else {
 958                         size = 0;
 959                         break;
 960                 }
 961                 ptr += size;
 962         }
 963 }
 964
 965 static int is_sync(struct sk_buff *skb, int type)
 966 {
 967         u8 *data = skb->data, *msgtype;
 968         unsigned int offset = 0;
 969
 970         if (type & PTP_CLASS_VLAN)
 971                 offset += VLAN_HLEN;
 972
 973         switch (type & PTP_CLASS_PMASK) {
 974         case PTP_CLASS_IPV4:
 975                 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
 976                 break;
 977         case PTP_CLASS_IPV6:
 978                 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
 979                 break;
 980         case PTP_CLASS_L2:
 981                 offset += ETH_HLEN;
 982                 break;
 983         default:
 984                 return 0;
 985         }
 986
 987         if (type & PTP_CLASS_V1)
 988                 offset += OFF_PTP_CONTROL;
 989
 990         if (skb->len < offset + 1)
 991                 return 0;
 992
 993         msgtype = data + offset;
 994
 995         return (*msgtype & 0xf) == 0;
 996 }
 997
 998 static void dp83640_free_clocks(void)
 999 {
1000         struct dp83640_clock *clock;
1001         struct list_head *this, *next;
1002
1003         mutex_lock(&phyter_clocks_lock);
1004
1005         list_for_each_safe(this, next, &phyter_clocks) {
1006                 clock = list_entry(this, struct dp83640_clock, list);
1007                 if (!list_empty(&clock->phylist)) {
1008                         pr_warn("phy list non-empty while unloading\n");
1009                         BUG();
1010                 }
1011                 list_del(&clock->list);
1012                 mutex_destroy(&clock->extreg_lock);
1013                 mutex_destroy(&clock->clock_lock);
1014                 put_device(&clock->bus->dev);
1015                 kfree(clock->caps.pin_config);
1016                 kfree(clock);
1017         }
1018
1019         mutex_unlock(&phyter_clocks_lock);
1020 }
1021
1022 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
1023 {
1024         INIT_LIST_HEAD(&clock->list);
1025         clock->bus = bus;
1026         mutex_init(&clock->extreg_lock);
1027         mutex_init(&clock->clock_lock);
1028         INIT_LIST_HEAD(&clock->phylist);
1029         clock->caps.owner = THIS_MODULE;
1030         sprintf(clock->caps.name, "dp83640 timer");
1031         clock->caps.max_adj     = 1953124;
1032         clock->caps.n_alarm     = 0;
1033         clock->caps.n_ext_ts    = N_EXT_TS;
1034         clock->caps.n_per_out   = N_PER_OUT;
1035         clock->caps.n_pins      = DP83640_N_PINS;
1036         clock->caps.pps         = 0;
1037         clock->caps.adjfreq     = ptp_dp83640_adjfreq;
1038         clock->caps.adjtime     = ptp_dp83640_adjtime;
1039         clock->caps.gettime64   = ptp_dp83640_gettime;
1040         clock->caps.settime64   = ptp_dp83640_settime;
1041         clock->caps.enable      = ptp_dp83640_enable;
1042         clock->caps.verify      = ptp_dp83640_verify;
1043         /*
1044          * Convert the module param defaults into a dynamic pin configuration.
1045          */
1046         dp83640_gpio_defaults(clock->caps.pin_config);
1047         /*
1048          * Get a reference to this bus instance.
1049          */
1050         get_device(&bus->dev);
1051 }
1052
1053 static int choose_this_phy(struct dp83640_clock *clock,
1054                            struct phy_device *phydev)
1055 {
1056         if (chosen_phy == -1 && !clock->chosen)
1057                 return 1;
1058
1059         if (chosen_phy == phydev->addr)
1060                 return 1;
1061
1062         return 0;
1063 }
1064
1065 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1066 {
1067         if (clock)
1068                 mutex_lock(&clock->clock_lock);
1069         return clock;
1070 }
1071
1072 /*
1073  * Look up and lock a clock by bus instance.
1074  * If there is no clock for this bus, then create it first.
1075  */
1076 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1077 {
1078         struct dp83640_clock *clock = NULL, *tmp;
1079         struct list_head *this;
1080
1081         mutex_lock(&phyter_clocks_lock);
1082
1083         list_for_each(this, &phyter_clocks) {
1084                 tmp = list_entry(this, struct dp83640_clock, list);
1085                 if (tmp->bus == bus) {
1086                         clock = tmp;
1087                         break;
1088                 }
1089         }
1090         if (clock)
1091                 goto out;
1092
1093         clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1094         if (!clock)
1095                 goto out;
1096
1097         clock->caps.pin_config = kzalloc(sizeof(struct ptp_pin_desc) *
1098                                          DP83640_N_PINS, GFP_KERNEL);
1099         if (!clock->caps.pin_config) {
1100                 kfree(clock);
1101                 clock = NULL;
1102                 goto out;
1103         }
1104         dp83640_clock_init(clock, bus);
1105         list_add_tail(&phyter_clocks, &clock->list);
1106 out:
1107         mutex_unlock(&phyter_clocks_lock);
1108
1109         return dp83640_clock_get(clock);
1110 }
1111
1112 static void dp83640_clock_put(struct dp83640_clock *clock)
1113 {
1114         mutex_unlock(&clock->clock_lock);
1115 }
1116
1117 static int dp83640_probe(struct phy_device *phydev)
1118 {
1119         struct dp83640_clock *clock;
1120         struct dp83640_private *dp83640;
1121         int err = -ENOMEM, i;
1122
1123         if (phydev->addr == BROADCAST_ADDR)
1124                 return 0;
1125
1126         clock = dp83640_clock_get_bus(phydev->bus);
1127         if (!clock)
1128                 goto no_clock;
1129
1130         dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1131         if (!dp83640)
1132                 goto no_memory;
1133
1134         dp83640->phydev = phydev;
1135         INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
1136
1137         INIT_LIST_HEAD(&dp83640->rxts);
1138         INIT_LIST_HEAD(&dp83640->rxpool);
1139         for (i = 0; i < MAX_RXTS; i++)
1140                 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1141
1142         phydev->priv = dp83640;
1143
1144         spin_lock_init(&dp83640->rx_lock);
1145         skb_queue_head_init(&dp83640->rx_queue);
1146         skb_queue_head_init(&dp83640->tx_queue);
1147
1148         dp83640->clock = clock;
1149
1150         if (choose_this_phy(clock, phydev)) {
1151                 clock->chosen = dp83640;
1152                 clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev);
1153                 if (IS_ERR(clock->ptp_clock)) {
1154                         err = PTR_ERR(clock->ptp_clock);
1155                         goto no_register;
1156                 }
1157         } else
1158                 list_add_tail(&dp83640->list, &clock->phylist);
1159
1160         dp83640_clock_put(clock);
1161         return 0;
1162
1163 no_register:
1164         clock->chosen = NULL;
1165         kfree(dp83640);
1166 no_memory:
1167         dp83640_clock_put(clock);
1168 no_clock:
1169         return err;
1170 }
1171
1172 static void dp83640_remove(struct phy_device *phydev)
1173 {
1174         struct dp83640_clock *clock;
1175         struct list_head *this, *next;
1176         struct dp83640_private *tmp, *dp83640 = phydev->priv;
1177
1178         if (phydev->addr == BROADCAST_ADDR)
1179                 return;
1180
1181         enable_status_frames(phydev, false);
1182         cancel_delayed_work_sync(&dp83640->ts_work);
1183
1184         skb_queue_purge(&dp83640->rx_queue);
1185         skb_queue_purge(&dp83640->tx_queue);
1186
1187         clock = dp83640_clock_get(dp83640->clock);
1188
1189         if (dp83640 == clock->chosen) {
1190                 ptp_clock_unregister(clock->ptp_clock);
1191                 clock->chosen = NULL;
1192         } else {
1193                 list_for_each_safe(this, next, &clock->phylist) {
1194                         tmp = list_entry(this, struct dp83640_private, list);
1195                         if (tmp == dp83640) {
1196                                 list_del_init(&tmp->list);
1197                                 break;
1198                         }
1199                 }
1200         }
1201
1202         dp83640_clock_put(clock);
1203         kfree(dp83640);
1204 }
1205
1206 static int dp83640_config_init(struct phy_device *phydev)
1207 {
1208         struct dp83640_private *dp83640 = phydev->priv;
1209         struct dp83640_clock *clock = dp83640->clock;
1210
1211         if (clock->chosen && !list_empty(&clock->phylist))
1212                 recalibrate(clock);
1213         else {
1214                 mutex_lock(&clock->extreg_lock);
1215                 enable_broadcast(phydev, clock->page, 1);
1216                 mutex_unlock(&clock->extreg_lock);
1217         }
1218
1219         enable_status_frames(phydev, true);
1220
1221         mutex_lock(&clock->extreg_lock);
1222         ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1223         mutex_unlock(&clock->extreg_lock);
1224
1225         return 0;
1226 }
1227
1228 static int dp83640_ack_interrupt(struct phy_device *phydev)
1229 {
1230         int err = phy_read(phydev, MII_DP83640_MISR);
1231
1232         if (err < 0)
1233                 return err;
1234
1235         return 0;
1236 }
1237
1238 static int dp83640_config_intr(struct phy_device *phydev)
1239 {
1240         int micr;
1241         int misr;
1242         int err;
1243
1244         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1245                 misr = phy_read(phydev, MII_DP83640_MISR);
1246                 if (misr < 0)
1247                         return misr;
1248                 misr |=
1249                         (MII_DP83640_MISR_ANC_INT_EN |
1250                         MII_DP83640_MISR_DUP_INT_EN |
1251                         MII_DP83640_MISR_SPD_INT_EN |
1252                         MII_DP83640_MISR_LINK_INT_EN);
1253                 err = phy_write(phydev, MII_DP83640_MISR, misr);
1254                 if (err < 0)
1255                         return err;
1256
1257                 micr = phy_read(phydev, MII_DP83640_MICR);
1258                 if (micr < 0)
1259                         return micr;
1260                 micr |=
1261                         (MII_DP83640_MICR_OE |
1262                         MII_DP83640_MICR_IE);
1263                 return phy_write(phydev, MII_DP83640_MICR, micr);
1264         } else {
1265                 micr = phy_read(phydev, MII_DP83640_MICR);
1266                 if (micr < 0)
1267                         return micr;
1268                 micr &=
1269                         ~(MII_DP83640_MICR_OE |
1270                         MII_DP83640_MICR_IE);
1271                 err = phy_write(phydev, MII_DP83640_MICR, micr);
1272                 if (err < 0)
1273                         return err;
1274
1275                 misr = phy_read(phydev, MII_DP83640_MISR);
1276                 if (misr < 0)
1277                         return misr;
1278                 misr &=
1279                         ~(MII_DP83640_MISR_ANC_INT_EN |
1280                         MII_DP83640_MISR_DUP_INT_EN |
1281                         MII_DP83640_MISR_SPD_INT_EN |
1282                         MII_DP83640_MISR_LINK_INT_EN);
1283                 return phy_write(phydev, MII_DP83640_MISR, misr);
1284         }
1285 }
1286
1287 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1288 {
1289         struct dp83640_private *dp83640 = phydev->priv;
1290         struct hwtstamp_config cfg;
1291         u16 txcfg0, rxcfg0;
1292
1293         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1294                 return -EFAULT;
1295
1296         if (cfg.flags) /* reserved for future extensions */
1297                 return -EINVAL;
1298
1299         if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1300                 return -ERANGE;
1301
1302         dp83640->hwts_tx_en = cfg.tx_type;
1303
1304         switch (cfg.rx_filter) {
1305         case HWTSTAMP_FILTER_NONE:
1306                 dp83640->hwts_rx_en = 0;
1307                 dp83640->layer = 0;
1308                 dp83640->version = 0;
1309                 break;
1310         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1311         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1312         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1313                 dp83640->hwts_rx_en = 1;
1314                 dp83640->layer = PTP_CLASS_L4;
1315                 dp83640->version = PTP_CLASS_V1;
1316                 break;
1317         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1318         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1319         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1320                 dp83640->hwts_rx_en = 1;
1321                 dp83640->layer = PTP_CLASS_L4;
1322                 dp83640->version = PTP_CLASS_V2;
1323                 break;
1324         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1325         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1326         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1327                 dp83640->hwts_rx_en = 1;
1328                 dp83640->layer = PTP_CLASS_L2;
1329                 dp83640->version = PTP_CLASS_V2;
1330                 break;
1331         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1332         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1333         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1334                 dp83640->hwts_rx_en = 1;
1335                 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
1336                 dp83640->version = PTP_CLASS_V2;
1337                 break;
1338         default:
1339                 return -ERANGE;
1340         }
1341
1342         txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1343         rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1344
1345         if (dp83640->layer & PTP_CLASS_L2) {
1346                 txcfg0 |= TX_L2_EN;
1347                 rxcfg0 |= RX_L2_EN;
1348         }
1349         if (dp83640->layer & PTP_CLASS_L4) {
1350                 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1351                 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1352         }
1353
1354         if (dp83640->hwts_tx_en)
1355                 txcfg0 |= TX_TS_EN;
1356
1357         if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1358                 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1359
1360         if (dp83640->hwts_rx_en)
1361                 rxcfg0 |= RX_TS_EN;
1362
1363         mutex_lock(&dp83640->clock->extreg_lock);
1364
1365         ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
1366         ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1367
1368         mutex_unlock(&dp83640->clock->extreg_lock);
1369
1370         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1371 }
1372
1373 static void rx_timestamp_work(struct work_struct *work)
1374 {
1375         struct dp83640_private *dp83640 =
1376                 container_of(work, struct dp83640_private, ts_work.work);
1377         struct sk_buff *skb;
1378
1379         /* Deliver expired packets. */
1380         while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1381                 struct dp83640_skb_info *skb_info;
1382
1383                 skb_info = (struct dp83640_skb_info *)skb->cb;
1384                 if (!time_after(jiffies, skb_info->tmo)) {
1385                         skb_queue_head(&dp83640->rx_queue, skb);
1386                         break;
1387                 }
1388
1389                 netif_rx_ni(skb);
1390         }
1391
1392         if (!skb_queue_empty(&dp83640->rx_queue))
1393                 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1394 }
1395
1396 static bool dp83640_rxtstamp(struct phy_device *phydev,
1397                              struct sk_buff *skb, int type)
1398 {
1399         struct dp83640_private *dp83640 = phydev->priv;
1400         struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1401         struct list_head *this, *next;
1402         struct rxts *rxts;
1403         struct skb_shared_hwtstamps *shhwtstamps = NULL;
1404         unsigned long flags;
1405
1406         if (is_status_frame(skb, type)) {
1407                 decode_status_frame(dp83640, skb);
1408                 kfree_skb(skb);
1409                 return true;
1410         }
1411
1412         if (!dp83640->hwts_rx_en)
1413                 return false;
1414
1415         if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)
1416                 return false;
1417
1418         spin_lock_irqsave(&dp83640->rx_lock, flags);
1419         prune_rx_ts(dp83640);
1420         list_for_each_safe(this, next, &dp83640->rxts) {
1421                 rxts = list_entry(this, struct rxts, list);
1422                 if (match(skb, type, rxts)) {
1423                         shhwtstamps = skb_hwtstamps(skb);
1424                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1425                         shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1426                         netif_rx_ni(skb);
1427                         list_del_init(&rxts->list);
1428                         list_add(&rxts->list, &dp83640->rxpool);
1429                         break;
1430                 }
1431         }
1432         spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1433
1434         if (!shhwtstamps) {
1435                 skb_info->ptp_type = type;
1436                 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1437                 skb_queue_tail(&dp83640->rx_queue, skb);
1438                 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1439         } else {
1440                 netif_rx_ni(skb);
1441         }
1442
1443         return true;
1444 }
1445
1446 static void dp83640_txtstamp(struct phy_device *phydev,
1447                              struct sk_buff *skb, int type)
1448 {
1449         struct dp83640_private *dp83640 = phydev->priv;
1450
1451         switch (dp83640->hwts_tx_en) {
1452
1453         case HWTSTAMP_TX_ONESTEP_SYNC:
1454                 if (is_sync(skb, type)) {
1455                         kfree_skb(skb);
1456                         return;
1457                 }
1458                 /* fall through */
1459         case HWTSTAMP_TX_ON:
1460                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1461                 skb_queue_tail(&dp83640->tx_queue, skb);
1462                 break;
1463
1464         case HWTSTAMP_TX_OFF:
1465         default:
1466                 kfree_skb(skb);
1467                 break;
1468         }
1469 }
1470
1471 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info)
1472 {
1473         struct dp83640_private *dp83640 = dev->priv;
1474
1475         info->so_timestamping =
1476                 SOF_TIMESTAMPING_TX_HARDWARE |
1477                 SOF_TIMESTAMPING_RX_HARDWARE |
1478                 SOF_TIMESTAMPING_RAW_HARDWARE;
1479         info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1480         info->tx_types =
1481                 (1 << HWTSTAMP_TX_OFF) |
1482                 (1 << HWTSTAMP_TX_ON) |
1483                 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1484         info->rx_filters =
1485                 (1 << HWTSTAMP_FILTER_NONE) |
1486                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1487                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1488                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1489                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1490         return 0;
1491 }
1492
1493 static struct phy_driver dp83640_driver = {
1494         .phy_id         = DP83640_PHY_ID,
1495         .phy_id_mask    = 0xfffffff0,
1496         .name           = "NatSemi DP83640",
1497         .features       = PHY_BASIC_FEATURES,
1498         .flags          = PHY_HAS_INTERRUPT,
1499         .probe          = dp83640_probe,
1500         .remove         = dp83640_remove,
1501         .config_init    = dp83640_config_init,
1502         .config_aneg    = genphy_config_aneg,
1503         .read_status    = genphy_read_status,
1504         .ack_interrupt  = dp83640_ack_interrupt,
1505         .config_intr    = dp83640_config_intr,
1506         .ts_info        = dp83640_ts_info,
1507         .hwtstamp       = dp83640_hwtstamp,
1508         .rxtstamp       = dp83640_rxtstamp,
1509         .txtstamp       = dp83640_txtstamp,
1510         .driver         = {.owner = THIS_MODULE,}
1511 };
1512
1513 static int __init dp83640_init(void)
1514 {
1515         return phy_driver_register(&dp83640_driver);
1516 }
1517
1518 static void __exit dp83640_exit(void)
1519 {
1520         dp83640_free_clocks();
1521         phy_driver_unregister(&dp83640_driver);
1522 }
1523
1524 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1525 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1526 MODULE_LICENSE("GPL");
1527
1528 module_init(dp83640_init);
1529 module_exit(dp83640_exit);
1530
1531 static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1532         { DP83640_PHY_ID, 0xfffffff0 },
1533         { }
1534 };
1535
1536 MODULE_DEVICE_TABLE(mdio, dp83640_tbl);