kernel/drivers/net/irda/smsc-sio.h

   1 #ifndef SMSC_SIO_H
   2 #define SMSC_SIO_H
   3
   4 /******************************************
   5  Keys. They should work with every SMsC SIO
   6  ******************************************/
   7
   8 #define SMSCSIO_CFGACCESSKEY            0x55
   9 #define SMSCSIO_CFGEXITKEY                      0xaa
  10
  11 /*****************************
  12  * Generic SIO Flat (!?)     *
  13  *****************************/
  14
  15 /* Register 0x0d */
  16 #define SMSCSIOFLAT_DEVICEID_REG                                0x0d
  17
  18 /* Register 0x0c */
  19 #define SMSCSIOFLAT_UARTMODE0C_REG                              0x0c
  20 #define         SMSCSIOFLAT_UART2MODE_MASK                      0x38
  21 #define         SMSCSIOFLAT_UART2MODE_VAL_COM           0x00
  22 #define         SMSCSIOFLAT_UART2MODE_VAL_IRDA          0x08
  23 #define         SMSCSIOFLAT_UART2MODE_VAL_ASKIR         0x10
  24
  25 /* Register 0x25 */
  26 #define SMSCSIOFLAT_UART2BASEADDR_REG                   0x25
  27
  28 /* Register 0x2b */
  29 #define SMSCSIOFLAT_FIRBASEADDR_REG                             0x2b
  30
  31 /* Register 0x2c */
  32 #define SMSCSIOFLAT_FIRDMASELECT_REG                    0x2c
  33 #define         SMSCSIOFLAT_FIRDMASELECT_MASK           0x0f
  34
  35 /* Register 0x28 */
  36 #define SMSCSIOFLAT_UARTIRQSELECT_REG                   0x28
  37 #define         SMSCSIOFLAT_UART2IRQSELECT_MASK         0x0f
  38 #define         SMSCSIOFLAT_UART1IRQSELECT_MASK         0xf0
  39 #define         SMSCSIOFLAT_UARTIRQSELECT_VAL_NONE      0x00
  40
  41
  42 /*********************
  43  * LPC47N227         *
  44  *********************/
  45
  46 #define LPC47N227_CFGACCESSKEY          0x55
  47 #define LPC47N227_CFGEXITKEY            0xaa
  48
  49 /* Register 0x00 */
  50 #define LPC47N227_FDCPOWERVALIDCONF_REG         0x00
  51 #define         LPC47N227_FDCPOWER_MASK                 0x08
  52 #define         LPC47N227_VALID_MASK                            0x80
  53
  54 /* Register 0x02 */
  55 #define LPC47N227_UART12POWER_REG                               0x02
  56 #define         LPC47N227_UART1POWERDOWN_MASK           0x08
  57 #define         LPC47N227_UART2POWERDOWN_MASK           0x80
  58
  59 /* Register 0x07 */
  60 #define LPC47N227_APMBOOTDRIVE_REG                              0x07
  61 #define         LPC47N227_PARPORT2AUTOPWRDOWN_MASK      0x10 /* auto power down on if set */
  62 #define         LPC47N227_UART2AUTOPWRDOWN_MASK 0x20 /* auto power down on if set */
  63 #define         LPC47N227_UART1AUTOPWRDOWN_MASK 0x40 /* auto power down on if set */
  64
  65 /* Register 0x0c */
  66 #define LPC47N227_UARTMODE0C_REG                                0x0c
  67 #define         LPC47N227_UART2MODE_MASK                        0x38
  68 #define         LPC47N227_UART2MODE_VAL_COM             0x00
  69 #define         LPC47N227_UART2MODE_VAL_IRDA            0x08
  70 #define         LPC47N227_UART2MODE_VAL_ASKIR           0x10
  71
  72 /* Register 0x0d */
  73 #define LPC47N227_DEVICEID_REG                                  0x0d
  74 #define         LPC47N227_DEVICEID_DEFVAL                       0x5a
  75
  76 /* Register 0x0e */
  77 #define LPC47N227_REVISIONID_REG                                0x0e
  78
  79 /* Register 0x25 */
  80 #define LPC47N227_UART2BASEADDR_REG                     0x25
  81
  82 /* Register 0x28 */
  83 #define LPC47N227_UARTIRQSELECT_REG                     0x28
  84 #define         LPC47N227_UART2IRQSELECT_MASK           0x0f
  85 #define         LPC47N227_UART1IRQSELECT_MASK           0xf0
  86 #define         LPC47N227_UARTIRQSELECT_VAL_NONE        0x00
  87
  88 /* Register 0x2b */
  89 #define LPC47N227_FIRBASEADDR_REG                               0x2b
  90
  91 /* Register 0x2c */
  92 #define LPC47N227_FIRDMASELECT_REG                              0x2c
  93 #define         LPC47N227_FIRDMASELECT_MASK             0x0f
  94 #define         LPC47N227_FIRDMASELECT_VAL_DMA1 0x01 /* 47n227 has three dma channels */
  95 #define         LPC47N227_FIRDMASELECT_VAL_DMA2 0x02
  96 #define         LPC47N227_FIRDMASELECT_VAL_DMA3 0x03
  97 #define         LPC47N227_FIRDMASELECT_VAL_NONE 0x0f
  98
  99
 100 #endif