kernel/drivers/net/irda/ali-ircc.c

   1 /*********************************************************************
   2  *
   3  * Filename:      ali-ircc.h
   4  * Version:       0.5
   5  * Description:   Driver for the ALI M1535D and M1543C FIR Controller
   6  * Status:        Experimental.
   7  * Author:        Benjamin Kong <benjamin_kong@ali.com.tw>
   8  * Created at:    2000/10/16 03:46PM
   9  * Modified at:   2001/1/3 02:55PM
  10  * Modified by:   Benjamin Kong <benjamin_kong@ali.com.tw>
  11  * Modified at:   2003/11/6 and support for ALi south-bridge chipsets M1563
  12  * Modified by:   Clear Zhang <clear_zhang@ali.com.tw>
  13  *
  14  *     Copyright (c) 2000 Benjamin Kong <benjamin_kong@ali.com.tw>
  15  *     All Rights Reserved
  16  *
  17  *     This program is free software; you can redistribute it and/or
  18  *     modify it under the terms of the GNU General Public License as
  19  *     published by the Free Software Foundation; either version 2 of
  20  *     the License, or (at your option) any later version.
  21  *
  22  ********************************************************************/
  23
  24 #include <linux/module.h>
  25 #include <linux/gfp.h>
  26
  27 #include <linux/kernel.h>
  28 #include <linux/types.h>
  29 #include <linux/skbuff.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/ioport.h>
  32 #include <linux/delay.h>
  33 #include <linux/init.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/rtnetlink.h>
  36 #include <linux/serial_reg.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/platform_device.h>
  39
  40 #include <asm/io.h>
  41 #include <asm/dma.h>
  42 #include <asm/byteorder.h>
  43
  44 #include <net/irda/wrapper.h>
  45 #include <net/irda/irda.h>
  46 #include <net/irda/irda_device.h>
  47
  48 #include "ali-ircc.h"
  49
  50 #define CHIP_IO_EXTENT 8
  51 #define BROKEN_DONGLE_ID
  52
  53 #define ALI_IRCC_DRIVER_NAME "ali-ircc"
  54
  55 /* Power Management */
  56 static int ali_ircc_suspend(struct platform_device *dev, pm_message_t state);
  57 static int ali_ircc_resume(struct platform_device *dev);
  58
  59 static struct platform_driver ali_ircc_driver = {
  60         .suspend        = ali_ircc_suspend,
  61         .resume         = ali_ircc_resume,
  62         .driver         = {
  63                 .name   = ALI_IRCC_DRIVER_NAME,
  64         },
  65 };
  66
  67 /* Module parameters */
  68 static int qos_mtt_bits = 0x07;  /* 1 ms or more */
  69
  70 /* Use BIOS settions by default, but user may supply module parameters */
  71 static unsigned int io[]  = { ~0, ~0, ~0, ~0 };
  72 static unsigned int irq[] = { 0, 0, 0, 0 };
  73 static unsigned int dma[] = { 0, 0, 0, 0 };
  74
  75 static int  ali_ircc_probe_53(ali_chip_t *chip, chipio_t *info);
  76 static int  ali_ircc_init_43(ali_chip_t *chip, chipio_t *info);
  77 static int  ali_ircc_init_53(ali_chip_t *chip, chipio_t *info);
  78
  79 /* These are the currently known ALi south-bridge chipsets, the only one difference
  80  * is that M1543C doesn't support HP HDSL-3600
  81  */
  82 static ali_chip_t chips[] =
  83 {
  84         { "M1543", { 0x3f0, 0x370 }, 0x51, 0x23, 0x20, 0x43, ali_ircc_probe_53, ali_ircc_init_43 },
  85         { "M1535", { 0x3f0, 0x370 }, 0x51, 0x23, 0x20, 0x53, ali_ircc_probe_53, ali_ircc_init_53 },
  86         { "M1563", { 0x3f0, 0x370 }, 0x51, 0x23, 0x20, 0x63, ali_ircc_probe_53, ali_ircc_init_53 },
  87         { NULL }
  88 };
  89
  90 /* Max 4 instances for now */
  91 static struct ali_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL };
  92
  93 /* Dongle Types */
  94 static char *dongle_types[] = {
  95         "TFDS6000",
  96         "HP HSDL-3600",
  97         "HP HSDL-1100",
  98         "No dongle connected",
  99 };
 100
 101 /* Some prototypes */
 102 static int  ali_ircc_open(int i, chipio_t *info);
 103
 104 static int  ali_ircc_close(struct ali_ircc_cb *self);
 105
 106 static int  ali_ircc_setup(chipio_t *info);
 107 static int  ali_ircc_is_receiving(struct ali_ircc_cb *self);
 108 static int  ali_ircc_net_open(struct net_device *dev);
 109 static int  ali_ircc_net_close(struct net_device *dev);
 110 static int  ali_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 111 static void ali_ircc_change_speed(struct ali_ircc_cb *self, __u32 baud);
 112
 113 /* SIR function */
 114 static netdev_tx_t ali_ircc_sir_hard_xmit(struct sk_buff *skb,
 115                                                 struct net_device *dev);
 116 static irqreturn_t ali_ircc_sir_interrupt(struct ali_ircc_cb *self);
 117 static void ali_ircc_sir_receive(struct ali_ircc_cb *self);
 118 static void ali_ircc_sir_write_wakeup(struct ali_ircc_cb *self);
 119 static int  ali_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
 120 static void ali_ircc_sir_change_speed(struct ali_ircc_cb *priv, __u32 speed);
 121
 122 /* FIR function */
 123 static netdev_tx_t  ali_ircc_fir_hard_xmit(struct sk_buff *skb,
 124                                                  struct net_device *dev);
 125 static void ali_ircc_fir_change_speed(struct ali_ircc_cb *priv, __u32 speed);
 126 static irqreturn_t ali_ircc_fir_interrupt(struct ali_ircc_cb *self);
 127 static int  ali_ircc_dma_receive(struct ali_ircc_cb *self);
 128 static int  ali_ircc_dma_receive_complete(struct ali_ircc_cb *self);
 129 static int  ali_ircc_dma_xmit_complete(struct ali_ircc_cb *self);
 130 static void ali_ircc_dma_xmit(struct ali_ircc_cb *self);
 131
 132 /* My Function */
 133 static int  ali_ircc_read_dongle_id (int i, chipio_t *info);
 134 static void ali_ircc_change_dongle_speed(struct ali_ircc_cb *priv, int speed);
 135
 136 /* ALi chip function */
 137 static void SIR2FIR(int iobase);
 138 static void FIR2SIR(int iobase);
 139 static void SetCOMInterrupts(struct ali_ircc_cb *self , unsigned char enable);
 140
 141 /*
 142  * Function ali_ircc_init ()
 143  *
 144  *    Initialize chip. Find out whay kinds of chips we are dealing with
 145  *    and their configuration registers address
 146  */
 147 static int __init ali_ircc_init(void)
 148 {
 149         ali_chip_t *chip;
 150         chipio_t info;
 151         int ret;
 152         int cfg, cfg_base;
 153         int reg, revision;
 154         int i = 0;
 155
 156         ret = platform_driver_register(&ali_ircc_driver);
 157         if (ret) {
 158                 net_err_ratelimited("%s, Can't register driver!\n",
 159                                     ALI_IRCC_DRIVER_NAME);
 160                 return ret;
 161         }
 162
 163         ret = -ENODEV;
 164
 165         /* Probe for all the ALi chipsets we know about */
 166         for (chip= chips; chip->name; chip++, i++)
 167         {
 168                 pr_debug("%s(), Probing for %s ...\n", __func__, chip->name);
 169
 170                 /* Try all config registers for this chip */
 171                 for (cfg=0; cfg<2; cfg++)
 172                 {
 173                         cfg_base = chip->cfg[cfg];
 174                         if (!cfg_base)
 175                                 continue;
 176
 177                         memset(&info, 0, sizeof(chipio_t));
 178                         info.cfg_base = cfg_base;
 179                         info.fir_base = io[i];
 180                         info.dma = dma[i];
 181                         info.irq = irq[i];
 182
 183
 184                         /* Enter Configuration */
 185                         outb(chip->entr1, cfg_base);
 186                         outb(chip->entr2, cfg_base);
 187
 188                         /* Select Logical Device 5 Registers (UART2) */
 189                         outb(0x07, cfg_base);
 190                         outb(0x05, cfg_base+1);
 191
 192                         /* Read Chip Identification Register */
 193                         outb(chip->cid_index, cfg_base);
 194                         reg = inb(cfg_base+1);
 195
 196                         if (reg == chip->cid_value)
 197                         {
 198                                 pr_debug("%s(), Chip found at 0x%03x\n",
 199                                          __func__, cfg_base);
 200
 201                                 outb(0x1F, cfg_base);
 202                                 revision = inb(cfg_base+1);
 203                                 pr_debug("%s(), Found %s chip, revision=%d\n",
 204                                          __func__, chip->name, revision);
 205
 206                                 /*
 207                                  * If the user supplies the base address, then
 208                                  * we init the chip, if not we probe the values
 209                                  * set by the BIOS
 210                                  */
 211                                 if (io[i] < 2000)
 212                                 {
 213                                         chip->init(chip, &info);
 214                                 }
 215                                 else
 216                                 {
 217                                         chip->probe(chip, &info);
 218                                 }
 219
 220                                 if (ali_ircc_open(i, &info) == 0)
 221                                         ret = 0;
 222                                 i++;
 223                         }
 224                         else
 225                         {
 226                                 pr_debug("%s(), No %s chip at 0x%03x\n",
 227                                          __func__, chip->name, cfg_base);
 228                         }
 229                         /* Exit configuration */
 230                         outb(0xbb, cfg_base);
 231                 }
 232         }
 233
 234         if (ret)
 235                 platform_driver_unregister(&ali_ircc_driver);
 236
 237         return ret;
 238 }
 239
 240 /*
 241  * Function ali_ircc_cleanup ()
 242  *
 243  *    Close all configured chips
 244  *
 245  */
 246 static void __exit ali_ircc_cleanup(void)
 247 {
 248         int i;
 249
 250         for (i=0; i < ARRAY_SIZE(dev_self); i++) {
 251                 if (dev_self[i])
 252                         ali_ircc_close(dev_self[i]);
 253         }
 254
 255         platform_driver_unregister(&ali_ircc_driver);
 256
 257 }
 258
 259 static const struct net_device_ops ali_ircc_sir_ops = {
 260         .ndo_open       = ali_ircc_net_open,
 261         .ndo_stop       = ali_ircc_net_close,
 262         .ndo_start_xmit = ali_ircc_sir_hard_xmit,
 263         .ndo_do_ioctl   = ali_ircc_net_ioctl,
 264 };
 265
 266 static const struct net_device_ops ali_ircc_fir_ops = {
 267         .ndo_open       = ali_ircc_net_open,
 268         .ndo_stop       = ali_ircc_net_close,
 269         .ndo_start_xmit = ali_ircc_fir_hard_xmit,
 270         .ndo_do_ioctl   = ali_ircc_net_ioctl,
 271 };
 272
 273 /*
 274  * Function ali_ircc_open (int i, chipio_t *inf)
 275  *
 276  *    Open driver instance
 277  *
 278  */
 279 static int ali_ircc_open(int i, chipio_t *info)
 280 {
 281         struct net_device *dev;
 282         struct ali_ircc_cb *self;
 283         int dongle_id;
 284         int err;
 285
 286         if (i >= ARRAY_SIZE(dev_self)) {
 287                 net_err_ratelimited("%s(), maximum number of supported chips reached!\n",
 288                                     __func__);
 289                 return -ENOMEM;
 290         }
 291
 292         /* Set FIR FIFO and DMA Threshold */
 293         if ((ali_ircc_setup(info)) == -1)
 294                 return -1;
 295
 296         dev = alloc_irdadev(sizeof(*self));
 297         if (dev == NULL) {
 298                 net_err_ratelimited("%s(), can't allocate memory for control block!\n",
 299                                     __func__);
 300                 return -ENOMEM;
 301         }
 302
 303         self = netdev_priv(dev);
 304         self->netdev = dev;
 305         spin_lock_init(&self->lock);
 306
 307         /* Need to store self somewhere */
 308         dev_self[i] = self;
 309         self->index = i;
 310
 311         /* Initialize IO */
 312         self->io.cfg_base  = info->cfg_base;    /* In ali_ircc_probe_53 assign          */
 313         self->io.fir_base  = info->fir_base;    /* info->sir_base = info->fir_base      */
 314         self->io.sir_base  = info->sir_base;    /* ALi SIR and FIR use the same address */
 315         self->io.irq       = info->irq;
 316         self->io.fir_ext   = CHIP_IO_EXTENT;
 317         self->io.dma       = info->dma;
 318         self->io.fifo_size = 16;                /* SIR: 16, FIR: 32 Benjamin 2000/11/1 */
 319
 320         /* Reserve the ioports that we need */
 321         if (!request_region(self->io.fir_base, self->io.fir_ext,
 322                             ALI_IRCC_DRIVER_NAME)) {
 323                 net_warn_ratelimited("%s(), can't get iobase of 0x%03x\n",
 324                                      __func__, self->io.fir_base);
 325                 err = -ENODEV;
 326                 goto err_out1;
 327         }
 328
 329         /* Initialize QoS for this device */
 330         irda_init_max_qos_capabilies(&self->qos);
 331
 332         /* The only value we must override it the baudrate */
 333         self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
 334                 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8); // benjamin 2000/11/8 05:27PM
 335
 336         self->qos.min_turn_time.bits = qos_mtt_bits;
 337
 338         irda_qos_bits_to_value(&self->qos);
 339
 340         /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
 341         self->rx_buff.truesize = 14384;
 342         self->tx_buff.truesize = 14384;
 343
 344         /* Allocate memory if needed */
 345         self->rx_buff.head =
 346                 dma_zalloc_coherent(NULL, self->rx_buff.truesize,
 347                                     &self->rx_buff_dma, GFP_KERNEL);
 348         if (self->rx_buff.head == NULL) {
 349                 err = -ENOMEM;
 350                 goto err_out2;
 351         }
 352
 353         self->tx_buff.head =
 354                 dma_zalloc_coherent(NULL, self->tx_buff.truesize,
 355                                     &self->tx_buff_dma, GFP_KERNEL);
 356         if (self->tx_buff.head == NULL) {
 357                 err = -ENOMEM;
 358                 goto err_out3;
 359         }
 360
 361         self->rx_buff.in_frame = FALSE;
 362         self->rx_buff.state = OUTSIDE_FRAME;
 363         self->tx_buff.data = self->tx_buff.head;
 364         self->rx_buff.data = self->rx_buff.head;
 365
 366         /* Reset Tx queue info */
 367         self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
 368         self->tx_fifo.tail = self->tx_buff.head;
 369
 370         /* Override the network functions we need to use */
 371         dev->netdev_ops = &ali_ircc_sir_ops;
 372
 373         err = register_netdev(dev);
 374         if (err) {
 375                 net_err_ratelimited("%s(), register_netdev() failed!\n",
 376                                     __func__);
 377                 goto err_out4;
 378         }
 379         net_info_ratelimited("IrDA: Registered device %s\n", dev->name);
 380
 381         /* Check dongle id */
 382         dongle_id = ali_ircc_read_dongle_id(i, info);
 383         net_info_ratelimited("%s(), %s, Found dongle: %s\n",
 384                              __func__, ALI_IRCC_DRIVER_NAME,
 385                              dongle_types[dongle_id]);
 386
 387         self->io.dongle_id = dongle_id;
 388
 389
 390         return 0;
 391
 392  err_out4:
 393         dma_free_coherent(NULL, self->tx_buff.truesize,
 394                           self->tx_buff.head, self->tx_buff_dma);
 395  err_out3:
 396         dma_free_coherent(NULL, self->rx_buff.truesize,
 397                           self->rx_buff.head, self->rx_buff_dma);
 398  err_out2:
 399         release_region(self->io.fir_base, self->io.fir_ext);
 400  err_out1:
 401         dev_self[i] = NULL;
 402         free_netdev(dev);
 403         return err;
 404 }
 405
 406
 407 /*
 408  * Function ali_ircc_close (self)
 409  *
 410  *    Close driver instance
 411  *
 412  */
 413 static int __exit ali_ircc_close(struct ali_ircc_cb *self)
 414 {
 415         int iobase;
 416
 417         IRDA_ASSERT(self != NULL, return -1;);
 418
 419         iobase = self->io.fir_base;
 420
 421         /* Remove netdevice */
 422         unregister_netdev(self->netdev);
 423
 424         /* Release the PORT that this driver is using */
 425         pr_debug("%s(), Releasing Region %03x\n", __func__, self->io.fir_base);
 426         release_region(self->io.fir_base, self->io.fir_ext);
 427
 428         if (self->tx_buff.head)
 429                 dma_free_coherent(NULL, self->tx_buff.truesize,
 430                                   self->tx_buff.head, self->tx_buff_dma);
 431
 432         if (self->rx_buff.head)
 433                 dma_free_coherent(NULL, self->rx_buff.truesize,
 434                                   self->rx_buff.head, self->rx_buff_dma);
 435
 436         dev_self[self->index] = NULL;
 437         free_netdev(self->netdev);
 438
 439
 440         return 0;
 441 }
 442
 443 /*
 444  * Function ali_ircc_init_43 (chip, info)
 445  *
 446  *    Initialize the ALi M1543 chip.
 447  */
 448 static int ali_ircc_init_43(ali_chip_t *chip, chipio_t *info)
 449 {
 450         /* All controller information like I/O address, DMA channel, IRQ
 451          * are set by BIOS
 452          */
 453
 454         return 0;
 455 }
 456
 457 /*
 458  * Function ali_ircc_init_53 (chip, info)
 459  *
 460  *    Initialize the ALi M1535 chip.
 461  */
 462 static int ali_ircc_init_53(ali_chip_t *chip, chipio_t *info)
 463 {
 464         /* All controller information like I/O address, DMA channel, IRQ
 465          * are set by BIOS
 466          */
 467
 468         return 0;
 469 }
 470
 471 /*
 472  * Function ali_ircc_probe_53 (chip, info)
 473  *
 474  *      Probes for the ALi M1535D or M1535
 475  */
 476 static int ali_ircc_probe_53(ali_chip_t *chip, chipio_t *info)
 477 {
 478         int cfg_base = info->cfg_base;
 479         int hi, low, reg;
 480
 481
 482         /* Enter Configuration */
 483         outb(chip->entr1, cfg_base);
 484         outb(chip->entr2, cfg_base);
 485
 486         /* Select Logical Device 5 Registers (UART2) */
 487         outb(0x07, cfg_base);
 488         outb(0x05, cfg_base+1);
 489
 490         /* Read address control register */
 491         outb(0x60, cfg_base);
 492         hi = inb(cfg_base+1);
 493         outb(0x61, cfg_base);
 494         low = inb(cfg_base+1);
 495         info->fir_base = (hi<<8) + low;
 496
 497         info->sir_base = info->fir_base;
 498
 499         pr_debug("%s(), probing fir_base=0x%03x\n", __func__, info->fir_base);
 500
 501         /* Read IRQ control register */
 502         outb(0x70, cfg_base);
 503         reg = inb(cfg_base+1);
 504         info->irq = reg & 0x0f;
 505         pr_debug("%s(), probing irq=%d\n", __func__, info->irq);
 506
 507         /* Read DMA channel */
 508         outb(0x74, cfg_base);
 509         reg = inb(cfg_base+1);
 510         info->dma = reg & 0x07;
 511
 512         if(info->dma == 0x04)
 513                 net_warn_ratelimited("%s(), No DMA channel assigned !\n",
 514                                      __func__);
 515         else
 516                 pr_debug("%s(), probing dma=%d\n", __func__, info->dma);
 517
 518         /* Read Enabled Status */
 519         outb(0x30, cfg_base);
 520         reg = inb(cfg_base+1);
 521         info->enabled = (reg & 0x80) && (reg & 0x01);
 522         pr_debug("%s(), probing enabled=%d\n", __func__, info->enabled);
 523
 524         /* Read Power Status */
 525         outb(0x22, cfg_base);
 526         reg = inb(cfg_base+1);
 527         info->suspended = (reg & 0x20);
 528         pr_debug("%s(), probing suspended=%d\n", __func__, info->suspended);
 529
 530         /* Exit configuration */
 531         outb(0xbb, cfg_base);
 532
 533
 534         return 0;
 535 }
 536
 537 /*
 538  * Function ali_ircc_setup (info)
 539  *
 540  *      Set FIR FIFO and DMA Threshold
 541  *      Returns non-negative on success.
 542  *
 543  */
 544 static int ali_ircc_setup(chipio_t *info)
 545 {
 546         unsigned char tmp;
 547         int version;
 548         int iobase = info->fir_base;
 549
 550
 551         /* Locking comments :
 552          * Most operations here need to be protected. We are called before
 553          * the device instance is created in ali_ircc_open(), therefore
 554          * nobody can bother us - Jean II */
 555
 556         /* Switch to FIR space */
 557         SIR2FIR(iobase);
 558
 559         /* Master Reset */
 560         outb(0x40, iobase+FIR_MCR); // benjamin 2000/11/30 11:45AM
 561
 562         /* Read FIR ID Version Register */
 563         switch_bank(iobase, BANK3);
 564         version = inb(iobase+FIR_ID_VR);
 565
 566         /* Should be 0x00 in the M1535/M1535D */
 567         if(version != 0x00)
 568         {
 569                 net_err_ratelimited("%s, Wrong chip version %02x\n",
 570                                     ALI_IRCC_DRIVER_NAME, version);
 571                 return -1;
 572         }
 573
 574         /* Set FIR FIFO Threshold Register */
 575         switch_bank(iobase, BANK1);
 576         outb(RX_FIFO_Threshold, iobase+FIR_FIFO_TR);
 577
 578         /* Set FIR DMA Threshold Register */
 579         outb(RX_DMA_Threshold, iobase+FIR_DMA_TR);
 580
 581         /* CRC enable */
 582         switch_bank(iobase, BANK2);
 583         outb(inb(iobase+FIR_IRDA_CR) | IRDA_CR_CRC, iobase+FIR_IRDA_CR);
 584
 585         /* NDIS driver set TX Length here BANK2 Alias 3, Alias4*/
 586
 587         /* Switch to Bank 0 */
 588         switch_bank(iobase, BANK0);
 589
 590         tmp = inb(iobase+FIR_LCR_B);
 591         tmp &=~0x20; // disable SIP
 592         tmp |= 0x80; // these two steps make RX mode
 593         tmp &= 0xbf;
 594         outb(tmp, iobase+FIR_LCR_B);
 595
 596         /* Disable Interrupt */
 597         outb(0x00, iobase+FIR_IER);
 598
 599
 600         /* Switch to SIR space */
 601         FIR2SIR(iobase);
 602
 603         net_info_ratelimited("%s, driver loaded (Benjamin Kong)\n",
 604                              ALI_IRCC_DRIVER_NAME);
 605
 606         /* Enable receive interrupts */
 607         // outb(UART_IER_RDI, iobase+UART_IER); //benjamin 2000/11/23 01:25PM
 608         // Turn on the interrupts in ali_ircc_net_open
 609
 610
 611         return 0;
 612 }
 613
 614 /*
 615  * Function ali_ircc_read_dongle_id (int index, info)
 616  *
 617  * Try to read dongle identification. This procedure needs to be executed
 618  * once after power-on/reset. It also needs to be used whenever you suspect
 619  * that the user may have plugged/unplugged the IrDA Dongle.
 620  */
 621 static int ali_ircc_read_dongle_id (int i, chipio_t *info)
 622 {
 623         int dongle_id, reg;
 624         int cfg_base = info->cfg_base;
 625
 626
 627         /* Enter Configuration */
 628         outb(chips[i].entr1, cfg_base);
 629         outb(chips[i].entr2, cfg_base);
 630
 631         /* Select Logical Device 5 Registers (UART2) */
 632         outb(0x07, cfg_base);
 633         outb(0x05, cfg_base+1);
 634
 635         /* Read Dongle ID */
 636         outb(0xf0, cfg_base);
 637         reg = inb(cfg_base+1);
 638         dongle_id = ((reg>>6)&0x02) | ((reg>>5)&0x01);
 639         pr_debug("%s(), probing dongle_id=%d, dongle_types=%s\n",
 640                  __func__, dongle_id, dongle_types[dongle_id]);
 641
 642         /* Exit configuration */
 643         outb(0xbb, cfg_base);
 644
 645
 646         return dongle_id;
 647 }
 648
 649 /*
 650  * Function ali_ircc_interrupt (irq, dev_id, regs)
 651  *
 652  *    An interrupt from the chip has arrived. Time to do some work
 653  *
 654  */
 655 static irqreturn_t ali_ircc_interrupt(int irq, void *dev_id)
 656 {
 657         struct net_device *dev = dev_id;
 658         struct ali_ircc_cb *self;
 659         int ret;
 660
 661
 662         self = netdev_priv(dev);
 663
 664         spin_lock(&self->lock);
 665
 666         /* Dispatch interrupt handler for the current speed */
 667         if (self->io.speed > 115200)
 668                 ret = ali_ircc_fir_interrupt(self);
 669         else
 670                 ret = ali_ircc_sir_interrupt(self);
 671
 672         spin_unlock(&self->lock);
 673
 674         return ret;
 675 }
 676 /*
 677  * Function ali_ircc_fir_interrupt(irq, struct ali_ircc_cb *self)
 678  *
 679  *    Handle MIR/FIR interrupt
 680  *
 681  */
 682 static irqreturn_t ali_ircc_fir_interrupt(struct ali_ircc_cb *self)
 683 {
 684         __u8 eir, OldMessageCount;
 685         int iobase, tmp;
 686
 687
 688         iobase = self->io.fir_base;
 689
 690         switch_bank(iobase, BANK0);
 691         self->InterruptID = inb(iobase+FIR_IIR);
 692         self->BusStatus = inb(iobase+FIR_BSR);
 693
 694         OldMessageCount = (self->LineStatus + 1) & 0x07;
 695         self->LineStatus = inb(iobase+FIR_LSR);
 696         //self->ier = inb(iobase+FIR_IER);              2000/12/1 04:32PM
 697         eir = self->InterruptID & self->ier; /* Mask out the interesting ones */
 698
 699         pr_debug("%s(), self->InterruptID = %x\n", __func__, self->InterruptID);
 700         pr_debug("%s(), self->LineStatus = %x\n", __func__, self->LineStatus);
 701         pr_debug("%s(), self->ier = %x\n", __func__, self->ier);
 702         pr_debug("%s(), eir = %x\n", __func__, eir);
 703
 704         /* Disable interrupts */
 705          SetCOMInterrupts(self, FALSE);
 706
 707         /* Tx or Rx Interrupt */
 708
 709         if (eir & IIR_EOM)
 710         {
 711                 if (self->io.direction == IO_XMIT) /* TX */
 712                 {
 713                         pr_debug("%s(), ******* IIR_EOM (Tx) *******\n",
 714                                  __func__);
 715
 716                         if(ali_ircc_dma_xmit_complete(self))
 717                         {
 718                                 if (irda_device_txqueue_empty(self->netdev))
 719                                 {
 720                                         /* Prepare for receive */
 721                                         ali_ircc_dma_receive(self);
 722                                         self->ier = IER_EOM;
 723                                 }
 724                         }
 725                         else
 726                         {
 727                                 self->ier = IER_EOM;
 728                         }
 729
 730                 }
 731                 else /* RX */
 732                 {
 733                         pr_debug("%s(), ******* IIR_EOM (Rx) *******\n",
 734                                  __func__);
 735
 736                         if(OldMessageCount > ((self->LineStatus+1) & 0x07))
 737                         {
 738                                 self->rcvFramesOverflow = TRUE;
 739                                 pr_debug("%s(), ******* self->rcvFramesOverflow = TRUE ********\n",
 740                                          __func__);
 741                         }
 742
 743                         if (ali_ircc_dma_receive_complete(self))
 744                         {
 745                                 pr_debug("%s(), ******* receive complete ********\n",
 746                                          __func__);
 747
 748                                 self->ier = IER_EOM;
 749                         }
 750                         else
 751                         {
 752                                 pr_debug("%s(), ******* Not receive complete ********\n",
 753                                          __func__);
 754
 755                                 self->ier = IER_EOM | IER_TIMER;
 756                         }
 757
 758                 }
 759         }
 760         /* Timer Interrupt */
 761         else if (eir & IIR_TIMER)
 762         {
 763                 if(OldMessageCount > ((self->LineStatus+1) & 0x07))
 764                 {
 765                         self->rcvFramesOverflow = TRUE;
 766                         pr_debug("%s(), ******* self->rcvFramesOverflow = TRUE *******\n",
 767                                  __func__);
 768                 }
 769                 /* Disable Timer */
 770                 switch_bank(iobase, BANK1);
 771                 tmp = inb(iobase+FIR_CR);
 772                 outb( tmp& ~CR_TIMER_EN, iobase+FIR_CR);
 773
 774                 /* Check if this is a Tx timer interrupt */
 775                 if (self->io.direction == IO_XMIT)
 776                 {
 777                         ali_ircc_dma_xmit(self);
 778
 779                         /* Interrupt on EOM */
 780                         self->ier = IER_EOM;
 781
 782                 }
 783                 else /* Rx */
 784                 {
 785                         if(ali_ircc_dma_receive_complete(self))
 786                         {
 787                                 self->ier = IER_EOM;
 788                         }
 789                         else
 790                         {
 791                                 self->ier = IER_EOM | IER_TIMER;
 792                         }
 793                 }
 794         }
 795
 796         /* Restore Interrupt */
 797         SetCOMInterrupts(self, TRUE);
 798
 799         return IRQ_RETVAL(eir);
 800 }
 801
 802 /*
 803  * Function ali_ircc_sir_interrupt (irq, self, eir)
 804  *
 805  *    Handle SIR interrupt
 806  *
 807  */
 808 static irqreturn_t ali_ircc_sir_interrupt(struct ali_ircc_cb *self)
 809 {
 810         int iobase;
 811         int iir, lsr;
 812
 813
 814         iobase = self->io.sir_base;
 815
 816         iir = inb(iobase+UART_IIR) & UART_IIR_ID;
 817         if (iir) {
 818                 /* Clear interrupt */
 819                 lsr = inb(iobase+UART_LSR);
 820
 821                 pr_debug("%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
 822                          __func__, iir, lsr, iobase);
 823
 824                 switch (iir)
 825                 {
 826                         case UART_IIR_RLSI:
 827                                 pr_debug("%s(), RLSI\n", __func__);
 828                                 break;
 829                         case UART_IIR_RDI:
 830                                 /* Receive interrupt */
 831                                 ali_ircc_sir_receive(self);
 832                                 break;
 833                         case UART_IIR_THRI:
 834                                 if (lsr & UART_LSR_THRE)
 835                                 {
 836                                         /* Transmitter ready for data */
 837                                         ali_ircc_sir_write_wakeup(self);
 838                                 }
 839                                 break;
 840                         default:
 841                                 pr_debug("%s(), unhandled IIR=%#x\n",
 842                                          __func__, iir);
 843                                 break;
 844                 }
 845
 846         }
 847
 848
 849         return IRQ_RETVAL(iir);
 850 }
 851
 852
 853 /*
 854  * Function ali_ircc_sir_receive (self)
 855  *
 856  *    Receive one frame from the infrared port
 857  *
 858  */
 859 static void ali_ircc_sir_receive(struct ali_ircc_cb *self)
 860 {
 861         int boguscount = 0;
 862         int iobase;
 863
 864         IRDA_ASSERT(self != NULL, return;);
 865
 866         iobase = self->io.sir_base;
 867
 868         /*
 869          * Receive all characters in Rx FIFO, unwrap and unstuff them.
 870          * async_unwrap_char will deliver all found frames
 871          */
 872         do {
 873                 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
 874                                   inb(iobase+UART_RX));
 875
 876                 /* Make sure we don't stay here too long */
 877                 if (boguscount++ > 32) {
 878                         pr_debug("%s(), breaking!\n", __func__);
 879                         break;
 880                 }
 881         } while (inb(iobase+UART_LSR) & UART_LSR_DR);
 882
 883 }
 884
 885 /*
 886  * Function ali_ircc_sir_write_wakeup (tty)
 887  *
 888  *    Called by the driver when there's room for more data.  If we have
 889  *    more packets to send, we send them here.
 890  *
 891  */
 892 static void ali_ircc_sir_write_wakeup(struct ali_ircc_cb *self)
 893 {
 894         int actual = 0;
 895         int iobase;
 896
 897         IRDA_ASSERT(self != NULL, return;);
 898
 899
 900         iobase = self->io.sir_base;
 901
 902         /* Finished with frame?  */
 903         if (self->tx_buff.len > 0)
 904         {
 905                 /* Write data left in transmit buffer */
 906                 actual = ali_ircc_sir_write(iobase, self->io.fifo_size,
 907                                       self->tx_buff.data, self->tx_buff.len);
 908                 self->tx_buff.data += actual;
 909                 self->tx_buff.len  -= actual;
 910         }
 911         else
 912         {
 913                 if (self->new_speed)
 914                 {
 915                         /* We must wait until all data are gone */
 916                         while(!(inb(iobase+UART_LSR) & UART_LSR_TEMT))
 917                                 pr_debug("%s(), UART_LSR_THRE\n", __func__);
 918
 919                         pr_debug("%s(), Changing speed! self->new_speed = %d\n",
 920                                  __func__, self->new_speed);
 921                         ali_ircc_change_speed(self, self->new_speed);
 922                         self->new_speed = 0;
 923
 924                         // benjamin 2000/11/10 06:32PM
 925                         if (self->io.speed > 115200)
 926                         {
 927                                 pr_debug("%s(), ali_ircc_change_speed from UART_LSR_TEMT\n",
 928                                          __func__);
 929
 930                                 self->ier = IER_EOM;
 931                                 // SetCOMInterrupts(self, TRUE);
 932                                 return;
 933                         }
 934                 }
 935                 else
 936                 {
 937                         netif_wake_queue(self->netdev);
 938                 }
 939
 940                 self->netdev->stats.tx_packets++;
 941
 942                 /* Turn on receive interrupts */
 943                 outb(UART_IER_RDI, iobase+UART_IER);
 944         }
 945
 946 }
 947
 948 static void ali_ircc_change_speed(struct ali_ircc_cb *self, __u32 baud)
 949 {
 950         struct net_device *dev = self->netdev;
 951         int iobase;
 952
 953
 954         pr_debug("%s(), setting speed = %d\n", __func__, baud);
 955
 956         /* This function *must* be called with irq off and spin-lock.
 957          * - Jean II */
 958
 959         iobase = self->io.fir_base;
 960
 961         SetCOMInterrupts(self, FALSE); // 2000/11/24 11:43AM
 962
 963         /* Go to MIR, FIR Speed */
 964         if (baud > 115200)
 965         {
 966
 967
 968                 ali_ircc_fir_change_speed(self, baud);
 969
 970                 /* Install FIR xmit handler*/
 971                 dev->netdev_ops = &ali_ircc_fir_ops;
 972
 973                 /* Enable Interuupt */
 974                 self->ier = IER_EOM; // benjamin 2000/11/20 07:24PM
 975
 976                 /* Be ready for incoming frames */
 977                 ali_ircc_dma_receive(self);     // benajmin 2000/11/8 07:46PM not complete
 978         }
 979         /* Go to SIR Speed */
 980         else
 981         {
 982                 ali_ircc_sir_change_speed(self, baud);
 983
 984                 /* Install SIR xmit handler*/
 985                 dev->netdev_ops = &ali_ircc_sir_ops;
 986         }
 987
 988
 989         SetCOMInterrupts(self, TRUE);   // 2000/11/24 11:43AM
 990
 991         netif_wake_queue(self->netdev);
 992
 993 }
 994
 995 static void ali_ircc_fir_change_speed(struct ali_ircc_cb *priv, __u32 baud)
 996 {
 997
 998         int iobase;
 999         struct ali_ircc_cb *self = priv;
1000         struct net_device *dev;
1001
1002
1003         IRDA_ASSERT(self != NULL, return;);
1004
1005         dev = self->netdev;
1006         iobase = self->io.fir_base;
1007
1008         pr_debug("%s(), self->io.speed = %d, change to speed = %d\n",
1009                  __func__, self->io.speed, baud);
1010
1011         /* Come from SIR speed */
1012         if(self->io.speed <=115200)
1013         {
1014                 SIR2FIR(iobase);
1015         }
1016
1017         /* Update accounting for new speed */
1018         self->io.speed = baud;
1019
1020         // Set Dongle Speed mode
1021         ali_ircc_change_dongle_speed(self, baud);
1022
1023 }
1024
1025 /*
1026  * Function ali_sir_change_speed (self, speed)
1027  *
1028  *    Set speed of IrDA port to specified baudrate
1029  *
1030  */
1031 static void ali_ircc_sir_change_speed(struct ali_ircc_cb *priv, __u32 speed)
1032 {
1033         struct ali_ircc_cb *self = priv;
1034         unsigned long flags;
1035         int iobase;
1036         int fcr;    /* FIFO control reg */
1037         int lcr;    /* Line control reg */
1038         int divisor;
1039
1040
1041         pr_debug("%s(), Setting speed to: %d\n", __func__, speed);
1042
1043         IRDA_ASSERT(self != NULL, return;);
1044
1045         iobase = self->io.sir_base;
1046
1047         /* Come from MIR or FIR speed */
1048         if(self->io.speed >115200)
1049         {
1050                 // Set Dongle Speed mode first
1051                 ali_ircc_change_dongle_speed(self, speed);
1052
1053                 FIR2SIR(iobase);
1054         }
1055
1056         // Clear Line and Auxiluary status registers 2000/11/24 11:47AM
1057
1058         inb(iobase+UART_LSR);
1059         inb(iobase+UART_SCR);
1060
1061         /* Update accounting for new speed */
1062         self->io.speed = speed;
1063
1064         spin_lock_irqsave(&self->lock, flags);
1065
1066         divisor = 115200/speed;
1067
1068         fcr = UART_FCR_ENABLE_FIFO;
1069
1070         /*
1071          * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1072          * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1073          * about this timeout since it will always be fast enough.
1074          */
1075         if (self->io.speed < 38400)
1076                 fcr |= UART_FCR_TRIGGER_1;
1077         else
1078                 fcr |= UART_FCR_TRIGGER_14;
1079
1080         /* IrDA ports use 8N1 */
1081         lcr = UART_LCR_WLEN8;
1082
1083         outb(UART_LCR_DLAB | lcr, iobase+UART_LCR); /* Set DLAB */
1084         outb(divisor & 0xff,      iobase+UART_DLL); /* Set speed */
1085         outb(divisor >> 8,        iobase+UART_DLM);
1086         outb(lcr,                 iobase+UART_LCR); /* Set 8N1  */
1087         outb(fcr,                 iobase+UART_FCR); /* Enable FIFO's */
1088
1089         /* without this, the connection will be broken after come back from FIR speed,
1090            but with this, the SIR connection is harder to established */
1091         outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), iobase+UART_MCR);
1092
1093         spin_unlock_irqrestore(&self->lock, flags);
1094
1095 }
1096
1097 static void ali_ircc_change_dongle_speed(struct ali_ircc_cb *priv, int speed)
1098 {
1099
1100         struct ali_ircc_cb *self = priv;
1101         int iobase,dongle_id;
1102         int tmp = 0;
1103
1104
1105         iobase = self->io.fir_base;     /* or iobase = self->io.sir_base; */
1106         dongle_id = self->io.dongle_id;
1107
1108         /* We are already locked, no need to do it again */
1109
1110         pr_debug("%s(), Set Speed for %s , Speed = %d\n",
1111                  __func__, dongle_types[dongle_id], speed);
1112
1113         switch_bank(iobase, BANK2);
1114         tmp = inb(iobase+FIR_IRDA_CR);
1115
1116         /* IBM type dongle */
1117         if(dongle_id == 0)
1118         {
1119                 if(speed == 4000000)
1120                 {
1121                         //            __ __
1122                         // SD/MODE __|     |__ __
1123                         //               __ __
1124                         // IRTX    __ __|     |__
1125                         //         T1 T2 T3 T4 T5
1126
1127                         tmp &=  ~IRDA_CR_HDLC;          // HDLC=0
1128                         tmp |= IRDA_CR_CRC;             // CRC=1
1129
1130                         switch_bank(iobase, BANK2);
1131                         outb(tmp, iobase+FIR_IRDA_CR);
1132
1133                         // T1 -> SD/MODE:0 IRTX:0
1134                         tmp &= ~0x09;
1135                         tmp |= 0x02;
1136                         outb(tmp, iobase+FIR_IRDA_CR);
1137                         udelay(2);
1138
1139                         // T2 -> SD/MODE:1 IRTX:0
1140                         tmp &= ~0x01;
1141                         tmp |= 0x0a;
1142                         outb(tmp, iobase+FIR_IRDA_CR);
1143                         udelay(2);
1144
1145                         // T3 -> SD/MODE:1 IRTX:1
1146                         tmp |= 0x0b;
1147                         outb(tmp, iobase+FIR_IRDA_CR);
1148                         udelay(2);
1149
1150                         // T4 -> SD/MODE:0 IRTX:1
1151                         tmp &= ~0x08;
1152                         tmp |= 0x03;
1153                         outb(tmp, iobase+FIR_IRDA_CR);
1154                         udelay(2);
1155
1156                         // T5 -> SD/MODE:0 IRTX:0
1157                         tmp &= ~0x09;
1158                         tmp |= 0x02;
1159                         outb(tmp, iobase+FIR_IRDA_CR);
1160                         udelay(2);
1161
1162                         // reset -> Normal TX output Signal
1163                         outb(tmp & ~0x02, iobase+FIR_IRDA_CR);
1164                 }
1165                 else /* speed <=1152000 */
1166                 {
1167                         //            __
1168                         // SD/MODE __|  |__
1169                         //
1170                         // IRTX    ________
1171                         //         T1 T2 T3
1172
1173                         /* MIR 115200, 57600 */
1174                         if (speed==1152000)
1175                         {
1176                                 tmp |= 0xA0;       //HDLC=1, 1.152Mbps=1
1177                         }
1178                         else
1179                         {
1180                                 tmp &=~0x80;       //HDLC 0.576Mbps
1181                                 tmp |= 0x20;       //HDLC=1,
1182                         }
1183
1184                         tmp |= IRDA_CR_CRC;             // CRC=1
1185
1186                         switch_bank(iobase, BANK2);
1187                         outb(tmp, iobase+FIR_IRDA_CR);
1188
1189                         /* MIR 115200, 57600 */
1190
1191                         //switch_bank(iobase, BANK2);
1192                         // T1 -> SD/MODE:0 IRTX:0
1193                         tmp &= ~0x09;
1194                         tmp |= 0x02;
1195                         outb(tmp, iobase+FIR_IRDA_CR);
1196                         udelay(2);
1197
1198                         // T2 -> SD/MODE:1 IRTX:0
1199                         tmp &= ~0x01;
1200                         tmp |= 0x0a;
1201                         outb(tmp, iobase+FIR_IRDA_CR);
1202
1203                         // T3 -> SD/MODE:0 IRTX:0
1204                         tmp &= ~0x09;
1205                         tmp |= 0x02;
1206                         outb(tmp, iobase+FIR_IRDA_CR);
1207                         udelay(2);
1208
1209                         // reset -> Normal TX output Signal
1210                         outb(tmp & ~0x02, iobase+FIR_IRDA_CR);
1211                 }
1212         }
1213         else if (dongle_id == 1) /* HP HDSL-3600 */
1214         {
1215                 switch(speed)
1216                 {
1217                 case 4000000:
1218                         tmp &=  ~IRDA_CR_HDLC;  // HDLC=0
1219                         break;
1220
1221                 case 1152000:
1222                         tmp |= 0xA0;            // HDLC=1, 1.152Mbps=1
1223                         break;
1224
1225                 case 576000:
1226                         tmp &=~0x80;            // HDLC 0.576Mbps
1227                         tmp |= 0x20;            // HDLC=1,
1228                         break;
1229                 }
1230
1231                 tmp |= IRDA_CR_CRC;             // CRC=1
1232
1233                 switch_bank(iobase, BANK2);
1234                 outb(tmp, iobase+FIR_IRDA_CR);
1235         }
1236         else /* HP HDSL-1100 */
1237         {
1238                 if(speed <= 115200) /* SIR */
1239                 {
1240
1241                         tmp &= ~IRDA_CR_FIR_SIN;        // HP sin select = 0
1242
1243                         switch_bank(iobase, BANK2);
1244                         outb(tmp, iobase+FIR_IRDA_CR);
1245                 }
1246                 else /* MIR FIR */
1247                 {
1248
1249                         switch(speed)
1250                         {
1251                         case 4000000:
1252                                 tmp &=  ~IRDA_CR_HDLC;  // HDLC=0
1253                                 break;
1254
1255                         case 1152000:
1256                                 tmp |= 0xA0;            // HDLC=1, 1.152Mbps=1
1257                                 break;
1258
1259                         case 576000:
1260                                 tmp &=~0x80;            // HDLC 0.576Mbps
1261                                 tmp |= 0x20;            // HDLC=1,
1262                                 break;
1263                         }
1264
1265                         tmp |= IRDA_CR_CRC;             // CRC=1
1266                         tmp |= IRDA_CR_FIR_SIN;         // HP sin select = 1
1267
1268                         switch_bank(iobase, BANK2);
1269                         outb(tmp, iobase+FIR_IRDA_CR);
1270                 }
1271         }
1272
1273         switch_bank(iobase, BANK0);
1274
1275 }
1276
1277 /*
1278  * Function ali_ircc_sir_write (driver)
1279  *
1280  *    Fill Tx FIFO with transmit data
1281  *
1282  */
1283 static int ali_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1284 {
1285         int actual = 0;
1286
1287
1288         /* Tx FIFO should be empty! */
1289         if (!(inb(iobase+UART_LSR) & UART_LSR_THRE)) {
1290                 pr_debug("%s(), failed, fifo not empty!\n", __func__);
1291                 return 0;
1292         }
1293
1294         /* Fill FIFO with current frame */
1295         while ((fifo_size-- > 0) && (actual < len)) {
1296                 /* Transmit next byte */
1297                 outb(buf[actual], iobase+UART_TX);
1298
1299                 actual++;
1300         }
1301
1302         return actual;
1303 }
1304
1305 /*
1306  * Function ali_ircc_net_open (dev)
1307  *
1308  *    Start the device
1309  *
1310  */
1311 static int ali_ircc_net_open(struct net_device *dev)
1312 {
1313         struct ali_ircc_cb *self;
1314         int iobase;
1315         char hwname[32];
1316
1317
1318         IRDA_ASSERT(dev != NULL, return -1;);
1319
1320         self = netdev_priv(dev);
1321
1322         IRDA_ASSERT(self != NULL, return 0;);
1323
1324         iobase = self->io.fir_base;
1325
1326         /* Request IRQ and install Interrupt Handler */
1327         if (request_irq(self->io.irq, ali_ircc_interrupt, 0, dev->name, dev))
1328         {
1329                 net_warn_ratelimited("%s, unable to allocate irq=%d\n",
1330                                      ALI_IRCC_DRIVER_NAME, self->io.irq);
1331                 return -EAGAIN;
1332         }
1333
1334         /*
1335          * Always allocate the DMA channel after the IRQ, and clean up on
1336          * failure.
1337          */
1338         if (request_dma(self->io.dma, dev->name)) {
1339                 net_warn_ratelimited("%s, unable to allocate dma=%d\n",
1340                                      ALI_IRCC_DRIVER_NAME, self->io.dma);
1341                 free_irq(self->io.irq, dev);
1342                 return -EAGAIN;
1343         }
1344
1345         /* Turn on interrups */
1346         outb(UART_IER_RDI , iobase+UART_IER);
1347
1348         /* Ready to play! */
1349         netif_start_queue(dev); //benjamin by irport
1350
1351         /* Give self a hardware name */
1352         sprintf(hwname, "ALI-FIR @ 0x%03x", self->io.fir_base);
1353
1354         /*
1355          * Open new IrLAP layer instance, now that everything should be
1356          * initialized properly
1357          */
1358         self->irlap = irlap_open(dev, &self->qos, hwname);
1359
1360
1361         return 0;
1362 }
1363
1364 /*
1365  * Function ali_ircc_net_close (dev)
1366  *
1367  *    Stop the device
1368  *
1369  */
1370 static int ali_ircc_net_close(struct net_device *dev)
1371 {
1372
1373         struct ali_ircc_cb *self;
1374         //int iobase;
1375
1376
1377         IRDA_ASSERT(dev != NULL, return -1;);
1378
1379         self = netdev_priv(dev);
1380         IRDA_ASSERT(self != NULL, return 0;);
1381
1382         /* Stop device */
1383         netif_stop_queue(dev);
1384
1385         /* Stop and remove instance of IrLAP */
1386         if (self->irlap)
1387                 irlap_close(self->irlap);
1388         self->irlap = NULL;
1389
1390         disable_dma(self->io.dma);
1391
1392         /* Disable interrupts */
1393         SetCOMInterrupts(self, FALSE);
1394
1395         free_irq(self->io.irq, dev);
1396         free_dma(self->io.dma);
1397
1398
1399         return 0;
1400 }
1401
1402 /*
1403  * Function ali_ircc_fir_hard_xmit (skb, dev)
1404  *
1405  *    Transmit the frame
1406  *
1407  */
1408 static netdev_tx_t ali_ircc_fir_hard_xmit(struct sk_buff *skb,
1409                                                 struct net_device *dev)
1410 {
1411         struct ali_ircc_cb *self;
1412         unsigned long flags;
1413         int iobase;
1414         __u32 speed;
1415         int mtt, diff;
1416
1417
1418         self = netdev_priv(dev);
1419         iobase = self->io.fir_base;
1420
1421         netif_stop_queue(dev);
1422
1423         /* Make sure tests *& speed change are atomic */
1424         spin_lock_irqsave(&self->lock, flags);
1425
1426         /* Note : you should make sure that speed changes are not going
1427          * to corrupt any outgoing frame. Look at nsc-ircc for the gory
1428          * details - Jean II */
1429
1430         /* Check if we need to change the speed */
1431         speed = irda_get_next_speed(skb);
1432         if ((speed != self->io.speed) && (speed != -1)) {
1433                 /* Check for empty frame */
1434                 if (!skb->len) {
1435                         ali_ircc_change_speed(self, speed);
1436                         dev->trans_start = jiffies;
1437                         spin_unlock_irqrestore(&self->lock, flags);
1438                         dev_kfree_skb(skb);
1439                         return NETDEV_TX_OK;
1440                 } else
1441                         self->new_speed = speed;
1442         }
1443
1444         /* Register and copy this frame to DMA memory */
1445         self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
1446         self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
1447         self->tx_fifo.tail += skb->len;
1448
1449         dev->stats.tx_bytes += skb->len;
1450
1451         skb_copy_from_linear_data(skb, self->tx_fifo.queue[self->tx_fifo.free].start,
1452                       skb->len);
1453         self->tx_fifo.len++;
1454         self->tx_fifo.free++;
1455
1456         /* Start transmit only if there is currently no transmit going on */
1457         if (self->tx_fifo.len == 1)
1458         {
1459                 /* Check if we must wait the min turn time or not */
1460                 mtt = irda_get_mtt(skb);
1461
1462                 if (mtt)
1463                 {
1464                         /* Check how much time we have used already */
1465                         diff = ktime_us_delta(ktime_get(), self->stamp);
1466                         /* self->stamp is set from ali_ircc_dma_receive_complete() */
1467
1468                         pr_debug("%s(), ******* diff = %d *******\n",
1469                                  __func__, diff);
1470
1471                         /* Check if the mtt is larger than the time we have
1472                          * already used by all the protocol processing
1473                          */
1474                         if (mtt > diff)
1475                         {
1476                                 mtt -= diff;
1477
1478                                 /*
1479                                  * Use timer if delay larger than 1000 us, and
1480                                  * use udelay for smaller values which should
1481                                  * be acceptable
1482                                  */
1483                                 if (mtt > 500)
1484                                 {
1485                                         /* Adjust for timer resolution */
1486                                         mtt = (mtt+250) / 500;  /* 4 discard, 5 get advanced, Let's round off */
1487
1488                                         pr_debug("%s(), ************** mtt = %d ***********\n",
1489                                                  __func__, mtt);
1490
1491                                         /* Setup timer */
1492                                         if (mtt == 1) /* 500 us */
1493                                         {
1494                                                 switch_bank(iobase, BANK1);
1495                                                 outb(TIMER_IIR_500, iobase+FIR_TIMER_IIR);
1496                                         }
1497                                         else if (mtt == 2) /* 1 ms */
1498                                         {
1499                                                 switch_bank(iobase, BANK1);
1500                                                 outb(TIMER_IIR_1ms, iobase+FIR_TIMER_IIR);
1501                                         }
1502                                         else /* > 2ms -> 4ms */
1503                                         {
1504                                                 switch_bank(iobase, BANK1);
1505                                                 outb(TIMER_IIR_2ms, iobase+FIR_TIMER_IIR);
1506                                         }
1507
1508
1509                                         /* Start timer */
1510                                         outb(inb(iobase+FIR_CR) | CR_TIMER_EN, iobase+FIR_CR);
1511                                         self->io.direction = IO_XMIT;
1512
1513                                         /* Enable timer interrupt */
1514                                         self->ier = IER_TIMER;
1515                                         SetCOMInterrupts(self, TRUE);
1516
1517                                         /* Timer will take care of the rest */
1518                                         goto out;
1519                                 }
1520                                 else
1521                                         udelay(mtt);
1522                         } // if (if (mtt > diff)
1523                 }// if (mtt)
1524
1525                 /* Enable EOM interrupt */
1526                 self->ier = IER_EOM;
1527                 SetCOMInterrupts(self, TRUE);
1528
1529                 /* Transmit frame */
1530                 ali_ircc_dma_xmit(self);
1531         } // if (self->tx_fifo.len == 1)
1532
1533  out:
1534
1535         /* Not busy transmitting anymore if window is not full */
1536         if (self->tx_fifo.free < MAX_TX_WINDOW)
1537                 netif_wake_queue(self->netdev);
1538
1539         /* Restore bank register */
1540         switch_bank(iobase, BANK0);
1541
1542         dev->trans_start = jiffies;
1543         spin_unlock_irqrestore(&self->lock, flags);
1544         dev_kfree_skb(skb);
1545
1546         return NETDEV_TX_OK;
1547 }
1548
1549
1550 static void ali_ircc_dma_xmit(struct ali_ircc_cb *self)
1551 {
1552         int iobase, tmp;
1553         unsigned char FIFO_OPTI, Hi, Lo;
1554
1555
1556
1557         iobase = self->io.fir_base;
1558
1559         /* FIFO threshold , this method comes from NDIS5 code */
1560
1561         if(self->tx_fifo.queue[self->tx_fifo.ptr].len < TX_FIFO_Threshold)
1562                 FIFO_OPTI = self->tx_fifo.queue[self->tx_fifo.ptr].len-1;
1563         else
1564                 FIFO_OPTI = TX_FIFO_Threshold;
1565
1566         /* Disable DMA */
1567         switch_bank(iobase, BANK1);
1568         outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1569
1570         self->io.direction = IO_XMIT;
1571
1572         irda_setup_dma(self->io.dma,
1573                        ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start -
1574                         self->tx_buff.head) + self->tx_buff_dma,
1575                        self->tx_fifo.queue[self->tx_fifo.ptr].len,
1576                        DMA_TX_MODE);
1577
1578         /* Reset Tx FIFO */
1579         switch_bank(iobase, BANK0);
1580         outb(LCR_A_FIFO_RESET, iobase+FIR_LCR_A);
1581
1582         /* Set Tx FIFO threshold */
1583         if (self->fifo_opti_buf!=FIFO_OPTI)
1584         {
1585                 switch_bank(iobase, BANK1);
1586                 outb(FIFO_OPTI, iobase+FIR_FIFO_TR) ;
1587                 self->fifo_opti_buf=FIFO_OPTI;
1588         }
1589
1590         /* Set Tx DMA threshold */
1591         switch_bank(iobase, BANK1);
1592         outb(TX_DMA_Threshold, iobase+FIR_DMA_TR);
1593
1594         /* Set max Tx frame size */
1595         Hi = (self->tx_fifo.queue[self->tx_fifo.ptr].len >> 8) & 0x0f;
1596         Lo = self->tx_fifo.queue[self->tx_fifo.ptr].len & 0xff;
1597         switch_bank(iobase, BANK2);
1598         outb(Hi, iobase+FIR_TX_DSR_HI);
1599         outb(Lo, iobase+FIR_TX_DSR_LO);
1600
1601         /* Disable SIP , Disable Brick Wall (we don't support in TX mode), Change to TX mode */
1602         switch_bank(iobase, BANK0);
1603         tmp = inb(iobase+FIR_LCR_B);
1604         tmp &= ~0x20; // Disable SIP
1605         outb(((unsigned char)(tmp & 0x3f) | LCR_B_TX_MODE) & ~LCR_B_BW, iobase+FIR_LCR_B);
1606         pr_debug("%s(), *** Change to TX mode: FIR_LCR_B = 0x%x ***\n",
1607                  __func__, inb(iobase + FIR_LCR_B));
1608
1609         outb(0, iobase+FIR_LSR);
1610
1611         /* Enable DMA and Burst Mode */
1612         switch_bank(iobase, BANK1);
1613         outb(inb(iobase+FIR_CR) | CR_DMA_EN | CR_DMA_BURST, iobase+FIR_CR);
1614
1615         switch_bank(iobase, BANK0);
1616
1617 }
1618
1619 static int  ali_ircc_dma_xmit_complete(struct ali_ircc_cb *self)
1620 {
1621         int iobase;
1622         int ret = TRUE;
1623
1624
1625         iobase = self->io.fir_base;
1626
1627         /* Disable DMA */
1628         switch_bank(iobase, BANK1);
1629         outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1630
1631         /* Check for underrun! */
1632         switch_bank(iobase, BANK0);
1633         if((inb(iobase+FIR_LSR) & LSR_FRAME_ABORT) == LSR_FRAME_ABORT)
1634
1635         {
1636                 net_err_ratelimited("%s(), ********* LSR_FRAME_ABORT *********\n",
1637                                     __func__);
1638                 self->netdev->stats.tx_errors++;
1639                 self->netdev->stats.tx_fifo_errors++;
1640         }
1641         else
1642         {
1643                 self->netdev->stats.tx_packets++;
1644         }
1645
1646         /* Check if we need to change the speed */
1647         if (self->new_speed)
1648         {
1649                 ali_ircc_change_speed(self, self->new_speed);
1650                 self->new_speed = 0;
1651         }
1652
1653         /* Finished with this frame, so prepare for next */
1654         self->tx_fifo.ptr++;
1655         self->tx_fifo.len--;
1656
1657         /* Any frames to be sent back-to-back? */
1658         if (self->tx_fifo.len)
1659         {
1660                 ali_ircc_dma_xmit(self);
1661
1662                 /* Not finished yet! */
1663                 ret = FALSE;
1664         }
1665         else
1666         {       /* Reset Tx FIFO info */
1667                 self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
1668                 self->tx_fifo.tail = self->tx_buff.head;
1669         }
1670
1671         /* Make sure we have room for more frames */
1672         if (self->tx_fifo.free < MAX_TX_WINDOW) {
1673                 /* Not busy transmitting anymore */
1674                 /* Tell the network layer, that we can accept more frames */
1675                 netif_wake_queue(self->netdev);
1676         }
1677
1678         switch_bank(iobase, BANK0);
1679
1680         return ret;
1681 }
1682
1683 /*
1684  * Function ali_ircc_dma_receive (self)
1685  *
1686  *    Get ready for receiving a frame. The device will initiate a DMA
1687  *    if it starts to receive a frame.
1688  *
1689  */
1690 static int ali_ircc_dma_receive(struct ali_ircc_cb *self)
1691 {
1692         int iobase, tmp;
1693
1694
1695         iobase = self->io.fir_base;
1696
1697         /* Reset Tx FIFO info */
1698         self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
1699         self->tx_fifo.tail = self->tx_buff.head;
1700
1701         /* Disable DMA */
1702         switch_bank(iobase, BANK1);
1703         outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1704
1705         /* Reset Message Count */
1706         switch_bank(iobase, BANK0);
1707         outb(0x07, iobase+FIR_LSR);
1708
1709         self->rcvFramesOverflow = FALSE;
1710
1711         self->LineStatus = inb(iobase+FIR_LSR) ;
1712
1713         /* Reset Rx FIFO info */
1714         self->io.direction = IO_RECV;
1715         self->rx_buff.data = self->rx_buff.head;
1716
1717         /* Reset Rx FIFO */
1718         // switch_bank(iobase, BANK0);
1719         outb(LCR_A_FIFO_RESET, iobase+FIR_LCR_A);
1720
1721         self->st_fifo.len = self->st_fifo.pending_bytes = 0;
1722         self->st_fifo.tail = self->st_fifo.head = 0;
1723
1724         irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1725                        DMA_RX_MODE);
1726
1727         /* Set Receive Mode,Brick Wall */
1728         //switch_bank(iobase, BANK0);
1729         tmp = inb(iobase+FIR_LCR_B);
1730         outb((unsigned char)(tmp &0x3f) | LCR_B_RX_MODE | LCR_B_BW , iobase + FIR_LCR_B); // 2000/12/1 05:16PM
1731         pr_debug("%s(), *** Change To RX mode: FIR_LCR_B = 0x%x ***\n",
1732                  __func__, inb(iobase + FIR_LCR_B));
1733
1734         /* Set Rx Threshold */
1735         switch_bank(iobase, BANK1);
1736         outb(RX_FIFO_Threshold, iobase+FIR_FIFO_TR);
1737         outb(RX_DMA_Threshold, iobase+FIR_DMA_TR);
1738
1739         /* Enable DMA and Burst Mode */
1740         // switch_bank(iobase, BANK1);
1741         outb(CR_DMA_EN | CR_DMA_BURST, iobase+FIR_CR);
1742
1743         switch_bank(iobase, BANK0);
1744         return 0;
1745 }
1746
1747 static int  ali_ircc_dma_receive_complete(struct ali_ircc_cb *self)
1748 {
1749         struct st_fifo *st_fifo;
1750         struct sk_buff *skb;
1751         __u8 status, MessageCount;
1752         int len, i, iobase, val;
1753
1754         st_fifo = &self->st_fifo;
1755         iobase = self->io.fir_base;
1756
1757         switch_bank(iobase, BANK0);
1758         MessageCount = inb(iobase+ FIR_LSR)&0x07;
1759
1760         if (MessageCount > 0)
1761                 pr_debug("%s(), Message count = %d\n", __func__, MessageCount);
1762
1763         for (i=0; i<=MessageCount; i++)
1764         {
1765                 /* Bank 0 */
1766                 switch_bank(iobase, BANK0);
1767                 status = inb(iobase+FIR_LSR);
1768
1769                 switch_bank(iobase, BANK2);
1770                 len = inb(iobase+FIR_RX_DSR_HI) & 0x0f;
1771                 len = len << 8;
1772                 len |= inb(iobase+FIR_RX_DSR_LO);
1773
1774                 pr_debug("%s(), RX Length = 0x%.2x,\n", __func__ , len);
1775                 pr_debug("%s(), RX Status = 0x%.2x,\n", __func__ , status);
1776
1777                 if (st_fifo->tail >= MAX_RX_WINDOW) {
1778                         pr_debug("%s(), window is full!\n", __func__);
1779                         continue;
1780                 }
1781
1782                 st_fifo->entries[st_fifo->tail].status = status;
1783                 st_fifo->entries[st_fifo->tail].len = len;
1784                 st_fifo->pending_bytes += len;
1785                 st_fifo->tail++;
1786                 st_fifo->len++;
1787         }
1788
1789         for (i=0; i<=MessageCount; i++)
1790         {
1791                 /* Get first entry */
1792                 status = st_fifo->entries[st_fifo->head].status;
1793                 len    = st_fifo->entries[st_fifo->head].len;
1794                 st_fifo->pending_bytes -= len;
1795                 st_fifo->head++;
1796                 st_fifo->len--;
1797
1798                 /* Check for errors */
1799                 if ((status & 0xd8) || self->rcvFramesOverflow || (len==0))
1800                 {
1801                         pr_debug("%s(), ************* RX Errors ************\n",
1802                                  __func__);
1803
1804                         /* Skip frame */
1805                         self->netdev->stats.rx_errors++;
1806
1807                         self->rx_buff.data += len;
1808
1809                         if (status & LSR_FIFO_UR)
1810                         {
1811                                 self->netdev->stats.rx_frame_errors++;
1812                                 pr_debug("%s(), ************* FIFO Errors ************\n",
1813                                          __func__);
1814                         }
1815                         if (status & LSR_FRAME_ERROR)
1816                         {
1817                                 self->netdev->stats.rx_frame_errors++;
1818                                 pr_debug("%s(), ************* FRAME Errors ************\n",
1819                                          __func__);
1820                         }
1821
1822                         if (status & LSR_CRC_ERROR)
1823                         {
1824                                 self->netdev->stats.rx_crc_errors++;
1825                                 pr_debug("%s(), ************* CRC Errors ************\n",
1826                                          __func__);
1827                         }
1828
1829                         if(self->rcvFramesOverflow)
1830                         {
1831                                 self->netdev->stats.rx_frame_errors++;
1832                                 pr_debug("%s(), ************* Overran DMA buffer ************\n",
1833                                          __func__);
1834                         }
1835                         if(len == 0)
1836                         {
1837                                 self->netdev->stats.rx_frame_errors++;
1838                                 pr_debug("%s(), ********** Receive Frame Size = 0 *********\n",
1839                                          __func__);
1840                         }
1841                 }
1842                 else
1843                 {
1844
1845                         if (st_fifo->pending_bytes < 32)
1846                         {
1847                                 switch_bank(iobase, BANK0);
1848                                 val = inb(iobase+FIR_BSR);
1849                                 if ((val& BSR_FIFO_NOT_EMPTY)== 0x80)
1850                                 {
1851                                         pr_debug("%s(), ************* BSR_FIFO_NOT_EMPTY ************\n",
1852                                                  __func__);
1853
1854                                         /* Put this entry back in fifo */
1855                                         st_fifo->head--;
1856                                         st_fifo->len++;
1857                                         st_fifo->pending_bytes += len;
1858                                         st_fifo->entries[st_fifo->head].status = status;
1859                                         st_fifo->entries[st_fifo->head].len = len;
1860
1861                                         /*
1862                                         * DMA not finished yet, so try again
1863                                         * later, set timer value, resolution
1864                                         * 500 us
1865                                         */
1866
1867                                         switch_bank(iobase, BANK1);
1868                                         outb(TIMER_IIR_500, iobase+FIR_TIMER_IIR); // 2001/1/2 05:07PM
1869
1870                                         /* Enable Timer */
1871                                         outb(inb(iobase+FIR_CR) | CR_TIMER_EN, iobase+FIR_CR);
1872
1873                                         return FALSE; /* I'll be back! */
1874                                 }
1875                         }
1876
1877                         /*
1878                          * Remember the time we received this frame, so we can
1879                          * reduce the min turn time a bit since we will know
1880                          * how much time we have used for protocol processing
1881                          */
1882                         self->stamp = ktime_get();
1883
1884                         skb = dev_alloc_skb(len+1);
1885                         if (skb == NULL)
1886                         {
1887                                 self->netdev->stats.rx_dropped++;
1888
1889                                 return FALSE;
1890                         }
1891
1892                         /* Make sure IP header gets aligned */
1893                         skb_reserve(skb, 1);
1894
1895                         /* Copy frame without CRC, CRC is removed by hardware*/
1896                         skb_put(skb, len);
1897                         skb_copy_to_linear_data(skb, self->rx_buff.data, len);
1898
1899                         /* Move to next frame */
1900                         self->rx_buff.data += len;
1901                         self->netdev->stats.rx_bytes += len;
1902                         self->netdev->stats.rx_packets++;
1903
1904                         skb->dev = self->netdev;
1905                         skb_reset_mac_header(skb);
1906                         skb->protocol = htons(ETH_P_IRDA);
1907                         netif_rx(skb);
1908                 }
1909         }
1910
1911         switch_bank(iobase, BANK0);
1912
1913         return TRUE;
1914 }
1915
1916
1917
1918 /*
1919  * Function ali_ircc_sir_hard_xmit (skb, dev)
1920  *
1921  *    Transmit the frame!
1922  *
1923  */
1924 static netdev_tx_t ali_ircc_sir_hard_xmit(struct sk_buff *skb,
1925                                                 struct net_device *dev)
1926 {
1927         struct ali_ircc_cb *self;
1928         unsigned long flags;
1929         int iobase;
1930         __u32 speed;
1931
1932
1933         IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
1934
1935         self = netdev_priv(dev);
1936         IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1937
1938         iobase = self->io.sir_base;
1939
1940         netif_stop_queue(dev);
1941
1942         /* Make sure tests *& speed change are atomic */
1943         spin_lock_irqsave(&self->lock, flags);
1944
1945         /* Note : you should make sure that speed changes are not going
1946          * to corrupt any outgoing frame. Look at nsc-ircc for the gory
1947          * details - Jean II */
1948
1949         /* Check if we need to change the speed */
1950         speed = irda_get_next_speed(skb);
1951         if ((speed != self->io.speed) && (speed != -1)) {
1952                 /* Check for empty frame */
1953                 if (!skb->len) {
1954                         ali_ircc_change_speed(self, speed);
1955                         dev->trans_start = jiffies;
1956                         spin_unlock_irqrestore(&self->lock, flags);
1957                         dev_kfree_skb(skb);
1958                         return NETDEV_TX_OK;
1959                 } else
1960                         self->new_speed = speed;
1961         }
1962
1963         /* Init tx buffer */
1964         self->tx_buff.data = self->tx_buff.head;
1965
1966         /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
1967         self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1968                                            self->tx_buff.truesize);
1969
1970         self->netdev->stats.tx_bytes += self->tx_buff.len;
1971
1972         /* Turn on transmit finished interrupt. Will fire immediately!  */
1973         outb(UART_IER_THRI, iobase+UART_IER);
1974
1975         dev->trans_start = jiffies;
1976         spin_unlock_irqrestore(&self->lock, flags);
1977
1978         dev_kfree_skb(skb);
1979
1980
1981         return NETDEV_TX_OK;
1982 }
1983
1984
1985 /*
1986  * Function ali_ircc_net_ioctl (dev, rq, cmd)
1987  *
1988  *    Process IOCTL commands for this device
1989  *
1990  */
1991 static int ali_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1992 {
1993         struct if_irda_req *irq = (struct if_irda_req *) rq;
1994         struct ali_ircc_cb *self;
1995         unsigned long flags;
1996         int ret = 0;
1997
1998
1999         IRDA_ASSERT(dev != NULL, return -1;);
2000
2001         self = netdev_priv(dev);
2002
2003         IRDA_ASSERT(self != NULL, return -1;);
2004
2005         pr_debug("%s(), %s, (cmd=0x%X)\n", __func__ , dev->name, cmd);
2006
2007         switch (cmd) {
2008         case SIOCSBANDWIDTH: /* Set bandwidth */
2009                 pr_debug("%s(), SIOCSBANDWIDTH\n", __func__);
2010                 /*
2011                  * This function will also be used by IrLAP to change the
2012                  * speed, so we still must allow for speed change within
2013                  * interrupt context.
2014                  */
2015                 if (!in_interrupt() && !capable(CAP_NET_ADMIN))
2016                         return -EPERM;
2017
2018                 spin_lock_irqsave(&self->lock, flags);
2019                 ali_ircc_change_speed(self, irq->ifr_baudrate);
2020                 spin_unlock_irqrestore(&self->lock, flags);
2021                 break;
2022         case SIOCSMEDIABUSY: /* Set media busy */
2023                 pr_debug("%s(), SIOCSMEDIABUSY\n", __func__);
2024                 if (!capable(CAP_NET_ADMIN))
2025                         return -EPERM;
2026                 irda_device_set_media_busy(self->netdev, TRUE);
2027                 break;
2028         case SIOCGRECEIVING: /* Check if we are receiving right now */
2029                 pr_debug("%s(), SIOCGRECEIVING\n", __func__);
2030                 /* This is protected */
2031                 irq->ifr_receiving = ali_ircc_is_receiving(self);
2032                 break;
2033         default:
2034                 ret = -EOPNOTSUPP;
2035         }
2036
2037
2038         return ret;
2039 }
2040
2041 /*
2042  * Function ali_ircc_is_receiving (self)
2043  *
2044  *    Return TRUE is we are currently receiving a frame
2045  *
2046  */
2047 static int ali_ircc_is_receiving(struct ali_ircc_cb *self)
2048 {
2049         unsigned long flags;
2050         int status = FALSE;
2051         int iobase;
2052
2053
2054         IRDA_ASSERT(self != NULL, return FALSE;);
2055
2056         spin_lock_irqsave(&self->lock, flags);
2057
2058         if (self->io.speed > 115200)
2059         {
2060                 iobase = self->io.fir_base;
2061
2062                 switch_bank(iobase, BANK1);
2063                 if((inb(iobase+FIR_FIFO_FR) & 0x3f) != 0)
2064                 {
2065                         /* We are receiving something */
2066                         pr_debug("%s(), We are receiving something\n",
2067                                  __func__);
2068                         status = TRUE;
2069                 }
2070                 switch_bank(iobase, BANK0);
2071         }
2072         else
2073         {
2074                 status = (self->rx_buff.state != OUTSIDE_FRAME);
2075         }
2076
2077         spin_unlock_irqrestore(&self->lock, flags);
2078
2079
2080         return status;
2081 }
2082
2083 static int ali_ircc_suspend(struct platform_device *dev, pm_message_t state)
2084 {
2085         struct ali_ircc_cb *self = platform_get_drvdata(dev);
2086
2087         net_info_ratelimited("%s, Suspending\n", ALI_IRCC_DRIVER_NAME);
2088
2089         if (self->io.suspended)
2090                 return 0;
2091
2092         ali_ircc_net_close(self->netdev);
2093
2094         self->io.suspended = 1;
2095
2096         return 0;
2097 }
2098
2099 static int ali_ircc_resume(struct platform_device *dev)
2100 {
2101         struct ali_ircc_cb *self = platform_get_drvdata(dev);
2102
2103         if (!self->io.suspended)
2104                 return 0;
2105
2106         ali_ircc_net_open(self->netdev);
2107
2108         net_info_ratelimited("%s, Waking up\n", ALI_IRCC_DRIVER_NAME);
2109
2110         self->io.suspended = 0;
2111
2112         return 0;
2113 }
2114
2115 /* ALi Chip Function */
2116
2117 static void SetCOMInterrupts(struct ali_ircc_cb *self , unsigned char enable)
2118 {
2119
2120         unsigned char newMask;
2121
2122         int iobase = self->io.fir_base; /* or sir_base */
2123
2124         pr_debug("%s(), -------- Start -------- ( Enable = %d )\n",
2125                  __func__, enable);
2126
2127         /* Enable the interrupt which we wish to */
2128         if (enable){
2129                 if (self->io.direction == IO_XMIT)
2130                 {
2131                         if (self->io.speed > 115200) /* FIR, MIR */
2132                         {
2133                                 newMask = self->ier;
2134                         }
2135                         else /* SIR */
2136                         {
2137                                 newMask = UART_IER_THRI | UART_IER_RDI;
2138                         }
2139                 }
2140                 else {
2141                         if (self->io.speed > 115200) /* FIR, MIR */
2142                         {
2143                                 newMask = self->ier;
2144                         }
2145                         else /* SIR */
2146                         {
2147                                 newMask = UART_IER_RDI;
2148                         }
2149                 }
2150         }
2151         else /* Disable all the interrupts */
2152         {
2153                 newMask = 0x00;
2154
2155         }
2156
2157         //SIR and FIR has different registers
2158         if (self->io.speed > 115200)
2159         {
2160                 switch_bank(iobase, BANK0);
2161                 outb(newMask, iobase+FIR_IER);
2162         }
2163         else
2164                 outb(newMask, iobase+UART_IER);
2165
2166 }
2167
2168 static void SIR2FIR(int iobase)
2169 {
2170         //unsigned char tmp;
2171
2172
2173         /* Already protected (change_speed() or setup()), no need to lock.
2174          * Jean II */
2175
2176         outb(0x28, iobase+UART_MCR);
2177         outb(0x68, iobase+UART_MCR);
2178         outb(0x88, iobase+UART_MCR);
2179
2180         outb(0x60, iobase+FIR_MCR);     /*  Master Reset */
2181         outb(0x20, iobase+FIR_MCR);     /*  Master Interrupt Enable */
2182
2183         //tmp = inb(iobase+FIR_LCR_B);  /* SIP enable */
2184         //tmp |= 0x20;
2185         //outb(tmp, iobase+FIR_LCR_B);
2186
2187 }
2188
2189 static void FIR2SIR(int iobase)
2190 {
2191         unsigned char val;
2192
2193
2194         /* Already protected (change_speed() or setup()), no need to lock.
2195          * Jean II */
2196
2197         outb(0x20, iobase+FIR_MCR);     /* IRQ to low */
2198         outb(0x00, iobase+UART_IER);
2199
2200         outb(0xA0, iobase+FIR_MCR);     /* Don't set master reset */
2201         outb(0x00, iobase+UART_FCR);
2202         outb(0x07, iobase+UART_FCR);
2203
2204         val = inb(iobase+UART_RX);
2205         val = inb(iobase+UART_LSR);
2206         val = inb(iobase+UART_MSR);
2207
2208 }
2209
2210 MODULE_AUTHOR("Benjamin Kong <benjamin_kong@ali.com.tw>");
2211 MODULE_DESCRIPTION("ALi FIR Controller Driver");
2212 MODULE_LICENSE("GPL");
2213 MODULE_ALIAS("platform:" ALI_IRCC_DRIVER_NAME);
2214
2215
2216 module_param_array(io, int, NULL, 0);
2217 MODULE_PARM_DESC(io, "Base I/O addresses");
2218 module_param_array(irq, int, NULL, 0);
2219 MODULE_PARM_DESC(irq, "IRQ lines");
2220 module_param_array(dma, int, NULL, 0);
2221 MODULE_PARM_DESC(dma, "DMA channels");
2222
2223 module_init(ali_ircc_init);
2224 module_exit(ali_ircc_cleanup);