2 * Texas Instruments 3-Port Ethernet Switch Address Lookup Engine
4 * Copyright (C) 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/seq_file.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/stat.h>
23 #include <linux/sysfs.h>
24 #include <linux/etherdevice.h>
28 #define BITMASK(bits) (BIT(bits) - 1)
30 #define ALE_VERSION_MAJOR(rev) ((rev >> 8) & 0xff)
31 #define ALE_VERSION_MINOR(rev) (rev & 0xff)
34 #define ALE_IDVER 0x00
35 #define ALE_CONTROL 0x08
36 #define ALE_PRESCALE 0x10
37 #define ALE_UNKNOWNVLAN 0x18
38 #define ALE_TABLE_CONTROL 0x20
39 #define ALE_TABLE 0x34
40 #define ALE_PORTCTL 0x40
42 #define ALE_TABLE_WRITE BIT(31)
44 #define ALE_TYPE_FREE 0
45 #define ALE_TYPE_ADDR 1
46 #define ALE_TYPE_VLAN 2
47 #define ALE_TYPE_VLAN_ADDR 3
49 #define ALE_UCAST_PERSISTANT 0
50 #define ALE_UCAST_UNTOUCHED 1
51 #define ALE_UCAST_OUI 2
52 #define ALE_UCAST_TOUCHED 3
54 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
60 idx = 2 - idx; /* flip */
61 return (ale_entry[idx] >> start) & BITMASK(bits);
64 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
69 value &= BITMASK(bits);
72 idx = 2 - idx; /* flip */
73 ale_entry[idx] &= ~(BITMASK(bits) << start);
74 ale_entry[idx] |= (value << start);
77 #define DEFINE_ALE_FIELD(name, start, bits) \
78 static inline int cpsw_ale_get_##name(u32 *ale_entry) \
80 return cpsw_ale_get_field(ale_entry, start, bits); \
82 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
84 cpsw_ale_set_field(ale_entry, start, bits, value); \
87 DEFINE_ALE_FIELD(entry_type, 60, 2)
88 DEFINE_ALE_FIELD(vlan_id, 48, 12)
89 DEFINE_ALE_FIELD(mcast_state, 62, 2)
90 DEFINE_ALE_FIELD(port_mask, 66, 3)
91 DEFINE_ALE_FIELD(super, 65, 1)
92 DEFINE_ALE_FIELD(ucast_type, 62, 2)
93 DEFINE_ALE_FIELD(port_num, 66, 2)
94 DEFINE_ALE_FIELD(blocked, 65, 1)
95 DEFINE_ALE_FIELD(secure, 64, 1)
96 DEFINE_ALE_FIELD(vlan_untag_force, 24, 3)
97 DEFINE_ALE_FIELD(vlan_reg_mcast, 16, 3)
98 DEFINE_ALE_FIELD(vlan_unreg_mcast, 8, 3)
99 DEFINE_ALE_FIELD(vlan_member_list, 0, 3)
100 DEFINE_ALE_FIELD(mcast, 40, 1)
102 /* The MAC address field in the ALE entry cannot be macroized as above */
103 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
107 for (i = 0; i < 6; i++)
108 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
111 static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
115 for (i = 0; i < 6; i++)
116 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
119 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry)
123 WARN_ON(idx > ale->params.ale_entries);
125 __raw_writel(idx, ale->params.ale_regs + ALE_TABLE_CONTROL);
127 for (i = 0; i < ALE_ENTRY_WORDS; i++)
128 ale_entry[i] = __raw_readl(ale->params.ale_regs +
134 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry)
138 WARN_ON(idx > ale->params.ale_entries);
140 for (i = 0; i < ALE_ENTRY_WORDS; i++)
141 __raw_writel(ale_entry[i], ale->params.ale_regs +
144 __raw_writel(idx | ALE_TABLE_WRITE, ale->params.ale_regs +
150 static int cpsw_ale_match_addr(struct cpsw_ale *ale, u8 *addr, u16 vid)
152 u32 ale_entry[ALE_ENTRY_WORDS];
155 for (idx = 0; idx < ale->params.ale_entries; idx++) {
158 cpsw_ale_read(ale, idx, ale_entry);
159 type = cpsw_ale_get_entry_type(ale_entry);
160 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
162 if (cpsw_ale_get_vlan_id(ale_entry) != vid)
164 cpsw_ale_get_addr(ale_entry, entry_addr);
165 if (ether_addr_equal(entry_addr, addr))
171 static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid)
173 u32 ale_entry[ALE_ENTRY_WORDS];
176 for (idx = 0; idx < ale->params.ale_entries; idx++) {
177 cpsw_ale_read(ale, idx, ale_entry);
178 type = cpsw_ale_get_entry_type(ale_entry);
179 if (type != ALE_TYPE_VLAN)
181 if (cpsw_ale_get_vlan_id(ale_entry) == vid)
187 static int cpsw_ale_match_free(struct cpsw_ale *ale)
189 u32 ale_entry[ALE_ENTRY_WORDS];
192 for (idx = 0; idx < ale->params.ale_entries; idx++) {
193 cpsw_ale_read(ale, idx, ale_entry);
194 type = cpsw_ale_get_entry_type(ale_entry);
195 if (type == ALE_TYPE_FREE)
201 static int cpsw_ale_find_ageable(struct cpsw_ale *ale)
203 u32 ale_entry[ALE_ENTRY_WORDS];
206 for (idx = 0; idx < ale->params.ale_entries; idx++) {
207 cpsw_ale_read(ale, idx, ale_entry);
208 type = cpsw_ale_get_entry_type(ale_entry);
209 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
211 if (cpsw_ale_get_mcast(ale_entry))
213 type = cpsw_ale_get_ucast_type(ale_entry);
214 if (type != ALE_UCAST_PERSISTANT &&
215 type != ALE_UCAST_OUI)
221 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry,
226 mask = cpsw_ale_get_port_mask(ale_entry);
227 if ((mask & port_mask) == 0)
228 return; /* ports dont intersect, not interested */
231 /* free if only remaining port is host port */
233 cpsw_ale_set_port_mask(ale_entry, mask);
235 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
238 int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid)
240 u32 ale_entry[ALE_ENTRY_WORDS];
243 for (idx = 0; idx < ale->params.ale_entries; idx++) {
244 cpsw_ale_read(ale, idx, ale_entry);
245 ret = cpsw_ale_get_entry_type(ale_entry);
246 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
249 /* if vid passed is -1 then remove all multicast entry from
250 * the table irrespective of vlan id, if a valid vlan id is
251 * passed then remove only multicast added to that vlan id.
252 * if vlan id doesn't match then move on to next entry.
254 if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid)
257 if (cpsw_ale_get_mcast(ale_entry)) {
260 cpsw_ale_get_addr(ale_entry, addr);
261 if (!is_broadcast_ether_addr(addr))
262 cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
265 cpsw_ale_write(ale, idx, ale_entry);
269 EXPORT_SYMBOL_GPL(cpsw_ale_flush_multicast);
271 static void cpsw_ale_flush_ucast(struct cpsw_ale *ale, u32 *ale_entry,
276 port = cpsw_ale_get_port_num(ale_entry);
277 if ((BIT(port) & port_mask) == 0)
278 return; /* ports dont intersect, not interested */
279 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
282 int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask)
284 u32 ale_entry[ALE_ENTRY_WORDS];
287 for (idx = 0; idx < ale->params.ale_entries; idx++) {
288 cpsw_ale_read(ale, idx, ale_entry);
289 ret = cpsw_ale_get_entry_type(ale_entry);
290 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
293 if (cpsw_ale_get_mcast(ale_entry))
294 cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
296 cpsw_ale_flush_ucast(ale, ale_entry, port_mask);
298 cpsw_ale_write(ale, idx, ale_entry);
302 EXPORT_SYMBOL_GPL(cpsw_ale_flush);
304 static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry,
307 if (flags & ALE_VLAN) {
308 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
309 cpsw_ale_set_vlan_id(ale_entry, vid);
311 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
315 int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port,
318 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
321 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
323 cpsw_ale_set_addr(ale_entry, addr);
324 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
325 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
326 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
327 cpsw_ale_set_port_num(ale_entry, port);
329 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
331 idx = cpsw_ale_match_free(ale);
333 idx = cpsw_ale_find_ageable(ale);
337 cpsw_ale_write(ale, idx, ale_entry);
340 EXPORT_SYMBOL_GPL(cpsw_ale_add_ucast);
342 int cpsw_ale_del_ucast(struct cpsw_ale *ale, u8 *addr, int port,
345 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
348 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
352 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
353 cpsw_ale_write(ale, idx, ale_entry);
356 EXPORT_SYMBOL_GPL(cpsw_ale_del_ucast);
358 int cpsw_ale_add_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask,
359 int flags, u16 vid, int mcast_state)
361 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
364 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
366 cpsw_ale_read(ale, idx, ale_entry);
368 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
370 cpsw_ale_set_addr(ale_entry, addr);
371 cpsw_ale_set_super(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
372 cpsw_ale_set_mcast_state(ale_entry, mcast_state);
374 mask = cpsw_ale_get_port_mask(ale_entry);
376 cpsw_ale_set_port_mask(ale_entry, port_mask);
379 idx = cpsw_ale_match_free(ale);
381 idx = cpsw_ale_find_ageable(ale);
385 cpsw_ale_write(ale, idx, ale_entry);
388 EXPORT_SYMBOL_GPL(cpsw_ale_add_mcast);
390 int cpsw_ale_del_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask,
393 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
396 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
400 cpsw_ale_read(ale, idx, ale_entry);
403 cpsw_ale_set_port_mask(ale_entry, port_mask);
405 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
407 cpsw_ale_write(ale, idx, ale_entry);
410 EXPORT_SYMBOL_GPL(cpsw_ale_del_mcast);
412 int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag,
413 int reg_mcast, int unreg_mcast)
415 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
418 idx = cpsw_ale_match_vlan(ale, vid);
420 cpsw_ale_read(ale, idx, ale_entry);
422 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN);
423 cpsw_ale_set_vlan_id(ale_entry, vid);
425 cpsw_ale_set_vlan_untag_force(ale_entry, untag);
426 cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast);
427 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast);
428 cpsw_ale_set_vlan_member_list(ale_entry, port);
431 idx = cpsw_ale_match_free(ale);
433 idx = cpsw_ale_find_ageable(ale);
437 cpsw_ale_write(ale, idx, ale_entry);
440 EXPORT_SYMBOL_GPL(cpsw_ale_add_vlan);
442 int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask)
444 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
447 idx = cpsw_ale_match_vlan(ale, vid);
451 cpsw_ale_read(ale, idx, ale_entry);
454 cpsw_ale_set_vlan_member_list(ale_entry, port_mask);
456 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
458 cpsw_ale_write(ale, idx, ale_entry);
461 EXPORT_SYMBOL_GPL(cpsw_ale_del_vlan);
463 void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti)
465 u32 ale_entry[ALE_ENTRY_WORDS];
469 /* Only bother doing the work if the setting is actually changing */
470 if (ale->allmulti == allmulti)
473 /* Remember the new setting to check against next time */
474 ale->allmulti = allmulti;
476 for (idx = 0; idx < ale->params.ale_entries; idx++) {
477 cpsw_ale_read(ale, idx, ale_entry);
478 type = cpsw_ale_get_entry_type(ale_entry);
479 if (type != ALE_TYPE_VLAN)
482 unreg_mcast = cpsw_ale_get_vlan_unreg_mcast(ale_entry);
487 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast);
488 cpsw_ale_write(ale, idx, ale_entry);
491 EXPORT_SYMBOL_GPL(cpsw_ale_set_allmulti);
493 struct ale_control_info {
495 int offset, port_offset;
496 int shift, port_shift;
500 static const struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = {
503 .offset = ALE_CONTROL,
511 .offset = ALE_CONTROL,
519 .offset = ALE_CONTROL,
525 [ALE_P0_UNI_FLOOD] = {
526 .name = "port0_unicast_flood",
527 .offset = ALE_CONTROL,
533 [ALE_VLAN_NOLEARN] = {
534 .name = "vlan_nolearn",
535 .offset = ALE_CONTROL,
541 [ALE_NO_PORT_VLAN] = {
542 .name = "no_port_vlan",
543 .offset = ALE_CONTROL,
551 .offset = ALE_CONTROL,
559 .offset = ALE_CONTROL,
565 [ALE_RATE_LIMIT_TX] = {
566 .name = "rate_limit_tx",
567 .offset = ALE_CONTROL,
574 .name = "vlan_aware",
575 .offset = ALE_CONTROL,
581 [ALE_AUTH_ENABLE] = {
582 .name = "auth_enable",
583 .offset = ALE_CONTROL,
590 .name = "rate_limit",
591 .offset = ALE_CONTROL,
598 .name = "port_state",
599 .offset = ALE_PORTCTL,
605 [ALE_PORT_DROP_UNTAGGED] = {
606 .name = "drop_untagged",
607 .offset = ALE_PORTCTL,
613 [ALE_PORT_DROP_UNKNOWN_VLAN] = {
614 .name = "drop_unknown",
615 .offset = ALE_PORTCTL,
621 [ALE_PORT_NOLEARN] = {
623 .offset = ALE_PORTCTL,
629 [ALE_PORT_NO_SA_UPDATE] = {
630 .name = "no_source_update",
631 .offset = ALE_PORTCTL,
637 [ALE_PORT_MCAST_LIMIT] = {
638 .name = "mcast_limit",
639 .offset = ALE_PORTCTL,
645 [ALE_PORT_BCAST_LIMIT] = {
646 .name = "bcast_limit",
647 .offset = ALE_PORTCTL,
653 [ALE_PORT_UNKNOWN_VLAN_MEMBER] = {
654 .name = "unknown_vlan_member",
655 .offset = ALE_UNKNOWNVLAN,
661 [ALE_PORT_UNKNOWN_MCAST_FLOOD] = {
662 .name = "unknown_mcast_flood",
663 .offset = ALE_UNKNOWNVLAN,
669 [ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = {
670 .name = "unknown_reg_flood",
671 .offset = ALE_UNKNOWNVLAN,
677 [ALE_PORT_UNTAGGED_EGRESS] = {
678 .name = "untagged_egress",
679 .offset = ALE_UNKNOWNVLAN,
687 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
690 const struct ale_control_info *info;
694 if (control < 0 || control >= ARRAY_SIZE(ale_controls))
697 info = &ale_controls[control];
698 if (info->port_offset == 0 && info->port_shift == 0)
699 port = 0; /* global, port is a dont care */
701 if (port < 0 || port > ale->params.ale_ports)
704 mask = BITMASK(info->bits);
708 offset = info->offset + (port * info->port_offset);
709 shift = info->shift + (port * info->port_shift);
711 tmp = __raw_readl(ale->params.ale_regs + offset);
712 tmp = (tmp & ~(mask << shift)) | (value << shift);
713 __raw_writel(tmp, ale->params.ale_regs + offset);
717 EXPORT_SYMBOL_GPL(cpsw_ale_control_set);
719 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
721 const struct ale_control_info *info;
725 if (control < 0 || control >= ARRAY_SIZE(ale_controls))
728 info = &ale_controls[control];
729 if (info->port_offset == 0 && info->port_shift == 0)
730 port = 0; /* global, port is a dont care */
732 if (port < 0 || port > ale->params.ale_ports)
735 offset = info->offset + (port * info->port_offset);
736 shift = info->shift + (port * info->port_shift);
738 tmp = __raw_readl(ale->params.ale_regs + offset) >> shift;
739 return tmp & BITMASK(info->bits);
741 EXPORT_SYMBOL_GPL(cpsw_ale_control_get);
743 static void cpsw_ale_timer(unsigned long arg)
745 struct cpsw_ale *ale = (struct cpsw_ale *)arg;
747 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
750 ale->timer.expires = jiffies + ale->ageout;
751 add_timer(&ale->timer);
755 int cpsw_ale_set_ageout(struct cpsw_ale *ale, int ageout)
757 del_timer_sync(&ale->timer);
758 ale->ageout = ageout * HZ;
760 ale->timer.expires = jiffies + ale->ageout;
761 add_timer(&ale->timer);
765 EXPORT_SYMBOL_GPL(cpsw_ale_set_ageout);
767 void cpsw_ale_start(struct cpsw_ale *ale)
771 rev = __raw_readl(ale->params.ale_regs + ALE_IDVER);
772 dev_dbg(ale->params.dev, "initialized cpsw ale revision %d.%d\n",
773 ALE_VERSION_MAJOR(rev), ALE_VERSION_MINOR(rev));
774 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1);
775 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
777 init_timer(&ale->timer);
778 ale->timer.data = (unsigned long)ale;
779 ale->timer.function = cpsw_ale_timer;
781 ale->timer.expires = jiffies + ale->ageout;
782 add_timer(&ale->timer);
785 EXPORT_SYMBOL_GPL(cpsw_ale_start);
787 void cpsw_ale_stop(struct cpsw_ale *ale)
789 del_timer_sync(&ale->timer);
791 EXPORT_SYMBOL_GPL(cpsw_ale_stop);
793 struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
795 struct cpsw_ale *ale;
797 ale = kzalloc(sizeof(*ale), GFP_KERNEL);
801 ale->params = *params;
802 ale->ageout = ale->params.ale_ageout * HZ;
806 EXPORT_SYMBOL_GPL(cpsw_ale_create);
808 int cpsw_ale_destroy(struct cpsw_ale *ale)
812 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
816 EXPORT_SYMBOL_GPL(cpsw_ale_destroy);
818 void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data)
822 for (i = 0; i < ale->params.ale_entries; i++) {
823 cpsw_ale_read(ale, i, data);
824 data += ALE_ENTRY_WORDS;
827 EXPORT_SYMBOL_GPL(cpsw_ale_dump);
829 MODULE_LICENSE("GPL v2");
830 MODULE_DESCRIPTION("TI CPSW ALE driver");
831 MODULE_AUTHOR("Texas Instruments");