kernel/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/pinctrl/consumer.h>
  47 #ifdef CONFIG_DEBUG_FS
  48 #include <linux/debugfs.h>
  49 #include <linux/seq_file.h>
  50 #endif /* CONFIG_DEBUG_FS */
  51 #include <linux/net_tstamp.h>
  52 #include "stmmac_ptp.h"
  53 #include "stmmac.h"
  54 #include <linux/reset.h>
  55
  56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  57
  58 /* Module parameters */
  59 #define TX_TIMEO        5000
  60 static int watchdog = TX_TIMEO;
  61 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  63
  64 static int debug = -1;
  65 module_param(debug, int, S_IRUGO | S_IWUSR);
  66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  67
  68 static int phyaddr = -1;
  69 module_param(phyaddr, int, S_IRUGO);
  70 MODULE_PARM_DESC(phyaddr, "Physical device address");
  71
  72 #define DMA_TX_SIZE 256
  73 static int dma_txsize = DMA_TX_SIZE;
  74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  76
  77 #define DMA_RX_SIZE 256
  78 static int dma_rxsize = DMA_RX_SIZE;
  79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
  80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
  81
  82 static int flow_ctrl = FLOW_OFF;
  83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  85
  86 static int pause = PAUSE_TIME;
  87 module_param(pause, int, S_IRUGO | S_IWUSR);
  88 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  89
  90 #define TC_DEFAULT 64
  91 static int tc = TC_DEFAULT;
  92 module_param(tc, int, S_IRUGO | S_IWUSR);
  93 MODULE_PARM_DESC(tc, "DMA threshold control value");
  94
  95 #define DEFAULT_BUFSIZE 1536
  96 static int buf_sz = DEFAULT_BUFSIZE;
  97 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  98 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  99
 100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 101                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 102                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 103
 104 #define STMMAC_DEFAULT_LPI_TIMER        1000
 105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 106 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 109
 110 /* By default the driver will use the ring mode to manage tx and rx descriptors
 111  * but passing this value so user can force to use the chain instead of the ring
 112  */
 113 static unsigned int chain_mode;
 114 module_param(chain_mode, int, S_IRUGO);
 115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 116
 117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 118
 119 #ifdef CONFIG_DEBUG_FS
 120 static int stmmac_init_fs(struct net_device *dev);
 121 static void stmmac_exit_fs(struct net_device *dev);
 122 #endif
 123
 124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 125
 126 /**
 127  * stmmac_verify_args - verify the driver parameters.
 128  * Description: it checks the driver parameters and set a default in case of
 129  * errors.
 130  */
 131 static void stmmac_verify_args(void)
 132 {
 133         if (unlikely(watchdog < 0))
 134                 watchdog = TX_TIMEO;
 135         if (unlikely(dma_rxsize < 0))
 136                 dma_rxsize = DMA_RX_SIZE;
 137         if (unlikely(dma_txsize < 0))
 138                 dma_txsize = DMA_TX_SIZE;
 139         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 140                 buf_sz = DEFAULT_BUFSIZE;
 141         if (unlikely(flow_ctrl > 1))
 142                 flow_ctrl = FLOW_AUTO;
 143         else if (likely(flow_ctrl < 0))
 144                 flow_ctrl = FLOW_OFF;
 145         if (unlikely((pause < 0) || (pause > 0xffff)))
 146                 pause = PAUSE_TIME;
 147         if (eee_timer < 0)
 148                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 149 }
 150
 151 /**
 152  * stmmac_clk_csr_set - dynamically set the MDC clock
 153  * @priv: driver private structure
 154  * Description: this is to dynamically set the MDC clock according to the csr
 155  * clock input.
 156  * Note:
 157  *      If a specific clk_csr value is passed from the platform
 158  *      this means that the CSR Clock Range selection cannot be
 159  *      changed at run-time and it is fixed (as reported in the driver
 160  *      documentation). Viceversa the driver will try to set the MDC
 161  *      clock dynamically according to the actual clock input.
 162  */
 163 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 164 {
 165         u32 clk_rate;
 166
 167         clk_rate = clk_get_rate(priv->stmmac_clk);
 168
 169         /* Platform provided default clk_csr would be assumed valid
 170          * for all other cases except for the below mentioned ones.
 171          * For values higher than the IEEE 802.3 specified frequency
 172          * we can not estimate the proper divider as it is not known
 173          * the frequency of clk_csr_i. So we do not change the default
 174          * divider.
 175          */
 176         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 177                 if (clk_rate < CSR_F_35M)
 178                         priv->clk_csr = STMMAC_CSR_20_35M;
 179                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 180                         priv->clk_csr = STMMAC_CSR_35_60M;
 181                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 182                         priv->clk_csr = STMMAC_CSR_60_100M;
 183                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 184                         priv->clk_csr = STMMAC_CSR_100_150M;
 185                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 186                         priv->clk_csr = STMMAC_CSR_150_250M;
 187                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 188                         priv->clk_csr = STMMAC_CSR_250_300M;
 189         }
 190 }
 191
 192 static void print_pkt(unsigned char *buf, int len)
 193 {
 194         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 195         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 196 }
 197
 198 /* minimum number of free TX descriptors required to wake up TX process */
 199 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 200
 201 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 202 {
 203         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 204 }
 205
 206 /**
 207  * stmmac_hw_fix_mac_speed - callback for speed selection
 208  * @priv: driver private structure
 209  * Description: on some platforms (e.g. ST), some HW system configuraton
 210  * registers have to be set according to the link speed negotiated.
 211  */
 212 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 213 {
 214         struct phy_device *phydev = priv->phydev;
 215
 216         if (likely(priv->plat->fix_mac_speed))
 217                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 218 }
 219
 220 /**
 221  * stmmac_enable_eee_mode - check and enter in LPI mode
 222  * @priv: driver private structure
 223  * Description: this function is to verify and enter in LPI mode in case of
 224  * EEE.
 225  */
 226 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 227 {
 228         /* Check and enter in LPI mode */
 229         if ((priv->dirty_tx == priv->cur_tx) &&
 230             (priv->tx_path_in_lpi_mode == false))
 231                 priv->hw->mac->set_eee_mode(priv->hw);
 232 }
 233
 234 /**
 235  * stmmac_disable_eee_mode - disable and exit from LPI mode
 236  * @priv: driver private structure
 237  * Description: this function is to exit and disable EEE in case of
 238  * LPI state is true. This is called by the xmit.
 239  */
 240 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 241 {
 242         priv->hw->mac->reset_eee_mode(priv->hw);
 243         del_timer_sync(&priv->eee_ctrl_timer);
 244         priv->tx_path_in_lpi_mode = false;
 245 }
 246
 247 /**
 248  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 249  * @arg : data hook
 250  * Description:
 251  *  if there is no data transfer and if we are not in LPI state,
 252  *  then MAC Transmitter can be moved to LPI state.
 253  */
 254 static void stmmac_eee_ctrl_timer(unsigned long arg)
 255 {
 256         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 257
 258         stmmac_enable_eee_mode(priv);
 259         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 260 }
 261
 262 /**
 263  * stmmac_eee_init - init EEE
 264  * @priv: driver private structure
 265  * Description:
 266  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 267  *  can also manage EEE, this function enable the LPI state and start related
 268  *  timer.
 269  */
 270 bool stmmac_eee_init(struct stmmac_priv *priv)
 271 {
 272         char *phy_bus_name = priv->plat->phy_bus_name;
 273         unsigned long flags;
 274         bool ret = false;
 275
 276         /* Using PCS we cannot dial with the phy registers at this stage
 277          * so we do not support extra feature like EEE.
 278          */
 279         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
 280             (priv->pcs == STMMAC_PCS_RTBI))
 281                 goto out;
 282
 283         /* Never init EEE in case of a switch is attached */
 284         if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
 285                 goto out;
 286
 287         /* MAC core supports the EEE feature. */
 288         if (priv->dma_cap.eee) {
 289                 int tx_lpi_timer = priv->tx_lpi_timer;
 290
 291                 /* Check if the PHY supports EEE */
 292                 if (phy_init_eee(priv->phydev, 1)) {
 293                         /* To manage at run-time if the EEE cannot be supported
 294                          * anymore (for example because the lp caps have been
 295                          * changed).
 296                          * In that case the driver disable own timers.
 297                          */
 298                         spin_lock_irqsave(&priv->lock, flags);
 299                         if (priv->eee_active) {
 300                                 pr_debug("stmmac: disable EEE\n");
 301                                 del_timer_sync(&priv->eee_ctrl_timer);
 302                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
 303                                                              tx_lpi_timer);
 304                         }
 305                         priv->eee_active = 0;
 306                         spin_unlock_irqrestore(&priv->lock, flags);
 307                         goto out;
 308                 }
 309                 /* Activate the EEE and start timers */
 310                 spin_lock_irqsave(&priv->lock, flags);
 311                 if (!priv->eee_active) {
 312                         priv->eee_active = 1;
 313                         setup_timer(&priv->eee_ctrl_timer,
 314                                     stmmac_eee_ctrl_timer,
 315                                     (unsigned long)priv);
 316                         mod_timer(&priv->eee_ctrl_timer,
 317                                   STMMAC_LPI_T(eee_timer));
 318
 319                         priv->hw->mac->set_eee_timer(priv->hw,
 320                                                      STMMAC_DEFAULT_LIT_LS,
 321                                                      tx_lpi_timer);
 322                 }
 323                 /* Set HW EEE according to the speed */
 324                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
 325
 326                 ret = true;
 327                 spin_unlock_irqrestore(&priv->lock, flags);
 328
 329                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
 330         }
 331 out:
 332         return ret;
 333 }
 334
 335 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 336  * @priv: driver private structure
 337  * @entry : descriptor index to be used.
 338  * @skb : the socket buffer
 339  * Description :
 340  * This function will read timestamp from the descriptor & pass it to stack.
 341  * and also perform some sanity checks.
 342  */
 343 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 344                                    unsigned int entry, struct sk_buff *skb)
 345 {
 346         struct skb_shared_hwtstamps shhwtstamp;
 347         u64 ns;
 348         void *desc = NULL;
 349
 350         if (!priv->hwts_tx_en)
 351                 return;
 352
 353         /* exit if skb doesn't support hw tstamp */
 354         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 355                 return;
 356
 357         if (priv->adv_ts)
 358                 desc = (priv->dma_etx + entry);
 359         else
 360                 desc = (priv->dma_tx + entry);
 361
 362         /* check tx tstamp status */
 363         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 364                 return;
 365
 366         /* get the valid tstamp */
 367         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 368
 369         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 370         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 371         /* pass tstamp to stack */
 372         skb_tstamp_tx(skb, &shhwtstamp);
 373
 374         return;
 375 }
 376
 377 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 378  * @priv: driver private structure
 379  * @entry : descriptor index to be used.
 380  * @skb : the socket buffer
 381  * Description :
 382  * This function will read received packet's timestamp from the descriptor
 383  * and pass it to stack. It also perform some sanity checks.
 384  */
 385 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 386                                    unsigned int entry, struct sk_buff *skb)
 387 {
 388         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 389         u64 ns;
 390         void *desc = NULL;
 391
 392         if (!priv->hwts_rx_en)
 393                 return;
 394
 395         if (priv->adv_ts)
 396                 desc = (priv->dma_erx + entry);
 397         else
 398                 desc = (priv->dma_rx + entry);
 399
 400         /* exit if rx tstamp is not valid */
 401         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 402                 return;
 403
 404         /* get valid tstamp */
 405         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 406         shhwtstamp = skb_hwtstamps(skb);
 407         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 408         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 409 }
 410
 411 /**
 412  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 413  *  @dev: device pointer.
 414  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 415  *  a proprietary structure used to pass information to the driver.
 416  *  Description:
 417  *  This function configures the MAC to enable/disable both outgoing(TX)
 418  *  and incoming(RX) packets time stamping based on user input.
 419  *  Return Value:
 420  *  0 on success and an appropriate -ve integer on failure.
 421  */
 422 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 423 {
 424         struct stmmac_priv *priv = netdev_priv(dev);
 425         struct hwtstamp_config config;
 426         struct timespec now;
 427         u64 temp = 0;
 428         u32 ptp_v2 = 0;
 429         u32 tstamp_all = 0;
 430         u32 ptp_over_ipv4_udp = 0;
 431         u32 ptp_over_ipv6_udp = 0;
 432         u32 ptp_over_ethernet = 0;
 433         u32 snap_type_sel = 0;
 434         u32 ts_master_en = 0;
 435         u32 ts_event_en = 0;
 436         u32 value = 0;
 437
 438         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 439                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 440                 priv->hwts_tx_en = 0;
 441                 priv->hwts_rx_en = 0;
 442
 443                 return -EOPNOTSUPP;
 444         }
 445
 446         if (copy_from_user(&config, ifr->ifr_data,
 447                            sizeof(struct hwtstamp_config)))
 448                 return -EFAULT;
 449
 450         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 451                  __func__, config.flags, config.tx_type, config.rx_filter);
 452
 453         /* reserved for future extensions */
 454         if (config.flags)
 455                 return -EINVAL;
 456
 457         if (config.tx_type != HWTSTAMP_TX_OFF &&
 458             config.tx_type != HWTSTAMP_TX_ON)
 459                 return -ERANGE;
 460
 461         if (priv->adv_ts) {
 462                 switch (config.rx_filter) {
 463                 case HWTSTAMP_FILTER_NONE:
 464                         /* time stamp no incoming packet at all */
 465                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 466                         break;
 467
 468                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 469                         /* PTP v1, UDP, any kind of event packet */
 470                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 471                         /* take time stamp for all event messages */
 472                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 473
 474                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 475                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 476                         break;
 477
 478                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 479                         /* PTP v1, UDP, Sync packet */
 480                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 481                         /* take time stamp for SYNC messages only */
 482                         ts_event_en = PTP_TCR_TSEVNTENA;
 483
 484                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 485                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 486                         break;
 487
 488                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 489                         /* PTP v1, UDP, Delay_req packet */
 490                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 491                         /* take time stamp for Delay_Req messages only */
 492                         ts_master_en = PTP_TCR_TSMSTRENA;
 493                         ts_event_en = PTP_TCR_TSEVNTENA;
 494
 495                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 496                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 497                         break;
 498
 499                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 500                         /* PTP v2, UDP, any kind of event packet */
 501                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 502                         ptp_v2 = PTP_TCR_TSVER2ENA;
 503                         /* take time stamp for all event messages */
 504                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 505
 506                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 507                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 508                         break;
 509
 510                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 511                         /* PTP v2, UDP, Sync packet */
 512                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 513                         ptp_v2 = PTP_TCR_TSVER2ENA;
 514                         /* take time stamp for SYNC messages only */
 515                         ts_event_en = PTP_TCR_TSEVNTENA;
 516
 517                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 518                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 519                         break;
 520
 521                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 522                         /* PTP v2, UDP, Delay_req packet */
 523                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 524                         ptp_v2 = PTP_TCR_TSVER2ENA;
 525                         /* take time stamp for Delay_Req messages only */
 526                         ts_master_en = PTP_TCR_TSMSTRENA;
 527                         ts_event_en = PTP_TCR_TSEVNTENA;
 528
 529                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 530                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 531                         break;
 532
 533                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 534                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 535                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 536                         ptp_v2 = PTP_TCR_TSVER2ENA;
 537                         /* take time stamp for all event messages */
 538                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 539
 540                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 541                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 542                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 543                         break;
 544
 545                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 546                         /* PTP v2/802.AS1, any layer, Sync packet */
 547                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 548                         ptp_v2 = PTP_TCR_TSVER2ENA;
 549                         /* take time stamp for SYNC messages only */
 550                         ts_event_en = PTP_TCR_TSEVNTENA;
 551
 552                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 553                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 554                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 555                         break;
 556
 557                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 558                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 559                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 560                         ptp_v2 = PTP_TCR_TSVER2ENA;
 561                         /* take time stamp for Delay_Req messages only */
 562                         ts_master_en = PTP_TCR_TSMSTRENA;
 563                         ts_event_en = PTP_TCR_TSEVNTENA;
 564
 565                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 566                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 567                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 568                         break;
 569
 570                 case HWTSTAMP_FILTER_ALL:
 571                         /* time stamp any incoming packet */
 572                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 573                         tstamp_all = PTP_TCR_TSENALL;
 574                         break;
 575
 576                 default:
 577                         return -ERANGE;
 578                 }
 579         } else {
 580                 switch (config.rx_filter) {
 581                 case HWTSTAMP_FILTER_NONE:
 582                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 583                         break;
 584                 default:
 585                         /* PTP v1, UDP, any kind of event packet */
 586                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 587                         break;
 588                 }
 589         }
 590         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 591         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 592
 593         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 594                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 595         else {
 596                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 597                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 598                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 599                          ts_master_en | snap_type_sel);
 600
 601                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 602
 603                 /* program Sub Second Increment reg */
 604                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
 605
 606                 /* calculate default added value:
 607                  * formula is :
 608                  * addend = (2^32)/freq_div_ratio;
 609                  * where, freq_div_ratio = clk_ptp_ref_i/50MHz
 610                  * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
 611                  * NOTE: clk_ptp_ref_i should be >= 50MHz to
 612                  *       achieve 20ns accuracy.
 613                  *
 614                  * 2^x * y == (y << x), hence
 615                  * 2^32 * 50000000 ==> (50000000 << 32)
 616                  */
 617                 temp = (u64) (50000000ULL << 32);
 618                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
 619                 priv->hw->ptp->config_addend(priv->ioaddr,
 620                                              priv->default_addend);
 621
 622                 /* initialize system time */
 623                 getnstimeofday(&now);
 624                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
 625                                             now.tv_nsec);
 626         }
 627
 628         return copy_to_user(ifr->ifr_data, &config,
 629                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 630 }
 631
 632 /**
 633  * stmmac_init_ptp - init PTP
 634  * @priv: driver private structure
 635  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 636  * This is done by looking at the HW cap. register.
 637  * This function also registers the ptp driver.
 638  */
 639 static int stmmac_init_ptp(struct stmmac_priv *priv)
 640 {
 641         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 642                 return -EOPNOTSUPP;
 643
 644         /* Fall-back to main clock in case of no PTP ref is passed */
 645         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
 646         if (IS_ERR(priv->clk_ptp_ref)) {
 647                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
 648                 priv->clk_ptp_ref = NULL;
 649         } else {
 650                 clk_prepare_enable(priv->clk_ptp_ref);
 651                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
 652         }
 653
 654         priv->adv_ts = 0;
 655         if (priv->dma_cap.atime_stamp && priv->extend_desc)
 656                 priv->adv_ts = 1;
 657
 658         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
 659                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 660
 661         if (netif_msg_hw(priv) && priv->adv_ts)
 662                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
 663
 664         priv->hw->ptp = &stmmac_ptp;
 665         priv->hwts_tx_en = 0;
 666         priv->hwts_rx_en = 0;
 667
 668         return stmmac_ptp_register(priv);
 669 }
 670
 671 static void stmmac_release_ptp(struct stmmac_priv *priv)
 672 {
 673         if (priv->clk_ptp_ref)
 674                 clk_disable_unprepare(priv->clk_ptp_ref);
 675         stmmac_ptp_unregister(priv);
 676 }
 677
 678 /**
 679  * stmmac_adjust_link - adjusts the link parameters
 680  * @dev: net device structure
 681  * Description: this is the helper called by the physical abstraction layer
 682  * drivers to communicate the phy link status. According the speed and duplex
 683  * this driver can invoke registered glue-logic as well.
 684  * It also invoke the eee initialization because it could happen when switch
 685  * on different networks (that are eee capable).
 686  */
 687 static void stmmac_adjust_link(struct net_device *dev)
 688 {
 689         struct stmmac_priv *priv = netdev_priv(dev);
 690         struct phy_device *phydev = priv->phydev;
 691         unsigned long flags;
 692         int new_state = 0;
 693         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 694
 695         if (phydev == NULL)
 696                 return;
 697
 698         spin_lock_irqsave(&priv->lock, flags);
 699
 700         if (phydev->link) {
 701                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 702
 703                 /* Now we make sure that we can be in full duplex mode.
 704                  * If not, we operate in half-duplex mode. */
 705                 if (phydev->duplex != priv->oldduplex) {
 706                         new_state = 1;
 707                         if (!(phydev->duplex))
 708                                 ctrl &= ~priv->hw->link.duplex;
 709                         else
 710                                 ctrl |= priv->hw->link.duplex;
 711                         priv->oldduplex = phydev->duplex;
 712                 }
 713                 /* Flow Control operation */
 714                 if (phydev->pause)
 715                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
 716                                                  fc, pause_time);
 717
 718                 if (phydev->speed != priv->speed) {
 719                         new_state = 1;
 720                         switch (phydev->speed) {
 721                         case 1000:
 722                                 if (likely(priv->plat->has_gmac))
 723                                         ctrl &= ~priv->hw->link.port;
 724                                 stmmac_hw_fix_mac_speed(priv);
 725                                 break;
 726                         case 100:
 727                         case 10:
 728                                 if (priv->plat->has_gmac) {
 729                                         ctrl |= priv->hw->link.port;
 730                                         if (phydev->speed == SPEED_100) {
 731                                                 ctrl |= priv->hw->link.speed;
 732                                         } else {
 733                                                 ctrl &= ~(priv->hw->link.speed);
 734                                         }
 735                                 } else {
 736                                         ctrl &= ~priv->hw->link.port;
 737                                 }
 738                                 stmmac_hw_fix_mac_speed(priv);
 739                                 break;
 740                         default:
 741                                 if (netif_msg_link(priv))
 742                                         pr_warn("%s: Speed (%d) not 10/100\n",
 743                                                 dev->name, phydev->speed);
 744                                 break;
 745                         }
 746
 747                         priv->speed = phydev->speed;
 748                 }
 749
 750                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 751
 752                 if (!priv->oldlink) {
 753                         new_state = 1;
 754                         priv->oldlink = 1;
 755                 }
 756         } else if (priv->oldlink) {
 757                 new_state = 1;
 758                 priv->oldlink = 0;
 759                 priv->speed = 0;
 760                 priv->oldduplex = -1;
 761         }
 762
 763         if (new_state && netif_msg_link(priv))
 764                 phy_print_status(phydev);
 765
 766         spin_unlock_irqrestore(&priv->lock, flags);
 767
 768         /* At this stage, it could be needed to setup the EEE or adjust some
 769          * MAC related HW registers.
 770          */
 771         priv->eee_enabled = stmmac_eee_init(priv);
 772 }
 773
 774 /**
 775  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 776  * @priv: driver private structure
 777  * Description: this is to verify if the HW supports the PCS.
 778  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 779  * configured for the TBI, RTBI, or SGMII PHY interface.
 780  */
 781 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 782 {
 783         int interface = priv->plat->interface;
 784
 785         if (priv->dma_cap.pcs) {
 786                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 787                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 788                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 789                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 790                         pr_debug("STMMAC: PCS RGMII support enable\n");
 791                         priv->pcs = STMMAC_PCS_RGMII;
 792                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 793                         pr_debug("STMMAC: PCS SGMII support enable\n");
 794                         priv->pcs = STMMAC_PCS_SGMII;
 795                 }
 796         }
 797 }
 798
 799 /**
 800  * stmmac_init_phy - PHY initialization
 801  * @dev: net device structure
 802  * Description: it initializes the driver's PHY state, and attaches the PHY
 803  * to the mac driver.
 804  *  Return value:
 805  *  0 on success
 806  */
 807 static int stmmac_init_phy(struct net_device *dev)
 808 {
 809         struct stmmac_priv *priv = netdev_priv(dev);
 810         struct phy_device *phydev;
 811         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 812         char bus_id[MII_BUS_ID_SIZE];
 813         int interface = priv->plat->interface;
 814         int max_speed = priv->plat->max_speed;
 815         priv->oldlink = 0;
 816         priv->speed = 0;
 817         priv->oldduplex = -1;
 818
 819         if (priv->plat->phy_bus_name)
 820                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 821                          priv->plat->phy_bus_name, priv->plat->bus_id);
 822         else
 823                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 824                          priv->plat->bus_id);
 825
 826         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 827                  priv->plat->phy_addr);
 828         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 829
 830         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 831
 832         if (IS_ERR_OR_NULL(phydev)) {
 833                 pr_err("%s: Could not attach to PHY\n", dev->name);
 834                 if (!phydev)
 835                         return -ENODEV;
 836
 837                 return PTR_ERR(phydev);
 838         }
 839
 840         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 841         if ((interface == PHY_INTERFACE_MODE_MII) ||
 842             (interface == PHY_INTERFACE_MODE_RMII) ||
 843                 (max_speed < 1000 && max_speed > 0))
 844                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 845                                          SUPPORTED_1000baseT_Full);
 846
 847         /*
 848          * Broken HW is sometimes missing the pull-up resistor on the
 849          * MDIO line, which results in reads to non-existent devices returning
 850          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 851          * device as well.
 852          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 853          */
 854         if (phydev->phy_id == 0) {
 855                 phy_disconnect(phydev);
 856                 return -ENODEV;
 857         }
 858         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 859                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 860
 861         priv->phydev = phydev;
 862
 863         return 0;
 864 }
 865
 866 /**
 867  * stmmac_display_ring - display ring
 868  * @head: pointer to the head of the ring passed.
 869  * @size: size of the ring.
 870  * @extend_desc: to verify if extended descriptors are used.
 871  * Description: display the control/status and buffer descriptors.
 872  */
 873 static void stmmac_display_ring(void *head, int size, int extend_desc)
 874 {
 875         int i;
 876         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
 877         struct dma_desc *p = (struct dma_desc *)head;
 878
 879         for (i = 0; i < size; i++) {
 880                 u64 x;
 881                 if (extend_desc) {
 882                         x = *(u64 *) ep;
 883                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 884                                 i, (unsigned int)virt_to_phys(ep),
 885                                 (unsigned int)x, (unsigned int)(x >> 32),
 886                                 ep->basic.des2, ep->basic.des3);
 887                         ep++;
 888                 } else {
 889                         x = *(u64 *) p;
 890                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 891                                 i, (unsigned int)virt_to_phys(p),
 892                                 (unsigned int)x, (unsigned int)(x >> 32),
 893                                 p->des2, p->des3);
 894                         p++;
 895                 }
 896                 pr_info("\n");
 897         }
 898 }
 899
 900 static void stmmac_display_rings(struct stmmac_priv *priv)
 901 {
 902         unsigned int txsize = priv->dma_tx_size;
 903         unsigned int rxsize = priv->dma_rx_size;
 904
 905         if (priv->extend_desc) {
 906                 pr_info("Extended RX descriptor ring:\n");
 907                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
 908                 pr_info("Extended TX descriptor ring:\n");
 909                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
 910         } else {
 911                 pr_info("RX descriptor ring:\n");
 912                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 913                 pr_info("TX descriptor ring:\n");
 914                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 915         }
 916 }
 917
 918 static int stmmac_set_bfsize(int mtu, int bufsize)
 919 {
 920         int ret = bufsize;
 921
 922         if (mtu >= BUF_SIZE_4KiB)
 923                 ret = BUF_SIZE_8KiB;
 924         else if (mtu >= BUF_SIZE_2KiB)
 925                 ret = BUF_SIZE_4KiB;
 926         else if (mtu > DEFAULT_BUFSIZE)
 927                 ret = BUF_SIZE_2KiB;
 928         else
 929                 ret = DEFAULT_BUFSIZE;
 930
 931         return ret;
 932 }
 933
 934 /**
 935  * stmmac_clear_descriptors - clear descriptors
 936  * @priv: driver private structure
 937  * Description: this function is called to clear the tx and rx descriptors
 938  * in case of both basic and extended descriptors are used.
 939  */
 940 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 941 {
 942         int i;
 943         unsigned int txsize = priv->dma_tx_size;
 944         unsigned int rxsize = priv->dma_rx_size;
 945
 946         /* Clear the Rx/Tx descriptors */
 947         for (i = 0; i < rxsize; i++)
 948                 if (priv->extend_desc)
 949                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 950                                                      priv->use_riwt, priv->mode,
 951                                                      (i == rxsize - 1));
 952                 else
 953                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 954                                                      priv->use_riwt, priv->mode,
 955                                                      (i == rxsize - 1));
 956         for (i = 0; i < txsize; i++)
 957                 if (priv->extend_desc)
 958                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 959                                                      priv->mode,
 960                                                      (i == txsize - 1));
 961                 else
 962                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 963                                                      priv->mode,
 964                                                      (i == txsize - 1));
 965 }
 966
 967 /**
 968  * stmmac_init_rx_buffers - init the RX descriptor buffer.
 969  * @priv: driver private structure
 970  * @p: descriptor pointer
 971  * @i: descriptor index
 972  * @flags: gfp flag.
 973  * Description: this function is called to allocate a receive buffer, perform
 974  * the DMA mapping and init the descriptor.
 975  */
 976 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 977                                   int i, gfp_t flags)
 978 {
 979         struct sk_buff *skb;
 980
 981         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
 982                                  flags);
 983         if (!skb) {
 984                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 985                 return -ENOMEM;
 986         }
 987         skb_reserve(skb, NET_IP_ALIGN);
 988         priv->rx_skbuff[i] = skb;
 989         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 990                                                 priv->dma_buf_sz,
 991                                                 DMA_FROM_DEVICE);
 992         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
 993                 pr_err("%s: DMA mapping error\n", __func__);
 994                 dev_kfree_skb_any(skb);
 995                 return -EINVAL;
 996         }
 997
 998         p->des2 = priv->rx_skbuff_dma[i];
 999
1000         if ((priv->hw->mode->init_desc3) &&
1001             (priv->dma_buf_sz == BUF_SIZE_16KiB))
1002                 priv->hw->mode->init_desc3(p);
1003
1004         return 0;
1005 }
1006
1007 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1008 {
1009         if (priv->rx_skbuff[i]) {
1010                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1011                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1012                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1013         }
1014         priv->rx_skbuff[i] = NULL;
1015 }
1016
1017 /**
1018  * init_dma_desc_rings - init the RX/TX descriptor rings
1019  * @dev: net device structure
1020  * @flags: gfp flag.
1021  * Description: this function initializes the DMA RX/TX descriptors
1022  * and allocates the socket buffers. It suppors the chained and ring
1023  * modes.
1024  */
1025 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1026 {
1027         int i;
1028         struct stmmac_priv *priv = netdev_priv(dev);
1029         unsigned int txsize = priv->dma_tx_size;
1030         unsigned int rxsize = priv->dma_rx_size;
1031         unsigned int bfsize = 0;
1032         int ret = -ENOMEM;
1033
1034         if (priv->hw->mode->set_16kib_bfsize)
1035                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1036
1037         if (bfsize < BUF_SIZE_16KiB)
1038                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1039
1040         priv->dma_buf_sz = bfsize;
1041
1042         if (netif_msg_probe(priv))
1043                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1044                          txsize, rxsize, bfsize);
1045
1046         if (netif_msg_probe(priv)) {
1047                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1048                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1049
1050                 /* RX INITIALIZATION */
1051                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1052         }
1053         for (i = 0; i < rxsize; i++) {
1054                 struct dma_desc *p;
1055                 if (priv->extend_desc)
1056                         p = &((priv->dma_erx + i)->basic);
1057                 else
1058                         p = priv->dma_rx + i;
1059
1060                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1061                 if (ret)
1062                         goto err_init_rx_buffers;
1063
1064                 if (netif_msg_probe(priv))
1065                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1066                                  priv->rx_skbuff[i]->data,
1067                                  (unsigned int)priv->rx_skbuff_dma[i]);
1068         }
1069         priv->cur_rx = 0;
1070         priv->dirty_rx = (unsigned int)(i - rxsize);
1071         buf_sz = bfsize;
1072
1073         /* Setup the chained descriptor addresses */
1074         if (priv->mode == STMMAC_CHAIN_MODE) {
1075                 if (priv->extend_desc) {
1076                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1077                                              rxsize, 1);
1078                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1079                                              txsize, 1);
1080                 } else {
1081                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1082                                              rxsize, 0);
1083                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1084                                              txsize, 0);
1085                 }
1086         }
1087
1088         /* TX INITIALIZATION */
1089         for (i = 0; i < txsize; i++) {
1090                 struct dma_desc *p;
1091                 if (priv->extend_desc)
1092                         p = &((priv->dma_etx + i)->basic);
1093                 else
1094                         p = priv->dma_tx + i;
1095                 p->des2 = 0;
1096                 priv->tx_skbuff_dma[i].buf = 0;
1097                 priv->tx_skbuff_dma[i].map_as_page = false;
1098                 priv->tx_skbuff[i] = NULL;
1099         }
1100
1101         priv->dirty_tx = 0;
1102         priv->cur_tx = 0;
1103         netdev_reset_queue(priv->dev);
1104
1105         stmmac_clear_descriptors(priv);
1106
1107         if (netif_msg_hw(priv))
1108                 stmmac_display_rings(priv);
1109
1110         return 0;
1111 err_init_rx_buffers:
1112         while (--i >= 0)
1113                 stmmac_free_rx_buffers(priv, i);
1114         return ret;
1115 }
1116
1117 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1118 {
1119         int i;
1120
1121         for (i = 0; i < priv->dma_rx_size; i++)
1122                 stmmac_free_rx_buffers(priv, i);
1123 }
1124
1125 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1126 {
1127         int i;
1128
1129         for (i = 0; i < priv->dma_tx_size; i++) {
1130                 struct dma_desc *p;
1131
1132                 if (priv->extend_desc)
1133                         p = &((priv->dma_etx + i)->basic);
1134                 else
1135                         p = priv->dma_tx + i;
1136
1137                 if (priv->tx_skbuff_dma[i].buf) {
1138                         if (priv->tx_skbuff_dma[i].map_as_page)
1139                                 dma_unmap_page(priv->device,
1140                                                priv->tx_skbuff_dma[i].buf,
1141                                                priv->hw->desc->get_tx_len(p),
1142                                                DMA_TO_DEVICE);
1143                         else
1144                                 dma_unmap_single(priv->device,
1145                                                  priv->tx_skbuff_dma[i].buf,
1146                                                  priv->hw->desc->get_tx_len(p),
1147                                                  DMA_TO_DEVICE);
1148                 }
1149
1150                 if (priv->tx_skbuff[i] != NULL) {
1151                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1152                         priv->tx_skbuff[i] = NULL;
1153                         priv->tx_skbuff_dma[i].buf = 0;
1154                         priv->tx_skbuff_dma[i].map_as_page = false;
1155                 }
1156         }
1157 }
1158
1159 /**
1160  * alloc_dma_desc_resources - alloc TX/RX resources.
1161  * @priv: private structure
1162  * Description: according to which descriptor can be used (extend or basic)
1163  * this function allocates the resources for TX and RX paths. In case of
1164  * reception, for example, it pre-allocated the RX socket buffer in order to
1165  * allow zero-copy mechanism.
1166  */
1167 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1168 {
1169         unsigned int txsize = priv->dma_tx_size;
1170         unsigned int rxsize = priv->dma_rx_size;
1171         int ret = -ENOMEM;
1172
1173         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1174                                             GFP_KERNEL);
1175         if (!priv->rx_skbuff_dma)
1176                 return -ENOMEM;
1177
1178         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1179                                         GFP_KERNEL);
1180         if (!priv->rx_skbuff)
1181                 goto err_rx_skbuff;
1182
1183         priv->tx_skbuff_dma = kmalloc_array(txsize,
1184                                             sizeof(*priv->tx_skbuff_dma),
1185                                             GFP_KERNEL);
1186         if (!priv->tx_skbuff_dma)
1187                 goto err_tx_skbuff_dma;
1188
1189         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1190                                         GFP_KERNEL);
1191         if (!priv->tx_skbuff)
1192                 goto err_tx_skbuff;
1193
1194         if (priv->extend_desc) {
1195                 priv->dma_erx = dma_zalloc_coherent(priv->device, rxsize *
1196                                                     sizeof(struct
1197                                                            dma_extended_desc),
1198                                                     &priv->dma_rx_phy,
1199                                                     GFP_KERNEL);
1200                 if (!priv->dma_erx)
1201                         goto err_dma;
1202
1203                 priv->dma_etx = dma_zalloc_coherent(priv->device, txsize *
1204                                                     sizeof(struct
1205                                                            dma_extended_desc),
1206                                                     &priv->dma_tx_phy,
1207                                                     GFP_KERNEL);
1208                 if (!priv->dma_etx) {
1209                         dma_free_coherent(priv->device, priv->dma_rx_size *
1210                                           sizeof(struct dma_extended_desc),
1211                                           priv->dma_erx, priv->dma_rx_phy);
1212                         goto err_dma;
1213                 }
1214         } else {
1215                 priv->dma_rx = dma_zalloc_coherent(priv->device, rxsize *
1216                                                    sizeof(struct dma_desc),
1217                                                    &priv->dma_rx_phy,
1218                                                    GFP_KERNEL);
1219                 if (!priv->dma_rx)
1220                         goto err_dma;
1221
1222                 priv->dma_tx = dma_zalloc_coherent(priv->device, txsize *
1223                                                    sizeof(struct dma_desc),
1224                                                    &priv->dma_tx_phy,
1225                                                    GFP_KERNEL);
1226                 if (!priv->dma_tx) {
1227                         dma_free_coherent(priv->device, priv->dma_rx_size *
1228                                           sizeof(struct dma_desc),
1229                                           priv->dma_rx, priv->dma_rx_phy);
1230                         goto err_dma;
1231                 }
1232         }
1233
1234         return 0;
1235
1236 err_dma:
1237         kfree(priv->tx_skbuff);
1238 err_tx_skbuff:
1239         kfree(priv->tx_skbuff_dma);
1240 err_tx_skbuff_dma:
1241         kfree(priv->rx_skbuff);
1242 err_rx_skbuff:
1243         kfree(priv->rx_skbuff_dma);
1244         return ret;
1245 }
1246
1247 static void free_dma_desc_resources(struct stmmac_priv *priv)
1248 {
1249         /* Release the DMA TX/RX socket buffers */
1250         dma_free_rx_skbufs(priv);
1251         dma_free_tx_skbufs(priv);
1252
1253         /* Free DMA regions of consistent memory previously allocated */
1254         if (!priv->extend_desc) {
1255                 dma_free_coherent(priv->device,
1256                                   priv->dma_tx_size * sizeof(struct dma_desc),
1257                                   priv->dma_tx, priv->dma_tx_phy);
1258                 dma_free_coherent(priv->device,
1259                                   priv->dma_rx_size * sizeof(struct dma_desc),
1260                                   priv->dma_rx, priv->dma_rx_phy);
1261         } else {
1262                 dma_free_coherent(priv->device, priv->dma_tx_size *
1263                                   sizeof(struct dma_extended_desc),
1264                                   priv->dma_etx, priv->dma_tx_phy);
1265                 dma_free_coherent(priv->device, priv->dma_rx_size *
1266                                   sizeof(struct dma_extended_desc),
1267                                   priv->dma_erx, priv->dma_rx_phy);
1268         }
1269         kfree(priv->rx_skbuff_dma);
1270         kfree(priv->rx_skbuff);
1271         kfree(priv->tx_skbuff_dma);
1272         kfree(priv->tx_skbuff);
1273 }
1274
1275 /**
1276  *  stmmac_dma_operation_mode - HW DMA operation mode
1277  *  @priv: driver private structure
1278  *  Description: it is used for configuring the DMA operation mode register in
1279  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1280  */
1281 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1282 {
1283         int rxfifosz = priv->plat->rx_fifo_size;
1284
1285         if (priv->plat->force_thresh_dma_mode)
1286                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1287         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1288                 /*
1289                  * In case of GMAC, SF mode can be enabled
1290                  * to perform the TX COE in HW. This depends on:
1291                  * 1) TX COE if actually supported
1292                  * 2) There is no bugged Jumbo frame support
1293                  *    that needs to not insert csum in the TDES.
1294                  */
1295                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1296                                         rxfifosz);
1297                 priv->xstats.threshold = SF_DMA_MODE;
1298         } else
1299                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1300                                         rxfifosz);
1301 }
1302
1303 /**
1304  * stmmac_tx_clean - to manage the transmission completion
1305  * @priv: driver private structure
1306  * Description: it reclaims the transmit resources after transmission completes.
1307  */
1308 static void stmmac_tx_clean(struct stmmac_priv *priv)
1309 {
1310         unsigned int txsize = priv->dma_tx_size;
1311         unsigned int bytes_compl = 0, pkts_compl = 0;
1312
1313         spin_lock(&priv->tx_lock);
1314
1315         priv->xstats.tx_clean++;
1316
1317         while (priv->dirty_tx != priv->cur_tx) {
1318                 int last;
1319                 unsigned int entry = priv->dirty_tx % txsize;
1320                 struct sk_buff *skb = priv->tx_skbuff[entry];
1321                 struct dma_desc *p;
1322
1323                 if (priv->extend_desc)
1324                         p = (struct dma_desc *)(priv->dma_etx + entry);
1325                 else
1326                         p = priv->dma_tx + entry;
1327
1328                 /* Check if the descriptor is owned by the DMA. */
1329                 if (priv->hw->desc->get_tx_owner(p))
1330                         break;
1331
1332                 /* Verify tx error by looking at the last segment. */
1333                 last = priv->hw->desc->get_tx_ls(p);
1334                 if (likely(last)) {
1335                         int tx_error =
1336                             priv->hw->desc->tx_status(&priv->dev->stats,
1337                                                       &priv->xstats, p,
1338                                                       priv->ioaddr);
1339                         if (likely(tx_error == 0)) {
1340                                 priv->dev->stats.tx_packets++;
1341                                 priv->xstats.tx_pkt_n++;
1342                         } else
1343                                 priv->dev->stats.tx_errors++;
1344
1345                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1346                 }
1347                 if (netif_msg_tx_done(priv))
1348                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1349                                  priv->cur_tx, priv->dirty_tx);
1350
1351                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1352                         if (priv->tx_skbuff_dma[entry].map_as_page)
1353                                 dma_unmap_page(priv->device,
1354                                                priv->tx_skbuff_dma[entry].buf,
1355                                                priv->hw->desc->get_tx_len(p),
1356                                                DMA_TO_DEVICE);
1357                         else
1358                                 dma_unmap_single(priv->device,
1359                                                  priv->tx_skbuff_dma[entry].buf,
1360                                                  priv->hw->desc->get_tx_len(p),
1361                                                  DMA_TO_DEVICE);
1362                         priv->tx_skbuff_dma[entry].buf = 0;
1363                         priv->tx_skbuff_dma[entry].map_as_page = false;
1364                 }
1365                 priv->hw->mode->clean_desc3(priv, p);
1366
1367                 if (likely(skb != NULL)) {
1368                         pkts_compl++;
1369                         bytes_compl += skb->len;
1370                         dev_consume_skb_any(skb);
1371                         priv->tx_skbuff[entry] = NULL;
1372                 }
1373
1374                 priv->hw->desc->release_tx_desc(p, priv->mode);
1375
1376                 priv->dirty_tx++;
1377         }
1378
1379         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1380
1381         if (unlikely(netif_queue_stopped(priv->dev) &&
1382                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1383                 netif_tx_lock(priv->dev);
1384                 if (netif_queue_stopped(priv->dev) &&
1385                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1386                         if (netif_msg_tx_done(priv))
1387                                 pr_debug("%s: restart transmit\n", __func__);
1388                         netif_wake_queue(priv->dev);
1389                 }
1390                 netif_tx_unlock(priv->dev);
1391         }
1392
1393         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1394                 stmmac_enable_eee_mode(priv);
1395                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1396         }
1397         spin_unlock(&priv->tx_lock);
1398 }
1399
1400 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1401 {
1402         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1403 }
1404
1405 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1406 {
1407         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1408 }
1409
1410 /**
1411  * stmmac_tx_err - to manage the tx error
1412  * @priv: driver private structure
1413  * Description: it cleans the descriptors and restarts the transmission
1414  * in case of transmission errors.
1415  */
1416 static void stmmac_tx_err(struct stmmac_priv *priv)
1417 {
1418         int i;
1419         int txsize = priv->dma_tx_size;
1420         netif_stop_queue(priv->dev);
1421
1422         priv->hw->dma->stop_tx(priv->ioaddr);
1423         dma_free_tx_skbufs(priv);
1424         for (i = 0; i < txsize; i++)
1425                 if (priv->extend_desc)
1426                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1427                                                      priv->mode,
1428                                                      (i == txsize - 1));
1429                 else
1430                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1431                                                      priv->mode,
1432                                                      (i == txsize - 1));
1433         priv->dirty_tx = 0;
1434         priv->cur_tx = 0;
1435         netdev_reset_queue(priv->dev);
1436         priv->hw->dma->start_tx(priv->ioaddr);
1437
1438         priv->dev->stats.tx_errors++;
1439         netif_wake_queue(priv->dev);
1440 }
1441
1442 /**
1443  * stmmac_dma_interrupt - DMA ISR
1444  * @priv: driver private structure
1445  * Description: this is the DMA ISR. It is called by the main ISR.
1446  * It calls the dwmac dma routine and schedule poll method in case of some
1447  * work can be done.
1448  */
1449 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1450 {
1451         int status;
1452         int rxfifosz = priv->plat->rx_fifo_size;
1453
1454         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1455         if (likely((status & handle_rx)) || (status & handle_tx)) {
1456                 if (likely(napi_schedule_prep(&priv->napi))) {
1457                         stmmac_disable_dma_irq(priv);
1458                         __napi_schedule(&priv->napi);
1459                 }
1460         }
1461         if (unlikely(status & tx_hard_error_bump_tc)) {
1462                 /* Try to bump up the dma threshold on this failure */
1463                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1464                     (tc <= 256)) {
1465                         tc += 64;
1466                         if (priv->plat->force_thresh_dma_mode)
1467                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1468                                                         rxfifosz);
1469                         else
1470                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1471                                                         SF_DMA_MODE, rxfifosz);
1472                         priv->xstats.threshold = tc;
1473                 }
1474         } else if (unlikely(status == tx_hard_error))
1475                 stmmac_tx_err(priv);
1476 }
1477
1478 /**
1479  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1480  * @priv: driver private structure
1481  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1482  */
1483 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1484 {
1485         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1486             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1487
1488         dwmac_mmc_intr_all_mask(priv->ioaddr);
1489
1490         if (priv->dma_cap.rmon) {
1491                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1492                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1493         } else
1494                 pr_info(" No MAC Management Counters available\n");
1495 }
1496
1497 /**
1498  * stmmac_get_synopsys_id - return the SYINID.
1499  * @priv: driver private structure
1500  * Description: this simple function is to decode and return the SYINID
1501  * starting from the HW core register.
1502  */
1503 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1504 {
1505         u32 hwid = priv->hw->synopsys_uid;
1506
1507         /* Check Synopsys Id (not available on old chips) */
1508         if (likely(hwid)) {
1509                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1510                 u32 synid = (hwid & 0x000000ff);
1511
1512                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1513                         uid, synid);
1514
1515                 return synid;
1516         }
1517         return 0;
1518 }
1519
1520 /**
1521  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1522  * @priv: driver private structure
1523  * Description: select the Enhanced/Alternate or Normal descriptors.
1524  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1525  * supported by the HW capability register.
1526  */
1527 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1528 {
1529         if (priv->plat->enh_desc) {
1530                 pr_info(" Enhanced/Alternate descriptors\n");
1531
1532                 /* GMAC older than 3.50 has no extended descriptors */
1533                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1534                         pr_info("\tEnabled extended descriptors\n");
1535                         priv->extend_desc = 1;
1536                 } else
1537                         pr_warn("Extended descriptors not supported\n");
1538
1539                 priv->hw->desc = &enh_desc_ops;
1540         } else {
1541                 pr_info(" Normal descriptors\n");
1542                 priv->hw->desc = &ndesc_ops;
1543         }
1544 }
1545
1546 /**
1547  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1548  * @priv: driver private structure
1549  * Description:
1550  *  new GMAC chip generations have a new register to indicate the
1551  *  presence of the optional feature/functions.
1552  *  This can be also used to override the value passed through the
1553  *  platform and necessary for old MAC10/100 and GMAC chips.
1554  */
1555 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1556 {
1557         u32 hw_cap = 0;
1558
1559         if (priv->hw->dma->get_hw_feature) {
1560                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1561
1562                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1563                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1564                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1565                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1566                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1567                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1568                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1569                 priv->dma_cap.pmt_remote_wake_up =
1570                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1571                 priv->dma_cap.pmt_magic_frame =
1572                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1573                 /* MMC */
1574                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1575                 /* IEEE 1588-2002 */
1576                 priv->dma_cap.time_stamp =
1577                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1578                 /* IEEE 1588-2008 */
1579                 priv->dma_cap.atime_stamp =
1580                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1581                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1582                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1583                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1584                 /* TX and RX csum */
1585                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1586                 priv->dma_cap.rx_coe_type1 =
1587                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1588                 priv->dma_cap.rx_coe_type2 =
1589                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1590                 priv->dma_cap.rxfifo_over_2048 =
1591                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1592                 /* TX and RX number of channels */
1593                 priv->dma_cap.number_rx_channel =
1594                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1595                 priv->dma_cap.number_tx_channel =
1596                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1597                 /* Alternate (enhanced) DESC mode */
1598                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1599         }
1600
1601         return hw_cap;
1602 }
1603
1604 /**
1605  * stmmac_check_ether_addr - check if the MAC addr is valid
1606  * @priv: driver private structure
1607  * Description:
1608  * it is to verify if the MAC address is valid, in case of failures it
1609  * generates a random MAC address
1610  */
1611 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1612 {
1613         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1614                 priv->hw->mac->get_umac_addr(priv->hw,
1615                                              priv->dev->dev_addr, 0);
1616                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1617                         eth_hw_addr_random(priv->dev);
1618                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1619                         priv->dev->dev_addr);
1620         }
1621 }
1622
1623 /**
1624  * stmmac_init_dma_engine - DMA init.
1625  * @priv: driver private structure
1626  * Description:
1627  * It inits the DMA invoking the specific MAC/GMAC callback.
1628  * Some DMA parameters can be passed from the platform;
1629  * in case of these are not passed a default is kept for the MAC or GMAC.
1630  */
1631 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1632 {
1633         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1634         int mixed_burst = 0;
1635         int atds = 0;
1636
1637         if (priv->plat->dma_cfg) {
1638                 pbl = priv->plat->dma_cfg->pbl;
1639                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1640                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1641                 burst_len = priv->plat->dma_cfg->burst_len;
1642         }
1643
1644         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1645                 atds = 1;
1646
1647         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1648                                    burst_len, priv->dma_tx_phy,
1649                                    priv->dma_rx_phy, atds);
1650 }
1651
1652 /**
1653  * stmmac_tx_timer - mitigation sw timer for tx.
1654  * @data: data pointer
1655  * Description:
1656  * This is the timer handler to directly invoke the stmmac_tx_clean.
1657  */
1658 static void stmmac_tx_timer(unsigned long data)
1659 {
1660         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1661
1662         stmmac_tx_clean(priv);
1663 }
1664
1665 /**
1666  * stmmac_init_tx_coalesce - init tx mitigation options.
1667  * @priv: driver private structure
1668  * Description:
1669  * This inits the transmit coalesce parameters: i.e. timer rate,
1670  * timer handler and default threshold used for enabling the
1671  * interrupt on completion bit.
1672  */
1673 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1674 {
1675         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1676         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1677         init_timer(&priv->txtimer);
1678         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1679         priv->txtimer.data = (unsigned long)priv;
1680         priv->txtimer.function = stmmac_tx_timer;
1681         add_timer(&priv->txtimer);
1682 }
1683
1684 /**
1685  * stmmac_hw_setup - setup mac in a usable state.
1686  *  @dev : pointer to the device structure.
1687  *  Description:
1688  *  this is the main function to setup the HW in a usable state because the
1689  *  dma engine is reset, the core registers are configured (e.g. AXI,
1690  *  Checksum features, timers). The DMA is ready to start receiving and
1691  *  transmitting.
1692  *  Return value:
1693  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1694  *  file on failure.
1695  */
1696 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1697 {
1698         struct stmmac_priv *priv = netdev_priv(dev);
1699         int ret;
1700
1701         /* DMA initialization and SW reset */
1702         ret = stmmac_init_dma_engine(priv);
1703         if (ret < 0) {
1704                 pr_err("%s: DMA engine initialization failed\n", __func__);
1705                 return ret;
1706         }
1707
1708         /* Copy the MAC addr into the HW  */
1709         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1710
1711         /* If required, perform hw setup of the bus. */
1712         if (priv->plat->bus_setup)
1713                 priv->plat->bus_setup(priv->ioaddr);
1714
1715         /* Initialize the MAC Core */
1716         priv->hw->mac->core_init(priv->hw, dev->mtu);
1717
1718         ret = priv->hw->mac->rx_ipc(priv->hw);
1719         if (!ret) {
1720                 pr_warn(" RX IPC Checksum Offload disabled\n");
1721                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1722                 priv->hw->rx_csum = 0;
1723         }
1724
1725         /* Enable the MAC Rx/Tx */
1726         stmmac_set_mac(priv->ioaddr, true);
1727
1728         /* Set the HW DMA mode and the COE */
1729         stmmac_dma_operation_mode(priv);
1730
1731         stmmac_mmc_setup(priv);
1732
1733         if (init_ptp) {
1734                 ret = stmmac_init_ptp(priv);
1735                 if (ret && ret != -EOPNOTSUPP)
1736                         pr_warn("%s: failed PTP initialisation\n", __func__);
1737         }
1738
1739 #ifdef CONFIG_DEBUG_FS
1740         ret = stmmac_init_fs(dev);
1741         if (ret < 0)
1742                 pr_warn("%s: failed debugFS registration\n", __func__);
1743 #endif
1744         /* Start the ball rolling... */
1745         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1746         priv->hw->dma->start_tx(priv->ioaddr);
1747         priv->hw->dma->start_rx(priv->ioaddr);
1748
1749         /* Dump DMA/MAC registers */
1750         if (netif_msg_hw(priv)) {
1751                 priv->hw->mac->dump_regs(priv->hw);
1752                 priv->hw->dma->dump_regs(priv->ioaddr);
1753         }
1754         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1755
1756         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1757                 priv->rx_riwt = MAX_DMA_RIWT;
1758                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1759         }
1760
1761         if (priv->pcs && priv->hw->mac->ctrl_ane)
1762                 priv->hw->mac->ctrl_ane(priv->hw, 0);
1763
1764         return 0;
1765 }
1766
1767 /**
1768  *  stmmac_open - open entry point of the driver
1769  *  @dev : pointer to the device structure.
1770  *  Description:
1771  *  This function is the open entry point of the driver.
1772  *  Return value:
1773  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1774  *  file on failure.
1775  */
1776 static int stmmac_open(struct net_device *dev)
1777 {
1778         struct stmmac_priv *priv = netdev_priv(dev);
1779         int ret;
1780
1781         stmmac_check_ether_addr(priv);
1782
1783         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1784             priv->pcs != STMMAC_PCS_RTBI) {
1785                 ret = stmmac_init_phy(dev);
1786                 if (ret) {
1787                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1788                                __func__, ret);
1789                         return ret;
1790                 }
1791         }
1792
1793         /* Extra statistics */
1794         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1795         priv->xstats.threshold = tc;
1796
1797         /* Create and initialize the TX/RX descriptors chains. */
1798         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1799         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1800         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1801
1802         ret = alloc_dma_desc_resources(priv);
1803         if (ret < 0) {
1804                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1805                 goto dma_desc_error;
1806         }
1807
1808         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1809         if (ret < 0) {
1810                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1811                 goto init_error;
1812         }
1813
1814         ret = stmmac_hw_setup(dev, true);
1815         if (ret < 0) {
1816                 pr_err("%s: Hw setup failed\n", __func__);
1817                 goto init_error;
1818         }
1819
1820         stmmac_init_tx_coalesce(priv);
1821
1822         if (priv->phydev)
1823                 phy_start(priv->phydev);
1824
1825         /* Request the IRQ lines */
1826         ret = request_irq(dev->irq, stmmac_interrupt,
1827                           IRQF_SHARED, dev->name, dev);
1828         if (unlikely(ret < 0)) {
1829                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1830                        __func__, dev->irq, ret);
1831                 goto init_error;
1832         }
1833
1834         /* Request the Wake IRQ in case of another line is used for WoL */
1835         if (priv->wol_irq != dev->irq) {
1836                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1837                                   IRQF_SHARED, dev->name, dev);
1838                 if (unlikely(ret < 0)) {
1839                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1840                                __func__, priv->wol_irq, ret);
1841                         goto wolirq_error;
1842                 }
1843         }
1844
1845         /* Request the IRQ lines */
1846         if (priv->lpi_irq > 0) {
1847                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1848                                   dev->name, dev);
1849                 if (unlikely(ret < 0)) {
1850                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1851                                __func__, priv->lpi_irq, ret);
1852                         goto lpiirq_error;
1853                 }
1854         }
1855
1856         napi_enable(&priv->napi);
1857         netif_start_queue(dev);
1858
1859         return 0;
1860
1861 lpiirq_error:
1862         if (priv->wol_irq != dev->irq)
1863                 free_irq(priv->wol_irq, dev);
1864 wolirq_error:
1865         free_irq(dev->irq, dev);
1866
1867 init_error:
1868         free_dma_desc_resources(priv);
1869 dma_desc_error:
1870         if (priv->phydev)
1871                 phy_disconnect(priv->phydev);
1872
1873         return ret;
1874 }
1875
1876 /**
1877  *  stmmac_release - close entry point of the driver
1878  *  @dev : device pointer.
1879  *  Description:
1880  *  This is the stop entry point of the driver.
1881  */
1882 static int stmmac_release(struct net_device *dev)
1883 {
1884         struct stmmac_priv *priv = netdev_priv(dev);
1885
1886         if (priv->eee_enabled)
1887                 del_timer_sync(&priv->eee_ctrl_timer);
1888
1889         /* Stop and disconnect the PHY */
1890         if (priv->phydev) {
1891                 phy_stop(priv->phydev);
1892                 phy_disconnect(priv->phydev);
1893                 priv->phydev = NULL;
1894         }
1895
1896         netif_stop_queue(dev);
1897
1898         napi_disable(&priv->napi);
1899
1900         del_timer_sync(&priv->txtimer);
1901
1902         /* Free the IRQ lines */
1903         free_irq(dev->irq, dev);
1904         if (priv->wol_irq != dev->irq)
1905                 free_irq(priv->wol_irq, dev);
1906         if (priv->lpi_irq > 0)
1907                 free_irq(priv->lpi_irq, dev);
1908
1909         /* Stop TX/RX DMA and clear the descriptors */
1910         priv->hw->dma->stop_tx(priv->ioaddr);
1911         priv->hw->dma->stop_rx(priv->ioaddr);
1912
1913         /* Release and free the Rx/Tx resources */
1914         free_dma_desc_resources(priv);
1915
1916         /* Disable the MAC Rx/Tx */
1917         stmmac_set_mac(priv->ioaddr, false);
1918
1919         netif_carrier_off(dev);
1920
1921 #ifdef CONFIG_DEBUG_FS
1922         stmmac_exit_fs(dev);
1923 #endif
1924
1925         stmmac_release_ptp(priv);
1926
1927         return 0;
1928 }
1929
1930 /**
1931  *  stmmac_xmit - Tx entry point of the driver
1932  *  @skb : the socket buffer
1933  *  @dev : device pointer
1934  *  Description : this is the tx entry point of the driver.
1935  *  It programs the chain or the ring and supports oversized frames
1936  *  and SG feature.
1937  */
1938 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1939 {
1940         struct stmmac_priv *priv = netdev_priv(dev);
1941         unsigned int txsize = priv->dma_tx_size;
1942         unsigned int entry;
1943         int i, csum_insertion = 0, is_jumbo = 0;
1944         int nfrags = skb_shinfo(skb)->nr_frags;
1945         struct dma_desc *desc, *first;
1946         unsigned int nopaged_len = skb_headlen(skb);
1947         unsigned int enh_desc = priv->plat->enh_desc;
1948
1949         spin_lock(&priv->tx_lock);
1950
1951         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1952                 spin_unlock(&priv->tx_lock);
1953                 if (!netif_queue_stopped(dev)) {
1954                         netif_stop_queue(dev);
1955                         /* This is a hard error, log it. */
1956                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1957                 }
1958                 return NETDEV_TX_BUSY;
1959         }
1960
1961         if (priv->tx_path_in_lpi_mode)
1962                 stmmac_disable_eee_mode(priv);
1963
1964         entry = priv->cur_tx % txsize;
1965
1966         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1967
1968         if (priv->extend_desc)
1969                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1970         else
1971                 desc = priv->dma_tx + entry;
1972
1973         first = desc;
1974
1975         /* To program the descriptors according to the size of the frame */
1976         if (enh_desc)
1977                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1978
1979         if (likely(!is_jumbo)) {
1980                 desc->des2 = dma_map_single(priv->device, skb->data,
1981                                             nopaged_len, DMA_TO_DEVICE);
1982                 if (dma_mapping_error(priv->device, desc->des2))
1983                         goto dma_map_err;
1984                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1985                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1986                                                 csum_insertion, priv->mode);
1987         } else {
1988                 desc = first;
1989                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1990                 if (unlikely(entry < 0))
1991                         goto dma_map_err;
1992         }
1993
1994         for (i = 0; i < nfrags; i++) {
1995                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1996                 int len = skb_frag_size(frag);
1997
1998                 priv->tx_skbuff[entry] = NULL;
1999                 entry = (++priv->cur_tx) % txsize;
2000                 if (priv->extend_desc)
2001                         desc = (struct dma_desc *)(priv->dma_etx + entry);
2002                 else
2003                         desc = priv->dma_tx + entry;
2004
2005                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
2006                                               DMA_TO_DEVICE);
2007                 if (dma_mapping_error(priv->device, desc->des2))
2008                         goto dma_map_err; /* should reuse desc w/o issues */
2009
2010                 priv->tx_skbuff_dma[entry].buf = desc->des2;
2011                 priv->tx_skbuff_dma[entry].map_as_page = true;
2012                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2013                                                 priv->mode);
2014                 wmb();
2015                 priv->hw->desc->set_tx_owner(desc);
2016                 wmb();
2017         }
2018
2019         priv->tx_skbuff[entry] = skb;
2020
2021         /* Finalize the latest segment. */
2022         priv->hw->desc->close_tx_desc(desc);
2023
2024         wmb();
2025         /* According to the coalesce parameter the IC bit for the latest
2026          * segment could be reset and the timer re-started to invoke the
2027          * stmmac_tx function. This approach takes care about the fragments.
2028          */
2029         priv->tx_count_frames += nfrags + 1;
2030         if (priv->tx_coal_frames > priv->tx_count_frames) {
2031                 priv->hw->desc->clear_tx_ic(desc);
2032                 priv->xstats.tx_reset_ic_bit++;
2033                 mod_timer(&priv->txtimer,
2034                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2035         } else
2036                 priv->tx_count_frames = 0;
2037
2038         /* To avoid raise condition */
2039         priv->hw->desc->set_tx_owner(first);
2040         wmb();
2041
2042         priv->cur_tx++;
2043
2044         if (netif_msg_pktdata(priv)) {
2045                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2046                         __func__, (priv->cur_tx % txsize),
2047                         (priv->dirty_tx % txsize), entry, first, nfrags);
2048
2049                 if (priv->extend_desc)
2050                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
2051                 else
2052                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
2053
2054                 pr_debug(">>> frame to be transmitted: ");
2055                 print_pkt(skb->data, skb->len);
2056         }
2057         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2058                 if (netif_msg_hw(priv))
2059                         pr_debug("%s: stop transmitted packets\n", __func__);
2060                 netif_stop_queue(dev);
2061         }
2062
2063         dev->stats.tx_bytes += skb->len;
2064
2065         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2066                      priv->hwts_tx_en)) {
2067                 /* declare that device is doing timestamping */
2068                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2069                 priv->hw->desc->enable_tx_timestamp(first);
2070         }
2071
2072         if (!priv->hwts_tx_en)
2073                 skb_tx_timestamp(skb);
2074
2075         netdev_sent_queue(dev, skb->len);
2076         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2077
2078         spin_unlock(&priv->tx_lock);
2079         return NETDEV_TX_OK;
2080
2081 dma_map_err:
2082         spin_unlock(&priv->tx_lock);
2083         dev_err(priv->device, "Tx dma map failed\n");
2084         dev_kfree_skb(skb);
2085         priv->dev->stats.tx_dropped++;
2086         return NETDEV_TX_OK;
2087 }
2088
2089 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2090 {
2091         struct ethhdr *ehdr;
2092         u16 vlanid;
2093
2094         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2095             NETIF_F_HW_VLAN_CTAG_RX &&
2096             !__vlan_get_tag(skb, &vlanid)) {
2097                 /* pop the vlan tag */
2098                 ehdr = (struct ethhdr *)skb->data;
2099                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2100                 skb_pull(skb, VLAN_HLEN);
2101                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2102         }
2103 }
2104
2105
2106 /**
2107  * stmmac_rx_refill - refill used skb preallocated buffers
2108  * @priv: driver private structure
2109  * Description : this is to reallocate the skb for the reception process
2110  * that is based on zero-copy.
2111  */
2112 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2113 {
2114         unsigned int rxsize = priv->dma_rx_size;
2115         int bfsize = priv->dma_buf_sz;
2116
2117         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2118                 unsigned int entry = priv->dirty_rx % rxsize;
2119                 struct dma_desc *p;
2120
2121                 if (priv->extend_desc)
2122                         p = (struct dma_desc *)(priv->dma_erx + entry);
2123                 else
2124                         p = priv->dma_rx + entry;
2125
2126                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2127                         struct sk_buff *skb;
2128
2129                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2130
2131                         if (unlikely(skb == NULL))
2132                                 break;
2133
2134                         priv->rx_skbuff[entry] = skb;
2135                         priv->rx_skbuff_dma[entry] =
2136                             dma_map_single(priv->device, skb->data, bfsize,
2137                                            DMA_FROM_DEVICE);
2138                         if (dma_mapping_error(priv->device,
2139                                               priv->rx_skbuff_dma[entry])) {
2140                                 dev_err(priv->device, "Rx dma map failed\n");
2141                                 dev_kfree_skb(skb);
2142                                 break;
2143                         }
2144                         p->des2 = priv->rx_skbuff_dma[entry];
2145
2146                         priv->hw->mode->refill_desc3(priv, p);
2147
2148                         if (netif_msg_rx_status(priv))
2149                                 pr_debug("\trefill entry #%d\n", entry);
2150                 }
2151                 wmb();
2152                 priv->hw->desc->set_rx_owner(p);
2153                 wmb();
2154         }
2155 }
2156
2157 /**
2158  * stmmac_rx - manage the receive process
2159  * @priv: driver private structure
2160  * @limit: napi bugget.
2161  * Description :  this the function called by the napi poll method.
2162  * It gets all the frames inside the ring.
2163  */
2164 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2165 {
2166         unsigned int rxsize = priv->dma_rx_size;
2167         unsigned int entry = priv->cur_rx % rxsize;
2168         unsigned int next_entry;
2169         unsigned int count = 0;
2170         int coe = priv->hw->rx_csum;
2171
2172         if (netif_msg_rx_status(priv)) {
2173                 pr_debug("%s: descriptor ring:\n", __func__);
2174                 if (priv->extend_desc)
2175                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2176                 else
2177                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2178         }
2179         while (count < limit) {
2180                 int status;
2181                 struct dma_desc *p;
2182
2183                 if (priv->extend_desc)
2184                         p = (struct dma_desc *)(priv->dma_erx + entry);
2185                 else
2186                         p = priv->dma_rx + entry;
2187
2188                 if (priv->hw->desc->get_rx_owner(p))
2189                         break;
2190
2191                 count++;
2192
2193                 next_entry = (++priv->cur_rx) % rxsize;
2194                 if (priv->extend_desc)
2195                         prefetch(priv->dma_erx + next_entry);
2196                 else
2197                         prefetch(priv->dma_rx + next_entry);
2198
2199                 /* read the status of the incoming frame */
2200                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2201                                                    &priv->xstats, p);
2202                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2203                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2204                                                            &priv->xstats,
2205                                                            priv->dma_erx +
2206                                                            entry);
2207                 if (unlikely(status == discard_frame)) {
2208                         priv->dev->stats.rx_errors++;
2209                         if (priv->hwts_rx_en && !priv->extend_desc) {
2210                                 /* DESC2 & DESC3 will be overwitten by device
2211                                  * with timestamp value, hence reinitialize
2212                                  * them in stmmac_rx_refill() function so that
2213                                  * device can reuse it.
2214                                  */
2215                                 priv->rx_skbuff[entry] = NULL;
2216                                 dma_unmap_single(priv->device,
2217                                                  priv->rx_skbuff_dma[entry],
2218                                                  priv->dma_buf_sz,
2219                                                  DMA_FROM_DEVICE);
2220                         }
2221                 } else {
2222                         struct sk_buff *skb;
2223                         int frame_len;
2224
2225                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2226
2227                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2228                          * Type frames (LLC/LLC-SNAP)
2229                          */
2230                         if (unlikely(status != llc_snap))
2231                                 frame_len -= ETH_FCS_LEN;
2232
2233                         if (netif_msg_rx_status(priv)) {
2234                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2235                                          p, entry, p->des2);
2236                                 if (frame_len > ETH_FRAME_LEN)
2237                                         pr_debug("\tframe size %d, COE: %d\n",
2238                                                  frame_len, status);
2239                         }
2240                         skb = priv->rx_skbuff[entry];
2241                         if (unlikely(!skb)) {
2242                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2243                                        priv->dev->name);
2244                                 priv->dev->stats.rx_dropped++;
2245                                 break;
2246                         }
2247                         prefetch(skb->data - NET_IP_ALIGN);
2248                         priv->rx_skbuff[entry] = NULL;
2249
2250                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2251
2252                         skb_put(skb, frame_len);
2253                         dma_unmap_single(priv->device,
2254                                          priv->rx_skbuff_dma[entry],
2255                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2256
2257                         if (netif_msg_pktdata(priv)) {
2258                                 pr_debug("frame received (%dbytes)", frame_len);
2259                                 print_pkt(skb->data, frame_len);
2260                         }
2261
2262                         stmmac_rx_vlan(priv->dev, skb);
2263
2264                         skb->protocol = eth_type_trans(skb, priv->dev);
2265
2266                         if (unlikely(!coe))
2267                                 skb_checksum_none_assert(skb);
2268                         else
2269                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2270
2271                         napi_gro_receive(&priv->napi, skb);
2272
2273                         priv->dev->stats.rx_packets++;
2274                         priv->dev->stats.rx_bytes += frame_len;
2275                 }
2276                 entry = next_entry;
2277         }
2278
2279         stmmac_rx_refill(priv);
2280
2281         priv->xstats.rx_pkt_n += count;
2282
2283         return count;
2284 }
2285
2286 /**
2287  *  stmmac_poll - stmmac poll method (NAPI)
2288  *  @napi : pointer to the napi structure.
2289  *  @budget : maximum number of packets that the current CPU can receive from
2290  *            all interfaces.
2291  *  Description :
2292  *  To look at the incoming frames and clear the tx resources.
2293  */
2294 static int stmmac_poll(struct napi_struct *napi, int budget)
2295 {
2296         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2297         int work_done = 0;
2298
2299         priv->xstats.napi_poll++;
2300         stmmac_tx_clean(priv);
2301
2302         work_done = stmmac_rx(priv, budget);
2303         if (work_done < budget) {
2304                 napi_complete(napi);
2305                 stmmac_enable_dma_irq(priv);
2306         }
2307         return work_done;
2308 }
2309
2310 /**
2311  *  stmmac_tx_timeout
2312  *  @dev : Pointer to net device structure
2313  *  Description: this function is called when a packet transmission fails to
2314  *   complete within a reasonable time. The driver will mark the error in the
2315  *   netdev structure and arrange for the device to be reset to a sane state
2316  *   in order to transmit a new packet.
2317  */
2318 static void stmmac_tx_timeout(struct net_device *dev)
2319 {
2320         struct stmmac_priv *priv = netdev_priv(dev);
2321
2322         /* Clear Tx resources and restart transmitting again */
2323         stmmac_tx_err(priv);
2324 }
2325
2326 /**
2327  *  stmmac_set_rx_mode - entry point for multicast addressing
2328  *  @dev : pointer to the device structure
2329  *  Description:
2330  *  This function is a driver entry point which gets called by the kernel
2331  *  whenever multicast addresses must be enabled/disabled.
2332  *  Return value:
2333  *  void.
2334  */
2335 static void stmmac_set_rx_mode(struct net_device *dev)
2336 {
2337         struct stmmac_priv *priv = netdev_priv(dev);
2338
2339         priv->hw->mac->set_filter(priv->hw, dev);
2340 }
2341
2342 /**
2343  *  stmmac_change_mtu - entry point to change MTU size for the device.
2344  *  @dev : device pointer.
2345  *  @new_mtu : the new MTU size for the device.
2346  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2347  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2348  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2349  *  Return value:
2350  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2351  *  file on failure.
2352  */
2353 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2354 {
2355         struct stmmac_priv *priv = netdev_priv(dev);
2356         int max_mtu;
2357
2358         if (netif_running(dev)) {
2359                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2360                 return -EBUSY;
2361         }
2362
2363         if (priv->plat->enh_desc)
2364                 max_mtu = JUMBO_LEN;
2365         else
2366                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2367
2368         if (priv->plat->maxmtu < max_mtu)
2369                 max_mtu = priv->plat->maxmtu;
2370
2371         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2372                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2373                 return -EINVAL;
2374         }
2375
2376         dev->mtu = new_mtu;
2377         netdev_update_features(dev);
2378
2379         return 0;
2380 }
2381
2382 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2383                                              netdev_features_t features)
2384 {
2385         struct stmmac_priv *priv = netdev_priv(dev);
2386
2387         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2388                 features &= ~NETIF_F_RXCSUM;
2389
2390         if (!priv->plat->tx_coe)
2391                 features &= ~NETIF_F_ALL_CSUM;
2392
2393         /* Some GMAC devices have a bugged Jumbo frame support that
2394          * needs to have the Tx COE disabled for oversized frames
2395          * (due to limited buffer sizes). In this case we disable
2396          * the TX csum insertionin the TDES and not use SF.
2397          */
2398         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2399                 features &= ~NETIF_F_ALL_CSUM;
2400
2401         return features;
2402 }
2403
2404 static int stmmac_set_features(struct net_device *netdev,
2405                                netdev_features_t features)
2406 {
2407         struct stmmac_priv *priv = netdev_priv(netdev);
2408
2409         /* Keep the COE Type in case of csum is supporting */
2410         if (features & NETIF_F_RXCSUM)
2411                 priv->hw->rx_csum = priv->plat->rx_coe;
2412         else
2413                 priv->hw->rx_csum = 0;
2414         /* No check needed because rx_coe has been set before and it will be
2415          * fixed in case of issue.
2416          */
2417         priv->hw->mac->rx_ipc(priv->hw);
2418
2419         return 0;
2420 }
2421
2422 /**
2423  *  stmmac_interrupt - main ISR
2424  *  @irq: interrupt number.
2425  *  @dev_id: to pass the net device pointer.
2426  *  Description: this is the main driver interrupt service routine.
2427  *  It can call:
2428  *  o DMA service routine (to manage incoming frame reception and transmission
2429  *    status)
2430  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2431  *    interrupts.
2432  */
2433 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2434 {
2435         struct net_device *dev = (struct net_device *)dev_id;
2436         struct stmmac_priv *priv = netdev_priv(dev);
2437
2438         if (priv->irq_wake)
2439                 pm_wakeup_event(priv->device, 0);
2440
2441         if (unlikely(!dev)) {
2442                 pr_err("%s: invalid dev pointer\n", __func__);
2443                 return IRQ_NONE;
2444         }
2445
2446         /* To handle GMAC own interrupts */
2447         if (priv->plat->has_gmac) {
2448                 int status = priv->hw->mac->host_irq_status(priv->hw,
2449                                                             &priv->xstats);
2450                 if (unlikely(status)) {
2451                         /* For LPI we need to save the tx status */
2452                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2453                                 priv->tx_path_in_lpi_mode = true;
2454                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2455                                 priv->tx_path_in_lpi_mode = false;
2456                 }
2457         }
2458
2459         /* To handle DMA interrupts */
2460         stmmac_dma_interrupt(priv);
2461
2462         return IRQ_HANDLED;
2463 }
2464
2465 #ifdef CONFIG_NET_POLL_CONTROLLER
2466 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2467  * to allow network I/O with interrupts disabled.
2468  */
2469 static void stmmac_poll_controller(struct net_device *dev)
2470 {
2471         disable_irq(dev->irq);
2472         stmmac_interrupt(dev->irq, dev);
2473         enable_irq(dev->irq);
2474 }
2475 #endif
2476
2477 /**
2478  *  stmmac_ioctl - Entry point for the Ioctl
2479  *  @dev: Device pointer.
2480  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2481  *  a proprietary structure used to pass information to the driver.
2482  *  @cmd: IOCTL command
2483  *  Description:
2484  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2485  */
2486 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2487 {
2488         struct stmmac_priv *priv = netdev_priv(dev);
2489         int ret = -EOPNOTSUPP;
2490
2491         if (!netif_running(dev))
2492                 return -EINVAL;
2493
2494         switch (cmd) {
2495         case SIOCGMIIPHY:
2496         case SIOCGMIIREG:
2497         case SIOCSMIIREG:
2498                 if (!priv->phydev)
2499                         return -EINVAL;
2500                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2501                 break;
2502         case SIOCSHWTSTAMP:
2503                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2504                 break;
2505         default:
2506                 break;
2507         }
2508
2509         return ret;
2510 }
2511
2512 #ifdef CONFIG_DEBUG_FS
2513 static struct dentry *stmmac_fs_dir;
2514
2515 static void sysfs_display_ring(void *head, int size, int extend_desc,
2516                                struct seq_file *seq)
2517 {
2518         int i;
2519         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2520         struct dma_desc *p = (struct dma_desc *)head;
2521
2522         for (i = 0; i < size; i++) {
2523                 u64 x;
2524                 if (extend_desc) {
2525                         x = *(u64 *) ep;
2526                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2527                                    i, (unsigned int)virt_to_phys(ep),
2528                                    (unsigned int)x, (unsigned int)(x >> 32),
2529                                    ep->basic.des2, ep->basic.des3);
2530                         ep++;
2531                 } else {
2532                         x = *(u64 *) p;
2533                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2534                                    i, (unsigned int)virt_to_phys(ep),
2535                                    (unsigned int)x, (unsigned int)(x >> 32),
2536                                    p->des2, p->des3);
2537                         p++;
2538                 }
2539                 seq_printf(seq, "\n");
2540         }
2541 }
2542
2543 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2544 {
2545         struct net_device *dev = seq->private;
2546         struct stmmac_priv *priv = netdev_priv(dev);
2547         unsigned int txsize = priv->dma_tx_size;
2548         unsigned int rxsize = priv->dma_rx_size;
2549
2550         if (priv->extend_desc) {
2551                 seq_printf(seq, "Extended RX descriptor ring:\n");
2552                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2553                 seq_printf(seq, "Extended TX descriptor ring:\n");
2554                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2555         } else {
2556                 seq_printf(seq, "RX descriptor ring:\n");
2557                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2558                 seq_printf(seq, "TX descriptor ring:\n");
2559                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2560         }
2561
2562         return 0;
2563 }
2564
2565 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2566 {
2567         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2568 }
2569
2570 static const struct file_operations stmmac_rings_status_fops = {
2571         .owner = THIS_MODULE,
2572         .open = stmmac_sysfs_ring_open,
2573         .read = seq_read,
2574         .llseek = seq_lseek,
2575         .release = single_release,
2576 };
2577
2578 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2579 {
2580         struct net_device *dev = seq->private;
2581         struct stmmac_priv *priv = netdev_priv(dev);
2582
2583         if (!priv->hw_cap_support) {
2584                 seq_printf(seq, "DMA HW features not supported\n");
2585                 return 0;
2586         }
2587
2588         seq_printf(seq, "==============================\n");
2589         seq_printf(seq, "\tDMA HW features\n");
2590         seq_printf(seq, "==============================\n");
2591
2592         seq_printf(seq, "\t10/100 Mbps %s\n",
2593                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2594         seq_printf(seq, "\t1000 Mbps %s\n",
2595                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2596         seq_printf(seq, "\tHalf duple %s\n",
2597                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2598         seq_printf(seq, "\tHash Filter: %s\n",
2599                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2600         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2601                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2602         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2603                    (priv->dma_cap.pcs) ? "Y" : "N");
2604         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2605                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2606         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2607                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2608         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2609                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2610         seq_printf(seq, "\tRMON module: %s\n",
2611                    (priv->dma_cap.rmon) ? "Y" : "N");
2612         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2613                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2614         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2615                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2616         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2617                    (priv->dma_cap.eee) ? "Y" : "N");
2618         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2619         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2620                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2621         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2622                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2623         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2624                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2625         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2626                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2627         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2628                    priv->dma_cap.number_rx_channel);
2629         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2630                    priv->dma_cap.number_tx_channel);
2631         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2632                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2633
2634         return 0;
2635 }
2636
2637 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2638 {
2639         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2640 }
2641
2642 static const struct file_operations stmmac_dma_cap_fops = {
2643         .owner = THIS_MODULE,
2644         .open = stmmac_sysfs_dma_cap_open,
2645         .read = seq_read,
2646         .llseek = seq_lseek,
2647         .release = single_release,
2648 };
2649
2650 static int stmmac_init_fs(struct net_device *dev)
2651 {
2652         struct stmmac_priv *priv = netdev_priv(dev);
2653
2654         /* Create per netdev entries */
2655         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
2656
2657         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
2658                 pr_err("ERROR %s/%s, debugfs create directory failed\n",
2659                        STMMAC_RESOURCE_NAME, dev->name);
2660
2661                 return -ENOMEM;
2662         }
2663
2664         /* Entry to report DMA RX/TX rings */
2665         priv->dbgfs_rings_status =
2666                 debugfs_create_file("descriptors_status", S_IRUGO,
2667                                     priv->dbgfs_dir, dev,
2668                                     &stmmac_rings_status_fops);
2669
2670         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
2671                 pr_info("ERROR creating stmmac ring debugfs file\n");
2672                 debugfs_remove_recursive(priv->dbgfs_dir);
2673
2674                 return -ENOMEM;
2675         }
2676
2677         /* Entry to report the DMA HW features */
2678         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
2679                                             priv->dbgfs_dir,
2680                                             dev, &stmmac_dma_cap_fops);
2681
2682         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
2683                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2684                 debugfs_remove_recursive(priv->dbgfs_dir);
2685
2686                 return -ENOMEM;
2687         }
2688
2689         return 0;
2690 }
2691
2692 static void stmmac_exit_fs(struct net_device *dev)
2693 {
2694         struct stmmac_priv *priv = netdev_priv(dev);
2695
2696         debugfs_remove_recursive(priv->dbgfs_dir);
2697 }
2698 #endif /* CONFIG_DEBUG_FS */
2699
2700 static const struct net_device_ops stmmac_netdev_ops = {
2701         .ndo_open = stmmac_open,
2702         .ndo_start_xmit = stmmac_xmit,
2703         .ndo_stop = stmmac_release,
2704         .ndo_change_mtu = stmmac_change_mtu,
2705         .ndo_fix_features = stmmac_fix_features,
2706         .ndo_set_features = stmmac_set_features,
2707         .ndo_set_rx_mode = stmmac_set_rx_mode,
2708         .ndo_tx_timeout = stmmac_tx_timeout,
2709         .ndo_do_ioctl = stmmac_ioctl,
2710 #ifdef CONFIG_NET_POLL_CONTROLLER
2711         .ndo_poll_controller = stmmac_poll_controller,
2712 #endif
2713         .ndo_set_mac_address = eth_mac_addr,
2714 };
2715
2716 /**
2717  *  stmmac_hw_init - Init the MAC device
2718  *  @priv: driver private structure
2719  *  Description: this function is to configure the MAC device according to
2720  *  some platform parameters or the HW capability register. It prepares the
2721  *  driver to use either ring or chain modes and to setup either enhanced or
2722  *  normal descriptors.
2723  */
2724 static int stmmac_hw_init(struct stmmac_priv *priv)
2725 {
2726         struct mac_device_info *mac;
2727
2728         /* Identify the MAC HW device */
2729         if (priv->plat->has_gmac) {
2730                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2731                 mac = dwmac1000_setup(priv->ioaddr,
2732                                       priv->plat->multicast_filter_bins,
2733                                       priv->plat->unicast_filter_entries);
2734         } else {
2735                 mac = dwmac100_setup(priv->ioaddr);
2736         }
2737         if (!mac)
2738                 return -ENOMEM;
2739
2740         priv->hw = mac;
2741
2742         /* Get and dump the chip ID */
2743         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2744
2745         /* To use the chained or ring mode */
2746         if (chain_mode) {
2747                 priv->hw->mode = &chain_mode_ops;
2748                 pr_info(" Chain mode enabled\n");
2749                 priv->mode = STMMAC_CHAIN_MODE;
2750         } else {
2751                 priv->hw->mode = &ring_mode_ops;
2752                 pr_info(" Ring mode enabled\n");
2753                 priv->mode = STMMAC_RING_MODE;
2754         }
2755
2756         /* Get the HW capability (new GMAC newer than 3.50a) */
2757         priv->hw_cap_support = stmmac_get_hw_features(priv);
2758         if (priv->hw_cap_support) {
2759                 pr_info(" DMA HW capability register supported");
2760
2761                 /* We can override some gmac/dma configuration fields: e.g.
2762                  * enh_desc, tx_coe (e.g. that are passed through the
2763                  * platform) with the values from the HW capability
2764                  * register (if supported).
2765                  */
2766                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2767                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2768
2769                 /* TXCOE doesn't work in thresh DMA mode */
2770                 if (priv->plat->force_thresh_dma_mode)
2771                         priv->plat->tx_coe = 0;
2772                 else
2773                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
2774
2775                 if (priv->dma_cap.rx_coe_type2)
2776                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2777                 else if (priv->dma_cap.rx_coe_type1)
2778                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2779
2780         } else
2781                 pr_info(" No HW DMA feature register supported");
2782
2783         /* To use alternate (extended) or normal descriptor structures */
2784         stmmac_selec_desc_mode(priv);
2785
2786         if (priv->plat->rx_coe) {
2787                 priv->hw->rx_csum = priv->plat->rx_coe;
2788                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2789                         priv->plat->rx_coe);
2790         }
2791         if (priv->plat->tx_coe)
2792                 pr_info(" TX Checksum insertion supported\n");
2793
2794         if (priv->plat->pmt) {
2795                 pr_info(" Wake-Up On Lan supported\n");
2796                 device_set_wakeup_capable(priv->device, 1);
2797         }
2798
2799         return 0;
2800 }
2801
2802 /**
2803  * stmmac_dvr_probe
2804  * @device: device pointer
2805  * @plat_dat: platform data pointer
2806  * @addr: iobase memory address
2807  * Description: this is the main probe function used to
2808  * call the alloc_etherdev, allocate the priv structure.
2809  * Return:
2810  * on success the new private structure is returned, otherwise the error
2811  * pointer.
2812  */
2813 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2814                                      struct plat_stmmacenet_data *plat_dat,
2815                                      void __iomem *addr)
2816 {
2817         int ret = 0;
2818         struct net_device *ndev = NULL;
2819         struct stmmac_priv *priv;
2820
2821         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2822         if (!ndev)
2823                 return ERR_PTR(-ENOMEM);
2824
2825         SET_NETDEV_DEV(ndev, device);
2826
2827         priv = netdev_priv(ndev);
2828         priv->device = device;
2829         priv->dev = ndev;
2830
2831         stmmac_set_ethtool_ops(ndev);
2832         priv->pause = pause;
2833         priv->plat = plat_dat;
2834         priv->ioaddr = addr;
2835         priv->dev->base_addr = (unsigned long)addr;
2836
2837         /* Verify driver arguments */
2838         stmmac_verify_args();
2839
2840         /* Override with kernel parameters if supplied XXX CRS XXX
2841          * this needs to have multiple instances
2842          */
2843         if ((phyaddr >= 0) && (phyaddr <= 31))
2844                 priv->plat->phy_addr = phyaddr;
2845
2846         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2847         if (IS_ERR(priv->stmmac_clk)) {
2848                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2849                          __func__);
2850                 /* If failed to obtain stmmac_clk and specific clk_csr value
2851                  * is NOT passed from the platform, probe fail.
2852                  */
2853                 if (!priv->plat->clk_csr) {
2854                         ret = PTR_ERR(priv->stmmac_clk);
2855                         goto error_clk_get;
2856                 } else {
2857                         priv->stmmac_clk = NULL;
2858                 }
2859         }
2860         clk_prepare_enable(priv->stmmac_clk);
2861
2862         priv->pclk = devm_clk_get(priv->device, "pclk");
2863         if (IS_ERR(priv->pclk)) {
2864                 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
2865                         ret = -EPROBE_DEFER;
2866                         goto error_pclk_get;
2867                 }
2868                 priv->pclk = NULL;
2869         }
2870         clk_prepare_enable(priv->pclk);
2871
2872         priv->stmmac_rst = devm_reset_control_get(priv->device,
2873                                                   STMMAC_RESOURCE_NAME);
2874         if (IS_ERR(priv->stmmac_rst)) {
2875                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2876                         ret = -EPROBE_DEFER;
2877                         goto error_hw_init;
2878                 }
2879                 dev_info(priv->device, "no reset control found\n");
2880                 priv->stmmac_rst = NULL;
2881         }
2882         if (priv->stmmac_rst)
2883                 reset_control_deassert(priv->stmmac_rst);
2884
2885         /* Init MAC and get the capabilities */
2886         ret = stmmac_hw_init(priv);
2887         if (ret)
2888                 goto error_hw_init;
2889
2890         ndev->netdev_ops = &stmmac_netdev_ops;
2891
2892         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2893                             NETIF_F_RXCSUM;
2894         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2895         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2896 #ifdef STMMAC_VLAN_TAG_USED
2897         /* Both mac100 and gmac support receive VLAN tag detection */
2898         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2899 #endif
2900         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2901
2902         if (flow_ctrl)
2903                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2904
2905         /* Rx Watchdog is available in the COREs newer than the 3.40.
2906          * In some case, for example on bugged HW this feature
2907          * has to be disable and this can be done by passing the
2908          * riwt_off field from the platform.
2909          */
2910         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2911                 priv->use_riwt = 1;
2912                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2913         }
2914
2915         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2916
2917         spin_lock_init(&priv->lock);
2918         spin_lock_init(&priv->tx_lock);
2919
2920         ret = register_netdev(ndev);
2921         if (ret) {
2922                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2923                 goto error_netdev_register;
2924         }
2925
2926         /* If a specific clk_csr value is passed from the platform
2927          * this means that the CSR Clock Range selection cannot be
2928          * changed at run-time and it is fixed. Viceversa the driver'll try to
2929          * set the MDC clock dynamically according to the csr actual
2930          * clock input.
2931          */
2932         if (!priv->plat->clk_csr)
2933                 stmmac_clk_csr_set(priv);
2934         else
2935                 priv->clk_csr = priv->plat->clk_csr;
2936
2937         stmmac_check_pcs_mode(priv);
2938
2939         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2940             priv->pcs != STMMAC_PCS_RTBI) {
2941                 /* MDIO bus Registration */
2942                 ret = stmmac_mdio_register(ndev);
2943                 if (ret < 0) {
2944                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2945                                  __func__, priv->plat->bus_id);
2946                         goto error_mdio_register;
2947                 }
2948         }
2949
2950         return priv;
2951
2952 error_mdio_register:
2953         unregister_netdev(ndev);
2954 error_netdev_register:
2955         netif_napi_del(&priv->napi);
2956 error_hw_init:
2957         clk_disable_unprepare(priv->pclk);
2958 error_pclk_get:
2959         clk_disable_unprepare(priv->stmmac_clk);
2960 error_clk_get:
2961         free_netdev(ndev);
2962
2963         return ERR_PTR(ret);
2964 }
2965 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
2966
2967 /**
2968  * stmmac_dvr_remove
2969  * @ndev: net device pointer
2970  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2971  * changes the link status, releases the DMA descriptor rings.
2972  */
2973 int stmmac_dvr_remove(struct net_device *ndev)
2974 {
2975         struct stmmac_priv *priv = netdev_priv(ndev);
2976
2977         pr_info("%s:\n\tremoving driver", __func__);
2978
2979         priv->hw->dma->stop_rx(priv->ioaddr);
2980         priv->hw->dma->stop_tx(priv->ioaddr);
2981
2982         stmmac_set_mac(priv->ioaddr, false);
2983         netif_carrier_off(ndev);
2984         unregister_netdev(ndev);
2985         if (priv->stmmac_rst)
2986                 reset_control_assert(priv->stmmac_rst);
2987         clk_disable_unprepare(priv->pclk);
2988         clk_disable_unprepare(priv->stmmac_clk);
2989         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2990             priv->pcs != STMMAC_PCS_RTBI)
2991                 stmmac_mdio_unregister(ndev);
2992         free_netdev(ndev);
2993
2994         return 0;
2995 }
2996 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
2997
2998 /**
2999  * stmmac_suspend - suspend callback
3000  * @ndev: net device pointer
3001  * Description: this is the function to suspend the device and it is called
3002  * by the platform driver to stop the network queue, release the resources,
3003  * program the PMT register (for WoL), clean and release driver resources.
3004  */
3005 int stmmac_suspend(struct net_device *ndev)
3006 {
3007         struct stmmac_priv *priv = netdev_priv(ndev);
3008         unsigned long flags;
3009
3010         if (!ndev || !netif_running(ndev))
3011                 return 0;
3012
3013         if (priv->phydev)
3014                 phy_stop(priv->phydev);
3015
3016         spin_lock_irqsave(&priv->lock, flags);
3017
3018         netif_device_detach(ndev);
3019         netif_stop_queue(ndev);
3020
3021         napi_disable(&priv->napi);
3022
3023         /* Stop TX/RX DMA */
3024         priv->hw->dma->stop_tx(priv->ioaddr);
3025         priv->hw->dma->stop_rx(priv->ioaddr);
3026
3027         stmmac_clear_descriptors(priv);
3028
3029         /* Enable Power down mode by programming the PMT regs */
3030         if (device_may_wakeup(priv->device)) {
3031                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3032                 priv->irq_wake = 1;
3033         } else {
3034                 stmmac_set_mac(priv->ioaddr, false);
3035                 pinctrl_pm_select_sleep_state(priv->device);
3036                 /* Disable clock in case of PWM is off */
3037                 clk_disable(priv->pclk);
3038                 clk_disable(priv->stmmac_clk);
3039         }
3040         spin_unlock_irqrestore(&priv->lock, flags);
3041
3042         priv->oldlink = 0;
3043         priv->speed = 0;
3044         priv->oldduplex = -1;
3045         return 0;
3046 }
3047 EXPORT_SYMBOL_GPL(stmmac_suspend);
3048
3049 /**
3050  * stmmac_resume - resume callback
3051  * @ndev: net device pointer
3052  * Description: when resume this function is invoked to setup the DMA and CORE
3053  * in a usable state.
3054  */
3055 int stmmac_resume(struct net_device *ndev)
3056 {
3057         struct stmmac_priv *priv = netdev_priv(ndev);
3058         unsigned long flags;
3059
3060         if (!netif_running(ndev))
3061                 return 0;
3062
3063         spin_lock_irqsave(&priv->lock, flags);
3064
3065         /* Power Down bit, into the PM register, is cleared
3066          * automatically as soon as a magic packet or a Wake-up frame
3067          * is received. Anyway, it's better to manually clear
3068          * this bit because it can generate problems while resuming
3069          * from another devices (e.g. serial console).
3070          */
3071         if (device_may_wakeup(priv->device)) {
3072                 priv->hw->mac->pmt(priv->hw, 0);
3073                 priv->irq_wake = 0;
3074         } else {
3075                 pinctrl_pm_select_default_state(priv->device);
3076                 /* enable the clk prevously disabled */
3077                 clk_enable(priv->stmmac_clk);
3078                 clk_enable(priv->pclk);
3079                 /* reset the phy so that it's ready */
3080                 if (priv->mii)
3081                         stmmac_mdio_reset(priv->mii);
3082         }
3083
3084         netif_device_attach(ndev);
3085
3086         init_dma_desc_rings(ndev, GFP_ATOMIC);
3087         stmmac_hw_setup(ndev, false);
3088         stmmac_init_tx_coalesce(priv);
3089
3090         napi_enable(&priv->napi);
3091
3092         netif_start_queue(ndev);
3093
3094         spin_unlock_irqrestore(&priv->lock, flags);
3095
3096         if (priv->phydev)
3097                 phy_start(priv->phydev);
3098
3099         return 0;
3100 }
3101 EXPORT_SYMBOL_GPL(stmmac_resume);
3102
3103 #ifndef MODULE
3104 static int __init stmmac_cmdline_opt(char *str)
3105 {
3106         char *opt;
3107
3108         if (!str || !*str)
3109                 return -EINVAL;
3110         while ((opt = strsep(&str, ",")) != NULL) {
3111                 if (!strncmp(opt, "debug:", 6)) {
3112                         if (kstrtoint(opt + 6, 0, &debug))
3113                                 goto err;
3114                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3115                         if (kstrtoint(opt + 8, 0, &phyaddr))
3116                                 goto err;
3117                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
3118                         if (kstrtoint(opt + 11, 0, &dma_txsize))
3119                                 goto err;
3120                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
3121                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
3122                                 goto err;
3123                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3124                         if (kstrtoint(opt + 7, 0, &buf_sz))
3125                                 goto err;
3126                 } else if (!strncmp(opt, "tc:", 3)) {
3127                         if (kstrtoint(opt + 3, 0, &tc))
3128                                 goto err;
3129                 } else if (!strncmp(opt, "watchdog:", 9)) {
3130                         if (kstrtoint(opt + 9, 0, &watchdog))
3131                                 goto err;
3132                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3133                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3134                                 goto err;
3135                 } else if (!strncmp(opt, "pause:", 6)) {
3136                         if (kstrtoint(opt + 6, 0, &pause))
3137                                 goto err;
3138                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3139                         if (kstrtoint(opt + 10, 0, &eee_timer))
3140                                 goto err;
3141                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3142                         if (kstrtoint(opt + 11, 0, &chain_mode))
3143                                 goto err;
3144                 }
3145         }
3146         return 0;
3147
3148 err:
3149         pr_err("%s: ERROR broken module parameter conversion", __func__);
3150         return -EINVAL;
3151 }
3152
3153 __setup("stmmaceth=", stmmac_cmdline_opt);
3154 #endif /* MODULE */
3155
3156 static int __init stmmac_init(void)
3157 {
3158 #ifdef CONFIG_DEBUG_FS
3159         /* Create debugfs main directory if it doesn't exist yet */
3160         if (!stmmac_fs_dir) {
3161                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3162
3163                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3164                         pr_err("ERROR %s, debugfs create directory failed\n",
3165                                STMMAC_RESOURCE_NAME);
3166
3167                         return -ENOMEM;
3168                 }
3169         }
3170 #endif
3171
3172         return 0;
3173 }
3174
3175 static void __exit stmmac_exit(void)
3176 {
3177 #ifdef CONFIG_DEBUG_FS
3178         debugfs_remove_recursive(stmmac_fs_dir);
3179 #endif
3180 }
3181
3182 module_init(stmmac_init)
3183 module_exit(stmmac_exit)
3184
3185 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3186 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3187 MODULE_LICENSE("GPL");