kernel/drivers/net/ethernet/sfc/falcon.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2013 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/i2c.h>
  17 #include <linux/mii.h>
  18 #include <linux/slab.h>
  19 #include "net_driver.h"
  20 #include "bitfield.h"
  21 #include "efx.h"
  22 #include "nic.h"
  23 #include "farch_regs.h"
  24 #include "io.h"
  25 #include "phy.h"
  26 #include "workarounds.h"
  27 #include "selftest.h"
  28 #include "mdio_10g.h"
  29
  30 /* Hardware control for SFC4000 (aka Falcon). */
  31
  32 /**************************************************************************
  33  *
  34  * NIC stats
  35  *
  36  **************************************************************************
  37  */
  38
  39 #define FALCON_MAC_STATS_SIZE 0x100
  40
  41 #define XgRxOctets_offset 0x0
  42 #define XgRxOctets_WIDTH 48
  43 #define XgRxOctetsOK_offset 0x8
  44 #define XgRxOctetsOK_WIDTH 48
  45 #define XgRxPkts_offset 0x10
  46 #define XgRxPkts_WIDTH 32
  47 #define XgRxPktsOK_offset 0x14
  48 #define XgRxPktsOK_WIDTH 32
  49 #define XgRxBroadcastPkts_offset 0x18
  50 #define XgRxBroadcastPkts_WIDTH 32
  51 #define XgRxMulticastPkts_offset 0x1C
  52 #define XgRxMulticastPkts_WIDTH 32
  53 #define XgRxUnicastPkts_offset 0x20
  54 #define XgRxUnicastPkts_WIDTH 32
  55 #define XgRxUndersizePkts_offset 0x24
  56 #define XgRxUndersizePkts_WIDTH 32
  57 #define XgRxOversizePkts_offset 0x28
  58 #define XgRxOversizePkts_WIDTH 32
  59 #define XgRxJabberPkts_offset 0x2C
  60 #define XgRxJabberPkts_WIDTH 32
  61 #define XgRxUndersizeFCSerrorPkts_offset 0x30
  62 #define XgRxUndersizeFCSerrorPkts_WIDTH 32
  63 #define XgRxDropEvents_offset 0x34
  64 #define XgRxDropEvents_WIDTH 32
  65 #define XgRxFCSerrorPkts_offset 0x38
  66 #define XgRxFCSerrorPkts_WIDTH 32
  67 #define XgRxAlignError_offset 0x3C
  68 #define XgRxAlignError_WIDTH 32
  69 #define XgRxSymbolError_offset 0x40
  70 #define XgRxSymbolError_WIDTH 32
  71 #define XgRxInternalMACError_offset 0x44
  72 #define XgRxInternalMACError_WIDTH 32
  73 #define XgRxControlPkts_offset 0x48
  74 #define XgRxControlPkts_WIDTH 32
  75 #define XgRxPausePkts_offset 0x4C
  76 #define XgRxPausePkts_WIDTH 32
  77 #define XgRxPkts64Octets_offset 0x50
  78 #define XgRxPkts64Octets_WIDTH 32
  79 #define XgRxPkts65to127Octets_offset 0x54
  80 #define XgRxPkts65to127Octets_WIDTH 32
  81 #define XgRxPkts128to255Octets_offset 0x58
  82 #define XgRxPkts128to255Octets_WIDTH 32
  83 #define XgRxPkts256to511Octets_offset 0x5C
  84 #define XgRxPkts256to511Octets_WIDTH 32
  85 #define XgRxPkts512to1023Octets_offset 0x60
  86 #define XgRxPkts512to1023Octets_WIDTH 32
  87 #define XgRxPkts1024to15xxOctets_offset 0x64
  88 #define XgRxPkts1024to15xxOctets_WIDTH 32
  89 #define XgRxPkts15xxtoMaxOctets_offset 0x68
  90 #define XgRxPkts15xxtoMaxOctets_WIDTH 32
  91 #define XgRxLengthError_offset 0x6C
  92 #define XgRxLengthError_WIDTH 32
  93 #define XgTxPkts_offset 0x80
  94 #define XgTxPkts_WIDTH 32
  95 #define XgTxOctets_offset 0x88
  96 #define XgTxOctets_WIDTH 48
  97 #define XgTxMulticastPkts_offset 0x90
  98 #define XgTxMulticastPkts_WIDTH 32
  99 #define XgTxBroadcastPkts_offset 0x94
 100 #define XgTxBroadcastPkts_WIDTH 32
 101 #define XgTxUnicastPkts_offset 0x98
 102 #define XgTxUnicastPkts_WIDTH 32
 103 #define XgTxControlPkts_offset 0x9C
 104 #define XgTxControlPkts_WIDTH 32
 105 #define XgTxPausePkts_offset 0xA0
 106 #define XgTxPausePkts_WIDTH 32
 107 #define XgTxPkts64Octets_offset 0xA4
 108 #define XgTxPkts64Octets_WIDTH 32
 109 #define XgTxPkts65to127Octets_offset 0xA8
 110 #define XgTxPkts65to127Octets_WIDTH 32
 111 #define XgTxPkts128to255Octets_offset 0xAC
 112 #define XgTxPkts128to255Octets_WIDTH 32
 113 #define XgTxPkts256to511Octets_offset 0xB0
 114 #define XgTxPkts256to511Octets_WIDTH 32
 115 #define XgTxPkts512to1023Octets_offset 0xB4
 116 #define XgTxPkts512to1023Octets_WIDTH 32
 117 #define XgTxPkts1024to15xxOctets_offset 0xB8
 118 #define XgTxPkts1024to15xxOctets_WIDTH 32
 119 #define XgTxPkts1519toMaxOctets_offset 0xBC
 120 #define XgTxPkts1519toMaxOctets_WIDTH 32
 121 #define XgTxUndersizePkts_offset 0xC0
 122 #define XgTxUndersizePkts_WIDTH 32
 123 #define XgTxOversizePkts_offset 0xC4
 124 #define XgTxOversizePkts_WIDTH 32
 125 #define XgTxNonTcpUdpPkt_offset 0xC8
 126 #define XgTxNonTcpUdpPkt_WIDTH 16
 127 #define XgTxMacSrcErrPkt_offset 0xCC
 128 #define XgTxMacSrcErrPkt_WIDTH 16
 129 #define XgTxIpSrcErrPkt_offset 0xD0
 130 #define XgTxIpSrcErrPkt_WIDTH 16
 131 #define XgDmaDone_offset 0xD4
 132 #define XgDmaDone_WIDTH 32
 133
 134 #define FALCON_XMAC_STATS_DMA_FLAG(efx)                         \
 135         (*(u32 *)((efx)->stats_buffer.addr + XgDmaDone_offset))
 136
 137 #define FALCON_DMA_STAT(ext_name, hw_name)                              \
 138         [FALCON_STAT_ ## ext_name] =                                    \
 139         { #ext_name,                                                    \
 140           /* 48-bit stats are zero-padded to 64 on DMA */               \
 141           hw_name ## _ ## WIDTH == 48 ? 64 : hw_name ## _ ## WIDTH,     \
 142           hw_name ## _ ## offset }
 143 #define FALCON_OTHER_STAT(ext_name)                                     \
 144         [FALCON_STAT_ ## ext_name] = { #ext_name, 0, 0 }
 145 #define GENERIC_SW_STAT(ext_name)                               \
 146         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
 147
 148 static const struct efx_hw_stat_desc falcon_stat_desc[FALCON_STAT_COUNT] = {
 149         FALCON_DMA_STAT(tx_bytes, XgTxOctets),
 150         FALCON_DMA_STAT(tx_packets, XgTxPkts),
 151         FALCON_DMA_STAT(tx_pause, XgTxPausePkts),
 152         FALCON_DMA_STAT(tx_control, XgTxControlPkts),
 153         FALCON_DMA_STAT(tx_unicast, XgTxUnicastPkts),
 154         FALCON_DMA_STAT(tx_multicast, XgTxMulticastPkts),
 155         FALCON_DMA_STAT(tx_broadcast, XgTxBroadcastPkts),
 156         FALCON_DMA_STAT(tx_lt64, XgTxUndersizePkts),
 157         FALCON_DMA_STAT(tx_64, XgTxPkts64Octets),
 158         FALCON_DMA_STAT(tx_65_to_127, XgTxPkts65to127Octets),
 159         FALCON_DMA_STAT(tx_128_to_255, XgTxPkts128to255Octets),
 160         FALCON_DMA_STAT(tx_256_to_511, XgTxPkts256to511Octets),
 161         FALCON_DMA_STAT(tx_512_to_1023, XgTxPkts512to1023Octets),
 162         FALCON_DMA_STAT(tx_1024_to_15xx, XgTxPkts1024to15xxOctets),
 163         FALCON_DMA_STAT(tx_15xx_to_jumbo, XgTxPkts1519toMaxOctets),
 164         FALCON_DMA_STAT(tx_gtjumbo, XgTxOversizePkts),
 165         FALCON_DMA_STAT(tx_non_tcpudp, XgTxNonTcpUdpPkt),
 166         FALCON_DMA_STAT(tx_mac_src_error, XgTxMacSrcErrPkt),
 167         FALCON_DMA_STAT(tx_ip_src_error, XgTxIpSrcErrPkt),
 168         FALCON_DMA_STAT(rx_bytes, XgRxOctets),
 169         FALCON_DMA_STAT(rx_good_bytes, XgRxOctetsOK),
 170         FALCON_OTHER_STAT(rx_bad_bytes),
 171         FALCON_DMA_STAT(rx_packets, XgRxPkts),
 172         FALCON_DMA_STAT(rx_good, XgRxPktsOK),
 173         FALCON_DMA_STAT(rx_bad, XgRxFCSerrorPkts),
 174         FALCON_DMA_STAT(rx_pause, XgRxPausePkts),
 175         FALCON_DMA_STAT(rx_control, XgRxControlPkts),
 176         FALCON_DMA_STAT(rx_unicast, XgRxUnicastPkts),
 177         FALCON_DMA_STAT(rx_multicast, XgRxMulticastPkts),
 178         FALCON_DMA_STAT(rx_broadcast, XgRxBroadcastPkts),
 179         FALCON_DMA_STAT(rx_lt64, XgRxUndersizePkts),
 180         FALCON_DMA_STAT(rx_64, XgRxPkts64Octets),
 181         FALCON_DMA_STAT(rx_65_to_127, XgRxPkts65to127Octets),
 182         FALCON_DMA_STAT(rx_128_to_255, XgRxPkts128to255Octets),
 183         FALCON_DMA_STAT(rx_256_to_511, XgRxPkts256to511Octets),
 184         FALCON_DMA_STAT(rx_512_to_1023, XgRxPkts512to1023Octets),
 185         FALCON_DMA_STAT(rx_1024_to_15xx, XgRxPkts1024to15xxOctets),
 186         FALCON_DMA_STAT(rx_15xx_to_jumbo, XgRxPkts15xxtoMaxOctets),
 187         FALCON_DMA_STAT(rx_gtjumbo, XgRxOversizePkts),
 188         FALCON_DMA_STAT(rx_bad_lt64, XgRxUndersizeFCSerrorPkts),
 189         FALCON_DMA_STAT(rx_bad_gtjumbo, XgRxJabberPkts),
 190         FALCON_DMA_STAT(rx_overflow, XgRxDropEvents),
 191         FALCON_DMA_STAT(rx_symbol_error, XgRxSymbolError),
 192         FALCON_DMA_STAT(rx_align_error, XgRxAlignError),
 193         FALCON_DMA_STAT(rx_length_error, XgRxLengthError),
 194         FALCON_DMA_STAT(rx_internal_error, XgRxInternalMACError),
 195         FALCON_OTHER_STAT(rx_nodesc_drop_cnt),
 196         GENERIC_SW_STAT(rx_nodesc_trunc),
 197         GENERIC_SW_STAT(rx_noskb_drops),
 198 };
 199 static const unsigned long falcon_stat_mask[] = {
 200         [0 ... BITS_TO_LONGS(FALCON_STAT_COUNT) - 1] = ~0UL,
 201 };
 202
 203 /**************************************************************************
 204  *
 205  * Basic SPI command set and bit definitions
 206  *
 207  *************************************************************************/
 208
 209 #define SPI_WRSR 0x01           /* Write status register */
 210 #define SPI_WRITE 0x02          /* Write data to memory array */
 211 #define SPI_READ 0x03           /* Read data from memory array */
 212 #define SPI_WRDI 0x04           /* Reset write enable latch */
 213 #define SPI_RDSR 0x05           /* Read status register */
 214 #define SPI_WREN 0x06           /* Set write enable latch */
 215 #define SPI_SST_EWSR 0x50       /* SST: Enable write to status register */
 216
 217 #define SPI_STATUS_WPEN 0x80    /* Write-protect pin enabled */
 218 #define SPI_STATUS_BP2 0x10     /* Block protection bit 2 */
 219 #define SPI_STATUS_BP1 0x08     /* Block protection bit 1 */
 220 #define SPI_STATUS_BP0 0x04     /* Block protection bit 0 */
 221 #define SPI_STATUS_WEN 0x02     /* State of the write enable latch */
 222 #define SPI_STATUS_NRDY 0x01    /* Device busy flag */
 223
 224 /**************************************************************************
 225  *
 226  * Non-volatile memory layout
 227  *
 228  **************************************************************************
 229  */
 230
 231 /* SFC4000 flash is partitioned into:
 232  *     0-0x400       chip and board config (see struct falcon_nvconfig)
 233  *     0x400-0x8000  unused (or may contain VPD if EEPROM not present)
 234  *     0x8000-end    boot code (mapped to PCI expansion ROM)
 235  * SFC4000 small EEPROM (size < 0x400) is used for VPD only.
 236  * SFC4000 large EEPROM (size >= 0x400) is partitioned into:
 237  *     0-0x400       chip and board config
 238  *     configurable  VPD
 239  *     0x800-0x1800  boot config
 240  * Aside from the chip and board config, all of these are optional and may
 241  * be absent or truncated depending on the devices used.
 242  */
 243 #define FALCON_NVCONFIG_END 0x400U
 244 #define FALCON_FLASH_BOOTCODE_START 0x8000U
 245 #define FALCON_EEPROM_BOOTCONFIG_START 0x800U
 246 #define FALCON_EEPROM_BOOTCONFIG_END 0x1800U
 247
 248 /* Board configuration v2 (v1 is obsolete; later versions are compatible) */
 249 struct falcon_nvconfig_board_v2 {
 250         __le16 nports;
 251         u8 port0_phy_addr;
 252         u8 port0_phy_type;
 253         u8 port1_phy_addr;
 254         u8 port1_phy_type;
 255         __le16 asic_sub_revision;
 256         __le16 board_revision;
 257 } __packed;
 258
 259 /* Board configuration v3 extra information */
 260 struct falcon_nvconfig_board_v3 {
 261         __le32 spi_device_type[2];
 262 } __packed;
 263
 264 /* Bit numbers for spi_device_type */
 265 #define SPI_DEV_TYPE_SIZE_LBN 0
 266 #define SPI_DEV_TYPE_SIZE_WIDTH 5
 267 #define SPI_DEV_TYPE_ADDR_LEN_LBN 6
 268 #define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
 269 #define SPI_DEV_TYPE_ERASE_CMD_LBN 8
 270 #define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
 271 #define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
 272 #define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
 273 #define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
 274 #define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
 275 #define SPI_DEV_TYPE_FIELD(type, field)                                 \
 276         (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
 277
 278 #define FALCON_NVCONFIG_OFFSET 0x300
 279
 280 #define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
 281 struct falcon_nvconfig {
 282         efx_oword_t ee_vpd_cfg_reg;                     /* 0x300 */
 283         u8 mac_address[2][8];                   /* 0x310 */
 284         efx_oword_t pcie_sd_ctl0123_reg;                /* 0x320 */
 285         efx_oword_t pcie_sd_ctl45_reg;                  /* 0x330 */
 286         efx_oword_t pcie_pcs_ctl_stat_reg;              /* 0x340 */
 287         efx_oword_t hw_init_reg;                        /* 0x350 */
 288         efx_oword_t nic_stat_reg;                       /* 0x360 */
 289         efx_oword_t glb_ctl_reg;                        /* 0x370 */
 290         efx_oword_t srm_cfg_reg;                        /* 0x380 */
 291         efx_oword_t spare_reg;                          /* 0x390 */
 292         __le16 board_magic_num;                 /* 0x3A0 */
 293         __le16 board_struct_ver;
 294         __le16 board_checksum;
 295         struct falcon_nvconfig_board_v2 board_v2;
 296         efx_oword_t ee_base_page_reg;                   /* 0x3B0 */
 297         struct falcon_nvconfig_board_v3 board_v3;       /* 0x3C0 */
 298 } __packed;
 299
 300 /*************************************************************************/
 301
 302 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method);
 303 static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx);
 304
 305 static const unsigned int
 306 /* "Large" EEPROM device: Atmel AT25640 or similar
 307  * 8 KB, 16-bit address, 32 B write block */
 308 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
 309                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
 310                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
 311 /* Default flash device: Atmel AT25F1024
 312  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
 313 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
 314                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
 315                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
 316                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
 317                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
 318
 319 /**************************************************************************
 320  *
 321  * I2C bus - this is a bit-bashing interface using GPIO pins
 322  * Note that it uses the output enables to tristate the outputs
 323  * SDA is the data pin and SCL is the clock
 324  *
 325  **************************************************************************
 326  */
 327 static void falcon_setsda(void *data, int state)
 328 {
 329         struct efx_nic *efx = (struct efx_nic *)data;
 330         efx_oword_t reg;
 331
 332         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 333         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
 334         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
 335 }
 336
 337 static void falcon_setscl(void *data, int state)
 338 {
 339         struct efx_nic *efx = (struct efx_nic *)data;
 340         efx_oword_t reg;
 341
 342         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 343         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
 344         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
 345 }
 346
 347 static int falcon_getsda(void *data)
 348 {
 349         struct efx_nic *efx = (struct efx_nic *)data;
 350         efx_oword_t reg;
 351
 352         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 353         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
 354 }
 355
 356 static int falcon_getscl(void *data)
 357 {
 358         struct efx_nic *efx = (struct efx_nic *)data;
 359         efx_oword_t reg;
 360
 361         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 362         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
 363 }
 364
 365 static const struct i2c_algo_bit_data falcon_i2c_bit_operations = {
 366         .setsda         = falcon_setsda,
 367         .setscl         = falcon_setscl,
 368         .getsda         = falcon_getsda,
 369         .getscl         = falcon_getscl,
 370         .udelay         = 5,
 371         /* Wait up to 50 ms for slave to let us pull SCL high */
 372         .timeout        = DIV_ROUND_UP(HZ, 20),
 373 };
 374
 375 static void falcon_push_irq_moderation(struct efx_channel *channel)
 376 {
 377         efx_dword_t timer_cmd;
 378         struct efx_nic *efx = channel->efx;
 379
 380         /* Set timer register */
 381         if (channel->irq_moderation) {
 382                 EFX_POPULATE_DWORD_2(timer_cmd,
 383                                      FRF_AB_TC_TIMER_MODE,
 384                                      FFE_BB_TIMER_MODE_INT_HLDOFF,
 385                                      FRF_AB_TC_TIMER_VAL,
 386                                      channel->irq_moderation - 1);
 387         } else {
 388                 EFX_POPULATE_DWORD_2(timer_cmd,
 389                                      FRF_AB_TC_TIMER_MODE,
 390                                      FFE_BB_TIMER_MODE_DIS,
 391                                      FRF_AB_TC_TIMER_VAL, 0);
 392         }
 393         BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
 394         efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
 395                                channel->channel);
 396 }
 397
 398 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
 399
 400 static void falcon_prepare_flush(struct efx_nic *efx)
 401 {
 402         falcon_deconfigure_mac_wrapper(efx);
 403
 404         /* Wait for the tx and rx fifo's to get to the next packet boundary
 405          * (~1ms without back-pressure), then to drain the remainder of the
 406          * fifo's at data path speeds (negligible), with a healthy margin. */
 407         msleep(10);
 408 }
 409
 410 /* Acknowledge a legacy interrupt from Falcon
 411  *
 412  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
 413  *
 414  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
 415  * BIU. Interrupt acknowledge is read sensitive so must write instead
 416  * (then read to ensure the BIU collector is flushed)
 417  *
 418  * NB most hardware supports MSI interrupts
 419  */
 420 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
 421 {
 422         efx_dword_t reg;
 423
 424         EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
 425         efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
 426         efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
 427 }
 428
 429 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
 430 {
 431         struct efx_nic *efx = dev_id;
 432         efx_oword_t *int_ker = efx->irq_status.addr;
 433         int syserr;
 434         int queues;
 435
 436         /* Check to see if this is our interrupt.  If it isn't, we
 437          * exit without having touched the hardware.
 438          */
 439         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
 440                 netif_vdbg(efx, intr, efx->net_dev,
 441                            "IRQ %d on CPU %d not for me\n", irq,
 442                            raw_smp_processor_id());
 443                 return IRQ_NONE;
 444         }
 445         efx->last_irq_cpu = raw_smp_processor_id();
 446         netif_vdbg(efx, intr, efx->net_dev,
 447                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
 448                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
 449
 450         if (!likely(ACCESS_ONCE(efx->irq_soft_enabled)))
 451                 return IRQ_HANDLED;
 452
 453         /* Check to see if we have a serious error condition */
 454         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
 455         if (unlikely(syserr))
 456                 return efx_farch_fatal_interrupt(efx);
 457
 458         /* Determine interrupting queues, clear interrupt status
 459          * register and acknowledge the device interrupt.
 460          */
 461         BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
 462         queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
 463         EFX_ZERO_OWORD(*int_ker);
 464         wmb(); /* Ensure the vector is cleared before interrupt ack */
 465         falcon_irq_ack_a1(efx);
 466
 467         if (queues & 1)
 468                 efx_schedule_channel_irq(efx_get_channel(efx, 0));
 469         if (queues & 2)
 470                 efx_schedule_channel_irq(efx_get_channel(efx, 1));
 471         return IRQ_HANDLED;
 472 }
 473
 474 /**************************************************************************
 475  *
 476  * RSS
 477  *
 478  **************************************************************************
 479  */
 480 static int dummy_rx_push_rss_config(struct efx_nic *efx, bool user,
 481                                     const u32 *rx_indir_table)
 482 {
 483         (void) efx;
 484         (void) user;
 485         (void) rx_indir_table;
 486         return -ENOSYS;
 487 }
 488
 489 static int falcon_b0_rx_push_rss_config(struct efx_nic *efx, bool user,
 490                                         const u32 *rx_indir_table)
 491 {
 492         efx_oword_t temp;
 493
 494         (void) user;
 495         /* Set hash key for IPv4 */
 496         memcpy(&temp, efx->rx_hash_key, sizeof(temp));
 497         efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
 498
 499         memcpy(efx->rx_indir_table, rx_indir_table,
 500                sizeof(efx->rx_indir_table));
 501         efx_farch_rx_push_indir_table(efx);
 502         return 0;
 503 }
 504
 505 /**************************************************************************
 506  *
 507  * EEPROM/flash
 508  *
 509  **************************************************************************
 510  */
 511
 512 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
 513
 514 static int falcon_spi_poll(struct efx_nic *efx)
 515 {
 516         efx_oword_t reg;
 517         efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
 518         return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
 519 }
 520
 521 /* Wait for SPI command completion */
 522 static int falcon_spi_wait(struct efx_nic *efx)
 523 {
 524         /* Most commands will finish quickly, so we start polling at
 525          * very short intervals.  Sometimes the command may have to
 526          * wait for VPD or expansion ROM access outside of our
 527          * control, so we allow up to 100 ms. */
 528         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
 529         int i;
 530
 531         for (i = 0; i < 10; i++) {
 532                 if (!falcon_spi_poll(efx))
 533                         return 0;
 534                 udelay(10);
 535         }
 536
 537         for (;;) {
 538                 if (!falcon_spi_poll(efx))
 539                         return 0;
 540                 if (time_after_eq(jiffies, timeout)) {
 541                         netif_err(efx, hw, efx->net_dev,
 542                                   "timed out waiting for SPI\n");
 543                         return -ETIMEDOUT;
 544                 }
 545                 schedule_timeout_uninterruptible(1);
 546         }
 547 }
 548
 549 static int
 550 falcon_spi_cmd(struct efx_nic *efx, const struct falcon_spi_device *spi,
 551                unsigned int command, int address,
 552                const void *in, void *out, size_t len)
 553 {
 554         bool addressed = (address >= 0);
 555         bool reading = (out != NULL);
 556         efx_oword_t reg;
 557         int rc;
 558
 559         /* Input validation */
 560         if (len > FALCON_SPI_MAX_LEN)
 561                 return -EINVAL;
 562
 563         /* Check that previous command is not still running */
 564         rc = falcon_spi_poll(efx);
 565         if (rc)
 566                 return rc;
 567
 568         /* Program address register, if we have an address */
 569         if (addressed) {
 570                 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
 571                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
 572         }
 573
 574         /* Program data register, if we have data */
 575         if (in != NULL) {
 576                 memcpy(&reg, in, len);
 577                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
 578         }
 579
 580         /* Issue read/write command */
 581         EFX_POPULATE_OWORD_7(reg,
 582                              FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
 583                              FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
 584                              FRF_AB_EE_SPI_HCMD_DABCNT, len,
 585                              FRF_AB_EE_SPI_HCMD_READ, reading,
 586                              FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
 587                              FRF_AB_EE_SPI_HCMD_ADBCNT,
 588                              (addressed ? spi->addr_len : 0),
 589                              FRF_AB_EE_SPI_HCMD_ENC, command);
 590         efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
 591
 592         /* Wait for read/write to complete */
 593         rc = falcon_spi_wait(efx);
 594         if (rc)
 595                 return rc;
 596
 597         /* Read data */
 598         if (out != NULL) {
 599                 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
 600                 memcpy(out, &reg, len);
 601         }
 602
 603         return 0;
 604 }
 605
 606 static inline u8
 607 falcon_spi_munge_command(const struct falcon_spi_device *spi,
 608                          const u8 command, const unsigned int address)
 609 {
 610         return command | (((address >> 8) & spi->munge_address) << 3);
 611 }
 612
 613 static int
 614 falcon_spi_read(struct efx_nic *efx, const struct falcon_spi_device *spi,
 615                 loff_t start, size_t len, size_t *retlen, u8 *buffer)
 616 {
 617         size_t block_len, pos = 0;
 618         unsigned int command;
 619         int rc = 0;
 620
 621         while (pos < len) {
 622                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
 623
 624                 command = falcon_spi_munge_command(spi, SPI_READ, start + pos);
 625                 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
 626                                     buffer + pos, block_len);
 627                 if (rc)
 628                         break;
 629                 pos += block_len;
 630
 631                 /* Avoid locking up the system */
 632                 cond_resched();
 633                 if (signal_pending(current)) {
 634                         rc = -EINTR;
 635                         break;
 636                 }
 637         }
 638
 639         if (retlen)
 640                 *retlen = pos;
 641         return rc;
 642 }
 643
 644 #ifdef CONFIG_SFC_MTD
 645
 646 struct falcon_mtd_partition {
 647         struct efx_mtd_partition common;
 648         const struct falcon_spi_device *spi;
 649         size_t offset;
 650 };
 651
 652 #define to_falcon_mtd_partition(mtd)                            \
 653         container_of(mtd, struct falcon_mtd_partition, common.mtd)
 654
 655 static size_t
 656 falcon_spi_write_limit(const struct falcon_spi_device *spi, size_t start)
 657 {
 658         return min(FALCON_SPI_MAX_LEN,
 659                    (spi->block_size - (start & (spi->block_size - 1))));
 660 }
 661
 662 /* Wait up to 10 ms for buffered write completion */
 663 static int
 664 falcon_spi_wait_write(struct efx_nic *efx, const struct falcon_spi_device *spi)
 665 {
 666         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
 667         u8 status;
 668         int rc;
 669
 670         for (;;) {
 671                 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
 672                                     &status, sizeof(status));
 673                 if (rc)
 674                         return rc;
 675                 if (!(status & SPI_STATUS_NRDY))
 676                         return 0;
 677                 if (time_after_eq(jiffies, timeout)) {
 678                         netif_err(efx, hw, efx->net_dev,
 679                                   "SPI write timeout on device %d"
 680                                   " last status=0x%02x\n",
 681                                   spi->device_id, status);
 682                         return -ETIMEDOUT;
 683                 }
 684                 schedule_timeout_uninterruptible(1);
 685         }
 686 }
 687
 688 static int
 689 falcon_spi_write(struct efx_nic *efx, const struct falcon_spi_device *spi,
 690                  loff_t start, size_t len, size_t *retlen, const u8 *buffer)
 691 {
 692         u8 verify_buffer[FALCON_SPI_MAX_LEN];
 693         size_t block_len, pos = 0;
 694         unsigned int command;
 695         int rc = 0;
 696
 697         while (pos < len) {
 698                 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
 699                 if (rc)
 700                         break;
 701
 702                 block_len = min(len - pos,
 703                                 falcon_spi_write_limit(spi, start + pos));
 704                 command = falcon_spi_munge_command(spi, SPI_WRITE, start + pos);
 705                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 706                                     buffer + pos, NULL, block_len);
 707                 if (rc)
 708                         break;
 709
 710                 rc = falcon_spi_wait_write(efx, spi);
 711                 if (rc)
 712                         break;
 713
 714                 command = falcon_spi_munge_command(spi, SPI_READ, start + pos);
 715                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 716                                     NULL, verify_buffer, block_len);
 717                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
 718                         rc = -EIO;
 719                         break;
 720                 }
 721
 722                 pos += block_len;
 723
 724                 /* Avoid locking up the system */
 725                 cond_resched();
 726                 if (signal_pending(current)) {
 727                         rc = -EINTR;
 728                         break;
 729                 }
 730         }
 731
 732         if (retlen)
 733                 *retlen = pos;
 734         return rc;
 735 }
 736
 737 static int
 738 falcon_spi_slow_wait(struct falcon_mtd_partition *part, bool uninterruptible)
 739 {
 740         const struct falcon_spi_device *spi = part->spi;
 741         struct efx_nic *efx = part->common.mtd.priv;
 742         u8 status;
 743         int rc, i;
 744
 745         /* Wait up to 4s for flash/EEPROM to finish a slow operation. */
 746         for (i = 0; i < 40; i++) {
 747                 __set_current_state(uninterruptible ?
 748                                     TASK_UNINTERRUPTIBLE : TASK_INTERRUPTIBLE);
 749                 schedule_timeout(HZ / 10);
 750                 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
 751                                     &status, sizeof(status));
 752                 if (rc)
 753                         return rc;
 754                 if (!(status & SPI_STATUS_NRDY))
 755                         return 0;
 756                 if (signal_pending(current))
 757                         return -EINTR;
 758         }
 759         pr_err("%s: timed out waiting for %s\n",
 760                part->common.name, part->common.dev_type_name);
 761         return -ETIMEDOUT;
 762 }
 763
 764 static int
 765 falcon_spi_unlock(struct efx_nic *efx, const struct falcon_spi_device *spi)
 766 {
 767         const u8 unlock_mask = (SPI_STATUS_BP2 | SPI_STATUS_BP1 |
 768                                 SPI_STATUS_BP0);
 769         u8 status;
 770         int rc;
 771
 772         rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
 773                             &status, sizeof(status));
 774         if (rc)
 775                 return rc;
 776
 777         if (!(status & unlock_mask))
 778                 return 0; /* already unlocked */
 779
 780         rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
 781         if (rc)
 782                 return rc;
 783         rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0);
 784         if (rc)
 785                 return rc;
 786
 787         status &= ~unlock_mask;
 788         rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status,
 789                             NULL, sizeof(status));
 790         if (rc)
 791                 return rc;
 792         rc = falcon_spi_wait_write(efx, spi);
 793         if (rc)
 794                 return rc;
 795
 796         return 0;
 797 }
 798
 799 #define FALCON_SPI_VERIFY_BUF_LEN 16
 800
 801 static int
 802 falcon_spi_erase(struct falcon_mtd_partition *part, loff_t start, size_t len)
 803 {
 804         const struct falcon_spi_device *spi = part->spi;
 805         struct efx_nic *efx = part->common.mtd.priv;
 806         unsigned pos, block_len;
 807         u8 empty[FALCON_SPI_VERIFY_BUF_LEN];
 808         u8 buffer[FALCON_SPI_VERIFY_BUF_LEN];
 809         int rc;
 810
 811         if (len != spi->erase_size)
 812                 return -EINVAL;
 813
 814         if (spi->erase_command == 0)
 815                 return -EOPNOTSUPP;
 816
 817         rc = falcon_spi_unlock(efx, spi);
 818         if (rc)
 819                 return rc;
 820         rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
 821         if (rc)
 822                 return rc;
 823         rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL,
 824                             NULL, 0);
 825         if (rc)
 826                 return rc;
 827         rc = falcon_spi_slow_wait(part, false);
 828
 829         /* Verify the entire region has been wiped */
 830         memset(empty, 0xff, sizeof(empty));
 831         for (pos = 0; pos < len; pos += block_len) {
 832                 block_len = min(len - pos, sizeof(buffer));
 833                 rc = falcon_spi_read(efx, spi, start + pos, block_len,
 834                                      NULL, buffer);
 835                 if (rc)
 836                         return rc;
 837                 if (memcmp(empty, buffer, block_len))
 838                         return -EIO;
 839
 840                 /* Avoid locking up the system */
 841                 cond_resched();
 842                 if (signal_pending(current))
 843                         return -EINTR;
 844         }
 845
 846         return rc;
 847 }
 848
 849 static void falcon_mtd_rename(struct efx_mtd_partition *part)
 850 {
 851         struct efx_nic *efx = part->mtd.priv;
 852
 853         snprintf(part->name, sizeof(part->name), "%s %s",
 854                  efx->name, part->type_name);
 855 }
 856
 857 static int falcon_mtd_read(struct mtd_info *mtd, loff_t start,
 858                            size_t len, size_t *retlen, u8 *buffer)
 859 {
 860         struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
 861         struct efx_nic *efx = mtd->priv;
 862         struct falcon_nic_data *nic_data = efx->nic_data;
 863         int rc;
 864
 865         rc = mutex_lock_interruptible(&nic_data->spi_lock);
 866         if (rc)
 867                 return rc;
 868         rc = falcon_spi_read(efx, part->spi, part->offset + start,
 869                              len, retlen, buffer);
 870         mutex_unlock(&nic_data->spi_lock);
 871         return rc;
 872 }
 873
 874 static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
 875 {
 876         struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
 877         struct efx_nic *efx = mtd->priv;
 878         struct falcon_nic_data *nic_data = efx->nic_data;
 879         int rc;
 880
 881         rc = mutex_lock_interruptible(&nic_data->spi_lock);
 882         if (rc)
 883                 return rc;
 884         rc = falcon_spi_erase(part, part->offset + start, len);
 885         mutex_unlock(&nic_data->spi_lock);
 886         return rc;
 887 }
 888
 889 static int falcon_mtd_write(struct mtd_info *mtd, loff_t start,
 890                             size_t len, size_t *retlen, const u8 *buffer)
 891 {
 892         struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
 893         struct efx_nic *efx = mtd->priv;
 894         struct falcon_nic_data *nic_data = efx->nic_data;
 895         int rc;
 896
 897         rc = mutex_lock_interruptible(&nic_data->spi_lock);
 898         if (rc)
 899                 return rc;
 900         rc = falcon_spi_write(efx, part->spi, part->offset + start,
 901                               len, retlen, buffer);
 902         mutex_unlock(&nic_data->spi_lock);
 903         return rc;
 904 }
 905
 906 static int falcon_mtd_sync(struct mtd_info *mtd)
 907 {
 908         struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
 909         struct efx_nic *efx = mtd->priv;
 910         struct falcon_nic_data *nic_data = efx->nic_data;
 911         int rc;
 912
 913         mutex_lock(&nic_data->spi_lock);
 914         rc = falcon_spi_slow_wait(part, true);
 915         mutex_unlock(&nic_data->spi_lock);
 916         return rc;
 917 }
 918
 919 static int falcon_mtd_probe(struct efx_nic *efx)
 920 {
 921         struct falcon_nic_data *nic_data = efx->nic_data;
 922         struct falcon_mtd_partition *parts;
 923         struct falcon_spi_device *spi;
 924         size_t n_parts;
 925         int rc = -ENODEV;
 926
 927         ASSERT_RTNL();
 928
 929         /* Allocate space for maximum number of partitions */
 930         parts = kcalloc(2, sizeof(*parts), GFP_KERNEL);
 931         if (!parts)
 932                 return -ENOMEM;
 933         n_parts = 0;
 934
 935         spi = &nic_data->spi_flash;
 936         if (falcon_spi_present(spi) && spi->size > FALCON_FLASH_BOOTCODE_START) {
 937                 parts[n_parts].spi = spi;
 938                 parts[n_parts].offset = FALCON_FLASH_BOOTCODE_START;
 939                 parts[n_parts].common.dev_type_name = "flash";
 940                 parts[n_parts].common.type_name = "sfc_flash_bootrom";
 941                 parts[n_parts].common.mtd.type = MTD_NORFLASH;
 942                 parts[n_parts].common.mtd.flags = MTD_CAP_NORFLASH;
 943                 parts[n_parts].common.mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START;
 944                 parts[n_parts].common.mtd.erasesize = spi->erase_size;
 945                 n_parts++;
 946         }
 947
 948         spi = &nic_data->spi_eeprom;
 949         if (falcon_spi_present(spi) && spi->size > FALCON_EEPROM_BOOTCONFIG_START) {
 950                 parts[n_parts].spi = spi;
 951                 parts[n_parts].offset = FALCON_EEPROM_BOOTCONFIG_START;
 952                 parts[n_parts].common.dev_type_name = "EEPROM";
 953                 parts[n_parts].common.type_name = "sfc_bootconfig";
 954                 parts[n_parts].common.mtd.type = MTD_RAM;
 955                 parts[n_parts].common.mtd.flags = MTD_CAP_RAM;
 956                 parts[n_parts].common.mtd.size =
 957                         min(spi->size, FALCON_EEPROM_BOOTCONFIG_END) -
 958                         FALCON_EEPROM_BOOTCONFIG_START;
 959                 parts[n_parts].common.mtd.erasesize = spi->erase_size;
 960                 n_parts++;
 961         }
 962
 963         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
 964         if (rc)
 965                 kfree(parts);
 966         return rc;
 967 }
 968
 969 #endif /* CONFIG_SFC_MTD */
 970
 971 /**************************************************************************
 972  *
 973  * XMAC operations
 974  *
 975  **************************************************************************
 976  */
 977
 978 /* Configure the XAUI driver that is an output from Falcon */
 979 static void falcon_setup_xaui(struct efx_nic *efx)
 980 {
 981         efx_oword_t sdctl, txdrv;
 982
 983         /* Move the XAUI into low power, unless there is no PHY, in
 984          * which case the XAUI will have to drive a cable. */
 985         if (efx->phy_type == PHY_TYPE_NONE)
 986                 return;
 987
 988         efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
 989         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
 990         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
 991         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
 992         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
 993         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
 994         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
 995         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
 996         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
 997         efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
 998
 999         EFX_POPULATE_OWORD_8(txdrv,
1000                              FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
1001                              FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
1002                              FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
1003                              FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
1004                              FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
1005                              FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
1006                              FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
1007                              FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
1008         efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
1009 }
1010
1011 int falcon_reset_xaui(struct efx_nic *efx)
1012 {
1013         struct falcon_nic_data *nic_data = efx->nic_data;
1014         efx_oword_t reg;
1015         int count;
1016
1017         /* Don't fetch MAC statistics over an XMAC reset */
1018         WARN_ON(nic_data->stats_disable_count == 0);
1019
1020         /* Start reset sequence */
1021         EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
1022         efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);
1023
1024         /* Wait up to 10 ms for completion, then reinitialise */
1025         for (count = 0; count < 1000; count++) {
1026                 efx_reado(efx, &reg, FR_AB_XX_PWR_RST);
1027                 if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
1028                     EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
1029                         falcon_setup_xaui(efx);
1030                         return 0;
1031                 }
1032                 udelay(10);
1033         }
1034         netif_err(efx, hw, efx->net_dev,
1035                   "timed out waiting for XAUI/XGXS reset\n");
1036         return -ETIMEDOUT;
1037 }
1038
1039 static void falcon_ack_status_intr(struct efx_nic *efx)
1040 {
1041         struct falcon_nic_data *nic_data = efx->nic_data;
1042         efx_oword_t reg;
1043
1044         if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
1045                 return;
1046
1047         /* We expect xgmii faults if the wireside link is down */
1048         if (!efx->link_state.up)
1049                 return;
1050
1051         /* We can only use this interrupt to signal the negative edge of
1052          * xaui_align [we have to poll the positive edge]. */
1053         if (nic_data->xmac_poll_required)
1054                 return;
1055
1056         efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);
1057 }
1058
1059 static bool falcon_xgxs_link_ok(struct efx_nic *efx)
1060 {
1061         efx_oword_t reg;
1062         bool align_done, link_ok = false;
1063         int sync_status;
1064
1065         /* Read link status */
1066         efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
1067
1068         align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
1069         sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
1070         if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
1071                 link_ok = true;
1072
1073         /* Clear link status ready for next read */
1074         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
1075         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
1076         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
1077         efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
1078
1079         return link_ok;
1080 }
1081
1082 static bool falcon_xmac_link_ok(struct efx_nic *efx)
1083 {
1084         /*
1085          * Check MAC's XGXS link status except when using XGMII loopback
1086          * which bypasses the XGXS block.
1087          * If possible, check PHY's XGXS link status except when using
1088          * MAC loopback.
1089          */
1090         return (efx->loopback_mode == LOOPBACK_XGMII ||
1091                 falcon_xgxs_link_ok(efx)) &&
1092                 (!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
1093                  LOOPBACK_INTERNAL(efx) ||
1094                  efx_mdio_phyxgxs_lane_sync(efx));
1095 }
1096
1097 static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
1098 {
1099         unsigned int max_frame_len;
1100         efx_oword_t reg;
1101         bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
1102         bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
1103
1104         /* Configure MAC  - cut-thru mode is hard wired on */
1105         EFX_POPULATE_OWORD_3(reg,
1106                              FRF_AB_XM_RX_JUMBO_MODE, 1,
1107                              FRF_AB_XM_TX_STAT_EN, 1,
1108                              FRF_AB_XM_RX_STAT_EN, 1);
1109         efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1110
1111         /* Configure TX */
1112         EFX_POPULATE_OWORD_6(reg,
1113                              FRF_AB_XM_TXEN, 1,
1114                              FRF_AB_XM_TX_PRMBL, 1,
1115                              FRF_AB_XM_AUTO_PAD, 1,
1116                              FRF_AB_XM_TXCRC, 1,
1117                              FRF_AB_XM_FCNTL, tx_fc,
1118                              FRF_AB_XM_IPG, 0x3);
1119         efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);
1120
1121         /* Configure RX */
1122         EFX_POPULATE_OWORD_5(reg,
1123                              FRF_AB_XM_RXEN, 1,
1124                              FRF_AB_XM_AUTO_DEPAD, 0,
1125                              FRF_AB_XM_ACPT_ALL_MCAST, 1,
1126                              FRF_AB_XM_ACPT_ALL_UCAST, !efx->unicast_filter,
1127                              FRF_AB_XM_PASS_CRC_ERR, 1);
1128         efx_writeo(efx, &reg, FR_AB_XM_RX_CFG);
1129
1130         /* Set frame length */
1131         max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
1132         EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
1133         efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
1134         EFX_POPULATE_OWORD_2(reg,
1135                              FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
1136                              FRF_AB_XM_TX_JUMBO_MODE, 1);
1137         efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);
1138
1139         EFX_POPULATE_OWORD_2(reg,
1140                              FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
1141                              FRF_AB_XM_DIS_FCNTL, !rx_fc);
1142         efx_writeo(efx, &reg, FR_AB_XM_FC);
1143
1144         /* Set MAC address */
1145         memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
1146         efx_writeo(efx, &reg, FR_AB_XM_ADR_LO);
1147         memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
1148         efx_writeo(efx, &reg, FR_AB_XM_ADR_HI);
1149 }
1150
1151 static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
1152 {
1153         efx_oword_t reg;
1154         bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
1155         bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
1156         bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
1157         bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
1158
1159         /* XGXS block is flaky and will need to be reset if moving
1160          * into our out of XGMII, XGXS or XAUI loopbacks. */
1161         efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
1162         old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
1163         old_xgmii_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
1164
1165         efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
1166         old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
1167
1168         /* The PHY driver may have turned XAUI off */
1169         if ((xgxs_loopback != old_xgxs_loopback) ||
1170             (xaui_loopback != old_xaui_loopback) ||
1171             (xgmii_loopback != old_xgmii_loopback))
1172                 falcon_reset_xaui(efx);
1173
1174         efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
1175         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
1176                             (xgxs_loopback || xaui_loopback) ?
1177                             FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
1178         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
1179         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
1180         efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
1181
1182         efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
1183         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
1184         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
1185         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
1186         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
1187         efx_writeo(efx, &reg, FR_AB_XX_SD_CTL);
1188 }
1189
1190
1191 /* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
1192 static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries)
1193 {
1194         bool mac_up = falcon_xmac_link_ok(efx);
1195
1196         if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
1197             efx_phy_mode_disabled(efx->phy_mode))
1198                 /* XAUI link is expected to be down */
1199                 return mac_up;
1200
1201         falcon_stop_nic_stats(efx);
1202
1203         while (!mac_up && tries) {
1204                 netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n");
1205                 falcon_reset_xaui(efx);
1206                 udelay(200);
1207
1208                 mac_up = falcon_xmac_link_ok(efx);
1209                 --tries;
1210         }
1211
1212         falcon_start_nic_stats(efx);
1213
1214         return mac_up;
1215 }
1216
1217 static bool falcon_xmac_check_fault(struct efx_nic *efx)
1218 {
1219         return !falcon_xmac_link_ok_retry(efx, 5);
1220 }
1221
1222 static int falcon_reconfigure_xmac(struct efx_nic *efx)
1223 {
1224         struct falcon_nic_data *nic_data = efx->nic_data;
1225
1226         efx_farch_filter_sync_rx_mode(efx);
1227
1228         falcon_reconfigure_xgxs_core(efx);
1229         falcon_reconfigure_xmac_core(efx);
1230
1231         falcon_reconfigure_mac_wrapper(efx);
1232
1233         nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
1234         falcon_ack_status_intr(efx);
1235
1236         return 0;
1237 }
1238
1239 static void falcon_poll_xmac(struct efx_nic *efx)
1240 {
1241         struct falcon_nic_data *nic_data = efx->nic_data;
1242
1243         /* We expect xgmii faults if the wireside link is down */
1244         if (!efx->link_state.up || !nic_data->xmac_poll_required)
1245                 return;
1246
1247         nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
1248         falcon_ack_status_intr(efx);
1249 }
1250
1251 /**************************************************************************
1252  *
1253  * MAC wrapper
1254  *
1255  **************************************************************************
1256  */
1257
1258 static void falcon_push_multicast_hash(struct efx_nic *efx)
1259 {
1260         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
1261
1262         WARN_ON(!mutex_is_locked(&efx->mac_lock));
1263
1264         efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
1265         efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
1266 }
1267
1268 static void falcon_reset_macs(struct efx_nic *efx)
1269 {
1270         struct falcon_nic_data *nic_data = efx->nic_data;
1271         efx_oword_t reg, mac_ctrl;
1272         int count;
1273
1274         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
1275                 /* It's not safe to use GLB_CTL_REG to reset the
1276                  * macs, so instead use the internal MAC resets
1277                  */
1278                 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1279                 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1280
1281                 for (count = 0; count < 10000; count++) {
1282                         efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
1283                         if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1284                             0)
1285                                 return;
1286                         udelay(10);
1287                 }
1288
1289                 netif_err(efx, hw, efx->net_dev,
1290                           "timed out waiting for XMAC core reset\n");
1291         }
1292
1293         /* Mac stats will fail whist the TX fifo is draining */
1294         WARN_ON(nic_data->stats_disable_count == 0);
1295
1296         efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1297         EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
1298         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1299
1300         efx_reado(efx, &reg, FR_AB_GLB_CTL);
1301         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1302         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1303         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1304         efx_writeo(efx, &reg, FR_AB_GLB_CTL);
1305
1306         count = 0;
1307         while (1) {
1308                 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1309                 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1310                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1311                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1312                         netif_dbg(efx, hw, efx->net_dev,
1313                                   "Completed MAC reset after %d loops\n",
1314                                   count);
1315                         break;
1316                 }
1317                 if (count > 20) {
1318                         netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
1319                         break;
1320                 }
1321                 count++;
1322                 udelay(10);
1323         }
1324
1325         /* Ensure the correct MAC is selected before statistics
1326          * are re-enabled by the caller */
1327         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1328
1329         falcon_setup_xaui(efx);
1330 }
1331
1332 static void falcon_drain_tx_fifo(struct efx_nic *efx)
1333 {
1334         efx_oword_t reg;
1335
1336         if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
1337             (efx->loopback_mode != LOOPBACK_NONE))
1338                 return;
1339
1340         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1341         /* There is no point in draining more than once */
1342         if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1343                 return;
1344
1345         falcon_reset_macs(efx);
1346 }
1347
1348 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1349 {
1350         efx_oword_t reg;
1351
1352         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1353                 return;
1354
1355         /* Isolate the MAC -> RX */
1356         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1357         EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1358         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1359
1360         /* Isolate TX -> MAC */
1361         falcon_drain_tx_fifo(efx);
1362 }
1363
1364 static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1365 {
1366         struct efx_link_state *link_state = &efx->link_state;
1367         efx_oword_t reg;
1368         int link_speed, isolate;
1369
1370         isolate = !!ACCESS_ONCE(efx->reset_pending);
1371
1372         switch (link_state->speed) {
1373         case 10000: link_speed = 3; break;
1374         case 1000:  link_speed = 2; break;
1375         case 100:   link_speed = 1; break;
1376         default:    link_speed = 0; break;
1377         }
1378
1379         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1380          * as advertised.  Disable to ensure packets are not
1381          * indefinitely held and TX queue can be flushed at any point
1382          * while the link is down. */
1383         EFX_POPULATE_OWORD_5(reg,
1384                              FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1385                              FRF_AB_MAC_BCAD_ACPT, 1,
1386                              FRF_AB_MAC_UC_PROM, !efx->unicast_filter,
1387                              FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1388                              FRF_AB_MAC_SPEED, link_speed);
1389         /* On B0, MAC backpressure can be disabled and packets get
1390          * discarded. */
1391         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1392                 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1393                                     !link_state->up || isolate);
1394         }
1395
1396         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1397
1398         /* Restore the multicast hash registers. */
1399         falcon_push_multicast_hash(efx);
1400
1401         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1402         /* Enable XOFF signal from RX FIFO (we enabled it during NIC
1403          * initialisation but it may read back as 0) */
1404         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1405         /* Unisolate the MAC -> RX */
1406         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1407                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
1408         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1409 }
1410
1411 static void falcon_stats_request(struct efx_nic *efx)
1412 {
1413         struct falcon_nic_data *nic_data = efx->nic_data;
1414         efx_oword_t reg;
1415
1416         WARN_ON(nic_data->stats_pending);
1417         WARN_ON(nic_data->stats_disable_count);
1418
1419         FALCON_XMAC_STATS_DMA_FLAG(efx) = 0;
1420         nic_data->stats_pending = true;
1421         wmb(); /* ensure done flag is clear */
1422
1423         /* Initiate DMA transfer of stats */
1424         EFX_POPULATE_OWORD_2(reg,
1425                              FRF_AB_MAC_STAT_DMA_CMD, 1,
1426                              FRF_AB_MAC_STAT_DMA_ADR,
1427                              efx->stats_buffer.dma_addr);
1428         efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
1429
1430         mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
1431 }
1432
1433 static void falcon_stats_complete(struct efx_nic *efx)
1434 {
1435         struct falcon_nic_data *nic_data = efx->nic_data;
1436
1437         if (!nic_data->stats_pending)
1438                 return;
1439
1440         nic_data->stats_pending = false;
1441         if (FALCON_XMAC_STATS_DMA_FLAG(efx)) {
1442                 rmb(); /* read the done flag before the stats */
1443                 efx_nic_update_stats(falcon_stat_desc, FALCON_STAT_COUNT,
1444                                      falcon_stat_mask, nic_data->stats,
1445                                      efx->stats_buffer.addr, true);
1446         } else {
1447                 netif_err(efx, hw, efx->net_dev,
1448                           "timed out waiting for statistics\n");
1449         }
1450 }
1451
1452 static void falcon_stats_timer_func(unsigned long context)
1453 {
1454         struct efx_nic *efx = (struct efx_nic *)context;
1455         struct falcon_nic_data *nic_data = efx->nic_data;
1456
1457         spin_lock(&efx->stats_lock);
1458
1459         falcon_stats_complete(efx);
1460         if (nic_data->stats_disable_count == 0)
1461                 falcon_stats_request(efx);
1462
1463         spin_unlock(&efx->stats_lock);
1464 }
1465
1466 static bool falcon_loopback_link_poll(struct efx_nic *efx)
1467 {
1468         struct efx_link_state old_state = efx->link_state;
1469
1470         WARN_ON(!mutex_is_locked(&efx->mac_lock));
1471         WARN_ON(!LOOPBACK_INTERNAL(efx));
1472
1473         efx->link_state.fd = true;
1474         efx->link_state.fc = efx->wanted_fc;
1475         efx->link_state.up = true;
1476         efx->link_state.speed = 10000;
1477
1478         return !efx_link_state_equal(&efx->link_state, &old_state);
1479 }
1480
1481 static int falcon_reconfigure_port(struct efx_nic *efx)
1482 {
1483         int rc;
1484
1485         WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
1486
1487         /* Poll the PHY link state *before* reconfiguring it. This means we
1488          * will pick up the correct speed (in loopback) to select the correct
1489          * MAC.
1490          */
1491         if (LOOPBACK_INTERNAL(efx))
1492                 falcon_loopback_link_poll(efx);
1493         else
1494                 efx->phy_op->poll(efx);
1495
1496         falcon_stop_nic_stats(efx);
1497         falcon_deconfigure_mac_wrapper(efx);
1498
1499         falcon_reset_macs(efx);
1500
1501         efx->phy_op->reconfigure(efx);
1502         rc = falcon_reconfigure_xmac(efx);
1503         BUG_ON(rc);
1504
1505         falcon_start_nic_stats(efx);
1506
1507         /* Synchronise efx->link_state with the kernel */
1508         efx_link_status_changed(efx);
1509
1510         return 0;
1511 }
1512
1513 /* TX flow control may automatically turn itself off if the link
1514  * partner (intermittently) stops responding to pause frames. There
1515  * isn't any indication that this has happened, so the best we do is
1516  * leave it up to the user to spot this and fix it by cycling transmit
1517  * flow control on this end.
1518  */
1519
1520 static void falcon_a1_prepare_enable_fc_tx(struct efx_nic *efx)
1521 {
1522         /* Schedule a reset to recover */
1523         efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
1524 }
1525
1526 static void falcon_b0_prepare_enable_fc_tx(struct efx_nic *efx)
1527 {
1528         /* Recover by resetting the EM block */
1529         falcon_stop_nic_stats(efx);
1530         falcon_drain_tx_fifo(efx);
1531         falcon_reconfigure_xmac(efx);
1532         falcon_start_nic_stats(efx);
1533 }
1534
1535 /**************************************************************************
1536  *
1537  * PHY access via GMII
1538  *
1539  **************************************************************************
1540  */
1541
1542 /* Wait for GMII access to complete */
1543 static int falcon_gmii_wait(struct efx_nic *efx)
1544 {
1545         efx_oword_t md_stat;
1546         int count;
1547
1548         /* wait up to 50ms - taken max from datasheet */
1549         for (count = 0; count < 5000; count++) {
1550                 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
1551                 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
1552                         if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
1553                             EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
1554                                 netif_err(efx, hw, efx->net_dev,
1555                                           "error from GMII access "
1556                                           EFX_OWORD_FMT"\n",
1557                                           EFX_OWORD_VAL(md_stat));
1558                                 return -EIO;
1559                         }
1560                         return 0;
1561                 }
1562                 udelay(10);
1563         }
1564         netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
1565         return -ETIMEDOUT;
1566 }
1567
1568 /* Write an MDIO register of a PHY connected to Falcon. */
1569 static int falcon_mdio_write(struct net_device *net_dev,
1570                              int prtad, int devad, u16 addr, u16 value)
1571 {
1572         struct efx_nic *efx = netdev_priv(net_dev);
1573         struct falcon_nic_data *nic_data = efx->nic_data;
1574         efx_oword_t reg;
1575         int rc;
1576
1577         netif_vdbg(efx, hw, efx->net_dev,
1578                    "writing MDIO %d register %d.%d with 0x%04x\n",
1579                     prtad, devad, addr, value);
1580
1581         mutex_lock(&nic_data->mdio_lock);
1582
1583         /* Check MDIO not currently being accessed */
1584         rc = falcon_gmii_wait(efx);
1585         if (rc)
1586                 goto out;
1587
1588         /* Write the address/ID register */
1589         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
1590         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
1591
1592         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
1593                              FRF_AB_MD_DEV_ADR, devad);
1594         efx_writeo(efx, &reg, FR_AB_MD_ID);
1595
1596         /* Write data */
1597         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
1598         efx_writeo(efx, &reg, FR_AB_MD_TXD);
1599
1600         EFX_POPULATE_OWORD_2(reg,
1601                              FRF_AB_MD_WRC, 1,
1602                              FRF_AB_MD_GC, 0);
1603         efx_writeo(efx, &reg, FR_AB_MD_CS);
1604
1605         /* Wait for data to be written */
1606         rc = falcon_gmii_wait(efx);
1607         if (rc) {
1608                 /* Abort the write operation */
1609                 EFX_POPULATE_OWORD_2(reg,
1610                                      FRF_AB_MD_WRC, 0,
1611                                      FRF_AB_MD_GC, 1);
1612                 efx_writeo(efx, &reg, FR_AB_MD_CS);
1613                 udelay(10);
1614         }
1615
1616 out:
1617         mutex_unlock(&nic_data->mdio_lock);
1618         return rc;
1619 }
1620
1621 /* Read an MDIO register of a PHY connected to Falcon. */
1622 static int falcon_mdio_read(struct net_device *net_dev,
1623                             int prtad, int devad, u16 addr)
1624 {
1625         struct efx_nic *efx = netdev_priv(net_dev);
1626         struct falcon_nic_data *nic_data = efx->nic_data;
1627         efx_oword_t reg;
1628         int rc;
1629
1630         mutex_lock(&nic_data->mdio_lock);
1631
1632         /* Check MDIO not currently being accessed */
1633         rc = falcon_gmii_wait(efx);
1634         if (rc)
1635                 goto out;
1636
1637         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
1638         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
1639
1640         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
1641                              FRF_AB_MD_DEV_ADR, devad);
1642         efx_writeo(efx, &reg, FR_AB_MD_ID);
1643
1644         /* Request data to be read */
1645         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
1646         efx_writeo(efx, &reg, FR_AB_MD_CS);
1647
1648         /* Wait for data to become available */
1649         rc = falcon_gmii_wait(efx);
1650         if (rc == 0) {
1651                 efx_reado(efx, &reg, FR_AB_MD_RXD);
1652                 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
1653                 netif_vdbg(efx, hw, efx->net_dev,
1654                            "read from MDIO %d register %d.%d, got %04x\n",
1655                            prtad, devad, addr, rc);
1656         } else {
1657                 /* Abort the read operation */
1658                 EFX_POPULATE_OWORD_2(reg,
1659                                      FRF_AB_MD_RIC, 0,
1660                                      FRF_AB_MD_GC, 1);
1661                 efx_writeo(efx, &reg, FR_AB_MD_CS);
1662
1663                 netif_dbg(efx, hw, efx->net_dev,
1664                           "read from MDIO %d register %d.%d, got error %d\n",
1665                           prtad, devad, addr, rc);
1666         }
1667
1668 out:
1669         mutex_unlock(&nic_data->mdio_lock);
1670         return rc;
1671 }
1672
1673 /* This call is responsible for hooking in the MAC and PHY operations */
1674 static int falcon_probe_port(struct efx_nic *efx)
1675 {
1676         struct falcon_nic_data *nic_data = efx->nic_data;
1677         int rc;
1678
1679         switch (efx->phy_type) {
1680         case PHY_TYPE_SFX7101:
1681                 efx->phy_op = &falcon_sfx7101_phy_ops;
1682                 break;
1683         case PHY_TYPE_QT2022C2:
1684         case PHY_TYPE_QT2025C:
1685                 efx->phy_op = &falcon_qt202x_phy_ops;
1686                 break;
1687         case PHY_TYPE_TXC43128:
1688                 efx->phy_op = &falcon_txc_phy_ops;
1689                 break;
1690         default:
1691                 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
1692                           efx->phy_type);
1693                 return -ENODEV;
1694         }
1695
1696         /* Fill out MDIO structure and loopback modes */
1697         mutex_init(&nic_data->mdio_lock);
1698         efx->mdio.mdio_read = falcon_mdio_read;
1699         efx->mdio.mdio_write = falcon_mdio_write;
1700         rc = efx->phy_op->probe(efx);
1701         if (rc != 0)
1702                 return rc;
1703
1704         /* Initial assumption */
1705         efx->link_state.speed = 10000;
1706         efx->link_state.fd = true;
1707
1708         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
1709         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1710                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
1711         else
1712                 efx->wanted_fc = EFX_FC_RX;
1713         if (efx->mdio.mmds & MDIO_DEVS_AN)
1714                 efx->wanted_fc |= EFX_FC_AUTO;
1715
1716         /* Allocate buffer for stats */
1717         rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
1718                                   FALCON_MAC_STATS_SIZE, GFP_KERNEL);
1719         if (rc)
1720                 return rc;
1721         netif_dbg(efx, probe, efx->net_dev,
1722                   "stats buffer at %llx (virt %p phys %llx)\n",
1723                   (u64)efx->stats_buffer.dma_addr,
1724                   efx->stats_buffer.addr,
1725                   (u64)virt_to_phys(efx->stats_buffer.addr));
1726
1727         return 0;
1728 }
1729
1730 static void falcon_remove_port(struct efx_nic *efx)
1731 {
1732         efx->phy_op->remove(efx);
1733         efx_nic_free_buffer(efx, &efx->stats_buffer);
1734 }
1735
1736 /* Global events are basically PHY events */
1737 static bool
1738 falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
1739 {
1740         struct efx_nic *efx = channel->efx;
1741         struct falcon_nic_data *nic_data = efx->nic_data;
1742
1743         if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
1744             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
1745             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR))
1746                 /* Ignored */
1747                 return true;
1748
1749         if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) &&
1750             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
1751                 nic_data->xmac_poll_required = true;
1752                 return true;
1753         }
1754
1755         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
1756             EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
1757             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
1758                 netif_err(efx, rx_err, efx->net_dev,
1759                           "channel %d seen global RX_RESET event. Resetting.\n",
1760                           channel->channel);
1761
1762                 atomic_inc(&efx->rx_reset);
1763                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1764                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1765                 return true;
1766         }
1767
1768         return false;
1769 }
1770
1771 /**************************************************************************
1772  *
1773  * Falcon test code
1774  *
1775  **************************************************************************/
1776
1777 static int
1778 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
1779 {
1780         struct falcon_nic_data *nic_data = efx->nic_data;
1781         struct falcon_nvconfig *nvconfig;
1782         struct falcon_spi_device *spi;
1783         void *region;
1784         int rc, magic_num, struct_ver;
1785         __le16 *word, *limit;
1786         u32 csum;
1787
1788         if (falcon_spi_present(&nic_data->spi_flash))
1789                 spi = &nic_data->spi_flash;
1790         else if (falcon_spi_present(&nic_data->spi_eeprom))
1791                 spi = &nic_data->spi_eeprom;
1792         else
1793                 return -EINVAL;
1794
1795         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
1796         if (!region)
1797                 return -ENOMEM;
1798         nvconfig = region + FALCON_NVCONFIG_OFFSET;
1799
1800         mutex_lock(&nic_data->spi_lock);
1801         rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
1802         mutex_unlock(&nic_data->spi_lock);
1803         if (rc) {
1804                 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
1805                           falcon_spi_present(&nic_data->spi_flash) ?
1806                           "flash" : "EEPROM");
1807                 rc = -EIO;
1808                 goto out;
1809         }
1810
1811         magic_num = le16_to_cpu(nvconfig->board_magic_num);
1812         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
1813
1814         rc = -EINVAL;
1815         if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
1816                 netif_err(efx, hw, efx->net_dev,
1817                           "NVRAM bad magic 0x%x\n", magic_num);
1818                 goto out;
1819         }
1820         if (struct_ver < 2) {
1821                 netif_err(efx, hw, efx->net_dev,
1822                           "NVRAM has ancient version 0x%x\n", struct_ver);
1823                 goto out;
1824         } else if (struct_ver < 4) {
1825                 word = &nvconfig->board_magic_num;
1826                 limit = (__le16 *) (nvconfig + 1);
1827         } else {
1828                 word = region;
1829                 limit = region + FALCON_NVCONFIG_END;
1830         }
1831         for (csum = 0; word < limit; ++word)
1832                 csum += le16_to_cpu(*word);
1833
1834         if (~csum & 0xffff) {
1835                 netif_err(efx, hw, efx->net_dev,
1836                           "NVRAM has incorrect checksum\n");
1837                 goto out;
1838         }
1839
1840         rc = 0;
1841         if (nvconfig_out)
1842                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
1843
1844  out:
1845         kfree(region);
1846         return rc;
1847 }
1848
1849 static int falcon_test_nvram(struct efx_nic *efx)
1850 {
1851         return falcon_read_nvram(efx, NULL);
1852 }
1853
1854 static const struct efx_farch_register_test falcon_b0_register_tests[] = {
1855         { FR_AZ_ADR_REGION,
1856           EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1857         { FR_AZ_RX_CFG,
1858           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1859         { FR_AZ_TX_CFG,
1860           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1861         { FR_AZ_TX_RESERVED,
1862           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1863         { FR_AB_MAC_CTRL,
1864           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1865         { FR_AZ_SRM_TX_DC_CFG,
1866           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1867         { FR_AZ_RX_DC_CFG,
1868           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1869         { FR_AZ_RX_DC_PF_WM,
1870           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1871         { FR_BZ_DP_CTRL,
1872           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1873         { FR_AB_GM_CFG2,
1874           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1875         { FR_AB_GMF_CFG0,
1876           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1877         { FR_AB_XM_GLB_CFG,
1878           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1879         { FR_AB_XM_TX_CFG,
1880           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1881         { FR_AB_XM_RX_CFG,
1882           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1883         { FR_AB_XM_RX_PARAM,
1884           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1885         { FR_AB_XM_FC,
1886           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1887         { FR_AB_XM_ADR_LO,
1888           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1889         { FR_AB_XX_SD_CTL,
1890           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1891 };
1892
1893 static int
1894 falcon_b0_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
1895 {
1896         enum reset_type reset_method = RESET_TYPE_INVISIBLE;
1897         int rc, rc2;
1898
1899         mutex_lock(&efx->mac_lock);
1900         if (efx->loopback_modes) {
1901                 /* We need the 312 clock from the PHY to test the XMAC
1902                  * registers, so move into XGMII loopback if available */
1903                 if (efx->loopback_modes & (1 << LOOPBACK_XGMII))
1904                         efx->loopback_mode = LOOPBACK_XGMII;
1905                 else
1906                         efx->loopback_mode = __ffs(efx->loopback_modes);
1907         }
1908         __efx_reconfigure_port(efx);
1909         mutex_unlock(&efx->mac_lock);
1910
1911         efx_reset_down(efx, reset_method);
1912
1913         tests->registers =
1914                 efx_farch_test_registers(efx, falcon_b0_register_tests,
1915                                          ARRAY_SIZE(falcon_b0_register_tests))
1916                 ? -1 : 1;
1917
1918         rc = falcon_reset_hw(efx, reset_method);
1919         rc2 = efx_reset_up(efx, reset_method, rc == 0);
1920         return rc ? rc : rc2;
1921 }
1922
1923 /**************************************************************************
1924  *
1925  * Device reset
1926  *
1927  **************************************************************************
1928  */
1929
1930 static enum reset_type falcon_map_reset_reason(enum reset_type reason)
1931 {
1932         switch (reason) {
1933         case RESET_TYPE_RX_RECOVERY:
1934         case RESET_TYPE_DMA_ERROR:
1935         case RESET_TYPE_TX_SKIP:
1936                 /* These can occasionally occur due to hardware bugs.
1937                  * We try to reset without disrupting the link.
1938                  */
1939                 return RESET_TYPE_INVISIBLE;
1940         default:
1941                 return RESET_TYPE_ALL;
1942         }
1943 }
1944
1945 static int falcon_map_reset_flags(u32 *flags)
1946 {
1947         enum {
1948                 FALCON_RESET_INVISIBLE = (ETH_RESET_DMA | ETH_RESET_FILTER |
1949                                           ETH_RESET_OFFLOAD | ETH_RESET_MAC),
1950                 FALCON_RESET_ALL = FALCON_RESET_INVISIBLE | ETH_RESET_PHY,
1951                 FALCON_RESET_WORLD = FALCON_RESET_ALL | ETH_RESET_IRQ,
1952         };
1953
1954         if ((*flags & FALCON_RESET_WORLD) == FALCON_RESET_WORLD) {
1955                 *flags &= ~FALCON_RESET_WORLD;
1956                 return RESET_TYPE_WORLD;
1957         }
1958
1959         if ((*flags & FALCON_RESET_ALL) == FALCON_RESET_ALL) {
1960                 *flags &= ~FALCON_RESET_ALL;
1961                 return RESET_TYPE_ALL;
1962         }
1963
1964         if ((*flags & FALCON_RESET_INVISIBLE) == FALCON_RESET_INVISIBLE) {
1965                 *flags &= ~FALCON_RESET_INVISIBLE;
1966                 return RESET_TYPE_INVISIBLE;
1967         }
1968
1969         return -EINVAL;
1970 }
1971
1972 /* Resets NIC to known state.  This routine must be called in process
1973  * context and is allowed to sleep. */
1974 static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1975 {
1976         struct falcon_nic_data *nic_data = efx->nic_data;
1977         efx_oword_t glb_ctl_reg_ker;
1978         int rc;
1979
1980         netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1981                   RESET_TYPE(method));
1982
1983         /* Initiate device reset */
1984         if (method == RESET_TYPE_WORLD) {
1985                 rc = pci_save_state(efx->pci_dev);
1986                 if (rc) {
1987                         netif_err(efx, drv, efx->net_dev,
1988                                   "failed to backup PCI state of primary "
1989                                   "function prior to hardware reset\n");
1990                         goto fail1;
1991                 }
1992                 if (efx_nic_is_dual_func(efx)) {
1993                         rc = pci_save_state(nic_data->pci_dev2);
1994                         if (rc) {
1995                                 netif_err(efx, drv, efx->net_dev,
1996                                           "failed to backup PCI state of "
1997                                           "secondary function prior to "
1998                                           "hardware reset\n");
1999                                 goto fail2;
2000                         }
2001                 }
2002
2003                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2004                                      FRF_AB_EXT_PHY_RST_DUR,
2005                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
2006                                      FRF_AB_SWRST, 1);
2007         } else {
2008                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2009                                      /* exclude PHY from "invisible" reset */
2010                                      FRF_AB_EXT_PHY_RST_CTL,
2011                                      method == RESET_TYPE_INVISIBLE,
2012                                      /* exclude EEPROM/flash and PCIe */
2013                                      FRF_AB_PCIE_CORE_RST_CTL, 1,
2014                                      FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2015                                      FRF_AB_PCIE_SD_RST_CTL, 1,
2016                                      FRF_AB_EE_RST_CTL, 1,
2017                                      FRF_AB_EXT_PHY_RST_DUR,
2018                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
2019                                      FRF_AB_SWRST, 1);
2020         }
2021         efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2022
2023         netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
2024         schedule_timeout_uninterruptible(HZ / 20);
2025
2026         /* Restore PCI configuration if needed */
2027         if (method == RESET_TYPE_WORLD) {
2028                 if (efx_nic_is_dual_func(efx))
2029                         pci_restore_state(nic_data->pci_dev2);
2030                 pci_restore_state(efx->pci_dev);
2031                 netif_dbg(efx, drv, efx->net_dev,
2032                           "successfully restored PCI config\n");
2033         }
2034
2035         /* Assert that reset complete */
2036         efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2037         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2038                 rc = -ETIMEDOUT;
2039                 netif_err(efx, hw, efx->net_dev,
2040                           "timed out waiting for hardware reset\n");
2041                 goto fail3;
2042         }
2043         netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
2044
2045         return 0;
2046
2047         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2048 fail2:
2049         pci_restore_state(efx->pci_dev);
2050 fail1:
2051 fail3:
2052         return rc;
2053 }
2054
2055 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2056 {
2057         struct falcon_nic_data *nic_data = efx->nic_data;
2058         int rc;
2059
2060         mutex_lock(&nic_data->spi_lock);
2061         rc = __falcon_reset_hw(efx, method);
2062         mutex_unlock(&nic_data->spi_lock);
2063
2064         return rc;
2065 }
2066
2067 static void falcon_monitor(struct efx_nic *efx)
2068 {
2069         bool link_changed;
2070         int rc;
2071
2072         BUG_ON(!mutex_is_locked(&efx->mac_lock));
2073
2074         rc = falcon_board(efx)->type->monitor(efx);
2075         if (rc) {
2076                 netif_err(efx, hw, efx->net_dev,
2077                           "Board sensor %s; shutting down PHY\n",
2078                           (rc == -ERANGE) ? "reported fault" : "failed");
2079                 efx->phy_mode |= PHY_MODE_LOW_POWER;
2080                 rc = __efx_reconfigure_port(efx);
2081                 WARN_ON(rc);
2082         }
2083
2084         if (LOOPBACK_INTERNAL(efx))
2085                 link_changed = falcon_loopback_link_poll(efx);
2086         else
2087                 link_changed = efx->phy_op->poll(efx);
2088
2089         if (link_changed) {
2090                 falcon_stop_nic_stats(efx);
2091                 falcon_deconfigure_mac_wrapper(efx);
2092
2093                 falcon_reset_macs(efx);
2094                 rc = falcon_reconfigure_xmac(efx);
2095                 BUG_ON(rc);
2096
2097                 falcon_start_nic_stats(efx);
2098
2099                 efx_link_status_changed(efx);
2100         }
2101
2102         falcon_poll_xmac(efx);
2103 }
2104
2105 /* Zeroes out the SRAM contents.  This routine must be called in
2106  * process context and is allowed to sleep.
2107  */
2108 static int falcon_reset_sram(struct efx_nic *efx)
2109 {
2110         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2111         int count;
2112
2113         /* Set the SRAM wake/sleep GPIO appropriately. */
2114         efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2115         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2116         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2117         efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2118
2119         /* Initiate SRAM reset */
2120         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2121                              FRF_AZ_SRM_INIT_EN, 1,
2122                              FRF_AZ_SRM_NB_SZ, 0);
2123         efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2124
2125         /* Wait for SRAM reset to complete */
2126         count = 0;
2127         do {
2128                 netif_dbg(efx, hw, efx->net_dev,
2129                           "waiting for SRAM reset (attempt %d)...\n", count);
2130
2131                 /* SRAM reset is slow; expect around 16ms */
2132                 schedule_timeout_uninterruptible(HZ / 50);
2133
2134                 /* Check for reset complete */
2135                 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2136                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2137                         netif_dbg(efx, hw, efx->net_dev,
2138                                   "SRAM reset complete\n");
2139
2140                         return 0;
2141                 }
2142         } while (++count < 20); /* wait up to 0.4 sec */
2143
2144         netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
2145         return -ETIMEDOUT;
2146 }
2147
2148 static void falcon_spi_device_init(struct efx_nic *efx,
2149                                   struct falcon_spi_device *spi_device,
2150                                   unsigned int device_id, u32 device_type)
2151 {
2152         if (device_type != 0) {
2153                 spi_device->device_id = device_id;
2154                 spi_device->size =
2155                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2156                 spi_device->addr_len =
2157                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2158                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2159                                              spi_device->addr_len == 1);
2160                 spi_device->erase_command =
2161                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2162                 spi_device->erase_size =
2163                         1 << SPI_DEV_TYPE_FIELD(device_type,
2164                                                 SPI_DEV_TYPE_ERASE_SIZE);
2165                 spi_device->block_size =
2166                         1 << SPI_DEV_TYPE_FIELD(device_type,
2167                                                 SPI_DEV_TYPE_BLOCK_SIZE);
2168         } else {
2169                 spi_device->size = 0;
2170         }
2171 }
2172
2173 /* Extract non-volatile configuration */
2174 static int falcon_probe_nvconfig(struct efx_nic *efx)
2175 {
2176         struct falcon_nic_data *nic_data = efx->nic_data;
2177         struct falcon_nvconfig *nvconfig;
2178         int rc;
2179
2180         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2181         if (!nvconfig)
2182                 return -ENOMEM;
2183
2184         rc = falcon_read_nvram(efx, nvconfig);
2185         if (rc)
2186                 goto out;
2187
2188         efx->phy_type = nvconfig->board_v2.port0_phy_type;
2189         efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr;
2190
2191         if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2192                 falcon_spi_device_init(
2193                         efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2194                         le32_to_cpu(nvconfig->board_v3
2195                                     .spi_device_type[FFE_AB_SPI_DEVICE_FLASH]));
2196                 falcon_spi_device_init(
2197                         efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2198                         le32_to_cpu(nvconfig->board_v3
2199                                     .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM]));
2200         }
2201
2202         /* Read the MAC addresses */
2203         ether_addr_copy(efx->net_dev->perm_addr, nvconfig->mac_address[0]);
2204
2205         netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
2206                   efx->phy_type, efx->mdio.prtad);
2207
2208         rc = falcon_probe_board(efx,
2209                                 le16_to_cpu(nvconfig->board_v2.board_revision));
2210 out:
2211         kfree(nvconfig);
2212         return rc;
2213 }
2214
2215 static int falcon_dimension_resources(struct efx_nic *efx)
2216 {
2217         efx->rx_dc_base = 0x20000;
2218         efx->tx_dc_base = 0x26000;
2219         return 0;
2220 }
2221
2222 /* Probe all SPI devices on the NIC */
2223 static void falcon_probe_spi_devices(struct efx_nic *efx)
2224 {
2225         struct falcon_nic_data *nic_data = efx->nic_data;
2226         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2227         int boot_dev;
2228
2229         efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2230         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2231         efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2232
2233         if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2234                 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2235                             FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2236                 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
2237                           boot_dev == FFE_AB_SPI_DEVICE_FLASH ?
2238                           "flash" : "EEPROM");
2239         } else {
2240                 /* Disable VPD and set clock dividers to safe
2241                  * values for initial programming. */
2242                 boot_dev = -1;
2243                 netif_dbg(efx, probe, efx->net_dev,
2244                           "Booted from internal ASIC settings;"
2245                           " setting SPI config\n");
2246                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2247                                      /* 125 MHz / 7 ~= 20 MHz */
2248                                      FRF_AB_EE_SF_CLOCK_DIV, 7,
2249                                      /* 125 MHz / 63 ~= 2 MHz */
2250                                      FRF_AB_EE_EE_CLOCK_DIV, 63);
2251                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2252         }
2253
2254         mutex_init(&nic_data->spi_lock);
2255
2256         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2257                 falcon_spi_device_init(efx, &nic_data->spi_flash,
2258                                        FFE_AB_SPI_DEVICE_FLASH,
2259                                        default_flash_type);
2260         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2261                 falcon_spi_device_init(efx, &nic_data->spi_eeprom,
2262                                        FFE_AB_SPI_DEVICE_EEPROM,
2263                                        large_eeprom_type);
2264 }
2265
2266 static unsigned int falcon_a1_mem_map_size(struct efx_nic *efx)
2267 {
2268         return 0x20000;
2269 }
2270
2271 static unsigned int falcon_b0_mem_map_size(struct efx_nic *efx)
2272 {
2273         /* Map everything up to and including the RSS indirection table.
2274          * The PCI core takes care of mapping the MSI-X tables.
2275          */
2276         return FR_BZ_RX_INDIRECTION_TBL +
2277                 FR_BZ_RX_INDIRECTION_TBL_STEP * FR_BZ_RX_INDIRECTION_TBL_ROWS;
2278 }
2279
2280 static int falcon_probe_nic(struct efx_nic *efx)
2281 {
2282         struct falcon_nic_data *nic_data;
2283         struct falcon_board *board;
2284         int rc;
2285
2286         efx->primary = efx; /* only one usable function per controller */
2287
2288         /* Allocate storage for hardware specific data */
2289         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2290         if (!nic_data)
2291                 return -ENOMEM;
2292         efx->nic_data = nic_data;
2293
2294         rc = -ENODEV;
2295
2296         if (efx_farch_fpga_ver(efx) != 0) {
2297                 netif_err(efx, probe, efx->net_dev,
2298                           "Falcon FPGA not supported\n");
2299                 goto fail1;
2300         }
2301
2302         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2303                 efx_oword_t nic_stat;
2304                 struct pci_dev *dev;
2305                 u8 pci_rev = efx->pci_dev->revision;
2306
2307                 if ((pci_rev == 0xff) || (pci_rev == 0)) {
2308                         netif_err(efx, probe, efx->net_dev,
2309                                   "Falcon rev A0 not supported\n");
2310                         goto fail1;
2311                 }
2312                 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2313                 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
2314                         netif_err(efx, probe, efx->net_dev,
2315                                   "Falcon rev A1 1G not supported\n");
2316                         goto fail1;
2317                 }
2318                 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2319                         netif_err(efx, probe, efx->net_dev,
2320                                   "Falcon rev A1 PCI-X not supported\n");
2321                         goto fail1;
2322                 }
2323
2324                 dev = pci_dev_get(efx->pci_dev);
2325                 while ((dev = pci_get_device(PCI_VENDOR_ID_SOLARFLARE,
2326                                              PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1,
2327                                              dev))) {
2328                         if (dev->bus == efx->pci_dev->bus &&
2329                             dev->devfn == efx->pci_dev->devfn + 1) {
2330                                 nic_data->pci_dev2 = dev;
2331                                 break;
2332                         }
2333                 }
2334                 if (!nic_data->pci_dev2) {
2335                         netif_err(efx, probe, efx->net_dev,
2336                                   "failed to find secondary function\n");
2337                         rc = -ENODEV;
2338                         goto fail2;
2339                 }
2340         }
2341
2342         /* Now we can reset the NIC */
2343         rc = __falcon_reset_hw(efx, RESET_TYPE_ALL);
2344         if (rc) {
2345                 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
2346                 goto fail3;
2347         }
2348
2349         /* Allocate memory for INT_KER */
2350         rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
2351                                   GFP_KERNEL);
2352         if (rc)
2353                 goto fail4;
2354         BUG_ON(efx->irq_status.dma_addr & 0x0f);
2355
2356         netif_dbg(efx, probe, efx->net_dev,
2357                   "INT_KER at %llx (virt %p phys %llx)\n",
2358                   (u64)efx->irq_status.dma_addr,
2359                   efx->irq_status.addr,
2360                   (u64)virt_to_phys(efx->irq_status.addr));
2361
2362         falcon_probe_spi_devices(efx);
2363
2364         /* Read in the non-volatile configuration */
2365         rc = falcon_probe_nvconfig(efx);
2366         if (rc) {
2367                 if (rc == -EINVAL)
2368                         netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n");
2369                 goto fail5;
2370         }
2371
2372         efx->max_channels = (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ? 4 :
2373                              EFX_MAX_CHANNELS);
2374         efx->max_tx_channels = efx->max_channels;
2375         efx->timer_quantum_ns = 4968; /* 621 cycles */
2376
2377         /* Initialise I2C adapter */
2378         board = falcon_board(efx);
2379         board->i2c_adap.owner = THIS_MODULE;
2380         board->i2c_data = falcon_i2c_bit_operations;
2381         board->i2c_data.data = efx;
2382         board->i2c_adap.algo_data = &board->i2c_data;
2383         board->i2c_adap.dev.parent = &efx->pci_dev->dev;
2384         strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
2385                 sizeof(board->i2c_adap.name));
2386         rc = i2c_bit_add_bus(&board->i2c_adap);
2387         if (rc)
2388                 goto fail5;
2389
2390         rc = falcon_board(efx)->type->init(efx);
2391         if (rc) {
2392                 netif_err(efx, probe, efx->net_dev,
2393                           "failed to initialise board\n");
2394                 goto fail6;
2395         }
2396
2397         nic_data->stats_disable_count = 1;
2398         setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
2399                     (unsigned long)efx);
2400
2401         return 0;
2402
2403  fail6:
2404         i2c_del_adapter(&board->i2c_adap);
2405         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2406  fail5:
2407         efx_nic_free_buffer(efx, &efx->irq_status);
2408  fail4:
2409  fail3:
2410         if (nic_data->pci_dev2) {
2411                 pci_dev_put(nic_data->pci_dev2);
2412                 nic_data->pci_dev2 = NULL;
2413         }
2414  fail2:
2415  fail1:
2416         kfree(efx->nic_data);
2417         return rc;
2418 }
2419
2420 static void falcon_init_rx_cfg(struct efx_nic *efx)
2421 {
2422         /* RX control FIFO thresholds (32 entries) */
2423         const unsigned ctrl_xon_thr = 20;
2424         const unsigned ctrl_xoff_thr = 25;
2425         efx_oword_t reg;
2426
2427         efx_reado(efx, &reg, FR_AZ_RX_CFG);
2428         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2429                 /* Data FIFO size is 5.5K.  The RX DMA engine only
2430                  * supports scattering for user-mode queues, but will
2431                  * split DMA writes at intervals of RX_USR_BUF_SIZE
2432                  * (32-byte units) even for kernel-mode queues.  We
2433                  * set it to be so large that that never happens.
2434                  */
2435                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2436                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2437                                     (3 * 4096) >> 5);
2438                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8);
2439                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8);
2440                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2441                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2442         } else {
2443                 /* Data FIFO size is 80K; register fields moved */
2444                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2445                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2446                                     EFX_RX_USR_BUF_SIZE >> 5);
2447                 /* Send XON and XOFF at ~3 * max MTU away from empty/full */
2448                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8);
2449                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8);
2450                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2451                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2452                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2453
2454                 /* Enable hash insertion. This is broken for the
2455                  * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
2456                  * IPv4 hashes. */
2457                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
2458                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);
2459                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);
2460         }
2461         /* Always enable XOFF signal from RX FIFO.  We enable
2462          * or disable transmission of pause frames at the MAC. */
2463         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
2464         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2465 }
2466
2467 /* This call performs hardware-specific global initialisation, such as
2468  * defining the descriptor cache sizes and number of RSS channels.
2469  * It does not set up any buffers, descriptor rings or event queues.
2470  */
2471 static int falcon_init_nic(struct efx_nic *efx)
2472 {
2473         efx_oword_t temp;
2474         int rc;
2475
2476         /* Use on-chip SRAM */
2477         efx_reado(efx, &temp, FR_AB_NIC_STAT);
2478         EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2479         efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2480
2481         rc = falcon_reset_sram(efx);
2482         if (rc)
2483                 return rc;
2484
2485         /* Clear the parity enables on the TX data fifos as
2486          * they produce false parity errors because of timing issues
2487          */
2488         if (EFX_WORKAROUND_5129(efx)) {
2489                 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
2490                 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
2491                 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
2492         }
2493
2494         if (EFX_WORKAROUND_7244(efx)) {
2495                 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
2496                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
2497                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
2498                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
2499                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
2500                 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
2501         }
2502
2503         /* XXX This is documented only for Falcon A0/A1 */
2504         /* Setup RX.  Wait for descriptor is broken and must
2505          * be disabled.  RXDP recovery shouldn't be needed, but is.
2506          */
2507         efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
2508         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
2509         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
2510         if (EFX_WORKAROUND_5583(efx))
2511                 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
2512         efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
2513
2514         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2515          * descriptors (which is bad).
2516          */
2517         efx_reado(efx, &temp, FR_AZ_TX_CFG);
2518         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
2519         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
2520
2521         falcon_init_rx_cfg(efx);
2522
2523         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
2524                 falcon_b0_rx_push_rss_config(efx, false, efx->rx_indir_table);
2525
2526                 /* Set destination of both TX and RX Flush events */
2527                 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
2528                 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
2529         }
2530
2531         efx_farch_init_common(efx);
2532
2533         return 0;
2534 }
2535
2536 static void falcon_remove_nic(struct efx_nic *efx)
2537 {
2538         struct falcon_nic_data *nic_data = efx->nic_data;
2539         struct falcon_board *board = falcon_board(efx);
2540
2541         board->type->fini(efx);
2542
2543         /* Remove I2C adapter and clear it in preparation for a retry */
2544         i2c_del_adapter(&board->i2c_adap);
2545         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2546
2547         efx_nic_free_buffer(efx, &efx->irq_status);
2548
2549         __falcon_reset_hw(efx, RESET_TYPE_ALL);
2550
2551         /* Release the second function after the reset */
2552         if (nic_data->pci_dev2) {
2553                 pci_dev_put(nic_data->pci_dev2);
2554                 nic_data->pci_dev2 = NULL;
2555         }
2556
2557         /* Tear down the private nic state */
2558         kfree(efx->nic_data);
2559         efx->nic_data = NULL;
2560 }
2561
2562 static size_t falcon_describe_nic_stats(struct efx_nic *efx, u8 *names)
2563 {
2564         return efx_nic_describe_stats(falcon_stat_desc, FALCON_STAT_COUNT,
2565                                       falcon_stat_mask, names);
2566 }
2567
2568 static size_t falcon_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
2569                                       struct rtnl_link_stats64 *core_stats)
2570 {
2571         struct falcon_nic_data *nic_data = efx->nic_data;
2572         u64 *stats = nic_data->stats;
2573         efx_oword_t cnt;
2574
2575         if (!nic_data->stats_disable_count) {
2576                 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
2577                 stats[FALCON_STAT_rx_nodesc_drop_cnt] +=
2578                         EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
2579
2580                 if (nic_data->stats_pending &&
2581                     FALCON_XMAC_STATS_DMA_FLAG(efx)) {
2582                         nic_data->stats_pending = false;
2583                         rmb(); /* read the done flag before the stats */
2584                         efx_nic_update_stats(
2585                                 falcon_stat_desc, FALCON_STAT_COUNT,
2586                                 falcon_stat_mask,
2587                                 stats, efx->stats_buffer.addr, true);
2588                 }
2589
2590                 /* Update derived statistic */
2591                 efx_update_diff_stat(&stats[FALCON_STAT_rx_bad_bytes],
2592                                      stats[FALCON_STAT_rx_bytes] -
2593                                      stats[FALCON_STAT_rx_good_bytes] -
2594                                      stats[FALCON_STAT_rx_control] * 64);
2595                 efx_update_sw_stats(efx, stats);
2596         }
2597
2598         if (full_stats)
2599                 memcpy(full_stats, stats, sizeof(u64) * FALCON_STAT_COUNT);
2600
2601         if (core_stats) {
2602                 core_stats->rx_packets = stats[FALCON_STAT_rx_packets];
2603                 core_stats->tx_packets = stats[FALCON_STAT_tx_packets];
2604                 core_stats->rx_bytes = stats[FALCON_STAT_rx_bytes];
2605                 core_stats->tx_bytes = stats[FALCON_STAT_tx_bytes];
2606                 core_stats->rx_dropped = stats[FALCON_STAT_rx_nodesc_drop_cnt] +
2607                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
2608                                          stats[GENERIC_STAT_rx_noskb_drops];
2609                 core_stats->multicast = stats[FALCON_STAT_rx_multicast];
2610                 core_stats->rx_length_errors =
2611                         stats[FALCON_STAT_rx_gtjumbo] +
2612                         stats[FALCON_STAT_rx_length_error];
2613                 core_stats->rx_crc_errors = stats[FALCON_STAT_rx_bad];
2614                 core_stats->rx_frame_errors = stats[FALCON_STAT_rx_align_error];
2615                 core_stats->rx_fifo_errors = stats[FALCON_STAT_rx_overflow];
2616
2617                 core_stats->rx_errors = (core_stats->rx_length_errors +
2618                                          core_stats->rx_crc_errors +
2619                                          core_stats->rx_frame_errors +
2620                                          stats[FALCON_STAT_rx_symbol_error]);
2621         }
2622
2623         return FALCON_STAT_COUNT;
2624 }
2625
2626 void falcon_start_nic_stats(struct efx_nic *efx)
2627 {
2628         struct falcon_nic_data *nic_data = efx->nic_data;
2629
2630         spin_lock_bh(&efx->stats_lock);
2631         if (--nic_data->stats_disable_count == 0)
2632                 falcon_stats_request(efx);
2633         spin_unlock_bh(&efx->stats_lock);
2634 }
2635
2636 /* We don't acutally pull stats on falcon. Wait 10ms so that
2637  * they arrive when we call this just after start_stats
2638  */
2639 static void falcon_pull_nic_stats(struct efx_nic *efx)
2640 {
2641         msleep(10);
2642 }
2643
2644 void falcon_stop_nic_stats(struct efx_nic *efx)
2645 {
2646         struct falcon_nic_data *nic_data = efx->nic_data;
2647         int i;
2648
2649         might_sleep();
2650
2651         spin_lock_bh(&efx->stats_lock);
2652         ++nic_data->stats_disable_count;
2653         spin_unlock_bh(&efx->stats_lock);
2654
2655         del_timer_sync(&nic_data->stats_timer);
2656
2657         /* Wait enough time for the most recent transfer to
2658          * complete. */
2659         for (i = 0; i < 4 && nic_data->stats_pending; i++) {
2660                 if (FALCON_XMAC_STATS_DMA_FLAG(efx))
2661                         break;
2662                 msleep(1);
2663         }
2664
2665         spin_lock_bh(&efx->stats_lock);
2666         falcon_stats_complete(efx);
2667         spin_unlock_bh(&efx->stats_lock);
2668 }
2669
2670 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
2671 {
2672         falcon_board(efx)->type->set_id_led(efx, mode);
2673 }
2674
2675 /**************************************************************************
2676  *
2677  * Wake on LAN
2678  *
2679  **************************************************************************
2680  */
2681
2682 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2683 {
2684         wol->supported = 0;
2685         wol->wolopts = 0;
2686         memset(&wol->sopass, 0, sizeof(wol->sopass));
2687 }
2688
2689 static int falcon_set_wol(struct efx_nic *efx, u32 type)
2690 {
2691         if (type != 0)
2692                 return -EINVAL;
2693         return 0;
2694 }
2695
2696 /**************************************************************************
2697  *
2698  * Revision-dependent attributes used by efx.c and nic.c
2699  *
2700  **************************************************************************
2701  */
2702
2703 const struct efx_nic_type falcon_a1_nic_type = {
2704         .is_vf = false,
2705         .mem_bar = EFX_MEM_BAR,
2706         .mem_map_size = falcon_a1_mem_map_size,
2707         .probe = falcon_probe_nic,
2708         .remove = falcon_remove_nic,
2709         .init = falcon_init_nic,
2710         .dimension_resources = falcon_dimension_resources,
2711         .fini = falcon_irq_ack_a1,
2712         .monitor = falcon_monitor,
2713         .map_reset_reason = falcon_map_reset_reason,
2714         .map_reset_flags = falcon_map_reset_flags,
2715         .reset = falcon_reset_hw,
2716         .probe_port = falcon_probe_port,
2717         .remove_port = falcon_remove_port,
2718         .handle_global_event = falcon_handle_global_event,
2719         .fini_dmaq = efx_farch_fini_dmaq,
2720         .prepare_flush = falcon_prepare_flush,
2721         .finish_flush = efx_port_dummy_op_void,
2722         .prepare_flr = efx_port_dummy_op_void,
2723         .finish_flr = efx_farch_finish_flr,
2724         .describe_stats = falcon_describe_nic_stats,
2725         .update_stats = falcon_update_nic_stats,
2726         .start_stats = falcon_start_nic_stats,
2727         .pull_stats = falcon_pull_nic_stats,
2728         .stop_stats = falcon_stop_nic_stats,
2729         .set_id_led = falcon_set_id_led,
2730         .push_irq_moderation = falcon_push_irq_moderation,
2731         .reconfigure_port = falcon_reconfigure_port,
2732         .prepare_enable_fc_tx = falcon_a1_prepare_enable_fc_tx,
2733         .reconfigure_mac = falcon_reconfigure_xmac,
2734         .check_mac_fault = falcon_xmac_check_fault,
2735         .get_wol = falcon_get_wol,
2736         .set_wol = falcon_set_wol,
2737         .resume_wol = efx_port_dummy_op_void,
2738         .test_nvram = falcon_test_nvram,
2739         .irq_enable_master = efx_farch_irq_enable_master,
2740         .irq_test_generate = efx_farch_irq_test_generate,
2741         .irq_disable_non_ev = efx_farch_irq_disable_master,
2742         .irq_handle_msi = efx_farch_msi_interrupt,
2743         .irq_handle_legacy = falcon_legacy_interrupt_a1,
2744         .tx_probe = efx_farch_tx_probe,
2745         .tx_init = efx_farch_tx_init,
2746         .tx_remove = efx_farch_tx_remove,
2747         .tx_write = efx_farch_tx_write,
2748         .rx_push_rss_config = dummy_rx_push_rss_config,
2749         .rx_probe = efx_farch_rx_probe,
2750         .rx_init = efx_farch_rx_init,
2751         .rx_remove = efx_farch_rx_remove,
2752         .rx_write = efx_farch_rx_write,
2753         .rx_defer_refill = efx_farch_rx_defer_refill,
2754         .ev_probe = efx_farch_ev_probe,
2755         .ev_init = efx_farch_ev_init,
2756         .ev_fini = efx_farch_ev_fini,
2757         .ev_remove = efx_farch_ev_remove,
2758         .ev_process = efx_farch_ev_process,
2759         .ev_read_ack = efx_farch_ev_read_ack,
2760         .ev_test_generate = efx_farch_ev_test_generate,
2761
2762         /* We don't expose the filter table on Falcon A1 as it is not
2763          * mapped into function 0, but these implementations still
2764          * work with a degenerate case of all tables set to size 0.
2765          */
2766         .filter_table_probe = efx_farch_filter_table_probe,
2767         .filter_table_restore = efx_farch_filter_table_restore,
2768         .filter_table_remove = efx_farch_filter_table_remove,
2769         .filter_insert = efx_farch_filter_insert,
2770         .filter_remove_safe = efx_farch_filter_remove_safe,
2771         .filter_get_safe = efx_farch_filter_get_safe,
2772         .filter_clear_rx = efx_farch_filter_clear_rx,
2773         .filter_count_rx_used = efx_farch_filter_count_rx_used,
2774         .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
2775         .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
2776
2777 #ifdef CONFIG_SFC_MTD
2778         .mtd_probe = falcon_mtd_probe,
2779         .mtd_rename = falcon_mtd_rename,
2780         .mtd_read = falcon_mtd_read,
2781         .mtd_erase = falcon_mtd_erase,
2782         .mtd_write = falcon_mtd_write,
2783         .mtd_sync = falcon_mtd_sync,
2784 #endif
2785
2786         .revision = EFX_REV_FALCON_A1,
2787         .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
2788         .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
2789         .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
2790         .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
2791         .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
2792         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
2793         .rx_buffer_padding = 0x24,
2794         .can_rx_scatter = false,
2795         .max_interrupt_mode = EFX_INT_MODE_MSI,
2796         .timer_period_max =  1 << FRF_AB_TC_TIMER_VAL_WIDTH,
2797         .offload_features = NETIF_F_IP_CSUM,
2798         .mcdi_max_ver = -1,
2799 };
2800
2801 const struct efx_nic_type falcon_b0_nic_type = {
2802         .is_vf = false,
2803         .mem_bar = EFX_MEM_BAR,
2804         .mem_map_size = falcon_b0_mem_map_size,
2805         .probe = falcon_probe_nic,
2806         .remove = falcon_remove_nic,
2807         .init = falcon_init_nic,
2808         .dimension_resources = falcon_dimension_resources,
2809         .fini = efx_port_dummy_op_void,
2810         .monitor = falcon_monitor,
2811         .map_reset_reason = falcon_map_reset_reason,
2812         .map_reset_flags = falcon_map_reset_flags,
2813         .reset = falcon_reset_hw,
2814         .probe_port = falcon_probe_port,
2815         .remove_port = falcon_remove_port,
2816         .handle_global_event = falcon_handle_global_event,
2817         .fini_dmaq = efx_farch_fini_dmaq,
2818         .prepare_flush = falcon_prepare_flush,
2819         .finish_flush = efx_port_dummy_op_void,
2820         .prepare_flr = efx_port_dummy_op_void,
2821         .finish_flr = efx_farch_finish_flr,
2822         .describe_stats = falcon_describe_nic_stats,
2823         .update_stats = falcon_update_nic_stats,
2824         .start_stats = falcon_start_nic_stats,
2825         .pull_stats = falcon_pull_nic_stats,
2826         .stop_stats = falcon_stop_nic_stats,
2827         .set_id_led = falcon_set_id_led,
2828         .push_irq_moderation = falcon_push_irq_moderation,
2829         .reconfigure_port = falcon_reconfigure_port,
2830         .prepare_enable_fc_tx = falcon_b0_prepare_enable_fc_tx,
2831         .reconfigure_mac = falcon_reconfigure_xmac,
2832         .check_mac_fault = falcon_xmac_check_fault,
2833         .get_wol = falcon_get_wol,
2834         .set_wol = falcon_set_wol,
2835         .resume_wol = efx_port_dummy_op_void,
2836         .test_chip = falcon_b0_test_chip,
2837         .test_nvram = falcon_test_nvram,
2838         .irq_enable_master = efx_farch_irq_enable_master,
2839         .irq_test_generate = efx_farch_irq_test_generate,
2840         .irq_disable_non_ev = efx_farch_irq_disable_master,
2841         .irq_handle_msi = efx_farch_msi_interrupt,
2842         .irq_handle_legacy = efx_farch_legacy_interrupt,
2843         .tx_probe = efx_farch_tx_probe,
2844         .tx_init = efx_farch_tx_init,
2845         .tx_remove = efx_farch_tx_remove,
2846         .tx_write = efx_farch_tx_write,
2847         .rx_push_rss_config = falcon_b0_rx_push_rss_config,
2848         .rx_probe = efx_farch_rx_probe,
2849         .rx_init = efx_farch_rx_init,
2850         .rx_remove = efx_farch_rx_remove,
2851         .rx_write = efx_farch_rx_write,
2852         .rx_defer_refill = efx_farch_rx_defer_refill,
2853         .ev_probe = efx_farch_ev_probe,
2854         .ev_init = efx_farch_ev_init,
2855         .ev_fini = efx_farch_ev_fini,
2856         .ev_remove = efx_farch_ev_remove,
2857         .ev_process = efx_farch_ev_process,
2858         .ev_read_ack = efx_farch_ev_read_ack,
2859         .ev_test_generate = efx_farch_ev_test_generate,
2860         .filter_table_probe = efx_farch_filter_table_probe,
2861         .filter_table_restore = efx_farch_filter_table_restore,
2862         .filter_table_remove = efx_farch_filter_table_remove,
2863         .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
2864         .filter_insert = efx_farch_filter_insert,
2865         .filter_remove_safe = efx_farch_filter_remove_safe,
2866         .filter_get_safe = efx_farch_filter_get_safe,
2867         .filter_clear_rx = efx_farch_filter_clear_rx,
2868         .filter_count_rx_used = efx_farch_filter_count_rx_used,
2869         .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
2870         .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
2871 #ifdef CONFIG_RFS_ACCEL
2872         .filter_rfs_insert = efx_farch_filter_rfs_insert,
2873         .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
2874 #endif
2875 #ifdef CONFIG_SFC_MTD
2876         .mtd_probe = falcon_mtd_probe,
2877         .mtd_rename = falcon_mtd_rename,
2878         .mtd_read = falcon_mtd_read,
2879         .mtd_erase = falcon_mtd_erase,
2880         .mtd_write = falcon_mtd_write,
2881         .mtd_sync = falcon_mtd_sync,
2882 #endif
2883
2884         .revision = EFX_REV_FALCON_B0,
2885         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
2886         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
2887         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
2888         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
2889         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
2890         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
2891         .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
2892         .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
2893         .rx_buffer_padding = 0,
2894         .can_rx_scatter = true,
2895         .max_interrupt_mode = EFX_INT_MODE_MSIX,
2896         .timer_period_max =  1 << FRF_AB_TC_TIMER_VAL_WIDTH,
2897         .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
2898         .mcdi_max_ver = -1,
2899         .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
2900 };