kernel/drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include <linux/in.h>
  19 #include <linux/jhash.h>
  20 #include <linux/wait.h>
  21 #include <linux/workqueue.h>
  22
  23 /* Hardware control for EF10 architecture including 'Huntington'. */
  24
  25 #define EFX_EF10_DRVGEN_EV              7
  26 enum {
  27         EFX_EF10_TEST = 1,
  28         EFX_EF10_REFILL,
  29 };
  30
  31 /* The reserved RSS context value */
  32 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  33
  34 /* The filter table(s) are managed by firmware and we have write-only
  35  * access.  When removing filters we must identify them to the
  36  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  37  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  38  * be able to tell in advance whether a requested insertion will
  39  * replace an existing filter.  Therefore we maintain a software hash
  40  * table, which should be at least as large as the hardware hash
  41  * table.
  42  *
  43  * Huntington has a single 8K filter table shared between all filter
  44  * types and both ports.
  45  */
  46 #define HUNT_FILTER_TBL_ROWS 8192
  47
  48 struct efx_ef10_filter_table {
  49 /* The RX match field masks supported by this fw & hw, in order of priority */
  50         enum efx_filter_match_flags rx_match_flags[
  51                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
  52         unsigned int rx_match_count;
  53
  54         struct {
  55                 unsigned long spec;     /* pointer to spec plus flag bits */
  56 /* BUSY flag indicates that an update is in progress.  AUTO_OLD is
  57  * used to mark and sweep MAC filters for the device address lists.
  58  */
  59 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
  60 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
  61 #define EFX_EF10_FILTER_FLAGS           3UL
  62                 u64 handle;             /* firmware handle */
  63         } *entry;
  64         wait_queue_head_t waitq;
  65 /* Shadow of net_device address lists, guarded by mac_lock */
  66 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  67 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  68         struct {
  69                 u8 addr[ETH_ALEN];
  70                 u16 id;
  71         } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX],
  72           dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
  73         int dev_uc_count;               /* negative for PROMISC */
  74         int dev_mc_count;               /* negative for PROMISC/ALLMULTI */
  75 };
  76
  77 /* An arbitrary search limit for the software hash table */
  78 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
  79
  80 static void efx_ef10_rx_push_rss_config(struct efx_nic *efx);
  81 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
  82 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
  83
  84 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
  85 {
  86         efx_dword_t reg;
  87
  88         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
  89         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
  90                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
  91 }
  92
  93 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
  94 {
  95         return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]);
  96 }
  97
  98 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
  99 {
 100         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
 101         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 102         size_t outlen;
 103         int rc;
 104
 105         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 106
 107         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 108                           outbuf, sizeof(outbuf), &outlen);
 109         if (rc)
 110                 return rc;
 111         if (outlen < sizeof(outbuf)) {
 112                 netif_err(efx, drv, efx->net_dev,
 113                           "unable to read datapath firmware capabilities\n");
 114                 return -EIO;
 115         }
 116
 117         nic_data->datapath_caps =
 118                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 119
 120         if (!(nic_data->datapath_caps &
 121               (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
 122                 netif_err(efx, drv, efx->net_dev,
 123                           "current firmware does not support TSO\n");
 124                 return -ENODEV;
 125         }
 126
 127         if (!(nic_data->datapath_caps &
 128               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 129                 netif_err(efx, probe, efx->net_dev,
 130                           "current firmware does not support an RX prefix\n");
 131                 return -ENODEV;
 132         }
 133
 134         return 0;
 135 }
 136
 137 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 138 {
 139         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 140         int rc;
 141
 142         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 143                           outbuf, sizeof(outbuf), NULL);
 144         if (rc)
 145                 return rc;
 146         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 147         return rc > 0 ? rc : -ERANGE;
 148 }
 149
 150 static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address)
 151 {
 152         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 153         size_t outlen;
 154         int rc;
 155
 156         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 157
 158         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 159                           outbuf, sizeof(outbuf), &outlen);
 160         if (rc)
 161                 return rc;
 162         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 163                 return -EIO;
 164
 165         ether_addr_copy(mac_address,
 166                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 167         return 0;
 168 }
 169
 170 static int efx_ef10_probe(struct efx_nic *efx)
 171 {
 172         struct efx_ef10_nic_data *nic_data;
 173         int i, rc;
 174
 175         /* We can have one VI for each 8K region.  However, until we
 176          * use TX option descriptors we need two TX queues per channel.
 177          */
 178         efx->max_channels =
 179                 min_t(unsigned int,
 180                       EFX_MAX_CHANNELS,
 181                       resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) /
 182                       (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
 183         if (WARN_ON(efx->max_channels == 0))
 184                 return -EIO;
 185
 186         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 187         if (!nic_data)
 188                 return -ENOMEM;
 189         efx->nic_data = nic_data;
 190
 191         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 192                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 193         if (rc)
 194                 goto fail1;
 195
 196         /* Get the MC's warm boot count.  In case it's rebooting right
 197          * now, be prepared to retry.
 198          */
 199         i = 0;
 200         for (;;) {
 201                 rc = efx_ef10_get_warm_boot_count(efx);
 202                 if (rc >= 0)
 203                         break;
 204                 if (++i == 5)
 205                         goto fail2;
 206                 ssleep(1);
 207         }
 208         nic_data->warm_boot_count = rc;
 209
 210         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 211
 212         /* In case we're recovering from a crash (kexec), we want to
 213          * cancel any outstanding request by the previous user of this
 214          * function.  We send a special message using the least
 215          * significant bits of the 'high' (doorbell) register.
 216          */
 217         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 218
 219         rc = efx_mcdi_init(efx);
 220         if (rc)
 221                 goto fail2;
 222
 223         /* Reset (most) configuration for this function */
 224         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 225         if (rc)
 226                 goto fail3;
 227
 228         /* Enable event logging */
 229         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 230         if (rc)
 231                 goto fail3;
 232
 233         rc = efx_ef10_init_datapath_caps(efx);
 234         if (rc < 0)
 235                 goto fail3;
 236
 237         efx->rx_packet_len_offset =
 238                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 239
 240         rc = efx_mcdi_port_get_number(efx);
 241         if (rc < 0)
 242                 goto fail3;
 243         efx->port_num = rc;
 244
 245         rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr);
 246         if (rc)
 247                 goto fail3;
 248
 249         rc = efx_ef10_get_sysclk_freq(efx);
 250         if (rc < 0)
 251                 goto fail3;
 252         efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
 253
 254         /* Check whether firmware supports bug 35388 workaround */
 255         rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
 256         if (rc == 0)
 257                 nic_data->workaround_35388 = true;
 258         else if (rc != -ENOSYS && rc != -ENOENT)
 259                 goto fail3;
 260         netif_dbg(efx, probe, efx->net_dev,
 261                   "workaround for bug 35388 is %sabled\n",
 262                   nic_data->workaround_35388 ? "en" : "dis");
 263
 264         rc = efx_mcdi_mon_probe(efx);
 265         if (rc)
 266                 goto fail3;
 267
 268         efx_ptp_probe(efx, NULL);
 269
 270         return 0;
 271
 272 fail3:
 273         efx_mcdi_fini(efx);
 274 fail2:
 275         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 276 fail1:
 277         kfree(nic_data);
 278         efx->nic_data = NULL;
 279         return rc;
 280 }
 281
 282 static int efx_ef10_free_vis(struct efx_nic *efx)
 283 {
 284         MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, 0);
 285         size_t outlen;
 286         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 287                                     outbuf, sizeof(outbuf), &outlen);
 288
 289         /* -EALREADY means nothing to free, so ignore */
 290         if (rc == -EALREADY)
 291                 rc = 0;
 292         if (rc)
 293                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 294                                        rc);
 295         return rc;
 296 }
 297
 298 #ifdef EFX_USE_PIO
 299
 300 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 301 {
 302         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 303         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 304         unsigned int i;
 305         int rc;
 306
 307         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 308
 309         for (i = 0; i < nic_data->n_piobufs; i++) {
 310                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 311                                nic_data->piobuf_handle[i]);
 312                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 313                                   NULL, 0, NULL);
 314                 WARN_ON(rc);
 315         }
 316
 317         nic_data->n_piobufs = 0;
 318 }
 319
 320 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 321 {
 322         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 323         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 324         unsigned int i;
 325         size_t outlen;
 326         int rc = 0;
 327
 328         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 329
 330         for (i = 0; i < n; i++) {
 331                 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 332                                   outbuf, sizeof(outbuf), &outlen);
 333                 if (rc)
 334                         break;
 335                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 336                         rc = -EIO;
 337                         break;
 338                 }
 339                 nic_data->piobuf_handle[i] =
 340                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 341                 netif_dbg(efx, probe, efx->net_dev,
 342                           "allocated PIO buffer %u handle %x\n", i,
 343                           nic_data->piobuf_handle[i]);
 344         }
 345
 346         nic_data->n_piobufs = i;
 347         if (rc)
 348                 efx_ef10_free_piobufs(efx);
 349         return rc;
 350 }
 351
 352 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 353 {
 354         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 355         MCDI_DECLARE_BUF(inbuf,
 356                          max(MC_CMD_LINK_PIOBUF_IN_LEN,
 357                              MC_CMD_UNLINK_PIOBUF_IN_LEN));
 358         struct efx_channel *channel;
 359         struct efx_tx_queue *tx_queue;
 360         unsigned int offset, index;
 361         int rc;
 362
 363         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 364         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 365
 366         /* Link a buffer to each VI in the write-combining mapping */
 367         for (index = 0; index < nic_data->n_piobufs; ++index) {
 368                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 369                                nic_data->piobuf_handle[index]);
 370                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 371                                nic_data->pio_write_vi_base + index);
 372                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 373                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 374                                   NULL, 0, NULL);
 375                 if (rc) {
 376                         netif_err(efx, drv, efx->net_dev,
 377                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 378                                   nic_data->pio_write_vi_base + index, index,
 379                                   rc);
 380                         goto fail;
 381                 }
 382                 netif_dbg(efx, probe, efx->net_dev,
 383                           "linked VI %u to PIO buffer %u\n",
 384                           nic_data->pio_write_vi_base + index, index);
 385         }
 386
 387         /* Link a buffer to each TX queue */
 388         efx_for_each_channel(channel, efx) {
 389                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 390                         /* We assign the PIO buffers to queues in
 391                          * reverse order to allow for the following
 392                          * special case.
 393                          */
 394                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 395                                    tx_queue->channel->channel - 1) *
 396                                   efx_piobuf_size);
 397                         index = offset / ER_DZ_TX_PIOBUF_SIZE;
 398                         offset = offset % ER_DZ_TX_PIOBUF_SIZE;
 399
 400                         /* When the host page size is 4K, the first
 401                          * host page in the WC mapping may be within
 402                          * the same VI page as the last TX queue.  We
 403                          * can only link one buffer to each VI.
 404                          */
 405                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 406                                 BUG_ON(index != 0);
 407                                 rc = 0;
 408                         } else {
 409                                 MCDI_SET_DWORD(inbuf,
 410                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 411                                                nic_data->piobuf_handle[index]);
 412                                 MCDI_SET_DWORD(inbuf,
 413                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 414                                                tx_queue->queue);
 415                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 416                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 417                                                   NULL, 0, NULL);
 418                         }
 419
 420                         if (rc) {
 421                                 /* This is non-fatal; the TX path just
 422                                  * won't use PIO for this queue
 423                                  */
 424                                 netif_err(efx, drv, efx->net_dev,
 425                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 426                                           tx_queue->queue, index, rc);
 427                                 tx_queue->piobuf = NULL;
 428                         } else {
 429                                 tx_queue->piobuf =
 430                                         nic_data->pio_write_base +
 431                                         index * EFX_VI_PAGE_SIZE + offset;
 432                                 tx_queue->piobuf_offset = offset;
 433                                 netif_dbg(efx, probe, efx->net_dev,
 434                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
 435                                           tx_queue->queue, index,
 436                                           tx_queue->piobuf_offset,
 437                                           tx_queue->piobuf);
 438                         }
 439                 }
 440         }
 441
 442         return 0;
 443
 444 fail:
 445         while (index--) {
 446                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
 447                                nic_data->pio_write_vi_base + index);
 448                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
 449                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
 450                              NULL, 0, NULL);
 451         }
 452         return rc;
 453 }
 454
 455 #else /* !EFX_USE_PIO */
 456
 457 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 458 {
 459         return n == 0 ? 0 : -ENOBUFS;
 460 }
 461
 462 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 463 {
 464         return 0;
 465 }
 466
 467 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 468 {
 469 }
 470
 471 #endif /* EFX_USE_PIO */
 472
 473 static void efx_ef10_remove(struct efx_nic *efx)
 474 {
 475         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 476         int rc;
 477
 478         efx_ptp_remove(efx);
 479
 480         efx_mcdi_mon_remove(efx);
 481
 482         efx_ef10_rx_free_indir_table(efx);
 483
 484         if (nic_data->wc_membase)
 485                 iounmap(nic_data->wc_membase);
 486
 487         rc = efx_ef10_free_vis(efx);
 488         WARN_ON(rc != 0);
 489
 490         if (!nic_data->must_restore_piobufs)
 491                 efx_ef10_free_piobufs(efx);
 492
 493         efx_mcdi_fini(efx);
 494         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 495         kfree(nic_data);
 496 }
 497
 498 static int efx_ef10_alloc_vis(struct efx_nic *efx,
 499                               unsigned int min_vis, unsigned int max_vis)
 500 {
 501         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
 502         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
 503         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 504         size_t outlen;
 505         int rc;
 506
 507         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
 508         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
 509         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
 510                           outbuf, sizeof(outbuf), &outlen);
 511         if (rc != 0)
 512                 return rc;
 513
 514         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
 515                 return -EIO;
 516
 517         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
 518                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
 519
 520         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
 521         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
 522         return 0;
 523 }
 524
 525 /* Note that the failure path of this function does not free
 526  * resources, as this will be done by efx_ef10_remove().
 527  */
 528 static int efx_ef10_dimension_resources(struct efx_nic *efx)
 529 {
 530         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 531         unsigned int uc_mem_map_size, wc_mem_map_size;
 532         unsigned int min_vis, pio_write_vi_base, max_vis;
 533         void __iomem *membase;
 534         int rc;
 535
 536         min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
 537
 538 #ifdef EFX_USE_PIO
 539         /* Try to allocate PIO buffers if wanted and if the full
 540          * number of PIO buffers would be sufficient to allocate one
 541          * copy-buffer per TX channel.  Failure is non-fatal, as there
 542          * are only a small number of PIO buffers shared between all
 543          * functions of the controller.
 544          */
 545         if (efx_piobuf_size != 0 &&
 546             ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
 547             efx->n_tx_channels) {
 548                 unsigned int n_piobufs =
 549                         DIV_ROUND_UP(efx->n_tx_channels,
 550                                      ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
 551
 552                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
 553                 if (rc)
 554                         netif_err(efx, probe, efx->net_dev,
 555                                   "failed to allocate PIO buffers (%d)\n", rc);
 556                 else
 557                         netif_dbg(efx, probe, efx->net_dev,
 558                                   "allocated %u PIO buffers\n", n_piobufs);
 559         }
 560 #else
 561         nic_data->n_piobufs = 0;
 562 #endif
 563
 564         /* PIO buffers should be mapped with write-combining enabled,
 565          * and we want to make single UC and WC mappings rather than
 566          * several of each (in fact that's the only option if host
 567          * page size is >4K).  So we may allocate some extra VIs just
 568          * for writing PIO buffers through.
 569          *
 570          * The UC mapping contains (min_vis - 1) complete VIs and the
 571          * first half of the next VI.  Then the WC mapping begins with
 572          * the second half of this last VI.
 573          */
 574         uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
 575                                      ER_DZ_TX_PIOBUF);
 576         if (nic_data->n_piobufs) {
 577                 /* pio_write_vi_base rounds down to give the number of complete
 578                  * VIs inside the UC mapping.
 579                  */
 580                 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
 581                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
 582                                                nic_data->n_piobufs) *
 583                                               EFX_VI_PAGE_SIZE) -
 584                                    uc_mem_map_size);
 585                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
 586         } else {
 587                 pio_write_vi_base = 0;
 588                 wc_mem_map_size = 0;
 589                 max_vis = min_vis;
 590         }
 591
 592         /* In case the last attached driver failed to free VIs, do it now */
 593         rc = efx_ef10_free_vis(efx);
 594         if (rc != 0)
 595                 return rc;
 596
 597         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
 598         if (rc != 0)
 599                 return rc;
 600
 601         /* If we didn't get enough VIs to map all the PIO buffers, free the
 602          * PIO buffers
 603          */
 604         if (nic_data->n_piobufs &&
 605             nic_data->n_allocated_vis <
 606             pio_write_vi_base + nic_data->n_piobufs) {
 607                 netif_dbg(efx, probe, efx->net_dev,
 608                           "%u VIs are not sufficient to map %u PIO buffers\n",
 609                           nic_data->n_allocated_vis, nic_data->n_piobufs);
 610                 efx_ef10_free_piobufs(efx);
 611         }
 612
 613         /* Shrink the original UC mapping of the memory BAR */
 614         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
 615         if (!membase) {
 616                 netif_err(efx, probe, efx->net_dev,
 617                           "could not shrink memory BAR to %x\n",
 618                           uc_mem_map_size);
 619                 return -ENOMEM;
 620         }
 621         iounmap(efx->membase);
 622         efx->membase = membase;
 623
 624         /* Set up the WC mapping if needed */
 625         if (wc_mem_map_size) {
 626                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
 627                                                   uc_mem_map_size,
 628                                                   wc_mem_map_size);
 629                 if (!nic_data->wc_membase) {
 630                         netif_err(efx, probe, efx->net_dev,
 631                                   "could not allocate WC mapping of size %x\n",
 632                                   wc_mem_map_size);
 633                         return -ENOMEM;
 634                 }
 635                 nic_data->pio_write_vi_base = pio_write_vi_base;
 636                 nic_data->pio_write_base =
 637                         nic_data->wc_membase +
 638                         (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
 639                          uc_mem_map_size);
 640
 641                 rc = efx_ef10_link_piobufs(efx);
 642                 if (rc)
 643                         efx_ef10_free_piobufs(efx);
 644         }
 645
 646         netif_dbg(efx, probe, efx->net_dev,
 647                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
 648                   &efx->membase_phys, efx->membase, uc_mem_map_size,
 649                   nic_data->wc_membase, wc_mem_map_size);
 650
 651         return 0;
 652 }
 653
 654 static int efx_ef10_init_nic(struct efx_nic *efx)
 655 {
 656         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 657         int rc;
 658
 659         if (nic_data->must_check_datapath_caps) {
 660                 rc = efx_ef10_init_datapath_caps(efx);
 661                 if (rc)
 662                         return rc;
 663                 nic_data->must_check_datapath_caps = false;
 664         }
 665
 666         if (nic_data->must_realloc_vis) {
 667                 /* We cannot let the number of VIs change now */
 668                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
 669                                         nic_data->n_allocated_vis);
 670                 if (rc)
 671                         return rc;
 672                 nic_data->must_realloc_vis = false;
 673         }
 674
 675         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
 676                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
 677                 if (rc == 0) {
 678                         rc = efx_ef10_link_piobufs(efx);
 679                         if (rc)
 680                                 efx_ef10_free_piobufs(efx);
 681                 }
 682
 683                 /* Log an error on failure, but this is non-fatal */
 684                 if (rc)
 685                         netif_err(efx, drv, efx->net_dev,
 686                                   "failed to restore PIO buffers (%d)\n", rc);
 687                 nic_data->must_restore_piobufs = false;
 688         }
 689
 690         efx_ef10_rx_push_rss_config(efx);
 691         return 0;
 692 }
 693
 694 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
 695 {
 696         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 697
 698         /* All our allocations have been reset */
 699         nic_data->must_realloc_vis = true;
 700         nic_data->must_restore_filters = true;
 701         nic_data->must_restore_piobufs = true;
 702         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 703 }
 704
 705 static int efx_ef10_map_reset_flags(u32 *flags)
 706 {
 707         enum {
 708                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
 709                                    ETH_RESET_SHARED_SHIFT),
 710                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
 711                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
 712                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
 713                                  ETH_RESET_SHARED_SHIFT)
 714         };
 715
 716         /* We assume for now that our PCI function is permitted to
 717          * reset everything.
 718          */
 719
 720         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
 721                 *flags &= ~EF10_RESET_MC;
 722                 return RESET_TYPE_WORLD;
 723         }
 724
 725         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
 726                 *flags &= ~EF10_RESET_PORT;
 727                 return RESET_TYPE_ALL;
 728         }
 729
 730         /* no invisible reset implemented */
 731
 732         return -EINVAL;
 733 }
 734
 735 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
 736 {
 737         int rc = efx_mcdi_reset(efx, reset_type);
 738
 739         /* If it was a port reset, trigger reallocation of MC resources.
 740          * Note that on an MC reset nothing needs to be done now because we'll
 741          * detect the MC reset later and handle it then.
 742          * For an FLR, we never get an MC reset event, but the MC has reset all
 743          * resources assigned to us, so we have to trigger reallocation now.
 744          */
 745         if ((reset_type == RESET_TYPE_ALL ||
 746              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
 747                 efx_ef10_reset_mc_allocations(efx);
 748         return rc;
 749 }
 750
 751 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
 752         [EF10_STAT_ ## ext_name] =                              \
 753         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
 754 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
 755         [EF10_STAT_ ## int_name] =                              \
 756         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
 757 #define EF10_OTHER_STAT(ext_name)                               \
 758         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
 759 #define GENERIC_SW_STAT(ext_name)                               \
 760         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
 761
 762 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
 763         EF10_DMA_STAT(tx_bytes, TX_BYTES),
 764         EF10_DMA_STAT(tx_packets, TX_PKTS),
 765         EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
 766         EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS),
 767         EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
 768         EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
 769         EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
 770         EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS),
 771         EF10_DMA_STAT(tx_64, TX_64_PKTS),
 772         EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
 773         EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
 774         EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
 775         EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
 776         EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
 777         EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
 778         EF10_DMA_STAT(rx_bytes, RX_BYTES),
 779         EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES),
 780         EF10_OTHER_STAT(rx_good_bytes),
 781         EF10_OTHER_STAT(rx_bad_bytes),
 782         EF10_DMA_STAT(rx_packets, RX_PKTS),
 783         EF10_DMA_STAT(rx_good, RX_GOOD_PKTS),
 784         EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
 785         EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
 786         EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS),
 787         EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
 788         EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
 789         EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
 790         EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
 791         EF10_DMA_STAT(rx_64, RX_64_PKTS),
 792         EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
 793         EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
 794         EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
 795         EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
 796         EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
 797         EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
 798         EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
 799         EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
 800         EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
 801         EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
 802         EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
 803         EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
 804         GENERIC_SW_STAT(rx_nodesc_trunc),
 805         GENERIC_SW_STAT(rx_noskb_drops),
 806         EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
 807         EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
 808         EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
 809         EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
 810         EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB),
 811         EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB),
 812         EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING),
 813         EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
 814         EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
 815         EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
 816         EF10_DMA_STAT(rx_dp_hlb_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS),
 817         EF10_DMA_STAT(rx_dp_hlb_wait, RXDP_EMERGENCY_WAIT_CONDITIONS),
 818 };
 819
 820 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) |           \
 821                                (1ULL << EF10_STAT_tx_packets) |         \
 822                                (1ULL << EF10_STAT_tx_pause) |           \
 823                                (1ULL << EF10_STAT_tx_unicast) |         \
 824                                (1ULL << EF10_STAT_tx_multicast) |       \
 825                                (1ULL << EF10_STAT_tx_broadcast) |       \
 826                                (1ULL << EF10_STAT_rx_bytes) |           \
 827                                (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
 828                                (1ULL << EF10_STAT_rx_good_bytes) |      \
 829                                (1ULL << EF10_STAT_rx_bad_bytes) |       \
 830                                (1ULL << EF10_STAT_rx_packets) |         \
 831                                (1ULL << EF10_STAT_rx_good) |            \
 832                                (1ULL << EF10_STAT_rx_bad) |             \
 833                                (1ULL << EF10_STAT_rx_pause) |           \
 834                                (1ULL << EF10_STAT_rx_control) |         \
 835                                (1ULL << EF10_STAT_rx_unicast) |         \
 836                                (1ULL << EF10_STAT_rx_multicast) |       \
 837                                (1ULL << EF10_STAT_rx_broadcast) |       \
 838                                (1ULL << EF10_STAT_rx_lt64) |            \
 839                                (1ULL << EF10_STAT_rx_64) |              \
 840                                (1ULL << EF10_STAT_rx_65_to_127) |       \
 841                                (1ULL << EF10_STAT_rx_128_to_255) |      \
 842                                (1ULL << EF10_STAT_rx_256_to_511) |      \
 843                                (1ULL << EF10_STAT_rx_512_to_1023) |     \
 844                                (1ULL << EF10_STAT_rx_1024_to_15xx) |    \
 845                                (1ULL << EF10_STAT_rx_15xx_to_jumbo) |   \
 846                                (1ULL << EF10_STAT_rx_gtjumbo) |         \
 847                                (1ULL << EF10_STAT_rx_bad_gtjumbo) |     \
 848                                (1ULL << EF10_STAT_rx_overflow) |        \
 849                                (1ULL << EF10_STAT_rx_nodesc_drops) |    \
 850                                (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
 851                                (1ULL << GENERIC_STAT_rx_noskb_drops))
 852
 853 /* These statistics are only provided by the 10G MAC.  For a 10G/40G
 854  * switchable port we do not expose these because they might not
 855  * include all the packets they should.
 856  */
 857 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) |       \
 858                                  (1ULL << EF10_STAT_tx_lt64) |          \
 859                                  (1ULL << EF10_STAT_tx_64) |            \
 860                                  (1ULL << EF10_STAT_tx_65_to_127) |     \
 861                                  (1ULL << EF10_STAT_tx_128_to_255) |    \
 862                                  (1ULL << EF10_STAT_tx_256_to_511) |    \
 863                                  (1ULL << EF10_STAT_tx_512_to_1023) |   \
 864                                  (1ULL << EF10_STAT_tx_1024_to_15xx) |  \
 865                                  (1ULL << EF10_STAT_tx_15xx_to_jumbo))
 866
 867 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
 868  * switchable port we do expose these because the errors will otherwise
 869  * be silent.
 870  */
 871 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) |  \
 872                                   (1ULL << EF10_STAT_rx_length_error))
 873
 874 /* These statistics are only provided if the firmware supports the
 875  * capability PM_AND_RXDP_COUNTERS.
 876  */
 877 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
 878         (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) |                   \
 879         (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) |                 \
 880         (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) |                    \
 881         (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) |                  \
 882         (1ULL << EF10_STAT_rx_pm_trunc_qbb) |                           \
 883         (1ULL << EF10_STAT_rx_pm_discard_qbb) |                         \
 884         (1ULL << EF10_STAT_rx_pm_discard_mapping) |                     \
 885         (1ULL << EF10_STAT_rx_dp_q_disabled_packets) |                  \
 886         (1ULL << EF10_STAT_rx_dp_di_dropped_packets) |                  \
 887         (1ULL << EF10_STAT_rx_dp_streaming_packets) |                   \
 888         (1ULL << EF10_STAT_rx_dp_hlb_fetch) |                           \
 889         (1ULL << EF10_STAT_rx_dp_hlb_wait))
 890
 891 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
 892 {
 893         u64 raw_mask = HUNT_COMMON_STAT_MASK;
 894         u32 port_caps = efx_mcdi_phy_get_caps(efx);
 895         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 896
 897         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
 898                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
 899         else
 900                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
 901
 902         if (nic_data->datapath_caps &
 903             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
 904                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
 905
 906         return raw_mask;
 907 }
 908
 909 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
 910 {
 911         u64 raw_mask = efx_ef10_raw_stat_mask(efx);
 912
 913 #if BITS_PER_LONG == 64
 914         mask[0] = raw_mask;
 915 #else
 916         mask[0] = raw_mask & 0xffffffff;
 917         mask[1] = raw_mask >> 32;
 918 #endif
 919 }
 920
 921 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
 922 {
 923         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
 924
 925         efx_ef10_get_stat_mask(efx, mask);
 926         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
 927                                       mask, names);
 928 }
 929
 930 static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
 931 {
 932         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 933         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
 934         __le64 generation_start, generation_end;
 935         u64 *stats = nic_data->stats;
 936         __le64 *dma_stats;
 937
 938         efx_ef10_get_stat_mask(efx, mask);
 939
 940         dma_stats = efx->stats_buffer.addr;
 941         nic_data = efx->nic_data;
 942
 943         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
 944         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
 945                 return 0;
 946         rmb();
 947         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
 948                              stats, efx->stats_buffer.addr, false);
 949         rmb();
 950         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
 951         if (generation_end != generation_start)
 952                 return -EAGAIN;
 953
 954         /* Update derived statistics */
 955         efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]);
 956         stats[EF10_STAT_rx_good_bytes] =
 957                 stats[EF10_STAT_rx_bytes] -
 958                 stats[EF10_STAT_rx_bytes_minus_good_bytes];
 959         efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes],
 960                              stats[EF10_STAT_rx_bytes_minus_good_bytes]);
 961         efx_update_sw_stats(efx, stats);
 962         return 0;
 963 }
 964
 965
 966 static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
 967                                     struct rtnl_link_stats64 *core_stats)
 968 {
 969         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
 970         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 971         u64 *stats = nic_data->stats;
 972         size_t stats_count = 0, index;
 973         int retry;
 974
 975         efx_ef10_get_stat_mask(efx, mask);
 976
 977         /* If we're unlucky enough to read statistics during the DMA, wait
 978          * up to 10ms for it to finish (typically takes <500us)
 979          */
 980         for (retry = 0; retry < 100; ++retry) {
 981                 if (efx_ef10_try_update_nic_stats(efx) == 0)
 982                         break;
 983                 udelay(100);
 984         }
 985
 986         if (full_stats) {
 987                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
 988                         if (efx_ef10_stat_desc[index].name) {
 989                                 *full_stats++ = stats[index];
 990                                 ++stats_count;
 991                         }
 992                 }
 993         }
 994
 995         if (core_stats) {
 996                 core_stats->rx_packets = stats[EF10_STAT_rx_packets];
 997                 core_stats->tx_packets = stats[EF10_STAT_tx_packets];
 998                 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes];
 999                 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes];
1000                 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops] +
1001                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
1002                                          stats[GENERIC_STAT_rx_noskb_drops];
1003                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1004                 core_stats->rx_length_errors =
1005                         stats[EF10_STAT_rx_gtjumbo] +
1006                         stats[EF10_STAT_rx_length_error];
1007                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1008                 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error];
1009                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1010                 core_stats->rx_errors = (core_stats->rx_length_errors +
1011                                          core_stats->rx_crc_errors +
1012                                          core_stats->rx_frame_errors);
1013         }
1014
1015         return stats_count;
1016 }
1017
1018 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1019 {
1020         struct efx_nic *efx = channel->efx;
1021         unsigned int mode, value;
1022         efx_dword_t timer_cmd;
1023
1024         if (channel->irq_moderation) {
1025                 mode = 3;
1026                 value = channel->irq_moderation - 1;
1027         } else {
1028                 mode = 0;
1029                 value = 0;
1030         }
1031
1032         if (EFX_EF10_WORKAROUND_35388(efx)) {
1033                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1034                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
1035                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
1036                                      ERF_DD_EVQ_IND_TIMER_VAL, value);
1037                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1038                                 channel->channel);
1039         } else {
1040                 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1041                                      ERF_DZ_TC_TIMER_VAL, value);
1042                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1043                                 channel->channel);
1044         }
1045 }
1046
1047 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1048 {
1049         wol->supported = 0;
1050         wol->wolopts = 0;
1051         memset(&wol->sopass, 0, sizeof(wol->sopass));
1052 }
1053
1054 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1055 {
1056         if (type != 0)
1057                 return -EINVAL;
1058         return 0;
1059 }
1060
1061 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1062                                   const efx_dword_t *hdr, size_t hdr_len,
1063                                   const efx_dword_t *sdu, size_t sdu_len)
1064 {
1065         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1066         u8 *pdu = nic_data->mcdi_buf.addr;
1067
1068         memcpy(pdu, hdr, hdr_len);
1069         memcpy(pdu + hdr_len, sdu, sdu_len);
1070         wmb();
1071
1072         /* The hardware provides 'low' and 'high' (doorbell) registers
1073          * for passing the 64-bit address of an MCDI request to
1074          * firmware.  However the dwords are swapped by firmware.  The
1075          * least significant bits of the doorbell are then 0 for all
1076          * MCDI requests due to alignment.
1077          */
1078         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1079                     ER_DZ_MC_DB_LWRD);
1080         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1081                     ER_DZ_MC_DB_HWRD);
1082 }
1083
1084 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1085 {
1086         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1087         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1088
1089         rmb();
1090         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1091 }
1092
1093 static void
1094 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1095                             size_t offset, size_t outlen)
1096 {
1097         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1098         const u8 *pdu = nic_data->mcdi_buf.addr;
1099
1100         memcpy(outbuf, pdu + offset, outlen);
1101 }
1102
1103 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1104 {
1105         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1106         int rc;
1107
1108         rc = efx_ef10_get_warm_boot_count(efx);
1109         if (rc < 0) {
1110                 /* The firmware is presumably in the process of
1111                  * rebooting.  However, we are supposed to report each
1112                  * reboot just once, so we must only do that once we
1113                  * can read and store the updated warm boot count.
1114                  */
1115                 return 0;
1116         }
1117
1118         if (rc == nic_data->warm_boot_count)
1119                 return 0;
1120
1121         nic_data->warm_boot_count = rc;
1122
1123         /* All our allocations have been reset */
1124         efx_ef10_reset_mc_allocations(efx);
1125
1126         /* The datapath firmware might have been changed */
1127         nic_data->must_check_datapath_caps = true;
1128
1129         /* MAC statistics have been cleared on the NIC; clear the local
1130          * statistic that we update with efx_update_diff_stat().
1131          */
1132         nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
1133
1134         return -EIO;
1135 }
1136
1137 /* Handle an MSI interrupt
1138  *
1139  * Handle an MSI hardware interrupt.  This routine schedules event
1140  * queue processing.  No interrupt acknowledgement cycle is necessary.
1141  * Also, we never need to check that the interrupt is for us, since
1142  * MSI interrupts cannot be shared.
1143  */
1144 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1145 {
1146         struct efx_msi_context *context = dev_id;
1147         struct efx_nic *efx = context->efx;
1148
1149         netif_vdbg(efx, intr, efx->net_dev,
1150                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1151
1152         if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1153                 /* Note test interrupts */
1154                 if (context->index == efx->irq_level)
1155                         efx->last_irq_cpu = raw_smp_processor_id();
1156
1157                 /* Schedule processing of the channel */
1158                 efx_schedule_channel_irq(efx->channel[context->index]);
1159         }
1160
1161         return IRQ_HANDLED;
1162 }
1163
1164 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1165 {
1166         struct efx_nic *efx = dev_id;
1167         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1168         struct efx_channel *channel;
1169         efx_dword_t reg;
1170         u32 queues;
1171
1172         /* Read the ISR which also ACKs the interrupts */
1173         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1174         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1175
1176         if (queues == 0)
1177                 return IRQ_NONE;
1178
1179         if (likely(soft_enabled)) {
1180                 /* Note test interrupts */
1181                 if (queues & (1U << efx->irq_level))
1182                         efx->last_irq_cpu = raw_smp_processor_id();
1183
1184                 efx_for_each_channel(channel, efx) {
1185                         if (queues & 1)
1186                                 efx_schedule_channel_irq(channel);
1187                         queues >>= 1;
1188                 }
1189         }
1190
1191         netif_vdbg(efx, intr, efx->net_dev,
1192                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1193                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1194
1195         return IRQ_HANDLED;
1196 }
1197
1198 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1199 {
1200         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1201
1202         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1203
1204         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1205         (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1206                             inbuf, sizeof(inbuf), NULL, 0, NULL);
1207 }
1208
1209 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1210 {
1211         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1212                                     (tx_queue->ptr_mask + 1) *
1213                                     sizeof(efx_qword_t),
1214                                     GFP_KERNEL);
1215 }
1216
1217 /* This writes to the TX_DESC_WPTR and also pushes data */
1218 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1219                                          const efx_qword_t *txd)
1220 {
1221         unsigned int write_ptr;
1222         efx_oword_t reg;
1223
1224         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1225         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1226         reg.qword[0] = *txd;
1227         efx_writeo_page(tx_queue->efx, &reg,
1228                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
1229 }
1230
1231 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1232 {
1233         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1234                                                        EFX_BUF_SIZE));
1235         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN);
1236         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1237         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1238         struct efx_channel *channel = tx_queue->channel;
1239         struct efx_nic *efx = tx_queue->efx;
1240         size_t inlen, outlen;
1241         dma_addr_t dma_addr;
1242         efx_qword_t *txd;
1243         int rc;
1244         int i;
1245
1246         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1247         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1248         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1249         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1250         MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1251                               INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1252                               INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1253         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1254         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1255
1256         dma_addr = tx_queue->txd.buf.dma_addr;
1257
1258         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1259                   tx_queue->queue, entries, (u64)dma_addr);
1260
1261         for (i = 0; i < entries; ++i) {
1262                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1263                 dma_addr += EFX_BUF_SIZE;
1264         }
1265
1266         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1267
1268         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1269                           outbuf, sizeof(outbuf), &outlen);
1270         if (rc)
1271                 goto fail;
1272
1273         /* A previous user of this TX queue might have set us up the
1274          * bomb by writing a descriptor to the TX push collector but
1275          * not the doorbell.  (Each collector belongs to a port, not a
1276          * queue or function, so cannot easily be reset.)  We must
1277          * attempt to push a no-op descriptor in its place.
1278          */
1279         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1280         tx_queue->insert_count = 1;
1281         txd = efx_tx_desc(tx_queue, 0);
1282         EFX_POPULATE_QWORD_4(*txd,
1283                              ESF_DZ_TX_DESC_IS_OPT, true,
1284                              ESF_DZ_TX_OPTION_TYPE,
1285                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1286                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1287                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1288         tx_queue->write_count = 1;
1289         wmb();
1290         efx_ef10_push_tx_desc(tx_queue, txd);
1291
1292         return;
1293
1294 fail:
1295         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1296                     tx_queue->queue);
1297 }
1298
1299 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1300 {
1301         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1302         MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN);
1303         struct efx_nic *efx = tx_queue->efx;
1304         size_t outlen;
1305         int rc;
1306
1307         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1308                        tx_queue->queue);
1309
1310         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
1311                           outbuf, sizeof(outbuf), &outlen);
1312
1313         if (rc && rc != -EALREADY)
1314                 goto fail;
1315
1316         return;
1317
1318 fail:
1319         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1320                                outbuf, outlen, rc);
1321 }
1322
1323 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1324 {
1325         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1326 }
1327
1328 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1329 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1330 {
1331         unsigned int write_ptr;
1332         efx_dword_t reg;
1333
1334         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1335         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1336         efx_writed_page(tx_queue->efx, &reg,
1337                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1338 }
1339
1340 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1341 {
1342         unsigned int old_write_count = tx_queue->write_count;
1343         struct efx_tx_buffer *buffer;
1344         unsigned int write_ptr;
1345         efx_qword_t *txd;
1346
1347         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1348
1349         do {
1350                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1351                 buffer = &tx_queue->buffer[write_ptr];
1352                 txd = efx_tx_desc(tx_queue, write_ptr);
1353                 ++tx_queue->write_count;
1354
1355                 /* Create TX descriptor ring entry */
1356                 if (buffer->flags & EFX_TX_BUF_OPTION) {
1357                         *txd = buffer->option;
1358                 } else {
1359                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1360                         EFX_POPULATE_QWORD_3(
1361                                 *txd,
1362                                 ESF_DZ_TX_KER_CONT,
1363                                 buffer->flags & EFX_TX_BUF_CONT,
1364                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1365                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1366                 }
1367         } while (tx_queue->write_count != tx_queue->insert_count);
1368
1369         wmb(); /* Ensure descriptors are written before they are fetched */
1370
1371         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1372                 txd = efx_tx_desc(tx_queue,
1373                                   old_write_count & tx_queue->ptr_mask);
1374                 efx_ef10_push_tx_desc(tx_queue, txd);
1375                 ++tx_queue->pushes;
1376         } else {
1377                 efx_ef10_notify_tx_desc(tx_queue);
1378         }
1379 }
1380
1381 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context)
1382 {
1383         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1384         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1385         size_t outlen;
1386         int rc;
1387
1388         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1389                        EVB_PORT_ID_ASSIGNED);
1390         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE,
1391                        MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE);
1392         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES,
1393                        EFX_MAX_CHANNELS);
1394
1395         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1396                 outbuf, sizeof(outbuf), &outlen);
1397         if (rc != 0)
1398                 return rc;
1399
1400         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1401                 return -EIO;
1402
1403         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1404
1405         return 0;
1406 }
1407
1408 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1409 {
1410         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1411         int rc;
1412
1413         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1414                        context);
1415
1416         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1417                             NULL, 0, NULL);
1418         WARN_ON(rc != 0);
1419 }
1420
1421 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context)
1422 {
1423         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1424         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1425         int i, rc;
1426
1427         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1428                        context);
1429         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1430                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1431
1432         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1433                 MCDI_PTR(tablebuf,
1434                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1435                                 (u8) efx->rx_indir_table[i];
1436
1437         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1438                           sizeof(tablebuf), NULL, 0, NULL);
1439         if (rc != 0)
1440                 return rc;
1441
1442         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1443                        context);
1444         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1445                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1446         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1447                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1448                         efx->rx_hash_key[i];
1449
1450         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1451                             sizeof(keybuf), NULL, 0, NULL);
1452 }
1453
1454 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1455 {
1456         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1457
1458         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1459                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1460         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1461 }
1462
1463 static void efx_ef10_rx_push_rss_config(struct efx_nic *efx)
1464 {
1465         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1466         int rc;
1467
1468         netif_dbg(efx, drv, efx->net_dev, "pushing RSS config\n");
1469
1470         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) {
1471                 rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context);
1472                 if (rc != 0)
1473                         goto fail;
1474         }
1475
1476         rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context);
1477         if (rc != 0)
1478                 goto fail;
1479
1480         return;
1481
1482 fail:
1483         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1484 }
1485
1486 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1487 {
1488         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1489                                     (rx_queue->ptr_mask + 1) *
1490                                     sizeof(efx_qword_t),
1491                                     GFP_KERNEL);
1492 }
1493
1494 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1495 {
1496         MCDI_DECLARE_BUF(inbuf,
1497                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1498                                                 EFX_BUF_SIZE));
1499         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN);
1500         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1501         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1502         struct efx_nic *efx = rx_queue->efx;
1503         size_t inlen, outlen;
1504         dma_addr_t dma_addr;
1505         int rc;
1506         int i;
1507
1508         rx_queue->scatter_n = 0;
1509         rx_queue->scatter_len = 0;
1510
1511         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1512         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1513         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1514         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1515                        efx_rx_queue_index(rx_queue));
1516         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
1517                               INIT_RXQ_IN_FLAG_PREFIX, 1,
1518                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
1519         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
1520         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1521
1522         dma_addr = rx_queue->rxd.buf.dma_addr;
1523
1524         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1525                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1526
1527         for (i = 0; i < entries; ++i) {
1528                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1529                 dma_addr += EFX_BUF_SIZE;
1530         }
1531
1532         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1533
1534         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
1535                           outbuf, sizeof(outbuf), &outlen);
1536         if (rc)
1537                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
1538                             efx_rx_queue_index(rx_queue));
1539 }
1540
1541 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1542 {
1543         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
1544         MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN);
1545         struct efx_nic *efx = rx_queue->efx;
1546         size_t outlen;
1547         int rc;
1548
1549         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1550                        efx_rx_queue_index(rx_queue));
1551
1552         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
1553                           outbuf, sizeof(outbuf), &outlen);
1554
1555         if (rc && rc != -EALREADY)
1556                 goto fail;
1557
1558         return;
1559
1560 fail:
1561         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
1562                                outbuf, outlen, rc);
1563 }
1564
1565 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1566 {
1567         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1568 }
1569
1570 /* This creates an entry in the RX descriptor queue */
1571 static inline void
1572 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1573 {
1574         struct efx_rx_buffer *rx_buf;
1575         efx_qword_t *rxd;
1576
1577         rxd = efx_rx_desc(rx_queue, index);
1578         rx_buf = efx_rx_buffer(rx_queue, index);
1579         EFX_POPULATE_QWORD_2(*rxd,
1580                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1581                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1582 }
1583
1584 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1585 {
1586         struct efx_nic *efx = rx_queue->efx;
1587         unsigned int write_count;
1588         efx_dword_t reg;
1589
1590         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1591         write_count = rx_queue->added_count & ~7;
1592         if (rx_queue->notified_count == write_count)
1593                 return;
1594
1595         do
1596                 efx_ef10_build_rx_desc(
1597                         rx_queue,
1598                         rx_queue->notified_count & rx_queue->ptr_mask);
1599         while (++rx_queue->notified_count != write_count);
1600
1601         wmb();
1602         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1603                              write_count & rx_queue->ptr_mask);
1604         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
1605                         efx_rx_queue_index(rx_queue));
1606 }
1607
1608 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1609
1610 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1611 {
1612         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1613         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1614         efx_qword_t event;
1615
1616         EFX_POPULATE_QWORD_2(event,
1617                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1618                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1619
1620         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1621
1622         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1623          * already swapped the data to little-endian order.
1624          */
1625         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1626                sizeof(efx_qword_t));
1627
1628         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1629                            inbuf, sizeof(inbuf), 0,
1630                            efx_ef10_rx_defer_refill_complete, 0);
1631 }
1632
1633 static void
1634 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1635                                   int rc, efx_dword_t *outbuf,
1636                                   size_t outlen_actual)
1637 {
1638         /* nothing to do */
1639 }
1640
1641 static int efx_ef10_ev_probe(struct efx_channel *channel)
1642 {
1643         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
1644                                     (channel->eventq_mask + 1) *
1645                                     sizeof(efx_qword_t),
1646                                     GFP_KERNEL);
1647 }
1648
1649 static int efx_ef10_ev_init(struct efx_channel *channel)
1650 {
1651         MCDI_DECLARE_BUF(inbuf,
1652                          MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
1653                                                 EFX_BUF_SIZE));
1654         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
1655         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
1656         struct efx_nic *efx = channel->efx;
1657         struct efx_ef10_nic_data *nic_data;
1658         bool supports_rx_merge;
1659         size_t inlen, outlen;
1660         dma_addr_t dma_addr;
1661         int rc;
1662         int i;
1663
1664         nic_data = efx->nic_data;
1665         supports_rx_merge =
1666                 !!(nic_data->datapath_caps &
1667                    1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
1668
1669         /* Fill event queue with all ones (i.e. empty events) */
1670         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1671
1672         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
1673         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
1674         /* INIT_EVQ expects index in vector table, not absolute */
1675         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
1676         MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
1677                               INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
1678                               INIT_EVQ_IN_FLAG_RX_MERGE, 1,
1679                               INIT_EVQ_IN_FLAG_TX_MERGE, 1,
1680                               INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
1681         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
1682                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
1683         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
1684         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
1685         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
1686                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
1687         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
1688
1689         dma_addr = channel->eventq.buf.dma_addr;
1690         for (i = 0; i < entries; ++i) {
1691                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
1692                 dma_addr += EFX_BUF_SIZE;
1693         }
1694
1695         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
1696
1697         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
1698                           outbuf, sizeof(outbuf), &outlen);
1699         /* IRQ return is ignored */
1700         return rc;
1701 }
1702
1703 static void efx_ef10_ev_fini(struct efx_channel *channel)
1704 {
1705         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
1706         MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN);
1707         struct efx_nic *efx = channel->efx;
1708         size_t outlen;
1709         int rc;
1710
1711         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
1712
1713         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
1714                           outbuf, sizeof(outbuf), &outlen);
1715
1716         if (rc && rc != -EALREADY)
1717                 goto fail;
1718
1719         return;
1720
1721 fail:
1722         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
1723                                outbuf, outlen, rc);
1724 }
1725
1726 static void efx_ef10_ev_remove(struct efx_channel *channel)
1727 {
1728         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
1729 }
1730
1731 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
1732                                            unsigned int rx_queue_label)
1733 {
1734         struct efx_nic *efx = rx_queue->efx;
1735
1736         netif_info(efx, hw, efx->net_dev,
1737                    "rx event arrived on queue %d labeled as queue %u\n",
1738                    efx_rx_queue_index(rx_queue), rx_queue_label);
1739
1740         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1741 }
1742
1743 static void
1744 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
1745                              unsigned int actual, unsigned int expected)
1746 {
1747         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
1748         struct efx_nic *efx = rx_queue->efx;
1749
1750         netif_info(efx, hw, efx->net_dev,
1751                    "dropped %d events (index=%d expected=%d)\n",
1752                    dropped, actual, expected);
1753
1754         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1755 }
1756
1757 /* partially received RX was aborted. clean up. */
1758 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
1759 {
1760         unsigned int rx_desc_ptr;
1761
1762         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
1763                   "scattered RX aborted (dropping %u buffers)\n",
1764                   rx_queue->scatter_n);
1765
1766         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
1767
1768         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
1769                       0, EFX_RX_PKT_DISCARD);
1770
1771         rx_queue->removed_count += rx_queue->scatter_n;
1772         rx_queue->scatter_n = 0;
1773         rx_queue->scatter_len = 0;
1774         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
1775 }
1776
1777 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
1778                                     const efx_qword_t *event)
1779 {
1780         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
1781         unsigned int n_descs, n_packets, i;
1782         struct efx_nic *efx = channel->efx;
1783         struct efx_rx_queue *rx_queue;
1784         bool rx_cont;
1785         u16 flags = 0;
1786
1787         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1788                 return 0;
1789
1790         /* Basic packet information */
1791         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
1792         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
1793         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
1794         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
1795         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
1796
1797         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
1798                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
1799                             EFX_QWORD_FMT "\n",
1800                             EFX_QWORD_VAL(*event));
1801
1802         rx_queue = efx_channel_get_rx_queue(channel);
1803
1804         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
1805                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
1806
1807         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
1808                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1809
1810         if (n_descs != rx_queue->scatter_n + 1) {
1811                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1812
1813                 /* detect rx abort */
1814                 if (unlikely(n_descs == rx_queue->scatter_n)) {
1815                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
1816                                 netdev_WARN(efx->net_dev,
1817                                             "invalid RX abort: scatter_n=%u event="
1818                                             EFX_QWORD_FMT "\n",
1819                                             rx_queue->scatter_n,
1820                                             EFX_QWORD_VAL(*event));
1821                         efx_ef10_handle_rx_abort(rx_queue);
1822                         return 0;
1823                 }
1824
1825                 /* Check that RX completion merging is valid, i.e.
1826                  * the current firmware supports it and this is a
1827                  * non-scattered packet.
1828                  */
1829                 if (!(nic_data->datapath_caps &
1830                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
1831                     rx_queue->scatter_n != 0 || rx_cont) {
1832                         efx_ef10_handle_rx_bad_lbits(
1833                                 rx_queue, next_ptr_lbits,
1834                                 (rx_queue->removed_count +
1835                                  rx_queue->scatter_n + 1) &
1836                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1837                         return 0;
1838                 }
1839
1840                 /* Merged completion for multiple non-scattered packets */
1841                 rx_queue->scatter_n = 1;
1842                 rx_queue->scatter_len = 0;
1843                 n_packets = n_descs;
1844                 ++channel->n_rx_merge_events;
1845                 channel->n_rx_merge_packets += n_packets;
1846                 flags |= EFX_RX_PKT_PREFIX_LEN;
1847         } else {
1848                 ++rx_queue->scatter_n;
1849                 rx_queue->scatter_len += rx_bytes;
1850                 if (rx_cont)
1851                         return 0;
1852                 n_packets = 1;
1853         }
1854
1855         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
1856                 flags |= EFX_RX_PKT_DISCARD;
1857
1858         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
1859                 channel->n_rx_ip_hdr_chksum_err += n_packets;
1860         } else if (unlikely(EFX_QWORD_FIELD(*event,
1861                                             ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
1862                 channel->n_rx_tcp_udp_chksum_err += n_packets;
1863         } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
1864                    rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
1865                 flags |= EFX_RX_PKT_CSUMMED;
1866         }
1867
1868         if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
1869                 flags |= EFX_RX_PKT_TCP;
1870
1871         channel->irq_mod_score += 2 * n_packets;
1872
1873         /* Handle received packet(s) */
1874         for (i = 0; i < n_packets; i++) {
1875                 efx_rx_packet(rx_queue,
1876                               rx_queue->removed_count & rx_queue->ptr_mask,
1877                               rx_queue->scatter_n, rx_queue->scatter_len,
1878                               flags);
1879                 rx_queue->removed_count += rx_queue->scatter_n;
1880         }
1881
1882         rx_queue->scatter_n = 0;
1883         rx_queue->scatter_len = 0;
1884
1885         return n_packets;
1886 }
1887
1888 static int
1889 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
1890 {
1891         struct efx_nic *efx = channel->efx;
1892         struct efx_tx_queue *tx_queue;
1893         unsigned int tx_ev_desc_ptr;
1894         unsigned int tx_ev_q_label;
1895         int tx_descs = 0;
1896
1897         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1898                 return 0;
1899
1900         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
1901                 return 0;
1902
1903         /* Transmit completion */
1904         tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
1905         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
1906         tx_queue = efx_channel_get_tx_queue(channel,
1907                                             tx_ev_q_label % EFX_TXQ_TYPES);
1908         tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
1909                     tx_queue->ptr_mask);
1910         efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
1911
1912         return tx_descs;
1913 }
1914
1915 static void
1916 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1917 {
1918         struct efx_nic *efx = channel->efx;
1919         int subcode;
1920
1921         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
1922
1923         switch (subcode) {
1924         case ESE_DZ_DRV_TIMER_EV:
1925         case ESE_DZ_DRV_WAKE_UP_EV:
1926                 break;
1927         case ESE_DZ_DRV_START_UP_EV:
1928                 /* event queue init complete. ok. */
1929                 break;
1930         default:
1931                 netif_err(efx, hw, efx->net_dev,
1932                           "channel %d unknown driver event type %d"
1933                           " (data " EFX_QWORD_FMT ")\n",
1934                           channel->channel, subcode,
1935                           EFX_QWORD_VAL(*event));
1936
1937         }
1938 }
1939
1940 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
1941                                                    efx_qword_t *event)
1942 {
1943         struct efx_nic *efx = channel->efx;
1944         u32 subcode;
1945
1946         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
1947
1948         switch (subcode) {
1949         case EFX_EF10_TEST:
1950                 channel->event_test_cpu = raw_smp_processor_id();
1951                 break;
1952         case EFX_EF10_REFILL:
1953                 /* The queue must be empty, so we won't receive any rx
1954                  * events, so efx_process_channel() won't refill the
1955                  * queue. Refill it here
1956                  */
1957                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
1958                 break;
1959         default:
1960                 netif_err(efx, hw, efx->net_dev,
1961                           "channel %d unknown driver event type %u"
1962                           " (data " EFX_QWORD_FMT ")\n",
1963                           channel->channel, (unsigned) subcode,
1964                           EFX_QWORD_VAL(*event));
1965         }
1966 }
1967
1968 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
1969 {
1970         struct efx_nic *efx = channel->efx;
1971         efx_qword_t event, *p_event;
1972         unsigned int read_ptr;
1973         int ev_code;
1974         int tx_descs = 0;
1975         int spent = 0;
1976
1977         if (quota <= 0)
1978                 return spent;
1979
1980         read_ptr = channel->eventq_read_ptr;
1981
1982         for (;;) {
1983                 p_event = efx_event(channel, read_ptr);
1984                 event = *p_event;
1985
1986                 if (!efx_event_present(&event))
1987                         break;
1988
1989                 EFX_SET_QWORD(*p_event);
1990
1991                 ++read_ptr;
1992
1993                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
1994
1995                 netif_vdbg(efx, drv, efx->net_dev,
1996                            "processing event on %d " EFX_QWORD_FMT "\n",
1997                            channel->channel, EFX_QWORD_VAL(event));
1998
1999                 switch (ev_code) {
2000                 case ESE_DZ_EV_CODE_MCDI_EV:
2001                         efx_mcdi_process_event(channel, &event);
2002                         break;
2003                 case ESE_DZ_EV_CODE_RX_EV:
2004                         spent += efx_ef10_handle_rx_event(channel, &event);
2005                         if (spent >= quota) {
2006                                 /* XXX can we split a merged event to
2007                                  * avoid going over-quota?
2008                                  */
2009                                 spent = quota;
2010                                 goto out;
2011                         }
2012                         break;
2013                 case ESE_DZ_EV_CODE_TX_EV:
2014                         tx_descs += efx_ef10_handle_tx_event(channel, &event);
2015                         if (tx_descs > efx->txq_entries) {
2016                                 spent = quota;
2017                                 goto out;
2018                         } else if (++spent == quota) {
2019                                 goto out;
2020                         }
2021                         break;
2022                 case ESE_DZ_EV_CODE_DRIVER_EV:
2023                         efx_ef10_handle_driver_event(channel, &event);
2024                         if (++spent == quota)
2025                                 goto out;
2026                         break;
2027                 case EFX_EF10_DRVGEN_EV:
2028                         efx_ef10_handle_driver_generated_event(channel, &event);
2029                         break;
2030                 default:
2031                         netif_err(efx, hw, efx->net_dev,
2032                                   "channel %d unknown event type %d"
2033                                   " (data " EFX_QWORD_FMT ")\n",
2034                                   channel->channel, ev_code,
2035                                   EFX_QWORD_VAL(event));
2036                 }
2037         }
2038
2039 out:
2040         channel->eventq_read_ptr = read_ptr;
2041         return spent;
2042 }
2043
2044 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2045 {
2046         struct efx_nic *efx = channel->efx;
2047         efx_dword_t rptr;
2048
2049         if (EFX_EF10_WORKAROUND_35388(efx)) {
2050                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2051                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2052                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2053                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2054
2055                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2056                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2057                                      ERF_DD_EVQ_IND_RPTR,
2058                                      (channel->eventq_read_ptr &
2059                                       channel->eventq_mask) >>
2060                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
2061                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2062                                 channel->channel);
2063                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2064                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2065                                      ERF_DD_EVQ_IND_RPTR,
2066                                      channel->eventq_read_ptr &
2067                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2068                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2069                                 channel->channel);
2070         } else {
2071                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2072                                      channel->eventq_read_ptr &
2073                                      channel->eventq_mask);
2074                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2075         }
2076 }
2077
2078 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2079 {
2080         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2081         struct efx_nic *efx = channel->efx;
2082         efx_qword_t event;
2083         int rc;
2084
2085         EFX_POPULATE_QWORD_2(event,
2086                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2087                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
2088
2089         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2090
2091         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2092          * already swapped the data to little-endian order.
2093          */
2094         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2095                sizeof(efx_qword_t));
2096
2097         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2098                           NULL, 0, NULL);
2099         if (rc != 0)
2100                 goto fail;
2101
2102         return;
2103
2104 fail:
2105         WARN_ON(true);
2106         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2107 }
2108
2109 void efx_ef10_handle_drain_event(struct efx_nic *efx)
2110 {
2111         if (atomic_dec_and_test(&efx->active_queues))
2112                 wake_up(&efx->flush_wq);
2113
2114         WARN_ON(atomic_read(&efx->active_queues) < 0);
2115 }
2116
2117 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2118 {
2119         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2120         struct efx_channel *channel;
2121         struct efx_tx_queue *tx_queue;
2122         struct efx_rx_queue *rx_queue;
2123         int pending;
2124
2125         /* If the MC has just rebooted, the TX/RX queues will have already been
2126          * torn down, but efx->active_queues needs to be set to zero.
2127          */
2128         if (nic_data->must_realloc_vis) {
2129                 atomic_set(&efx->active_queues, 0);
2130                 return 0;
2131         }
2132
2133         /* Do not attempt to write to the NIC during EEH recovery */
2134         if (efx->state != STATE_RECOVERY) {
2135                 efx_for_each_channel(channel, efx) {
2136                         efx_for_each_channel_rx_queue(rx_queue, channel)
2137                                 efx_ef10_rx_fini(rx_queue);
2138                         efx_for_each_channel_tx_queue(tx_queue, channel)
2139                                 efx_ef10_tx_fini(tx_queue);
2140                 }
2141
2142                 wait_event_timeout(efx->flush_wq,
2143                                    atomic_read(&efx->active_queues) == 0,
2144                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2145                 pending = atomic_read(&efx->active_queues);
2146                 if (pending) {
2147                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2148                                   pending);
2149                         return -ETIMEDOUT;
2150                 }
2151         }
2152
2153         return 0;
2154 }
2155
2156 static void efx_ef10_prepare_flr(struct efx_nic *efx)
2157 {
2158         atomic_set(&efx->active_queues, 0);
2159 }
2160
2161 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2162                                   const struct efx_filter_spec *right)
2163 {
2164         if ((left->match_flags ^ right->match_flags) |
2165             ((left->flags ^ right->flags) &
2166              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2167                 return false;
2168
2169         return memcmp(&left->outer_vid, &right->outer_vid,
2170                       sizeof(struct efx_filter_spec) -
2171                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
2172 }
2173
2174 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2175 {
2176         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2177         return jhash2((const u32 *)&spec->outer_vid,
2178                       (sizeof(struct efx_filter_spec) -
2179                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
2180                       0);
2181         /* XXX should we randomise the initval? */
2182 }
2183
2184 /* Decide whether a filter should be exclusive or else should allow
2185  * delivery to additional recipients.  Currently we decide that
2186  * filters for specific local unicast MAC and IP addresses are
2187  * exclusive.
2188  */
2189 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2190 {
2191         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2192             !is_multicast_ether_addr(spec->loc_mac))
2193                 return true;
2194
2195         if ((spec->match_flags &
2196              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2197             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2198                 if (spec->ether_type == htons(ETH_P_IP) &&
2199                     !ipv4_is_multicast(spec->loc_host[0]))
2200                         return true;
2201                 if (spec->ether_type == htons(ETH_P_IPV6) &&
2202                     ((const u8 *)spec->loc_host)[0] != 0xff)
2203                         return true;
2204         }
2205
2206         return false;
2207 }
2208
2209 static struct efx_filter_spec *
2210 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2211                            unsigned int filter_idx)
2212 {
2213         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2214                                           ~EFX_EF10_FILTER_FLAGS);
2215 }
2216
2217 static unsigned int
2218 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2219                            unsigned int filter_idx)
2220 {
2221         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2222 }
2223
2224 static void
2225 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2226                           unsigned int filter_idx,
2227                           const struct efx_filter_spec *spec,
2228                           unsigned int flags)
2229 {
2230         table->entry[filter_idx].spec = (unsigned long)spec | flags;
2231 }
2232
2233 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2234                                       const struct efx_filter_spec *spec,
2235                                       efx_dword_t *inbuf, u64 handle,
2236                                       bool replacing)
2237 {
2238         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2239
2240         memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2241
2242         if (replacing) {
2243                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2244                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
2245                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2246         } else {
2247                 u32 match_fields = 0;
2248
2249                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2250                                efx_ef10_filter_is_exclusive(spec) ?
2251                                MC_CMD_FILTER_OP_IN_OP_INSERT :
2252                                MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2253
2254                 /* Convert match flags and values.  Unlike almost
2255                  * everything else in MCDI, these fields are in
2256                  * network byte order.
2257                  */
2258                 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2259                         match_fields |=
2260                                 is_multicast_ether_addr(spec->loc_mac) ?
2261                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2262                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2263 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
2264                 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
2265                         match_fields |=                                      \
2266                                 1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
2267                                 mcdi_field ## _LBN;                          \
2268                         BUILD_BUG_ON(                                        \
2269                                 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2270                                 sizeof(spec->gen_field));                    \
2271                         memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2272                                &spec->gen_field, sizeof(spec->gen_field));   \
2273                 }
2274                 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2275                 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2276                 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2277                 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2278                 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2279                 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2280                 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2281                 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2282                 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2283                 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2284 #undef COPY_FIELD
2285                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2286                                match_fields);
2287         }
2288
2289         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
2290         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2291                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2292                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2293                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2294         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2295                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2296         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2297                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2298                        0 : spec->dmaq_id);
2299         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2300                        (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2301                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2302                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2303         if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2304                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2305                                spec->rss_context !=
2306                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2307                                spec->rss_context : nic_data->rx_rss_context);
2308 }
2309
2310 static int efx_ef10_filter_push(struct efx_nic *efx,
2311                                 const struct efx_filter_spec *spec,
2312                                 u64 *handle, bool replacing)
2313 {
2314         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2315         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2316         int rc;
2317
2318         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2319         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2320                           outbuf, sizeof(outbuf), NULL);
2321         if (rc == 0)
2322                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2323         if (rc == -ENOSPC)
2324                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
2325         return rc;
2326 }
2327
2328 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2329                                         enum efx_filter_match_flags match_flags)
2330 {
2331         unsigned int match_pri;
2332
2333         for (match_pri = 0;
2334              match_pri < table->rx_match_count;
2335              match_pri++)
2336                 if (table->rx_match_flags[match_pri] == match_flags)
2337                         return match_pri;
2338
2339         return -EPROTONOSUPPORT;
2340 }
2341
2342 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2343                                   struct efx_filter_spec *spec,
2344                                   bool replace_equal)
2345 {
2346         struct efx_ef10_filter_table *table = efx->filter_state;
2347         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2348         struct efx_filter_spec *saved_spec;
2349         unsigned int match_pri, hash;
2350         unsigned int priv_flags;
2351         bool replacing = false;
2352         int ins_index = -1;
2353         DEFINE_WAIT(wait);
2354         bool is_mc_recip;
2355         s32 rc;
2356
2357         /* For now, only support RX filters */
2358         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2359             EFX_FILTER_FLAG_RX)
2360                 return -EINVAL;
2361
2362         rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2363         if (rc < 0)
2364                 return rc;
2365         match_pri = rc;
2366
2367         hash = efx_ef10_filter_hash(spec);
2368         is_mc_recip = efx_filter_is_mc_recipient(spec);
2369         if (is_mc_recip)
2370                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2371
2372         /* Find any existing filters with the same match tuple or
2373          * else a free slot to insert at.  If any of them are busy,
2374          * we have to wait and retry.
2375          */
2376         for (;;) {
2377                 unsigned int depth = 1;
2378                 unsigned int i;
2379
2380                 spin_lock_bh(&efx->filter_lock);
2381
2382                 for (;;) {
2383                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2384                         saved_spec = efx_ef10_filter_entry_spec(table, i);
2385
2386                         if (!saved_spec) {
2387                                 if (ins_index < 0)
2388                                         ins_index = i;
2389                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2390                                 if (table->entry[i].spec &
2391                                     EFX_EF10_FILTER_FLAG_BUSY)
2392                                         break;
2393                                 if (spec->priority < saved_spec->priority &&
2394                                     spec->priority != EFX_FILTER_PRI_AUTO) {
2395                                         rc = -EPERM;
2396                                         goto out_unlock;
2397                                 }
2398                                 if (!is_mc_recip) {
2399                                         /* This is the only one */
2400                                         if (spec->priority ==
2401                                             saved_spec->priority &&
2402                                             !replace_equal) {
2403                                                 rc = -EEXIST;
2404                                                 goto out_unlock;
2405                                         }
2406                                         ins_index = i;
2407                                         goto found;
2408                                 } else if (spec->priority >
2409                                            saved_spec->priority ||
2410                                            (spec->priority ==
2411                                             saved_spec->priority &&
2412                                             replace_equal)) {
2413                                         if (ins_index < 0)
2414                                                 ins_index = i;
2415                                         else
2416                                                 __set_bit(depth, mc_rem_map);
2417                                 }
2418                         }
2419
2420                         /* Once we reach the maximum search depth, use
2421                          * the first suitable slot or return -EBUSY if
2422                          * there was none
2423                          */
2424                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2425                                 if (ins_index < 0) {
2426                                         rc = -EBUSY;
2427                                         goto out_unlock;
2428                                 }
2429                                 goto found;
2430                         }
2431
2432                         ++depth;
2433                 }
2434
2435                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2436                 spin_unlock_bh(&efx->filter_lock);
2437                 schedule();
2438         }
2439
2440 found:
2441         /* Create a software table entry if necessary, and mark it
2442          * busy.  We might yet fail to insert, but any attempt to
2443          * insert a conflicting filter while we're waiting for the
2444          * firmware must find the busy entry.
2445          */
2446         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2447         if (saved_spec) {
2448                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
2449                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
2450                         /* Just make sure it won't be removed */
2451                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
2452                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
2453                         table->entry[ins_index].spec &=
2454                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2455                         rc = ins_index;
2456                         goto out_unlock;
2457                 }
2458                 replacing = true;
2459                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2460         } else {
2461                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2462                 if (!saved_spec) {
2463                         rc = -ENOMEM;
2464                         goto out_unlock;
2465                 }
2466                 *saved_spec = *spec;
2467                 priv_flags = 0;
2468         }
2469         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2470                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2471
2472         /* Mark lower-priority multicast recipients busy prior to removal */
2473         if (is_mc_recip) {
2474                 unsigned int depth, i;
2475
2476                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2477                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2478                         if (test_bit(depth, mc_rem_map))
2479                                 table->entry[i].spec |=
2480                                         EFX_EF10_FILTER_FLAG_BUSY;
2481                 }
2482         }
2483
2484         spin_unlock_bh(&efx->filter_lock);
2485
2486         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2487                                   replacing);
2488
2489         /* Finalise the software table entry */
2490         spin_lock_bh(&efx->filter_lock);
2491         if (rc == 0) {
2492                 if (replacing) {
2493                         /* Update the fields that may differ */
2494                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
2495                                 saved_spec->flags |=
2496                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
2497                         saved_spec->priority = spec->priority;
2498                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
2499                         saved_spec->flags |= spec->flags;
2500                         saved_spec->rss_context = spec->rss_context;
2501                         saved_spec->dmaq_id = spec->dmaq_id;
2502                 }
2503         } else if (!replacing) {
2504                 kfree(saved_spec);
2505                 saved_spec = NULL;
2506         }
2507         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2508
2509         /* Remove and finalise entries for lower-priority multicast
2510          * recipients
2511          */
2512         if (is_mc_recip) {
2513                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2514                 unsigned int depth, i;
2515
2516                 memset(inbuf, 0, sizeof(inbuf));
2517
2518                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2519                         if (!test_bit(depth, mc_rem_map))
2520                                 continue;
2521
2522                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2523                         saved_spec = efx_ef10_filter_entry_spec(table, i);
2524                         priv_flags = efx_ef10_filter_entry_flags(table, i);
2525
2526                         if (rc == 0) {
2527                                 spin_unlock_bh(&efx->filter_lock);
2528                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2529                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2530                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2531                                                table->entry[i].handle);
2532                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2533                                                   inbuf, sizeof(inbuf),
2534                                                   NULL, 0, NULL);
2535                                 spin_lock_bh(&efx->filter_lock);
2536                         }
2537
2538                         if (rc == 0) {
2539                                 kfree(saved_spec);
2540                                 saved_spec = NULL;
2541                                 priv_flags = 0;
2542                         } else {
2543                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2544                         }
2545                         efx_ef10_filter_set_entry(table, i, saved_spec,
2546                                                   priv_flags);
2547                 }
2548         }
2549
2550         /* If successful, return the inserted filter ID */
2551         if (rc == 0)
2552                 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2553
2554         wake_up_all(&table->waitq);
2555 out_unlock:
2556         spin_unlock_bh(&efx->filter_lock);
2557         finish_wait(&table->waitq, &wait);
2558         return rc;
2559 }
2560
2561 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
2562 {
2563         /* no need to do anything here on EF10 */
2564 }
2565
2566 /* Remove a filter.
2567  * If !by_index, remove by ID
2568  * If by_index, remove by index
2569  * Filter ID may come from userland and must be range-checked.
2570  */
2571 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
2572                                            unsigned int priority_mask,
2573                                            u32 filter_id, bool by_index)
2574 {
2575         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2576         struct efx_ef10_filter_table *table = efx->filter_state;
2577         MCDI_DECLARE_BUF(inbuf,
2578                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2579                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2580         struct efx_filter_spec *spec;
2581         DEFINE_WAIT(wait);
2582         int rc;
2583
2584         /* Find the software table entry and mark it busy.  Don't
2585          * remove it yet; any attempt to update while we're waiting
2586          * for the firmware must find the busy entry.
2587          */
2588         for (;;) {
2589                 spin_lock_bh(&efx->filter_lock);
2590                 if (!(table->entry[filter_idx].spec &
2591                       EFX_EF10_FILTER_FLAG_BUSY))
2592                         break;
2593                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2594                 spin_unlock_bh(&efx->filter_lock);
2595                 schedule();
2596         }
2597
2598         spec = efx_ef10_filter_entry_spec(table, filter_idx);
2599         if (!spec ||
2600             (!by_index &&
2601              efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2602              filter_id / HUNT_FILTER_TBL_ROWS)) {
2603                 rc = -ENOENT;
2604                 goto out_unlock;
2605         }
2606
2607         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
2608             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
2609                 /* Just remove flags */
2610                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
2611                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2612                 rc = 0;
2613                 goto out_unlock;
2614         }
2615
2616         if (!(priority_mask & (1U << spec->priority))) {
2617                 rc = -ENOENT;
2618                 goto out_unlock;
2619         }
2620
2621         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2622         spin_unlock_bh(&efx->filter_lock);
2623
2624         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
2625                 /* Reset to an automatic filter */
2626
2627                 struct efx_filter_spec new_spec = *spec;
2628
2629                 new_spec.priority = EFX_FILTER_PRI_AUTO;
2630                 new_spec.flags = (EFX_FILTER_FLAG_RX |
2631                                   EFX_FILTER_FLAG_RX_RSS);
2632                 new_spec.dmaq_id = 0;
2633                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2634                 rc = efx_ef10_filter_push(efx, &new_spec,
2635                                           &table->entry[filter_idx].handle,
2636                                           true);
2637
2638                 spin_lock_bh(&efx->filter_lock);
2639                 if (rc == 0)
2640                         *spec = new_spec;
2641         } else {
2642                 /* Really remove the filter */
2643
2644                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2645                                efx_ef10_filter_is_exclusive(spec) ?
2646                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
2647                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2648                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2649                                table->entry[filter_idx].handle);
2650                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2651                                   inbuf, sizeof(inbuf), NULL, 0, NULL);
2652
2653                 spin_lock_bh(&efx->filter_lock);
2654                 if (rc == 0) {
2655                         kfree(spec);
2656                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2657                 }
2658         }
2659
2660         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2661         wake_up_all(&table->waitq);
2662 out_unlock:
2663         spin_unlock_bh(&efx->filter_lock);
2664         finish_wait(&table->waitq, &wait);
2665         return rc;
2666 }
2667
2668 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
2669                                        enum efx_filter_priority priority,
2670                                        u32 filter_id)
2671 {
2672         return efx_ef10_filter_remove_internal(efx, 1U << priority,
2673                                                filter_id, false);
2674 }
2675
2676 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
2677                                     enum efx_filter_priority priority,
2678                                     u32 filter_id, struct efx_filter_spec *spec)
2679 {
2680         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2681         struct efx_ef10_filter_table *table = efx->filter_state;
2682         const struct efx_filter_spec *saved_spec;
2683         int rc;
2684
2685         spin_lock_bh(&efx->filter_lock);
2686         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
2687         if (saved_spec && saved_spec->priority == priority &&
2688             efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
2689             filter_id / HUNT_FILTER_TBL_ROWS) {
2690                 *spec = *saved_spec;
2691                 rc = 0;
2692         } else {
2693                 rc = -ENOENT;
2694         }
2695         spin_unlock_bh(&efx->filter_lock);
2696         return rc;
2697 }
2698
2699 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
2700                                      enum efx_filter_priority priority)
2701 {
2702         unsigned int priority_mask;
2703         unsigned int i;
2704         int rc;
2705
2706         priority_mask = (((1U << (priority + 1)) - 1) &
2707                          ~(1U << EFX_FILTER_PRI_AUTO));
2708
2709         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
2710                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
2711                                                      i, true);
2712                 if (rc && rc != -ENOENT)
2713                         return rc;
2714         }
2715
2716         return 0;
2717 }
2718
2719 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
2720                                          enum efx_filter_priority priority)
2721 {
2722         struct efx_ef10_filter_table *table = efx->filter_state;
2723         unsigned int filter_idx;
2724         s32 count = 0;
2725
2726         spin_lock_bh(&efx->filter_lock);
2727         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2728                 if (table->entry[filter_idx].spec &&
2729                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
2730                     priority)
2731                         ++count;
2732         }
2733         spin_unlock_bh(&efx->filter_lock);
2734         return count;
2735 }
2736
2737 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
2738 {
2739         struct efx_ef10_filter_table *table = efx->filter_state;
2740
2741         return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
2742 }
2743
2744 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
2745                                       enum efx_filter_priority priority,
2746                                       u32 *buf, u32 size)
2747 {
2748         struct efx_ef10_filter_table *table = efx->filter_state;
2749         struct efx_filter_spec *spec;
2750         unsigned int filter_idx;
2751         s32 count = 0;
2752
2753         spin_lock_bh(&efx->filter_lock);
2754         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2755                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2756                 if (spec && spec->priority == priority) {
2757                         if (count == size) {
2758                                 count = -EMSGSIZE;
2759                                 break;
2760                         }
2761                         buf[count++] = (efx_ef10_filter_rx_match_pri(
2762                                                 table, spec->match_flags) *
2763                                         HUNT_FILTER_TBL_ROWS +
2764                                         filter_idx);
2765                 }
2766         }
2767         spin_unlock_bh(&efx->filter_lock);
2768         return count;
2769 }
2770
2771 #ifdef CONFIG_RFS_ACCEL
2772
2773 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
2774
2775 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
2776                                       struct efx_filter_spec *spec)
2777 {
2778         struct efx_ef10_filter_table *table = efx->filter_state;
2779         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2780         struct efx_filter_spec *saved_spec;
2781         unsigned int hash, i, depth = 1;
2782         bool replacing = false;
2783         int ins_index = -1;
2784         u64 cookie;
2785         s32 rc;
2786
2787         /* Must be an RX filter without RSS and not for a multicast
2788          * destination address (RFS only works for connected sockets).
2789          * These restrictions allow us to pass only a tiny amount of
2790          * data through to the completion function.
2791          */
2792         EFX_WARN_ON_PARANOID(spec->flags !=
2793                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
2794         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
2795         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
2796
2797         hash = efx_ef10_filter_hash(spec);
2798
2799         spin_lock_bh(&efx->filter_lock);
2800
2801         /* Find any existing filter with the same match tuple or else
2802          * a free slot to insert at.  If an existing filter is busy,
2803          * we have to give up.
2804          */
2805         for (;;) {
2806                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2807                 saved_spec = efx_ef10_filter_entry_spec(table, i);
2808
2809                 if (!saved_spec) {
2810                         if (ins_index < 0)
2811                                 ins_index = i;
2812                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2813                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
2814                                 rc = -EBUSY;
2815                                 goto fail_unlock;
2816                         }
2817                         if (spec->priority < saved_spec->priority) {
2818                                 rc = -EPERM;
2819                                 goto fail_unlock;
2820                         }
2821                         ins_index = i;
2822                         break;
2823                 }
2824
2825                 /* Once we reach the maximum search depth, use the
2826                  * first suitable slot or return -EBUSY if there was
2827                  * none
2828                  */
2829                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2830                         if (ins_index < 0) {
2831                                 rc = -EBUSY;
2832                                 goto fail_unlock;
2833                         }
2834                         break;
2835                 }
2836
2837                 ++depth;
2838         }
2839
2840         /* Create a software table entry if necessary, and mark it
2841          * busy.  We might yet fail to insert, but any attempt to
2842          * insert a conflicting filter while we're waiting for the
2843          * firmware must find the busy entry.
2844          */
2845         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2846         if (saved_spec) {
2847                 replacing = true;
2848         } else {
2849                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2850                 if (!saved_spec) {
2851                         rc = -ENOMEM;
2852                         goto fail_unlock;
2853                 }
2854                 *saved_spec = *spec;
2855         }
2856         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2857                                   EFX_EF10_FILTER_FLAG_BUSY);
2858
2859         spin_unlock_bh(&efx->filter_lock);
2860
2861         /* Pack up the variables needed on completion */
2862         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
2863
2864         efx_ef10_filter_push_prep(efx, spec, inbuf,
2865                                   table->entry[ins_index].handle, replacing);
2866         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2867                            MC_CMD_FILTER_OP_OUT_LEN,
2868                            efx_ef10_filter_rfs_insert_complete, cookie);
2869
2870         return ins_index;
2871
2872 fail_unlock:
2873         spin_unlock_bh(&efx->filter_lock);
2874         return rc;
2875 }
2876
2877 static void
2878 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
2879                                     int rc, efx_dword_t *outbuf,
2880                                     size_t outlen_actual)
2881 {
2882         struct efx_ef10_filter_table *table = efx->filter_state;
2883         unsigned int ins_index, dmaq_id;
2884         struct efx_filter_spec *spec;
2885         bool replacing;
2886
2887         /* Unpack the cookie */
2888         replacing = cookie >> 31;
2889         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
2890         dmaq_id = cookie & 0xffff;
2891
2892         spin_lock_bh(&efx->filter_lock);
2893         spec = efx_ef10_filter_entry_spec(table, ins_index);
2894         if (rc == 0) {
2895                 table->entry[ins_index].handle =
2896                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2897                 if (replacing)
2898                         spec->dmaq_id = dmaq_id;
2899         } else if (!replacing) {
2900                 kfree(spec);
2901                 spec = NULL;
2902         }
2903         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
2904         spin_unlock_bh(&efx->filter_lock);
2905
2906         wake_up_all(&table->waitq);
2907 }
2908
2909 static void
2910 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2911                                     unsigned long filter_idx,
2912                                     int rc, efx_dword_t *outbuf,
2913                                     size_t outlen_actual);
2914
2915 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2916                                            unsigned int filter_idx)
2917 {
2918         struct efx_ef10_filter_table *table = efx->filter_state;
2919         struct efx_filter_spec *spec =
2920                 efx_ef10_filter_entry_spec(table, filter_idx);
2921         MCDI_DECLARE_BUF(inbuf,
2922                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2923                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2924
2925         if (!spec ||
2926             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
2927             spec->priority != EFX_FILTER_PRI_HINT ||
2928             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
2929                                  flow_id, filter_idx))
2930                 return false;
2931
2932         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2933                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
2934         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2935                        table->entry[filter_idx].handle);
2936         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
2937                                efx_ef10_filter_rfs_expire_complete, filter_idx))
2938                 return false;
2939
2940         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2941         return true;
2942 }
2943
2944 static void
2945 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2946                                     unsigned long filter_idx,
2947                                     int rc, efx_dword_t *outbuf,
2948                                     size_t outlen_actual)
2949 {
2950         struct efx_ef10_filter_table *table = efx->filter_state;
2951         struct efx_filter_spec *spec =
2952                 efx_ef10_filter_entry_spec(table, filter_idx);
2953
2954         spin_lock_bh(&efx->filter_lock);
2955         if (rc == 0) {
2956                 kfree(spec);
2957                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2958         }
2959         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2960         wake_up_all(&table->waitq);
2961         spin_unlock_bh(&efx->filter_lock);
2962 }
2963
2964 #endif /* CONFIG_RFS_ACCEL */
2965
2966 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
2967 {
2968         int match_flags = 0;
2969
2970 #define MAP_FLAG(gen_flag, mcdi_field) {                                \
2971                 u32 old_mcdi_flags = mcdi_flags;                        \
2972                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ##      \
2973                                 mcdi_field ## _LBN);                    \
2974                 if (mcdi_flags != old_mcdi_flags)                       \
2975                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
2976         }
2977         MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
2978         MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
2979         MAP_FLAG(REM_HOST, SRC_IP);
2980         MAP_FLAG(LOC_HOST, DST_IP);
2981         MAP_FLAG(REM_MAC, SRC_MAC);
2982         MAP_FLAG(REM_PORT, SRC_PORT);
2983         MAP_FLAG(LOC_MAC, DST_MAC);
2984         MAP_FLAG(LOC_PORT, DST_PORT);
2985         MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
2986         MAP_FLAG(INNER_VID, INNER_VLAN);
2987         MAP_FLAG(OUTER_VID, OUTER_VLAN);
2988         MAP_FLAG(IP_PROTO, IP_PROTO);
2989 #undef MAP_FLAG
2990
2991         /* Did we map them all? */
2992         if (mcdi_flags)
2993                 return -EINVAL;
2994
2995         return match_flags;
2996 }
2997
2998 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
2999 {
3000         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3001         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3002         unsigned int pd_match_pri, pd_match_count;
3003         struct efx_ef10_filter_table *table;
3004         size_t outlen;
3005         int rc;
3006
3007         table = kzalloc(sizeof(*table), GFP_KERNEL);
3008         if (!table)
3009                 return -ENOMEM;
3010
3011         /* Find out which RX filter types are supported, and their priorities */
3012         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3013                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3014         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3015                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3016                           &outlen);
3017         if (rc)
3018                 goto fail;
3019         pd_match_count = MCDI_VAR_ARRAY_LEN(
3020                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3021         table->rx_match_count = 0;
3022
3023         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3024                 u32 mcdi_flags =
3025                         MCDI_ARRAY_DWORD(
3026                                 outbuf,
3027                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3028                                 pd_match_pri);
3029                 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3030                 if (rc < 0) {
3031                         netif_dbg(efx, probe, efx->net_dev,
3032                                   "%s: fw flags %#x pri %u not supported in driver\n",
3033                                   __func__, mcdi_flags, pd_match_pri);
3034                 } else {
3035                         netif_dbg(efx, probe, efx->net_dev,
3036                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3037                                   __func__, mcdi_flags, pd_match_pri,
3038                                   rc, table->rx_match_count);
3039                         table->rx_match_flags[table->rx_match_count++] = rc;
3040                 }
3041         }
3042
3043         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3044         if (!table->entry) {
3045                 rc = -ENOMEM;
3046                 goto fail;
3047         }
3048
3049         efx->filter_state = table;
3050         init_waitqueue_head(&table->waitq);
3051         return 0;
3052
3053 fail:
3054         kfree(table);
3055         return rc;
3056 }
3057
3058 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3059 {
3060         struct efx_ef10_filter_table *table = efx->filter_state;
3061         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3062         struct efx_filter_spec *spec;
3063         unsigned int filter_idx;
3064         bool failed = false;
3065         int rc;
3066
3067         if (!nic_data->must_restore_filters)
3068                 return;
3069
3070         spin_lock_bh(&efx->filter_lock);
3071
3072         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3073                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3074                 if (!spec)
3075                         continue;
3076
3077                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3078                 spin_unlock_bh(&efx->filter_lock);
3079
3080                 rc = efx_ef10_filter_push(efx, spec,
3081                                           &table->entry[filter_idx].handle,
3082                                           false);
3083                 if (rc)
3084                         failed = true;
3085
3086                 spin_lock_bh(&efx->filter_lock);
3087                 if (rc) {
3088                         kfree(spec);
3089                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3090                 } else {
3091                         table->entry[filter_idx].spec &=
3092                                 ~EFX_EF10_FILTER_FLAG_BUSY;
3093                 }
3094         }
3095
3096         spin_unlock_bh(&efx->filter_lock);
3097
3098         if (failed)
3099                 netif_err(efx, hw, efx->net_dev,
3100                           "unable to restore all filters\n");
3101         else
3102                 nic_data->must_restore_filters = false;
3103 }
3104
3105 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3106 {
3107         struct efx_ef10_filter_table *table = efx->filter_state;
3108         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3109         struct efx_filter_spec *spec;
3110         unsigned int filter_idx;
3111         int rc;
3112
3113         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3114                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3115                 if (!spec)
3116                         continue;
3117
3118                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3119                                efx_ef10_filter_is_exclusive(spec) ?
3120                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
3121                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3122                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3123                                table->entry[filter_idx].handle);
3124                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3125                                   NULL, 0, NULL);
3126                 if (rc)
3127                         netdev_WARN(efx->net_dev,
3128                                     "filter_idx=%#x handle=%#llx\n",
3129                                     filter_idx,
3130                                     table->entry[filter_idx].handle);
3131                 kfree(spec);
3132         }
3133
3134         vfree(table->entry);
3135         kfree(table);
3136 }
3137
3138 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
3139 {
3140         struct efx_ef10_filter_table *table = efx->filter_state;
3141         struct net_device *net_dev = efx->net_dev;
3142         struct efx_filter_spec spec;
3143         bool remove_failed = false;
3144         struct netdev_hw_addr *uc;
3145         struct netdev_hw_addr *mc;
3146         unsigned int filter_idx;
3147         int i, n, rc;
3148
3149         if (!efx_dev_registered(efx))
3150                 return;
3151
3152         /* Mark old filters that may need to be removed */
3153         spin_lock_bh(&efx->filter_lock);
3154         n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count;
3155         for (i = 0; i < n; i++) {
3156                 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
3157                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3158         }
3159         n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count;
3160         for (i = 0; i < n; i++) {
3161                 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
3162                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3163         }
3164         spin_unlock_bh(&efx->filter_lock);
3165
3166         /* Copy/convert the address lists; add the primary station
3167          * address and broadcast address
3168          */
3169         netif_addr_lock_bh(net_dev);
3170         if (net_dev->flags & IFF_PROMISC ||
3171             netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) {
3172                 table->dev_uc_count = -1;
3173         } else {
3174                 table->dev_uc_count = 1 + netdev_uc_count(net_dev);
3175                 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3176                 i = 1;
3177                 netdev_for_each_uc_addr(uc, net_dev) {
3178                         ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
3179                         i++;
3180                 }
3181         }
3182         if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
3183             netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) {
3184                 table->dev_mc_count = -1;
3185         } else {
3186                 table->dev_mc_count = 1 + netdev_mc_count(net_dev);
3187                 eth_broadcast_addr(table->dev_mc_list[0].addr);
3188                 i = 1;
3189                 netdev_for_each_mc_addr(mc, net_dev) {
3190                         ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
3191                         i++;
3192                 }
3193         }
3194         netif_addr_unlock_bh(net_dev);
3195
3196         /* Insert/renew unicast filters */
3197         if (table->dev_uc_count >= 0) {
3198                 for (i = 0; i < table->dev_uc_count; i++) {
3199                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3200                                            EFX_FILTER_FLAG_RX_RSS,
3201                                            0);
3202                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3203                                                  table->dev_uc_list[i].addr);
3204                         rc = efx_ef10_filter_insert(efx, &spec, true);
3205                         if (rc < 0) {
3206                                 /* Fall back to unicast-promisc */
3207                                 while (i--)
3208                                         efx_ef10_filter_remove_safe(
3209                                                 efx, EFX_FILTER_PRI_AUTO,
3210                                                 table->dev_uc_list[i].id);
3211                                 table->dev_uc_count = -1;
3212                                 break;
3213                         }
3214                         table->dev_uc_list[i].id = rc;
3215                 }
3216         }
3217         if (table->dev_uc_count < 0) {
3218                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3219                                    EFX_FILTER_FLAG_RX_RSS,
3220                                    0);
3221                 efx_filter_set_uc_def(&spec);
3222                 rc = efx_ef10_filter_insert(efx, &spec, true);
3223                 if (rc < 0) {
3224                         WARN_ON(1);
3225                         table->dev_uc_count = 0;
3226                 } else {
3227                         table->dev_uc_list[0].id = rc;
3228                 }
3229         }
3230
3231         /* Insert/renew multicast filters */
3232         if (table->dev_mc_count >= 0) {
3233                 for (i = 0; i < table->dev_mc_count; i++) {
3234                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3235                                            EFX_FILTER_FLAG_RX_RSS,
3236                                            0);
3237                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3238                                                  table->dev_mc_list[i].addr);
3239                         rc = efx_ef10_filter_insert(efx, &spec, true);
3240                         if (rc < 0) {
3241                                 /* Fall back to multicast-promisc */
3242                                 while (i--)
3243                                         efx_ef10_filter_remove_safe(
3244                                                 efx, EFX_FILTER_PRI_AUTO,
3245                                                 table->dev_mc_list[i].id);
3246                                 table->dev_mc_count = -1;
3247                                 break;
3248                         }
3249                         table->dev_mc_list[i].id = rc;
3250                 }
3251         }
3252         if (table->dev_mc_count < 0) {
3253                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3254                                    EFX_FILTER_FLAG_RX_RSS,
3255                                    0);
3256                 efx_filter_set_mc_def(&spec);
3257                 rc = efx_ef10_filter_insert(efx, &spec, true);
3258                 if (rc < 0) {
3259                         WARN_ON(1);
3260                         table->dev_mc_count = 0;
3261                 } else {
3262                         table->dev_mc_list[0].id = rc;
3263                 }
3264         }
3265
3266         /* Remove filters that weren't renewed.  Since nothing else
3267          * changes the AUTO_OLD flag or removes these filters, we
3268          * don't need to hold the filter_lock while scanning for
3269          * these filters.
3270          */
3271         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3272                 if (ACCESS_ONCE(table->entry[i].spec) &
3273                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
3274                         if (efx_ef10_filter_remove_internal(
3275                                     efx, 1U << EFX_FILTER_PRI_AUTO,
3276                                     i, true) < 0)
3277                                 remove_failed = true;
3278                 }
3279         }
3280         WARN_ON(remove_failed);
3281 }
3282
3283 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
3284 {
3285         efx_ef10_filter_sync_rx_mode(efx);
3286
3287         return efx_mcdi_set_mac(efx);
3288 }
3289
3290 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3291 {
3292         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3293
3294         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3295         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3296                             NULL, 0, NULL);
3297 }
3298
3299 /* MC BISTs follow a different poll mechanism to phy BISTs.
3300  * The BIST is done in the poll handler on the MC, and the MCDI command
3301  * will block until the BIST is done.
3302  */
3303 static int efx_ef10_poll_bist(struct efx_nic *efx)
3304 {
3305         int rc;
3306         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3307         size_t outlen;
3308         u32 result;
3309
3310         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3311                            outbuf, sizeof(outbuf), &outlen);
3312         if (rc != 0)
3313                 return rc;
3314
3315         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3316                 return -EIO;
3317
3318         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3319         switch (result) {
3320         case MC_CMD_POLL_BIST_PASSED:
3321                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3322                 return 0;
3323         case MC_CMD_POLL_BIST_TIMEOUT:
3324                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3325                 return -EIO;
3326         case MC_CMD_POLL_BIST_FAILED:
3327                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3328                 return -EIO;
3329         default:
3330                 netif_err(efx, hw, efx->net_dev,
3331                           "BIST returned unknown result %u", result);
3332                 return -EIO;
3333         }
3334 }
3335
3336 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3337 {
3338         int rc;
3339
3340         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3341
3342         rc = efx_ef10_start_bist(efx, bist_type);
3343         if (rc != 0)
3344                 return rc;
3345
3346         return efx_ef10_poll_bist(efx);
3347 }
3348
3349 static int
3350 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3351 {
3352         int rc, rc2;
3353
3354         efx_reset_down(efx, RESET_TYPE_WORLD);
3355
3356         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3357                           NULL, 0, NULL, 0, NULL);
3358         if (rc != 0)
3359                 goto out;
3360
3361         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3362         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3363
3364         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3365
3366 out:
3367         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3368         return rc ? rc : rc2;
3369 }
3370
3371 #ifdef CONFIG_SFC_MTD
3372
3373 struct efx_ef10_nvram_type_info {
3374         u16 type, type_mask;
3375         u8 port;
3376         const char *name;
3377 };
3378
3379 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3380         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
3381         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
3382         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
3383         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
3384         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
3385         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
3386         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
3387         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
3388         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
3389         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
3390         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
3391 };
3392
3393 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3394                                         struct efx_mcdi_mtd_partition *part,
3395                                         unsigned int type)
3396 {
3397         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3398         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3399         const struct efx_ef10_nvram_type_info *info;
3400         size_t size, erase_size, outlen;
3401         bool protected;
3402         int rc;
3403
3404         for (info = efx_ef10_nvram_types; ; info++) {
3405                 if (info ==
3406                     efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
3407                         return -ENODEV;
3408                 if ((type & ~info->type_mask) == info->type)
3409                         break;
3410         }
3411         if (info->port != efx_port_num(efx))
3412                 return -ENODEV;
3413
3414         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3415         if (rc)
3416                 return rc;
3417         if (protected)
3418                 return -ENODEV; /* hide it */
3419
3420         part->nvram_type = type;
3421
3422         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3423         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3424                           outbuf, sizeof(outbuf), &outlen);
3425         if (rc)
3426                 return rc;
3427         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3428                 return -EIO;
3429         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3430             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3431                 part->fw_subtype = MCDI_DWORD(outbuf,
3432                                               NVRAM_METADATA_OUT_SUBTYPE);
3433
3434         part->common.dev_type_name = "EF10 NVRAM manager";
3435         part->common.type_name = info->name;
3436
3437         part->common.mtd.type = MTD_NORFLASH;
3438         part->common.mtd.flags = MTD_CAP_NORFLASH;
3439         part->common.mtd.size = size;
3440         part->common.mtd.erasesize = erase_size;
3441
3442         return 0;
3443 }
3444
3445 static int efx_ef10_mtd_probe(struct efx_nic *efx)
3446 {
3447         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
3448         struct efx_mcdi_mtd_partition *parts;
3449         size_t outlen, n_parts_total, i, n_parts;
3450         unsigned int type;
3451         int rc;
3452
3453         ASSERT_RTNL();
3454
3455         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3456         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3457                           outbuf, sizeof(outbuf), &outlen);
3458         if (rc)
3459                 return rc;
3460         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3461                 return -EIO;
3462
3463         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3464         if (n_parts_total >
3465             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3466                 return -EIO;
3467
3468         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3469         if (!parts)
3470                 return -ENOMEM;
3471
3472         n_parts = 0;
3473         for (i = 0; i < n_parts_total; i++) {
3474                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3475                                         i);
3476                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
3477                 if (rc == 0)
3478                         n_parts++;
3479                 else if (rc != -ENODEV)
3480                         goto fail;
3481         }
3482
3483         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3484 fail:
3485         if (rc)
3486                 kfree(parts);
3487         return rc;
3488 }
3489
3490 #endif /* CONFIG_SFC_MTD */
3491
3492 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3493 {
3494         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3495 }
3496
3497 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3498                                            bool temp)
3499 {
3500         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3501         int rc;
3502
3503         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3504             channel->sync_events_state == SYNC_EVENTS_VALID ||
3505             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3506                 return 0;
3507         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3508
3509         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3510         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3511         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3512                        channel->channel);
3513
3514         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3515                           inbuf, sizeof(inbuf), NULL, 0, NULL);
3516
3517         if (rc != 0)
3518                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3519                                                     SYNC_EVENTS_DISABLED;
3520
3521         return rc;
3522 }
3523
3524 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3525                                             bool temp)
3526 {
3527         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3528         int rc;
3529
3530         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3531             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3532                 return 0;
3533         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3534                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3535                 return 0;
3536         }
3537         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3538                                             SYNC_EVENTS_DISABLED;
3539
3540         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
3541         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3542         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
3543                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
3544         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
3545                        channel->channel);
3546
3547         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3548                           inbuf, sizeof(inbuf), NULL, 0, NULL);
3549
3550         return rc;
3551 }
3552
3553 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
3554                                            bool temp)
3555 {
3556         int (*set)(struct efx_channel *channel, bool temp);
3557         struct efx_channel *channel;
3558
3559         set = en ?
3560               efx_ef10_rx_enable_timestamping :
3561               efx_ef10_rx_disable_timestamping;
3562
3563         efx_for_each_channel(channel, efx) {
3564                 int rc = set(channel, temp);
3565                 if (en && rc != 0) {
3566                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
3567                         return rc;
3568                 }
3569         }
3570
3571         return 0;
3572 }
3573
3574 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
3575                                       struct hwtstamp_config *init)
3576 {
3577         int rc;
3578
3579         switch (init->rx_filter) {
3580         case HWTSTAMP_FILTER_NONE:
3581                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
3582                 /* if TX timestamping is still requested then leave PTP on */
3583                 return efx_ptp_change_mode(efx,
3584                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
3585         case HWTSTAMP_FILTER_ALL:
3586         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3587         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3588         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3589         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3590         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3591         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3592         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3593         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3594         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3595         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3596         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3597         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3598                 init->rx_filter = HWTSTAMP_FILTER_ALL;
3599                 rc = efx_ptp_change_mode(efx, true, 0);
3600                 if (!rc)
3601                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
3602                 if (rc)
3603                         efx_ptp_change_mode(efx, false, 0);
3604                 return rc;
3605         default:
3606                 return -ERANGE;
3607         }
3608 }
3609
3610 const struct efx_nic_type efx_hunt_a0_nic_type = {
3611         .mem_map_size = efx_ef10_mem_map_size,
3612         .probe = efx_ef10_probe,
3613         .remove = efx_ef10_remove,
3614         .dimension_resources = efx_ef10_dimension_resources,
3615         .init = efx_ef10_init_nic,
3616         .fini = efx_port_dummy_op_void,
3617         .map_reset_reason = efx_mcdi_map_reset_reason,
3618         .map_reset_flags = efx_ef10_map_reset_flags,
3619         .reset = efx_ef10_reset,
3620         .probe_port = efx_mcdi_port_probe,
3621         .remove_port = efx_mcdi_port_remove,
3622         .fini_dmaq = efx_ef10_fini_dmaq,
3623         .prepare_flr = efx_ef10_prepare_flr,
3624         .finish_flr = efx_port_dummy_op_void,
3625         .describe_stats = efx_ef10_describe_stats,
3626         .update_stats = efx_ef10_update_stats,
3627         .start_stats = efx_mcdi_mac_start_stats,
3628         .pull_stats = efx_mcdi_mac_pull_stats,
3629         .stop_stats = efx_mcdi_mac_stop_stats,
3630         .set_id_led = efx_mcdi_set_id_led,
3631         .push_irq_moderation = efx_ef10_push_irq_moderation,
3632         .reconfigure_mac = efx_ef10_mac_reconfigure,
3633         .check_mac_fault = efx_mcdi_mac_check_fault,
3634         .reconfigure_port = efx_mcdi_port_reconfigure,
3635         .get_wol = efx_ef10_get_wol,
3636         .set_wol = efx_ef10_set_wol,
3637         .resume_wol = efx_port_dummy_op_void,
3638         .test_chip = efx_ef10_test_chip,
3639         .test_nvram = efx_mcdi_nvram_test_all,
3640         .mcdi_request = efx_ef10_mcdi_request,
3641         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
3642         .mcdi_read_response = efx_ef10_mcdi_read_response,
3643         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
3644         .irq_enable_master = efx_port_dummy_op_void,
3645         .irq_test_generate = efx_ef10_irq_test_generate,
3646         .irq_disable_non_ev = efx_port_dummy_op_void,
3647         .irq_handle_msi = efx_ef10_msi_interrupt,
3648         .irq_handle_legacy = efx_ef10_legacy_interrupt,
3649         .tx_probe = efx_ef10_tx_probe,
3650         .tx_init = efx_ef10_tx_init,
3651         .tx_remove = efx_ef10_tx_remove,
3652         .tx_write = efx_ef10_tx_write,
3653         .rx_push_rss_config = efx_ef10_rx_push_rss_config,
3654         .rx_probe = efx_ef10_rx_probe,
3655         .rx_init = efx_ef10_rx_init,
3656         .rx_remove = efx_ef10_rx_remove,
3657         .rx_write = efx_ef10_rx_write,
3658         .rx_defer_refill = efx_ef10_rx_defer_refill,
3659         .ev_probe = efx_ef10_ev_probe,
3660         .ev_init = efx_ef10_ev_init,
3661         .ev_fini = efx_ef10_ev_fini,
3662         .ev_remove = efx_ef10_ev_remove,
3663         .ev_process = efx_ef10_ev_process,
3664         .ev_read_ack = efx_ef10_ev_read_ack,
3665         .ev_test_generate = efx_ef10_ev_test_generate,
3666         .filter_table_probe = efx_ef10_filter_table_probe,
3667         .filter_table_restore = efx_ef10_filter_table_restore,
3668         .filter_table_remove = efx_ef10_filter_table_remove,
3669         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
3670         .filter_insert = efx_ef10_filter_insert,
3671         .filter_remove_safe = efx_ef10_filter_remove_safe,
3672         .filter_get_safe = efx_ef10_filter_get_safe,
3673         .filter_clear_rx = efx_ef10_filter_clear_rx,
3674         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
3675         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
3676         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
3677 #ifdef CONFIG_RFS_ACCEL
3678         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
3679         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
3680 #endif
3681 #ifdef CONFIG_SFC_MTD
3682         .mtd_probe = efx_ef10_mtd_probe,
3683         .mtd_rename = efx_mcdi_mtd_rename,
3684         .mtd_read = efx_mcdi_mtd_read,
3685         .mtd_erase = efx_mcdi_mtd_erase,
3686         .mtd_write = efx_mcdi_mtd_write,
3687         .mtd_sync = efx_mcdi_mtd_sync,
3688 #endif
3689         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
3690         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
3691         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
3692         .sriov_init = efx_ef10_sriov_init,
3693         .sriov_fini = efx_ef10_sriov_fini,
3694         .sriov_mac_address_changed = efx_ef10_sriov_mac_address_changed,
3695         .sriov_wanted = efx_ef10_sriov_wanted,
3696         .sriov_reset = efx_ef10_sriov_reset,
3697
3698         .revision = EFX_REV_HUNT_A0,
3699         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
3700         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
3701         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
3702         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
3703         .can_rx_scatter = true,
3704         .always_rx_scatter = true,
3705         .max_interrupt_mode = EFX_INT_MODE_MSIX,
3706         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
3707         .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3708                              NETIF_F_RXHASH | NETIF_F_NTUPLE),
3709         .mcdi_max_ver = 2,
3710         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
3711         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
3712                             1 << HWTSTAMP_FILTER_ALL,
3713 };