kernel/drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  49 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  50 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  51 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  52 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  53 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  54 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  55 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  56 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  57 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  58 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  59
  60 #ifdef RTL8169_DEBUG
  61 #define assert(expr) \
  62         if (!(expr)) {                                  \
  63                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  64                 #expr,__FILE__,__func__,__LINE__);              \
  65         }
  66 #define dprintk(fmt, args...) \
  67         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  68 #else
  69 #define assert(expr) do {} while (0)
  70 #define dprintk(fmt, args...)   do {} while (0)
  71 #endif /* RTL8169_DEBUG */
  72
  73 #define R8169_MSG_DEFAULT \
  74         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  75
  76 #define TX_SLOTS_AVAIL(tp) \
  77         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  78
  79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  81         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  82
  83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  84    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  85 static const int multicast_filter_limit = 32;
  86
  87 #define MAX_READ_REQUEST_SHIFT  12
  88 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  89 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  90
  91 #define R8169_REGS_SIZE         256
  92 #define R8169_NAPI_WEIGHT       64
  93 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  94 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  95 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  96 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  97
  98 #define RTL8169_TX_TIMEOUT      (6*HZ)
  99 #define RTL8169_PHY_TIMEOUT     (10*HZ)
 100
 101 /* write/read MMIO register */
 102 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 103 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 104 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 105 #define RTL_R8(reg)             readb (ioaddr + (reg))
 106 #define RTL_R16(reg)            readw (ioaddr + (reg))
 107 #define RTL_R32(reg)            readl (ioaddr + (reg))
 108
 109 enum mac_version {
 110         RTL_GIGA_MAC_VER_01 = 0,
 111         RTL_GIGA_MAC_VER_02,
 112         RTL_GIGA_MAC_VER_03,
 113         RTL_GIGA_MAC_VER_04,
 114         RTL_GIGA_MAC_VER_05,
 115         RTL_GIGA_MAC_VER_06,
 116         RTL_GIGA_MAC_VER_07,
 117         RTL_GIGA_MAC_VER_08,
 118         RTL_GIGA_MAC_VER_09,
 119         RTL_GIGA_MAC_VER_10,
 120         RTL_GIGA_MAC_VER_11,
 121         RTL_GIGA_MAC_VER_12,
 122         RTL_GIGA_MAC_VER_13,
 123         RTL_GIGA_MAC_VER_14,
 124         RTL_GIGA_MAC_VER_15,
 125         RTL_GIGA_MAC_VER_16,
 126         RTL_GIGA_MAC_VER_17,
 127         RTL_GIGA_MAC_VER_18,
 128         RTL_GIGA_MAC_VER_19,
 129         RTL_GIGA_MAC_VER_20,
 130         RTL_GIGA_MAC_VER_21,
 131         RTL_GIGA_MAC_VER_22,
 132         RTL_GIGA_MAC_VER_23,
 133         RTL_GIGA_MAC_VER_24,
 134         RTL_GIGA_MAC_VER_25,
 135         RTL_GIGA_MAC_VER_26,
 136         RTL_GIGA_MAC_VER_27,
 137         RTL_GIGA_MAC_VER_28,
 138         RTL_GIGA_MAC_VER_29,
 139         RTL_GIGA_MAC_VER_30,
 140         RTL_GIGA_MAC_VER_31,
 141         RTL_GIGA_MAC_VER_32,
 142         RTL_GIGA_MAC_VER_33,
 143         RTL_GIGA_MAC_VER_34,
 144         RTL_GIGA_MAC_VER_35,
 145         RTL_GIGA_MAC_VER_36,
 146         RTL_GIGA_MAC_VER_37,
 147         RTL_GIGA_MAC_VER_38,
 148         RTL_GIGA_MAC_VER_39,
 149         RTL_GIGA_MAC_VER_40,
 150         RTL_GIGA_MAC_VER_41,
 151         RTL_GIGA_MAC_VER_42,
 152         RTL_GIGA_MAC_VER_43,
 153         RTL_GIGA_MAC_VER_44,
 154         RTL_GIGA_MAC_VER_45,
 155         RTL_GIGA_MAC_VER_46,
 156         RTL_GIGA_MAC_VER_47,
 157         RTL_GIGA_MAC_VER_48,
 158         RTL_GIGA_MAC_VER_49,
 159         RTL_GIGA_MAC_VER_50,
 160         RTL_GIGA_MAC_VER_51,
 161         RTL_GIGA_MAC_NONE   = 0xff,
 162 };
 163
 164 enum rtl_tx_desc_version {
 165         RTL_TD_0        = 0,
 166         RTL_TD_1        = 1,
 167 };
 168
 169 #define JUMBO_1K        ETH_DATA_LEN
 170 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 171 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 172 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 173 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 174
 175 #define _R(NAME,TD,FW,SZ,B) {   \
 176         .name = NAME,           \
 177         .txd_version = TD,      \
 178         .fw_name = FW,          \
 179         .jumbo_max = SZ,        \
 180         .jumbo_tx_csum = B      \
 181 }
 182
 183 static const struct {
 184         const char *name;
 185         enum rtl_tx_desc_version txd_version;
 186         const char *fw_name;
 187         u16 jumbo_max;
 188         bool jumbo_tx_csum;
 189 } rtl_chip_infos[] = {
 190         /* PCI devices. */
 191         [RTL_GIGA_MAC_VER_01] =
 192                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 193         [RTL_GIGA_MAC_VER_02] =
 194                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 195         [RTL_GIGA_MAC_VER_03] =
 196                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 197         [RTL_GIGA_MAC_VER_04] =
 198                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 199         [RTL_GIGA_MAC_VER_05] =
 200                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 201         [RTL_GIGA_MAC_VER_06] =
 202                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 203         /* PCI-E devices. */
 204         [RTL_GIGA_MAC_VER_07] =
 205                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_08] =
 207                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 208         [RTL_GIGA_MAC_VER_09] =
 209                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 210         [RTL_GIGA_MAC_VER_10] =
 211                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 212         [RTL_GIGA_MAC_VER_11] =
 213                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 214         [RTL_GIGA_MAC_VER_12] =
 215                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 216         [RTL_GIGA_MAC_VER_13] =
 217                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 218         [RTL_GIGA_MAC_VER_14] =
 219                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 220         [RTL_GIGA_MAC_VER_15] =
 221                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 222         [RTL_GIGA_MAC_VER_16] =
 223                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 224         [RTL_GIGA_MAC_VER_17] =
 225                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 226         [RTL_GIGA_MAC_VER_18] =
 227                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 228         [RTL_GIGA_MAC_VER_19] =
 229                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 230         [RTL_GIGA_MAC_VER_20] =
 231                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 232         [RTL_GIGA_MAC_VER_21] =
 233                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 234         [RTL_GIGA_MAC_VER_22] =
 235                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 236         [RTL_GIGA_MAC_VER_23] =
 237                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 238         [RTL_GIGA_MAC_VER_24] =
 239                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 240         [RTL_GIGA_MAC_VER_25] =
 241                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_26] =
 244                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_27] =
 247                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 248         [RTL_GIGA_MAC_VER_28] =
 249                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_29] =
 251                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 252                                                         JUMBO_1K, true),
 253         [RTL_GIGA_MAC_VER_30] =
 254                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 255                                                         JUMBO_1K, true),
 256         [RTL_GIGA_MAC_VER_31] =
 257                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 258         [RTL_GIGA_MAC_VER_32] =
 259                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_33] =
 262                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 263                                                         JUMBO_9K, false),
 264         [RTL_GIGA_MAC_VER_34] =
 265                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_35] =
 268                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 269                                                         JUMBO_9K, false),
 270         [RTL_GIGA_MAC_VER_36] =
 271                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 272                                                         JUMBO_9K, false),
 273         [RTL_GIGA_MAC_VER_37] =
 274                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 275                                                         JUMBO_1K, true),
 276         [RTL_GIGA_MAC_VER_38] =
 277                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 278                                                         JUMBO_9K, false),
 279         [RTL_GIGA_MAC_VER_39] =
 280                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 281                                                         JUMBO_1K, true),
 282         [RTL_GIGA_MAC_VER_40] =
 283                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 284                                                         JUMBO_9K, false),
 285         [RTL_GIGA_MAC_VER_41] =
 286                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 287         [RTL_GIGA_MAC_VER_42] =
 288                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 289                                                         JUMBO_9K, false),
 290         [RTL_GIGA_MAC_VER_43] =
 291                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 292                                                         JUMBO_1K, true),
 293         [RTL_GIGA_MAC_VER_44] =
 294                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 295                                                         JUMBO_9K, false),
 296         [RTL_GIGA_MAC_VER_45] =
 297                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
 298                                                         JUMBO_9K, false),
 299         [RTL_GIGA_MAC_VER_46] =
 300                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
 301                                                         JUMBO_9K, false),
 302         [RTL_GIGA_MAC_VER_47] =
 303                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
 304                                                         JUMBO_1K, false),
 305         [RTL_GIGA_MAC_VER_48] =
 306                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
 307                                                         JUMBO_1K, false),
 308         [RTL_GIGA_MAC_VER_49] =
 309                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 310                                                         JUMBO_9K, false),
 311         [RTL_GIGA_MAC_VER_50] =
 312                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 313                                                         JUMBO_9K, false),
 314         [RTL_GIGA_MAC_VER_51] =
 315                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 316                                                         JUMBO_9K, false),
 317 };
 318 #undef _R
 319
 320 enum cfg_version {
 321         RTL_CFG_0 = 0x00,
 322         RTL_CFG_1,
 323         RTL_CFG_2
 324 };
 325
 326 static const struct pci_device_id rtl8169_pci_tbl[] = {
 327         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 328         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 329         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 330         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 331         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 332         { PCI_VENDOR_ID_DLINK,                  0x4300,
 333                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 334         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 335         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 336         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 337         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 338         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 339                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 340         { 0x0001,                               0x8168,
 341                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 342         {0,},
 343 };
 344
 345 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 346
 347 static int rx_buf_sz = 16383;
 348 static int use_dac;
 349 static struct {
 350         u32 msg_enable;
 351 } debug = { -1 };
 352
 353 enum rtl_registers {
 354         MAC0            = 0,    /* Ethernet hardware address. */
 355         MAC4            = 4,
 356         MAR0            = 8,    /* Multicast filter. */
 357         CounterAddrLow          = 0x10,
 358         CounterAddrHigh         = 0x14,
 359         TxDescStartAddrLow      = 0x20,
 360         TxDescStartAddrHigh     = 0x24,
 361         TxHDescStartAddrLow     = 0x28,
 362         TxHDescStartAddrHigh    = 0x2c,
 363         FLASH           = 0x30,
 364         ERSR            = 0x36,
 365         ChipCmd         = 0x37,
 366         TxPoll          = 0x38,
 367         IntrMask        = 0x3c,
 368         IntrStatus      = 0x3e,
 369
 370         TxConfig        = 0x40,
 371 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 372 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 373
 374         RxConfig        = 0x44,
 375 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 376 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 377 #define RXCFG_FIFO_SHIFT                13
 378                                         /* No threshold before first PCI xfer */
 379 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 380 #define RX_EARLY_OFF                    (1 << 11)
 381 #define RXCFG_DMA_SHIFT                 8
 382                                         /* Unlimited maximum PCI burst. */
 383 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 384
 385         RxMissed        = 0x4c,
 386         Cfg9346         = 0x50,
 387         Config0         = 0x51,
 388         Config1         = 0x52,
 389         Config2         = 0x53,
 390 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 391
 392         Config3         = 0x54,
 393         Config4         = 0x55,
 394         Config5         = 0x56,
 395         MultiIntr       = 0x5c,
 396         PHYAR           = 0x60,
 397         PHYstatus       = 0x6c,
 398         RxMaxSize       = 0xda,
 399         CPlusCmd        = 0xe0,
 400         IntrMitigate    = 0xe2,
 401         RxDescAddrLow   = 0xe4,
 402         RxDescAddrHigh  = 0xe8,
 403         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 404
 405 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 406
 407         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 408
 409 #define TxPacketMax     (8064 >> 7)
 410 #define EarlySize       0x27
 411
 412         FuncEvent       = 0xf0,
 413         FuncEventMask   = 0xf4,
 414         FuncPresetState = 0xf8,
 415         IBCR0           = 0xf8,
 416         IBCR2           = 0xf9,
 417         IBIMR0          = 0xfa,
 418         IBISR0          = 0xfb,
 419         FuncForceEvent  = 0xfc,
 420 };
 421
 422 enum rtl8110_registers {
 423         TBICSR                  = 0x64,
 424         TBI_ANAR                = 0x68,
 425         TBI_LPAR                = 0x6a,
 426 };
 427
 428 enum rtl8168_8101_registers {
 429         CSIDR                   = 0x64,
 430         CSIAR                   = 0x68,
 431 #define CSIAR_FLAG                      0x80000000
 432 #define CSIAR_WRITE_CMD                 0x80000000
 433 #define CSIAR_BYTE_ENABLE               0x0f
 434 #define CSIAR_BYTE_ENABLE_SHIFT         12
 435 #define CSIAR_ADDR_MASK                 0x0fff
 436 #define CSIAR_FUNC_CARD                 0x00000000
 437 #define CSIAR_FUNC_SDIO                 0x00010000
 438 #define CSIAR_FUNC_NIC                  0x00020000
 439 #define CSIAR_FUNC_NIC2                 0x00010000
 440         PMCH                    = 0x6f,
 441         EPHYAR                  = 0x80,
 442 #define EPHYAR_FLAG                     0x80000000
 443 #define EPHYAR_WRITE_CMD                0x80000000
 444 #define EPHYAR_REG_MASK                 0x1f
 445 #define EPHYAR_REG_SHIFT                16
 446 #define EPHYAR_DATA_MASK                0xffff
 447         DLLPR                   = 0xd0,
 448 #define PFM_EN                          (1 << 6)
 449 #define TX_10M_PS_EN                    (1 << 7)
 450         DBG_REG                 = 0xd1,
 451 #define FIX_NAK_1                       (1 << 4)
 452 #define FIX_NAK_2                       (1 << 3)
 453         TWSI                    = 0xd2,
 454         MCU                     = 0xd3,
 455 #define NOW_IS_OOB                      (1 << 7)
 456 #define TX_EMPTY                        (1 << 5)
 457 #define RX_EMPTY                        (1 << 4)
 458 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 459 #define EN_NDP                          (1 << 3)
 460 #define EN_OOB_RESET                    (1 << 2)
 461 #define LINK_LIST_RDY                   (1 << 1)
 462         EFUSEAR                 = 0xdc,
 463 #define EFUSEAR_FLAG                    0x80000000
 464 #define EFUSEAR_WRITE_CMD               0x80000000
 465 #define EFUSEAR_READ_CMD                0x00000000
 466 #define EFUSEAR_REG_MASK                0x03ff
 467 #define EFUSEAR_REG_SHIFT               8
 468 #define EFUSEAR_DATA_MASK               0xff
 469         MISC_1                  = 0xf2,
 470 #define PFM_D3COLD_EN                   (1 << 6)
 471 };
 472
 473 enum rtl8168_registers {
 474         LED_FREQ                = 0x1a,
 475         EEE_LED                 = 0x1b,
 476         ERIDR                   = 0x70,
 477         ERIAR                   = 0x74,
 478 #define ERIAR_FLAG                      0x80000000
 479 #define ERIAR_WRITE_CMD                 0x80000000
 480 #define ERIAR_READ_CMD                  0x00000000
 481 #define ERIAR_ADDR_BYTE_ALIGN           4
 482 #define ERIAR_TYPE_SHIFT                16
 483 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 484 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 485 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 486 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 487 #define ERIAR_MASK_SHIFT                12
 488 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 489 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 490 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 491 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 492 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 493         EPHY_RXER_NUM           = 0x7c,
 494         OCPDR                   = 0xb0, /* OCP GPHY access */
 495 #define OCPDR_WRITE_CMD                 0x80000000
 496 #define OCPDR_READ_CMD                  0x00000000
 497 #define OCPDR_REG_MASK                  0x7f
 498 #define OCPDR_GPHY_REG_SHIFT            16
 499 #define OCPDR_DATA_MASK                 0xffff
 500         OCPAR                   = 0xb4,
 501 #define OCPAR_FLAG                      0x80000000
 502 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 503 #define OCPAR_GPHY_READ_CMD             0x0000f060
 504         GPHY_OCP                = 0xb8,
 505         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 506         MISC                    = 0xf0, /* 8168e only. */
 507 #define TXPLA_RST                       (1 << 29)
 508 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 509 #define PWM_EN                          (1 << 22)
 510 #define RXDV_GATED_EN                   (1 << 19)
 511 #define EARLY_TALLY_EN                  (1 << 16)
 512 };
 513
 514 enum rtl_register_content {
 515         /* InterruptStatusBits */
 516         SYSErr          = 0x8000,
 517         PCSTimeout      = 0x4000,
 518         SWInt           = 0x0100,
 519         TxDescUnavail   = 0x0080,
 520         RxFIFOOver      = 0x0040,
 521         LinkChg         = 0x0020,
 522         RxOverflow      = 0x0010,
 523         TxErr           = 0x0008,
 524         TxOK            = 0x0004,
 525         RxErr           = 0x0002,
 526         RxOK            = 0x0001,
 527
 528         /* RxStatusDesc */
 529         RxBOVF  = (1 << 24),
 530         RxFOVF  = (1 << 23),
 531         RxRWT   = (1 << 22),
 532         RxRES   = (1 << 21),
 533         RxRUNT  = (1 << 20),
 534         RxCRC   = (1 << 19),
 535
 536         /* ChipCmdBits */
 537         StopReq         = 0x80,
 538         CmdReset        = 0x10,
 539         CmdRxEnb        = 0x08,
 540         CmdTxEnb        = 0x04,
 541         RxBufEmpty      = 0x01,
 542
 543         /* TXPoll register p.5 */
 544         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 545         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 546         FSWInt          = 0x01,         /* Forced software interrupt */
 547
 548         /* Cfg9346Bits */
 549         Cfg9346_Lock    = 0x00,
 550         Cfg9346_Unlock  = 0xc0,
 551
 552         /* rx_mode_bits */
 553         AcceptErr       = 0x20,
 554         AcceptRunt      = 0x10,
 555         AcceptBroadcast = 0x08,
 556         AcceptMulticast = 0x04,
 557         AcceptMyPhys    = 0x02,
 558         AcceptAllPhys   = 0x01,
 559 #define RX_CONFIG_ACCEPT_MASK           0x3f
 560
 561         /* TxConfigBits */
 562         TxInterFrameGapShift = 24,
 563         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 564
 565         /* Config1 register p.24 */
 566         LEDS1           = (1 << 7),
 567         LEDS0           = (1 << 6),
 568         Speed_down      = (1 << 4),
 569         MEMMAP          = (1 << 3),
 570         IOMAP           = (1 << 2),
 571         VPD             = (1 << 1),
 572         PMEnable        = (1 << 0),     /* Power Management Enable */
 573
 574         /* Config2 register p. 25 */
 575         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 576         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 577         PCI_Clock_66MHz = 0x01,
 578         PCI_Clock_33MHz = 0x00,
 579
 580         /* Config3 register p.25 */
 581         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 582         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 583         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 584         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 585         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 586
 587         /* Config4 register */
 588         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 589
 590         /* Config5 register p.27 */
 591         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 592         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 593         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 594         Spi_en          = (1 << 3),
 595         LanWake         = (1 << 1),     /* LanWake enable/disable */
 596         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 597         ASPM_en         = (1 << 0),     /* ASPM enable */
 598
 599         /* TBICSR p.28 */
 600         TBIReset        = 0x80000000,
 601         TBILoopback     = 0x40000000,
 602         TBINwEnable     = 0x20000000,
 603         TBINwRestart    = 0x10000000,
 604         TBILinkOk       = 0x02000000,
 605         TBINwComplete   = 0x01000000,
 606
 607         /* CPlusCmd p.31 */
 608         EnableBist      = (1 << 15),    // 8168 8101
 609         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 610         Normal_mode     = (1 << 13),    // unused
 611         Force_half_dup  = (1 << 12),    // 8168 8101
 612         Force_rxflow_en = (1 << 11),    // 8168 8101
 613         Force_txflow_en = (1 << 10),    // 8168 8101
 614         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 615         ASF             = (1 << 8),     // 8168 8101
 616         PktCntrDisable  = (1 << 7),     // 8168 8101
 617         Mac_dbgo_sel    = 0x001c,       // 8168
 618         RxVlan          = (1 << 6),
 619         RxChkSum        = (1 << 5),
 620         PCIDAC          = (1 << 4),
 621         PCIMulRW        = (1 << 3),
 622         INTT_0          = 0x0000,       // 8168
 623         INTT_1          = 0x0001,       // 8168
 624         INTT_2          = 0x0002,       // 8168
 625         INTT_3          = 0x0003,       // 8168
 626
 627         /* rtl8169_PHYstatus */
 628         TBI_Enable      = 0x80,
 629         TxFlowCtrl      = 0x40,
 630         RxFlowCtrl      = 0x20,
 631         _1000bpsF       = 0x10,
 632         _100bps         = 0x08,
 633         _10bps          = 0x04,
 634         LinkStatus      = 0x02,
 635         FullDup         = 0x01,
 636
 637         /* _TBICSRBit */
 638         TBILinkOK       = 0x02000000,
 639
 640         /* DumpCounterCommand */
 641         CounterDump     = 0x8,
 642
 643         /* magic enable v2 */
 644         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 645 };
 646
 647 enum rtl_desc_bit {
 648         /* First doubleword. */
 649         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 650         RingEnd         = (1 << 30), /* End of descriptor ring */
 651         FirstFrag       = (1 << 29), /* First segment of a packet */
 652         LastFrag        = (1 << 28), /* Final segment of a packet */
 653 };
 654
 655 /* Generic case. */
 656 enum rtl_tx_desc_bit {
 657         /* First doubleword. */
 658         TD_LSO          = (1 << 27),            /* Large Send Offload */
 659 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 660
 661         /* Second doubleword. */
 662         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 663 };
 664
 665 /* 8169, 8168b and 810x except 8102e. */
 666 enum rtl_tx_desc_bit_0 {
 667         /* First doubleword. */
 668 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 669         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 670         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 671         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 672 };
 673
 674 /* 8102e, 8168c and beyond. */
 675 enum rtl_tx_desc_bit_1 {
 676         /* First doubleword. */
 677         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 678         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 679 #define GTTCPHO_SHIFT                   18
 680 #define GTTCPHO_MAX                     0x7fU
 681
 682         /* Second doubleword. */
 683 #define TCPHO_SHIFT                     18
 684 #define TCPHO_MAX                       0x3ffU
 685 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 686         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 687         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 688         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 689         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 690 };
 691
 692 enum rtl_rx_desc_bit {
 693         /* Rx private */
 694         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 695         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 696
 697 #define RxProtoUDP      (PID1)
 698 #define RxProtoTCP      (PID0)
 699 #define RxProtoIP       (PID1 | PID0)
 700 #define RxProtoMask     RxProtoIP
 701
 702         IPFail          = (1 << 16), /* IP checksum failed */
 703         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 704         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 705         RxVlanTag       = (1 << 16), /* VLAN tag available */
 706 };
 707
 708 #define RsvdMask        0x3fffc000
 709
 710 struct TxDesc {
 711         __le32 opts1;
 712         __le32 opts2;
 713         __le64 addr;
 714 };
 715
 716 struct RxDesc {
 717         __le32 opts1;
 718         __le32 opts2;
 719         __le64 addr;
 720 };
 721
 722 struct ring_info {
 723         struct sk_buff  *skb;
 724         u32             len;
 725         u8              __pad[sizeof(void *) - sizeof(u32)];
 726 };
 727
 728 enum features {
 729         RTL_FEATURE_WOL         = (1 << 0),
 730         RTL_FEATURE_MSI         = (1 << 1),
 731         RTL_FEATURE_GMII        = (1 << 2),
 732 };
 733
 734 struct rtl8169_counters {
 735         __le64  tx_packets;
 736         __le64  rx_packets;
 737         __le64  tx_errors;
 738         __le32  rx_errors;
 739         __le16  rx_missed;
 740         __le16  align_errors;
 741         __le32  tx_one_collision;
 742         __le32  tx_multi_collision;
 743         __le64  rx_unicast;
 744         __le64  rx_broadcast;
 745         __le32  rx_multicast;
 746         __le16  tx_aborted;
 747         __le16  tx_underun;
 748 };
 749
 750 enum rtl_flag {
 751         RTL_FLAG_TASK_ENABLED,
 752         RTL_FLAG_TASK_SLOW_PENDING,
 753         RTL_FLAG_TASK_RESET_PENDING,
 754         RTL_FLAG_TASK_PHY_PENDING,
 755         RTL_FLAG_MAX
 756 };
 757
 758 struct rtl8169_stats {
 759         u64                     packets;
 760         u64                     bytes;
 761         struct u64_stats_sync   syncp;
 762 };
 763
 764 struct rtl8169_private {
 765         void __iomem *mmio_addr;        /* memory map physical address */
 766         struct pci_dev *pci_dev;
 767         struct net_device *dev;
 768         struct napi_struct napi;
 769         u32 msg_enable;
 770         u16 txd_version;
 771         u16 mac_version;
 772         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 773         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 774         u32 dirty_tx;
 775         struct rtl8169_stats rx_stats;
 776         struct rtl8169_stats tx_stats;
 777         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 778         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 779         dma_addr_t TxPhyAddr;
 780         dma_addr_t RxPhyAddr;
 781         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 782         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 783         struct timer_list timer;
 784         u16 cp_cmd;
 785
 786         u16 event_slow;
 787
 788         struct mdio_ops {
 789                 void (*write)(struct rtl8169_private *, int, int);
 790                 int (*read)(struct rtl8169_private *, int);
 791         } mdio_ops;
 792
 793         struct pll_power_ops {
 794                 void (*down)(struct rtl8169_private *);
 795                 void (*up)(struct rtl8169_private *);
 796         } pll_power_ops;
 797
 798         struct jumbo_ops {
 799                 void (*enable)(struct rtl8169_private *);
 800                 void (*disable)(struct rtl8169_private *);
 801         } jumbo_ops;
 802
 803         struct csi_ops {
 804                 void (*write)(struct rtl8169_private *, int, int);
 805                 u32 (*read)(struct rtl8169_private *, int);
 806         } csi_ops;
 807
 808         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 809         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 810         void (*phy_reset_enable)(struct rtl8169_private *tp);
 811         void (*hw_start)(struct net_device *);
 812         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 813         unsigned int (*link_ok)(void __iomem *);
 814         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 815         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 816
 817         struct {
 818                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 819                 struct mutex mutex;
 820                 struct work_struct work;
 821         } wk;
 822
 823         unsigned features;
 824
 825         struct mii_if_info mii;
 826         struct rtl8169_counters counters;
 827         u32 saved_wolopts;
 828         u32 opts1_mask;
 829
 830         struct rtl_fw {
 831                 const struct firmware *fw;
 832
 833 #define RTL_VER_SIZE            32
 834
 835                 char version[RTL_VER_SIZE];
 836
 837                 struct rtl_fw_phy_action {
 838                         __le32 *code;
 839                         size_t size;
 840                 } phy_action;
 841         } *rtl_fw;
 842 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 843
 844         u32 ocp_base;
 845 };
 846
 847 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 848 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 849 module_param(use_dac, int, 0);
 850 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 851 module_param_named(debug, debug.msg_enable, int, 0);
 852 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 853 MODULE_LICENSE("GPL");
 854 MODULE_VERSION(RTL8169_VERSION);
 855 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 856 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 857 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 858 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 859 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 860 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 861 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 862 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 863 MODULE_FIRMWARE(FIRMWARE_8402_1);
 864 MODULE_FIRMWARE(FIRMWARE_8411_1);
 865 MODULE_FIRMWARE(FIRMWARE_8411_2);
 866 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 867 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 868 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 869 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 870 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 871 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 872 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 873 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 874
 875 static void rtl_lock_work(struct rtl8169_private *tp)
 876 {
 877         mutex_lock(&tp->wk.mutex);
 878 }
 879
 880 static void rtl_unlock_work(struct rtl8169_private *tp)
 881 {
 882         mutex_unlock(&tp->wk.mutex);
 883 }
 884
 885 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 886 {
 887         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 888                                            PCI_EXP_DEVCTL_READRQ, force);
 889 }
 890
 891 struct rtl_cond {
 892         bool (*check)(struct rtl8169_private *);
 893         const char *msg;
 894 };
 895
 896 static void rtl_udelay(unsigned int d)
 897 {
 898         udelay(d);
 899 }
 900
 901 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 902                           void (*delay)(unsigned int), unsigned int d, int n,
 903                           bool high)
 904 {
 905         int i;
 906
 907         for (i = 0; i < n; i++) {
 908                 delay(d);
 909                 if (c->check(tp) == high)
 910                         return true;
 911         }
 912         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 913                   c->msg, !high, n, d);
 914         return false;
 915 }
 916
 917 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 918                                       const struct rtl_cond *c,
 919                                       unsigned int d, int n)
 920 {
 921         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 922 }
 923
 924 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 925                                      const struct rtl_cond *c,
 926                                      unsigned int d, int n)
 927 {
 928         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 929 }
 930
 931 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 932                                       const struct rtl_cond *c,
 933                                       unsigned int d, int n)
 934 {
 935         return rtl_loop_wait(tp, c, msleep, d, n, true);
 936 }
 937
 938 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 939                                      const struct rtl_cond *c,
 940                                      unsigned int d, int n)
 941 {
 942         return rtl_loop_wait(tp, c, msleep, d, n, false);
 943 }
 944
 945 #define DECLARE_RTL_COND(name)                          \
 946 static bool name ## _check(struct rtl8169_private *);   \
 947                                                         \
 948 static const struct rtl_cond name = {                   \
 949         .check  = name ## _check,                       \
 950         .msg    = #name                                 \
 951 };                                                      \
 952                                                         \
 953 static bool name ## _check(struct rtl8169_private *tp)
 954
 955 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 956 {
 957         if (reg & 0xffff0001) {
 958                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 959                 return true;
 960         }
 961         return false;
 962 }
 963
 964 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 965 {
 966         void __iomem *ioaddr = tp->mmio_addr;
 967
 968         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
 969 }
 970
 971 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 972 {
 973         void __iomem *ioaddr = tp->mmio_addr;
 974
 975         if (rtl_ocp_reg_failure(tp, reg))
 976                 return;
 977
 978         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 979
 980         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 981 }
 982
 983 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 984 {
 985         void __iomem *ioaddr = tp->mmio_addr;
 986
 987         if (rtl_ocp_reg_failure(tp, reg))
 988                 return 0;
 989
 990         RTL_W32(GPHY_OCP, reg << 15);
 991
 992         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 993                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
 994 }
 995
 996 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 997 {
 998         void __iomem *ioaddr = tp->mmio_addr;
 999
1000         if (rtl_ocp_reg_failure(tp, reg))
1001                 return;
1002
1003         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1004 }
1005
1006 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1007 {
1008         void __iomem *ioaddr = tp->mmio_addr;
1009
1010         if (rtl_ocp_reg_failure(tp, reg))
1011                 return 0;
1012
1013         RTL_W32(OCPDR, reg << 15);
1014
1015         return RTL_R32(OCPDR);
1016 }
1017
1018 #define OCP_STD_PHY_BASE        0xa400
1019
1020 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1021 {
1022         if (reg == 0x1f) {
1023                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1024                 return;
1025         }
1026
1027         if (tp->ocp_base != OCP_STD_PHY_BASE)
1028                 reg -= 0x10;
1029
1030         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1031 }
1032
1033 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1034 {
1035         if (tp->ocp_base != OCP_STD_PHY_BASE)
1036                 reg -= 0x10;
1037
1038         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1039 }
1040
1041 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1042 {
1043         if (reg == 0x1f) {
1044                 tp->ocp_base = value << 4;
1045                 return;
1046         }
1047
1048         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1049 }
1050
1051 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1052 {
1053         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1054 }
1055
1056 DECLARE_RTL_COND(rtl_phyar_cond)
1057 {
1058         void __iomem *ioaddr = tp->mmio_addr;
1059
1060         return RTL_R32(PHYAR) & 0x80000000;
1061 }
1062
1063 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1064 {
1065         void __iomem *ioaddr = tp->mmio_addr;
1066
1067         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1068
1069         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1070         /*
1071          * According to hardware specs a 20us delay is required after write
1072          * complete indication, but before sending next command.
1073          */
1074         udelay(20);
1075 }
1076
1077 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1078 {
1079         void __iomem *ioaddr = tp->mmio_addr;
1080         int value;
1081
1082         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1083
1084         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1085                 RTL_R32(PHYAR) & 0xffff : ~0;
1086
1087         /*
1088          * According to hardware specs a 20us delay is required after read
1089          * complete indication, but before sending next command.
1090          */
1091         udelay(20);
1092
1093         return value;
1094 }
1095
1096 DECLARE_RTL_COND(rtl_ocpar_cond)
1097 {
1098         void __iomem *ioaddr = tp->mmio_addr;
1099
1100         return RTL_R32(OCPAR) & OCPAR_FLAG;
1101 }
1102
1103 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1104 {
1105         void __iomem *ioaddr = tp->mmio_addr;
1106
1107         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1108         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1109         RTL_W32(EPHY_RXER_NUM, 0);
1110
1111         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1112 }
1113
1114 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1115 {
1116         r8168dp_1_mdio_access(tp, reg,
1117                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1118 }
1119
1120 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1121 {
1122         void __iomem *ioaddr = tp->mmio_addr;
1123
1124         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1125
1126         mdelay(1);
1127         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1128         RTL_W32(EPHY_RXER_NUM, 0);
1129
1130         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1131                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1132 }
1133
1134 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1135
1136 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1137 {
1138         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1139 }
1140
1141 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1142 {
1143         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1144 }
1145
1146 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1147 {
1148         void __iomem *ioaddr = tp->mmio_addr;
1149
1150         r8168dp_2_mdio_start(ioaddr);
1151
1152         r8169_mdio_write(tp, reg, value);
1153
1154         r8168dp_2_mdio_stop(ioaddr);
1155 }
1156
1157 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1158 {
1159         void __iomem *ioaddr = tp->mmio_addr;
1160         int value;
1161
1162         r8168dp_2_mdio_start(ioaddr);
1163
1164         value = r8169_mdio_read(tp, reg);
1165
1166         r8168dp_2_mdio_stop(ioaddr);
1167
1168         return value;
1169 }
1170
1171 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1172 {
1173         tp->mdio_ops.write(tp, location, val);
1174 }
1175
1176 static int rtl_readphy(struct rtl8169_private *tp, int location)
1177 {
1178         return tp->mdio_ops.read(tp, location);
1179 }
1180
1181 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1182 {
1183         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1184 }
1185
1186 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1187 {
1188         int val;
1189
1190         val = rtl_readphy(tp, reg_addr);
1191         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1192 }
1193
1194 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1195                            int val)
1196 {
1197         struct rtl8169_private *tp = netdev_priv(dev);
1198
1199         rtl_writephy(tp, location, val);
1200 }
1201
1202 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1203 {
1204         struct rtl8169_private *tp = netdev_priv(dev);
1205
1206         return rtl_readphy(tp, location);
1207 }
1208
1209 DECLARE_RTL_COND(rtl_ephyar_cond)
1210 {
1211         void __iomem *ioaddr = tp->mmio_addr;
1212
1213         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1214 }
1215
1216 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1217 {
1218         void __iomem *ioaddr = tp->mmio_addr;
1219
1220         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1221                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1222
1223         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1224
1225         udelay(10);
1226 }
1227
1228 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1229 {
1230         void __iomem *ioaddr = tp->mmio_addr;
1231
1232         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1233
1234         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1235                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1236 }
1237
1238 DECLARE_RTL_COND(rtl_eriar_cond)
1239 {
1240         void __iomem *ioaddr = tp->mmio_addr;
1241
1242         return RTL_R32(ERIAR) & ERIAR_FLAG;
1243 }
1244
1245 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1246                           u32 val, int type)
1247 {
1248         void __iomem *ioaddr = tp->mmio_addr;
1249
1250         BUG_ON((addr & 3) || (mask == 0));
1251         RTL_W32(ERIDR, val);
1252         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1253
1254         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1255 }
1256
1257 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1258 {
1259         void __iomem *ioaddr = tp->mmio_addr;
1260
1261         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1262
1263         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1264                 RTL_R32(ERIDR) : ~0;
1265 }
1266
1267 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1268                          u32 m, int type)
1269 {
1270         u32 val;
1271
1272         val = rtl_eri_read(tp, addr, type);
1273         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1274 }
1275
1276 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1277 {
1278         void __iomem *ioaddr = tp->mmio_addr;
1279
1280         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1281         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1282                 RTL_R32(OCPDR) : ~0;
1283 }
1284
1285 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1286 {
1287         return rtl_eri_read(tp, reg, ERIAR_OOB);
1288 }
1289
1290 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1291 {
1292         switch (tp->mac_version) {
1293         case RTL_GIGA_MAC_VER_27:
1294         case RTL_GIGA_MAC_VER_28:
1295         case RTL_GIGA_MAC_VER_31:
1296                 return r8168dp_ocp_read(tp, mask, reg);
1297         case RTL_GIGA_MAC_VER_49:
1298         case RTL_GIGA_MAC_VER_50:
1299         case RTL_GIGA_MAC_VER_51:
1300                 return r8168ep_ocp_read(tp, mask, reg);
1301         default:
1302                 BUG();
1303                 return ~0;
1304         }
1305 }
1306
1307 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1308                               u32 data)
1309 {
1310         void __iomem *ioaddr = tp->mmio_addr;
1311
1312         RTL_W32(OCPDR, data);
1313         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1314         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1315 }
1316
1317 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1318                               u32 data)
1319 {
1320         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1321                       data, ERIAR_OOB);
1322 }
1323
1324 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1325 {
1326         switch (tp->mac_version) {
1327         case RTL_GIGA_MAC_VER_27:
1328         case RTL_GIGA_MAC_VER_28:
1329         case RTL_GIGA_MAC_VER_31:
1330                 r8168dp_ocp_write(tp, mask, reg, data);
1331                 break;
1332         case RTL_GIGA_MAC_VER_49:
1333         case RTL_GIGA_MAC_VER_50:
1334         case RTL_GIGA_MAC_VER_51:
1335                 r8168ep_ocp_write(tp, mask, reg, data);
1336                 break;
1337         default:
1338                 BUG();
1339                 break;
1340         }
1341 }
1342
1343 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1344 {
1345         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1346
1347         ocp_write(tp, 0x1, 0x30, 0x00000001);
1348 }
1349
1350 #define OOB_CMD_RESET           0x00
1351 #define OOB_CMD_DRIVER_START    0x05
1352 #define OOB_CMD_DRIVER_STOP     0x06
1353
1354 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1355 {
1356         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1357 }
1358
1359 DECLARE_RTL_COND(rtl_ocp_read_cond)
1360 {
1361         u16 reg;
1362
1363         reg = rtl8168_get_ocp_reg(tp);
1364
1365         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1366 }
1367
1368 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1369 {
1370         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1371 }
1372
1373 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1374 {
1375         void __iomem *ioaddr = tp->mmio_addr;
1376
1377         return RTL_R8(IBISR0) & 0x02;
1378 }
1379
1380 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1381 {
1382         void __iomem *ioaddr = tp->mmio_addr;
1383
1384         RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1385         rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1386         RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1387         RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1388 }
1389
1390 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1391 {
1392         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1393         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1394 }
1395
1396 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1397 {
1398         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1399         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1400         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1401 }
1402
1403 static void rtl8168_driver_start(struct rtl8169_private *tp)
1404 {
1405         switch (tp->mac_version) {
1406         case RTL_GIGA_MAC_VER_27:
1407         case RTL_GIGA_MAC_VER_28:
1408         case RTL_GIGA_MAC_VER_31:
1409                 rtl8168dp_driver_start(tp);
1410                 break;
1411         case RTL_GIGA_MAC_VER_49:
1412         case RTL_GIGA_MAC_VER_50:
1413         case RTL_GIGA_MAC_VER_51:
1414                 rtl8168ep_driver_start(tp);
1415                 break;
1416         default:
1417                 BUG();
1418                 break;
1419         }
1420 }
1421
1422 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1423 {
1424         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1425         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1426 }
1427
1428 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1429 {
1430         rtl8168ep_stop_cmac(tp);
1431         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1432         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1433         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1434 }
1435
1436 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1437 {
1438         switch (tp->mac_version) {
1439         case RTL_GIGA_MAC_VER_27:
1440         case RTL_GIGA_MAC_VER_28:
1441         case RTL_GIGA_MAC_VER_31:
1442                 rtl8168dp_driver_stop(tp);
1443                 break;
1444         case RTL_GIGA_MAC_VER_49:
1445         case RTL_GIGA_MAC_VER_50:
1446         case RTL_GIGA_MAC_VER_51:
1447                 rtl8168ep_driver_stop(tp);
1448                 break;
1449         default:
1450                 BUG();
1451                 break;
1452         }
1453 }
1454
1455 static int r8168dp_check_dash(struct rtl8169_private *tp)
1456 {
1457         u16 reg = rtl8168_get_ocp_reg(tp);
1458
1459         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1460 }
1461
1462 static int r8168ep_check_dash(struct rtl8169_private *tp)
1463 {
1464         return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1465 }
1466
1467 static int r8168_check_dash(struct rtl8169_private *tp)
1468 {
1469         switch (tp->mac_version) {
1470         case RTL_GIGA_MAC_VER_27:
1471         case RTL_GIGA_MAC_VER_28:
1472         case RTL_GIGA_MAC_VER_31:
1473                 return r8168dp_check_dash(tp);
1474         case RTL_GIGA_MAC_VER_49:
1475         case RTL_GIGA_MAC_VER_50:
1476         case RTL_GIGA_MAC_VER_51:
1477                 return r8168ep_check_dash(tp);
1478         default:
1479                 return 0;
1480         }
1481 }
1482
1483 struct exgmac_reg {
1484         u16 addr;
1485         u16 mask;
1486         u32 val;
1487 };
1488
1489 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1490                                    const struct exgmac_reg *r, int len)
1491 {
1492         while (len-- > 0) {
1493                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1494                 r++;
1495         }
1496 }
1497
1498 DECLARE_RTL_COND(rtl_efusear_cond)
1499 {
1500         void __iomem *ioaddr = tp->mmio_addr;
1501
1502         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1503 }
1504
1505 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1506 {
1507         void __iomem *ioaddr = tp->mmio_addr;
1508
1509         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1510
1511         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1512                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1513 }
1514
1515 static u16 rtl_get_events(struct rtl8169_private *tp)
1516 {
1517         void __iomem *ioaddr = tp->mmio_addr;
1518
1519         return RTL_R16(IntrStatus);
1520 }
1521
1522 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1523 {
1524         void __iomem *ioaddr = tp->mmio_addr;
1525
1526         RTL_W16(IntrStatus, bits);
1527         mmiowb();
1528 }
1529
1530 static void rtl_irq_disable(struct rtl8169_private *tp)
1531 {
1532         void __iomem *ioaddr = tp->mmio_addr;
1533
1534         RTL_W16(IntrMask, 0);
1535         mmiowb();
1536 }
1537
1538 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1539 {
1540         void __iomem *ioaddr = tp->mmio_addr;
1541
1542         RTL_W16(IntrMask, bits);
1543 }
1544
1545 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1546 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1547 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1548
1549 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1550 {
1551         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1552 }
1553
1554 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1555 {
1556         void __iomem *ioaddr = tp->mmio_addr;
1557
1558         rtl_irq_disable(tp);
1559         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1560         RTL_R8(ChipCmd);
1561 }
1562
1563 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1564 {
1565         void __iomem *ioaddr = tp->mmio_addr;
1566
1567         return RTL_R32(TBICSR) & TBIReset;
1568 }
1569
1570 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1571 {
1572         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1573 }
1574
1575 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1576 {
1577         return RTL_R32(TBICSR) & TBILinkOk;
1578 }
1579
1580 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1581 {
1582         return RTL_R8(PHYstatus) & LinkStatus;
1583 }
1584
1585 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1586 {
1587         void __iomem *ioaddr = tp->mmio_addr;
1588
1589         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1590 }
1591
1592 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1593 {
1594         unsigned int val;
1595
1596         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1597         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1598 }
1599
1600 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1601 {
1602         void __iomem *ioaddr = tp->mmio_addr;
1603         struct net_device *dev = tp->dev;
1604
1605         if (!netif_running(dev))
1606                 return;
1607
1608         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1609             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1610                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1611                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1612                                       ERIAR_EXGMAC);
1613                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1614                                       ERIAR_EXGMAC);
1615                 } else if (RTL_R8(PHYstatus) & _100bps) {
1616                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1617                                       ERIAR_EXGMAC);
1618                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1619                                       ERIAR_EXGMAC);
1620                 } else {
1621                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1622                                       ERIAR_EXGMAC);
1623                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1624                                       ERIAR_EXGMAC);
1625                 }
1626                 /* Reset packet filter */
1627                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1628                              ERIAR_EXGMAC);
1629                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1630                              ERIAR_EXGMAC);
1631         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1632                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1633                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1634                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1635                                       ERIAR_EXGMAC);
1636                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1637                                       ERIAR_EXGMAC);
1638                 } else {
1639                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1640                                       ERIAR_EXGMAC);
1641                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1642                                       ERIAR_EXGMAC);
1643                 }
1644         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1645                 if (RTL_R8(PHYstatus) & _10bps) {
1646                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1647                                       ERIAR_EXGMAC);
1648                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1649                                       ERIAR_EXGMAC);
1650                 } else {
1651                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1652                                       ERIAR_EXGMAC);
1653                 }
1654         }
1655 }
1656
1657 static void __rtl8169_check_link_status(struct net_device *dev,
1658                                         struct rtl8169_private *tp,
1659                                         void __iomem *ioaddr, bool pm)
1660 {
1661         if (tp->link_ok(ioaddr)) {
1662                 rtl_link_chg_patch(tp);
1663                 /* This is to cancel a scheduled suspend if there's one. */
1664                 if (pm)
1665                         pm_request_resume(&tp->pci_dev->dev);
1666                 netif_carrier_on(dev);
1667                 if (net_ratelimit())
1668                         netif_info(tp, ifup, dev, "link up\n");
1669         } else {
1670                 netif_carrier_off(dev);
1671                 netif_info(tp, ifdown, dev, "link down\n");
1672                 if (pm)
1673                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1674         }
1675 }
1676
1677 static void rtl8169_check_link_status(struct net_device *dev,
1678                                       struct rtl8169_private *tp,
1679                                       void __iomem *ioaddr)
1680 {
1681         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1682 }
1683
1684 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1685
1686 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1687 {
1688         void __iomem *ioaddr = tp->mmio_addr;
1689         u8 options;
1690         u32 wolopts = 0;
1691
1692         options = RTL_R8(Config1);
1693         if (!(options & PMEnable))
1694                 return 0;
1695
1696         options = RTL_R8(Config3);
1697         if (options & LinkUp)
1698                 wolopts |= WAKE_PHY;
1699         switch (tp->mac_version) {
1700         case RTL_GIGA_MAC_VER_34:
1701         case RTL_GIGA_MAC_VER_35:
1702         case RTL_GIGA_MAC_VER_36:
1703         case RTL_GIGA_MAC_VER_37:
1704         case RTL_GIGA_MAC_VER_38:
1705         case RTL_GIGA_MAC_VER_40:
1706         case RTL_GIGA_MAC_VER_41:
1707         case RTL_GIGA_MAC_VER_42:
1708         case RTL_GIGA_MAC_VER_43:
1709         case RTL_GIGA_MAC_VER_44:
1710         case RTL_GIGA_MAC_VER_45:
1711         case RTL_GIGA_MAC_VER_46:
1712         case RTL_GIGA_MAC_VER_47:
1713         case RTL_GIGA_MAC_VER_48:
1714         case RTL_GIGA_MAC_VER_49:
1715         case RTL_GIGA_MAC_VER_50:
1716         case RTL_GIGA_MAC_VER_51:
1717                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1718                         wolopts |= WAKE_MAGIC;
1719                 break;
1720         default:
1721                 if (options & MagicPacket)
1722                         wolopts |= WAKE_MAGIC;
1723                 break;
1724         }
1725
1726         options = RTL_R8(Config5);
1727         if (options & UWF)
1728                 wolopts |= WAKE_UCAST;
1729         if (options & BWF)
1730                 wolopts |= WAKE_BCAST;
1731         if (options & MWF)
1732                 wolopts |= WAKE_MCAST;
1733
1734         return wolopts;
1735 }
1736
1737 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1738 {
1739         struct rtl8169_private *tp = netdev_priv(dev);
1740
1741         rtl_lock_work(tp);
1742
1743         wol->supported = WAKE_ANY;
1744         wol->wolopts = __rtl8169_get_wol(tp);
1745
1746         rtl_unlock_work(tp);
1747 }
1748
1749 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1750 {
1751         void __iomem *ioaddr = tp->mmio_addr;
1752         unsigned int i, tmp;
1753         static const struct {
1754                 u32 opt;
1755                 u16 reg;
1756                 u8  mask;
1757         } cfg[] = {
1758                 { WAKE_PHY,   Config3, LinkUp },
1759                 { WAKE_UCAST, Config5, UWF },
1760                 { WAKE_BCAST, Config5, BWF },
1761                 { WAKE_MCAST, Config5, MWF },
1762                 { WAKE_ANY,   Config5, LanWake },
1763                 { WAKE_MAGIC, Config3, MagicPacket }
1764         };
1765         u8 options;
1766
1767         RTL_W8(Cfg9346, Cfg9346_Unlock);
1768
1769         switch (tp->mac_version) {
1770         case RTL_GIGA_MAC_VER_34:
1771         case RTL_GIGA_MAC_VER_35:
1772         case RTL_GIGA_MAC_VER_36:
1773         case RTL_GIGA_MAC_VER_37:
1774         case RTL_GIGA_MAC_VER_38:
1775         case RTL_GIGA_MAC_VER_40:
1776         case RTL_GIGA_MAC_VER_41:
1777         case RTL_GIGA_MAC_VER_42:
1778         case RTL_GIGA_MAC_VER_43:
1779         case RTL_GIGA_MAC_VER_44:
1780         case RTL_GIGA_MAC_VER_45:
1781         case RTL_GIGA_MAC_VER_46:
1782         case RTL_GIGA_MAC_VER_47:
1783         case RTL_GIGA_MAC_VER_48:
1784         case RTL_GIGA_MAC_VER_49:
1785         case RTL_GIGA_MAC_VER_50:
1786         case RTL_GIGA_MAC_VER_51:
1787                 tmp = ARRAY_SIZE(cfg) - 1;
1788                 if (wolopts & WAKE_MAGIC)
1789                         rtl_w0w1_eri(tp,
1790                                      0x0dc,
1791                                      ERIAR_MASK_0100,
1792                                      MagicPacket_v2,
1793                                      0x0000,
1794                                      ERIAR_EXGMAC);
1795                 else
1796                         rtl_w0w1_eri(tp,
1797                                      0x0dc,
1798                                      ERIAR_MASK_0100,
1799                                      0x0000,
1800                                      MagicPacket_v2,
1801                                      ERIAR_EXGMAC);
1802                 break;
1803         default:
1804                 tmp = ARRAY_SIZE(cfg);
1805                 break;
1806         }
1807
1808         for (i = 0; i < tmp; i++) {
1809                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1810                 if (wolopts & cfg[i].opt)
1811                         options |= cfg[i].mask;
1812                 RTL_W8(cfg[i].reg, options);
1813         }
1814
1815         switch (tp->mac_version) {
1816         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1817                 options = RTL_R8(Config1) & ~PMEnable;
1818                 if (wolopts)
1819                         options |= PMEnable;
1820                 RTL_W8(Config1, options);
1821                 break;
1822         default:
1823                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1824                 if (wolopts)
1825                         options |= PME_SIGNAL;
1826                 RTL_W8(Config2, options);
1827                 break;
1828         }
1829
1830         RTL_W8(Cfg9346, Cfg9346_Lock);
1831 }
1832
1833 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1834 {
1835         struct rtl8169_private *tp = netdev_priv(dev);
1836
1837         rtl_lock_work(tp);
1838
1839         if (wol->wolopts)
1840                 tp->features |= RTL_FEATURE_WOL;
1841         else
1842                 tp->features &= ~RTL_FEATURE_WOL;
1843         __rtl8169_set_wol(tp, wol->wolopts);
1844
1845         rtl_unlock_work(tp);
1846
1847         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1848
1849         return 0;
1850 }
1851
1852 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1853 {
1854         return rtl_chip_infos[tp->mac_version].fw_name;
1855 }
1856
1857 static void rtl8169_get_drvinfo(struct net_device *dev,
1858                                 struct ethtool_drvinfo *info)
1859 {
1860         struct rtl8169_private *tp = netdev_priv(dev);
1861         struct rtl_fw *rtl_fw = tp->rtl_fw;
1862
1863         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1864         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1865         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1866         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1867         if (!IS_ERR_OR_NULL(rtl_fw))
1868                 strlcpy(info->fw_version, rtl_fw->version,
1869                         sizeof(info->fw_version));
1870 }
1871
1872 static int rtl8169_get_regs_len(struct net_device *dev)
1873 {
1874         return R8169_REGS_SIZE;
1875 }
1876
1877 static int rtl8169_set_speed_tbi(struct net_device *dev,
1878                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1879 {
1880         struct rtl8169_private *tp = netdev_priv(dev);
1881         void __iomem *ioaddr = tp->mmio_addr;
1882         int ret = 0;
1883         u32 reg;
1884
1885         reg = RTL_R32(TBICSR);
1886         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1887             (duplex == DUPLEX_FULL)) {
1888                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1889         } else if (autoneg == AUTONEG_ENABLE)
1890                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1891         else {
1892                 netif_warn(tp, link, dev,
1893                            "incorrect speed setting refused in TBI mode\n");
1894                 ret = -EOPNOTSUPP;
1895         }
1896
1897         return ret;
1898 }
1899
1900 static int rtl8169_set_speed_xmii(struct net_device *dev,
1901                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1902 {
1903         struct rtl8169_private *tp = netdev_priv(dev);
1904         int giga_ctrl, bmcr;
1905         int rc = -EINVAL;
1906
1907         rtl_writephy(tp, 0x1f, 0x0000);
1908
1909         if (autoneg == AUTONEG_ENABLE) {
1910                 int auto_nego;
1911
1912                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1913                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1914                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1915
1916                 if (adv & ADVERTISED_10baseT_Half)
1917                         auto_nego |= ADVERTISE_10HALF;
1918                 if (adv & ADVERTISED_10baseT_Full)
1919                         auto_nego |= ADVERTISE_10FULL;
1920                 if (adv & ADVERTISED_100baseT_Half)
1921                         auto_nego |= ADVERTISE_100HALF;
1922                 if (adv & ADVERTISED_100baseT_Full)
1923                         auto_nego |= ADVERTISE_100FULL;
1924
1925                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1926
1927                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1928                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1929
1930                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1931                 if (tp->mii.supports_gmii) {
1932                         if (adv & ADVERTISED_1000baseT_Half)
1933                                 giga_ctrl |= ADVERTISE_1000HALF;
1934                         if (adv & ADVERTISED_1000baseT_Full)
1935                                 giga_ctrl |= ADVERTISE_1000FULL;
1936                 } else if (adv & (ADVERTISED_1000baseT_Half |
1937                                   ADVERTISED_1000baseT_Full)) {
1938                         netif_info(tp, link, dev,
1939                                    "PHY does not support 1000Mbps\n");
1940                         goto out;
1941                 }
1942
1943                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1944
1945                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1946                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1947         } else {
1948                 giga_ctrl = 0;
1949
1950                 if (speed == SPEED_10)
1951                         bmcr = 0;
1952                 else if (speed == SPEED_100)
1953                         bmcr = BMCR_SPEED100;
1954                 else
1955                         goto out;
1956
1957                 if (duplex == DUPLEX_FULL)
1958                         bmcr |= BMCR_FULLDPLX;
1959         }
1960
1961         rtl_writephy(tp, MII_BMCR, bmcr);
1962
1963         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1964             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1965                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1966                         rtl_writephy(tp, 0x17, 0x2138);
1967                         rtl_writephy(tp, 0x0e, 0x0260);
1968                 } else {
1969                         rtl_writephy(tp, 0x17, 0x2108);
1970                         rtl_writephy(tp, 0x0e, 0x0000);
1971                 }
1972         }
1973
1974         rc = 0;
1975 out:
1976         return rc;
1977 }
1978
1979 static int rtl8169_set_speed(struct net_device *dev,
1980                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1981 {
1982         struct rtl8169_private *tp = netdev_priv(dev);
1983         int ret;
1984
1985         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1986         if (ret < 0)
1987                 goto out;
1988
1989         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1990             (advertising & ADVERTISED_1000baseT_Full)) {
1991                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1992         }
1993 out:
1994         return ret;
1995 }
1996
1997 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1998 {
1999         struct rtl8169_private *tp = netdev_priv(dev);
2000         int ret;
2001
2002         del_timer_sync(&tp->timer);
2003
2004         rtl_lock_work(tp);
2005         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2006                                 cmd->duplex, cmd->advertising);
2007         rtl_unlock_work(tp);
2008
2009         return ret;
2010 }
2011
2012 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2013         netdev_features_t features)
2014 {
2015         struct rtl8169_private *tp = netdev_priv(dev);
2016
2017         if (dev->mtu > TD_MSS_MAX)
2018                 features &= ~NETIF_F_ALL_TSO;
2019
2020         if (dev->mtu > JUMBO_1K &&
2021             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2022                 features &= ~NETIF_F_IP_CSUM;
2023
2024         return features;
2025 }
2026
2027 static void __rtl8169_set_features(struct net_device *dev,
2028                                    netdev_features_t features)
2029 {
2030         struct rtl8169_private *tp = netdev_priv(dev);
2031         void __iomem *ioaddr = tp->mmio_addr;
2032         u32 rx_config;
2033
2034         rx_config = RTL_R32(RxConfig);
2035         if (features & NETIF_F_RXALL)
2036                 rx_config |= (AcceptErr | AcceptRunt);
2037         else
2038                 rx_config &= ~(AcceptErr | AcceptRunt);
2039
2040         RTL_W32(RxConfig, rx_config);
2041
2042         if (features & NETIF_F_RXCSUM)
2043                 tp->cp_cmd |= RxChkSum;
2044         else
2045                 tp->cp_cmd &= ~RxChkSum;
2046
2047         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2048                 tp->cp_cmd |= RxVlan;
2049         else
2050                 tp->cp_cmd &= ~RxVlan;
2051
2052         tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2053
2054         RTL_W16(CPlusCmd, tp->cp_cmd);
2055         RTL_R16(CPlusCmd);
2056 }
2057
2058 static int rtl8169_set_features(struct net_device *dev,
2059                                 netdev_features_t features)
2060 {
2061         struct rtl8169_private *tp = netdev_priv(dev);
2062
2063         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2064
2065         rtl_lock_work(tp);
2066         if (features ^ dev->features)
2067                 __rtl8169_set_features(dev, features);
2068         rtl_unlock_work(tp);
2069
2070         return 0;
2071 }
2072
2073
2074 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2075 {
2076         return (skb_vlan_tag_present(skb)) ?
2077                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2078 }
2079
2080 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2081 {
2082         u32 opts2 = le32_to_cpu(desc->opts2);
2083
2084         if (opts2 & RxVlanTag)
2085                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2086 }
2087
2088 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
2089 {
2090         struct rtl8169_private *tp = netdev_priv(dev);
2091         void __iomem *ioaddr = tp->mmio_addr;
2092         u32 status;
2093
2094         cmd->supported =
2095                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2096         cmd->port = PORT_FIBRE;
2097         cmd->transceiver = XCVR_INTERNAL;
2098
2099         status = RTL_R32(TBICSR);
2100         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
2101         cmd->autoneg = !!(status & TBINwEnable);
2102
2103         ethtool_cmd_speed_set(cmd, SPEED_1000);
2104         cmd->duplex = DUPLEX_FULL; /* Always set */
2105
2106         return 0;
2107 }
2108
2109 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
2110 {
2111         struct rtl8169_private *tp = netdev_priv(dev);
2112
2113         return mii_ethtool_gset(&tp->mii, cmd);
2114 }
2115
2116 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2117 {
2118         struct rtl8169_private *tp = netdev_priv(dev);
2119         int rc;
2120
2121         rtl_lock_work(tp);
2122         rc = tp->get_settings(dev, cmd);
2123         rtl_unlock_work(tp);
2124
2125         return rc;
2126 }
2127
2128 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2129                              void *p)
2130 {
2131         struct rtl8169_private *tp = netdev_priv(dev);
2132         u32 __iomem *data = tp->mmio_addr;
2133         u32 *dw = p;
2134         int i;
2135
2136         rtl_lock_work(tp);
2137         for (i = 0; i < R8169_REGS_SIZE; i += 4)
2138                 memcpy_fromio(dw++, data++, 4);
2139         rtl_unlock_work(tp);
2140 }
2141
2142 static u32 rtl8169_get_msglevel(struct net_device *dev)
2143 {
2144         struct rtl8169_private *tp = netdev_priv(dev);
2145
2146         return tp->msg_enable;
2147 }
2148
2149 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2150 {
2151         struct rtl8169_private *tp = netdev_priv(dev);
2152
2153         tp->msg_enable = value;
2154 }
2155
2156 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2157         "tx_packets",
2158         "rx_packets",
2159         "tx_errors",
2160         "rx_errors",
2161         "rx_missed",
2162         "align_errors",
2163         "tx_single_collisions",
2164         "tx_multi_collisions",
2165         "unicast",
2166         "broadcast",
2167         "multicast",
2168         "tx_aborted",
2169         "tx_underrun",
2170 };
2171
2172 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2173 {
2174         switch (sset) {
2175         case ETH_SS_STATS:
2176                 return ARRAY_SIZE(rtl8169_gstrings);
2177         default:
2178                 return -EOPNOTSUPP;
2179         }
2180 }
2181
2182 DECLARE_RTL_COND(rtl_counters_cond)
2183 {
2184         void __iomem *ioaddr = tp->mmio_addr;
2185
2186         return RTL_R32(CounterAddrLow) & CounterDump;
2187 }
2188
2189 static void rtl8169_update_counters(struct net_device *dev)
2190 {
2191         struct rtl8169_private *tp = netdev_priv(dev);
2192         void __iomem *ioaddr = tp->mmio_addr;
2193         struct device *d = &tp->pci_dev->dev;
2194         struct rtl8169_counters *counters;
2195         dma_addr_t paddr;
2196         u32 cmd;
2197
2198         /*
2199          * Some chips are unable to dump tally counters when the receiver
2200          * is disabled.
2201          */
2202         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2203                 return;
2204
2205         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
2206         if (!counters)
2207                 return;
2208
2209         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2210         cmd = (u64)paddr & DMA_BIT_MASK(32);
2211         RTL_W32(CounterAddrLow, cmd);
2212         RTL_W32(CounterAddrLow, cmd | CounterDump);
2213
2214         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
2215                 memcpy(&tp->counters, counters, sizeof(*counters));
2216
2217         RTL_W32(CounterAddrLow, 0);
2218         RTL_W32(CounterAddrHigh, 0);
2219
2220         dma_free_coherent(d, sizeof(*counters), counters, paddr);
2221 }
2222
2223 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2224                                       struct ethtool_stats *stats, u64 *data)
2225 {
2226         struct rtl8169_private *tp = netdev_priv(dev);
2227
2228         ASSERT_RTNL();
2229
2230         rtl8169_update_counters(dev);
2231
2232         data[0] = le64_to_cpu(tp->counters.tx_packets);
2233         data[1] = le64_to_cpu(tp->counters.rx_packets);
2234         data[2] = le64_to_cpu(tp->counters.tx_errors);
2235         data[3] = le32_to_cpu(tp->counters.rx_errors);
2236         data[4] = le16_to_cpu(tp->counters.rx_missed);
2237         data[5] = le16_to_cpu(tp->counters.align_errors);
2238         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2239         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2240         data[8] = le64_to_cpu(tp->counters.rx_unicast);
2241         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2242         data[10] = le32_to_cpu(tp->counters.rx_multicast);
2243         data[11] = le16_to_cpu(tp->counters.tx_aborted);
2244         data[12] = le16_to_cpu(tp->counters.tx_underun);
2245 }
2246
2247 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2248 {
2249         switch(stringset) {
2250         case ETH_SS_STATS:
2251                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2252                 break;
2253         }
2254 }
2255
2256 static const struct ethtool_ops rtl8169_ethtool_ops = {
2257         .get_drvinfo            = rtl8169_get_drvinfo,
2258         .get_regs_len           = rtl8169_get_regs_len,
2259         .get_link               = ethtool_op_get_link,
2260         .get_settings           = rtl8169_get_settings,
2261         .set_settings           = rtl8169_set_settings,
2262         .get_msglevel           = rtl8169_get_msglevel,
2263         .set_msglevel           = rtl8169_set_msglevel,
2264         .get_regs               = rtl8169_get_regs,
2265         .get_wol                = rtl8169_get_wol,
2266         .set_wol                = rtl8169_set_wol,
2267         .get_strings            = rtl8169_get_strings,
2268         .get_sset_count         = rtl8169_get_sset_count,
2269         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2270         .get_ts_info            = ethtool_op_get_ts_info,
2271 };
2272
2273 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2274                                     struct net_device *dev, u8 default_version)
2275 {
2276         void __iomem *ioaddr = tp->mmio_addr;
2277         /*
2278          * The driver currently handles the 8168Bf and the 8168Be identically
2279          * but they can be identified more specifically through the test below
2280          * if needed:
2281          *
2282          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2283          *
2284          * Same thing for the 8101Eb and the 8101Ec:
2285          *
2286          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2287          */
2288         static const struct rtl_mac_info {
2289                 u32 mask;
2290                 u32 val;
2291                 int mac_version;
2292         } mac_info[] = {
2293                 /* 8168EP family. */
2294                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2295                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2296                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2297
2298                 /* 8168H family. */
2299                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2300                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2301
2302                 /* 8168G family. */
2303                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2304                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2305                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2306                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2307
2308                 /* 8168F family. */
2309                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2310                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2311                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2312
2313                 /* 8168E family. */
2314                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2315                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2316                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2317                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2318
2319                 /* 8168D family. */
2320                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2321                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2322                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2323
2324                 /* 8168DP family. */
2325                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2326                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2327                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2328
2329                 /* 8168C family. */
2330                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2331                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2332                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2333                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2334                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2335                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2336                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2337                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2338                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2339
2340                 /* 8168B family. */
2341                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2342                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2343                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2344                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2345
2346                 /* 8101 family. */
2347                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2348                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2349                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2350                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2351                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2352                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2353                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2354                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2355                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2356                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2357                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2358                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2359                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2360                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2361                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2362                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2363                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2364                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2365                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2366                 /* FIXME: where did these entries come from ? -- FR */
2367                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2368                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2369
2370                 /* 8110 family. */
2371                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2372                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2373                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2374                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2375                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2376                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2377
2378                 /* Catch-all */
2379                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2380         };
2381         const struct rtl_mac_info *p = mac_info;
2382         u32 reg;
2383
2384         reg = RTL_R32(TxConfig);
2385         while ((reg & p->mask) != p->val)
2386                 p++;
2387         tp->mac_version = p->mac_version;
2388
2389         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2390                 netif_notice(tp, probe, dev,
2391                              "unknown MAC, using family default\n");
2392                 tp->mac_version = default_version;
2393         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2394                 tp->mac_version = tp->mii.supports_gmii ?
2395                                   RTL_GIGA_MAC_VER_42 :
2396                                   RTL_GIGA_MAC_VER_43;
2397         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2398                 tp->mac_version = tp->mii.supports_gmii ?
2399                                   RTL_GIGA_MAC_VER_45 :
2400                                   RTL_GIGA_MAC_VER_47;
2401         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2402                 tp->mac_version = tp->mii.supports_gmii ?
2403                                   RTL_GIGA_MAC_VER_46 :
2404                                   RTL_GIGA_MAC_VER_48;
2405         }
2406 }
2407
2408 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2409 {
2410         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2411 }
2412
2413 struct phy_reg {
2414         u16 reg;
2415         u16 val;
2416 };
2417
2418 static void rtl_writephy_batch(struct rtl8169_private *tp,
2419                                const struct phy_reg *regs, int len)
2420 {
2421         while (len-- > 0) {
2422                 rtl_writephy(tp, regs->reg, regs->val);
2423                 regs++;
2424         }
2425 }
2426
2427 #define PHY_READ                0x00000000
2428 #define PHY_DATA_OR             0x10000000
2429 #define PHY_DATA_AND            0x20000000
2430 #define PHY_BJMPN               0x30000000
2431 #define PHY_MDIO_CHG            0x40000000
2432 #define PHY_CLEAR_READCOUNT     0x70000000
2433 #define PHY_WRITE               0x80000000
2434 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2435 #define PHY_COMP_EQ_SKIPN       0xa0000000
2436 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2437 #define PHY_WRITE_PREVIOUS      0xc0000000
2438 #define PHY_SKIPN               0xd0000000
2439 #define PHY_DELAY_MS            0xe0000000
2440
2441 struct fw_info {
2442         u32     magic;
2443         char    version[RTL_VER_SIZE];
2444         __le32  fw_start;
2445         __le32  fw_len;
2446         u8      chksum;
2447 } __packed;
2448
2449 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2450
2451 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2452 {
2453         const struct firmware *fw = rtl_fw->fw;
2454         struct fw_info *fw_info = (struct fw_info *)fw->data;
2455         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2456         char *version = rtl_fw->version;
2457         bool rc = false;
2458
2459         if (fw->size < FW_OPCODE_SIZE)
2460                 goto out;
2461
2462         if (!fw_info->magic) {
2463                 size_t i, size, start;
2464                 u8 checksum = 0;
2465
2466                 if (fw->size < sizeof(*fw_info))
2467                         goto out;
2468
2469                 for (i = 0; i < fw->size; i++)
2470                         checksum += fw->data[i];
2471                 if (checksum != 0)
2472                         goto out;
2473
2474                 start = le32_to_cpu(fw_info->fw_start);
2475                 if (start > fw->size)
2476                         goto out;
2477
2478                 size = le32_to_cpu(fw_info->fw_len);
2479                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2480                         goto out;
2481
2482                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2483
2484                 pa->code = (__le32 *)(fw->data + start);
2485                 pa->size = size;
2486         } else {
2487                 if (fw->size % FW_OPCODE_SIZE)
2488                         goto out;
2489
2490                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2491
2492                 pa->code = (__le32 *)fw->data;
2493                 pa->size = fw->size / FW_OPCODE_SIZE;
2494         }
2495         version[RTL_VER_SIZE - 1] = 0;
2496
2497         rc = true;
2498 out:
2499         return rc;
2500 }
2501
2502 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2503                            struct rtl_fw_phy_action *pa)
2504 {
2505         bool rc = false;
2506         size_t index;
2507
2508         for (index = 0; index < pa->size; index++) {
2509                 u32 action = le32_to_cpu(pa->code[index]);
2510                 u32 regno = (action & 0x0fff0000) >> 16;
2511
2512                 switch(action & 0xf0000000) {
2513                 case PHY_READ:
2514                 case PHY_DATA_OR:
2515                 case PHY_DATA_AND:
2516                 case PHY_MDIO_CHG:
2517                 case PHY_CLEAR_READCOUNT:
2518                 case PHY_WRITE:
2519                 case PHY_WRITE_PREVIOUS:
2520                 case PHY_DELAY_MS:
2521                         break;
2522
2523                 case PHY_BJMPN:
2524                         if (regno > index) {
2525                                 netif_err(tp, ifup, tp->dev,
2526                                           "Out of range of firmware\n");
2527                                 goto out;
2528                         }
2529                         break;
2530                 case PHY_READCOUNT_EQ_SKIP:
2531                         if (index + 2 >= pa->size) {
2532                                 netif_err(tp, ifup, tp->dev,
2533                                           "Out of range of firmware\n");
2534                                 goto out;
2535                         }
2536                         break;
2537                 case PHY_COMP_EQ_SKIPN:
2538                 case PHY_COMP_NEQ_SKIPN:
2539                 case PHY_SKIPN:
2540                         if (index + 1 + regno >= pa->size) {
2541                                 netif_err(tp, ifup, tp->dev,
2542                                           "Out of range of firmware\n");
2543                                 goto out;
2544                         }
2545                         break;
2546
2547                 default:
2548                         netif_err(tp, ifup, tp->dev,
2549                                   "Invalid action 0x%08x\n", action);
2550                         goto out;
2551                 }
2552         }
2553         rc = true;
2554 out:
2555         return rc;
2556 }
2557
2558 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2559 {
2560         struct net_device *dev = tp->dev;
2561         int rc = -EINVAL;
2562
2563         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2564                 netif_err(tp, ifup, dev, "invalid firmware\n");
2565                 goto out;
2566         }
2567
2568         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2569                 rc = 0;
2570 out:
2571         return rc;
2572 }
2573
2574 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2575 {
2576         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2577         struct mdio_ops org, *ops = &tp->mdio_ops;
2578         u32 predata, count;
2579         size_t index;
2580
2581         predata = count = 0;
2582         org.write = ops->write;
2583         org.read = ops->read;
2584
2585         for (index = 0; index < pa->size; ) {
2586                 u32 action = le32_to_cpu(pa->code[index]);
2587                 u32 data = action & 0x0000ffff;
2588                 u32 regno = (action & 0x0fff0000) >> 16;
2589
2590                 if (!action)
2591                         break;
2592
2593                 switch(action & 0xf0000000) {
2594                 case PHY_READ:
2595                         predata = rtl_readphy(tp, regno);
2596                         count++;
2597                         index++;
2598                         break;
2599                 case PHY_DATA_OR:
2600                         predata |= data;
2601                         index++;
2602                         break;
2603                 case PHY_DATA_AND:
2604                         predata &= data;
2605                         index++;
2606                         break;
2607                 case PHY_BJMPN:
2608                         index -= regno;
2609                         break;
2610                 case PHY_MDIO_CHG:
2611                         if (data == 0) {
2612                                 ops->write = org.write;
2613                                 ops->read = org.read;
2614                         } else if (data == 1) {
2615                                 ops->write = mac_mcu_write;
2616                                 ops->read = mac_mcu_read;
2617                         }
2618
2619                         index++;
2620                         break;
2621                 case PHY_CLEAR_READCOUNT:
2622                         count = 0;
2623                         index++;
2624                         break;
2625                 case PHY_WRITE:
2626                         rtl_writephy(tp, regno, data);
2627                         index++;
2628                         break;
2629                 case PHY_READCOUNT_EQ_SKIP:
2630                         index += (count == data) ? 2 : 1;
2631                         break;
2632                 case PHY_COMP_EQ_SKIPN:
2633                         if (predata == data)
2634                                 index += regno;
2635                         index++;
2636                         break;
2637                 case PHY_COMP_NEQ_SKIPN:
2638                         if (predata != data)
2639                                 index += regno;
2640                         index++;
2641                         break;
2642                 case PHY_WRITE_PREVIOUS:
2643                         rtl_writephy(tp, regno, predata);
2644                         index++;
2645                         break;
2646                 case PHY_SKIPN:
2647                         index += regno + 1;
2648                         break;
2649                 case PHY_DELAY_MS:
2650                         mdelay(data);
2651                         index++;
2652                         break;
2653
2654                 default:
2655                         BUG();
2656                 }
2657         }
2658
2659         ops->write = org.write;
2660         ops->read = org.read;
2661 }
2662
2663 static void rtl_release_firmware(struct rtl8169_private *tp)
2664 {
2665         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2666                 release_firmware(tp->rtl_fw->fw);
2667                 kfree(tp->rtl_fw);
2668         }
2669         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2670 }
2671
2672 static void rtl_apply_firmware(struct rtl8169_private *tp)
2673 {
2674         struct rtl_fw *rtl_fw = tp->rtl_fw;
2675
2676         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2677         if (!IS_ERR_OR_NULL(rtl_fw))
2678                 rtl_phy_write_fw(tp, rtl_fw);
2679 }
2680
2681 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2682 {
2683         if (rtl_readphy(tp, reg) != val)
2684                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2685         else
2686                 rtl_apply_firmware(tp);
2687 }
2688
2689 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2690 {
2691         static const struct phy_reg phy_reg_init[] = {
2692                 { 0x1f, 0x0001 },
2693                 { 0x06, 0x006e },
2694                 { 0x08, 0x0708 },
2695                 { 0x15, 0x4000 },
2696                 { 0x18, 0x65c7 },
2697
2698                 { 0x1f, 0x0001 },
2699                 { 0x03, 0x00a1 },
2700                 { 0x02, 0x0008 },
2701                 { 0x01, 0x0120 },
2702                 { 0x00, 0x1000 },
2703                 { 0x04, 0x0800 },
2704                 { 0x04, 0x0000 },
2705
2706                 { 0x03, 0xff41 },
2707                 { 0x02, 0xdf60 },
2708                 { 0x01, 0x0140 },
2709                 { 0x00, 0x0077 },
2710                 { 0x04, 0x7800 },
2711                 { 0x04, 0x7000 },
2712
2713                 { 0x03, 0x802f },
2714                 { 0x02, 0x4f02 },
2715                 { 0x01, 0x0409 },
2716                 { 0x00, 0xf0f9 },
2717                 { 0x04, 0x9800 },
2718                 { 0x04, 0x9000 },
2719
2720                 { 0x03, 0xdf01 },
2721                 { 0x02, 0xdf20 },
2722                 { 0x01, 0xff95 },
2723                 { 0x00, 0xba00 },
2724                 { 0x04, 0xa800 },
2725                 { 0x04, 0xa000 },
2726
2727                 { 0x03, 0xff41 },
2728                 { 0x02, 0xdf20 },
2729                 { 0x01, 0x0140 },
2730                 { 0x00, 0x00bb },
2731                 { 0x04, 0xb800 },
2732                 { 0x04, 0xb000 },
2733
2734                 { 0x03, 0xdf41 },
2735                 { 0x02, 0xdc60 },
2736                 { 0x01, 0x6340 },
2737                 { 0x00, 0x007d },
2738                 { 0x04, 0xd800 },
2739                 { 0x04, 0xd000 },
2740
2741                 { 0x03, 0xdf01 },
2742                 { 0x02, 0xdf20 },
2743                 { 0x01, 0x100a },
2744                 { 0x00, 0xa0ff },
2745                 { 0x04, 0xf800 },
2746                 { 0x04, 0xf000 },
2747
2748                 { 0x1f, 0x0000 },
2749                 { 0x0b, 0x0000 },
2750                 { 0x00, 0x9200 }
2751         };
2752
2753         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2754 }
2755
2756 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2757 {
2758         static const struct phy_reg phy_reg_init[] = {
2759                 { 0x1f, 0x0002 },
2760                 { 0x01, 0x90d0 },
2761                 { 0x1f, 0x0000 }
2762         };
2763
2764         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2765 }
2766
2767 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2768 {
2769         struct pci_dev *pdev = tp->pci_dev;
2770
2771         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2772             (pdev->subsystem_device != 0xe000))
2773                 return;
2774
2775         rtl_writephy(tp, 0x1f, 0x0001);
2776         rtl_writephy(tp, 0x10, 0xf01b);
2777         rtl_writephy(tp, 0x1f, 0x0000);
2778 }
2779
2780 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2781 {
2782         static const struct phy_reg phy_reg_init[] = {
2783                 { 0x1f, 0x0001 },
2784                 { 0x04, 0x0000 },
2785                 { 0x03, 0x00a1 },
2786                 { 0x02, 0x0008 },
2787                 { 0x01, 0x0120 },
2788                 { 0x00, 0x1000 },
2789                 { 0x04, 0x0800 },
2790                 { 0x04, 0x9000 },
2791                 { 0x03, 0x802f },
2792                 { 0x02, 0x4f02 },
2793                 { 0x01, 0x0409 },
2794                 { 0x00, 0xf099 },
2795                 { 0x04, 0x9800 },
2796                 { 0x04, 0xa000 },
2797                 { 0x03, 0xdf01 },
2798                 { 0x02, 0xdf20 },
2799                 { 0x01, 0xff95 },
2800                 { 0x00, 0xba00 },
2801                 { 0x04, 0xa800 },
2802                 { 0x04, 0xf000 },
2803                 { 0x03, 0xdf01 },
2804                 { 0x02, 0xdf20 },
2805                 { 0x01, 0x101a },
2806                 { 0x00, 0xa0ff },
2807                 { 0x04, 0xf800 },
2808                 { 0x04, 0x0000 },
2809                 { 0x1f, 0x0000 },
2810
2811                 { 0x1f, 0x0001 },
2812                 { 0x10, 0xf41b },
2813                 { 0x14, 0xfb54 },
2814                 { 0x18, 0xf5c7 },
2815                 { 0x1f, 0x0000 },
2816
2817                 { 0x1f, 0x0001 },
2818                 { 0x17, 0x0cc0 },
2819                 { 0x1f, 0x0000 }
2820         };
2821
2822         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2823
2824         rtl8169scd_hw_phy_config_quirk(tp);
2825 }
2826
2827 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2828 {
2829         static const struct phy_reg phy_reg_init[] = {
2830                 { 0x1f, 0x0001 },
2831                 { 0x04, 0x0000 },
2832                 { 0x03, 0x00a1 },
2833                 { 0x02, 0x0008 },
2834                 { 0x01, 0x0120 },
2835                 { 0x00, 0x1000 },
2836                 { 0x04, 0x0800 },
2837                 { 0x04, 0x9000 },
2838                 { 0x03, 0x802f },
2839                 { 0x02, 0x4f02 },
2840                 { 0x01, 0x0409 },
2841                 { 0x00, 0xf099 },
2842                 { 0x04, 0x9800 },
2843                 { 0x04, 0xa000 },
2844                 { 0x03, 0xdf01 },
2845                 { 0x02, 0xdf20 },
2846                 { 0x01, 0xff95 },
2847                 { 0x00, 0xba00 },
2848                 { 0x04, 0xa800 },
2849                 { 0x04, 0xf000 },
2850                 { 0x03, 0xdf01 },
2851                 { 0x02, 0xdf20 },
2852                 { 0x01, 0x101a },
2853                 { 0x00, 0xa0ff },
2854                 { 0x04, 0xf800 },
2855                 { 0x04, 0x0000 },
2856                 { 0x1f, 0x0000 },
2857
2858                 { 0x1f, 0x0001 },
2859                 { 0x0b, 0x8480 },
2860                 { 0x1f, 0x0000 },
2861
2862                 { 0x1f, 0x0001 },
2863                 { 0x18, 0x67c7 },
2864                 { 0x04, 0x2000 },
2865                 { 0x03, 0x002f },
2866                 { 0x02, 0x4360 },
2867                 { 0x01, 0x0109 },
2868                 { 0x00, 0x3022 },
2869                 { 0x04, 0x2800 },
2870                 { 0x1f, 0x0000 },
2871
2872                 { 0x1f, 0x0001 },
2873                 { 0x17, 0x0cc0 },
2874                 { 0x1f, 0x0000 }
2875         };
2876
2877         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2878 }
2879
2880 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2881 {
2882         static const struct phy_reg phy_reg_init[] = {
2883                 { 0x10, 0xf41b },
2884                 { 0x1f, 0x0000 }
2885         };
2886
2887         rtl_writephy(tp, 0x1f, 0x0001);
2888         rtl_patchphy(tp, 0x16, 1 << 0);
2889
2890         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2891 }
2892
2893 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2894 {
2895         static const struct phy_reg phy_reg_init[] = {
2896                 { 0x1f, 0x0001 },
2897                 { 0x10, 0xf41b },
2898                 { 0x1f, 0x0000 }
2899         };
2900
2901         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2902 }
2903
2904 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2905 {
2906         static const struct phy_reg phy_reg_init[] = {
2907                 { 0x1f, 0x0000 },
2908                 { 0x1d, 0x0f00 },
2909                 { 0x1f, 0x0002 },
2910                 { 0x0c, 0x1ec8 },
2911                 { 0x1f, 0x0000 }
2912         };
2913
2914         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2915 }
2916
2917 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2918 {
2919         static const struct phy_reg phy_reg_init[] = {
2920                 { 0x1f, 0x0001 },
2921                 { 0x1d, 0x3d98 },
2922                 { 0x1f, 0x0000 }
2923         };
2924
2925         rtl_writephy(tp, 0x1f, 0x0000);
2926         rtl_patchphy(tp, 0x14, 1 << 5);
2927         rtl_patchphy(tp, 0x0d, 1 << 5);
2928
2929         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2930 }
2931
2932 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2933 {
2934         static const struct phy_reg phy_reg_init[] = {
2935                 { 0x1f, 0x0001 },
2936                 { 0x12, 0x2300 },
2937                 { 0x1f, 0x0002 },
2938                 { 0x00, 0x88d4 },
2939                 { 0x01, 0x82b1 },
2940                 { 0x03, 0x7002 },
2941                 { 0x08, 0x9e30 },
2942                 { 0x09, 0x01f0 },
2943                 { 0x0a, 0x5500 },
2944                 { 0x0c, 0x00c8 },
2945                 { 0x1f, 0x0003 },
2946                 { 0x12, 0xc096 },
2947                 { 0x16, 0x000a },
2948                 { 0x1f, 0x0000 },
2949                 { 0x1f, 0x0000 },
2950                 { 0x09, 0x2000 },
2951                 { 0x09, 0x0000 }
2952         };
2953
2954         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2955
2956         rtl_patchphy(tp, 0x14, 1 << 5);
2957         rtl_patchphy(tp, 0x0d, 1 << 5);
2958         rtl_writephy(tp, 0x1f, 0x0000);
2959 }
2960
2961 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2962 {
2963         static const struct phy_reg phy_reg_init[] = {
2964                 { 0x1f, 0x0001 },
2965                 { 0x12, 0x2300 },
2966                 { 0x03, 0x802f },
2967                 { 0x02, 0x4f02 },
2968                 { 0x01, 0x0409 },
2969                 { 0x00, 0xf099 },
2970                 { 0x04, 0x9800 },
2971                 { 0x04, 0x9000 },
2972                 { 0x1d, 0x3d98 },
2973                 { 0x1f, 0x0002 },
2974                 { 0x0c, 0x7eb8 },
2975                 { 0x06, 0x0761 },
2976                 { 0x1f, 0x0003 },
2977                 { 0x16, 0x0f0a },
2978                 { 0x1f, 0x0000 }
2979         };
2980
2981         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2982
2983         rtl_patchphy(tp, 0x16, 1 << 0);
2984         rtl_patchphy(tp, 0x14, 1 << 5);
2985         rtl_patchphy(tp, 0x0d, 1 << 5);
2986         rtl_writephy(tp, 0x1f, 0x0000);
2987 }
2988
2989 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2990 {
2991         static const struct phy_reg phy_reg_init[] = {
2992                 { 0x1f, 0x0001 },
2993                 { 0x12, 0x2300 },
2994                 { 0x1d, 0x3d98 },
2995                 { 0x1f, 0x0002 },
2996                 { 0x0c, 0x7eb8 },
2997                 { 0x06, 0x5461 },
2998                 { 0x1f, 0x0003 },
2999                 { 0x16, 0x0f0a },
3000                 { 0x1f, 0x0000 }
3001         };
3002
3003         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3004
3005         rtl_patchphy(tp, 0x16, 1 << 0);
3006         rtl_patchphy(tp, 0x14, 1 << 5);
3007         rtl_patchphy(tp, 0x0d, 1 << 5);
3008         rtl_writephy(tp, 0x1f, 0x0000);
3009 }
3010
3011 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3012 {
3013         rtl8168c_3_hw_phy_config(tp);
3014 }
3015
3016 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3017 {
3018         static const struct phy_reg phy_reg_init_0[] = {
3019                 /* Channel Estimation */
3020                 { 0x1f, 0x0001 },
3021                 { 0x06, 0x4064 },
3022                 { 0x07, 0x2863 },
3023                 { 0x08, 0x059c },
3024                 { 0x09, 0x26b4 },
3025                 { 0x0a, 0x6a19 },
3026                 { 0x0b, 0xdcc8 },
3027                 { 0x10, 0xf06d },
3028                 { 0x14, 0x7f68 },
3029                 { 0x18, 0x7fd9 },
3030                 { 0x1c, 0xf0ff },
3031                 { 0x1d, 0x3d9c },
3032                 { 0x1f, 0x0003 },
3033                 { 0x12, 0xf49f },
3034                 { 0x13, 0x070b },
3035                 { 0x1a, 0x05ad },
3036                 { 0x14, 0x94c0 },
3037
3038                 /*
3039                  * Tx Error Issue
3040                  * Enhance line driver power
3041                  */
3042                 { 0x1f, 0x0002 },
3043                 { 0x06, 0x5561 },
3044                 { 0x1f, 0x0005 },
3045                 { 0x05, 0x8332 },
3046                 { 0x06, 0x5561 },
3047
3048                 /*
3049                  * Can not link to 1Gbps with bad cable
3050                  * Decrease SNR threshold form 21.07dB to 19.04dB
3051                  */
3052                 { 0x1f, 0x0001 },
3053                 { 0x17, 0x0cc0 },
3054
3055                 { 0x1f, 0x0000 },
3056                 { 0x0d, 0xf880 }
3057         };
3058
3059         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3060
3061         /*
3062          * Rx Error Issue
3063          * Fine Tune Switching regulator parameter
3064          */
3065         rtl_writephy(tp, 0x1f, 0x0002);
3066         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3067         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3068
3069         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3070                 static const struct phy_reg phy_reg_init[] = {
3071                         { 0x1f, 0x0002 },
3072                         { 0x05, 0x669a },
3073                         { 0x1f, 0x0005 },
3074                         { 0x05, 0x8330 },
3075                         { 0x06, 0x669a },
3076                         { 0x1f, 0x0002 }
3077                 };
3078                 int val;
3079
3080                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3081
3082                 val = rtl_readphy(tp, 0x0d);
3083
3084                 if ((val & 0x00ff) != 0x006c) {
3085                         static const u32 set[] = {
3086                                 0x0065, 0x0066, 0x0067, 0x0068,
3087                                 0x0069, 0x006a, 0x006b, 0x006c
3088                         };
3089                         int i;
3090
3091                         rtl_writephy(tp, 0x1f, 0x0002);
3092
3093                         val &= 0xff00;
3094                         for (i = 0; i < ARRAY_SIZE(set); i++)
3095                                 rtl_writephy(tp, 0x0d, val | set[i]);
3096                 }
3097         } else {
3098                 static const struct phy_reg phy_reg_init[] = {
3099                         { 0x1f, 0x0002 },
3100                         { 0x05, 0x6662 },
3101                         { 0x1f, 0x0005 },
3102                         { 0x05, 0x8330 },
3103                         { 0x06, 0x6662 }
3104                 };
3105
3106                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3107         }
3108
3109         /* RSET couple improve */
3110         rtl_writephy(tp, 0x1f, 0x0002);
3111         rtl_patchphy(tp, 0x0d, 0x0300);
3112         rtl_patchphy(tp, 0x0f, 0x0010);
3113
3114         /* Fine tune PLL performance */
3115         rtl_writephy(tp, 0x1f, 0x0002);
3116         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3117         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3118
3119         rtl_writephy(tp, 0x1f, 0x0005);
3120         rtl_writephy(tp, 0x05, 0x001b);
3121
3122         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3123
3124         rtl_writephy(tp, 0x1f, 0x0000);
3125 }
3126
3127 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3128 {
3129         static const struct phy_reg phy_reg_init_0[] = {
3130                 /* Channel Estimation */
3131                 { 0x1f, 0x0001 },
3132                 { 0x06, 0x4064 },
3133                 { 0x07, 0x2863 },
3134                 { 0x08, 0x059c },
3135                 { 0x09, 0x26b4 },
3136                 { 0x0a, 0x6a19 },
3137                 { 0x0b, 0xdcc8 },
3138                 { 0x10, 0xf06d },
3139                 { 0x14, 0x7f68 },
3140                 { 0x18, 0x7fd9 },
3141                 { 0x1c, 0xf0ff },
3142                 { 0x1d, 0x3d9c },
3143                 { 0x1f, 0x0003 },
3144                 { 0x12, 0xf49f },
3145                 { 0x13, 0x070b },
3146                 { 0x1a, 0x05ad },
3147                 { 0x14, 0x94c0 },
3148
3149                 /*
3150                  * Tx Error Issue
3151                  * Enhance line driver power
3152                  */
3153                 { 0x1f, 0x0002 },
3154                 { 0x06, 0x5561 },
3155                 { 0x1f, 0x0005 },
3156                 { 0x05, 0x8332 },
3157                 { 0x06, 0x5561 },
3158
3159                 /*
3160                  * Can not link to 1Gbps with bad cable
3161                  * Decrease SNR threshold form 21.07dB to 19.04dB
3162                  */
3163                 { 0x1f, 0x0001 },
3164                 { 0x17, 0x0cc0 },
3165
3166                 { 0x1f, 0x0000 },
3167                 { 0x0d, 0xf880 }
3168         };
3169
3170         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3171
3172         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3173                 static const struct phy_reg phy_reg_init[] = {
3174                         { 0x1f, 0x0002 },
3175                         { 0x05, 0x669a },
3176                         { 0x1f, 0x0005 },
3177                         { 0x05, 0x8330 },
3178                         { 0x06, 0x669a },
3179
3180                         { 0x1f, 0x0002 }
3181                 };
3182                 int val;
3183
3184                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3185
3186                 val = rtl_readphy(tp, 0x0d);
3187                 if ((val & 0x00ff) != 0x006c) {
3188                         static const u32 set[] = {
3189                                 0x0065, 0x0066, 0x0067, 0x0068,
3190                                 0x0069, 0x006a, 0x006b, 0x006c
3191                         };
3192                         int i;
3193
3194                         rtl_writephy(tp, 0x1f, 0x0002);
3195
3196                         val &= 0xff00;
3197                         for (i = 0; i < ARRAY_SIZE(set); i++)
3198                                 rtl_writephy(tp, 0x0d, val | set[i]);
3199                 }
3200         } else {
3201                 static const struct phy_reg phy_reg_init[] = {
3202                         { 0x1f, 0x0002 },
3203                         { 0x05, 0x2642 },
3204                         { 0x1f, 0x0005 },
3205                         { 0x05, 0x8330 },
3206                         { 0x06, 0x2642 }
3207                 };
3208
3209                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3210         }
3211
3212         /* Fine tune PLL performance */
3213         rtl_writephy(tp, 0x1f, 0x0002);
3214         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3215         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3216
3217         /* Switching regulator Slew rate */
3218         rtl_writephy(tp, 0x1f, 0x0002);
3219         rtl_patchphy(tp, 0x0f, 0x0017);
3220
3221         rtl_writephy(tp, 0x1f, 0x0005);
3222         rtl_writephy(tp, 0x05, 0x001b);
3223
3224         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3225
3226         rtl_writephy(tp, 0x1f, 0x0000);
3227 }
3228
3229 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3230 {
3231         static const struct phy_reg phy_reg_init[] = {
3232                 { 0x1f, 0x0002 },
3233                 { 0x10, 0x0008 },
3234                 { 0x0d, 0x006c },
3235
3236                 { 0x1f, 0x0000 },
3237                 { 0x0d, 0xf880 },
3238
3239                 { 0x1f, 0x0001 },
3240                 { 0x17, 0x0cc0 },
3241
3242                 { 0x1f, 0x0001 },
3243                 { 0x0b, 0xa4d8 },
3244                 { 0x09, 0x281c },
3245                 { 0x07, 0x2883 },
3246                 { 0x0a, 0x6b35 },
3247                 { 0x1d, 0x3da4 },
3248                 { 0x1c, 0xeffd },
3249                 { 0x14, 0x7f52 },
3250                 { 0x18, 0x7fc6 },
3251                 { 0x08, 0x0601 },
3252                 { 0x06, 0x4063 },
3253                 { 0x10, 0xf074 },
3254                 { 0x1f, 0x0003 },
3255                 { 0x13, 0x0789 },
3256                 { 0x12, 0xf4bd },
3257                 { 0x1a, 0x04fd },
3258                 { 0x14, 0x84b0 },
3259                 { 0x1f, 0x0000 },
3260                 { 0x00, 0x9200 },
3261
3262                 { 0x1f, 0x0005 },
3263                 { 0x01, 0x0340 },
3264                 { 0x1f, 0x0001 },
3265                 { 0x04, 0x4000 },
3266                 { 0x03, 0x1d21 },
3267                 { 0x02, 0x0c32 },
3268                 { 0x01, 0x0200 },
3269                 { 0x00, 0x5554 },
3270                 { 0x04, 0x4800 },
3271                 { 0x04, 0x4000 },
3272                 { 0x04, 0xf000 },
3273                 { 0x03, 0xdf01 },
3274                 { 0x02, 0xdf20 },
3275                 { 0x01, 0x101a },
3276                 { 0x00, 0xa0ff },
3277                 { 0x04, 0xf800 },
3278                 { 0x04, 0xf000 },
3279                 { 0x1f, 0x0000 },
3280
3281                 { 0x1f, 0x0007 },
3282                 { 0x1e, 0x0023 },
3283                 { 0x16, 0x0000 },
3284                 { 0x1f, 0x0000 }
3285         };
3286
3287         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3288 }
3289
3290 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3291 {
3292         static const struct phy_reg phy_reg_init[] = {
3293                 { 0x1f, 0x0001 },
3294                 { 0x17, 0x0cc0 },
3295
3296                 { 0x1f, 0x0007 },
3297                 { 0x1e, 0x002d },
3298                 { 0x18, 0x0040 },
3299                 { 0x1f, 0x0000 }
3300         };
3301
3302         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3303         rtl_patchphy(tp, 0x0d, 1 << 5);
3304 }
3305
3306 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3307 {
3308         static const struct phy_reg phy_reg_init[] = {
3309                 /* Enable Delay cap */
3310                 { 0x1f, 0x0005 },
3311                 { 0x05, 0x8b80 },
3312                 { 0x06, 0xc896 },
3313                 { 0x1f, 0x0000 },
3314
3315                 /* Channel estimation fine tune */
3316                 { 0x1f, 0x0001 },
3317                 { 0x0b, 0x6c20 },
3318                 { 0x07, 0x2872 },
3319                 { 0x1c, 0xefff },
3320                 { 0x1f, 0x0003 },
3321                 { 0x14, 0x6420 },
3322                 { 0x1f, 0x0000 },
3323
3324                 /* Update PFM & 10M TX idle timer */
3325                 { 0x1f, 0x0007 },
3326                 { 0x1e, 0x002f },
3327                 { 0x15, 0x1919 },
3328                 { 0x1f, 0x0000 },
3329
3330                 { 0x1f, 0x0007 },
3331                 { 0x1e, 0x00ac },
3332                 { 0x18, 0x0006 },
3333                 { 0x1f, 0x0000 }
3334         };
3335
3336         rtl_apply_firmware(tp);
3337
3338         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3339
3340         /* DCO enable for 10M IDLE Power */
3341         rtl_writephy(tp, 0x1f, 0x0007);
3342         rtl_writephy(tp, 0x1e, 0x0023);
3343         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3344         rtl_writephy(tp, 0x1f, 0x0000);
3345
3346         /* For impedance matching */
3347         rtl_writephy(tp, 0x1f, 0x0002);
3348         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3349         rtl_writephy(tp, 0x1f, 0x0000);
3350
3351         /* PHY auto speed down */
3352         rtl_writephy(tp, 0x1f, 0x0007);
3353         rtl_writephy(tp, 0x1e, 0x002d);
3354         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3355         rtl_writephy(tp, 0x1f, 0x0000);
3356         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3357
3358         rtl_writephy(tp, 0x1f, 0x0005);
3359         rtl_writephy(tp, 0x05, 0x8b86);
3360         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3361         rtl_writephy(tp, 0x1f, 0x0000);
3362
3363         rtl_writephy(tp, 0x1f, 0x0005);
3364         rtl_writephy(tp, 0x05, 0x8b85);
3365         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3366         rtl_writephy(tp, 0x1f, 0x0007);
3367         rtl_writephy(tp, 0x1e, 0x0020);
3368         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3369         rtl_writephy(tp, 0x1f, 0x0006);
3370         rtl_writephy(tp, 0x00, 0x5a00);
3371         rtl_writephy(tp, 0x1f, 0x0000);
3372         rtl_writephy(tp, 0x0d, 0x0007);
3373         rtl_writephy(tp, 0x0e, 0x003c);
3374         rtl_writephy(tp, 0x0d, 0x4007);
3375         rtl_writephy(tp, 0x0e, 0x0000);
3376         rtl_writephy(tp, 0x0d, 0x0000);
3377 }
3378
3379 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3380 {
3381         const u16 w[] = {
3382                 addr[0] | (addr[1] << 8),
3383                 addr[2] | (addr[3] << 8),
3384                 addr[4] | (addr[5] << 8)
3385         };
3386         const struct exgmac_reg e[] = {
3387                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3388                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3389                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3390                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3391         };
3392
3393         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3394 }
3395
3396 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3397 {
3398         static const struct phy_reg phy_reg_init[] = {
3399                 /* Enable Delay cap */
3400                 { 0x1f, 0x0004 },
3401                 { 0x1f, 0x0007 },
3402                 { 0x1e, 0x00ac },
3403                 { 0x18, 0x0006 },
3404                 { 0x1f, 0x0002 },
3405                 { 0x1f, 0x0000 },
3406                 { 0x1f, 0x0000 },
3407
3408                 /* Channel estimation fine tune */
3409                 { 0x1f, 0x0003 },
3410                 { 0x09, 0xa20f },
3411                 { 0x1f, 0x0000 },
3412                 { 0x1f, 0x0000 },
3413
3414                 /* Green Setting */
3415                 { 0x1f, 0x0005 },
3416                 { 0x05, 0x8b5b },
3417                 { 0x06, 0x9222 },
3418                 { 0x05, 0x8b6d },
3419                 { 0x06, 0x8000 },
3420                 { 0x05, 0x8b76 },
3421                 { 0x06, 0x8000 },
3422                 { 0x1f, 0x0000 }
3423         };
3424
3425         rtl_apply_firmware(tp);
3426
3427         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3428
3429         /* For 4-corner performance improve */
3430         rtl_writephy(tp, 0x1f, 0x0005);
3431         rtl_writephy(tp, 0x05, 0x8b80);
3432         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3433         rtl_writephy(tp, 0x1f, 0x0000);
3434
3435         /* PHY auto speed down */
3436         rtl_writephy(tp, 0x1f, 0x0004);
3437         rtl_writephy(tp, 0x1f, 0x0007);
3438         rtl_writephy(tp, 0x1e, 0x002d);
3439         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3440         rtl_writephy(tp, 0x1f, 0x0002);
3441         rtl_writephy(tp, 0x1f, 0x0000);
3442         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3443
3444         /* improve 10M EEE waveform */
3445         rtl_writephy(tp, 0x1f, 0x0005);
3446         rtl_writephy(tp, 0x05, 0x8b86);
3447         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3448         rtl_writephy(tp, 0x1f, 0x0000);
3449
3450         /* Improve 2-pair detection performance */
3451         rtl_writephy(tp, 0x1f, 0x0005);
3452         rtl_writephy(tp, 0x05, 0x8b85);
3453         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3454         rtl_writephy(tp, 0x1f, 0x0000);
3455
3456         /* EEE setting */
3457         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3458         rtl_writephy(tp, 0x1f, 0x0005);
3459         rtl_writephy(tp, 0x05, 0x8b85);
3460         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3461         rtl_writephy(tp, 0x1f, 0x0004);
3462         rtl_writephy(tp, 0x1f, 0x0007);
3463         rtl_writephy(tp, 0x1e, 0x0020);
3464         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3465         rtl_writephy(tp, 0x1f, 0x0002);
3466         rtl_writephy(tp, 0x1f, 0x0000);
3467         rtl_writephy(tp, 0x0d, 0x0007);
3468         rtl_writephy(tp, 0x0e, 0x003c);
3469         rtl_writephy(tp, 0x0d, 0x4007);
3470         rtl_writephy(tp, 0x0e, 0x0000);
3471         rtl_writephy(tp, 0x0d, 0x0000);
3472
3473         /* Green feature */
3474         rtl_writephy(tp, 0x1f, 0x0003);
3475         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3476         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3477         rtl_writephy(tp, 0x1f, 0x0000);
3478
3479         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3480         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3481 }
3482
3483 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3484 {
3485         /* For 4-corner performance improve */
3486         rtl_writephy(tp, 0x1f, 0x0005);
3487         rtl_writephy(tp, 0x05, 0x8b80);
3488         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3489         rtl_writephy(tp, 0x1f, 0x0000);
3490
3491         /* PHY auto speed down */
3492         rtl_writephy(tp, 0x1f, 0x0007);
3493         rtl_writephy(tp, 0x1e, 0x002d);
3494         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3495         rtl_writephy(tp, 0x1f, 0x0000);
3496         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3497
3498         /* Improve 10M EEE waveform */
3499         rtl_writephy(tp, 0x1f, 0x0005);
3500         rtl_writephy(tp, 0x05, 0x8b86);
3501         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3502         rtl_writephy(tp, 0x1f, 0x0000);
3503 }
3504
3505 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3506 {
3507         static const struct phy_reg phy_reg_init[] = {
3508                 /* Channel estimation fine tune */
3509                 { 0x1f, 0x0003 },
3510                 { 0x09, 0xa20f },
3511                 { 0x1f, 0x0000 },
3512
3513                 /* Modify green table for giga & fnet */
3514                 { 0x1f, 0x0005 },
3515                 { 0x05, 0x8b55 },
3516                 { 0x06, 0x0000 },
3517                 { 0x05, 0x8b5e },
3518                 { 0x06, 0x0000 },
3519                 { 0x05, 0x8b67 },
3520                 { 0x06, 0x0000 },
3521                 { 0x05, 0x8b70 },
3522                 { 0x06, 0x0000 },
3523                 { 0x1f, 0x0000 },
3524                 { 0x1f, 0x0007 },
3525                 { 0x1e, 0x0078 },
3526                 { 0x17, 0x0000 },
3527                 { 0x19, 0x00fb },
3528                 { 0x1f, 0x0000 },
3529
3530                 /* Modify green table for 10M */
3531                 { 0x1f, 0x0005 },
3532                 { 0x05, 0x8b79 },
3533                 { 0x06, 0xaa00 },
3534                 { 0x1f, 0x0000 },
3535
3536                 /* Disable hiimpedance detection (RTCT) */
3537                 { 0x1f, 0x0003 },
3538                 { 0x01, 0x328a },
3539                 { 0x1f, 0x0000 }
3540         };
3541
3542         rtl_apply_firmware(tp);
3543
3544         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3545
3546         rtl8168f_hw_phy_config(tp);
3547
3548         /* Improve 2-pair detection performance */
3549         rtl_writephy(tp, 0x1f, 0x0005);
3550         rtl_writephy(tp, 0x05, 0x8b85);
3551         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3552         rtl_writephy(tp, 0x1f, 0x0000);
3553 }
3554
3555 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3556 {
3557         rtl_apply_firmware(tp);
3558
3559         rtl8168f_hw_phy_config(tp);
3560 }
3561
3562 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3563 {
3564         static const struct phy_reg phy_reg_init[] = {
3565                 /* Channel estimation fine tune */
3566                 { 0x1f, 0x0003 },
3567                 { 0x09, 0xa20f },
3568                 { 0x1f, 0x0000 },
3569
3570                 /* Modify green table for giga & fnet */
3571                 { 0x1f, 0x0005 },
3572                 { 0x05, 0x8b55 },
3573                 { 0x06, 0x0000 },
3574                 { 0x05, 0x8b5e },
3575                 { 0x06, 0x0000 },
3576                 { 0x05, 0x8b67 },
3577                 { 0x06, 0x0000 },
3578                 { 0x05, 0x8b70 },
3579                 { 0x06, 0x0000 },
3580                 { 0x1f, 0x0000 },
3581                 { 0x1f, 0x0007 },
3582                 { 0x1e, 0x0078 },
3583                 { 0x17, 0x0000 },
3584                 { 0x19, 0x00aa },
3585                 { 0x1f, 0x0000 },
3586
3587                 /* Modify green table for 10M */
3588                 { 0x1f, 0x0005 },
3589                 { 0x05, 0x8b79 },
3590                 { 0x06, 0xaa00 },
3591                 { 0x1f, 0x0000 },
3592
3593                 /* Disable hiimpedance detection (RTCT) */
3594                 { 0x1f, 0x0003 },
3595                 { 0x01, 0x328a },
3596                 { 0x1f, 0x0000 }
3597         };
3598
3599
3600         rtl_apply_firmware(tp);
3601
3602         rtl8168f_hw_phy_config(tp);
3603
3604         /* Improve 2-pair detection performance */
3605         rtl_writephy(tp, 0x1f, 0x0005);
3606         rtl_writephy(tp, 0x05, 0x8b85);
3607         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3608         rtl_writephy(tp, 0x1f, 0x0000);
3609
3610         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3611
3612         /* Modify green table for giga */
3613         rtl_writephy(tp, 0x1f, 0x0005);
3614         rtl_writephy(tp, 0x05, 0x8b54);
3615         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3616         rtl_writephy(tp, 0x05, 0x8b5d);
3617         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3618         rtl_writephy(tp, 0x05, 0x8a7c);
3619         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3620         rtl_writephy(tp, 0x05, 0x8a7f);
3621         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3622         rtl_writephy(tp, 0x05, 0x8a82);
3623         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3624         rtl_writephy(tp, 0x05, 0x8a85);
3625         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3626         rtl_writephy(tp, 0x05, 0x8a88);
3627         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3628         rtl_writephy(tp, 0x1f, 0x0000);
3629
3630         /* uc same-seed solution */
3631         rtl_writephy(tp, 0x1f, 0x0005);
3632         rtl_writephy(tp, 0x05, 0x8b85);
3633         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3634         rtl_writephy(tp, 0x1f, 0x0000);
3635
3636         /* eee setting */
3637         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3638         rtl_writephy(tp, 0x1f, 0x0005);
3639         rtl_writephy(tp, 0x05, 0x8b85);
3640         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3641         rtl_writephy(tp, 0x1f, 0x0004);
3642         rtl_writephy(tp, 0x1f, 0x0007);
3643         rtl_writephy(tp, 0x1e, 0x0020);
3644         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3645         rtl_writephy(tp, 0x1f, 0x0000);
3646         rtl_writephy(tp, 0x0d, 0x0007);
3647         rtl_writephy(tp, 0x0e, 0x003c);
3648         rtl_writephy(tp, 0x0d, 0x4007);
3649         rtl_writephy(tp, 0x0e, 0x0000);
3650         rtl_writephy(tp, 0x0d, 0x0000);
3651
3652         /* Green feature */
3653         rtl_writephy(tp, 0x1f, 0x0003);
3654         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3655         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3656         rtl_writephy(tp, 0x1f, 0x0000);
3657 }
3658
3659 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3660 {
3661         rtl_apply_firmware(tp);
3662
3663         rtl_writephy(tp, 0x1f, 0x0a46);
3664         if (rtl_readphy(tp, 0x10) & 0x0100) {
3665                 rtl_writephy(tp, 0x1f, 0x0bcc);
3666                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3667         } else {
3668                 rtl_writephy(tp, 0x1f, 0x0bcc);
3669                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3670         }
3671
3672         rtl_writephy(tp, 0x1f, 0x0a46);
3673         if (rtl_readphy(tp, 0x13) & 0x0100) {
3674                 rtl_writephy(tp, 0x1f, 0x0c41);
3675                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3676         } else {
3677                 rtl_writephy(tp, 0x1f, 0x0c41);
3678                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3679         }
3680
3681         /* Enable PHY auto speed down */
3682         rtl_writephy(tp, 0x1f, 0x0a44);
3683         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3684
3685         rtl_writephy(tp, 0x1f, 0x0bcc);
3686         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3687         rtl_writephy(tp, 0x1f, 0x0a44);
3688         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3689         rtl_writephy(tp, 0x1f, 0x0a43);
3690         rtl_writephy(tp, 0x13, 0x8084);
3691         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3692         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3693
3694         /* EEE auto-fallback function */
3695         rtl_writephy(tp, 0x1f, 0x0a4b);
3696         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3697
3698         /* Enable UC LPF tune function */
3699         rtl_writephy(tp, 0x1f, 0x0a43);
3700         rtl_writephy(tp, 0x13, 0x8012);
3701         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3702
3703         rtl_writephy(tp, 0x1f, 0x0c42);
3704         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3705
3706         /* Improve SWR Efficiency */
3707         rtl_writephy(tp, 0x1f, 0x0bcd);
3708         rtl_writephy(tp, 0x14, 0x5065);
3709         rtl_writephy(tp, 0x14, 0xd065);
3710         rtl_writephy(tp, 0x1f, 0x0bc8);
3711         rtl_writephy(tp, 0x11, 0x5655);
3712         rtl_writephy(tp, 0x1f, 0x0bcd);
3713         rtl_writephy(tp, 0x14, 0x1065);
3714         rtl_writephy(tp, 0x14, 0x9065);
3715         rtl_writephy(tp, 0x14, 0x1065);
3716
3717         /* Check ALDPS bit, disable it if enabled */
3718         rtl_writephy(tp, 0x1f, 0x0a43);
3719         if (rtl_readphy(tp, 0x10) & 0x0004)
3720                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3721
3722         rtl_writephy(tp, 0x1f, 0x0000);
3723 }
3724
3725 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3726 {
3727         rtl_apply_firmware(tp);
3728 }
3729
3730 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3731 {
3732         u16 dout_tapbin;
3733         u32 data;
3734
3735         rtl_apply_firmware(tp);
3736
3737         /* CHN EST parameters adjust - giga master */
3738         rtl_writephy(tp, 0x1f, 0x0a43);
3739         rtl_writephy(tp, 0x13, 0x809b);
3740         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3741         rtl_writephy(tp, 0x13, 0x80a2);
3742         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3743         rtl_writephy(tp, 0x13, 0x80a4);
3744         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3745         rtl_writephy(tp, 0x13, 0x809c);
3746         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3747         rtl_writephy(tp, 0x1f, 0x0000);
3748
3749         /* CHN EST parameters adjust - giga slave */
3750         rtl_writephy(tp, 0x1f, 0x0a43);
3751         rtl_writephy(tp, 0x13, 0x80ad);
3752         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3753         rtl_writephy(tp, 0x13, 0x80b4);
3754         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3755         rtl_writephy(tp, 0x13, 0x80ac);
3756         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3757         rtl_writephy(tp, 0x1f, 0x0000);
3758
3759         /* CHN EST parameters adjust - fnet */
3760         rtl_writephy(tp, 0x1f, 0x0a43);
3761         rtl_writephy(tp, 0x13, 0x808e);
3762         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3763         rtl_writephy(tp, 0x13, 0x8090);
3764         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3765         rtl_writephy(tp, 0x13, 0x8092);
3766         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3767         rtl_writephy(tp, 0x1f, 0x0000);
3768
3769         /* enable R-tune & PGA-retune function */
3770         dout_tapbin = 0;
3771         rtl_writephy(tp, 0x1f, 0x0a46);
3772         data = rtl_readphy(tp, 0x13);
3773         data &= 3;
3774         data <<= 2;
3775         dout_tapbin |= data;
3776         data = rtl_readphy(tp, 0x12);
3777         data &= 0xc000;
3778         data >>= 14;
3779         dout_tapbin |= data;
3780         dout_tapbin = ~(dout_tapbin^0x08);
3781         dout_tapbin <<= 12;
3782         dout_tapbin &= 0xf000;
3783         rtl_writephy(tp, 0x1f, 0x0a43);
3784         rtl_writephy(tp, 0x13, 0x827a);
3785         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3786         rtl_writephy(tp, 0x13, 0x827b);
3787         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3788         rtl_writephy(tp, 0x13, 0x827c);
3789         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3790         rtl_writephy(tp, 0x13, 0x827d);
3791         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3792
3793         rtl_writephy(tp, 0x1f, 0x0a43);
3794         rtl_writephy(tp, 0x13, 0x0811);
3795         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3796         rtl_writephy(tp, 0x1f, 0x0a42);
3797         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3798         rtl_writephy(tp, 0x1f, 0x0000);
3799
3800         /* enable GPHY 10M */
3801         rtl_writephy(tp, 0x1f, 0x0a44);
3802         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3803         rtl_writephy(tp, 0x1f, 0x0000);
3804
3805         /* SAR ADC performance */
3806         rtl_writephy(tp, 0x1f, 0x0bca);
3807         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3808         rtl_writephy(tp, 0x1f, 0x0000);
3809
3810         rtl_writephy(tp, 0x1f, 0x0a43);
3811         rtl_writephy(tp, 0x13, 0x803f);
3812         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3813         rtl_writephy(tp, 0x13, 0x8047);
3814         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3815         rtl_writephy(tp, 0x13, 0x804f);
3816         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3817         rtl_writephy(tp, 0x13, 0x8057);
3818         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3819         rtl_writephy(tp, 0x13, 0x805f);
3820         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3821         rtl_writephy(tp, 0x13, 0x8067);
3822         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3823         rtl_writephy(tp, 0x13, 0x806f);
3824         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3825         rtl_writephy(tp, 0x1f, 0x0000);
3826
3827         /* disable phy pfm mode */
3828         rtl_writephy(tp, 0x1f, 0x0a44);
3829         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3830         rtl_writephy(tp, 0x1f, 0x0000);
3831
3832         /* Check ALDPS bit, disable it if enabled */
3833         rtl_writephy(tp, 0x1f, 0x0a43);
3834         if (rtl_readphy(tp, 0x10) & 0x0004)
3835                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3836
3837         rtl_writephy(tp, 0x1f, 0x0000);
3838 }
3839
3840 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3841 {
3842         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3843         u16 rlen;
3844         u32 data;
3845
3846         rtl_apply_firmware(tp);
3847
3848         /* CHIN EST parameter update */
3849         rtl_writephy(tp, 0x1f, 0x0a43);
3850         rtl_writephy(tp, 0x13, 0x808a);
3851         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3852         rtl_writephy(tp, 0x1f, 0x0000);
3853
3854         /* enable R-tune & PGA-retune function */
3855         rtl_writephy(tp, 0x1f, 0x0a43);
3856         rtl_writephy(tp, 0x13, 0x0811);
3857         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3858         rtl_writephy(tp, 0x1f, 0x0a42);
3859         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3860         rtl_writephy(tp, 0x1f, 0x0000);
3861
3862         /* enable GPHY 10M */
3863         rtl_writephy(tp, 0x1f, 0x0a44);
3864         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3865         rtl_writephy(tp, 0x1f, 0x0000);
3866
3867         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3868         data = r8168_mac_ocp_read(tp, 0xdd02);
3869         ioffset_p3 = ((data & 0x80)>>7);
3870         ioffset_p3 <<= 3;
3871
3872         data = r8168_mac_ocp_read(tp, 0xdd00);
3873         ioffset_p3 |= ((data & (0xe000))>>13);
3874         ioffset_p2 = ((data & (0x1e00))>>9);
3875         ioffset_p1 = ((data & (0x01e0))>>5);
3876         ioffset_p0 = ((data & 0x0010)>>4);
3877         ioffset_p0 <<= 3;
3878         ioffset_p0 |= (data & (0x07));
3879         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3880
3881         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3882             (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
3883                 rtl_writephy(tp, 0x1f, 0x0bcf);
3884                 rtl_writephy(tp, 0x16, data);
3885                 rtl_writephy(tp, 0x1f, 0x0000);
3886         }
3887
3888         /* Modify rlen (TX LPF corner frequency) level */
3889         rtl_writephy(tp, 0x1f, 0x0bcd);
3890         data = rtl_readphy(tp, 0x16);
3891         data &= 0x000f;
3892         rlen = 0;
3893         if (data > 3)
3894                 rlen = data - 3;
3895         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3896         rtl_writephy(tp, 0x17, data);
3897         rtl_writephy(tp, 0x1f, 0x0bcd);
3898         rtl_writephy(tp, 0x1f, 0x0000);
3899
3900         /* disable phy pfm mode */
3901         rtl_writephy(tp, 0x1f, 0x0a44);
3902         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3903         rtl_writephy(tp, 0x1f, 0x0000);
3904
3905         /* Check ALDPS bit, disable it if enabled */
3906         rtl_writephy(tp, 0x1f, 0x0a43);
3907         if (rtl_readphy(tp, 0x10) & 0x0004)
3908                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3909
3910         rtl_writephy(tp, 0x1f, 0x0000);
3911 }
3912
3913 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3914 {
3915         /* Enable PHY auto speed down */
3916         rtl_writephy(tp, 0x1f, 0x0a44);
3917         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3918         rtl_writephy(tp, 0x1f, 0x0000);
3919
3920         /* patch 10M & ALDPS */
3921         rtl_writephy(tp, 0x1f, 0x0bcc);
3922         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3923         rtl_writephy(tp, 0x1f, 0x0a44);
3924         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3925         rtl_writephy(tp, 0x1f, 0x0a43);
3926         rtl_writephy(tp, 0x13, 0x8084);
3927         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3928         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3929         rtl_writephy(tp, 0x1f, 0x0000);
3930
3931         /* Enable EEE auto-fallback function */
3932         rtl_writephy(tp, 0x1f, 0x0a4b);
3933         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3934         rtl_writephy(tp, 0x1f, 0x0000);
3935
3936         /* Enable UC LPF tune function */
3937         rtl_writephy(tp, 0x1f, 0x0a43);
3938         rtl_writephy(tp, 0x13, 0x8012);
3939         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3940         rtl_writephy(tp, 0x1f, 0x0000);
3941
3942         /* set rg_sel_sdm_rate */
3943         rtl_writephy(tp, 0x1f, 0x0c42);
3944         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3945         rtl_writephy(tp, 0x1f, 0x0000);
3946
3947         /* Check ALDPS bit, disable it if enabled */
3948         rtl_writephy(tp, 0x1f, 0x0a43);
3949         if (rtl_readphy(tp, 0x10) & 0x0004)
3950                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3951
3952         rtl_writephy(tp, 0x1f, 0x0000);
3953 }
3954
3955 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3956 {
3957         /* patch 10M & ALDPS */
3958         rtl_writephy(tp, 0x1f, 0x0bcc);
3959         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3960         rtl_writephy(tp, 0x1f, 0x0a44);
3961         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3962         rtl_writephy(tp, 0x1f, 0x0a43);
3963         rtl_writephy(tp, 0x13, 0x8084);
3964         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3965         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3966         rtl_writephy(tp, 0x1f, 0x0000);
3967
3968         /* Enable UC LPF tune function */
3969         rtl_writephy(tp, 0x1f, 0x0a43);
3970         rtl_writephy(tp, 0x13, 0x8012);
3971         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3972         rtl_writephy(tp, 0x1f, 0x0000);
3973
3974         /* Set rg_sel_sdm_rate */
3975         rtl_writephy(tp, 0x1f, 0x0c42);
3976         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3977         rtl_writephy(tp, 0x1f, 0x0000);
3978
3979         /* Channel estimation parameters */
3980         rtl_writephy(tp, 0x1f, 0x0a43);
3981         rtl_writephy(tp, 0x13, 0x80f3);
3982         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3983         rtl_writephy(tp, 0x13, 0x80f0);
3984         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3985         rtl_writephy(tp, 0x13, 0x80ef);
3986         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3987         rtl_writephy(tp, 0x13, 0x80f6);
3988         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3989         rtl_writephy(tp, 0x13, 0x80ec);
3990         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3991         rtl_writephy(tp, 0x13, 0x80ed);
3992         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3993         rtl_writephy(tp, 0x13, 0x80f2);
3994         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3995         rtl_writephy(tp, 0x13, 0x80f4);
3996         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3997         rtl_writephy(tp, 0x1f, 0x0a43);
3998         rtl_writephy(tp, 0x13, 0x8110);
3999         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4000         rtl_writephy(tp, 0x13, 0x810f);
4001         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4002         rtl_writephy(tp, 0x13, 0x8111);
4003         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4004         rtl_writephy(tp, 0x13, 0x8113);
4005         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4006         rtl_writephy(tp, 0x13, 0x8115);
4007         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4008         rtl_writephy(tp, 0x13, 0x810e);
4009         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4010         rtl_writephy(tp, 0x13, 0x810c);
4011         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4012         rtl_writephy(tp, 0x13, 0x810b);
4013         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4014         rtl_writephy(tp, 0x1f, 0x0a43);
4015         rtl_writephy(tp, 0x13, 0x80d1);
4016         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4017         rtl_writephy(tp, 0x13, 0x80cd);
4018         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4019         rtl_writephy(tp, 0x13, 0x80d3);
4020         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4021         rtl_writephy(tp, 0x13, 0x80d5);
4022         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4023         rtl_writephy(tp, 0x13, 0x80d7);
4024         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4025
4026         /* Force PWM-mode */
4027         rtl_writephy(tp, 0x1f, 0x0bcd);
4028         rtl_writephy(tp, 0x14, 0x5065);
4029         rtl_writephy(tp, 0x14, 0xd065);
4030         rtl_writephy(tp, 0x1f, 0x0bc8);
4031         rtl_writephy(tp, 0x12, 0x00ed);
4032         rtl_writephy(tp, 0x1f, 0x0bcd);
4033         rtl_writephy(tp, 0x14, 0x1065);
4034         rtl_writephy(tp, 0x14, 0x9065);
4035         rtl_writephy(tp, 0x14, 0x1065);
4036         rtl_writephy(tp, 0x1f, 0x0000);
4037
4038         /* Check ALDPS bit, disable it if enabled */
4039         rtl_writephy(tp, 0x1f, 0x0a43);
4040         if (rtl_readphy(tp, 0x10) & 0x0004)
4041                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4042
4043         rtl_writephy(tp, 0x1f, 0x0000);
4044 }
4045
4046 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4047 {
4048         static const struct phy_reg phy_reg_init[] = {
4049                 { 0x1f, 0x0003 },
4050                 { 0x08, 0x441d },
4051                 { 0x01, 0x9100 },
4052                 { 0x1f, 0x0000 }
4053         };
4054
4055         rtl_writephy(tp, 0x1f, 0x0000);
4056         rtl_patchphy(tp, 0x11, 1 << 12);
4057         rtl_patchphy(tp, 0x19, 1 << 13);
4058         rtl_patchphy(tp, 0x10, 1 << 15);
4059
4060         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4061 }
4062
4063 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4064 {
4065         static const struct phy_reg phy_reg_init[] = {
4066                 { 0x1f, 0x0005 },
4067                 { 0x1a, 0x0000 },
4068                 { 0x1f, 0x0000 },
4069
4070                 { 0x1f, 0x0004 },
4071                 { 0x1c, 0x0000 },
4072                 { 0x1f, 0x0000 },
4073
4074                 { 0x1f, 0x0001 },
4075                 { 0x15, 0x7701 },
4076                 { 0x1f, 0x0000 }
4077         };
4078
4079         /* Disable ALDPS before ram code */
4080         rtl_writephy(tp, 0x1f, 0x0000);
4081         rtl_writephy(tp, 0x18, 0x0310);
4082         msleep(100);
4083
4084         rtl_apply_firmware(tp);
4085
4086         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4087 }
4088
4089 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4090 {
4091         /* Disable ALDPS before setting firmware */
4092         rtl_writephy(tp, 0x1f, 0x0000);
4093         rtl_writephy(tp, 0x18, 0x0310);
4094         msleep(20);
4095
4096         rtl_apply_firmware(tp);
4097
4098         /* EEE setting */
4099         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4100         rtl_writephy(tp, 0x1f, 0x0004);
4101         rtl_writephy(tp, 0x10, 0x401f);
4102         rtl_writephy(tp, 0x19, 0x7030);
4103         rtl_writephy(tp, 0x1f, 0x0000);
4104 }
4105
4106 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4107 {
4108         static const struct phy_reg phy_reg_init[] = {
4109                 { 0x1f, 0x0004 },
4110                 { 0x10, 0xc07f },
4111                 { 0x19, 0x7030 },
4112                 { 0x1f, 0x0000 }
4113         };
4114
4115         /* Disable ALDPS before ram code */
4116         rtl_writephy(tp, 0x1f, 0x0000);
4117         rtl_writephy(tp, 0x18, 0x0310);
4118         msleep(100);
4119
4120         rtl_apply_firmware(tp);
4121
4122         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4123         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4124
4125         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4126 }
4127
4128 static void rtl_hw_phy_config(struct net_device *dev)
4129 {
4130         struct rtl8169_private *tp = netdev_priv(dev);
4131
4132         rtl8169_print_mac_version(tp);
4133
4134         switch (tp->mac_version) {
4135         case RTL_GIGA_MAC_VER_01:
4136                 break;
4137         case RTL_GIGA_MAC_VER_02:
4138         case RTL_GIGA_MAC_VER_03:
4139                 rtl8169s_hw_phy_config(tp);
4140                 break;
4141         case RTL_GIGA_MAC_VER_04:
4142                 rtl8169sb_hw_phy_config(tp);
4143                 break;
4144         case RTL_GIGA_MAC_VER_05:
4145                 rtl8169scd_hw_phy_config(tp);
4146                 break;
4147         case RTL_GIGA_MAC_VER_06:
4148                 rtl8169sce_hw_phy_config(tp);
4149                 break;
4150         case RTL_GIGA_MAC_VER_07:
4151         case RTL_GIGA_MAC_VER_08:
4152         case RTL_GIGA_MAC_VER_09:
4153                 rtl8102e_hw_phy_config(tp);
4154                 break;
4155         case RTL_GIGA_MAC_VER_11:
4156                 rtl8168bb_hw_phy_config(tp);
4157                 break;
4158         case RTL_GIGA_MAC_VER_12:
4159                 rtl8168bef_hw_phy_config(tp);
4160                 break;
4161         case RTL_GIGA_MAC_VER_17:
4162                 rtl8168bef_hw_phy_config(tp);
4163                 break;
4164         case RTL_GIGA_MAC_VER_18:
4165                 rtl8168cp_1_hw_phy_config(tp);
4166                 break;
4167         case RTL_GIGA_MAC_VER_19:
4168                 rtl8168c_1_hw_phy_config(tp);
4169                 break;
4170         case RTL_GIGA_MAC_VER_20:
4171                 rtl8168c_2_hw_phy_config(tp);
4172                 break;
4173         case RTL_GIGA_MAC_VER_21:
4174                 rtl8168c_3_hw_phy_config(tp);
4175                 break;
4176         case RTL_GIGA_MAC_VER_22:
4177                 rtl8168c_4_hw_phy_config(tp);
4178                 break;
4179         case RTL_GIGA_MAC_VER_23:
4180         case RTL_GIGA_MAC_VER_24:
4181                 rtl8168cp_2_hw_phy_config(tp);
4182                 break;
4183         case RTL_GIGA_MAC_VER_25:
4184                 rtl8168d_1_hw_phy_config(tp);
4185                 break;
4186         case RTL_GIGA_MAC_VER_26:
4187                 rtl8168d_2_hw_phy_config(tp);
4188                 break;
4189         case RTL_GIGA_MAC_VER_27:
4190                 rtl8168d_3_hw_phy_config(tp);
4191                 break;
4192         case RTL_GIGA_MAC_VER_28:
4193                 rtl8168d_4_hw_phy_config(tp);
4194                 break;
4195         case RTL_GIGA_MAC_VER_29:
4196         case RTL_GIGA_MAC_VER_30:
4197                 rtl8105e_hw_phy_config(tp);
4198                 break;
4199         case RTL_GIGA_MAC_VER_31:
4200                 /* None. */
4201                 break;
4202         case RTL_GIGA_MAC_VER_32:
4203         case RTL_GIGA_MAC_VER_33:
4204                 rtl8168e_1_hw_phy_config(tp);
4205                 break;
4206         case RTL_GIGA_MAC_VER_34:
4207                 rtl8168e_2_hw_phy_config(tp);
4208                 break;
4209         case RTL_GIGA_MAC_VER_35:
4210                 rtl8168f_1_hw_phy_config(tp);
4211                 break;
4212         case RTL_GIGA_MAC_VER_36:
4213                 rtl8168f_2_hw_phy_config(tp);
4214                 break;
4215
4216         case RTL_GIGA_MAC_VER_37:
4217                 rtl8402_hw_phy_config(tp);
4218                 break;
4219
4220         case RTL_GIGA_MAC_VER_38:
4221                 rtl8411_hw_phy_config(tp);
4222                 break;
4223
4224         case RTL_GIGA_MAC_VER_39:
4225                 rtl8106e_hw_phy_config(tp);
4226                 break;
4227
4228         case RTL_GIGA_MAC_VER_40:
4229                 rtl8168g_1_hw_phy_config(tp);
4230                 break;
4231         case RTL_GIGA_MAC_VER_42:
4232         case RTL_GIGA_MAC_VER_43:
4233         case RTL_GIGA_MAC_VER_44:
4234                 rtl8168g_2_hw_phy_config(tp);
4235                 break;
4236         case RTL_GIGA_MAC_VER_45:
4237         case RTL_GIGA_MAC_VER_47:
4238                 rtl8168h_1_hw_phy_config(tp);
4239                 break;
4240         case RTL_GIGA_MAC_VER_46:
4241         case RTL_GIGA_MAC_VER_48:
4242                 rtl8168h_2_hw_phy_config(tp);
4243                 break;
4244
4245         case RTL_GIGA_MAC_VER_49:
4246                 rtl8168ep_1_hw_phy_config(tp);
4247                 break;
4248         case RTL_GIGA_MAC_VER_50:
4249         case RTL_GIGA_MAC_VER_51:
4250                 rtl8168ep_2_hw_phy_config(tp);
4251                 break;
4252
4253         case RTL_GIGA_MAC_VER_41:
4254         default:
4255                 break;
4256         }
4257 }
4258
4259 static void rtl_phy_work(struct rtl8169_private *tp)
4260 {
4261         struct timer_list *timer = &tp->timer;
4262         void __iomem *ioaddr = tp->mmio_addr;
4263         unsigned long timeout = RTL8169_PHY_TIMEOUT;
4264
4265         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4266
4267         if (tp->phy_reset_pending(tp)) {
4268                 /*
4269                  * A busy loop could burn quite a few cycles on nowadays CPU.
4270                  * Let's delay the execution of the timer for a few ticks.
4271                  */
4272                 timeout = HZ/10;
4273                 goto out_mod_timer;
4274         }
4275
4276         if (tp->link_ok(ioaddr))
4277                 return;
4278
4279         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4280
4281         tp->phy_reset_enable(tp);
4282
4283 out_mod_timer:
4284         mod_timer(timer, jiffies + timeout);
4285 }
4286
4287 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4288 {
4289         if (!test_and_set_bit(flag, tp->wk.flags))
4290                 schedule_work(&tp->wk.work);
4291 }
4292
4293 static void rtl8169_phy_timer(unsigned long __opaque)
4294 {
4295         struct net_device *dev = (struct net_device *)__opaque;
4296         struct rtl8169_private *tp = netdev_priv(dev);
4297
4298         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4299 }
4300
4301 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4302                                   void __iomem *ioaddr)
4303 {
4304         iounmap(ioaddr);
4305         pci_release_regions(pdev);
4306         pci_clear_mwi(pdev);
4307         pci_disable_device(pdev);
4308         free_netdev(dev);
4309 }
4310
4311 DECLARE_RTL_COND(rtl_phy_reset_cond)
4312 {
4313         return tp->phy_reset_pending(tp);
4314 }
4315
4316 static void rtl8169_phy_reset(struct net_device *dev,
4317                               struct rtl8169_private *tp)
4318 {
4319         tp->phy_reset_enable(tp);
4320         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4321 }
4322
4323 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4324 {
4325         void __iomem *ioaddr = tp->mmio_addr;
4326
4327         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4328             (RTL_R8(PHYstatus) & TBI_Enable);
4329 }
4330
4331 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4332 {
4333         void __iomem *ioaddr = tp->mmio_addr;
4334
4335         rtl_hw_phy_config(dev);
4336
4337         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4338                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4339                 RTL_W8(0x82, 0x01);
4340         }
4341
4342         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4343
4344         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4345                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4346
4347         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4348                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4349                 RTL_W8(0x82, 0x01);
4350                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4351                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4352         }
4353
4354         rtl8169_phy_reset(dev, tp);
4355
4356         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4357                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4358                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4359                           (tp->mii.supports_gmii ?
4360                            ADVERTISED_1000baseT_Half |
4361                            ADVERTISED_1000baseT_Full : 0));
4362
4363         if (rtl_tbi_enabled(tp))
4364                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4365 }
4366
4367 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4368 {
4369         void __iomem *ioaddr = tp->mmio_addr;
4370
4371         rtl_lock_work(tp);
4372
4373         RTL_W8(Cfg9346, Cfg9346_Unlock);
4374
4375         RTL_W32(MAC4, addr[4] | addr[5] << 8);
4376         RTL_R32(MAC4);
4377
4378         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4379         RTL_R32(MAC0);
4380
4381         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4382                 rtl_rar_exgmac_set(tp, addr);
4383
4384         RTL_W8(Cfg9346, Cfg9346_Lock);
4385
4386         rtl_unlock_work(tp);
4387 }
4388
4389 static int rtl_set_mac_address(struct net_device *dev, void *p)
4390 {
4391         struct rtl8169_private *tp = netdev_priv(dev);
4392         struct sockaddr *addr = p;
4393
4394         if (!is_valid_ether_addr(addr->sa_data))
4395                 return -EADDRNOTAVAIL;
4396
4397         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4398
4399         rtl_rar_set(tp, dev->dev_addr);
4400
4401         return 0;
4402 }
4403
4404 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4405 {
4406         struct rtl8169_private *tp = netdev_priv(dev);
4407         struct mii_ioctl_data *data = if_mii(ifr);
4408
4409         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4410 }
4411
4412 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4413                           struct mii_ioctl_data *data, int cmd)
4414 {
4415         switch (cmd) {
4416         case SIOCGMIIPHY:
4417                 data->phy_id = 32; /* Internal PHY */
4418                 return 0;
4419
4420         case SIOCGMIIREG:
4421                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4422                 return 0;
4423
4424         case SIOCSMIIREG:
4425                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4426                 return 0;
4427         }
4428         return -EOPNOTSUPP;
4429 }
4430
4431 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4432 {
4433         return -EOPNOTSUPP;
4434 }
4435
4436 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4437 {
4438         if (tp->features & RTL_FEATURE_MSI) {
4439                 pci_disable_msi(pdev);
4440                 tp->features &= ~RTL_FEATURE_MSI;
4441         }
4442 }
4443
4444 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4445 {
4446         struct mdio_ops *ops = &tp->mdio_ops;
4447
4448         switch (tp->mac_version) {
4449         case RTL_GIGA_MAC_VER_27:
4450                 ops->write      = r8168dp_1_mdio_write;
4451                 ops->read       = r8168dp_1_mdio_read;
4452                 break;
4453         case RTL_GIGA_MAC_VER_28:
4454         case RTL_GIGA_MAC_VER_31:
4455                 ops->write      = r8168dp_2_mdio_write;
4456                 ops->read       = r8168dp_2_mdio_read;
4457                 break;
4458         case RTL_GIGA_MAC_VER_40:
4459         case RTL_GIGA_MAC_VER_41:
4460         case RTL_GIGA_MAC_VER_42:
4461         case RTL_GIGA_MAC_VER_43:
4462         case RTL_GIGA_MAC_VER_44:
4463         case RTL_GIGA_MAC_VER_45:
4464         case RTL_GIGA_MAC_VER_46:
4465         case RTL_GIGA_MAC_VER_47:
4466         case RTL_GIGA_MAC_VER_48:
4467         case RTL_GIGA_MAC_VER_49:
4468         case RTL_GIGA_MAC_VER_50:
4469         case RTL_GIGA_MAC_VER_51:
4470                 ops->write      = r8168g_mdio_write;
4471                 ops->read       = r8168g_mdio_read;
4472                 break;
4473         default:
4474                 ops->write      = r8169_mdio_write;
4475                 ops->read       = r8169_mdio_read;
4476                 break;
4477         }
4478 }
4479
4480 static void rtl_speed_down(struct rtl8169_private *tp)
4481 {
4482         u32 adv;
4483         int lpa;
4484
4485         rtl_writephy(tp, 0x1f, 0x0000);
4486         lpa = rtl_readphy(tp, MII_LPA);
4487
4488         if (lpa & (LPA_10HALF | LPA_10FULL))
4489                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4490         else if (lpa & (LPA_100HALF | LPA_100FULL))
4491                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4492                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4493         else
4494                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4495                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4496                       (tp->mii.supports_gmii ?
4497                        ADVERTISED_1000baseT_Half |
4498                        ADVERTISED_1000baseT_Full : 0);
4499
4500         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4501                           adv);
4502 }
4503
4504 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4505 {
4506         void __iomem *ioaddr = tp->mmio_addr;
4507
4508         switch (tp->mac_version) {
4509         case RTL_GIGA_MAC_VER_25:
4510         case RTL_GIGA_MAC_VER_26:
4511         case RTL_GIGA_MAC_VER_29:
4512         case RTL_GIGA_MAC_VER_30:
4513         case RTL_GIGA_MAC_VER_32:
4514         case RTL_GIGA_MAC_VER_33:
4515         case RTL_GIGA_MAC_VER_34:
4516         case RTL_GIGA_MAC_VER_37:
4517         case RTL_GIGA_MAC_VER_38:
4518         case RTL_GIGA_MAC_VER_39:
4519         case RTL_GIGA_MAC_VER_40:
4520         case RTL_GIGA_MAC_VER_41:
4521         case RTL_GIGA_MAC_VER_42:
4522         case RTL_GIGA_MAC_VER_43:
4523         case RTL_GIGA_MAC_VER_44:
4524         case RTL_GIGA_MAC_VER_45:
4525         case RTL_GIGA_MAC_VER_46:
4526         case RTL_GIGA_MAC_VER_47:
4527         case RTL_GIGA_MAC_VER_48:
4528         case RTL_GIGA_MAC_VER_49:
4529         case RTL_GIGA_MAC_VER_50:
4530         case RTL_GIGA_MAC_VER_51:
4531                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4532                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4533                 break;
4534         default:
4535                 break;
4536         }
4537 }
4538
4539 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4540 {
4541         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4542                 return false;
4543
4544         rtl_speed_down(tp);
4545         rtl_wol_suspend_quirk(tp);
4546
4547         return true;
4548 }
4549
4550 static void r810x_phy_power_down(struct rtl8169_private *tp)
4551 {
4552         rtl_writephy(tp, 0x1f, 0x0000);
4553         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4554 }
4555
4556 static void r810x_phy_power_up(struct rtl8169_private *tp)
4557 {
4558         rtl_writephy(tp, 0x1f, 0x0000);
4559         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4560 }
4561
4562 static void r810x_pll_power_down(struct rtl8169_private *tp)
4563 {
4564         void __iomem *ioaddr = tp->mmio_addr;
4565
4566         if (rtl_wol_pll_power_down(tp))
4567                 return;
4568
4569         r810x_phy_power_down(tp);
4570
4571         switch (tp->mac_version) {
4572         case RTL_GIGA_MAC_VER_07:
4573         case RTL_GIGA_MAC_VER_08:
4574         case RTL_GIGA_MAC_VER_09:
4575         case RTL_GIGA_MAC_VER_10:
4576         case RTL_GIGA_MAC_VER_13:
4577         case RTL_GIGA_MAC_VER_16:
4578                 break;
4579         default:
4580                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4581                 break;
4582         }
4583 }
4584
4585 static void r810x_pll_power_up(struct rtl8169_private *tp)
4586 {
4587         void __iomem *ioaddr = tp->mmio_addr;
4588
4589         r810x_phy_power_up(tp);
4590
4591         switch (tp->mac_version) {
4592         case RTL_GIGA_MAC_VER_07:
4593         case RTL_GIGA_MAC_VER_08:
4594         case RTL_GIGA_MAC_VER_09:
4595         case RTL_GIGA_MAC_VER_10:
4596         case RTL_GIGA_MAC_VER_13:
4597         case RTL_GIGA_MAC_VER_16:
4598                 break;
4599         case RTL_GIGA_MAC_VER_47:
4600         case RTL_GIGA_MAC_VER_48:
4601                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4602                 break;
4603         default:
4604                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4605                 break;
4606         }
4607 }
4608
4609 static void r8168_phy_power_up(struct rtl8169_private *tp)
4610 {
4611         rtl_writephy(tp, 0x1f, 0x0000);
4612         switch (tp->mac_version) {
4613         case RTL_GIGA_MAC_VER_11:
4614         case RTL_GIGA_MAC_VER_12:
4615         case RTL_GIGA_MAC_VER_17:
4616         case RTL_GIGA_MAC_VER_18:
4617         case RTL_GIGA_MAC_VER_19:
4618         case RTL_GIGA_MAC_VER_20:
4619         case RTL_GIGA_MAC_VER_21:
4620         case RTL_GIGA_MAC_VER_22:
4621         case RTL_GIGA_MAC_VER_23:
4622         case RTL_GIGA_MAC_VER_24:
4623         case RTL_GIGA_MAC_VER_25:
4624         case RTL_GIGA_MAC_VER_26:
4625         case RTL_GIGA_MAC_VER_27:
4626         case RTL_GIGA_MAC_VER_28:
4627         case RTL_GIGA_MAC_VER_31:
4628                 rtl_writephy(tp, 0x0e, 0x0000);
4629                 break;
4630         default:
4631                 break;
4632         }
4633         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4634 }
4635
4636 static void r8168_phy_power_down(struct rtl8169_private *tp)
4637 {
4638         rtl_writephy(tp, 0x1f, 0x0000);
4639         switch (tp->mac_version) {
4640         case RTL_GIGA_MAC_VER_32:
4641         case RTL_GIGA_MAC_VER_33:
4642         case RTL_GIGA_MAC_VER_40:
4643         case RTL_GIGA_MAC_VER_41:
4644                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4645                 break;
4646
4647         case RTL_GIGA_MAC_VER_11:
4648         case RTL_GIGA_MAC_VER_12:
4649         case RTL_GIGA_MAC_VER_17:
4650         case RTL_GIGA_MAC_VER_18:
4651         case RTL_GIGA_MAC_VER_19:
4652         case RTL_GIGA_MAC_VER_20:
4653         case RTL_GIGA_MAC_VER_21:
4654         case RTL_GIGA_MAC_VER_22:
4655         case RTL_GIGA_MAC_VER_23:
4656         case RTL_GIGA_MAC_VER_24:
4657         case RTL_GIGA_MAC_VER_25:
4658         case RTL_GIGA_MAC_VER_26:
4659         case RTL_GIGA_MAC_VER_27:
4660         case RTL_GIGA_MAC_VER_28:
4661         case RTL_GIGA_MAC_VER_31:
4662                 rtl_writephy(tp, 0x0e, 0x0200);
4663         default:
4664                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4665                 break;
4666         }
4667 }
4668
4669 static void r8168_pll_power_down(struct rtl8169_private *tp)
4670 {
4671         void __iomem *ioaddr = tp->mmio_addr;
4672
4673         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4674              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4675              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4676              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4677              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4678              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4679             r8168_check_dash(tp)) {
4680                 return;
4681         }
4682
4683         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4684              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4685             (RTL_R16(CPlusCmd) & ASF)) {
4686                 return;
4687         }
4688
4689         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4690             tp->mac_version == RTL_GIGA_MAC_VER_33)
4691                 rtl_ephy_write(tp, 0x19, 0xff64);
4692
4693         if (rtl_wol_pll_power_down(tp))
4694                 return;
4695
4696         r8168_phy_power_down(tp);
4697
4698         switch (tp->mac_version) {
4699         case RTL_GIGA_MAC_VER_25:
4700         case RTL_GIGA_MAC_VER_26:
4701         case RTL_GIGA_MAC_VER_27:
4702         case RTL_GIGA_MAC_VER_28:
4703         case RTL_GIGA_MAC_VER_31:
4704         case RTL_GIGA_MAC_VER_32:
4705         case RTL_GIGA_MAC_VER_33:
4706         case RTL_GIGA_MAC_VER_44:
4707         case RTL_GIGA_MAC_VER_45:
4708         case RTL_GIGA_MAC_VER_46:
4709         case RTL_GIGA_MAC_VER_50:
4710         case RTL_GIGA_MAC_VER_51:
4711                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4712                 break;
4713         case RTL_GIGA_MAC_VER_40:
4714         case RTL_GIGA_MAC_VER_41:
4715         case RTL_GIGA_MAC_VER_49:
4716                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4717                              0xfc000000, ERIAR_EXGMAC);
4718                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4719                 break;
4720         }
4721 }
4722
4723 static void r8168_pll_power_up(struct rtl8169_private *tp)
4724 {
4725         void __iomem *ioaddr = tp->mmio_addr;
4726
4727         switch (tp->mac_version) {
4728         case RTL_GIGA_MAC_VER_25:
4729         case RTL_GIGA_MAC_VER_26:
4730         case RTL_GIGA_MAC_VER_27:
4731         case RTL_GIGA_MAC_VER_28:
4732         case RTL_GIGA_MAC_VER_31:
4733         case RTL_GIGA_MAC_VER_32:
4734         case RTL_GIGA_MAC_VER_33:
4735                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4736                 break;
4737         case RTL_GIGA_MAC_VER_44:
4738         case RTL_GIGA_MAC_VER_45:
4739         case RTL_GIGA_MAC_VER_46:
4740         case RTL_GIGA_MAC_VER_50:
4741         case RTL_GIGA_MAC_VER_51:
4742                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4743                 break;
4744         case RTL_GIGA_MAC_VER_40:
4745         case RTL_GIGA_MAC_VER_41:
4746         case RTL_GIGA_MAC_VER_49:
4747                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4748                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4749                              0x00000000, ERIAR_EXGMAC);
4750                 break;
4751         }
4752
4753         r8168_phy_power_up(tp);
4754 }
4755
4756 static void rtl_generic_op(struct rtl8169_private *tp,
4757                            void (*op)(struct rtl8169_private *))
4758 {
4759         if (op)
4760                 op(tp);
4761 }
4762
4763 static void rtl_pll_power_down(struct rtl8169_private *tp)
4764 {
4765         rtl_generic_op(tp, tp->pll_power_ops.down);
4766 }
4767
4768 static void rtl_pll_power_up(struct rtl8169_private *tp)
4769 {
4770         rtl_generic_op(tp, tp->pll_power_ops.up);
4771 }
4772
4773 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4774 {
4775         struct pll_power_ops *ops = &tp->pll_power_ops;
4776
4777         switch (tp->mac_version) {
4778         case RTL_GIGA_MAC_VER_07:
4779         case RTL_GIGA_MAC_VER_08:
4780         case RTL_GIGA_MAC_VER_09:
4781         case RTL_GIGA_MAC_VER_10:
4782         case RTL_GIGA_MAC_VER_16:
4783         case RTL_GIGA_MAC_VER_29:
4784         case RTL_GIGA_MAC_VER_30:
4785         case RTL_GIGA_MAC_VER_37:
4786         case RTL_GIGA_MAC_VER_39:
4787         case RTL_GIGA_MAC_VER_43:
4788         case RTL_GIGA_MAC_VER_47:
4789         case RTL_GIGA_MAC_VER_48:
4790                 ops->down       = r810x_pll_power_down;
4791                 ops->up         = r810x_pll_power_up;
4792                 break;
4793
4794         case RTL_GIGA_MAC_VER_11:
4795         case RTL_GIGA_MAC_VER_12:
4796         case RTL_GIGA_MAC_VER_17:
4797         case RTL_GIGA_MAC_VER_18:
4798         case RTL_GIGA_MAC_VER_19:
4799         case RTL_GIGA_MAC_VER_20:
4800         case RTL_GIGA_MAC_VER_21:
4801         case RTL_GIGA_MAC_VER_22:
4802         case RTL_GIGA_MAC_VER_23:
4803         case RTL_GIGA_MAC_VER_24:
4804         case RTL_GIGA_MAC_VER_25:
4805         case RTL_GIGA_MAC_VER_26:
4806         case RTL_GIGA_MAC_VER_27:
4807         case RTL_GIGA_MAC_VER_28:
4808         case RTL_GIGA_MAC_VER_31:
4809         case RTL_GIGA_MAC_VER_32:
4810         case RTL_GIGA_MAC_VER_33:
4811         case RTL_GIGA_MAC_VER_34:
4812         case RTL_GIGA_MAC_VER_35:
4813         case RTL_GIGA_MAC_VER_36:
4814         case RTL_GIGA_MAC_VER_38:
4815         case RTL_GIGA_MAC_VER_40:
4816         case RTL_GIGA_MAC_VER_41:
4817         case RTL_GIGA_MAC_VER_42:
4818         case RTL_GIGA_MAC_VER_44:
4819         case RTL_GIGA_MAC_VER_45:
4820         case RTL_GIGA_MAC_VER_46:
4821         case RTL_GIGA_MAC_VER_49:
4822         case RTL_GIGA_MAC_VER_50:
4823         case RTL_GIGA_MAC_VER_51:
4824                 ops->down       = r8168_pll_power_down;
4825                 ops->up         = r8168_pll_power_up;
4826                 break;
4827
4828         default:
4829                 ops->down       = NULL;
4830                 ops->up         = NULL;
4831                 break;
4832         }
4833 }
4834
4835 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4836 {
4837         void __iomem *ioaddr = tp->mmio_addr;
4838
4839         switch (tp->mac_version) {
4840         case RTL_GIGA_MAC_VER_01:
4841         case RTL_GIGA_MAC_VER_02:
4842         case RTL_GIGA_MAC_VER_03:
4843         case RTL_GIGA_MAC_VER_04:
4844         case RTL_GIGA_MAC_VER_05:
4845         case RTL_GIGA_MAC_VER_06:
4846         case RTL_GIGA_MAC_VER_10:
4847         case RTL_GIGA_MAC_VER_11:
4848         case RTL_GIGA_MAC_VER_12:
4849         case RTL_GIGA_MAC_VER_13:
4850         case RTL_GIGA_MAC_VER_14:
4851         case RTL_GIGA_MAC_VER_15:
4852         case RTL_GIGA_MAC_VER_16:
4853         case RTL_GIGA_MAC_VER_17:
4854                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4855                 break;
4856         case RTL_GIGA_MAC_VER_18:
4857         case RTL_GIGA_MAC_VER_19:
4858         case RTL_GIGA_MAC_VER_20:
4859         case RTL_GIGA_MAC_VER_21:
4860         case RTL_GIGA_MAC_VER_22:
4861         case RTL_GIGA_MAC_VER_23:
4862         case RTL_GIGA_MAC_VER_24:
4863         case RTL_GIGA_MAC_VER_34:
4864         case RTL_GIGA_MAC_VER_35:
4865                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4866                 break;
4867         case RTL_GIGA_MAC_VER_40:
4868                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4869                 break;
4870         case RTL_GIGA_MAC_VER_41:
4871         case RTL_GIGA_MAC_VER_42:
4872         case RTL_GIGA_MAC_VER_43:
4873         case RTL_GIGA_MAC_VER_44:
4874         case RTL_GIGA_MAC_VER_45:
4875         case RTL_GIGA_MAC_VER_46:
4876         case RTL_GIGA_MAC_VER_47:
4877         case RTL_GIGA_MAC_VER_48:
4878         case RTL_GIGA_MAC_VER_49:
4879         case RTL_GIGA_MAC_VER_50:
4880         case RTL_GIGA_MAC_VER_51:
4881                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4882                 break;
4883         default:
4884                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4885                 break;
4886         }
4887 }
4888
4889 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4890 {
4891         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4892 }
4893
4894 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4895 {
4896         void __iomem *ioaddr = tp->mmio_addr;
4897
4898         RTL_W8(Cfg9346, Cfg9346_Unlock);
4899         rtl_generic_op(tp, tp->jumbo_ops.enable);
4900         RTL_W8(Cfg9346, Cfg9346_Lock);
4901 }
4902
4903 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4904 {
4905         void __iomem *ioaddr = tp->mmio_addr;
4906
4907         RTL_W8(Cfg9346, Cfg9346_Unlock);
4908         rtl_generic_op(tp, tp->jumbo_ops.disable);
4909         RTL_W8(Cfg9346, Cfg9346_Lock);
4910 }
4911
4912 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4913 {
4914         void __iomem *ioaddr = tp->mmio_addr;
4915
4916         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4917         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4918         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
4919 }
4920
4921 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4922 {
4923         void __iomem *ioaddr = tp->mmio_addr;
4924
4925         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4926         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4927         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4928 }
4929
4930 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4931 {
4932         void __iomem *ioaddr = tp->mmio_addr;
4933
4934         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4935 }
4936
4937 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4938 {
4939         void __iomem *ioaddr = tp->mmio_addr;
4940
4941         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4942 }
4943
4944 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4945 {
4946         void __iomem *ioaddr = tp->mmio_addr;
4947
4948         RTL_W8(MaxTxPacketSize, 0x3f);
4949         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4950         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4951         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
4952 }
4953
4954 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4955 {
4956         void __iomem *ioaddr = tp->mmio_addr;
4957
4958         RTL_W8(MaxTxPacketSize, 0x0c);
4959         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4960         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4961         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4962 }
4963
4964 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4965 {
4966         rtl_tx_performance_tweak(tp->pci_dev,
4967                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4968 }
4969
4970 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4971 {
4972         rtl_tx_performance_tweak(tp->pci_dev,
4973                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4974 }
4975
4976 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4977 {
4978         void __iomem *ioaddr = tp->mmio_addr;
4979
4980         r8168b_0_hw_jumbo_enable(tp);
4981
4982         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4983 }
4984
4985 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4986 {
4987         void __iomem *ioaddr = tp->mmio_addr;
4988
4989         r8168b_0_hw_jumbo_disable(tp);
4990
4991         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4992 }
4993
4994 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4995 {
4996         struct jumbo_ops *ops = &tp->jumbo_ops;
4997
4998         switch (tp->mac_version) {
4999         case RTL_GIGA_MAC_VER_11:
5000                 ops->disable    = r8168b_0_hw_jumbo_disable;
5001                 ops->enable     = r8168b_0_hw_jumbo_enable;
5002                 break;
5003         case RTL_GIGA_MAC_VER_12:
5004         case RTL_GIGA_MAC_VER_17:
5005                 ops->disable    = r8168b_1_hw_jumbo_disable;
5006                 ops->enable     = r8168b_1_hw_jumbo_enable;
5007                 break;
5008         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5009         case RTL_GIGA_MAC_VER_19:
5010         case RTL_GIGA_MAC_VER_20:
5011         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5012         case RTL_GIGA_MAC_VER_22:
5013         case RTL_GIGA_MAC_VER_23:
5014         case RTL_GIGA_MAC_VER_24:
5015         case RTL_GIGA_MAC_VER_25:
5016         case RTL_GIGA_MAC_VER_26:
5017                 ops->disable    = r8168c_hw_jumbo_disable;
5018                 ops->enable     = r8168c_hw_jumbo_enable;
5019                 break;
5020         case RTL_GIGA_MAC_VER_27:
5021         case RTL_GIGA_MAC_VER_28:
5022                 ops->disable    = r8168dp_hw_jumbo_disable;
5023                 ops->enable     = r8168dp_hw_jumbo_enable;
5024                 break;
5025         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5026         case RTL_GIGA_MAC_VER_32:
5027         case RTL_GIGA_MAC_VER_33:
5028         case RTL_GIGA_MAC_VER_34:
5029                 ops->disable    = r8168e_hw_jumbo_disable;
5030                 ops->enable     = r8168e_hw_jumbo_enable;
5031                 break;
5032
5033         /*
5034          * No action needed for jumbo frames with 8169.
5035          * No jumbo for 810x at all.
5036          */
5037         case RTL_GIGA_MAC_VER_40:
5038         case RTL_GIGA_MAC_VER_41:
5039         case RTL_GIGA_MAC_VER_42:
5040         case RTL_GIGA_MAC_VER_43:
5041         case RTL_GIGA_MAC_VER_44:
5042         case RTL_GIGA_MAC_VER_45:
5043         case RTL_GIGA_MAC_VER_46:
5044         case RTL_GIGA_MAC_VER_47:
5045         case RTL_GIGA_MAC_VER_48:
5046         case RTL_GIGA_MAC_VER_49:
5047         case RTL_GIGA_MAC_VER_50:
5048         case RTL_GIGA_MAC_VER_51:
5049         default:
5050                 ops->disable    = NULL;
5051                 ops->enable     = NULL;
5052                 break;
5053         }
5054 }
5055
5056 DECLARE_RTL_COND(rtl_chipcmd_cond)
5057 {
5058         void __iomem *ioaddr = tp->mmio_addr;
5059
5060         return RTL_R8(ChipCmd) & CmdReset;
5061 }
5062
5063 static void rtl_hw_reset(struct rtl8169_private *tp)
5064 {
5065         void __iomem *ioaddr = tp->mmio_addr;
5066
5067         RTL_W8(ChipCmd, CmdReset);
5068
5069         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5070 }
5071
5072 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5073 {
5074         struct rtl_fw *rtl_fw;
5075         const char *name;
5076         int rc = -ENOMEM;
5077
5078         name = rtl_lookup_firmware_name(tp);
5079         if (!name)
5080                 goto out_no_firmware;
5081
5082         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5083         if (!rtl_fw)
5084                 goto err_warn;
5085
5086         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5087         if (rc < 0)
5088                 goto err_free;
5089
5090         rc = rtl_check_firmware(tp, rtl_fw);
5091         if (rc < 0)
5092                 goto err_release_firmware;
5093
5094         tp->rtl_fw = rtl_fw;
5095 out:
5096         return;
5097
5098 err_release_firmware:
5099         release_firmware(rtl_fw->fw);
5100 err_free:
5101         kfree(rtl_fw);
5102 err_warn:
5103         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5104                    name, rc);
5105 out_no_firmware:
5106         tp->rtl_fw = NULL;
5107         goto out;
5108 }
5109
5110 static void rtl_request_firmware(struct rtl8169_private *tp)
5111 {
5112         if (IS_ERR(tp->rtl_fw))
5113                 rtl_request_uncached_firmware(tp);
5114 }
5115
5116 static void rtl_rx_close(struct rtl8169_private *tp)
5117 {
5118         void __iomem *ioaddr = tp->mmio_addr;
5119
5120         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5121 }
5122
5123 DECLARE_RTL_COND(rtl_npq_cond)
5124 {
5125         void __iomem *ioaddr = tp->mmio_addr;
5126
5127         return RTL_R8(TxPoll) & NPQ;
5128 }
5129
5130 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5131 {
5132         void __iomem *ioaddr = tp->mmio_addr;
5133
5134         return RTL_R32(TxConfig) & TXCFG_EMPTY;
5135 }
5136
5137 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5138 {
5139         void __iomem *ioaddr = tp->mmio_addr;
5140
5141         /* Disable interrupts */
5142         rtl8169_irq_mask_and_ack(tp);
5143
5144         rtl_rx_close(tp);
5145
5146         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5147             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5148             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5149                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5150         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5151                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5152                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5153                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5154                    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5155                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5156                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5157                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5158                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5159                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5160                    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5161                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5162                    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5163                    tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5164                    tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5165                    tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5166                    tp->mac_version == RTL_GIGA_MAC_VER_51) {
5167                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5168                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5169         } else {
5170                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5171                 udelay(100);
5172         }
5173
5174         rtl_hw_reset(tp);
5175 }
5176
5177 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5178 {
5179         void __iomem *ioaddr = tp->mmio_addr;
5180
5181         /* Set DMA burst size and Interframe Gap Time */
5182         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5183                 (InterFrameGap << TxInterFrameGapShift));
5184 }
5185
5186 static void rtl_hw_start(struct net_device *dev)
5187 {
5188         struct rtl8169_private *tp = netdev_priv(dev);
5189
5190         tp->hw_start(dev);
5191
5192         rtl_irq_enable_all(tp);
5193 }
5194
5195 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5196                                          void __iomem *ioaddr)
5197 {
5198         /*
5199          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5200          * register to be written before TxDescAddrLow to work.
5201          * Switching from MMIO to I/O access fixes the issue as well.
5202          */
5203         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5204         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5205         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5206         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5207 }
5208
5209 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5210 {
5211         u16 cmd;
5212
5213         cmd = RTL_R16(CPlusCmd);
5214         RTL_W16(CPlusCmd, cmd);
5215         return cmd;
5216 }
5217
5218 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5219 {
5220         /* Low hurts. Let's disable the filtering. */
5221         RTL_W16(RxMaxSize, rx_buf_sz + 1);
5222 }
5223
5224 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5225 {
5226         static const struct rtl_cfg2_info {
5227                 u32 mac_version;
5228                 u32 clk;
5229                 u32 val;
5230         } cfg2_info [] = {
5231                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5232                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5233                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5234                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5235         };
5236         const struct rtl_cfg2_info *p = cfg2_info;
5237         unsigned int i;
5238         u32 clk;
5239
5240         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5241         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5242                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5243                         RTL_W32(0x7c, p->val);
5244                         break;
5245                 }
5246         }
5247 }
5248
5249 static void rtl_set_rx_mode(struct net_device *dev)
5250 {
5251         struct rtl8169_private *tp = netdev_priv(dev);
5252         void __iomem *ioaddr = tp->mmio_addr;
5253         u32 mc_filter[2];       /* Multicast hash filter */
5254         int rx_mode;
5255         u32 tmp = 0;
5256
5257         if (dev->flags & IFF_PROMISC) {
5258                 /* Unconditionally log net taps. */
5259                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5260                 rx_mode =
5261                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5262                     AcceptAllPhys;
5263                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5264         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5265                    (dev->flags & IFF_ALLMULTI)) {
5266                 /* Too many to filter perfectly -- accept all multicasts. */
5267                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5268                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5269         } else {
5270                 struct netdev_hw_addr *ha;
5271
5272                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5273                 mc_filter[1] = mc_filter[0] = 0;
5274                 netdev_for_each_mc_addr(ha, dev) {
5275                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5276                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5277                         rx_mode |= AcceptMulticast;
5278                 }
5279         }
5280
5281         if (dev->features & NETIF_F_RXALL)
5282                 rx_mode |= (AcceptErr | AcceptRunt);
5283
5284         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5285
5286         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5287                 u32 data = mc_filter[0];
5288
5289                 mc_filter[0] = swab32(mc_filter[1]);
5290                 mc_filter[1] = swab32(data);
5291         }
5292
5293         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5294                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5295
5296         RTL_W32(MAR0 + 4, mc_filter[1]);
5297         RTL_W32(MAR0 + 0, mc_filter[0]);
5298
5299         RTL_W32(RxConfig, tmp);
5300 }
5301
5302 static void rtl_hw_start_8169(struct net_device *dev)
5303 {
5304         struct rtl8169_private *tp = netdev_priv(dev);
5305         void __iomem *ioaddr = tp->mmio_addr;
5306         struct pci_dev *pdev = tp->pci_dev;
5307
5308         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5309                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5310                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5311         }
5312
5313         RTL_W8(Cfg9346, Cfg9346_Unlock);
5314         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5315             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5316             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5317             tp->mac_version == RTL_GIGA_MAC_VER_04)
5318                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5319
5320         rtl_init_rxcfg(tp);
5321
5322         RTL_W8(EarlyTxThres, NoEarlyTx);
5323
5324         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5325
5326         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5327             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5328             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5329             tp->mac_version == RTL_GIGA_MAC_VER_04)
5330                 rtl_set_rx_tx_config_registers(tp);
5331
5332         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5333
5334         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5335             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5336                 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5337                         "Bit-3 and bit-14 MUST be 1\n");
5338                 tp->cp_cmd |= (1 << 14);
5339         }
5340
5341         RTL_W16(CPlusCmd, tp->cp_cmd);
5342
5343         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5344
5345         /*
5346          * Undocumented corner. Supposedly:
5347          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5348          */
5349         RTL_W16(IntrMitigate, 0x0000);
5350
5351         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5352
5353         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5354             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5355             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5356             tp->mac_version != RTL_GIGA_MAC_VER_04) {
5357                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5358                 rtl_set_rx_tx_config_registers(tp);
5359         }
5360
5361         RTL_W8(Cfg9346, Cfg9346_Lock);
5362
5363         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5364         RTL_R8(IntrMask);
5365
5366         RTL_W32(RxMissed, 0);
5367
5368         rtl_set_rx_mode(dev);
5369
5370         /* no early-rx interrupts */
5371         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5372 }
5373
5374 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5375 {
5376         if (tp->csi_ops.write)
5377                 tp->csi_ops.write(tp, addr, value);
5378 }
5379
5380 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5381 {
5382         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5383 }
5384
5385 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5386 {
5387         u32 csi;
5388
5389         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5390         rtl_csi_write(tp, 0x070c, csi | bits);
5391 }
5392
5393 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5394 {
5395         rtl_csi_access_enable(tp, 0x17000000);
5396 }
5397
5398 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5399 {
5400         rtl_csi_access_enable(tp, 0x27000000);
5401 }
5402
5403 DECLARE_RTL_COND(rtl_csiar_cond)
5404 {
5405         void __iomem *ioaddr = tp->mmio_addr;
5406
5407         return RTL_R32(CSIAR) & CSIAR_FLAG;
5408 }
5409
5410 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5411 {
5412         void __iomem *ioaddr = tp->mmio_addr;
5413
5414         RTL_W32(CSIDR, value);
5415         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5416                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5417
5418         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5419 }
5420
5421 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5422 {
5423         void __iomem *ioaddr = tp->mmio_addr;
5424
5425         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5426                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5427
5428         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5429                 RTL_R32(CSIDR) : ~0;
5430 }
5431
5432 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5433 {
5434         void __iomem *ioaddr = tp->mmio_addr;
5435
5436         RTL_W32(CSIDR, value);
5437         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5438                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5439                 CSIAR_FUNC_NIC);
5440
5441         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5442 }
5443
5444 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5445 {
5446         void __iomem *ioaddr = tp->mmio_addr;
5447
5448         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5449                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5450
5451         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5452                 RTL_R32(CSIDR) : ~0;
5453 }
5454
5455 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5456 {
5457         void __iomem *ioaddr = tp->mmio_addr;
5458
5459         RTL_W32(CSIDR, value);
5460         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5461                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5462                 CSIAR_FUNC_NIC2);
5463
5464         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5465 }
5466
5467 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5468 {
5469         void __iomem *ioaddr = tp->mmio_addr;
5470
5471         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5472                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5473
5474         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5475                 RTL_R32(CSIDR) : ~0;
5476 }
5477
5478 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5479 {
5480         struct csi_ops *ops = &tp->csi_ops;
5481
5482         switch (tp->mac_version) {
5483         case RTL_GIGA_MAC_VER_01:
5484         case RTL_GIGA_MAC_VER_02:
5485         case RTL_GIGA_MAC_VER_03:
5486         case RTL_GIGA_MAC_VER_04:
5487         case RTL_GIGA_MAC_VER_05:
5488         case RTL_GIGA_MAC_VER_06:
5489         case RTL_GIGA_MAC_VER_10:
5490         case RTL_GIGA_MAC_VER_11:
5491         case RTL_GIGA_MAC_VER_12:
5492         case RTL_GIGA_MAC_VER_13:
5493         case RTL_GIGA_MAC_VER_14:
5494         case RTL_GIGA_MAC_VER_15:
5495         case RTL_GIGA_MAC_VER_16:
5496         case RTL_GIGA_MAC_VER_17:
5497                 ops->write      = NULL;
5498                 ops->read       = NULL;
5499                 break;
5500
5501         case RTL_GIGA_MAC_VER_37:
5502         case RTL_GIGA_MAC_VER_38:
5503                 ops->write      = r8402_csi_write;
5504                 ops->read       = r8402_csi_read;
5505                 break;
5506
5507         case RTL_GIGA_MAC_VER_44:
5508                 ops->write      = r8411_csi_write;
5509                 ops->read       = r8411_csi_read;
5510                 break;
5511
5512         default:
5513                 ops->write      = r8169_csi_write;
5514                 ops->read       = r8169_csi_read;
5515                 break;
5516         }
5517 }
5518
5519 struct ephy_info {
5520         unsigned int offset;
5521         u16 mask;
5522         u16 bits;
5523 };
5524
5525 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5526                           int len)
5527 {
5528         u16 w;
5529
5530         while (len-- > 0) {
5531                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5532                 rtl_ephy_write(tp, e->offset, w);
5533                 e++;
5534         }
5535 }
5536
5537 static void rtl_disable_clock_request(struct pci_dev *pdev)
5538 {
5539         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5540                                    PCI_EXP_LNKCTL_CLKREQ_EN);
5541 }
5542
5543 static void rtl_enable_clock_request(struct pci_dev *pdev)
5544 {
5545         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5546                                  PCI_EXP_LNKCTL_CLKREQ_EN);
5547 }
5548
5549 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5550 {
5551         void __iomem *ioaddr = tp->mmio_addr;
5552         u8 data;
5553
5554         data = RTL_R8(Config3);
5555
5556         if (enable)
5557                 data |= Rdy_to_L23;
5558         else
5559                 data &= ~Rdy_to_L23;
5560
5561         RTL_W8(Config3, data);
5562 }
5563
5564 #define R8168_CPCMD_QUIRK_MASK (\
5565         EnableBist | \
5566         Mac_dbgo_oe | \
5567         Force_half_dup | \
5568         Force_rxflow_en | \
5569         Force_txflow_en | \
5570         Cxpl_dbg_sel | \
5571         ASF | \
5572         PktCntrDisable | \
5573         Mac_dbgo_sel)
5574
5575 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5576 {
5577         void __iomem *ioaddr = tp->mmio_addr;
5578         struct pci_dev *pdev = tp->pci_dev;
5579
5580         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5581
5582         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5583
5584         if (tp->dev->mtu <= ETH_DATA_LEN) {
5585                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5586                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5587         }
5588 }
5589
5590 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5591 {
5592         void __iomem *ioaddr = tp->mmio_addr;
5593
5594         rtl_hw_start_8168bb(tp);
5595
5596         RTL_W8(MaxTxPacketSize, TxPacketMax);
5597
5598         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5599 }
5600
5601 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5602 {
5603         void __iomem *ioaddr = tp->mmio_addr;
5604         struct pci_dev *pdev = tp->pci_dev;
5605
5606         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5607
5608         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5609
5610         if (tp->dev->mtu <= ETH_DATA_LEN)
5611                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5612
5613         rtl_disable_clock_request(pdev);
5614
5615         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5616 }
5617
5618 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5619 {
5620         static const struct ephy_info e_info_8168cp[] = {
5621                 { 0x01, 0,      0x0001 },
5622                 { 0x02, 0x0800, 0x1000 },
5623                 { 0x03, 0,      0x0042 },
5624                 { 0x06, 0x0080, 0x0000 },
5625                 { 0x07, 0,      0x2000 }
5626         };
5627
5628         rtl_csi_access_enable_2(tp);
5629
5630         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5631
5632         __rtl_hw_start_8168cp(tp);
5633 }
5634
5635 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5636 {
5637         void __iomem *ioaddr = tp->mmio_addr;
5638         struct pci_dev *pdev = tp->pci_dev;
5639
5640         rtl_csi_access_enable_2(tp);
5641
5642         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5643
5644         if (tp->dev->mtu <= ETH_DATA_LEN)
5645                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5646
5647         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5648 }
5649
5650 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5651 {
5652         void __iomem *ioaddr = tp->mmio_addr;
5653         struct pci_dev *pdev = tp->pci_dev;
5654
5655         rtl_csi_access_enable_2(tp);
5656
5657         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5658
5659         /* Magic. */
5660         RTL_W8(DBG_REG, 0x20);
5661
5662         RTL_W8(MaxTxPacketSize, TxPacketMax);
5663
5664         if (tp->dev->mtu <= ETH_DATA_LEN)
5665                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5666
5667         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5668 }
5669
5670 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5671 {
5672         void __iomem *ioaddr = tp->mmio_addr;
5673         static const struct ephy_info e_info_8168c_1[] = {
5674                 { 0x02, 0x0800, 0x1000 },
5675                 { 0x03, 0,      0x0002 },
5676                 { 0x06, 0x0080, 0x0000 }
5677         };
5678
5679         rtl_csi_access_enable_2(tp);
5680
5681         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5682
5683         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5684
5685         __rtl_hw_start_8168cp(tp);
5686 }
5687
5688 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5689 {
5690         static const struct ephy_info e_info_8168c_2[] = {
5691                 { 0x01, 0,      0x0001 },
5692                 { 0x03, 0x0400, 0x0220 }
5693         };
5694
5695         rtl_csi_access_enable_2(tp);
5696
5697         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5698
5699         __rtl_hw_start_8168cp(tp);
5700 }
5701
5702 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5703 {
5704         rtl_hw_start_8168c_2(tp);
5705 }
5706
5707 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5708 {
5709         rtl_csi_access_enable_2(tp);
5710
5711         __rtl_hw_start_8168cp(tp);
5712 }
5713
5714 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5715 {
5716         void __iomem *ioaddr = tp->mmio_addr;
5717         struct pci_dev *pdev = tp->pci_dev;
5718
5719         rtl_csi_access_enable_2(tp);
5720
5721         rtl_disable_clock_request(pdev);
5722
5723         RTL_W8(MaxTxPacketSize, TxPacketMax);
5724
5725         if (tp->dev->mtu <= ETH_DATA_LEN)
5726                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5727
5728         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5729 }
5730
5731 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5732 {
5733         void __iomem *ioaddr = tp->mmio_addr;
5734         struct pci_dev *pdev = tp->pci_dev;
5735
5736         rtl_csi_access_enable_1(tp);
5737
5738         if (tp->dev->mtu <= ETH_DATA_LEN)
5739                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5740
5741         RTL_W8(MaxTxPacketSize, TxPacketMax);
5742
5743         rtl_disable_clock_request(pdev);
5744 }
5745
5746 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5747 {
5748         void __iomem *ioaddr = tp->mmio_addr;
5749         struct pci_dev *pdev = tp->pci_dev;
5750         static const struct ephy_info e_info_8168d_4[] = {
5751                 { 0x0b, ~0,     0x48 },
5752                 { 0x19, 0x20,   0x50 },
5753                 { 0x0c, ~0,     0x20 }
5754         };
5755         int i;
5756
5757         rtl_csi_access_enable_1(tp);
5758
5759         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5760
5761         RTL_W8(MaxTxPacketSize, TxPacketMax);
5762
5763         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5764                 const struct ephy_info *e = e_info_8168d_4 + i;
5765                 u16 w;
5766
5767                 w = rtl_ephy_read(tp, e->offset);
5768                 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5769         }
5770
5771         rtl_enable_clock_request(pdev);
5772 }
5773
5774 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5775 {
5776         void __iomem *ioaddr = tp->mmio_addr;
5777         struct pci_dev *pdev = tp->pci_dev;
5778         static const struct ephy_info e_info_8168e_1[] = {
5779                 { 0x00, 0x0200, 0x0100 },
5780                 { 0x00, 0x0000, 0x0004 },
5781                 { 0x06, 0x0002, 0x0001 },
5782                 { 0x06, 0x0000, 0x0030 },
5783                 { 0x07, 0x0000, 0x2000 },
5784                 { 0x00, 0x0000, 0x0020 },
5785                 { 0x03, 0x5800, 0x2000 },
5786                 { 0x03, 0x0000, 0x0001 },
5787                 { 0x01, 0x0800, 0x1000 },
5788                 { 0x07, 0x0000, 0x4000 },
5789                 { 0x1e, 0x0000, 0x2000 },
5790                 { 0x19, 0xffff, 0xfe6c },
5791                 { 0x0a, 0x0000, 0x0040 }
5792         };
5793
5794         rtl_csi_access_enable_2(tp);
5795
5796         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5797
5798         if (tp->dev->mtu <= ETH_DATA_LEN)
5799                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5800
5801         RTL_W8(MaxTxPacketSize, TxPacketMax);
5802
5803         rtl_disable_clock_request(pdev);
5804
5805         /* Reset tx FIFO pointer */
5806         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5807         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5808
5809         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5810 }
5811
5812 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5813 {
5814         void __iomem *ioaddr = tp->mmio_addr;
5815         struct pci_dev *pdev = tp->pci_dev;
5816         static const struct ephy_info e_info_8168e_2[] = {
5817                 { 0x09, 0x0000, 0x0080 },
5818                 { 0x19, 0x0000, 0x0224 }
5819         };
5820
5821         rtl_csi_access_enable_1(tp);
5822
5823         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5824
5825         if (tp->dev->mtu <= ETH_DATA_LEN)
5826                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5827
5828         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5829         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5830         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5831         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5832         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5833         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5834         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5835         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5836
5837         RTL_W8(MaxTxPacketSize, EarlySize);
5838
5839         rtl_disable_clock_request(pdev);
5840
5841         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5842         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5843
5844         /* Adjust EEE LED frequency */
5845         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5846
5847         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5848         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5849         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5850 }
5851
5852 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5853 {
5854         void __iomem *ioaddr = tp->mmio_addr;
5855         struct pci_dev *pdev = tp->pci_dev;
5856
5857         rtl_csi_access_enable_2(tp);
5858
5859         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5860
5861         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5862         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5863         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5864         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5865         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5866         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5867         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5868         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5869         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5870         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5871
5872         RTL_W8(MaxTxPacketSize, EarlySize);
5873
5874         rtl_disable_clock_request(pdev);
5875
5876         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5877         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5878         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5879         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5880         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5881 }
5882
5883 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5884 {
5885         void __iomem *ioaddr = tp->mmio_addr;
5886         static const struct ephy_info e_info_8168f_1[] = {
5887                 { 0x06, 0x00c0, 0x0020 },
5888                 { 0x08, 0x0001, 0x0002 },
5889                 { 0x09, 0x0000, 0x0080 },
5890                 { 0x19, 0x0000, 0x0224 }
5891         };
5892
5893         rtl_hw_start_8168f(tp);
5894
5895         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5896
5897         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5898
5899         /* Adjust EEE LED frequency */
5900         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5901 }
5902
5903 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5904 {
5905         static const struct ephy_info e_info_8168f_1[] = {
5906                 { 0x06, 0x00c0, 0x0020 },
5907                 { 0x0f, 0xffff, 0x5200 },
5908                 { 0x1e, 0x0000, 0x4000 },
5909                 { 0x19, 0x0000, 0x0224 }
5910         };
5911
5912         rtl_hw_start_8168f(tp);
5913         rtl_pcie_state_l2l3_enable(tp, false);
5914
5915         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5916
5917         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5918 }
5919
5920 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5921 {
5922         void __iomem *ioaddr = tp->mmio_addr;
5923         struct pci_dev *pdev = tp->pci_dev;
5924
5925         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5926
5927         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5928         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5929         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5930         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5931
5932         rtl_csi_access_enable_1(tp);
5933
5934         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5935
5936         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5937         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5938         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5939
5940         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5941         RTL_W8(MaxTxPacketSize, EarlySize);
5942
5943         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5944         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5945
5946         /* Adjust EEE LED frequency */
5947         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5948
5949         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5950         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5951
5952         rtl_pcie_state_l2l3_enable(tp, false);
5953 }
5954
5955 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5956 {
5957         void __iomem *ioaddr = tp->mmio_addr;
5958         static const struct ephy_info e_info_8168g_1[] = {
5959                 { 0x00, 0x0000, 0x0008 },
5960                 { 0x0c, 0x37d0, 0x0820 },
5961                 { 0x1e, 0x0000, 0x0001 },
5962                 { 0x19, 0x8000, 0x0000 }
5963         };
5964
5965         rtl_hw_start_8168g(tp);
5966
5967         /* disable aspm and clock request before access ephy */
5968         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5969         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5970         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5971 }
5972
5973 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5974 {
5975         void __iomem *ioaddr = tp->mmio_addr;
5976         static const struct ephy_info e_info_8168g_2[] = {
5977                 { 0x00, 0x0000, 0x0008 },
5978                 { 0x0c, 0x3df0, 0x0200 },
5979                 { 0x19, 0xffff, 0xfc00 },
5980                 { 0x1e, 0xffff, 0x20eb }
5981         };
5982
5983         rtl_hw_start_8168g(tp);
5984
5985         /* disable aspm and clock request before access ephy */
5986         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5987         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5988         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5989 }
5990
5991 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5992 {
5993         void __iomem *ioaddr = tp->mmio_addr;
5994         static const struct ephy_info e_info_8411_2[] = {
5995                 { 0x00, 0x0000, 0x0008 },
5996                 { 0x0c, 0x3df0, 0x0200 },
5997                 { 0x0f, 0xffff, 0x5200 },
5998                 { 0x19, 0x0020, 0x0000 },
5999                 { 0x1e, 0x0000, 0x2000 }
6000         };
6001
6002         rtl_hw_start_8168g(tp);
6003
6004         /* disable aspm and clock request before access ephy */
6005         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6006         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6007         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6008 }
6009
6010 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6011 {
6012         void __iomem *ioaddr = tp->mmio_addr;
6013         struct pci_dev *pdev = tp->pci_dev;
6014         u16 rg_saw_cnt;
6015         u32 data;
6016         static const struct ephy_info e_info_8168h_1[] = {
6017                 { 0x1e, 0x0800, 0x0001 },
6018                 { 0x1d, 0x0000, 0x0800 },
6019                 { 0x05, 0xffff, 0x2089 },
6020                 { 0x06, 0xffff, 0x5881 },
6021                 { 0x04, 0xffff, 0x154a },
6022                 { 0x01, 0xffff, 0x068b }
6023         };
6024
6025         /* disable aspm and clock request before access ephy */
6026         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6027         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6028         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6029
6030         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6031
6032         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6033         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6034         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6035         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6036
6037         rtl_csi_access_enable_1(tp);
6038
6039         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6040
6041         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6042         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6043
6044         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6045
6046         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6047
6048         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6049
6050         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6051         RTL_W8(MaxTxPacketSize, EarlySize);
6052
6053         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6054         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6055
6056         /* Adjust EEE LED frequency */
6057         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6058
6059         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6060         RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6061
6062         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6063
6064         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6065
6066         rtl_pcie_state_l2l3_enable(tp, false);
6067
6068         rtl_writephy(tp, 0x1f, 0x0c42);
6069         rg_saw_cnt = rtl_readphy(tp, 0x13);
6070         rtl_writephy(tp, 0x1f, 0x0000);
6071         if (rg_saw_cnt > 0) {
6072                 u16 sw_cnt_1ms_ini;
6073
6074                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6075                 sw_cnt_1ms_ini &= 0x0fff;
6076                 data = r8168_mac_ocp_read(tp, 0xd412);
6077                 data &= 0x0fff;
6078                 data |= sw_cnt_1ms_ini;
6079                 r8168_mac_ocp_write(tp, 0xd412, data);
6080         }
6081
6082         data = r8168_mac_ocp_read(tp, 0xe056);
6083         data &= 0xf0;
6084         data |= 0x07;
6085         r8168_mac_ocp_write(tp, 0xe056, data);
6086
6087         data = r8168_mac_ocp_read(tp, 0xe052);
6088         data &= 0x8008;
6089         data |= 0x6000;
6090         r8168_mac_ocp_write(tp, 0xe052, data);
6091
6092         data = r8168_mac_ocp_read(tp, 0xe0d6);
6093         data &= 0x01ff;
6094         data |= 0x017f;
6095         r8168_mac_ocp_write(tp, 0xe0d6, data);
6096
6097         data = r8168_mac_ocp_read(tp, 0xd420);
6098         data &= 0x0fff;
6099         data |= 0x047f;
6100         r8168_mac_ocp_write(tp, 0xd420, data);
6101
6102         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6103         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6104         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6105         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6106 }
6107
6108 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6109 {
6110         void __iomem *ioaddr = tp->mmio_addr;
6111         struct pci_dev *pdev = tp->pci_dev;
6112
6113         rtl8168ep_stop_cmac(tp);
6114
6115         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6116
6117         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6118         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6119         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6120         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6121
6122         rtl_csi_access_enable_1(tp);
6123
6124         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6125
6126         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6127         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6128
6129         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6130
6131         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6132
6133         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6134         RTL_W8(MaxTxPacketSize, EarlySize);
6135
6136         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6137         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6138
6139         /* Adjust EEE LED frequency */
6140         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6141
6142         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6143
6144         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6145
6146         rtl_pcie_state_l2l3_enable(tp, false);
6147 }
6148
6149 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6150 {
6151         void __iomem *ioaddr = tp->mmio_addr;
6152         static const struct ephy_info e_info_8168ep_1[] = {
6153                 { 0x00, 0xffff, 0x10ab },
6154                 { 0x06, 0xffff, 0xf030 },
6155                 { 0x08, 0xffff, 0x2006 },
6156                 { 0x0d, 0xffff, 0x1666 },
6157                 { 0x0c, 0x3ff0, 0x0000 }
6158         };
6159
6160         /* disable aspm and clock request before access ephy */
6161         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6162         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6163         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6164
6165         rtl_hw_start_8168ep(tp);
6166 }
6167
6168 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6169 {
6170         void __iomem *ioaddr = tp->mmio_addr;
6171         static const struct ephy_info e_info_8168ep_2[] = {
6172                 { 0x00, 0xffff, 0x10a3 },
6173                 { 0x19, 0xffff, 0xfc00 },
6174                 { 0x1e, 0xffff, 0x20ea }
6175         };
6176
6177         /* disable aspm and clock request before access ephy */
6178         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6179         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6180         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6181
6182         rtl_hw_start_8168ep(tp);
6183
6184         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6185         RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6186 }
6187
6188 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6189 {
6190         void __iomem *ioaddr = tp->mmio_addr;
6191         u32 data;
6192         static const struct ephy_info e_info_8168ep_3[] = {
6193                 { 0x00, 0xffff, 0x10a3 },
6194                 { 0x19, 0xffff, 0x7c00 },
6195                 { 0x1e, 0xffff, 0x20eb },
6196                 { 0x0d, 0xffff, 0x1666 }
6197         };
6198
6199         /* disable aspm and clock request before access ephy */
6200         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6201         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6202         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6203
6204         rtl_hw_start_8168ep(tp);
6205
6206         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6207         RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6208
6209         data = r8168_mac_ocp_read(tp, 0xd3e2);
6210         data &= 0xf000;
6211         data |= 0x0271;
6212         r8168_mac_ocp_write(tp, 0xd3e2, data);
6213
6214         data = r8168_mac_ocp_read(tp, 0xd3e4);
6215         data &= 0xff00;
6216         r8168_mac_ocp_write(tp, 0xd3e4, data);
6217
6218         data = r8168_mac_ocp_read(tp, 0xe860);
6219         data |= 0x0080;
6220         r8168_mac_ocp_write(tp, 0xe860, data);
6221 }
6222
6223 static void rtl_hw_start_8168(struct net_device *dev)
6224 {
6225         struct rtl8169_private *tp = netdev_priv(dev);
6226         void __iomem *ioaddr = tp->mmio_addr;
6227
6228         RTL_W8(Cfg9346, Cfg9346_Unlock);
6229
6230         RTL_W8(MaxTxPacketSize, TxPacketMax);
6231
6232         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6233
6234         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6235
6236         RTL_W16(CPlusCmd, tp->cp_cmd);
6237
6238         RTL_W16(IntrMitigate, 0x5151);
6239
6240         /* Work around for RxFIFO overflow. */
6241         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6242                 tp->event_slow |= RxFIFOOver | PCSTimeout;
6243                 tp->event_slow &= ~RxOverflow;
6244         }
6245
6246         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6247
6248         rtl_set_rx_tx_config_registers(tp);
6249
6250         RTL_R8(IntrMask);
6251
6252         switch (tp->mac_version) {
6253         case RTL_GIGA_MAC_VER_11:
6254                 rtl_hw_start_8168bb(tp);
6255                 break;
6256
6257         case RTL_GIGA_MAC_VER_12:
6258         case RTL_GIGA_MAC_VER_17:
6259                 rtl_hw_start_8168bef(tp);
6260                 break;
6261
6262         case RTL_GIGA_MAC_VER_18:
6263                 rtl_hw_start_8168cp_1(tp);
6264                 break;
6265
6266         case RTL_GIGA_MAC_VER_19:
6267                 rtl_hw_start_8168c_1(tp);
6268                 break;
6269
6270         case RTL_GIGA_MAC_VER_20:
6271                 rtl_hw_start_8168c_2(tp);
6272                 break;
6273
6274         case RTL_GIGA_MAC_VER_21:
6275                 rtl_hw_start_8168c_3(tp);
6276                 break;
6277
6278         case RTL_GIGA_MAC_VER_22:
6279                 rtl_hw_start_8168c_4(tp);
6280                 break;
6281
6282         case RTL_GIGA_MAC_VER_23:
6283                 rtl_hw_start_8168cp_2(tp);
6284                 break;
6285
6286         case RTL_GIGA_MAC_VER_24:
6287                 rtl_hw_start_8168cp_3(tp);
6288                 break;
6289
6290         case RTL_GIGA_MAC_VER_25:
6291         case RTL_GIGA_MAC_VER_26:
6292         case RTL_GIGA_MAC_VER_27:
6293                 rtl_hw_start_8168d(tp);
6294                 break;
6295
6296         case RTL_GIGA_MAC_VER_28:
6297                 rtl_hw_start_8168d_4(tp);
6298                 break;
6299
6300         case RTL_GIGA_MAC_VER_31:
6301                 rtl_hw_start_8168dp(tp);
6302                 break;
6303
6304         case RTL_GIGA_MAC_VER_32:
6305         case RTL_GIGA_MAC_VER_33:
6306                 rtl_hw_start_8168e_1(tp);
6307                 break;
6308         case RTL_GIGA_MAC_VER_34:
6309                 rtl_hw_start_8168e_2(tp);
6310                 break;
6311
6312         case RTL_GIGA_MAC_VER_35:
6313         case RTL_GIGA_MAC_VER_36:
6314                 rtl_hw_start_8168f_1(tp);
6315                 break;
6316
6317         case RTL_GIGA_MAC_VER_38:
6318                 rtl_hw_start_8411(tp);
6319                 break;
6320
6321         case RTL_GIGA_MAC_VER_40:
6322         case RTL_GIGA_MAC_VER_41:
6323                 rtl_hw_start_8168g_1(tp);
6324                 break;
6325         case RTL_GIGA_MAC_VER_42:
6326                 rtl_hw_start_8168g_2(tp);
6327                 break;
6328
6329         case RTL_GIGA_MAC_VER_44:
6330                 rtl_hw_start_8411_2(tp);
6331                 break;
6332
6333         case RTL_GIGA_MAC_VER_45:
6334         case RTL_GIGA_MAC_VER_46:
6335                 rtl_hw_start_8168h_1(tp);
6336                 break;
6337
6338         case RTL_GIGA_MAC_VER_49:
6339                 rtl_hw_start_8168ep_1(tp);
6340                 break;
6341
6342         case RTL_GIGA_MAC_VER_50:
6343                 rtl_hw_start_8168ep_2(tp);
6344                 break;
6345
6346         case RTL_GIGA_MAC_VER_51:
6347                 rtl_hw_start_8168ep_3(tp);
6348                 break;
6349
6350         default:
6351                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6352                         dev->name, tp->mac_version);
6353                 break;
6354         }
6355
6356         RTL_W8(Cfg9346, Cfg9346_Lock);
6357
6358         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6359
6360         rtl_set_rx_mode(dev);
6361
6362         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6363 }
6364
6365 #define R810X_CPCMD_QUIRK_MASK (\
6366         EnableBist | \
6367         Mac_dbgo_oe | \
6368         Force_half_dup | \
6369         Force_rxflow_en | \
6370         Force_txflow_en | \
6371         Cxpl_dbg_sel | \
6372         ASF | \
6373         PktCntrDisable | \
6374         Mac_dbgo_sel)
6375
6376 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6377 {
6378         void __iomem *ioaddr = tp->mmio_addr;
6379         struct pci_dev *pdev = tp->pci_dev;
6380         static const struct ephy_info e_info_8102e_1[] = {
6381                 { 0x01, 0, 0x6e65 },
6382                 { 0x02, 0, 0x091f },
6383                 { 0x03, 0, 0xc2f9 },
6384                 { 0x06, 0, 0xafb5 },
6385                 { 0x07, 0, 0x0e00 },
6386                 { 0x19, 0, 0xec80 },
6387                 { 0x01, 0, 0x2e65 },
6388                 { 0x01, 0, 0x6e65 }
6389         };
6390         u8 cfg1;
6391
6392         rtl_csi_access_enable_2(tp);
6393
6394         RTL_W8(DBG_REG, FIX_NAK_1);
6395
6396         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6397
6398         RTL_W8(Config1,
6399                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6400         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6401
6402         cfg1 = RTL_R8(Config1);
6403         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6404                 RTL_W8(Config1, cfg1 & ~LEDS0);
6405
6406         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6407 }
6408
6409 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6410 {
6411         void __iomem *ioaddr = tp->mmio_addr;
6412         struct pci_dev *pdev = tp->pci_dev;
6413
6414         rtl_csi_access_enable_2(tp);
6415
6416         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6417
6418         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6419         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6420 }
6421
6422 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6423 {
6424         rtl_hw_start_8102e_2(tp);
6425
6426         rtl_ephy_write(tp, 0x03, 0xc2f9);
6427 }
6428
6429 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6430 {
6431         void __iomem *ioaddr = tp->mmio_addr;
6432         static const struct ephy_info e_info_8105e_1[] = {
6433                 { 0x07, 0, 0x4000 },
6434                 { 0x19, 0, 0x0200 },
6435                 { 0x19, 0, 0x0020 },
6436                 { 0x1e, 0, 0x2000 },
6437                 { 0x03, 0, 0x0001 },
6438                 { 0x19, 0, 0x0100 },
6439                 { 0x19, 0, 0x0004 },
6440                 { 0x0a, 0, 0x0020 }
6441         };
6442
6443         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6444         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6445
6446         /* Disable Early Tally Counter */
6447         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6448
6449         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6450         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6451
6452         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6453
6454         rtl_pcie_state_l2l3_enable(tp, false);
6455 }
6456
6457 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6458 {
6459         rtl_hw_start_8105e_1(tp);
6460         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6461 }
6462
6463 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6464 {
6465         void __iomem *ioaddr = tp->mmio_addr;
6466         static const struct ephy_info e_info_8402[] = {
6467                 { 0x19, 0xffff, 0xff64 },
6468                 { 0x1e, 0, 0x4000 }
6469         };
6470
6471         rtl_csi_access_enable_2(tp);
6472
6473         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6474         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6475
6476         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6477         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6478
6479         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6480
6481         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6482
6483         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6484         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6485         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6486         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6487         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6488         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6489         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6490
6491         rtl_pcie_state_l2l3_enable(tp, false);
6492 }
6493
6494 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6495 {
6496         void __iomem *ioaddr = tp->mmio_addr;
6497
6498         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6499         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6500
6501         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6502         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6503         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6504
6505         rtl_pcie_state_l2l3_enable(tp, false);
6506 }
6507
6508 static void rtl_hw_start_8101(struct net_device *dev)
6509 {
6510         struct rtl8169_private *tp = netdev_priv(dev);
6511         void __iomem *ioaddr = tp->mmio_addr;
6512         struct pci_dev *pdev = tp->pci_dev;
6513
6514         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6515                 tp->event_slow &= ~RxFIFOOver;
6516
6517         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6518             tp->mac_version == RTL_GIGA_MAC_VER_16)
6519                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6520                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
6521
6522         RTL_W8(Cfg9346, Cfg9346_Unlock);
6523
6524         RTL_W8(MaxTxPacketSize, TxPacketMax);
6525
6526         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6527
6528         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6529         RTL_W16(CPlusCmd, tp->cp_cmd);
6530
6531         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6532
6533         rtl_set_rx_tx_config_registers(tp);
6534
6535         switch (tp->mac_version) {
6536         case RTL_GIGA_MAC_VER_07:
6537                 rtl_hw_start_8102e_1(tp);
6538                 break;
6539
6540         case RTL_GIGA_MAC_VER_08:
6541                 rtl_hw_start_8102e_3(tp);
6542                 break;
6543
6544         case RTL_GIGA_MAC_VER_09:
6545                 rtl_hw_start_8102e_2(tp);
6546                 break;
6547
6548         case RTL_GIGA_MAC_VER_29:
6549                 rtl_hw_start_8105e_1(tp);
6550                 break;
6551         case RTL_GIGA_MAC_VER_30:
6552                 rtl_hw_start_8105e_2(tp);
6553                 break;
6554
6555         case RTL_GIGA_MAC_VER_37:
6556                 rtl_hw_start_8402(tp);
6557                 break;
6558
6559         case RTL_GIGA_MAC_VER_39:
6560                 rtl_hw_start_8106(tp);
6561                 break;
6562         case RTL_GIGA_MAC_VER_43:
6563                 rtl_hw_start_8168g_2(tp);
6564                 break;
6565         case RTL_GIGA_MAC_VER_47:
6566         case RTL_GIGA_MAC_VER_48:
6567                 rtl_hw_start_8168h_1(tp);
6568                 break;
6569         }
6570
6571         RTL_W8(Cfg9346, Cfg9346_Lock);
6572
6573         RTL_W16(IntrMitigate, 0x0000);
6574
6575         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6576
6577         rtl_set_rx_mode(dev);
6578
6579         RTL_R8(IntrMask);
6580
6581         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6582 }
6583
6584 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6585 {
6586         struct rtl8169_private *tp = netdev_priv(dev);
6587
6588         if (new_mtu < ETH_ZLEN ||
6589             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
6590                 return -EINVAL;
6591
6592         if (new_mtu > ETH_DATA_LEN)
6593                 rtl_hw_jumbo_enable(tp);
6594         else
6595                 rtl_hw_jumbo_disable(tp);
6596
6597         dev->mtu = new_mtu;
6598         netdev_update_features(dev);
6599
6600         return 0;
6601 }
6602
6603 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6604 {
6605         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6606         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6607 }
6608
6609 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6610                                      void **data_buff, struct RxDesc *desc)
6611 {
6612         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6613                          DMA_FROM_DEVICE);
6614
6615         kfree(*data_buff);
6616         *data_buff = NULL;
6617         rtl8169_make_unusable_by_asic(desc);
6618 }
6619
6620 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6621 {
6622         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6623
6624         /* Force memory writes to complete before releasing descriptor */
6625         dma_wmb();
6626
6627         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6628 }
6629
6630 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6631                                        u32 rx_buf_sz)
6632 {
6633         desc->addr = cpu_to_le64(mapping);
6634         rtl8169_mark_to_asic(desc, rx_buf_sz);
6635 }
6636
6637 static inline void *rtl8169_align(void *data)
6638 {
6639         return (void *)ALIGN((long)data, 16);
6640 }
6641
6642 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6643                                              struct RxDesc *desc)
6644 {
6645         void *data;
6646         dma_addr_t mapping;
6647         struct device *d = &tp->pci_dev->dev;
6648         struct net_device *dev = tp->dev;
6649         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6650
6651         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6652         if (!data)
6653                 return NULL;
6654
6655         if (rtl8169_align(data) != data) {
6656                 kfree(data);
6657                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6658                 if (!data)
6659                         return NULL;
6660         }
6661
6662         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6663                                  DMA_FROM_DEVICE);
6664         if (unlikely(dma_mapping_error(d, mapping))) {
6665                 if (net_ratelimit())
6666                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6667                 goto err_out;
6668         }
6669
6670         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6671         return data;
6672
6673 err_out:
6674         kfree(data);
6675         return NULL;
6676 }
6677
6678 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6679 {
6680         unsigned int i;
6681
6682         for (i = 0; i < NUM_RX_DESC; i++) {
6683                 if (tp->Rx_databuff[i]) {
6684                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6685                                             tp->RxDescArray + i);
6686                 }
6687         }
6688 }
6689
6690 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6691 {
6692         desc->opts1 |= cpu_to_le32(RingEnd);
6693 }
6694
6695 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6696 {
6697         unsigned int i;
6698
6699         for (i = 0; i < NUM_RX_DESC; i++) {
6700                 void *data;
6701
6702                 if (tp->Rx_databuff[i])
6703                         continue;
6704
6705                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6706                 if (!data) {
6707                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6708                         goto err_out;
6709                 }
6710                 tp->Rx_databuff[i] = data;
6711         }
6712
6713         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6714         return 0;
6715
6716 err_out:
6717         rtl8169_rx_clear(tp);
6718         return -ENOMEM;
6719 }
6720
6721 static int rtl8169_init_ring(struct net_device *dev)
6722 {
6723         struct rtl8169_private *tp = netdev_priv(dev);
6724
6725         rtl8169_init_ring_indexes(tp);
6726
6727         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6728         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6729
6730         return rtl8169_rx_fill(tp);
6731 }
6732
6733 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6734                                  struct TxDesc *desc)
6735 {
6736         unsigned int len = tx_skb->len;
6737
6738         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6739
6740         desc->opts1 = 0x00;
6741         desc->opts2 = 0x00;
6742         desc->addr = 0x00;
6743         tx_skb->len = 0;
6744 }
6745
6746 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6747                                    unsigned int n)
6748 {
6749         unsigned int i;
6750
6751         for (i = 0; i < n; i++) {
6752                 unsigned int entry = (start + i) % NUM_TX_DESC;
6753                 struct ring_info *tx_skb = tp->tx_skb + entry;
6754                 unsigned int len = tx_skb->len;
6755
6756                 if (len) {
6757                         struct sk_buff *skb = tx_skb->skb;
6758
6759                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6760                                              tp->TxDescArray + entry);
6761                         if (skb) {
6762                                 tp->dev->stats.tx_dropped++;
6763                                 dev_kfree_skb_any(skb);
6764                                 tx_skb->skb = NULL;
6765                         }
6766                 }
6767         }
6768 }
6769
6770 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6771 {
6772         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6773         tp->cur_tx = tp->dirty_tx = 0;
6774 }
6775
6776 static void rtl_reset_work(struct rtl8169_private *tp)
6777 {
6778         struct net_device *dev = tp->dev;
6779         int i;
6780
6781         napi_disable(&tp->napi);
6782         netif_stop_queue(dev);
6783         synchronize_sched();
6784
6785         rtl8169_hw_reset(tp);
6786
6787         for (i = 0; i < NUM_RX_DESC; i++)
6788                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6789
6790         rtl8169_tx_clear(tp);
6791         rtl8169_init_ring_indexes(tp);
6792
6793         napi_enable(&tp->napi);
6794         rtl_hw_start(dev);
6795         netif_wake_queue(dev);
6796         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6797 }
6798
6799 static void rtl8169_tx_timeout(struct net_device *dev)
6800 {
6801         struct rtl8169_private *tp = netdev_priv(dev);
6802
6803         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6804 }
6805
6806 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6807                               u32 *opts)
6808 {
6809         struct skb_shared_info *info = skb_shinfo(skb);
6810         unsigned int cur_frag, entry;
6811         struct TxDesc *uninitialized_var(txd);
6812         struct device *d = &tp->pci_dev->dev;
6813
6814         entry = tp->cur_tx;
6815         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6816                 const skb_frag_t *frag = info->frags + cur_frag;
6817                 dma_addr_t mapping;
6818                 u32 status, len;
6819                 void *addr;
6820
6821                 entry = (entry + 1) % NUM_TX_DESC;
6822
6823                 txd = tp->TxDescArray + entry;
6824                 len = skb_frag_size(frag);
6825                 addr = skb_frag_address(frag);
6826                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6827                 if (unlikely(dma_mapping_error(d, mapping))) {
6828                         if (net_ratelimit())
6829                                 netif_err(tp, drv, tp->dev,
6830                                           "Failed to map TX fragments DMA!\n");
6831                         goto err_out;
6832                 }
6833
6834                 /* Anti gcc 2.95.3 bugware (sic) */
6835                 status = opts[0] | len |
6836                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6837
6838                 txd->opts1 = cpu_to_le32(status);
6839                 txd->opts2 = cpu_to_le32(opts[1]);
6840                 txd->addr = cpu_to_le64(mapping);
6841
6842                 tp->tx_skb[entry].len = len;
6843         }
6844
6845         if (cur_frag) {
6846                 tp->tx_skb[entry].skb = skb;
6847                 txd->opts1 |= cpu_to_le32(LastFrag);
6848         }
6849
6850         return cur_frag;
6851
6852 err_out:
6853         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6854         return -EIO;
6855 }
6856
6857 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6858 {
6859         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6860 }
6861
6862 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6863                                       struct net_device *dev);
6864 /* r8169_csum_workaround()
6865  * The hw limites the value the transport offset. When the offset is out of the
6866  * range, calculate the checksum by sw.
6867  */
6868 static void r8169_csum_workaround(struct rtl8169_private *tp,
6869                                   struct sk_buff *skb)
6870 {
6871         if (skb_shinfo(skb)->gso_size) {
6872                 netdev_features_t features = tp->dev->features;
6873                 struct sk_buff *segs, *nskb;
6874
6875                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6876                 segs = skb_gso_segment(skb, features);
6877                 if (IS_ERR(segs) || !segs)
6878                         goto drop;
6879
6880                 do {
6881                         nskb = segs;
6882                         segs = segs->next;
6883                         nskb->next = NULL;
6884                         rtl8169_start_xmit(nskb, tp->dev);
6885                 } while (segs);
6886
6887                 dev_consume_skb_any(skb);
6888         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6889                 if (skb_checksum_help(skb) < 0)
6890                         goto drop;
6891
6892                 rtl8169_start_xmit(skb, tp->dev);
6893         } else {
6894                 struct net_device_stats *stats;
6895
6896 drop:
6897                 stats = &tp->dev->stats;
6898                 stats->tx_dropped++;
6899                 dev_kfree_skb_any(skb);
6900         }
6901 }
6902
6903 /* msdn_giant_send_check()
6904  * According to the document of microsoft, the TCP Pseudo Header excludes the
6905  * packet length for IPv6 TCP large packets.
6906  */
6907 static int msdn_giant_send_check(struct sk_buff *skb)
6908 {
6909         const struct ipv6hdr *ipv6h;
6910         struct tcphdr *th;
6911         int ret;
6912
6913         ret = skb_cow_head(skb, 0);
6914         if (ret)
6915                 return ret;
6916
6917         ipv6h = ipv6_hdr(skb);
6918         th = tcp_hdr(skb);
6919
6920         th->check = 0;
6921         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6922
6923         return ret;
6924 }
6925
6926 static inline __be16 get_protocol(struct sk_buff *skb)
6927 {
6928         __be16 protocol;
6929
6930         if (skb->protocol == htons(ETH_P_8021Q))
6931                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6932         else
6933                 protocol = skb->protocol;
6934
6935         return protocol;
6936 }
6937
6938 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6939                                 struct sk_buff *skb, u32 *opts)
6940 {
6941         u32 mss = skb_shinfo(skb)->gso_size;
6942
6943         if (mss) {
6944                 opts[0] |= TD_LSO;
6945                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6946         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6947                 const struct iphdr *ip = ip_hdr(skb);
6948
6949                 if (ip->protocol == IPPROTO_TCP)
6950                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6951                 else if (ip->protocol == IPPROTO_UDP)
6952                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6953                 else
6954                         WARN_ON_ONCE(1);
6955         }
6956
6957         return true;
6958 }
6959
6960 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6961                                 struct sk_buff *skb, u32 *opts)
6962 {
6963         u32 transport_offset = (u32)skb_transport_offset(skb);
6964         u32 mss = skb_shinfo(skb)->gso_size;
6965
6966         if (mss) {
6967                 if (transport_offset > GTTCPHO_MAX) {
6968                         netif_warn(tp, tx_err, tp->dev,
6969                                    "Invalid transport offset 0x%x for TSO\n",
6970                                    transport_offset);
6971                         return false;
6972                 }
6973
6974                 switch (get_protocol(skb)) {
6975                 case htons(ETH_P_IP):
6976                         opts[0] |= TD1_GTSENV4;
6977                         break;
6978
6979                 case htons(ETH_P_IPV6):
6980                         if (msdn_giant_send_check(skb))
6981                                 return false;
6982
6983                         opts[0] |= TD1_GTSENV6;
6984                         break;
6985
6986                 default:
6987                         WARN_ON_ONCE(1);
6988                         break;
6989                 }
6990
6991                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6992                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6993         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6994                 u8 ip_protocol;
6995
6996                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6997                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6998
6999                 if (transport_offset > TCPHO_MAX) {
7000                         netif_warn(tp, tx_err, tp->dev,
7001                                    "Invalid transport offset 0x%x\n",
7002                                    transport_offset);
7003                         return false;
7004                 }
7005
7006                 switch (get_protocol(skb)) {
7007                 case htons(ETH_P_IP):
7008                         opts[1] |= TD1_IPv4_CS;
7009                         ip_protocol = ip_hdr(skb)->protocol;
7010                         break;
7011
7012                 case htons(ETH_P_IPV6):
7013                         opts[1] |= TD1_IPv6_CS;
7014                         ip_protocol = ipv6_hdr(skb)->nexthdr;
7015                         break;
7016
7017                 default:
7018                         ip_protocol = IPPROTO_RAW;
7019                         break;
7020                 }
7021
7022                 if (ip_protocol == IPPROTO_TCP)
7023                         opts[1] |= TD1_TCP_CS;
7024                 else if (ip_protocol == IPPROTO_UDP)
7025                         opts[1] |= TD1_UDP_CS;
7026                 else
7027                         WARN_ON_ONCE(1);
7028
7029                 opts[1] |= transport_offset << TCPHO_SHIFT;
7030         } else {
7031                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7032                         return !eth_skb_pad(skb);
7033         }
7034
7035         return true;
7036 }
7037
7038 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7039                                       struct net_device *dev)
7040 {
7041         struct rtl8169_private *tp = netdev_priv(dev);
7042         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7043         struct TxDesc *txd = tp->TxDescArray + entry;
7044         void __iomem *ioaddr = tp->mmio_addr;
7045         struct device *d = &tp->pci_dev->dev;
7046         dma_addr_t mapping;
7047         u32 status, len;
7048         u32 opts[2];
7049         int frags;
7050
7051         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7052                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7053                 goto err_stop_0;
7054         }
7055
7056         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7057                 goto err_stop_0;
7058
7059         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7060         opts[0] = DescOwn;
7061
7062         if (!tp->tso_csum(tp, skb, opts)) {
7063                 r8169_csum_workaround(tp, skb);
7064                 return NETDEV_TX_OK;
7065         }
7066
7067         len = skb_headlen(skb);
7068         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7069         if (unlikely(dma_mapping_error(d, mapping))) {
7070                 if (net_ratelimit())
7071                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7072                 goto err_dma_0;
7073         }
7074
7075         tp->tx_skb[entry].len = len;
7076         txd->addr = cpu_to_le64(mapping);
7077
7078         frags = rtl8169_xmit_frags(tp, skb, opts);
7079         if (frags < 0)
7080                 goto err_dma_1;
7081         else if (frags)
7082                 opts[0] |= FirstFrag;
7083         else {
7084                 opts[0] |= FirstFrag | LastFrag;
7085                 tp->tx_skb[entry].skb = skb;
7086         }
7087
7088         txd->opts2 = cpu_to_le32(opts[1]);
7089
7090         skb_tx_timestamp(skb);
7091
7092         /* Force memory writes to complete before releasing descriptor */
7093         dma_wmb();
7094
7095         /* Anti gcc 2.95.3 bugware (sic) */
7096         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7097         txd->opts1 = cpu_to_le32(status);
7098
7099         /* Force all memory writes to complete before notifying device */
7100         wmb();
7101
7102         tp->cur_tx += frags + 1;
7103
7104         RTL_W8(TxPoll, NPQ);
7105
7106         mmiowb();
7107
7108         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7109                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7110                  * not miss a ring update when it notices a stopped queue.
7111                  */
7112                 smp_wmb();
7113                 netif_stop_queue(dev);
7114                 /* Sync with rtl_tx:
7115                  * - publish queue status and cur_tx ring index (write barrier)
7116                  * - refresh dirty_tx ring index (read barrier).
7117                  * May the current thread have a pessimistic view of the ring
7118                  * status and forget to wake up queue, a racing rtl_tx thread
7119                  * can't.
7120                  */
7121                 smp_mb();
7122                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7123                         netif_wake_queue(dev);
7124         }
7125
7126         return NETDEV_TX_OK;
7127
7128 err_dma_1:
7129         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7130 err_dma_0:
7131         dev_kfree_skb_any(skb);
7132         dev->stats.tx_dropped++;
7133         return NETDEV_TX_OK;
7134
7135 err_stop_0:
7136         netif_stop_queue(dev);
7137         dev->stats.tx_dropped++;
7138         return NETDEV_TX_BUSY;
7139 }
7140
7141 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7142 {
7143         struct rtl8169_private *tp = netdev_priv(dev);
7144         struct pci_dev *pdev = tp->pci_dev;
7145         u16 pci_status, pci_cmd;
7146
7147         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7148         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7149
7150         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7151                   pci_cmd, pci_status);
7152
7153         /*
7154          * The recovery sequence below admits a very elaborated explanation:
7155          * - it seems to work;
7156          * - I did not see what else could be done;
7157          * - it makes iop3xx happy.
7158          *
7159          * Feel free to adjust to your needs.
7160          */
7161         if (pdev->broken_parity_status)
7162                 pci_cmd &= ~PCI_COMMAND_PARITY;
7163         else
7164                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7165
7166         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7167
7168         pci_write_config_word(pdev, PCI_STATUS,
7169                 pci_status & (PCI_STATUS_DETECTED_PARITY |
7170                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7171                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7172
7173         /* The infamous DAC f*ckup only happens at boot time */
7174         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7175                 void __iomem *ioaddr = tp->mmio_addr;
7176
7177                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7178                 tp->cp_cmd &= ~PCIDAC;
7179                 RTL_W16(CPlusCmd, tp->cp_cmd);
7180                 dev->features &= ~NETIF_F_HIGHDMA;
7181         }
7182
7183         rtl8169_hw_reset(tp);
7184
7185         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7186 }
7187
7188 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7189 {
7190         unsigned int dirty_tx, tx_left;
7191
7192         dirty_tx = tp->dirty_tx;
7193         smp_rmb();
7194         tx_left = tp->cur_tx - dirty_tx;
7195
7196         while (tx_left > 0) {
7197                 unsigned int entry = dirty_tx % NUM_TX_DESC;
7198                 struct ring_info *tx_skb = tp->tx_skb + entry;
7199                 u32 status;
7200
7201                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7202                 if (status & DescOwn)
7203                         break;
7204
7205                 /* This barrier is needed to keep us from reading
7206                  * any other fields out of the Tx descriptor until
7207                  * we know the status of DescOwn
7208                  */
7209                 dma_rmb();
7210
7211                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7212                                      tp->TxDescArray + entry);
7213                 if (status & LastFrag) {
7214                         u64_stats_update_begin(&tp->tx_stats.syncp);
7215                         tp->tx_stats.packets++;
7216                         tp->tx_stats.bytes += tx_skb->skb->len;
7217                         u64_stats_update_end(&tp->tx_stats.syncp);
7218                         dev_kfree_skb_any(tx_skb->skb);
7219                         tx_skb->skb = NULL;
7220                 }
7221                 dirty_tx++;
7222                 tx_left--;
7223         }
7224
7225         if (tp->dirty_tx != dirty_tx) {
7226                 tp->dirty_tx = dirty_tx;
7227                 /* Sync with rtl8169_start_xmit:
7228                  * - publish dirty_tx ring index (write barrier)
7229                  * - refresh cur_tx ring index and queue status (read barrier)
7230                  * May the current thread miss the stopped queue condition,
7231                  * a racing xmit thread can only have a right view of the
7232                  * ring status.
7233                  */
7234                 smp_mb();
7235                 if (netif_queue_stopped(dev) &&
7236                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7237                         netif_wake_queue(dev);
7238                 }
7239                 /*
7240                  * 8168 hack: TxPoll requests are lost when the Tx packets are
7241                  * too close. Let's kick an extra TxPoll request when a burst
7242                  * of start_xmit activity is detected (if it is not detected,
7243                  * it is slow enough). -- FR
7244                  */
7245                 if (tp->cur_tx != dirty_tx) {
7246                         void __iomem *ioaddr = tp->mmio_addr;
7247
7248                         RTL_W8(TxPoll, NPQ);
7249                 }
7250         }
7251 }
7252
7253 static inline int rtl8169_fragmented_frame(u32 status)
7254 {
7255         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7256 }
7257
7258 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7259 {
7260         u32 status = opts1 & RxProtoMask;
7261
7262         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7263             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7264                 skb->ip_summed = CHECKSUM_UNNECESSARY;
7265         else
7266                 skb_checksum_none_assert(skb);
7267 }
7268
7269 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7270                                            struct rtl8169_private *tp,
7271                                            int pkt_size,
7272                                            dma_addr_t addr)
7273 {
7274         struct sk_buff *skb;
7275         struct device *d = &tp->pci_dev->dev;
7276
7277         data = rtl8169_align(data);
7278         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7279         prefetch(data);
7280         skb = napi_alloc_skb(&tp->napi, pkt_size);
7281         if (skb)
7282                 memcpy(skb->data, data, pkt_size);
7283         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7284
7285         return skb;
7286 }
7287
7288 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7289 {
7290         unsigned int cur_rx, rx_left;
7291         unsigned int count;
7292
7293         cur_rx = tp->cur_rx;
7294
7295         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7296                 unsigned int entry = cur_rx % NUM_RX_DESC;
7297                 struct RxDesc *desc = tp->RxDescArray + entry;
7298                 u32 status;
7299
7300                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7301                 if (status & DescOwn)
7302                         break;
7303
7304                 /* This barrier is needed to keep us from reading
7305                  * any other fields out of the Rx descriptor until
7306                  * we know the status of DescOwn
7307                  */
7308                 dma_rmb();
7309
7310                 if (unlikely(status & RxRES)) {
7311                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7312                                    status);
7313                         dev->stats.rx_errors++;
7314                         if (status & (RxRWT | RxRUNT))
7315                                 dev->stats.rx_length_errors++;
7316                         if (status & RxCRC)
7317                                 dev->stats.rx_crc_errors++;
7318                         if (status & RxFOVF) {
7319                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7320                                 dev->stats.rx_fifo_errors++;
7321                         }
7322                         if ((status & (RxRUNT | RxCRC)) &&
7323                             !(status & (RxRWT | RxFOVF)) &&
7324                             (dev->features & NETIF_F_RXALL))
7325                                 goto process_pkt;
7326                 } else {
7327                         struct sk_buff *skb;
7328                         dma_addr_t addr;
7329                         int pkt_size;
7330
7331 process_pkt:
7332                         addr = le64_to_cpu(desc->addr);
7333                         if (likely(!(dev->features & NETIF_F_RXFCS)))
7334                                 pkt_size = (status & 0x00003fff) - 4;
7335                         else
7336                                 pkt_size = status & 0x00003fff;
7337
7338                         /*
7339                          * The driver does not support incoming fragmented
7340                          * frames. They are seen as a symptom of over-mtu
7341                          * sized frames.
7342                          */
7343                         if (unlikely(rtl8169_fragmented_frame(status))) {
7344                                 dev->stats.rx_dropped++;
7345                                 dev->stats.rx_length_errors++;
7346                                 goto release_descriptor;
7347                         }
7348
7349                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7350                                                   tp, pkt_size, addr);
7351                         if (!skb) {
7352                                 dev->stats.rx_dropped++;
7353                                 goto release_descriptor;
7354                         }
7355
7356                         rtl8169_rx_csum(skb, status);
7357                         skb_put(skb, pkt_size);
7358                         skb->protocol = eth_type_trans(skb, dev);
7359
7360                         rtl8169_rx_vlan_tag(desc, skb);
7361
7362                         napi_gro_receive(&tp->napi, skb);
7363
7364                         u64_stats_update_begin(&tp->rx_stats.syncp);
7365                         tp->rx_stats.packets++;
7366                         tp->rx_stats.bytes += pkt_size;
7367                         u64_stats_update_end(&tp->rx_stats.syncp);
7368                 }
7369 release_descriptor:
7370                 desc->opts2 = 0;
7371                 rtl8169_mark_to_asic(desc, rx_buf_sz);
7372         }
7373
7374         count = cur_rx - tp->cur_rx;
7375         tp->cur_rx = cur_rx;
7376
7377         return count;
7378 }
7379
7380 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7381 {
7382         struct net_device *dev = dev_instance;
7383         struct rtl8169_private *tp = netdev_priv(dev);
7384         int handled = 0;
7385         u16 status;
7386
7387         status = rtl_get_events(tp);
7388         if (status && status != 0xffff) {
7389                 status &= RTL_EVENT_NAPI | tp->event_slow;
7390                 if (status) {
7391                         handled = 1;
7392
7393                         rtl_irq_disable(tp);
7394                         napi_schedule(&tp->napi);
7395                 }
7396         }
7397         return IRQ_RETVAL(handled);
7398 }
7399
7400 /*
7401  * Workqueue context.
7402  */
7403 static void rtl_slow_event_work(struct rtl8169_private *tp)
7404 {
7405         struct net_device *dev = tp->dev;
7406         u16 status;
7407
7408         status = rtl_get_events(tp) & tp->event_slow;
7409         rtl_ack_events(tp, status);
7410
7411         if (unlikely(status & RxFIFOOver)) {
7412                 switch (tp->mac_version) {
7413                 /* Work around for rx fifo overflow */
7414                 case RTL_GIGA_MAC_VER_11:
7415                         netif_stop_queue(dev);
7416                         /* XXX - Hack alert. See rtl_task(). */
7417                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7418                 default:
7419                         break;
7420                 }
7421         }
7422
7423         if (unlikely(status & SYSErr))
7424                 rtl8169_pcierr_interrupt(dev);
7425
7426         if (status & LinkChg)
7427                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7428
7429         rtl_irq_enable_all(tp);
7430 }
7431
7432 static void rtl_task(struct work_struct *work)
7433 {
7434         static const struct {
7435                 int bitnr;
7436                 void (*action)(struct rtl8169_private *);
7437         } rtl_work[] = {
7438                 /* XXX - keep rtl_slow_event_work() as first element. */
7439                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
7440                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
7441                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
7442         };
7443         struct rtl8169_private *tp =
7444                 container_of(work, struct rtl8169_private, wk.work);
7445         struct net_device *dev = tp->dev;
7446         int i;
7447
7448         rtl_lock_work(tp);
7449
7450         if (!netif_running(dev) ||
7451             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7452                 goto out_unlock;
7453
7454         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7455                 bool pending;
7456
7457                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7458                 if (pending)
7459                         rtl_work[i].action(tp);
7460         }
7461
7462 out_unlock:
7463         rtl_unlock_work(tp);
7464 }
7465
7466 static int rtl8169_poll(struct napi_struct *napi, int budget)
7467 {
7468         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7469         struct net_device *dev = tp->dev;
7470         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7471         int work_done= 0;
7472         u16 status;
7473
7474         status = rtl_get_events(tp);
7475         rtl_ack_events(tp, status & ~tp->event_slow);
7476
7477         if (status & RTL_EVENT_NAPI_RX)
7478                 work_done = rtl_rx(dev, tp, (u32) budget);
7479
7480         if (status & RTL_EVENT_NAPI_TX)
7481                 rtl_tx(dev, tp);
7482
7483         if (status & tp->event_slow) {
7484                 enable_mask &= ~tp->event_slow;
7485
7486                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7487         }
7488
7489         if (work_done < budget) {
7490                 napi_complete(napi);
7491
7492                 rtl_irq_enable(tp, enable_mask);
7493                 mmiowb();
7494         }
7495
7496         return work_done;
7497 }
7498
7499 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7500 {
7501         struct rtl8169_private *tp = netdev_priv(dev);
7502
7503         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7504                 return;
7505
7506         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7507         RTL_W32(RxMissed, 0);
7508 }
7509
7510 static void rtl8169_down(struct net_device *dev)
7511 {
7512         struct rtl8169_private *tp = netdev_priv(dev);
7513         void __iomem *ioaddr = tp->mmio_addr;
7514
7515         del_timer_sync(&tp->timer);
7516
7517         napi_disable(&tp->napi);
7518         netif_stop_queue(dev);
7519
7520         rtl8169_hw_reset(tp);
7521         /*
7522          * At this point device interrupts can not be enabled in any function,
7523          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7524          * and napi is disabled (rtl8169_poll).
7525          */
7526         rtl8169_rx_missed(dev, ioaddr);
7527
7528         /* Give a racing hard_start_xmit a few cycles to complete. */
7529         synchronize_sched();
7530
7531         rtl8169_tx_clear(tp);
7532
7533         rtl8169_rx_clear(tp);
7534
7535         rtl_pll_power_down(tp);
7536 }
7537
7538 static int rtl8169_close(struct net_device *dev)
7539 {
7540         struct rtl8169_private *tp = netdev_priv(dev);
7541         struct pci_dev *pdev = tp->pci_dev;
7542
7543         pm_runtime_get_sync(&pdev->dev);
7544
7545         /* Update counters before going down */
7546         rtl8169_update_counters(dev);
7547
7548         rtl_lock_work(tp);
7549         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7550
7551         rtl8169_down(dev);
7552         rtl_unlock_work(tp);
7553
7554         cancel_work_sync(&tp->wk.work);
7555
7556         free_irq(pdev->irq, dev);
7557
7558         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7559                           tp->RxPhyAddr);
7560         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7561                           tp->TxPhyAddr);
7562         tp->TxDescArray = NULL;
7563         tp->RxDescArray = NULL;
7564
7565         pm_runtime_put_sync(&pdev->dev);
7566
7567         return 0;
7568 }
7569
7570 #ifdef CONFIG_NET_POLL_CONTROLLER
7571 static void rtl8169_netpoll(struct net_device *dev)
7572 {
7573         struct rtl8169_private *tp = netdev_priv(dev);
7574
7575         rtl8169_interrupt(tp->pci_dev->irq, dev);
7576 }
7577 #endif
7578
7579 static int rtl_open(struct net_device *dev)
7580 {
7581         struct rtl8169_private *tp = netdev_priv(dev);
7582         void __iomem *ioaddr = tp->mmio_addr;
7583         struct pci_dev *pdev = tp->pci_dev;
7584         int retval = -ENOMEM;
7585
7586         pm_runtime_get_sync(&pdev->dev);
7587
7588         /*
7589          * Rx and Tx descriptors needs 256 bytes alignment.
7590          * dma_alloc_coherent provides more.
7591          */
7592         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7593                                              &tp->TxPhyAddr, GFP_KERNEL);
7594         if (!tp->TxDescArray)
7595                 goto err_pm_runtime_put;
7596
7597         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7598                                              &tp->RxPhyAddr, GFP_KERNEL);
7599         if (!tp->RxDescArray)
7600                 goto err_free_tx_0;
7601
7602         retval = rtl8169_init_ring(dev);
7603         if (retval < 0)
7604                 goto err_free_rx_1;
7605
7606         INIT_WORK(&tp->wk.work, rtl_task);
7607
7608         smp_mb();
7609
7610         rtl_request_firmware(tp);
7611
7612         retval = request_irq(pdev->irq, rtl8169_interrupt,
7613                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7614                              dev->name, dev);
7615         if (retval < 0)
7616                 goto err_release_fw_2;
7617
7618         rtl_lock_work(tp);
7619
7620         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7621
7622         napi_enable(&tp->napi);
7623
7624         rtl8169_init_phy(dev, tp);
7625
7626         __rtl8169_set_features(dev, dev->features);
7627
7628         rtl_pll_power_up(tp);
7629
7630         rtl_hw_start(dev);
7631
7632         netif_start_queue(dev);
7633
7634         rtl_unlock_work(tp);
7635
7636         tp->saved_wolopts = 0;
7637         pm_runtime_put_noidle(&pdev->dev);
7638
7639         rtl8169_check_link_status(dev, tp, ioaddr);
7640 out:
7641         return retval;
7642
7643 err_release_fw_2:
7644         rtl_release_firmware(tp);
7645         rtl8169_rx_clear(tp);
7646 err_free_rx_1:
7647         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7648                           tp->RxPhyAddr);
7649         tp->RxDescArray = NULL;
7650 err_free_tx_0:
7651         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7652                           tp->TxPhyAddr);
7653         tp->TxDescArray = NULL;
7654 err_pm_runtime_put:
7655         pm_runtime_put_noidle(&pdev->dev);
7656         goto out;
7657 }
7658
7659 static struct rtnl_link_stats64 *
7660 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7661 {
7662         struct rtl8169_private *tp = netdev_priv(dev);
7663         void __iomem *ioaddr = tp->mmio_addr;
7664         unsigned int start;
7665
7666         if (netif_running(dev))
7667                 rtl8169_rx_missed(dev, ioaddr);
7668
7669         do {
7670                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7671                 stats->rx_packets = tp->rx_stats.packets;
7672                 stats->rx_bytes = tp->rx_stats.bytes;
7673         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7674
7675
7676         do {
7677                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7678                 stats->tx_packets = tp->tx_stats.packets;
7679                 stats->tx_bytes = tp->tx_stats.bytes;
7680         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7681
7682         stats->rx_dropped       = dev->stats.rx_dropped;
7683         stats->tx_dropped       = dev->stats.tx_dropped;
7684         stats->rx_length_errors = dev->stats.rx_length_errors;
7685         stats->rx_errors        = dev->stats.rx_errors;
7686         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
7687         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
7688         stats->rx_missed_errors = dev->stats.rx_missed_errors;
7689
7690         return stats;
7691 }
7692
7693 static void rtl8169_net_suspend(struct net_device *dev)
7694 {
7695         struct rtl8169_private *tp = netdev_priv(dev);
7696
7697         if (!netif_running(dev))
7698                 return;
7699
7700         netif_device_detach(dev);
7701         netif_stop_queue(dev);
7702
7703         rtl_lock_work(tp);
7704         napi_disable(&tp->napi);
7705         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7706         rtl_unlock_work(tp);
7707
7708         rtl_pll_power_down(tp);
7709 }
7710
7711 #ifdef CONFIG_PM
7712
7713 static int rtl8169_suspend(struct device *device)
7714 {
7715         struct pci_dev *pdev = to_pci_dev(device);
7716         struct net_device *dev = pci_get_drvdata(pdev);
7717
7718         rtl8169_net_suspend(dev);
7719
7720         return 0;
7721 }
7722
7723 static void __rtl8169_resume(struct net_device *dev)
7724 {
7725         struct rtl8169_private *tp = netdev_priv(dev);
7726
7727         netif_device_attach(dev);
7728
7729         rtl_pll_power_up(tp);
7730
7731         rtl_lock_work(tp);
7732         napi_enable(&tp->napi);
7733         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7734         rtl_unlock_work(tp);
7735
7736         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7737 }
7738
7739 static int rtl8169_resume(struct device *device)
7740 {
7741         struct pci_dev *pdev = to_pci_dev(device);
7742         struct net_device *dev = pci_get_drvdata(pdev);
7743         struct rtl8169_private *tp = netdev_priv(dev);
7744
7745         rtl8169_init_phy(dev, tp);
7746
7747         if (netif_running(dev))
7748                 __rtl8169_resume(dev);
7749
7750         return 0;
7751 }
7752
7753 static int rtl8169_runtime_suspend(struct device *device)
7754 {
7755         struct pci_dev *pdev = to_pci_dev(device);
7756         struct net_device *dev = pci_get_drvdata(pdev);
7757         struct rtl8169_private *tp = netdev_priv(dev);
7758
7759         if (!tp->TxDescArray)
7760                 return 0;
7761
7762         rtl_lock_work(tp);
7763         tp->saved_wolopts = __rtl8169_get_wol(tp);
7764         __rtl8169_set_wol(tp, WAKE_ANY);
7765         rtl_unlock_work(tp);
7766
7767         rtl8169_net_suspend(dev);
7768
7769         return 0;
7770 }
7771
7772 static int rtl8169_runtime_resume(struct device *device)
7773 {
7774         struct pci_dev *pdev = to_pci_dev(device);
7775         struct net_device *dev = pci_get_drvdata(pdev);
7776         struct rtl8169_private *tp = netdev_priv(dev);
7777
7778         if (!tp->TxDescArray)
7779                 return 0;
7780
7781         rtl_lock_work(tp);
7782         __rtl8169_set_wol(tp, tp->saved_wolopts);
7783         tp->saved_wolopts = 0;
7784         rtl_unlock_work(tp);
7785
7786         rtl8169_init_phy(dev, tp);
7787
7788         __rtl8169_resume(dev);
7789
7790         return 0;
7791 }
7792
7793 static int rtl8169_runtime_idle(struct device *device)
7794 {
7795         struct pci_dev *pdev = to_pci_dev(device);
7796         struct net_device *dev = pci_get_drvdata(pdev);
7797         struct rtl8169_private *tp = netdev_priv(dev);
7798
7799         return tp->TxDescArray ? -EBUSY : 0;
7800 }
7801
7802 static const struct dev_pm_ops rtl8169_pm_ops = {
7803         .suspend                = rtl8169_suspend,
7804         .resume                 = rtl8169_resume,
7805         .freeze                 = rtl8169_suspend,
7806         .thaw                   = rtl8169_resume,
7807         .poweroff               = rtl8169_suspend,
7808         .restore                = rtl8169_resume,
7809         .runtime_suspend        = rtl8169_runtime_suspend,
7810         .runtime_resume         = rtl8169_runtime_resume,
7811         .runtime_idle           = rtl8169_runtime_idle,
7812 };
7813
7814 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7815
7816 #else /* !CONFIG_PM */
7817
7818 #define RTL8169_PM_OPS  NULL
7819
7820 #endif /* !CONFIG_PM */
7821
7822 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7823 {
7824         void __iomem *ioaddr = tp->mmio_addr;
7825
7826         /* WoL fails with 8168b when the receiver is disabled. */
7827         switch (tp->mac_version) {
7828         case RTL_GIGA_MAC_VER_11:
7829         case RTL_GIGA_MAC_VER_12:
7830         case RTL_GIGA_MAC_VER_17:
7831                 pci_clear_master(tp->pci_dev);
7832
7833                 RTL_W8(ChipCmd, CmdRxEnb);
7834                 /* PCI commit */
7835                 RTL_R8(ChipCmd);
7836                 break;
7837         default:
7838                 break;
7839         }
7840 }
7841
7842 static void rtl_shutdown(struct pci_dev *pdev)
7843 {
7844         struct net_device *dev = pci_get_drvdata(pdev);
7845         struct rtl8169_private *tp = netdev_priv(dev);
7846         struct device *d = &pdev->dev;
7847
7848         pm_runtime_get_sync(d);
7849
7850         rtl8169_net_suspend(dev);
7851
7852         /* Restore original MAC address */
7853         rtl_rar_set(tp, dev->perm_addr);
7854
7855         rtl8169_hw_reset(tp);
7856
7857         if (system_state == SYSTEM_POWER_OFF) {
7858                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7859                         rtl_wol_suspend_quirk(tp);
7860                         rtl_wol_shutdown_quirk(tp);
7861                 }
7862
7863                 pci_wake_from_d3(pdev, true);
7864                 pci_set_power_state(pdev, PCI_D3hot);
7865         }
7866
7867         pm_runtime_put_noidle(d);
7868 }
7869
7870 static void rtl_remove_one(struct pci_dev *pdev)
7871 {
7872         struct net_device *dev = pci_get_drvdata(pdev);
7873         struct rtl8169_private *tp = netdev_priv(dev);
7874
7875         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7876              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7877              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
7878              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
7879              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
7880              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
7881             r8168_check_dash(tp)) {
7882                 rtl8168_driver_stop(tp);
7883         }
7884
7885         netif_napi_del(&tp->napi);
7886
7887         unregister_netdev(dev);
7888
7889         rtl_release_firmware(tp);
7890
7891         if (pci_dev_run_wake(pdev))
7892                 pm_runtime_get_noresume(&pdev->dev);
7893
7894         /* restore original MAC address */
7895         rtl_rar_set(tp, dev->perm_addr);
7896
7897         rtl_disable_msi(pdev, tp);
7898         rtl8169_release_board(pdev, dev, tp->mmio_addr);
7899 }
7900
7901 static const struct net_device_ops rtl_netdev_ops = {
7902         .ndo_open               = rtl_open,
7903         .ndo_stop               = rtl8169_close,
7904         .ndo_get_stats64        = rtl8169_get_stats64,
7905         .ndo_start_xmit         = rtl8169_start_xmit,
7906         .ndo_tx_timeout         = rtl8169_tx_timeout,
7907         .ndo_validate_addr      = eth_validate_addr,
7908         .ndo_change_mtu         = rtl8169_change_mtu,
7909         .ndo_fix_features       = rtl8169_fix_features,
7910         .ndo_set_features       = rtl8169_set_features,
7911         .ndo_set_mac_address    = rtl_set_mac_address,
7912         .ndo_do_ioctl           = rtl8169_ioctl,
7913         .ndo_set_rx_mode        = rtl_set_rx_mode,
7914 #ifdef CONFIG_NET_POLL_CONTROLLER
7915         .ndo_poll_controller    = rtl8169_netpoll,
7916 #endif
7917
7918 };
7919
7920 static const struct rtl_cfg_info {
7921         void (*hw_start)(struct net_device *);
7922         unsigned int region;
7923         unsigned int align;
7924         u16 event_slow;
7925         unsigned features;
7926         u8 default_ver;
7927 } rtl_cfg_infos [] = {
7928         [RTL_CFG_0] = {
7929                 .hw_start       = rtl_hw_start_8169,
7930                 .region         = 1,
7931                 .align          = 0,
7932                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7933                 .features       = RTL_FEATURE_GMII,
7934                 .default_ver    = RTL_GIGA_MAC_VER_01,
7935         },
7936         [RTL_CFG_1] = {
7937                 .hw_start       = rtl_hw_start_8168,
7938                 .region         = 2,
7939                 .align          = 8,
7940                 .event_slow     = SYSErr | LinkChg | RxOverflow,
7941                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
7942                 .default_ver    = RTL_GIGA_MAC_VER_11,
7943         },
7944         [RTL_CFG_2] = {
7945                 .hw_start       = rtl_hw_start_8101,
7946                 .region         = 2,
7947                 .align          = 8,
7948                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7949                                   PCSTimeout,
7950                 .features       = RTL_FEATURE_MSI,
7951                 .default_ver    = RTL_GIGA_MAC_VER_13,
7952         }
7953 };
7954
7955 /* Cfg9346_Unlock assumed. */
7956 static unsigned rtl_try_msi(struct rtl8169_private *tp,
7957                             const struct rtl_cfg_info *cfg)
7958 {
7959         void __iomem *ioaddr = tp->mmio_addr;
7960         unsigned msi = 0;
7961         u8 cfg2;
7962
7963         cfg2 = RTL_R8(Config2) & ~MSIEnable;
7964         if (cfg->features & RTL_FEATURE_MSI) {
7965                 if (pci_enable_msi(tp->pci_dev)) {
7966                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
7967                 } else {
7968                         cfg2 |= MSIEnable;
7969                         msi = RTL_FEATURE_MSI;
7970                 }
7971         }
7972         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
7973                 RTL_W8(Config2, cfg2);
7974         return msi;
7975 }
7976
7977 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7978 {
7979         void __iomem *ioaddr = tp->mmio_addr;
7980
7981         return RTL_R8(MCU) & LINK_LIST_RDY;
7982 }
7983
7984 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7985 {
7986         void __iomem *ioaddr = tp->mmio_addr;
7987
7988         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7989 }
7990
7991 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7992 {
7993         void __iomem *ioaddr = tp->mmio_addr;
7994         u32 data;
7995
7996         tp->ocp_base = OCP_STD_PHY_BASE;
7997
7998         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
7999
8000         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8001                 return;
8002
8003         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8004                 return;
8005
8006         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8007         msleep(1);
8008         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8009
8010         data = r8168_mac_ocp_read(tp, 0xe8de);
8011         data &= ~(1 << 14);
8012         r8168_mac_ocp_write(tp, 0xe8de, data);
8013
8014         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8015                 return;
8016
8017         data = r8168_mac_ocp_read(tp, 0xe8de);
8018         data |= (1 << 15);
8019         r8168_mac_ocp_write(tp, 0xe8de, data);
8020
8021         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8022                 return;
8023 }
8024
8025 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8026 {
8027         rtl8168ep_stop_cmac(tp);
8028         rtl_hw_init_8168g(tp);
8029 }
8030
8031 static void rtl_hw_initialize(struct rtl8169_private *tp)
8032 {
8033         switch (tp->mac_version) {
8034         case RTL_GIGA_MAC_VER_40:
8035         case RTL_GIGA_MAC_VER_41:
8036         case RTL_GIGA_MAC_VER_42:
8037         case RTL_GIGA_MAC_VER_43:
8038         case RTL_GIGA_MAC_VER_44:
8039         case RTL_GIGA_MAC_VER_45:
8040         case RTL_GIGA_MAC_VER_46:
8041         case RTL_GIGA_MAC_VER_47:
8042         case RTL_GIGA_MAC_VER_48:
8043                 rtl_hw_init_8168g(tp);
8044                 break;
8045         case RTL_GIGA_MAC_VER_49:
8046         case RTL_GIGA_MAC_VER_50:
8047         case RTL_GIGA_MAC_VER_51:
8048                 rtl_hw_init_8168ep(tp);
8049                 break;
8050         default:
8051                 break;
8052         }
8053 }
8054
8055 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8056 {
8057         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8058         const unsigned int region = cfg->region;
8059         struct rtl8169_private *tp;
8060         struct mii_if_info *mii;
8061         struct net_device *dev;
8062         void __iomem *ioaddr;
8063         int chipset, i;
8064         int rc;
8065
8066         if (netif_msg_drv(&debug)) {
8067                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8068                        MODULENAME, RTL8169_VERSION);
8069         }
8070
8071         dev = alloc_etherdev(sizeof (*tp));
8072         if (!dev) {
8073                 rc = -ENOMEM;
8074                 goto out;
8075         }
8076
8077         SET_NETDEV_DEV(dev, &pdev->dev);
8078         dev->netdev_ops = &rtl_netdev_ops;
8079         tp = netdev_priv(dev);
8080         tp->dev = dev;
8081         tp->pci_dev = pdev;
8082         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8083
8084         mii = &tp->mii;
8085         mii->dev = dev;
8086         mii->mdio_read = rtl_mdio_read;
8087         mii->mdio_write = rtl_mdio_write;
8088         mii->phy_id_mask = 0x1f;
8089         mii->reg_num_mask = 0x1f;
8090         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8091
8092         /* disable ASPM completely as that cause random device stop working
8093          * problems as well as full system hangs for some PCIe devices users */
8094         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8095                                      PCIE_LINK_STATE_CLKPM);
8096
8097         /* enable device (incl. PCI PM wakeup and hotplug setup) */
8098         rc = pci_enable_device(pdev);
8099         if (rc < 0) {
8100                 netif_err(tp, probe, dev, "enable failure\n");
8101                 goto err_out_free_dev_1;
8102         }
8103
8104         if (pci_set_mwi(pdev) < 0)
8105                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8106
8107         /* make sure PCI base addr 1 is MMIO */
8108         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8109                 netif_err(tp, probe, dev,
8110                           "region #%d not an MMIO resource, aborting\n",
8111                           region);
8112                 rc = -ENODEV;
8113                 goto err_out_mwi_2;
8114         }
8115
8116         /* check for weird/broken PCI region reporting */
8117         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8118                 netif_err(tp, probe, dev,
8119                           "Invalid PCI region size(s), aborting\n");
8120                 rc = -ENODEV;
8121                 goto err_out_mwi_2;
8122         }
8123
8124         rc = pci_request_regions(pdev, MODULENAME);
8125         if (rc < 0) {
8126                 netif_err(tp, probe, dev, "could not request regions\n");
8127                 goto err_out_mwi_2;
8128         }
8129
8130         tp->cp_cmd = 0;
8131
8132         if ((sizeof(dma_addr_t) > 4) &&
8133             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
8134                 tp->cp_cmd |= PCIDAC;
8135                 dev->features |= NETIF_F_HIGHDMA;
8136         } else {
8137                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8138                 if (rc < 0) {
8139                         netif_err(tp, probe, dev, "DMA configuration failed\n");
8140                         goto err_out_free_res_3;
8141                 }
8142         }
8143
8144         /* ioremap MMIO region */
8145         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8146         if (!ioaddr) {
8147                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8148                 rc = -EIO;
8149                 goto err_out_free_res_3;
8150         }
8151         tp->mmio_addr = ioaddr;
8152
8153         if (!pci_is_pcie(pdev))
8154                 netif_info(tp, probe, dev, "not PCI Express\n");
8155
8156         /* Identify chip attached to board */
8157         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8158
8159         rtl_init_rxcfg(tp);
8160
8161         rtl_irq_disable(tp);
8162
8163         rtl_hw_initialize(tp);
8164
8165         rtl_hw_reset(tp);
8166
8167         rtl_ack_events(tp, 0xffff);
8168
8169         pci_set_master(pdev);
8170
8171         rtl_init_mdio_ops(tp);
8172         rtl_init_pll_power_ops(tp);
8173         rtl_init_jumbo_ops(tp);
8174         rtl_init_csi_ops(tp);
8175
8176         rtl8169_print_mac_version(tp);
8177
8178         chipset = tp->mac_version;
8179         tp->txd_version = rtl_chip_infos[chipset].txd_version;
8180
8181         RTL_W8(Cfg9346, Cfg9346_Unlock);
8182         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8183         RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8184         switch (tp->mac_version) {
8185         case RTL_GIGA_MAC_VER_34:
8186         case RTL_GIGA_MAC_VER_35:
8187         case RTL_GIGA_MAC_VER_36:
8188         case RTL_GIGA_MAC_VER_37:
8189         case RTL_GIGA_MAC_VER_38:
8190         case RTL_GIGA_MAC_VER_40:
8191         case RTL_GIGA_MAC_VER_41:
8192         case RTL_GIGA_MAC_VER_42:
8193         case RTL_GIGA_MAC_VER_43:
8194         case RTL_GIGA_MAC_VER_44:
8195         case RTL_GIGA_MAC_VER_45:
8196         case RTL_GIGA_MAC_VER_46:
8197         case RTL_GIGA_MAC_VER_47:
8198         case RTL_GIGA_MAC_VER_48:
8199         case RTL_GIGA_MAC_VER_49:
8200         case RTL_GIGA_MAC_VER_50:
8201         case RTL_GIGA_MAC_VER_51:
8202                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8203                         tp->features |= RTL_FEATURE_WOL;
8204                 if ((RTL_R8(Config3) & LinkUp) != 0)
8205                         tp->features |= RTL_FEATURE_WOL;
8206                 break;
8207         default:
8208                 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8209                         tp->features |= RTL_FEATURE_WOL;
8210                 break;
8211         }
8212         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8213                 tp->features |= RTL_FEATURE_WOL;
8214         tp->features |= rtl_try_msi(tp, cfg);
8215         RTL_W8(Cfg9346, Cfg9346_Lock);
8216
8217         if (rtl_tbi_enabled(tp)) {
8218                 tp->set_speed = rtl8169_set_speed_tbi;
8219                 tp->get_settings = rtl8169_gset_tbi;
8220                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8221                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8222                 tp->link_ok = rtl8169_tbi_link_ok;
8223                 tp->do_ioctl = rtl_tbi_ioctl;
8224         } else {
8225                 tp->set_speed = rtl8169_set_speed_xmii;
8226                 tp->get_settings = rtl8169_gset_xmii;
8227                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8228                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8229                 tp->link_ok = rtl8169_xmii_link_ok;
8230                 tp->do_ioctl = rtl_xmii_ioctl;
8231         }
8232
8233         mutex_init(&tp->wk.mutex);
8234         u64_stats_init(&tp->rx_stats.syncp);
8235         u64_stats_init(&tp->tx_stats.syncp);
8236
8237         /* Get MAC address */
8238         if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8239             tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8240             tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8241             tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8242             tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8243             tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8244             tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8245             tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8246             tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8247             tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8248             tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8249             tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8250             tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8251             tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8252             tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8253             tp->mac_version == RTL_GIGA_MAC_VER_51) {
8254                 u16 mac_addr[3];
8255
8256                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8257                 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8258
8259                 if (is_valid_ether_addr((u8 *)mac_addr))
8260                         rtl_rar_set(tp, (u8 *)mac_addr);
8261         }
8262         for (i = 0; i < ETH_ALEN; i++)
8263                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8264
8265         dev->ethtool_ops = &rtl8169_ethtool_ops;
8266         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8267
8268         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8269
8270         /* don't enable SG, IP_CSUM and TSO by default - it might not work
8271          * properly for all devices */
8272         dev->features |= NETIF_F_RXCSUM |
8273                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8274
8275         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8276                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8277                 NETIF_F_HW_VLAN_CTAG_RX;
8278         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8279                 NETIF_F_HIGHDMA;
8280
8281         tp->cp_cmd |= RxChkSum | RxVlan;
8282
8283         /*
8284          * Pretend we are using VLANs; This bypasses a nasty bug where
8285          * Interrupts stop flowing on high load on 8110SCd controllers.
8286          */
8287         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8288                 /* Disallow toggling */
8289                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8290
8291         if (tp->txd_version == RTL_TD_0)
8292                 tp->tso_csum = rtl8169_tso_csum_v1;
8293         else if (tp->txd_version == RTL_TD_1) {
8294                 tp->tso_csum = rtl8169_tso_csum_v2;
8295                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8296         } else
8297                 WARN_ON_ONCE(1);
8298
8299         dev->hw_features |= NETIF_F_RXALL;
8300         dev->hw_features |= NETIF_F_RXFCS;
8301
8302         tp->hw_start = cfg->hw_start;
8303         tp->event_slow = cfg->event_slow;
8304
8305         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8306                 ~(RxBOVF | RxFOVF) : ~0;
8307
8308         init_timer(&tp->timer);
8309         tp->timer.data = (unsigned long) dev;
8310         tp->timer.function = rtl8169_phy_timer;
8311
8312         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8313
8314         rc = register_netdev(dev);
8315         if (rc < 0)
8316                 goto err_out_msi_4;
8317
8318         pci_set_drvdata(pdev, dev);
8319
8320         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8321                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8322                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8323         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8324                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8325                            "tx checksumming: %s]\n",
8326                            rtl_chip_infos[chipset].jumbo_max,
8327                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8328         }
8329
8330         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8331              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8332              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8333              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8334              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8335              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8336             r8168_check_dash(tp)) {
8337                 rtl8168_driver_start(tp);
8338         }
8339
8340         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8341
8342         if (pci_dev_run_wake(pdev))
8343                 pm_runtime_put_noidle(&pdev->dev);
8344
8345         netif_carrier_off(dev);
8346
8347 out:
8348         return rc;
8349
8350 err_out_msi_4:
8351         netif_napi_del(&tp->napi);
8352         rtl_disable_msi(pdev, tp);
8353         iounmap(ioaddr);
8354 err_out_free_res_3:
8355         pci_release_regions(pdev);
8356 err_out_mwi_2:
8357         pci_clear_mwi(pdev);
8358         pci_disable_device(pdev);
8359 err_out_free_dev_1:
8360         free_netdev(dev);
8361         goto out;
8362 }
8363
8364 static struct pci_driver rtl8169_pci_driver = {
8365         .name           = MODULENAME,
8366         .id_table       = rtl8169_pci_tbl,
8367         .probe          = rtl_init_one,
8368         .remove         = rtl_remove_one,
8369         .shutdown       = rtl_shutdown,
8370         .driver.pm      = RTL8169_PM_OPS,
8371 };
8372
8373 module_pci_driver(rtl8169_pci_driver);