kernel/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic_sriov.h"
   9 #include "qlcnic.h"
  10 #include "qlcnic_hw.h"
  11
  12 /* Reset template definitions */
  13 #define QLC_83XX_RESTART_TEMPLATE_SIZE          0x2000
  14 #define QLC_83XX_RESET_TEMPLATE_ADDR            0x4F0000
  15 #define QLC_83XX_RESET_SEQ_VERSION              0x0101
  16
  17 #define QLC_83XX_OPCODE_NOP                     0x0000
  18 #define QLC_83XX_OPCODE_WRITE_LIST              0x0001
  19 #define QLC_83XX_OPCODE_READ_WRITE_LIST         0x0002
  20 #define QLC_83XX_OPCODE_POLL_LIST               0x0004
  21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST         0x0008
  22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE       0x0010
  23 #define QLC_83XX_OPCODE_SEQ_PAUSE               0x0020
  24 #define QLC_83XX_OPCODE_SEQ_END                 0x0040
  25 #define QLC_83XX_OPCODE_TMPL_END                0x0080
  26 #define QLC_83XX_OPCODE_POLL_READ_LIST          0x0100
  27
  28 /* EPORT control registers */
  29 #define QLC_83XX_RESET_CONTROL                  0x28084E50
  30 #define QLC_83XX_RESET_REG                      0x28084E60
  31 #define QLC_83XX_RESET_PORT0                    0x28084E70
  32 #define QLC_83XX_RESET_PORT1                    0x28084E80
  33 #define QLC_83XX_RESET_PORT2                    0x28084E90
  34 #define QLC_83XX_RESET_PORT3                    0x28084EA0
  35 #define QLC_83XX_RESET_SRESHIM                  0x28084EB0
  36 #define QLC_83XX_RESET_EPGSHIM                  0x28084EC0
  37 #define QLC_83XX_RESET_ETHERPCS                 0x28084ED0
  38
  39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
  40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
  41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
  42 static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev);
  43 static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *);
  44 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *);
  45
  46 /* Template header */
  47 struct qlc_83xx_reset_hdr {
  48 #if defined(__LITTLE_ENDIAN)
  49         u16     version;
  50         u16     signature;
  51         u16     size;
  52         u16     entries;
  53         u16     hdr_size;
  54         u16     checksum;
  55         u16     init_offset;
  56         u16     start_offset;
  57 #elif defined(__BIG_ENDIAN)
  58         u16     signature;
  59         u16     version;
  60         u16     entries;
  61         u16     size;
  62         u16     checksum;
  63         u16     hdr_size;
  64         u16     start_offset;
  65         u16     init_offset;
  66 #endif
  67 } __packed;
  68
  69 /* Command entry header. */
  70 struct qlc_83xx_entry_hdr {
  71 #if defined(__LITTLE_ENDIAN)
  72         u16     cmd;
  73         u16     size;
  74         u16     count;
  75         u16     delay;
  76 #elif defined(__BIG_ENDIAN)
  77         u16     size;
  78         u16     cmd;
  79         u16     delay;
  80         u16     count;
  81 #endif
  82 } __packed;
  83
  84 /* Generic poll command */
  85 struct qlc_83xx_poll {
  86         u32     mask;
  87         u32     status;
  88 } __packed;
  89
  90 /* Read modify write command */
  91 struct qlc_83xx_rmw {
  92         u32     mask;
  93         u32     xor_value;
  94         u32     or_value;
  95 #if defined(__LITTLE_ENDIAN)
  96         u8      shl;
  97         u8      shr;
  98         u8      index_a;
  99         u8      rsvd;
 100 #elif defined(__BIG_ENDIAN)
 101         u8      rsvd;
 102         u8      index_a;
 103         u8      shr;
 104         u8      shl;
 105 #endif
 106 } __packed;
 107
 108 /* Generic command with 2 DWORD */
 109 struct qlc_83xx_entry {
 110         u32 arg1;
 111         u32 arg2;
 112 } __packed;
 113
 114 /* Generic command with 4 DWORD */
 115 struct qlc_83xx_quad_entry {
 116         u32 dr_addr;
 117         u32 dr_value;
 118         u32 ar_addr;
 119         u32 ar_value;
 120 } __packed;
 121 static const char *const qlc_83xx_idc_states[] = {
 122         "Unknown",
 123         "Cold",
 124         "Init",
 125         "Ready",
 126         "Need Reset",
 127         "Need Quiesce",
 128         "Failed",
 129         "Quiesce"
 130 };
 131
 132 static int
 133 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
 134 {
 135         u32 val;
 136
 137         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 138         if ((val & 0xFFFF))
 139                 return 1;
 140         else
 141                 return 0;
 142 }
 143
 144 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
 145 {
 146         u32 cur, prev;
 147         cur = adapter->ahw->idc.curr_state;
 148         prev = adapter->ahw->idc.prev_state;
 149
 150         dev_info(&adapter->pdev->dev,
 151                  "current state  = %s,  prev state = %s\n",
 152                  adapter->ahw->idc.name[cur],
 153                  adapter->ahw->idc.name[prev]);
 154 }
 155
 156 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
 157                                             u8 mode, int lock)
 158 {
 159         u32 val;
 160         int seconds;
 161
 162         if (lock) {
 163                 if (qlcnic_83xx_lock_driver(adapter))
 164                         return -EBUSY;
 165         }
 166
 167         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
 168         val |= (adapter->portnum & 0xf);
 169         val |= mode << 7;
 170         if (mode)
 171                 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 172         else
 173                 seconds = jiffies / HZ;
 174
 175         val |= seconds << 8;
 176         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
 177         adapter->ahw->idc.sec_counter = jiffies / HZ;
 178
 179         if (lock)
 180                 qlcnic_83xx_unlock_driver(adapter);
 181
 182         return 0;
 183 }
 184
 185 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
 186 {
 187         u32 val;
 188
 189         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
 190         val = val & ~(0x3 << (adapter->portnum * 2));
 191         val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
 192         QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
 193 }
 194
 195 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
 196                                                 int lock)
 197 {
 198         u32 val;
 199
 200         if (lock) {
 201                 if (qlcnic_83xx_lock_driver(adapter))
 202                         return -EBUSY;
 203         }
 204
 205         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 206         val = val & ~0xFF;
 207         val = val | QLC_83XX_IDC_MAJOR_VERSION;
 208         QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
 209
 210         if (lock)
 211                 qlcnic_83xx_unlock_driver(adapter);
 212
 213         return 0;
 214 }
 215
 216 static int
 217 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
 218                                         int status, int lock)
 219 {
 220         u32 val;
 221
 222         if (lock) {
 223                 if (qlcnic_83xx_lock_driver(adapter))
 224                         return -EBUSY;
 225         }
 226
 227         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 228
 229         if (status)
 230                 val = val | (1 << adapter->portnum);
 231         else
 232                 val = val & ~(1 << adapter->portnum);
 233
 234         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 235         qlcnic_83xx_idc_update_minor_version(adapter);
 236
 237         if (lock)
 238                 qlcnic_83xx_unlock_driver(adapter);
 239
 240         return 0;
 241 }
 242
 243 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
 244 {
 245         u32 val;
 246         u8 version;
 247
 248         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 249         version = val & 0xFF;
 250
 251         if (version != QLC_83XX_IDC_MAJOR_VERSION) {
 252                 dev_info(&adapter->pdev->dev,
 253                          "%s:mismatch. version 0x%x, expected version 0x%x\n",
 254                          __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
 255                 return -EIO;
 256         }
 257
 258         return 0;
 259 }
 260
 261 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
 262                                            int lock)
 263 {
 264         u32 val;
 265
 266         if (lock) {
 267                 if (qlcnic_83xx_lock_driver(adapter))
 268                         return -EBUSY;
 269         }
 270
 271         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
 272         /* Clear graceful reset bit */
 273         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 274         val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
 275         QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
 276
 277         if (lock)
 278                 qlcnic_83xx_unlock_driver(adapter);
 279
 280         return 0;
 281 }
 282
 283 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
 284                                               int flag, int lock)
 285 {
 286         u32 val;
 287
 288         if (lock) {
 289                 if (qlcnic_83xx_lock_driver(adapter))
 290                         return -EBUSY;
 291         }
 292
 293         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 294         if (flag)
 295                 val = val | (1 << adapter->portnum);
 296         else
 297                 val = val & ~(1 << adapter->portnum);
 298         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
 299
 300         if (lock)
 301                 qlcnic_83xx_unlock_driver(adapter);
 302
 303         return 0;
 304 }
 305
 306 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
 307                                          int time_limit)
 308 {
 309         u64 seconds;
 310
 311         seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 312         if (seconds <= time_limit)
 313                 return 0;
 314         else
 315                 return -EBUSY;
 316 }
 317
 318 /**
 319  * qlcnic_83xx_idc_check_reset_ack_reg
 320  *
 321  * @adapter: adapter structure
 322  *
 323  * Check ACK wait limit and clear the functions which failed to ACK
 324  *
 325  * Return 0 if all functions have acknowledged the reset request.
 326  **/
 327 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
 328 {
 329         int timeout;
 330         u32 ack, presence, val;
 331
 332         timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
 333         ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 334         presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 335         dev_info(&adapter->pdev->dev,
 336                  "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
 337         if (!((ack & presence) == presence)) {
 338                 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
 339                         /* Clear functions which failed to ACK */
 340                         dev_info(&adapter->pdev->dev,
 341                                  "%s: ACK wait exceeds time limit\n", __func__);
 342                         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 343                         val = val & ~(ack ^ presence);
 344                         if (qlcnic_83xx_lock_driver(adapter))
 345                                 return -EBUSY;
 346                         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 347                         dev_info(&adapter->pdev->dev,
 348                                  "%s: updated drv presence reg = 0x%x\n",
 349                                  __func__, val);
 350                         qlcnic_83xx_unlock_driver(adapter);
 351                         return 0;
 352
 353                 } else {
 354                         return 1;
 355                 }
 356         } else {
 357                 dev_info(&adapter->pdev->dev,
 358                          "%s: Reset ACK received from all functions\n",
 359                          __func__);
 360                 return 0;
 361         }
 362 }
 363
 364 /**
 365  * qlcnic_83xx_idc_tx_soft_reset
 366  *
 367  * @adapter: adapter structure
 368  *
 369  * Handle context deletion and recreation request from transmit routine
 370  *
 371  * Returns -EBUSY  or Success (0)
 372  *
 373  **/
 374 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
 375 {
 376         struct net_device *netdev = adapter->netdev;
 377
 378         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
 379                 return -EBUSY;
 380
 381         netif_device_detach(netdev);
 382         qlcnic_down(adapter, netdev);
 383         qlcnic_up(adapter, netdev);
 384         netif_device_attach(netdev);
 385         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 386         netdev_info(adapter->netdev, "%s: soft reset complete.\n", __func__);
 387
 388         return 0;
 389 }
 390
 391 /**
 392  * qlcnic_83xx_idc_detach_driver
 393  *
 394  * @adapter: adapter structure
 395  * Detach net interface, stop TX and cleanup resources before the HW reset.
 396  * Returns: None
 397  *
 398  **/
 399 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
 400 {
 401         int i;
 402         struct net_device *netdev = adapter->netdev;
 403
 404         netif_device_detach(netdev);
 405         qlcnic_83xx_detach_mailbox_work(adapter);
 406
 407         /* Disable mailbox interrupt */
 408         qlcnic_83xx_disable_mbx_intr(adapter);
 409         qlcnic_down(adapter, netdev);
 410         for (i = 0; i < adapter->ahw->num_msix; i++) {
 411                 adapter->ahw->intr_tbl[i].id = i;
 412                 adapter->ahw->intr_tbl[i].enabled = 0;
 413                 adapter->ahw->intr_tbl[i].src = 0;
 414         }
 415
 416         if (qlcnic_sriov_pf_check(adapter))
 417                 qlcnic_sriov_pf_reset(adapter);
 418 }
 419
 420 /**
 421  * qlcnic_83xx_idc_attach_driver
 422  *
 423  * @adapter: adapter structure
 424  *
 425  * Re-attach and re-enable net interface
 426  * Returns: None
 427  *
 428  **/
 429 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
 430 {
 431         struct net_device *netdev = adapter->netdev;
 432
 433         if (netif_running(netdev)) {
 434                 if (qlcnic_up(adapter, netdev))
 435                         goto done;
 436                 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
 437         }
 438 done:
 439         netif_device_attach(netdev);
 440 }
 441
 442 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
 443                                               int lock)
 444 {
 445         if (lock) {
 446                 if (qlcnic_83xx_lock_driver(adapter))
 447                         return -EBUSY;
 448         }
 449
 450         qlcnic_83xx_idc_clear_registers(adapter, 0);
 451         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
 452         if (lock)
 453                 qlcnic_83xx_unlock_driver(adapter);
 454
 455         qlcnic_83xx_idc_log_state_history(adapter);
 456         dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
 457
 458         return 0;
 459 }
 460
 461 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
 462                                             int lock)
 463 {
 464         if (lock) {
 465                 if (qlcnic_83xx_lock_driver(adapter))
 466                         return -EBUSY;
 467         }
 468
 469         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
 470
 471         if (lock)
 472                 qlcnic_83xx_unlock_driver(adapter);
 473
 474         return 0;
 475 }
 476
 477 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
 478                                               int lock)
 479 {
 480         if (lock) {
 481                 if (qlcnic_83xx_lock_driver(adapter))
 482                         return -EBUSY;
 483         }
 484
 485         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 486                QLC_83XX_IDC_DEV_NEED_QUISCENT);
 487
 488         if (lock)
 489                 qlcnic_83xx_unlock_driver(adapter);
 490
 491         return 0;
 492 }
 493
 494 static int
 495 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
 496 {
 497         if (lock) {
 498                 if (qlcnic_83xx_lock_driver(adapter))
 499                         return -EBUSY;
 500         }
 501
 502         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 503                QLC_83XX_IDC_DEV_NEED_RESET);
 504
 505         if (lock)
 506                 qlcnic_83xx_unlock_driver(adapter);
 507
 508         return 0;
 509 }
 510
 511 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
 512                                              int lock)
 513 {
 514         if (lock) {
 515                 if (qlcnic_83xx_lock_driver(adapter))
 516                         return -EBUSY;
 517         }
 518
 519         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
 520         if (lock)
 521                 qlcnic_83xx_unlock_driver(adapter);
 522
 523         return 0;
 524 }
 525
 526 /**
 527  * qlcnic_83xx_idc_find_reset_owner_id
 528  *
 529  * @adapter: adapter structure
 530  *
 531  * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
 532  * Within the same class, function with lowest PCI ID assumes ownership
 533  *
 534  * Returns: reset owner id or failure indication (-EIO)
 535  *
 536  **/
 537 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
 538 {
 539         u32 reg, reg1, reg2, i, j, owner, class;
 540
 541         reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
 542         reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
 543         owner = QLCNIC_TYPE_NIC;
 544         i = 0;
 545         j = 0;
 546         reg = reg1;
 547
 548         do {
 549                 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
 550                 if (class == owner)
 551                         break;
 552                 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
 553                         reg = reg2;
 554                         j = 0;
 555                 } else {
 556                         j++;
 557                 }
 558
 559                 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
 560                         if (owner == QLCNIC_TYPE_NIC)
 561                                 owner = QLCNIC_TYPE_ISCSI;
 562                         else if (owner == QLCNIC_TYPE_ISCSI)
 563                                 owner = QLCNIC_TYPE_FCOE;
 564                         else if (owner == QLCNIC_TYPE_FCOE)
 565                                 return -EIO;
 566                         reg = reg1;
 567                         j = 0;
 568                         i = 0;
 569                 }
 570         } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
 571
 572         return i;
 573 }
 574
 575 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
 576 {
 577         int ret = 0;
 578
 579         ret = qlcnic_83xx_restart_hw(adapter);
 580
 581         if (ret) {
 582                 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
 583         } else {
 584                 qlcnic_83xx_idc_clear_registers(adapter, lock);
 585                 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
 586         }
 587
 588         return ret;
 589 }
 590
 591 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
 592 {
 593         u32 status;
 594
 595         status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
 596
 597         if (status & QLCNIC_RCODE_FATAL_ERROR) {
 598                 dev_err(&adapter->pdev->dev,
 599                         "peg halt status1=0x%x\n", status);
 600                 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
 601                         dev_err(&adapter->pdev->dev,
 602                                 "On board active cooling fan failed. "
 603                                 "Device has been halted.\n");
 604                         dev_err(&adapter->pdev->dev,
 605                                 "Replace the adapter.\n");
 606                         return -EIO;
 607                 }
 608         }
 609
 610         return 0;
 611 }
 612
 613 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
 614 {
 615         int err;
 616
 617         qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
 618         qlcnic_83xx_enable_mbx_interrupt(adapter);
 619
 620         qlcnic_83xx_initialize_nic(adapter, 1);
 621
 622         err = qlcnic_sriov_pf_reinit(adapter);
 623         if (err)
 624                 return err;
 625
 626         qlcnic_83xx_enable_mbx_interrupt(adapter);
 627
 628         if (qlcnic_83xx_configure_opmode(adapter)) {
 629                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 630                 return -EIO;
 631         }
 632
 633         if (adapter->nic_ops->init_driver(adapter)) {
 634                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 635                 return -EIO;
 636         }
 637
 638         if (adapter->portnum == 0)
 639                 qlcnic_set_drv_version(adapter);
 640
 641         qlcnic_dcb_get_info(adapter->dcb);
 642         qlcnic_83xx_idc_attach_driver(adapter);
 643
 644         return 0;
 645 }
 646
 647 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
 648 {
 649         struct qlcnic_hardware_context *ahw = adapter->ahw;
 650
 651         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
 652         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 653         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
 654
 655         ahw->idc.quiesce_req = 0;
 656         ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
 657         ahw->idc.err_code = 0;
 658         ahw->idc.collect_dump = 0;
 659         ahw->reset_context = 0;
 660         adapter->tx_timeo_cnt = 0;
 661         ahw->idc.delay_reset = 0;
 662
 663         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 664 }
 665
 666 /**
 667  * qlcnic_83xx_idc_ready_state_entry
 668  *
 669  * @adapter: adapter structure
 670  *
 671  * Perform ready state initialization, this routine will get invoked only
 672  * once from READY state.
 673  *
 674  * Returns: Error code or Success(0)
 675  *
 676  **/
 677 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
 678 {
 679         struct qlcnic_hardware_context *ahw = adapter->ahw;
 680
 681         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
 682                 qlcnic_83xx_idc_update_idc_params(adapter);
 683                 /* Re-attach the device if required */
 684                 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
 685                     (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
 686                         if (qlcnic_83xx_idc_reattach_driver(adapter))
 687                                 return -EIO;
 688                 }
 689         }
 690
 691         return 0;
 692 }
 693
 694 /**
 695  * qlcnic_83xx_idc_vnic_pf_entry
 696  *
 697  * @adapter: adapter structure
 698  *
 699  * Ensure vNIC mode privileged function starts only after vNIC mode is
 700  * enabled by management function.
 701  * If vNIC mode is ready, start initialization.
 702  *
 703  * Returns: -EIO or 0
 704  *
 705  **/
 706 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
 707 {
 708         u32 state;
 709         struct qlcnic_hardware_context *ahw = adapter->ahw;
 710
 711         /* Privileged function waits till mgmt function enables VNIC mode */
 712         state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
 713         if (state != QLCNIC_DEV_NPAR_OPER) {
 714                 if (!ahw->idc.vnic_wait_limit--) {
 715                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 716                         return -EIO;
 717                 }
 718                 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
 719                 return -EIO;
 720
 721         } else {
 722                 /* Perform one time initialization from ready state */
 723                 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
 724                         qlcnic_83xx_idc_update_idc_params(adapter);
 725
 726                         /* If the previous state is UNKNOWN, device will be
 727                            already attached properly by Init routine*/
 728                         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
 729                                 if (qlcnic_83xx_idc_reattach_driver(adapter))
 730                                         return -EIO;
 731                         }
 732                         adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
 733                         dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
 734                 }
 735         }
 736
 737         return 0;
 738 }
 739
 740 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
 741 {
 742         adapter->ahw->idc.err_code = -EIO;
 743         dev_err(&adapter->pdev->dev,
 744                 "%s: Device in unknown state\n", __func__);
 745         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 746         return 0;
 747 }
 748
 749 /**
 750  * qlcnic_83xx_idc_cold_state
 751  *
 752  * @adapter: adapter structure
 753  *
 754  * If HW is up and running device will enter READY state.
 755  * If firmware image from host needs to be loaded, device is
 756  * forced to start with the file firmware image.
 757  *
 758  * Returns: Error code or Success(0)
 759  *
 760  **/
 761 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
 762 {
 763         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
 764         qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
 765
 766         if (qlcnic_load_fw_file) {
 767                 qlcnic_83xx_idc_restart_hw(adapter, 0);
 768         } else {
 769                 if (qlcnic_83xx_check_hw_status(adapter)) {
 770                         qlcnic_83xx_idc_enter_failed_state(adapter, 0);
 771                         return -EIO;
 772                 } else {
 773                         qlcnic_83xx_idc_enter_ready_state(adapter, 0);
 774                 }
 775         }
 776         return 0;
 777 }
 778
 779 /**
 780  * qlcnic_83xx_idc_init_state
 781  *
 782  * @adapter: adapter structure
 783  *
 784  * Reset owner will restart the device from this state.
 785  * Device will enter failed state if it remains
 786  * in this state for more than DEV_INIT time limit.
 787  *
 788  * Returns: Error code or Success(0)
 789  *
 790  **/
 791 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
 792 {
 793         int timeout, ret = 0;
 794         u32 owner;
 795
 796         timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
 797         if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
 798                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 799                 if (adapter->ahw->pci_func == owner)
 800                         ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
 801         } else {
 802                 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
 803         }
 804
 805         return ret;
 806 }
 807
 808 /**
 809  * qlcnic_83xx_idc_ready_state
 810  *
 811  * @adapter: adapter structure
 812  *
 813  * Perform IDC protocol specicifed actions after monitoring device state and
 814  * events.
 815  *
 816  * Returns: Error code or Success(0)
 817  *
 818  **/
 819 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
 820 {
 821         struct qlcnic_hardware_context *ahw = adapter->ahw;
 822         struct qlcnic_mailbox *mbx = ahw->mailbox;
 823         int ret = 0;
 824         u32 val;
 825
 826         /* Perform NIC configuration based ready state entry actions */
 827         if (ahw->idc.state_entry(adapter))
 828                 return -EIO;
 829
 830         if (qlcnic_check_temp(adapter)) {
 831                 if (ahw->temp == QLCNIC_TEMP_PANIC) {
 832                         qlcnic_83xx_idc_check_fan_failure(adapter);
 833                         dev_err(&adapter->pdev->dev,
 834                                 "Error: device temperature %d above limits\n",
 835                                 adapter->ahw->temp);
 836                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 837                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 838                         qlcnic_83xx_idc_detach_driver(adapter);
 839                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 840                         return -EIO;
 841                 }
 842         }
 843
 844         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 845         ret = qlcnic_83xx_check_heartbeat(adapter);
 846         if (ret) {
 847                 adapter->flags |= QLCNIC_FW_HANG;
 848                 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 849                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 850                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 851                         qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 852                 }  else {
 853                         netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n",
 854                                     __func__);
 855                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 856                 }
 857                 return -EIO;
 858         }
 859
 860         if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
 861                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 862
 863                 /* Move to need reset state and prepare for reset */
 864                 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 865                 return ret;
 866         }
 867
 868         /* Check for soft reset request */
 869         if (ahw->reset_context &&
 870             !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 871                 adapter->ahw->reset_context = 0;
 872                 qlcnic_83xx_idc_tx_soft_reset(adapter);
 873                 return ret;
 874         }
 875
 876         /* Move to need quiesce state if requested */
 877         if (adapter->ahw->idc.quiesce_req) {
 878                 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
 879                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 880                 return ret;
 881         }
 882
 883         return ret;
 884 }
 885
 886 /**
 887  * qlcnic_83xx_idc_need_reset_state
 888  *
 889  * @adapter: adapter structure
 890  *
 891  * Device will remain in this state until:
 892  *      Reset request ACK's are received from all the functions
 893  *      Wait time exceeds max time limit
 894  *
 895  * Returns: Error code or Success(0)
 896  *
 897  **/
 898 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
 899 {
 900         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 901         int ret = 0;
 902
 903         if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
 904                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 905                 set_bit(__QLCNIC_RESETTING, &adapter->state);
 906                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 907                 if (adapter->ahw->nic_mode == QLCNIC_VNIC_MODE)
 908                         qlcnic_83xx_disable_vnic_mode(adapter, 1);
 909
 910                 if (qlcnic_check_diag_status(adapter)) {
 911                         dev_info(&adapter->pdev->dev,
 912                                  "%s: Wait for diag completion\n", __func__);
 913                         adapter->ahw->idc.delay_reset = 1;
 914                         return 0;
 915                 } else {
 916                         qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 917                         qlcnic_83xx_idc_detach_driver(adapter);
 918                 }
 919         }
 920
 921         if (qlcnic_check_diag_status(adapter)) {
 922                 dev_info(&adapter->pdev->dev,
 923                          "%s: Wait for diag completion\n", __func__);
 924                 return  -1;
 925         } else {
 926                 if (adapter->ahw->idc.delay_reset) {
 927                         qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 928                         qlcnic_83xx_idc_detach_driver(adapter);
 929                         adapter->ahw->idc.delay_reset = 0;
 930                 }
 931
 932                 /* Check for ACK from other functions */
 933                 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
 934                 if (ret) {
 935                         dev_info(&adapter->pdev->dev,
 936                                  "%s: Waiting for reset ACK\n", __func__);
 937                         return -1;
 938                 }
 939         }
 940
 941         /* Transit to INIT state and restart the HW */
 942         qlcnic_83xx_idc_enter_init_state(adapter, 1);
 943
 944         return ret;
 945 }
 946
 947 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
 948 {
 949         dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
 950         return 0;
 951 }
 952
 953 static void qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
 954 {
 955         struct qlcnic_hardware_context *ahw = adapter->ahw;
 956         u32 val, owner;
 957
 958         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 959         if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) {
 960                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 961                 if (ahw->pci_func == owner) {
 962                         qlcnic_83xx_stop_hw(adapter);
 963                         qlcnic_dump_fw(adapter);
 964                 }
 965         }
 966
 967         netdev_warn(adapter->netdev, "%s: Reboot will be required to recover the adapter!!\n",
 968                     __func__);
 969         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 970         ahw->idc.err_code = -EIO;
 971
 972         return;
 973 }
 974
 975 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
 976 {
 977         dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
 978         return 0;
 979 }
 980
 981 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
 982                                                 u32 state)
 983 {
 984         u32 cur, prev, next;
 985
 986         cur = adapter->ahw->idc.curr_state;
 987         prev = adapter->ahw->idc.prev_state;
 988         next = state;
 989
 990         if ((next < QLC_83XX_IDC_DEV_COLD) ||
 991             (next > QLC_83XX_IDC_DEV_QUISCENT)) {
 992                 dev_err(&adapter->pdev->dev,
 993                         "%s: curr %d, prev %d, next state %d is  invalid\n",
 994                         __func__, cur, prev, state);
 995                 return 1;
 996         }
 997
 998         if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
 999             (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
1000                 if ((next != QLC_83XX_IDC_DEV_COLD) &&
1001                     (next != QLC_83XX_IDC_DEV_READY)) {
1002                         dev_err(&adapter->pdev->dev,
1003                                 "%s: failed, cur %d prev %d next %d\n",
1004                                 __func__, cur, prev, next);
1005                         return 1;
1006                 }
1007         }
1008
1009         if (next == QLC_83XX_IDC_DEV_INIT) {
1010                 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
1011                     (prev != QLC_83XX_IDC_DEV_COLD) &&
1012                     (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
1013                         dev_err(&adapter->pdev->dev,
1014                                 "%s: failed, cur %d prev %d next %d\n",
1015                                 __func__, cur, prev, next);
1016                         return 1;
1017                 }
1018         }
1019
1020         return 0;
1021 }
1022
1023 #ifdef CONFIG_QLCNIC_VXLAN
1024 #define QLC_83XX_ENCAP_TYPE_VXLAN       BIT_1
1025 #define QLC_83XX_MATCH_ENCAP_ID         BIT_2
1026 #define QLC_83XX_SET_VXLAN_UDP_DPORT    BIT_3
1027 #define QLC_83XX_VXLAN_UDP_DPORT(PORT)  ((PORT & 0xffff) << 16)
1028
1029 #define QLCNIC_ENABLE_INGRESS_ENCAP_PARSING 1
1030 #define QLCNIC_DISABLE_INGRESS_ENCAP_PARSING 0
1031
1032 static int qlcnic_set_vxlan_port(struct qlcnic_adapter *adapter)
1033 {
1034         u16 port = adapter->ahw->vxlan_port;
1035         struct qlcnic_cmd_args cmd;
1036         int ret = 0;
1037
1038         memset(&cmd, 0, sizeof(cmd));
1039
1040         ret = qlcnic_alloc_mbx_args(&cmd, adapter,
1041                                     QLCNIC_CMD_INIT_NIC_FUNC);
1042         if (ret)
1043                 return ret;
1044
1045         cmd.req.arg[1] = QLC_83XX_MULTI_TENANCY_INFO;
1046         cmd.req.arg[2] = QLC_83XX_ENCAP_TYPE_VXLAN |
1047                          QLC_83XX_SET_VXLAN_UDP_DPORT |
1048                          QLC_83XX_VXLAN_UDP_DPORT(port);
1049
1050         ret = qlcnic_issue_cmd(adapter, &cmd);
1051         if (ret)
1052                 netdev_err(adapter->netdev,
1053                            "Failed to set VXLAN port %d in adapter\n",
1054                            port);
1055
1056         qlcnic_free_mbx_args(&cmd);
1057
1058         return ret;
1059 }
1060
1061 static int qlcnic_set_vxlan_parsing(struct qlcnic_adapter *adapter,
1062                                     bool state)
1063 {
1064         u16 vxlan_port = adapter->ahw->vxlan_port;
1065         struct qlcnic_cmd_args cmd;
1066         int ret = 0;
1067
1068         memset(&cmd, 0, sizeof(cmd));
1069
1070         ret = qlcnic_alloc_mbx_args(&cmd, adapter,
1071                                     QLCNIC_CMD_SET_INGRESS_ENCAP);
1072         if (ret)
1073                 return ret;
1074
1075         cmd.req.arg[1] = state ? QLCNIC_ENABLE_INGRESS_ENCAP_PARSING :
1076                                  QLCNIC_DISABLE_INGRESS_ENCAP_PARSING;
1077
1078         ret = qlcnic_issue_cmd(adapter, &cmd);
1079         if (ret)
1080                 netdev_err(adapter->netdev,
1081                            "Failed to %s VXLAN parsing for port %d\n",
1082                            state ? "enable" : "disable", vxlan_port);
1083         else
1084                 netdev_info(adapter->netdev,
1085                             "%s VXLAN parsing for port %d\n",
1086                             state ? "Enabled" : "Disabled", vxlan_port);
1087
1088         qlcnic_free_mbx_args(&cmd);
1089
1090         return ret;
1091 }
1092 #endif
1093
1094 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
1095 {
1096         if (adapter->fhash.fnum)
1097                 qlcnic_prune_lb_filters(adapter);
1098
1099 #ifdef CONFIG_QLCNIC_VXLAN
1100         if (adapter->flags & QLCNIC_ADD_VXLAN_PORT) {
1101                 if (qlcnic_set_vxlan_port(adapter))
1102                         return;
1103
1104                 if (qlcnic_set_vxlan_parsing(adapter, true))
1105                         return;
1106
1107                 adapter->flags &= ~QLCNIC_ADD_VXLAN_PORT;
1108         } else if (adapter->flags & QLCNIC_DEL_VXLAN_PORT) {
1109                 if (qlcnic_set_vxlan_parsing(adapter, false))
1110                         return;
1111
1112                 adapter->ahw->vxlan_port = 0;
1113                 adapter->flags &= ~QLCNIC_DEL_VXLAN_PORT;
1114         }
1115 #endif
1116 }
1117
1118 /**
1119  * qlcnic_83xx_idc_poll_dev_state
1120  *
1121  * @work: kernel work queue structure used to schedule the function
1122  *
1123  * Poll device state periodically and perform state specific
1124  * actions defined by Inter Driver Communication (IDC) protocol.
1125  *
1126  * Returns: None
1127  *
1128  **/
1129 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1130 {
1131         struct qlcnic_adapter *adapter;
1132         u32 state;
1133
1134         adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1135         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1136
1137         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1138                 qlcnic_83xx_idc_log_state_history(adapter);
1139                 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1140         } else {
1141                 adapter->ahw->idc.curr_state = state;
1142         }
1143
1144         switch (adapter->ahw->idc.curr_state) {
1145         case QLC_83XX_IDC_DEV_READY:
1146                 qlcnic_83xx_idc_ready_state(adapter);
1147                 break;
1148         case QLC_83XX_IDC_DEV_NEED_RESET:
1149                 qlcnic_83xx_idc_need_reset_state(adapter);
1150                 break;
1151         case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1152                 qlcnic_83xx_idc_need_quiesce_state(adapter);
1153                 break;
1154         case QLC_83XX_IDC_DEV_FAILED:
1155                 qlcnic_83xx_idc_failed_state(adapter);
1156                 return;
1157         case QLC_83XX_IDC_DEV_INIT:
1158                 qlcnic_83xx_idc_init_state(adapter);
1159                 break;
1160         case QLC_83XX_IDC_DEV_QUISCENT:
1161                 qlcnic_83xx_idc_quiesce_state(adapter);
1162                 break;
1163         default:
1164                 qlcnic_83xx_idc_unknown_state(adapter);
1165                 return;
1166         }
1167         adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1168         qlcnic_83xx_periodic_tasks(adapter);
1169
1170         /* Re-schedule the function */
1171         if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1172                 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1173                                      adapter->ahw->idc.delay);
1174 }
1175
1176 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1177 {
1178         u32 idc_params, val;
1179
1180         if (qlcnic_83xx_flash_read32(adapter, QLC_83XX_IDC_FLASH_PARAM_ADDR,
1181                                      (u8 *)&idc_params, 1)) {
1182                 dev_info(&adapter->pdev->dev,
1183                          "%s:failed to get IDC params from flash\n", __func__);
1184                 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1185                 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1186         } else {
1187                 adapter->dev_init_timeo = idc_params & 0xFFFF;
1188                 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1189         }
1190
1191         adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1192         adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1193         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1194         adapter->ahw->idc.err_code = 0;
1195         adapter->ahw->idc.collect_dump = 0;
1196         adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1197
1198         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1199         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1200
1201         /* Check if reset recovery is disabled */
1202         if (!qlcnic_auto_fw_reset) {
1203                 /* Propagate do not reset request to other functions */
1204                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1205                 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1206                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1207         }
1208 }
1209
1210 static int
1211 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1212 {
1213         u32 state, val;
1214
1215         if (qlcnic_83xx_lock_driver(adapter))
1216                 return -EIO;
1217
1218         /* Clear driver lock register */
1219         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1220         if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1221                 qlcnic_83xx_unlock_driver(adapter);
1222                 return -EIO;
1223         }
1224
1225         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1226         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1227                 qlcnic_83xx_unlock_driver(adapter);
1228                 return -EIO;
1229         }
1230
1231         if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1232                 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1233                        QLC_83XX_IDC_DEV_COLD);
1234                 state = QLC_83XX_IDC_DEV_COLD;
1235         }
1236
1237         adapter->ahw->idc.curr_state = state;
1238         /* First to load function should cold boot the device */
1239         if (state == QLC_83XX_IDC_DEV_COLD)
1240                 qlcnic_83xx_idc_cold_state_handler(adapter);
1241
1242         /* Check if reset recovery is enabled */
1243         if (qlcnic_auto_fw_reset) {
1244                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1245                 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1246                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1247         }
1248
1249         qlcnic_83xx_unlock_driver(adapter);
1250
1251         return 0;
1252 }
1253
1254 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1255 {
1256         int ret = -EIO;
1257
1258         qlcnic_83xx_setup_idc_parameters(adapter);
1259
1260         if (qlcnic_83xx_get_reset_instruction_template(adapter))
1261                 return ret;
1262
1263         if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1264                 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1265                         return -EIO;
1266         } else {
1267                 if (qlcnic_83xx_idc_check_major_version(adapter))
1268                         return -EIO;
1269         }
1270
1271         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1272
1273         return 0;
1274 }
1275
1276 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1277 {
1278         int id;
1279         u32 val;
1280
1281         while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1282                 usleep_range(10000, 11000);
1283
1284         id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1285         id = id & 0xFF;
1286
1287         if (id == adapter->portnum) {
1288                 dev_err(&adapter->pdev->dev,
1289                         "%s: wait for lock recovery.. %d\n", __func__, id);
1290                 msleep(20);
1291                 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1292                 id = id & 0xFF;
1293         }
1294
1295         /* Clear driver presence bit */
1296         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1297         val = val & ~(1 << adapter->portnum);
1298         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1299         clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1300         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1301
1302         cancel_delayed_work_sync(&adapter->fw_work);
1303 }
1304
1305 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1306 {
1307         u32 val;
1308
1309         if (qlcnic_sriov_vf_check(adapter))
1310                 return;
1311
1312         if (qlcnic_83xx_lock_driver(adapter)) {
1313                 dev_err(&adapter->pdev->dev,
1314                         "%s:failed, please retry\n", __func__);
1315                 return;
1316         }
1317
1318         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1319         if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) {
1320                 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n",
1321                             __func__);
1322                 qlcnic_83xx_idc_enter_failed_state(adapter, 0);
1323                 qlcnic_83xx_unlock_driver(adapter);
1324                 return;
1325         }
1326
1327         if (key == QLCNIC_FORCE_FW_RESET) {
1328                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1329                 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1330                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1331         } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1332                 adapter->ahw->idc.collect_dump = 1;
1333         }
1334
1335         qlcnic_83xx_unlock_driver(adapter);
1336         return;
1337 }
1338
1339 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1340 {
1341         u8 *p_cache;
1342         u32 src, size;
1343         u64 dest;
1344         int ret = -EIO;
1345
1346         src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1347         dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1348         size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1349
1350         /* alignment check */
1351         if (size & 0xF)
1352                 size = (size + 16) & ~0xF;
1353
1354         p_cache = vzalloc(size);
1355         if (p_cache == NULL)
1356                 return -ENOMEM;
1357
1358         ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1359                                                 size / sizeof(u32));
1360         if (ret) {
1361                 vfree(p_cache);
1362                 return ret;
1363         }
1364         /* 16 byte write to MS memory */
1365         ret = qlcnic_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1366                                      size / 16);
1367         if (ret) {
1368                 vfree(p_cache);
1369                 return ret;
1370         }
1371         vfree(p_cache);
1372
1373         return ret;
1374 }
1375
1376 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1377 {
1378         struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
1379         const struct firmware *fw = fw_info->fw;
1380         u32 dest, *p_cache, *temp;
1381         int i, ret = -EIO;
1382         __le32 *temp_le;
1383         u8 data[16];
1384         size_t size;
1385         u64 addr;
1386
1387         temp = kzalloc(fw->size, GFP_KERNEL);
1388         if (!temp) {
1389                 release_firmware(fw);
1390                 fw_info->fw = NULL;
1391                 return -ENOMEM;
1392         }
1393
1394         temp_le = (__le32 *)fw->data;
1395
1396         /* FW image in file is in little endian, swap the data to nullify
1397          * the effect of writel() operation on big endian platform.
1398          */
1399         for (i = 0; i < fw->size / sizeof(u32); i++)
1400                 temp[i] = __le32_to_cpu(temp_le[i]);
1401
1402         dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1403         size = (fw->size & ~0xF);
1404         p_cache = temp;
1405         addr = (u64)dest;
1406
1407         ret = qlcnic_ms_mem_write128(adapter, addr,
1408                                      p_cache, size / 16);
1409         if (ret) {
1410                 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1411                 goto exit;
1412         }
1413
1414         /* alignment check */
1415         if (fw->size & 0xF) {
1416                 addr = dest + size;
1417                 for (i = 0; i < (fw->size & 0xF); i++)
1418                         data[i] = temp[size + i];
1419                 for (; i < 16; i++)
1420                         data[i] = 0;
1421                 ret = qlcnic_ms_mem_write128(adapter, addr,
1422                                              (u32 *)data, 1);
1423                 if (ret) {
1424                         dev_err(&adapter->pdev->dev,
1425                                 "MS memory write failed\n");
1426                         goto exit;
1427                 }
1428         }
1429
1430 exit:
1431         release_firmware(fw);
1432         fw_info->fw = NULL;
1433         kfree(temp);
1434
1435         return ret;
1436 }
1437
1438 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1439 {
1440         int i, j;
1441         u32 val = 0, val1 = 0, reg = 0;
1442         int err = 0;
1443
1444         val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err);
1445         if (err == -EIO)
1446                 return;
1447         dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1448
1449         for (j = 0; j < 2; j++) {
1450                 if (j == 0) {
1451                         dev_info(&adapter->pdev->dev,
1452                                  "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1453                         reg = QLC_83XX_PORT0_THRESHOLD;
1454                 } else if (j == 1) {
1455                         dev_info(&adapter->pdev->dev,
1456                                  "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1457                         reg = QLC_83XX_PORT1_THRESHOLD;
1458                 }
1459                 for (i = 0; i < 8; i++) {
1460                         val = QLCRD32(adapter, reg + (i * 0x4), &err);
1461                         if (err == -EIO)
1462                                 return;
1463                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1464                 }
1465                 dev_info(&adapter->pdev->dev, "\n");
1466         }
1467
1468         for (j = 0; j < 2; j++) {
1469                 if (j == 0) {
1470                         dev_info(&adapter->pdev->dev,
1471                                  "Port 0 RxB TC Max Cell Registers[4..1]:");
1472                         reg = QLC_83XX_PORT0_TC_MC_REG;
1473                 } else if (j == 1) {
1474                         dev_info(&adapter->pdev->dev,
1475                                  "Port 1 RxB TC Max Cell Registers[4..1]:");
1476                         reg = QLC_83XX_PORT1_TC_MC_REG;
1477                 }
1478                 for (i = 0; i < 4; i++) {
1479                         val = QLCRD32(adapter, reg + (i * 0x4), &err);
1480                         if (err == -EIO)
1481                                 return;
1482                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1483                 }
1484                 dev_info(&adapter->pdev->dev, "\n");
1485         }
1486
1487         for (j = 0; j < 2; j++) {
1488                 if (j == 0) {
1489                         dev_info(&adapter->pdev->dev,
1490                                  "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1491                         reg = QLC_83XX_PORT0_TC_STATS;
1492                 } else if (j == 1) {
1493                         dev_info(&adapter->pdev->dev,
1494                                  "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1495                         reg = QLC_83XX_PORT1_TC_STATS;
1496                 }
1497                 for (i = 7; i >= 0; i--) {
1498                         val = QLCRD32(adapter, reg, &err);
1499                         if (err == -EIO)
1500                                 return;
1501                         val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
1502                         QLCWR32(adapter, reg, (val | (i << 29)));
1503                         val = QLCRD32(adapter, reg, &err);
1504                         if (err == -EIO)
1505                                 return;
1506                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1507                 }
1508                 dev_info(&adapter->pdev->dev, "\n");
1509         }
1510
1511         val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err);
1512         if (err == -EIO)
1513                 return;
1514         val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err);
1515         if (err == -EIO)
1516                 return;
1517         dev_info(&adapter->pdev->dev,
1518                  "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1519                  val, val1);
1520 }
1521
1522
1523 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1524 {
1525         u32 reg = 0, i, j;
1526
1527         if (qlcnic_83xx_lock_driver(adapter)) {
1528                 dev_err(&adapter->pdev->dev,
1529                         "%s:failed to acquire driver lock\n", __func__);
1530                 return;
1531         }
1532
1533         qlcnic_83xx_dump_pause_control_regs(adapter);
1534         QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1535
1536         for (j = 0; j < 2; j++) {
1537                 if (j == 0)
1538                         reg = QLC_83XX_PORT0_THRESHOLD;
1539                 else if (j == 1)
1540                         reg = QLC_83XX_PORT1_THRESHOLD;
1541
1542                 for (i = 0; i < 8; i++)
1543                         QLCWR32(adapter, reg + (i * 0x4), 0x0);
1544         }
1545
1546         for (j = 0; j < 2; j++) {
1547                 if (j == 0)
1548                         reg = QLC_83XX_PORT0_TC_MC_REG;
1549                 else if (j == 1)
1550                         reg = QLC_83XX_PORT1_TC_MC_REG;
1551
1552                 for (i = 0; i < 4; i++)
1553                         QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1554         }
1555
1556         QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1557         QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1558         dev_info(&adapter->pdev->dev,
1559                  "Disabled pause frames successfully on all ports\n");
1560         qlcnic_83xx_unlock_driver(adapter);
1561 }
1562
1563 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1564 {
1565         QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1566         QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1567         QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1568         QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1569         QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1570         QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1571         QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1572         QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1573         QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1574 }
1575
1576 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1577 {
1578         u32 heartbeat, peg_status;
1579         int retries, ret = -EIO, err = 0;
1580
1581         retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1582         p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1583                                                QLCNIC_PEG_ALIVE_COUNTER);
1584
1585         do {
1586                 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1587                 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1588                                                 QLCNIC_PEG_ALIVE_COUNTER);
1589                 if (heartbeat != p_dev->heartbeat) {
1590                         ret = QLCNIC_RCODE_SUCCESS;
1591                         break;
1592                 }
1593         } while (--retries);
1594
1595         if (ret) {
1596                 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1597                 qlcnic_83xx_take_eport_out_of_reset(p_dev);
1598                 qlcnic_83xx_disable_pause_frames(p_dev);
1599                 peg_status = QLC_SHARED_REG_RD32(p_dev,
1600                                                  QLCNIC_PEG_HALT_STATUS1);
1601                 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1602                          "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1603                          "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1604                          "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1605                          "PEG_NET_4_PC: 0x%x\n", peg_status,
1606                          QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1607                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err),
1608                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err),
1609                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err),
1610                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err),
1611                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err));
1612
1613                 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1614                         dev_err(&p_dev->pdev->dev,
1615                                 "Device is being reset err code 0x00006700.\n");
1616         }
1617
1618         return ret;
1619 }
1620
1621 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1622 {
1623         int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1624         u32 val;
1625
1626         do {
1627                 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1628                 if (val == QLC_83XX_CMDPEG_COMPLETE)
1629                         return 0;
1630                 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1631         } while (--retries);
1632
1633         dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1634         return -EIO;
1635 }
1636
1637 static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1638 {
1639         int err;
1640
1641         err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1642         if (err)
1643                 return err;
1644
1645         err = qlcnic_83xx_check_heartbeat(p_dev);
1646         if (err)
1647                 return err;
1648
1649         return err;
1650 }
1651
1652 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1653                                 int duration, u32 mask, u32 status)
1654 {
1655         int timeout_error, err = 0;
1656         u32 value;
1657         u8 retries;
1658
1659         value = QLCRD32(p_dev, addr, &err);
1660         if (err == -EIO)
1661                 return err;
1662         retries = duration / 10;
1663
1664         do {
1665                 if ((value & mask) != status) {
1666                         timeout_error = 1;
1667                         msleep(duration / 10);
1668                         value = QLCRD32(p_dev, addr, &err);
1669                         if (err == -EIO)
1670                                 return err;
1671                 } else {
1672                         timeout_error = 0;
1673                         break;
1674                 }
1675         } while (retries--);
1676
1677         if (timeout_error) {
1678                 p_dev->ahw->reset.seq_error++;
1679                 dev_err(&p_dev->pdev->dev,
1680                         "%s: Timeout Err, entry_num = %d\n",
1681                         __func__, p_dev->ahw->reset.seq_index);
1682                 dev_err(&p_dev->pdev->dev,
1683                         "0x%08x 0x%08x 0x%08x\n",
1684                         value, mask, status);
1685         }
1686
1687         return timeout_error;
1688 }
1689
1690 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1691 {
1692         u32 sum = 0;
1693         u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1694         int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1695
1696         while (count-- > 0)
1697                 sum += *buff++;
1698
1699         while (sum >> 16)
1700                 sum = (sum & 0xFFFF) + (sum >> 16);
1701
1702         if (~sum) {
1703                 return 0;
1704         } else {
1705                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1706                 return -1;
1707         }
1708 }
1709
1710 static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1711 {
1712         struct qlcnic_hardware_context *ahw = p_dev->ahw;
1713         u32 addr, count, prev_ver, curr_ver;
1714         u8 *p_buff;
1715
1716         if (ahw->reset.buff != NULL) {
1717                 prev_ver = p_dev->fw_version;
1718                 curr_ver = qlcnic_83xx_get_fw_version(p_dev);
1719                 if (curr_ver > prev_ver)
1720                         kfree(ahw->reset.buff);
1721                 else
1722                         return 0;
1723         }
1724
1725         ahw->reset.seq_error = 0;
1726         ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1727         if (p_dev->ahw->reset.buff == NULL)
1728                 return -ENOMEM;
1729
1730         p_buff = p_dev->ahw->reset.buff;
1731         addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1732         count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1733
1734         /* Copy template header from flash */
1735         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1736                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1737                 return -EIO;
1738         }
1739         ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1740         addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1741         p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1742         count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1743
1744         /* Copy rest of the template */
1745         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1746                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1747                 return -EIO;
1748         }
1749
1750         if (qlcnic_83xx_reset_template_checksum(p_dev))
1751                 return -EIO;
1752         /* Get Stop, Start and Init command offsets */
1753         ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1754         ahw->reset.start_offset = ahw->reset.buff +
1755                                   ahw->reset.hdr->start_offset;
1756         ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1757         return 0;
1758 }
1759
1760 /* Read Write HW register command */
1761 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1762                                            u32 raddr, u32 waddr)
1763 {
1764         int err = 0;
1765         u32 value;
1766
1767         value = QLCRD32(p_dev, raddr, &err);
1768         if (err == -EIO)
1769                 return;
1770         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1771 }
1772
1773 /* Read Modify Write HW register command */
1774 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1775                                     u32 raddr, u32 waddr,
1776                                     struct qlc_83xx_rmw *p_rmw_hdr)
1777 {
1778         int err = 0;
1779         u32 value;
1780
1781         if (p_rmw_hdr->index_a) {
1782                 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1783         } else {
1784                 value = QLCRD32(p_dev, raddr, &err);
1785                 if (err == -EIO)
1786                         return;
1787         }
1788
1789         value &= p_rmw_hdr->mask;
1790         value <<= p_rmw_hdr->shl;
1791         value >>= p_rmw_hdr->shr;
1792         value |= p_rmw_hdr->or_value;
1793         value ^= p_rmw_hdr->xor_value;
1794         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1795 }
1796
1797 /* Write HW register command */
1798 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1799                                    struct qlc_83xx_entry_hdr *p_hdr)
1800 {
1801         int i;
1802         struct qlc_83xx_entry *entry;
1803
1804         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1805                                           sizeof(struct qlc_83xx_entry_hdr));
1806
1807         for (i = 0; i < p_hdr->count; i++, entry++) {
1808                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1809                                              entry->arg2);
1810                 if (p_hdr->delay)
1811                         udelay((u32)(p_hdr->delay));
1812         }
1813 }
1814
1815 /* Read and Write instruction */
1816 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1817                                         struct qlc_83xx_entry_hdr *p_hdr)
1818 {
1819         int i;
1820         struct qlc_83xx_entry *entry;
1821
1822         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1823                                           sizeof(struct qlc_83xx_entry_hdr));
1824
1825         for (i = 0; i < p_hdr->count; i++, entry++) {
1826                 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1827                                                entry->arg2);
1828                 if (p_hdr->delay)
1829                         udelay((u32)(p_hdr->delay));
1830         }
1831 }
1832
1833 /* Poll HW register command */
1834 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1835                                   struct qlc_83xx_entry_hdr *p_hdr)
1836 {
1837         long delay;
1838         struct qlc_83xx_entry *entry;
1839         struct qlc_83xx_poll *poll;
1840         int i, err = 0;
1841         unsigned long arg1, arg2;
1842
1843         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1844                                         sizeof(struct qlc_83xx_entry_hdr));
1845
1846         entry = (struct qlc_83xx_entry *)((char *)poll +
1847                                           sizeof(struct qlc_83xx_poll));
1848         delay = (long)p_hdr->delay;
1849
1850         if (!delay) {
1851                 for (i = 0; i < p_hdr->count; i++, entry++)
1852                         qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1853                                              delay, poll->mask,
1854                                              poll->status);
1855         } else {
1856                 for (i = 0; i < p_hdr->count; i++, entry++) {
1857                         arg1 = entry->arg1;
1858                         arg2 = entry->arg2;
1859                         if (delay) {
1860                                 if (qlcnic_83xx_poll_reg(p_dev,
1861                                                          arg1, delay,
1862                                                          poll->mask,
1863                                                          poll->status)){
1864                                         QLCRD32(p_dev, arg1, &err);
1865                                         if (err == -EIO)
1866                                                 return;
1867                                         QLCRD32(p_dev, arg2, &err);
1868                                         if (err == -EIO)
1869                                                 return;
1870                                 }
1871                         }
1872                 }
1873         }
1874 }
1875
1876 /* Poll and write HW register command */
1877 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1878                                         struct qlc_83xx_entry_hdr *p_hdr)
1879 {
1880         int i;
1881         long delay;
1882         struct qlc_83xx_quad_entry *entry;
1883         struct qlc_83xx_poll *poll;
1884
1885         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1886                                         sizeof(struct qlc_83xx_entry_hdr));
1887         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1888                                                sizeof(struct qlc_83xx_poll));
1889         delay = (long)p_hdr->delay;
1890
1891         for (i = 0; i < p_hdr->count; i++, entry++) {
1892                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1893                                              entry->dr_value);
1894                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1895                                              entry->ar_value);
1896                 if (delay)
1897                         qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1898                                              poll->mask, poll->status);
1899         }
1900 }
1901
1902 /* Read Modify Write register command */
1903 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1904                                           struct qlc_83xx_entry_hdr *p_hdr)
1905 {
1906         int i;
1907         struct qlc_83xx_entry *entry;
1908         struct qlc_83xx_rmw *rmw_hdr;
1909
1910         rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1911                                           sizeof(struct qlc_83xx_entry_hdr));
1912
1913         entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1914                                           sizeof(struct qlc_83xx_rmw));
1915
1916         for (i = 0; i < p_hdr->count; i++, entry++) {
1917                 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1918                                         entry->arg2, rmw_hdr);
1919                 if (p_hdr->delay)
1920                         udelay((u32)(p_hdr->delay));
1921         }
1922 }
1923
1924 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1925 {
1926         if (p_hdr->delay)
1927                 mdelay((u32)((long)p_hdr->delay));
1928 }
1929
1930 /* Read and poll register command */
1931 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1932                                        struct qlc_83xx_entry_hdr *p_hdr)
1933 {
1934         long delay;
1935         int index, i, j, err;
1936         struct qlc_83xx_quad_entry *entry;
1937         struct qlc_83xx_poll *poll;
1938         unsigned long addr;
1939
1940         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1941                                         sizeof(struct qlc_83xx_entry_hdr));
1942
1943         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1944                                                sizeof(struct qlc_83xx_poll));
1945         delay = (long)p_hdr->delay;
1946
1947         for (i = 0; i < p_hdr->count; i++, entry++) {
1948                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1949                                              entry->ar_value);
1950                 if (delay) {
1951                         if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1952                                                   poll->mask, poll->status)){
1953                                 index = p_dev->ahw->reset.array_index;
1954                                 addr = entry->dr_addr;
1955                                 j = QLCRD32(p_dev, addr, &err);
1956                                 if (err == -EIO)
1957                                         return;
1958
1959                                 p_dev->ahw->reset.array[index++] = j;
1960
1961                                 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1962                                         p_dev->ahw->reset.array_index = 1;
1963                         }
1964                 }
1965         }
1966 }
1967
1968 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1969 {
1970         p_dev->ahw->reset.seq_end = 1;
1971 }
1972
1973 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1974 {
1975         p_dev->ahw->reset.template_end = 1;
1976         if (p_dev->ahw->reset.seq_error == 0)
1977                 dev_err(&p_dev->pdev->dev,
1978                         "HW restart process completed successfully.\n");
1979         else
1980                 dev_err(&p_dev->pdev->dev,
1981                         "HW restart completed with timeout errors.\n");
1982 }
1983
1984 /**
1985 * qlcnic_83xx_exec_template_cmd
1986 *
1987 * @p_dev: adapter structure
1988 * @p_buff: Poiter to instruction template
1989 *
1990 * Template provides instructions to stop, restart and initalize firmware.
1991 * These instructions are abstracted as a series of read, write and
1992 * poll operations on hardware registers. Register information and operation
1993 * specifics are not exposed to the driver. Driver reads the template from
1994 * flash and executes the instructions located at pre-defined offsets.
1995 *
1996 * Returns: None
1997 * */
1998 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1999                                           char *p_buff)
2000 {
2001         int index, entries;
2002         struct qlc_83xx_entry_hdr *p_hdr;
2003         char *entry = p_buff;
2004
2005         p_dev->ahw->reset.seq_end = 0;
2006         p_dev->ahw->reset.template_end = 0;
2007         entries = p_dev->ahw->reset.hdr->entries;
2008         index = p_dev->ahw->reset.seq_index;
2009
2010         for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
2011                 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
2012
2013                 switch (p_hdr->cmd) {
2014                 case QLC_83XX_OPCODE_NOP:
2015                         break;
2016                 case QLC_83XX_OPCODE_WRITE_LIST:
2017                         qlcnic_83xx_write_list(p_dev, p_hdr);
2018                         break;
2019                 case QLC_83XX_OPCODE_READ_WRITE_LIST:
2020                         qlcnic_83xx_read_write_list(p_dev, p_hdr);
2021                         break;
2022                 case QLC_83XX_OPCODE_POLL_LIST:
2023                         qlcnic_83xx_poll_list(p_dev, p_hdr);
2024                         break;
2025                 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
2026                         qlcnic_83xx_poll_write_list(p_dev, p_hdr);
2027                         break;
2028                 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
2029                         qlcnic_83xx_read_modify_write(p_dev, p_hdr);
2030                         break;
2031                 case QLC_83XX_OPCODE_SEQ_PAUSE:
2032                         qlcnic_83xx_pause(p_hdr);
2033                         break;
2034                 case QLC_83XX_OPCODE_SEQ_END:
2035                         qlcnic_83xx_seq_end(p_dev);
2036                         break;
2037                 case QLC_83XX_OPCODE_TMPL_END:
2038                         qlcnic_83xx_template_end(p_dev);
2039                         break;
2040                 case QLC_83XX_OPCODE_POLL_READ_LIST:
2041                         qlcnic_83xx_poll_read_list(p_dev, p_hdr);
2042                         break;
2043                 default:
2044                         dev_err(&p_dev->pdev->dev,
2045                                 "%s: Unknown opcode 0x%04x in template %d\n",
2046                                 __func__, p_hdr->cmd, index);
2047                         break;
2048                 }
2049                 entry += p_hdr->size;
2050         }
2051         p_dev->ahw->reset.seq_index = index;
2052 }
2053
2054 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
2055 {
2056         p_dev->ahw->reset.seq_index = 0;
2057
2058         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
2059         if (p_dev->ahw->reset.seq_end != 1)
2060                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
2061 }
2062
2063 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
2064 {
2065         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
2066         if (p_dev->ahw->reset.template_end != 1)
2067                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
2068 }
2069
2070 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
2071 {
2072         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
2073         if (p_dev->ahw->reset.seq_end != 1)
2074                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
2075 }
2076
2077 /* POST FW related definations*/
2078 #define QLC_83XX_POST_SIGNATURE_REG     0x41602014
2079 #define QLC_83XX_POST_MODE_REG          0x41602018
2080 #define QLC_83XX_POST_FAST_MODE         0
2081 #define QLC_83XX_POST_MEDIUM_MODE       1
2082 #define QLC_83XX_POST_SLOW_MODE         2
2083
2084 /* POST Timeout values in milliseconds */
2085 #define QLC_83XX_POST_FAST_MODE_TIMEOUT 690
2086 #define QLC_83XX_POST_MED_MODE_TIMEOUT  2930
2087 #define QLC_83XX_POST_SLOW_MODE_TIMEOUT 7500
2088
2089 /* POST result values */
2090 #define QLC_83XX_POST_PASS                      0xfffffff0
2091 #define QLC_83XX_POST_ASIC_STRESS_TEST_FAIL     0xffffffff
2092 #define QLC_83XX_POST_DDR_TEST_FAIL             0xfffffffe
2093 #define QLC_83XX_POST_ASIC_MEMORY_TEST_FAIL     0xfffffffc
2094 #define QLC_83XX_POST_FLASH_TEST_FAIL           0xfffffff8
2095
2096 static int qlcnic_83xx_run_post(struct qlcnic_adapter *adapter)
2097 {
2098         struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
2099         struct device *dev = &adapter->pdev->dev;
2100         int timeout, count, ret = 0;
2101         u32 signature;
2102
2103         /* Set timeout values with extra 2 seconds of buffer */
2104         switch (adapter->ahw->post_mode) {
2105         case QLC_83XX_POST_FAST_MODE:
2106                 timeout = QLC_83XX_POST_FAST_MODE_TIMEOUT + 2000;
2107                 break;
2108         case QLC_83XX_POST_MEDIUM_MODE:
2109                 timeout = QLC_83XX_POST_MED_MODE_TIMEOUT + 2000;
2110                 break;
2111         case QLC_83XX_POST_SLOW_MODE:
2112                 timeout = QLC_83XX_POST_SLOW_MODE_TIMEOUT + 2000;
2113                 break;
2114         default:
2115                 return -EINVAL;
2116         }
2117
2118         strncpy(fw_info->fw_file_name, QLC_83XX_POST_FW_FILE_NAME,
2119                 QLC_FW_FILE_NAME_LEN);
2120
2121         ret = request_firmware(&fw_info->fw, fw_info->fw_file_name, dev);
2122         if (ret) {
2123                 dev_err(dev, "POST firmware can not be loaded, skipping POST\n");
2124                 return 0;
2125         }
2126
2127         ret = qlcnic_83xx_copy_fw_file(adapter);
2128         if (ret)
2129                 return ret;
2130
2131         /* clear QLC_83XX_POST_SIGNATURE_REG register */
2132         qlcnic_ind_wr(adapter, QLC_83XX_POST_SIGNATURE_REG, 0);
2133
2134         /* Set POST mode */
2135         qlcnic_ind_wr(adapter, QLC_83XX_POST_MODE_REG,
2136                       adapter->ahw->post_mode);
2137
2138         QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2139                             QLC_83XX_BOOT_FROM_FILE);
2140
2141         qlcnic_83xx_start_hw(adapter);
2142
2143         count = 0;
2144         do {
2145                 msleep(100);
2146                 count += 100;
2147
2148                 signature = qlcnic_ind_rd(adapter, QLC_83XX_POST_SIGNATURE_REG);
2149                 if (signature == QLC_83XX_POST_PASS)
2150                         break;
2151         } while (timeout > count);
2152
2153         if (timeout <= count) {
2154                 dev_err(dev, "POST timed out, signature = 0x%08x\n", signature);
2155                 return -EIO;
2156         }
2157
2158         switch (signature) {
2159         case QLC_83XX_POST_PASS:
2160                 dev_info(dev, "POST passed, Signature = 0x%08x\n", signature);
2161                 break;
2162         case QLC_83XX_POST_ASIC_STRESS_TEST_FAIL:
2163                 dev_err(dev, "POST failed, Test case : ASIC STRESS TEST, Signature = 0x%08x\n",
2164                         signature);
2165                 ret = -EIO;
2166                 break;
2167         case QLC_83XX_POST_DDR_TEST_FAIL:
2168                 dev_err(dev, "POST failed, Test case : DDT TEST, Signature = 0x%08x\n",
2169                         signature);
2170                 ret = -EIO;
2171                 break;
2172         case QLC_83XX_POST_ASIC_MEMORY_TEST_FAIL:
2173                 dev_err(dev, "POST failed, Test case : ASIC MEMORY TEST, Signature = 0x%08x\n",
2174                         signature);
2175                 ret = -EIO;
2176                 break;
2177         case QLC_83XX_POST_FLASH_TEST_FAIL:
2178                 dev_err(dev, "POST failed, Test case : FLASH TEST, Signature = 0x%08x\n",
2179                         signature);
2180                 ret = -EIO;
2181                 break;
2182         default:
2183                 dev_err(dev, "POST failed, Test case : INVALID, Signature = 0x%08x\n",
2184                         signature);
2185                 ret = -EIO;
2186                 break;
2187         }
2188
2189         return ret;
2190 }
2191
2192 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
2193 {
2194         struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
2195         int err = -EIO;
2196
2197         if (request_firmware(&fw_info->fw, fw_info->fw_file_name,
2198                              &(adapter->pdev->dev))) {
2199                 dev_err(&adapter->pdev->dev,
2200                         "No file FW image, loading flash FW image.\n");
2201                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2202                                     QLC_83XX_BOOT_FROM_FLASH);
2203         } else {
2204                 if (qlcnic_83xx_copy_fw_file(adapter))
2205                         return err;
2206                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2207                                     QLC_83XX_BOOT_FROM_FILE);
2208         }
2209
2210         return 0;
2211 }
2212
2213 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
2214 {
2215         u32 val;
2216         int err = -EIO;
2217
2218         qlcnic_83xx_stop_hw(adapter);
2219
2220         /* Collect FW register dump if required */
2221         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
2222         if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
2223                 qlcnic_dump_fw(adapter);
2224
2225         if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) {
2226                 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n",
2227                             __func__);
2228                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
2229                 return err;
2230         }
2231
2232         qlcnic_83xx_init_hw(adapter);
2233
2234         if (qlcnic_83xx_copy_bootloader(adapter))
2235                 return err;
2236
2237         /* Check if POST needs to be run */
2238         if (adapter->ahw->run_post) {
2239                 err = qlcnic_83xx_run_post(adapter);
2240                 if (err)
2241                         return err;
2242
2243                 /* No need to run POST in next reset sequence */
2244                 adapter->ahw->run_post = false;
2245
2246                 /* Again reset the adapter to load regular firmware  */
2247                 qlcnic_83xx_stop_hw(adapter);
2248                 qlcnic_83xx_init_hw(adapter);
2249
2250                 err = qlcnic_83xx_copy_bootloader(adapter);
2251                 if (err)
2252                         return err;
2253         }
2254
2255         /* Boot either flash image or firmware image from host file system */
2256         if (qlcnic_load_fw_file == 1) {
2257                 if (qlcnic_83xx_load_fw_image_from_host(adapter))
2258                         return err;
2259         } else {
2260                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2261                                     QLC_83XX_BOOT_FROM_FLASH);
2262         }
2263
2264         qlcnic_83xx_start_hw(adapter);
2265         if (qlcnic_83xx_check_hw_status(adapter))
2266                 return -EIO;
2267
2268         return 0;
2269 }
2270
2271 static int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
2272 {
2273         int err;
2274         struct qlcnic_info nic_info;
2275         struct qlcnic_hardware_context *ahw = adapter->ahw;
2276
2277         memset(&nic_info, 0, sizeof(struct qlcnic_info));
2278         err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
2279         if (err)
2280                 return -EIO;
2281
2282         ahw->physical_port = (u8) nic_info.phys_port;
2283         ahw->switch_mode = nic_info.switch_mode;
2284         ahw->max_tx_ques = nic_info.max_tx_ques;
2285         ahw->max_rx_ques = nic_info.max_rx_ques;
2286         ahw->capabilities = nic_info.capabilities;
2287         ahw->max_mac_filters = nic_info.max_mac_filters;
2288         ahw->max_mtu = nic_info.max_mtu;
2289
2290         /* eSwitch capability indicates vNIC mode.
2291          * vNIC and SRIOV are mutually exclusive operational modes.
2292          * If SR-IOV capability is detected, SR-IOV physical function
2293          * will get initialized in default mode.
2294          * SR-IOV virtual function initialization follows a
2295          * different code path and opmode.
2296          * SRIOV mode has precedence over vNIC mode.
2297          */
2298         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
2299                 return QLC_83XX_DEFAULT_OPMODE;
2300
2301         if (ahw->capabilities & QLC_83XX_ESWITCH_CAPABILITY)
2302                 return QLCNIC_VNIC_MODE;
2303
2304         return QLC_83XX_DEFAULT_OPMODE;
2305 }
2306
2307 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
2308 {
2309         struct qlcnic_hardware_context *ahw = adapter->ahw;
2310         u16 max_sds_rings, max_tx_rings;
2311         int ret;
2312
2313         ret = qlcnic_83xx_get_nic_configuration(adapter);
2314         if (ret == -EIO)
2315                 return -EIO;
2316
2317         if (ret == QLCNIC_VNIC_MODE) {
2318                 ahw->nic_mode = QLCNIC_VNIC_MODE;
2319
2320                 if (qlcnic_83xx_config_vnic_opmode(adapter))
2321                         return -EIO;
2322
2323                 max_sds_rings = QLCNIC_MAX_VNIC_SDS_RINGS;
2324                 max_tx_rings = QLCNIC_MAX_VNIC_TX_RINGS;
2325         } else if (ret == QLC_83XX_DEFAULT_OPMODE) {
2326                 ahw->nic_mode = QLCNIC_DEFAULT_MODE;
2327                 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
2328                 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
2329                 max_sds_rings = QLCNIC_MAX_SDS_RINGS;
2330                 max_tx_rings = QLCNIC_MAX_TX_RINGS;
2331         } else {
2332                 dev_err(&adapter->pdev->dev, "%s: Invalid opmode %d\n",
2333                         __func__, ret);
2334                 return -EIO;
2335         }
2336
2337         adapter->max_sds_rings = min(ahw->max_rx_ques, max_sds_rings);
2338         adapter->max_tx_rings = min(ahw->max_tx_ques, max_tx_rings);
2339
2340         return 0;
2341 }
2342
2343 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2344 {
2345         struct qlcnic_hardware_context *ahw = adapter->ahw;
2346
2347         if (ahw->port_type == QLCNIC_XGBE) {
2348                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2349                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2350                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2351                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2352
2353         } else if (ahw->port_type == QLCNIC_GBE) {
2354                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2355                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2356                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2357                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2358         }
2359         adapter->num_txd = MAX_CMD_DESCRIPTORS;
2360         adapter->max_rds_rings = MAX_RDS_RINGS;
2361 }
2362
2363 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2364 {
2365         int err = -EIO;
2366
2367         qlcnic_83xx_get_minidump_template(adapter);
2368         if (qlcnic_83xx_get_port_info(adapter))
2369                 return err;
2370
2371         qlcnic_83xx_config_buff_descriptors(adapter);
2372         adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2373         adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2374
2375         dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2376                  adapter->ahw->fw_hal_version);
2377
2378         return 0;
2379 }
2380
2381 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2382 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2383 {
2384         struct qlcnic_cmd_args cmd;
2385         u32 presence_mask, audit_mask;
2386         int status;
2387
2388         presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2389         audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2390
2391         if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2392                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
2393                                                QLCNIC_CMD_STOP_NIC_FUNC);
2394                 if (status)
2395                         return;
2396
2397                 cmd.req.arg[1] = BIT_31;
2398                 status = qlcnic_issue_cmd(adapter, &cmd);
2399                 if (status)
2400                         dev_err(&adapter->pdev->dev,
2401                                 "Failed to clean up the function resources\n");
2402                 qlcnic_free_mbx_args(&cmd);
2403         }
2404 }
2405
2406 static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter *adapter)
2407 {
2408         struct qlcnic_hardware_context *ahw = adapter->ahw;
2409         struct pci_dev *pdev = adapter->pdev;
2410         struct qlc_83xx_fw_info *fw_info;
2411         int err = 0;
2412
2413         ahw->fw_info = kzalloc(sizeof(*fw_info), GFP_KERNEL);
2414         if (!ahw->fw_info) {
2415                 err = -ENOMEM;
2416         } else {
2417                 fw_info = ahw->fw_info;
2418                 switch (pdev->device) {
2419                 case PCI_DEVICE_ID_QLOGIC_QLE834X:
2420                 case PCI_DEVICE_ID_QLOGIC_QLE8830:
2421                         strncpy(fw_info->fw_file_name, QLC_83XX_FW_FILE_NAME,
2422                                 QLC_FW_FILE_NAME_LEN);
2423                         break;
2424                 case PCI_DEVICE_ID_QLOGIC_QLE844X:
2425                         strncpy(fw_info->fw_file_name, QLC_84XX_FW_FILE_NAME,
2426                                 QLC_FW_FILE_NAME_LEN);
2427                         break;
2428                 default:
2429                         dev_err(&pdev->dev, "%s: Invalid device id\n",
2430                                 __func__);
2431                         err = -EINVAL;
2432                         break;
2433                 }
2434         }
2435
2436         return err;
2437 }
2438
2439 static void qlcnic_83xx_init_rings(struct qlcnic_adapter *adapter)
2440 {
2441         u8 rx_cnt = QLCNIC_DEF_SDS_RINGS;
2442         u8 tx_cnt = QLCNIC_DEF_TX_RINGS;
2443
2444         adapter->max_tx_rings = QLCNIC_MAX_TX_RINGS;
2445         adapter->max_sds_rings = QLCNIC_MAX_SDS_RINGS;
2446
2447         if (!adapter->ahw->msix_supported) {
2448                 rx_cnt = QLCNIC_SINGLE_RING;
2449                 tx_cnt = QLCNIC_SINGLE_RING;
2450         }
2451
2452         /* compute and set drv sds rings */
2453         qlcnic_set_tx_ring_count(adapter, tx_cnt);
2454         qlcnic_set_sds_ring_count(adapter, rx_cnt);
2455 }
2456
2457 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2458 {
2459         struct qlcnic_hardware_context *ahw = adapter->ahw;
2460         int err = 0;
2461
2462         adapter->rx_mac_learn = false;
2463         ahw->msix_supported = !!qlcnic_use_msi_x;
2464
2465         /* Check if POST needs to be run */
2466         switch (qlcnic_load_fw_file) {
2467         case 2:
2468                 ahw->post_mode = QLC_83XX_POST_FAST_MODE;
2469                 ahw->run_post = true;
2470                 break;
2471         case 3:
2472                 ahw->post_mode = QLC_83XX_POST_MEDIUM_MODE;
2473                 ahw->run_post = true;
2474                 break;
2475         case 4:
2476                 ahw->post_mode = QLC_83XX_POST_SLOW_MODE;
2477                 ahw->run_post = true;
2478                 break;
2479         default:
2480                 ahw->run_post = false;
2481                 break;
2482         }
2483
2484         qlcnic_83xx_init_rings(adapter);
2485
2486         err = qlcnic_83xx_init_mailbox_work(adapter);
2487         if (err)
2488                 goto exit;
2489
2490         if (qlcnic_sriov_vf_check(adapter)) {
2491                 err = qlcnic_sriov_vf_init(adapter, pci_using_dac);
2492                 if (err)
2493                         goto detach_mbx;
2494                 else
2495                         return err;
2496         }
2497
2498         if (qlcnic_83xx_read_flash_descriptor_table(adapter) ||
2499             qlcnic_83xx_read_flash_mfg_id(adapter)) {
2500                 dev_err(&adapter->pdev->dev, "Failed reading flash mfg id\n");
2501                 err = -ENOTRECOVERABLE;
2502                 goto detach_mbx;
2503         }
2504
2505         err = qlcnic_83xx_check_hw_status(adapter);
2506         if (err)
2507                 goto detach_mbx;
2508
2509         err = qlcnic_83xx_get_fw_info(adapter);
2510         if (err)
2511                 goto detach_mbx;
2512
2513         err = qlcnic_83xx_idc_init(adapter);
2514         if (err)
2515                 goto detach_mbx;
2516
2517         err = qlcnic_setup_intr(adapter);
2518         if (err) {
2519                 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
2520                 goto disable_intr;
2521         }
2522
2523         INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2524
2525         err = qlcnic_83xx_setup_mbx_intr(adapter);
2526         if (err)
2527                 goto disable_mbx_intr;
2528
2529         qlcnic_83xx_clear_function_resources(adapter);
2530         qlcnic_dcb_enable(adapter->dcb);
2531         qlcnic_83xx_initialize_nic(adapter, 1);
2532         qlcnic_dcb_get_info(adapter->dcb);
2533
2534         /* Configure default, SR-IOV or Virtual NIC mode of operation */
2535         err = qlcnic_83xx_configure_opmode(adapter);
2536         if (err)
2537                 goto disable_mbx_intr;
2538
2539
2540         /* Perform operating mode specific initialization */
2541         err = adapter->nic_ops->init_driver(adapter);
2542         if (err)
2543                 goto disable_mbx_intr;
2544
2545         /* Periodically monitor device status */
2546         qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2547         return 0;
2548
2549 disable_mbx_intr:
2550         qlcnic_83xx_free_mbx_intr(adapter);
2551
2552 disable_intr:
2553         qlcnic_teardown_intr(adapter);
2554
2555 detach_mbx:
2556         qlcnic_83xx_detach_mailbox_work(adapter);
2557         qlcnic_83xx_free_mailbox(ahw->mailbox);
2558         ahw->mailbox = NULL;
2559 exit:
2560         return err;
2561 }
2562
2563 void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *adapter)
2564 {
2565         struct qlcnic_hardware_context *ahw = adapter->ahw;
2566         struct qlc_83xx_idc *idc = &ahw->idc;
2567
2568         clear_bit(QLC_83XX_MBX_READY, &idc->status);
2569         cancel_delayed_work_sync(&adapter->fw_work);
2570
2571         if (ahw->nic_mode == QLCNIC_VNIC_MODE)
2572                 qlcnic_83xx_disable_vnic_mode(adapter, 1);
2573
2574         qlcnic_83xx_idc_detach_driver(adapter);
2575         qlcnic_83xx_initialize_nic(adapter, 0);
2576
2577         cancel_delayed_work_sync(&adapter->idc_aen_work);
2578 }
2579
2580 int qlcnic_83xx_aer_reset(struct qlcnic_adapter *adapter)
2581 {
2582         struct qlcnic_hardware_context *ahw = adapter->ahw;
2583         struct qlc_83xx_idc *idc = &ahw->idc;
2584         int ret = 0;
2585         u32 owner;
2586
2587         /* Mark the previous IDC state as NEED_RESET so
2588          * that state_entry() will perform the reattachment
2589          * and bringup the device
2590          */
2591         idc->prev_state = QLC_83XX_IDC_DEV_NEED_RESET;
2592         owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
2593         if (ahw->pci_func == owner) {
2594                 ret = qlcnic_83xx_restart_hw(adapter);
2595                 if (ret < 0)
2596                         return ret;
2597                 qlcnic_83xx_idc_clear_registers(adapter, 0);
2598         }
2599
2600         ret = idc->state_entry(adapter);
2601         return ret;
2602 }
2603
2604 void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *adapter)
2605 {
2606         struct qlcnic_hardware_context *ahw = adapter->ahw;
2607         struct qlc_83xx_idc *idc = &ahw->idc;
2608         u32 owner;
2609
2610         idc->prev_state = QLC_83XX_IDC_DEV_READY;
2611         owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
2612         if (ahw->pci_func == owner)
2613                 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
2614
2615         qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 0);
2616 }