kernel/drivers/net/ethernet/qlogic/qed/qed_int.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef _QED_INT_H
  10 #define _QED_INT_H
  11
  12 #include <linux/types.h>
  13 #include <linux/slab.h>
  14 #include "qed.h"
  15
  16 /* Fields of IGU PF CONFIGRATION REGISTER */
  17 #define IGU_PF_CONF_FUNC_EN       (0x1 << 0)    /* function enable        */
  18 #define IGU_PF_CONF_MSI_MSIX_EN   (0x1 << 1)    /* MSI/MSIX enable        */
  19 #define IGU_PF_CONF_INT_LINE_EN   (0x1 << 2)    /* INT enable             */
  20 #define IGU_PF_CONF_ATTN_BIT_EN   (0x1 << 3)    /* attention enable       */
  21 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4)    /* single ISR mode enable */
  22 #define IGU_PF_CONF_SIMD_MODE     (0x1 << 5)    /* simd all ones mode     */
  23
  24 /* Igu control commands
  25  */
  26 enum igu_ctrl_cmd {
  27         IGU_CTRL_CMD_TYPE_RD,
  28         IGU_CTRL_CMD_TYPE_WR,
  29         MAX_IGU_CTRL_CMD
  30 };
  31
  32 /* Control register for the IGU command register
  33  */
  34 struct igu_ctrl_reg {
  35         u32 ctrl_data;
  36 #define IGU_CTRL_REG_FID_MASK           0xFFFF  /* Opaque_FID    */
  37 #define IGU_CTRL_REG_FID_SHIFT          0
  38 #define IGU_CTRL_REG_PXP_ADDR_MASK      0xFFF   /* Command address */
  39 #define IGU_CTRL_REG_PXP_ADDR_SHIFT     16
  40 #define IGU_CTRL_REG_RESERVED_MASK      0x1
  41 #define IGU_CTRL_REG_RESERVED_SHIFT     28
  42 #define IGU_CTRL_REG_TYPE_MASK          0x1 /* use enum igu_ctrl_cmd */
  43 #define IGU_CTRL_REG_TYPE_SHIFT         31
  44 };
  45
  46 enum qed_coalescing_fsm {
  47         QED_COAL_RX_STATE_MACHINE,
  48         QED_COAL_TX_STATE_MACHINE
  49 };
  50
  51 /**
  52  * @brief qed_int_cau_conf_pi - configure cau for a given
  53  *        status block
  54  *
  55  * @param p_hwfn
  56  * @param p_ptt
  57  * @param igu_sb_id
  58  * @param pi_index
  59  * @param state
  60  * @param timeset
  61  */
  62 void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
  63                          struct qed_ptt *p_ptt,
  64                          u16 igu_sb_id,
  65                          u32 pi_index,
  66                          enum qed_coalescing_fsm coalescing_fsm,
  67                          u8 timeset);
  68
  69 /**
  70  * @brief qed_int_igu_enable_int - enable device interrupts
  71  *
  72  * @param p_hwfn
  73  * @param p_ptt
  74  * @param int_mode - interrupt mode to use
  75  */
  76 void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
  77                             struct qed_ptt *p_ptt,
  78                             enum qed_int_mode int_mode);
  79
  80 /**
  81  * @brief qed_int_igu_disable_int - disable device interrupts
  82  *
  83  * @param p_hwfn
  84  * @param p_ptt
  85  */
  86 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
  87                              struct qed_ptt *p_ptt);
  88
  89 /**
  90  * @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc
  91  *        register from igu.
  92  *
  93  * @param p_hwfn
  94  *
  95  * @return u64
  96  */
  97 u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn);
  98
  99 #define QED_SP_SB_ID 0xffff
 100 /**
 101  * @brief qed_int_sb_init - Initializes the sb_info structure.
 102  *
 103  * once the structure is initialized it can be passed to sb related functions.
 104  *
 105  * @param p_hwfn
 106  * @param p_ptt
 107  * @param sb_info       points to an uninitialized (but
 108  *                      allocated) sb_info structure
 109  * @param sb_virt_addr
 110  * @param sb_phy_addr
 111  * @param sb_id the sb_id to be used (zero based in driver)
 112  *                      should use QED_SP_SB_ID for SP Status block
 113  *
 114  * @return int
 115  */
 116 int qed_int_sb_init(struct qed_hwfn *p_hwfn,
 117                     struct qed_ptt *p_ptt,
 118                     struct qed_sb_info *sb_info,
 119                     void *sb_virt_addr,
 120                     dma_addr_t sb_phy_addr,
 121                     u16 sb_id);
 122 /**
 123  * @brief qed_int_sb_setup - Setup the sb.
 124  *
 125  * @param p_hwfn
 126  * @param p_ptt
 127  * @param sb_info       initialized sb_info structure
 128  */
 129 void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
 130                       struct qed_ptt *p_ptt,
 131                       struct qed_sb_info *sb_info);
 132
 133 /**
 134  * @brief qed_int_sb_release - releases the sb_info structure.
 135  *
 136  * once the structure is released, it's memory can be freed
 137  *
 138  * @param p_hwfn
 139  * @param sb_info       points to an allocated sb_info structure
 140  * @param sb_id         the sb_id to be used (zero based in driver)
 141  *                      should never be equal to QED_SP_SB_ID
 142  *                      (SP Status block)
 143  *
 144  * @return int
 145  */
 146 int qed_int_sb_release(struct qed_hwfn *p_hwfn,
 147                        struct qed_sb_info *sb_info,
 148                        u16 sb_id);
 149
 150 /**
 151  * @brief qed_int_sp_dpc - To be called when an interrupt is received on the
 152  *        default status block.
 153  *
 154  * @param p_hwfn - pointer to hwfn
 155  *
 156  */
 157 void qed_int_sp_dpc(unsigned long hwfn_cookie);
 158
 159 /**
 160  * @brief qed_int_get_num_sbs - get the number of status
 161  *        blocks configured for this funciton in the igu.
 162  *
 163  * @param p_hwfn
 164  * @param p_iov_blks - configured free blks for vfs
 165  *
 166  * @return int - number of status blocks configured
 167  */
 168 int qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
 169                         int *p_iov_blks);
 170
 171 /**
 172  * @brief qed_int_disable_post_isr_release - performs the cleanup post ISR
 173  *        release. The API need to be called after releasing all slowpath IRQs
 174  *        of the device.
 175  *
 176  * @param cdev
 177  *
 178  */
 179 void qed_int_disable_post_isr_release(struct qed_dev *cdev);
 180
 181 #define QED_CAU_DEF_RX_TIMER_RES 0
 182 #define QED_CAU_DEF_TX_TIMER_RES 0
 183
 184 #define QED_SB_ATT_IDX  0x0001
 185 #define QED_SB_EVENT_MASK       0x0003
 186
 187 #define SB_ALIGNED_SIZE(p_hwfn) \
 188         ALIGNED_TYPE_SIZE(struct status_block, p_hwfn)
 189
 190 struct qed_igu_block {
 191         u8      status;
 192 #define QED_IGU_STATUS_FREE     0x01
 193 #define QED_IGU_STATUS_VALID    0x02
 194 #define QED_IGU_STATUS_PF       0x04
 195
 196         u8      vector_number;
 197         u8      function_id;
 198         u8      is_pf;
 199 };
 200
 201 struct qed_igu_map {
 202         struct qed_igu_block igu_blocks[MAX_TOT_SB_PER_PATH];
 203 };
 204
 205 struct qed_igu_info {
 206         struct qed_igu_map      igu_map;
 207         u16                     igu_dsb_id;
 208         u16                     igu_base_sb;
 209         u16                     igu_base_sb_iov;
 210         u16                     igu_sb_cnt;
 211         u16                     igu_sb_cnt_iov;
 212         u16                     free_blks;
 213 };
 214
 215 /* TODO Names of function may change... */
 216 void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
 217                               struct qed_ptt *p_ptt,
 218                               bool b_set,
 219                               bool b_slowpath);
 220
 221 void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn);
 222
 223 /**
 224  * @brief qed_int_igu_read_cam - Reads the IGU CAM.
 225  *      This function needs to be called during hardware
 226  *      prepare. It reads the info from igu cam to know which
 227  *      status block is the default / base status block etc.
 228  *
 229  * @param p_hwfn
 230  * @param p_ptt
 231  *
 232  * @return int
 233  */
 234 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
 235                          struct qed_ptt *p_ptt);
 236
 237 typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn,
 238                                  void *cookie);
 239 /**
 240  * @brief qed_int_register_cb - Register callback func for
 241  *      slowhwfn statusblock.
 242  *
 243  *      Every protocol that uses the slowhwfn status block
 244  *      should register a callback function that will be called
 245  *      once there is an update of the sp status block.
 246  *
 247  * @param p_hwfn
 248  * @param comp_cb - function to be called when there is an
 249  *                  interrupt on the sp sb
 250  *
 251  * @param cookie  - passed to the callback function
 252  * @param sb_idx  - OUT parameter which gives the chosen index
 253  *                  for this protocol.
 254  * @param p_fw_cons  - pointer to the actual address of the
 255  *                     consumer for this protocol.
 256  *
 257  * @return int
 258  */
 259 int qed_int_register_cb(struct qed_hwfn *p_hwfn,
 260                         qed_int_comp_cb_t comp_cb,
 261                         void *cookie,
 262                         u8 *sb_idx,
 263                         __le16 **p_fw_cons);
 264
 265 /**
 266  * @brief qed_int_unregister_cb - Unregisters callback
 267  *      function from sp sb.
 268  *      Partner of qed_int_register_cb -> should be called
 269  *      when no longer required.
 270  *
 271  * @param p_hwfn
 272  * @param pi
 273  *
 274  * @return int
 275  */
 276 int qed_int_unregister_cb(struct qed_hwfn *p_hwfn,
 277                           u8 pi);
 278
 279 /**
 280  * @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id.
 281  *
 282  * @param p_hwfn
 283  *
 284  * @return u16
 285  */
 286 u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn);
 287
 288 /**
 289  * @brief Status block cleanup. Should be called for each status
 290  *        block that will be used -> both PF / VF
 291  *
 292  * @param p_hwfn
 293  * @param p_ptt
 294  * @param sb_id         - igu status block id
 295  * @param cleanup_set   - set(1) / clear(0)
 296  * @param opaque_fid    - the function for which to perform
 297  *                      cleanup, for example a PF on behalf of
 298  *                      its VFs.
 299  */
 300 void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
 301                             struct qed_ptt *p_ptt,
 302                             u32 sb_id,
 303                             bool cleanup_set,
 304                             u16 opaque_fid);
 305
 306 /**
 307  * @brief Status block cleanup. Should be called for each status
 308  *        block that will be used -> both PF / VF
 309  *
 310  * @param p_hwfn
 311  * @param p_ptt
 312  * @param sb_id         - igu status block id
 313  * @param opaque        - opaque fid of the sb owner.
 314  * @param cleanup_set   - set(1) / clear(0)
 315  */
 316 void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
 317                                      struct qed_ptt *p_ptt,
 318                                      u32 sb_id,
 319                                      u16 opaque,
 320                                      bool b_set);
 321
 322 /**
 323  * @brief qed_int_cau_conf - configure cau for a given status
 324  *        block
 325  *
 326  * @param p_hwfn
 327  * @param ptt
 328  * @param sb_phys
 329  * @param igu_sb_id
 330  * @param vf_number
 331  * @param vf_valid
 332  */
 333 void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
 334                          struct qed_ptt *p_ptt,
 335                          dma_addr_t sb_phys,
 336                          u16 igu_sb_id,
 337                          u16 vf_number,
 338                          u8 vf_valid);
 339
 340 /**
 341  * @brief qed_int_alloc
 342  *
 343  * @param p_hwfn
 344  * @param p_ptt
 345  *
 346  * @return int
 347  */
 348 int qed_int_alloc(struct qed_hwfn *p_hwfn,
 349                   struct qed_ptt *p_ptt);
 350
 351 /**
 352  * @brief qed_int_free
 353  *
 354  * @param p_hwfn
 355  */
 356 void qed_int_free(struct qed_hwfn *p_hwfn);
 357
 358 /**
 359  * @brief qed_int_setup
 360  *
 361  * @param p_hwfn
 362  * @param p_ptt
 363  */
 364 void qed_int_setup(struct qed_hwfn *p_hwfn,
 365                    struct qed_ptt *p_ptt);
 366
 367 /**
 368  * @brief - Enable Interrupt & Attention for hw function
 369  *
 370  * @param p_hwfn
 371  * @param p_ptt
 372  * @param int_mode
 373  *
 374  * @return int
 375  */
 376 int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
 377                        enum qed_int_mode int_mode);
 378
 379 /**
 380  * @brief - Initialize CAU status block entry
 381  *
 382  * @param p_hwfn
 383  * @param p_sb_entry
 384  * @param pf_id
 385  * @param vf_number
 386  * @param vf_valid
 387  */
 388 void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
 389                            struct cau_sb_entry *p_sb_entry,
 390                            u8 pf_id,
 391                            u16 vf_number,
 392                            u8 vf_valid);
 393
 394 #define QED_MAPPING_MEMORY_SIZE(dev)    (NUM_OF_SBS(dev))
 395
 396 #endif