kernel/drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/flow_table.h>
  34 #include "en.h"
  35
  36 struct mlx5e_rq_param {
  37         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  38         struct mlx5_wq_param       wq;
  39 };
  40
  41 struct mlx5e_sq_param {
  42         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  43         struct mlx5_wq_param       wq;
  44         u16                        max_inline;
  45 };
  46
  47 struct mlx5e_cq_param {
  48         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        eq_ix;
  51 };
  52
  53 struct mlx5e_channel_param {
  54         struct mlx5e_rq_param      rq;
  55         struct mlx5e_sq_param      sq;
  56         struct mlx5e_cq_param      rx_cq;
  57         struct mlx5e_cq_param      tx_cq;
  58 };
  59
  60 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  61 {
  62         struct mlx5_core_dev *mdev = priv->mdev;
  63         u8 port_state;
  64
  65         port_state = mlx5_query_vport_state(mdev,
  66                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
  67
  68         if (port_state == VPORT_STATE_UP)
  69                 netif_carrier_on(priv->netdev);
  70         else
  71                 netif_carrier_off(priv->netdev);
  72 }
  73
  74 static void mlx5e_update_carrier_work(struct work_struct *work)
  75 {
  76         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  77                                                update_carrier_work);
  78
  79         mutex_lock(&priv->state_lock);
  80         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  81                 mlx5e_update_carrier(priv);
  82         mutex_unlock(&priv->state_lock);
  83 }
  84
  85 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
  86 {
  87         struct mlx5_core_dev *mdev = priv->mdev;
  88         struct mlx5e_pport_stats *s = &priv->stats.pport;
  89         u32 *in;
  90         u32 *out;
  91         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
  92
  93         in  = mlx5_vzalloc(sz);
  94         out = mlx5_vzalloc(sz);
  95         if (!in || !out)
  96                 goto free_out;
  97
  98         MLX5_SET(ppcnt_reg, in, local_port, 1);
  99
 100         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 101         mlx5_core_access_reg(mdev, in, sz, out,
 102                              sz, MLX5_REG_PPCNT, 0, 0);
 103         memcpy(s->IEEE_802_3_counters,
 104                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 105                sizeof(s->IEEE_802_3_counters));
 106
 107         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 108         mlx5_core_access_reg(mdev, in, sz, out,
 109                              sz, MLX5_REG_PPCNT, 0, 0);
 110         memcpy(s->RFC_2863_counters,
 111                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 112                sizeof(s->RFC_2863_counters));
 113
 114         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 115         mlx5_core_access_reg(mdev, in, sz, out,
 116                              sz, MLX5_REG_PPCNT, 0, 0);
 117         memcpy(s->RFC_2819_counters,
 118                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 119                sizeof(s->RFC_2819_counters));
 120
 121 free_out:
 122         kvfree(in);
 123         kvfree(out);
 124 }
 125
 126 void mlx5e_update_stats(struct mlx5e_priv *priv)
 127 {
 128         struct mlx5_core_dev *mdev = priv->mdev;
 129         struct mlx5e_vport_stats *s = &priv->stats.vport;
 130         struct mlx5e_rq_stats *rq_stats;
 131         struct mlx5e_sq_stats *sq_stats;
 132         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 133         u32 *out;
 134         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 135         u64 tx_offload_none;
 136         int i, j;
 137
 138         out = mlx5_vzalloc(outlen);
 139         if (!out)
 140                 return;
 141
 142         /* Collect firts the SW counters and then HW for consistency */
 143         s->tso_packets          = 0;
 144         s->tso_bytes            = 0;
 145         s->tx_queue_stopped     = 0;
 146         s->tx_queue_wake        = 0;
 147         s->tx_queue_dropped     = 0;
 148         tx_offload_none         = 0;
 149         s->lro_packets          = 0;
 150         s->lro_bytes            = 0;
 151         s->rx_csum_none         = 0;
 152         s->rx_csum_sw           = 0;
 153         s->rx_wqe_err           = 0;
 154         for (i = 0; i < priv->params.num_channels; i++) {
 155                 rq_stats = &priv->channel[i]->rq.stats;
 156
 157                 s->lro_packets  += rq_stats->lro_packets;
 158                 s->lro_bytes    += rq_stats->lro_bytes;
 159                 s->rx_csum_none += rq_stats->csum_none;
 160                 s->rx_csum_sw   += rq_stats->csum_sw;
 161                 s->rx_wqe_err   += rq_stats->wqe_err;
 162
 163                 for (j = 0; j < priv->params.num_tc; j++) {
 164                         sq_stats = &priv->channel[i]->sq[j].stats;
 165
 166                         s->tso_packets          += sq_stats->tso_packets;
 167                         s->tso_bytes            += sq_stats->tso_bytes;
 168                         s->tx_queue_stopped     += sq_stats->stopped;
 169                         s->tx_queue_wake        += sq_stats->wake;
 170                         s->tx_queue_dropped     += sq_stats->dropped;
 171                         tx_offload_none         += sq_stats->csum_offload_none;
 172                 }
 173         }
 174
 175         /* HW counters */
 176         memset(in, 0, sizeof(in));
 177
 178         MLX5_SET(query_vport_counter_in, in, opcode,
 179                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 180         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 181         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 182
 183         memset(out, 0, outlen);
 184
 185         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 186                 goto free_out;
 187
 188 #define MLX5_GET_CTR(p, x) \
 189         MLX5_GET64(query_vport_counter_out, p, x)
 190
 191         s->rx_error_packets     =
 192                 MLX5_GET_CTR(out, received_errors.packets);
 193         s->rx_error_bytes       =
 194                 MLX5_GET_CTR(out, received_errors.octets);
 195         s->tx_error_packets     =
 196                 MLX5_GET_CTR(out, transmit_errors.packets);
 197         s->tx_error_bytes       =
 198                 MLX5_GET_CTR(out, transmit_errors.octets);
 199
 200         s->rx_unicast_packets   =
 201                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 202         s->rx_unicast_bytes     =
 203                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 204         s->tx_unicast_packets   =
 205                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 206         s->tx_unicast_bytes     =
 207                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 208
 209         s->rx_multicast_packets =
 210                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 211         s->rx_multicast_bytes   =
 212                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 213         s->tx_multicast_packets =
 214                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 215         s->tx_multicast_bytes   =
 216                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 217
 218         s->rx_broadcast_packets =
 219                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 220         s->rx_broadcast_bytes   =
 221                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 222         s->tx_broadcast_packets =
 223                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 224         s->tx_broadcast_bytes   =
 225                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 226
 227         s->rx_packets =
 228                 s->rx_unicast_packets +
 229                 s->rx_multicast_packets +
 230                 s->rx_broadcast_packets;
 231         s->rx_bytes =
 232                 s->rx_unicast_bytes +
 233                 s->rx_multicast_bytes +
 234                 s->rx_broadcast_bytes;
 235         s->tx_packets =
 236                 s->tx_unicast_packets +
 237                 s->tx_multicast_packets +
 238                 s->tx_broadcast_packets;
 239         s->tx_bytes =
 240                 s->tx_unicast_bytes +
 241                 s->tx_multicast_bytes +
 242                 s->tx_broadcast_bytes;
 243
 244         /* Update calculated offload counters */
 245         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 246         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 247                                s->rx_csum_sw;
 248
 249         mlx5e_update_pport_counters(priv);
 250 free_out:
 251         kvfree(out);
 252 }
 253
 254 static void mlx5e_update_stats_work(struct work_struct *work)
 255 {
 256         struct delayed_work *dwork = to_delayed_work(work);
 257         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 258                                                update_stats_work);
 259         mutex_lock(&priv->state_lock);
 260         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 261                 mlx5e_update_stats(priv);
 262                 schedule_delayed_work(dwork,
 263                                       msecs_to_jiffies(
 264                                               MLX5E_UPDATE_STATS_INTERVAL));
 265         }
 266         mutex_unlock(&priv->state_lock);
 267 }
 268
 269 static void __mlx5e_async_event(struct mlx5e_priv *priv,
 270                                 enum mlx5_dev_event event)
 271 {
 272         switch (event) {
 273         case MLX5_DEV_EVENT_PORT_UP:
 274         case MLX5_DEV_EVENT_PORT_DOWN:
 275                 schedule_work(&priv->update_carrier_work);
 276                 break;
 277
 278         default:
 279                 break;
 280         }
 281 }
 282
 283 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 284                               enum mlx5_dev_event event, unsigned long param)
 285 {
 286         struct mlx5e_priv *priv = vpriv;
 287
 288         spin_lock(&priv->async_events_spinlock);
 289         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 290                 __mlx5e_async_event(priv, event);
 291         spin_unlock(&priv->async_events_spinlock);
 292 }
 293
 294 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 295 {
 296         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 297 }
 298
 299 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 300 {
 301         spin_lock_irq(&priv->async_events_spinlock);
 302         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 303         spin_unlock_irq(&priv->async_events_spinlock);
 304 }
 305
 306 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 307 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 308
 309 static int mlx5e_create_rq(struct mlx5e_channel *c,
 310                            struct mlx5e_rq_param *param,
 311                            struct mlx5e_rq *rq)
 312 {
 313         struct mlx5e_priv *priv = c->priv;
 314         struct mlx5_core_dev *mdev = priv->mdev;
 315         void *rqc = param->rqc;
 316         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 317         int wq_sz;
 318         int err;
 319         int i;
 320
 321         param->wq.db_numa_node = cpu_to_node(c->cpu);
 322
 323         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 324                                 &rq->wq_ctrl);
 325         if (err)
 326                 return err;
 327
 328         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 329
 330         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 331         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 332                                cpu_to_node(c->cpu));
 333         if (!rq->skb) {
 334                 err = -ENOMEM;
 335                 goto err_rq_wq_destroy;
 336         }
 337
 338         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
 339                                              MLX5E_SW2HW_MTU(priv->netdev->mtu);
 340         rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 341
 342         for (i = 0; i < wq_sz; i++) {
 343                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 344                 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 345
 346                 wqe->data.lkey       = c->mkey_be;
 347                 wqe->data.byte_count =
 348                         cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 349         }
 350
 351         rq->pdev    = c->pdev;
 352         rq->netdev  = c->netdev;
 353         rq->channel = c;
 354         rq->ix      = c->ix;
 355         rq->priv    = c->priv;
 356
 357         return 0;
 358
 359 err_rq_wq_destroy:
 360         mlx5_wq_destroy(&rq->wq_ctrl);
 361
 362         return err;
 363 }
 364
 365 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 366 {
 367         kfree(rq->skb);
 368         mlx5_wq_destroy(&rq->wq_ctrl);
 369 }
 370
 371 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 372 {
 373         struct mlx5e_priv *priv = rq->priv;
 374         struct mlx5_core_dev *mdev = priv->mdev;
 375
 376         void *in;
 377         void *rqc;
 378         void *wq;
 379         int inlen;
 380         int err;
 381
 382         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 383                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 384         in = mlx5_vzalloc(inlen);
 385         if (!in)
 386                 return -ENOMEM;
 387
 388         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 389         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 390
 391         memcpy(rqc, param->rqc, sizeof(param->rqc));
 392
 393         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 394         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 395         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 396         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 397                                                 MLX5_ADAPTER_PAGE_SHIFT);
 398         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 399
 400         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 401                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 402
 403         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 404
 405         kvfree(in);
 406
 407         return err;
 408 }
 409
 410 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 411 {
 412         struct mlx5e_channel *c = rq->channel;
 413         struct mlx5e_priv *priv = c->priv;
 414         struct mlx5_core_dev *mdev = priv->mdev;
 415
 416         void *in;
 417         void *rqc;
 418         int inlen;
 419         int err;
 420
 421         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 422         in = mlx5_vzalloc(inlen);
 423         if (!in)
 424                 return -ENOMEM;
 425
 426         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 427
 428         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 429         MLX5_SET(rqc, rqc, state, next_state);
 430
 431         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 432
 433         kvfree(in);
 434
 435         return err;
 436 }
 437
 438 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 439 {
 440         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 441 }
 442
 443 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 444 {
 445         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 446         struct mlx5e_channel *c = rq->channel;
 447         struct mlx5e_priv *priv = c->priv;
 448         struct mlx5_wq_ll *wq = &rq->wq;
 449
 450         while (time_before(jiffies, exp_time)) {
 451                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 452                         return 0;
 453
 454                 msleep(20);
 455         }
 456
 457         return -ETIMEDOUT;
 458 }
 459
 460 static int mlx5e_open_rq(struct mlx5e_channel *c,
 461                          struct mlx5e_rq_param *param,
 462                          struct mlx5e_rq *rq)
 463 {
 464         int err;
 465
 466         err = mlx5e_create_rq(c, param, rq);
 467         if (err)
 468                 return err;
 469
 470         err = mlx5e_enable_rq(rq, param);
 471         if (err)
 472                 goto err_destroy_rq;
 473
 474         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 475         if (err)
 476                 goto err_disable_rq;
 477
 478         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 479         mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
 480
 481         return 0;
 482
 483 err_disable_rq:
 484         mlx5e_disable_rq(rq);
 485 err_destroy_rq:
 486         mlx5e_destroy_rq(rq);
 487
 488         return err;
 489 }
 490
 491 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 492 {
 493         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 494         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 495
 496         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 497         while (!mlx5_wq_ll_is_empty(&rq->wq))
 498                 msleep(20);
 499
 500         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 501         napi_synchronize(&rq->channel->napi);
 502
 503         mlx5e_disable_rq(rq);
 504         mlx5e_destroy_rq(rq);
 505 }
 506
 507 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 508 {
 509         kfree(sq->dma_fifo);
 510         kfree(sq->skb);
 511 }
 512
 513 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 514 {
 515         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 516         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 517
 518         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 519         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 520                                     numa);
 521
 522         if (!sq->skb || !sq->dma_fifo) {
 523                 mlx5e_free_sq_db(sq);
 524                 return -ENOMEM;
 525         }
 526
 527         sq->dma_fifo_mask = df_sz - 1;
 528
 529         return 0;
 530 }
 531
 532 static int mlx5e_create_sq(struct mlx5e_channel *c,
 533                            int tc,
 534                            struct mlx5e_sq_param *param,
 535                            struct mlx5e_sq *sq)
 536 {
 537         struct mlx5e_priv *priv = c->priv;
 538         struct mlx5_core_dev *mdev = priv->mdev;
 539
 540         void *sqc = param->sqc;
 541         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 542         int txq_ix;
 543         int err;
 544
 545         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 546         if (err)
 547                 return err;
 548
 549         param->wq.db_numa_node = cpu_to_node(c->cpu);
 550
 551         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 552                                  &sq->wq_ctrl);
 553         if (err)
 554                 goto err_unmap_free_uar;
 555
 556         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 557         sq->uar_map     = sq->uar.map;
 558         sq->uar_bf_map  = sq->uar.bf_map;
 559         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 560         sq->max_inline  = param->max_inline;
 561
 562         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 563         if (err)
 564                 goto err_sq_wq_destroy;
 565
 566         txq_ix = c->ix + tc * priv->params.num_channels;
 567         sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 568
 569         sq->pdev      = c->pdev;
 570         sq->mkey_be   = c->mkey_be;
 571         sq->channel   = c;
 572         sq->tc        = tc;
 573         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 574         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 575         priv->txq_to_sq_map[txq_ix] = sq;
 576
 577         return 0;
 578
 579 err_sq_wq_destroy:
 580         mlx5_wq_destroy(&sq->wq_ctrl);
 581
 582 err_unmap_free_uar:
 583         mlx5_unmap_free_uar(mdev, &sq->uar);
 584
 585         return err;
 586 }
 587
 588 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 589 {
 590         struct mlx5e_channel *c = sq->channel;
 591         struct mlx5e_priv *priv = c->priv;
 592
 593         mlx5e_free_sq_db(sq);
 594         mlx5_wq_destroy(&sq->wq_ctrl);
 595         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 596 }
 597
 598 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 599 {
 600         struct mlx5e_channel *c = sq->channel;
 601         struct mlx5e_priv *priv = c->priv;
 602         struct mlx5_core_dev *mdev = priv->mdev;
 603
 604         void *in;
 605         void *sqc;
 606         void *wq;
 607         int inlen;
 608         int err;
 609
 610         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 611                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 612         in = mlx5_vzalloc(inlen);
 613         if (!in)
 614                 return -ENOMEM;
 615
 616         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 617         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 618
 619         memcpy(sqc, param->sqc, sizeof(param->sqc));
 620
 621         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 622         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 623         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 624         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 625         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 626
 627         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 628         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 629         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 630                                           MLX5_ADAPTER_PAGE_SHIFT);
 631         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 632
 633         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 634                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 635
 636         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 637
 638         kvfree(in);
 639
 640         return err;
 641 }
 642
 643 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 644 {
 645         struct mlx5e_channel *c = sq->channel;
 646         struct mlx5e_priv *priv = c->priv;
 647         struct mlx5_core_dev *mdev = priv->mdev;
 648
 649         void *in;
 650         void *sqc;
 651         int inlen;
 652         int err;
 653
 654         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 655         in = mlx5_vzalloc(inlen);
 656         if (!in)
 657                 return -ENOMEM;
 658
 659         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 660
 661         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 662         MLX5_SET(sqc, sqc, state, next_state);
 663
 664         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 665
 666         kvfree(in);
 667
 668         return err;
 669 }
 670
 671 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 672 {
 673         struct mlx5e_channel *c = sq->channel;
 674         struct mlx5e_priv *priv = c->priv;
 675         struct mlx5_core_dev *mdev = priv->mdev;
 676
 677         mlx5_core_destroy_sq(mdev, sq->sqn);
 678 }
 679
 680 static int mlx5e_open_sq(struct mlx5e_channel *c,
 681                          int tc,
 682                          struct mlx5e_sq_param *param,
 683                          struct mlx5e_sq *sq)
 684 {
 685         int err;
 686
 687         err = mlx5e_create_sq(c, tc, param, sq);
 688         if (err)
 689                 return err;
 690
 691         err = mlx5e_enable_sq(sq, param);
 692         if (err)
 693                 goto err_destroy_sq;
 694
 695         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 696         if (err)
 697                 goto err_disable_sq;
 698
 699         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 700         netdev_tx_reset_queue(sq->txq);
 701         netif_tx_start_queue(sq->txq);
 702
 703         return 0;
 704
 705 err_disable_sq:
 706         mlx5e_disable_sq(sq);
 707 err_destroy_sq:
 708         mlx5e_destroy_sq(sq);
 709
 710         return err;
 711 }
 712
 713 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 714 {
 715         __netif_tx_lock_bh(txq);
 716         netif_tx_stop_queue(txq);
 717         __netif_tx_unlock_bh(txq);
 718 }
 719
 720 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 721 {
 722         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 723         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 724         netif_tx_disable_queue(sq->txq);
 725
 726         /* ensure hw is notified of all pending wqes */
 727         if (mlx5e_sq_has_room_for(sq, 1))
 728                 mlx5e_send_nop(sq, true);
 729
 730         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 731         while (sq->cc != sq->pc) /* wait till sq is empty */
 732                 msleep(20);
 733
 734         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 735         napi_synchronize(&sq->channel->napi);
 736
 737         mlx5e_disable_sq(sq);
 738         mlx5e_destroy_sq(sq);
 739 }
 740
 741 static int mlx5e_create_cq(struct mlx5e_channel *c,
 742                            struct mlx5e_cq_param *param,
 743                            struct mlx5e_cq *cq)
 744 {
 745         struct mlx5e_priv *priv = c->priv;
 746         struct mlx5_core_dev *mdev = priv->mdev;
 747         struct mlx5_core_cq *mcq = &cq->mcq;
 748         int eqn_not_used;
 749         unsigned int irqn;
 750         int err;
 751         u32 i;
 752
 753         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 754         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 755         param->eq_ix   = c->ix;
 756
 757         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 758                                &cq->wq_ctrl);
 759         if (err)
 760                 return err;
 761
 762         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 763
 764         cq->napi        = &c->napi;
 765
 766         mcq->cqe_sz     = 64;
 767         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 768         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 769         *mcq->set_ci_db = 0;
 770         *mcq->arm_db    = 0;
 771         mcq->vector     = param->eq_ix;
 772         mcq->comp       = mlx5e_completion_event;
 773         mcq->event      = mlx5e_cq_error_event;
 774         mcq->irqn       = irqn;
 775         mcq->uar        = &priv->cq_uar;
 776
 777         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 778                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 779
 780                 cqe->op_own = 0xf1;
 781         }
 782
 783         cq->channel = c;
 784         cq->priv = priv;
 785
 786         return 0;
 787 }
 788
 789 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 790 {
 791         mlx5_wq_destroy(&cq->wq_ctrl);
 792 }
 793
 794 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 795 {
 796         struct mlx5e_priv *priv = cq->priv;
 797         struct mlx5_core_dev *mdev = priv->mdev;
 798         struct mlx5_core_cq *mcq = &cq->mcq;
 799
 800         void *in;
 801         void *cqc;
 802         int inlen;
 803         unsigned int irqn_not_used;
 804         int eqn;
 805         int err;
 806
 807         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 808                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 809         in = mlx5_vzalloc(inlen);
 810         if (!in)
 811                 return -ENOMEM;
 812
 813         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 814
 815         memcpy(cqc, param->cqc, sizeof(param->cqc));
 816
 817         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 818                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 819
 820         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 821
 822         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 823         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 824         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 825                                             MLX5_ADAPTER_PAGE_SHIFT);
 826         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 827
 828         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 829
 830         kvfree(in);
 831
 832         if (err)
 833                 return err;
 834
 835         mlx5e_cq_arm(cq);
 836
 837         return 0;
 838 }
 839
 840 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 841 {
 842         struct mlx5e_priv *priv = cq->priv;
 843         struct mlx5_core_dev *mdev = priv->mdev;
 844
 845         mlx5_core_destroy_cq(mdev, &cq->mcq);
 846 }
 847
 848 static int mlx5e_open_cq(struct mlx5e_channel *c,
 849                          struct mlx5e_cq_param *param,
 850                          struct mlx5e_cq *cq,
 851                          u16 moderation_usecs,
 852                          u16 moderation_frames)
 853 {
 854         int err;
 855         struct mlx5e_priv *priv = c->priv;
 856         struct mlx5_core_dev *mdev = priv->mdev;
 857
 858         err = mlx5e_create_cq(c, param, cq);
 859         if (err)
 860                 return err;
 861
 862         err = mlx5e_enable_cq(cq, param);
 863         if (err)
 864                 goto err_destroy_cq;
 865
 866         if (MLX5_CAP_GEN(mdev, cq_moderation))
 867                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 868                                                moderation_usecs,
 869                                                moderation_frames);
 870         return 0;
 871
 872 err_destroy_cq:
 873         mlx5e_destroy_cq(cq);
 874
 875         return err;
 876 }
 877
 878 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 879 {
 880         mlx5e_disable_cq(cq);
 881         mlx5e_destroy_cq(cq);
 882 }
 883
 884 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 885 {
 886         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 887 }
 888
 889 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 890                              struct mlx5e_channel_param *cparam)
 891 {
 892         struct mlx5e_priv *priv = c->priv;
 893         int err;
 894         int tc;
 895
 896         for (tc = 0; tc < c->num_tc; tc++) {
 897                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 898                                     priv->params.tx_cq_moderation_usec,
 899                                     priv->params.tx_cq_moderation_pkts);
 900                 if (err)
 901                         goto err_close_tx_cqs;
 902         }
 903
 904         return 0;
 905
 906 err_close_tx_cqs:
 907         for (tc--; tc >= 0; tc--)
 908                 mlx5e_close_cq(&c->sq[tc].cq);
 909
 910         return err;
 911 }
 912
 913 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 914 {
 915         int tc;
 916
 917         for (tc = 0; tc < c->num_tc; tc++)
 918                 mlx5e_close_cq(&c->sq[tc].cq);
 919 }
 920
 921 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 922                           struct mlx5e_channel_param *cparam)
 923 {
 924         int err;
 925         int tc;
 926
 927         for (tc = 0; tc < c->num_tc; tc++) {
 928                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 929                 if (err)
 930                         goto err_close_sqs;
 931         }
 932
 933         return 0;
 934
 935 err_close_sqs:
 936         for (tc--; tc >= 0; tc--)
 937                 mlx5e_close_sq(&c->sq[tc]);
 938
 939         return err;
 940 }
 941
 942 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 943 {
 944         int tc;
 945
 946         for (tc = 0; tc < c->num_tc; tc++)
 947                 mlx5e_close_sq(&c->sq[tc]);
 948 }
 949
 950 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
 951 {
 952         int i;
 953
 954         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
 955                 priv->channeltc_to_txq_map[ix][i] =
 956                         ix + i * priv->params.num_channels;
 957 }
 958
 959 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
 960                               struct mlx5e_channel_param *cparam,
 961                               struct mlx5e_channel **cp)
 962 {
 963         struct net_device *netdev = priv->netdev;
 964         int cpu = mlx5e_get_cpu(priv, ix);
 965         struct mlx5e_channel *c;
 966         int err;
 967
 968         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
 969         if (!c)
 970                 return -ENOMEM;
 971
 972         c->priv     = priv;
 973         c->ix       = ix;
 974         c->cpu      = cpu;
 975         c->pdev     = &priv->mdev->pdev->dev;
 976         c->netdev   = priv->netdev;
 977         c->mkey_be  = cpu_to_be32(priv->mr.key);
 978         c->num_tc   = priv->params.num_tc;
 979
 980         mlx5e_build_channeltc_to_txq_map(priv, ix);
 981
 982         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
 983
 984         err = mlx5e_open_tx_cqs(c, cparam);
 985         if (err)
 986                 goto err_napi_del;
 987
 988         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
 989                             priv->params.rx_cq_moderation_usec,
 990                             priv->params.rx_cq_moderation_pkts);
 991         if (err)
 992                 goto err_close_tx_cqs;
 993
 994         napi_enable(&c->napi);
 995
 996         err = mlx5e_open_sqs(c, cparam);
 997         if (err)
 998                 goto err_disable_napi;
 999
1000         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1001         if (err)
1002                 goto err_close_sqs;
1003
1004         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1005         *cp = c;
1006
1007         return 0;
1008
1009 err_close_sqs:
1010         mlx5e_close_sqs(c);
1011
1012 err_disable_napi:
1013         napi_disable(&c->napi);
1014         mlx5e_close_cq(&c->rq.cq);
1015
1016 err_close_tx_cqs:
1017         mlx5e_close_tx_cqs(c);
1018
1019 err_napi_del:
1020         netif_napi_del(&c->napi);
1021         kfree(c);
1022
1023         return err;
1024 }
1025
1026 static void mlx5e_close_channel(struct mlx5e_channel *c)
1027 {
1028         mlx5e_close_rq(&c->rq);
1029         mlx5e_close_sqs(c);
1030         napi_disable(&c->napi);
1031         mlx5e_close_cq(&c->rq.cq);
1032         mlx5e_close_tx_cqs(c);
1033         netif_napi_del(&c->napi);
1034         kfree(c);
1035 }
1036
1037 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1038                                  struct mlx5e_rq_param *param)
1039 {
1040         void *rqc = param->rqc;
1041         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1042
1043         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
1044         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1045         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1046         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1047         MLX5_SET(wq, wq, pd,               priv->pdn);
1048
1049         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1050         param->wq.linear = 1;
1051 }
1052
1053 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1054                                  struct mlx5e_sq_param *param)
1055 {
1056         void *sqc = param->sqc;
1057         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1058
1059         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1060         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1061         MLX5_SET(wq, wq, pd,            priv->pdn);
1062
1063         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1064         param->max_inline = priv->params.tx_max_inline;
1065 }
1066
1067 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1068                                         struct mlx5e_cq_param *param)
1069 {
1070         void *cqc = param->cqc;
1071
1072         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1073 }
1074
1075 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1076                                     struct mlx5e_cq_param *param)
1077 {
1078         void *cqc = param->cqc;
1079
1080         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1081
1082         mlx5e_build_common_cq_param(priv, param);
1083 }
1084
1085 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1086                                     struct mlx5e_cq_param *param)
1087 {
1088         void *cqc = param->cqc;
1089
1090         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1091
1092         mlx5e_build_common_cq_param(priv, param);
1093 }
1094
1095 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1096                                       struct mlx5e_channel_param *cparam)
1097 {
1098         memset(cparam, 0, sizeof(*cparam));
1099
1100         mlx5e_build_rq_param(priv, &cparam->rq);
1101         mlx5e_build_sq_param(priv, &cparam->sq);
1102         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1103         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1104 }
1105
1106 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1107 {
1108         struct mlx5e_channel_param cparam;
1109         int nch = priv->params.num_channels;
1110         int err = -ENOMEM;
1111         int i;
1112         int j;
1113
1114         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1115                                 GFP_KERNEL);
1116
1117         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1118                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1119
1120         if (!priv->channel || !priv->txq_to_sq_map)
1121                 goto err_free_txq_to_sq_map;
1122
1123         mlx5e_build_channel_param(priv, &cparam);
1124         for (i = 0; i < nch; i++) {
1125                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1126                 if (err)
1127                         goto err_close_channels;
1128         }
1129
1130         for (j = 0; j < nch; j++) {
1131                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1132                 if (err)
1133                         goto err_close_channels;
1134         }
1135
1136         return 0;
1137
1138 err_close_channels:
1139         for (i--; i >= 0; i--)
1140                 mlx5e_close_channel(priv->channel[i]);
1141
1142 err_free_txq_to_sq_map:
1143         kfree(priv->txq_to_sq_map);
1144         kfree(priv->channel);
1145
1146         return err;
1147 }
1148
1149 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1150 {
1151         int i;
1152
1153         for (i = 0; i < priv->params.num_channels; i++)
1154                 mlx5e_close_channel(priv->channel[i]);
1155
1156         kfree(priv->txq_to_sq_map);
1157         kfree(priv->channel);
1158 }
1159
1160 static int mlx5e_rx_hash_fn(int hfunc)
1161 {
1162         return (hfunc == ETH_RSS_HASH_TOP) ?
1163                MLX5_RX_HASH_FN_TOEPLITZ :
1164                MLX5_RX_HASH_FN_INVERTED_XOR8;
1165 }
1166
1167 static int mlx5e_bits_invert(unsigned long a, int size)
1168 {
1169         int inv = 0;
1170         int i;
1171
1172         for (i = 0; i < size; i++)
1173                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1174
1175         return inv;
1176 }
1177
1178 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1179 {
1180         int i;
1181
1182         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1183                 int ix = i;
1184
1185                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1186                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1187
1188                 ix = priv->params.indirection_rqt[ix];
1189                 ix = ix % priv->params.num_channels;
1190                 MLX5_SET(rqtc, rqtc, rq_num[i],
1191                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1192                          priv->channel[ix]->rq.rqn :
1193                          priv->drop_rq.rqn);
1194         }
1195 }
1196
1197 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1198                                 enum mlx5e_rqt_ix rqt_ix)
1199 {
1200
1201         switch (rqt_ix) {
1202         case MLX5E_INDIRECTION_RQT:
1203                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1204
1205                 break;
1206
1207         default: /* MLX5E_SINGLE_RQ_RQT */
1208                 MLX5_SET(rqtc, rqtc, rq_num[0],
1209                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1210                          priv->channel[0]->rq.rqn :
1211                          priv->drop_rq.rqn);
1212
1213                 break;
1214         }
1215 }
1216
1217 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1218 {
1219         struct mlx5_core_dev *mdev = priv->mdev;
1220         u32 *in;
1221         void *rqtc;
1222         int inlen;
1223         int sz;
1224         int err;
1225
1226         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1227
1228         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1229         in = mlx5_vzalloc(inlen);
1230         if (!in)
1231                 return -ENOMEM;
1232
1233         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1234
1235         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1236         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1237
1238         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1239
1240         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1241
1242         kvfree(in);
1243
1244         return err;
1245 }
1246
1247 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1248 {
1249         struct mlx5_core_dev *mdev = priv->mdev;
1250         u32 *in;
1251         void *rqtc;
1252         int inlen;
1253         int sz;
1254         int err;
1255
1256         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1257
1258         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1259         in = mlx5_vzalloc(inlen);
1260         if (!in)
1261                 return -ENOMEM;
1262
1263         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1264
1265         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1266
1267         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1268
1269         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1270
1271         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1272
1273         kvfree(in);
1274
1275         return err;
1276 }
1277
1278 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1279 {
1280         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1281 }
1282
1283 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1284 {
1285         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1286         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1287 }
1288
1289 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1290 {
1291         if (!priv->params.lro_en)
1292                 return;
1293
1294 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1295
1296         MLX5_SET(tirc, tirc, lro_enable_mask,
1297                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1298                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1299         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1300                  (priv->params.lro_wqe_sz -
1301                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1302         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1303                  MLX5_CAP_ETH(priv->mdev,
1304                               lro_timer_supported_periods[2]));
1305 }
1306
1307 static int mlx5e_modify_tir_lro(struct mlx5e_priv *priv, int tt)
1308 {
1309         struct mlx5_core_dev *mdev = priv->mdev;
1310
1311         void *in;
1312         void *tirc;
1313         int inlen;
1314         int err;
1315
1316         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1317         in = mlx5_vzalloc(inlen);
1318         if (!in)
1319                 return -ENOMEM;
1320
1321         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1322         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1323
1324         mlx5e_build_tir_ctx_lro(tirc, priv);
1325
1326         err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1327
1328         kvfree(in);
1329
1330         return err;
1331 }
1332
1333 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1334                                                   u32 tirn)
1335 {
1336         void *in;
1337         int inlen;
1338         int err;
1339
1340         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1341         in = mlx5_vzalloc(inlen);
1342         if (!in)
1343                 return -ENOMEM;
1344
1345         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1346
1347         err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1348
1349         kvfree(in);
1350
1351         return err;
1352 }
1353
1354 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1355 {
1356         int err;
1357         int i;
1358
1359         for (i = 0; i < MLX5E_NUM_TT; i++) {
1360                 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1361                                                              priv->tirn[i]);
1362                 if (err)
1363                         return err;
1364         }
1365
1366         return 0;
1367 }
1368
1369 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1370 {
1371         struct mlx5e_priv *priv = netdev_priv(netdev);
1372         struct mlx5_core_dev *mdev = priv->mdev;
1373         u16 hw_mtu;
1374         int err;
1375
1376         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1377         if (err)
1378                 return err;
1379
1380         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1381
1382         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1383                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1384                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1385
1386         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1387         return 0;
1388 }
1389
1390 int mlx5e_open_locked(struct net_device *netdev)
1391 {
1392         struct mlx5e_priv *priv = netdev_priv(netdev);
1393         int num_txqs;
1394         int err;
1395
1396         set_bit(MLX5E_STATE_OPENED, &priv->state);
1397
1398         num_txqs = priv->params.num_channels * priv->params.num_tc;
1399         netif_set_real_num_tx_queues(netdev, num_txqs);
1400         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1401
1402         err = mlx5e_set_dev_port_mtu(netdev);
1403         if (err)
1404                 goto err_clear_state_opened_flag;
1405
1406         err = mlx5e_open_channels(priv);
1407         if (err) {
1408                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1409                            __func__, err);
1410                 goto err_clear_state_opened_flag;
1411         }
1412
1413         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1414         if (err) {
1415                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1416                            __func__, err);
1417                 goto err_close_channels;
1418         }
1419
1420         mlx5e_update_carrier(priv);
1421         mlx5e_redirect_rqts(priv);
1422
1423         schedule_delayed_work(&priv->update_stats_work, 0);
1424
1425         return 0;
1426
1427 err_close_channels:
1428         mlx5e_close_channels(priv);
1429 err_clear_state_opened_flag:
1430         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1431         return err;
1432 }
1433
1434 static int mlx5e_open(struct net_device *netdev)
1435 {
1436         struct mlx5e_priv *priv = netdev_priv(netdev);
1437         int err;
1438
1439         mutex_lock(&priv->state_lock);
1440         err = mlx5e_open_locked(netdev);
1441         mutex_unlock(&priv->state_lock);
1442
1443         return err;
1444 }
1445
1446 int mlx5e_close_locked(struct net_device *netdev)
1447 {
1448         struct mlx5e_priv *priv = netdev_priv(netdev);
1449
1450         /* May already be CLOSED in case a previous configuration operation
1451          * (e.g RX/TX queue size change) that involves close&open failed.
1452          */
1453         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1454                 return 0;
1455
1456         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1457
1458         mlx5e_redirect_rqts(priv);
1459         netif_carrier_off(priv->netdev);
1460         mlx5e_close_channels(priv);
1461
1462         return 0;
1463 }
1464
1465 static int mlx5e_close(struct net_device *netdev)
1466 {
1467         struct mlx5e_priv *priv = netdev_priv(netdev);
1468         int err;
1469
1470         mutex_lock(&priv->state_lock);
1471         err = mlx5e_close_locked(netdev);
1472         mutex_unlock(&priv->state_lock);
1473
1474         return err;
1475 }
1476
1477 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1478                                 struct mlx5e_rq *rq,
1479                                 struct mlx5e_rq_param *param)
1480 {
1481         struct mlx5_core_dev *mdev = priv->mdev;
1482         void *rqc = param->rqc;
1483         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1484         int err;
1485
1486         param->wq.db_numa_node = param->wq.buf_numa_node;
1487
1488         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1489                                 &rq->wq_ctrl);
1490         if (err)
1491                 return err;
1492
1493         rq->priv = priv;
1494
1495         return 0;
1496 }
1497
1498 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1499                                 struct mlx5e_cq *cq,
1500                                 struct mlx5e_cq_param *param)
1501 {
1502         struct mlx5_core_dev *mdev = priv->mdev;
1503         struct mlx5_core_cq *mcq = &cq->mcq;
1504         int eqn_not_used;
1505         unsigned int irqn;
1506         int err;
1507
1508         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1509                                &cq->wq_ctrl);
1510         if (err)
1511                 return err;
1512
1513         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1514
1515         mcq->cqe_sz     = 64;
1516         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1517         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1518         *mcq->set_ci_db = 0;
1519         *mcq->arm_db    = 0;
1520         mcq->vector     = param->eq_ix;
1521         mcq->comp       = mlx5e_completion_event;
1522         mcq->event      = mlx5e_cq_error_event;
1523         mcq->irqn       = irqn;
1524         mcq->uar        = &priv->cq_uar;
1525
1526         cq->priv = priv;
1527
1528         return 0;
1529 }
1530
1531 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1532 {
1533         struct mlx5e_cq_param cq_param;
1534         struct mlx5e_rq_param rq_param;
1535         struct mlx5e_rq *rq = &priv->drop_rq;
1536         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1537         int err;
1538
1539         memset(&cq_param, 0, sizeof(cq_param));
1540         memset(&rq_param, 0, sizeof(rq_param));
1541         mlx5e_build_rx_cq_param(priv, &cq_param);
1542         mlx5e_build_rq_param(priv, &rq_param);
1543
1544         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1545         if (err)
1546                 return err;
1547
1548         err = mlx5e_enable_cq(cq, &cq_param);
1549         if (err)
1550                 goto err_destroy_cq;
1551
1552         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1553         if (err)
1554                 goto err_disable_cq;
1555
1556         err = mlx5e_enable_rq(rq, &rq_param);
1557         if (err)
1558                 goto err_destroy_rq;
1559
1560         return 0;
1561
1562 err_destroy_rq:
1563         mlx5e_destroy_rq(&priv->drop_rq);
1564
1565 err_disable_cq:
1566         mlx5e_disable_cq(&priv->drop_rq.cq);
1567
1568 err_destroy_cq:
1569         mlx5e_destroy_cq(&priv->drop_rq.cq);
1570
1571         return err;
1572 }
1573
1574 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1575 {
1576         mlx5e_disable_rq(&priv->drop_rq);
1577         mlx5e_destroy_rq(&priv->drop_rq);
1578         mlx5e_disable_cq(&priv->drop_rq.cq);
1579         mlx5e_destroy_cq(&priv->drop_rq.cq);
1580 }
1581
1582 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1583 {
1584         struct mlx5_core_dev *mdev = priv->mdev;
1585         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1586         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1587
1588         memset(in, 0, sizeof(in));
1589
1590         MLX5_SET(tisc, tisc, prio,  tc);
1591         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1592
1593         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1594 }
1595
1596 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1597 {
1598         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1599 }
1600
1601 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1602 {
1603         int err;
1604         int tc;
1605
1606         for (tc = 0; tc < priv->params.num_tc; tc++) {
1607                 err = mlx5e_create_tis(priv, tc);
1608                 if (err)
1609                         goto err_close_tises;
1610         }
1611
1612         return 0;
1613
1614 err_close_tises:
1615         for (tc--; tc >= 0; tc--)
1616                 mlx5e_destroy_tis(priv, tc);
1617
1618         return err;
1619 }
1620
1621 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1622 {
1623         int tc;
1624
1625         for (tc = 0; tc < priv->params.num_tc; tc++)
1626                 mlx5e_destroy_tis(priv, tc);
1627 }
1628
1629 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1630 {
1631         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1632
1633         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1634
1635 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1636                                  MLX5_HASH_FIELD_SEL_DST_IP)
1637
1638 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1639                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1640                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1641                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1642
1643 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1644                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1645                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1646
1647         mlx5e_build_tir_ctx_lro(tirc, priv);
1648
1649         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1650
1651         switch (tt) {
1652         case MLX5E_TT_ANY:
1653                 MLX5_SET(tirc, tirc, indirect_table,
1654                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1655                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1656                 break;
1657         default:
1658                 MLX5_SET(tirc, tirc, indirect_table,
1659                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1660                 MLX5_SET(tirc, tirc, rx_hash_fn,
1661                          mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1662                 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1663                         void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1664                                                      rx_hash_toeplitz_key);
1665                         size_t len = MLX5_FLD_SZ_BYTES(tirc,
1666                                                        rx_hash_toeplitz_key);
1667
1668                         MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1669                         memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1670                 }
1671                 break;
1672         }
1673
1674         switch (tt) {
1675         case MLX5E_TT_IPV4_TCP:
1676                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1677                          MLX5_L3_PROT_TYPE_IPV4);
1678                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1679                          MLX5_L4_PROT_TYPE_TCP);
1680                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1681                          MLX5_HASH_IP_L4PORTS);
1682                 break;
1683
1684         case MLX5E_TT_IPV6_TCP:
1685                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1686                          MLX5_L3_PROT_TYPE_IPV6);
1687                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1688                          MLX5_L4_PROT_TYPE_TCP);
1689                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1690                          MLX5_HASH_IP_L4PORTS);
1691                 break;
1692
1693         case MLX5E_TT_IPV4_UDP:
1694                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1695                          MLX5_L3_PROT_TYPE_IPV4);
1696                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1697                          MLX5_L4_PROT_TYPE_UDP);
1698                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1699                          MLX5_HASH_IP_L4PORTS);
1700                 break;
1701
1702         case MLX5E_TT_IPV6_UDP:
1703                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1704                          MLX5_L3_PROT_TYPE_IPV6);
1705                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1706                          MLX5_L4_PROT_TYPE_UDP);
1707                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1708                          MLX5_HASH_IP_L4PORTS);
1709                 break;
1710
1711         case MLX5E_TT_IPV4_IPSEC_AH:
1712                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1713                          MLX5_L3_PROT_TYPE_IPV4);
1714                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1715                          MLX5_HASH_IP_IPSEC_SPI);
1716                 break;
1717
1718         case MLX5E_TT_IPV6_IPSEC_AH:
1719                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1720                          MLX5_L3_PROT_TYPE_IPV6);
1721                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1722                          MLX5_HASH_IP_IPSEC_SPI);
1723                 break;
1724
1725         case MLX5E_TT_IPV4_IPSEC_ESP:
1726                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1727                          MLX5_L3_PROT_TYPE_IPV4);
1728                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1729                          MLX5_HASH_IP_IPSEC_SPI);
1730                 break;
1731
1732         case MLX5E_TT_IPV6_IPSEC_ESP:
1733                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1734                          MLX5_L3_PROT_TYPE_IPV6);
1735                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1736                          MLX5_HASH_IP_IPSEC_SPI);
1737                 break;
1738
1739         case MLX5E_TT_IPV4:
1740                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1741                          MLX5_L3_PROT_TYPE_IPV4);
1742                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1743                          MLX5_HASH_IP);
1744                 break;
1745
1746         case MLX5E_TT_IPV6:
1747                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1748                          MLX5_L3_PROT_TYPE_IPV6);
1749                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1750                          MLX5_HASH_IP);
1751                 break;
1752         }
1753 }
1754
1755 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1756 {
1757         struct mlx5_core_dev *mdev = priv->mdev;
1758         u32 *in;
1759         void *tirc;
1760         int inlen;
1761         int err;
1762
1763         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1764         in = mlx5_vzalloc(inlen);
1765         if (!in)
1766                 return -ENOMEM;
1767
1768         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1769
1770         mlx5e_build_tir_ctx(priv, tirc, tt);
1771
1772         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1773
1774         kvfree(in);
1775
1776         return err;
1777 }
1778
1779 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1780 {
1781         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1782 }
1783
1784 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1785 {
1786         int err;
1787         int i;
1788
1789         for (i = 0; i < MLX5E_NUM_TT; i++) {
1790                 err = mlx5e_create_tir(priv, i);
1791                 if (err)
1792                         goto err_destroy_tirs;
1793         }
1794
1795         return 0;
1796
1797 err_destroy_tirs:
1798         for (i--; i >= 0; i--)
1799                 mlx5e_destroy_tir(priv, i);
1800
1801         return err;
1802 }
1803
1804 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1805 {
1806         int i;
1807
1808         for (i = 0; i < MLX5E_NUM_TT; i++)
1809                 mlx5e_destroy_tir(priv, i);
1810 }
1811
1812 static struct rtnl_link_stats64 *
1813 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1814 {
1815         struct mlx5e_priv *priv = netdev_priv(dev);
1816         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1817
1818         stats->rx_packets = vstats->rx_packets;
1819         stats->rx_bytes   = vstats->rx_bytes;
1820         stats->tx_packets = vstats->tx_packets;
1821         stats->tx_bytes   = vstats->tx_bytes;
1822         stats->multicast  = vstats->rx_multicast_packets +
1823                             vstats->tx_multicast_packets;
1824         stats->tx_errors  = vstats->tx_error_packets;
1825         stats->rx_errors  = vstats->rx_error_packets;
1826         stats->tx_dropped = vstats->tx_queue_dropped;
1827         stats->rx_crc_errors = 0;
1828         stats->rx_length_errors = 0;
1829
1830         return stats;
1831 }
1832
1833 static void mlx5e_set_rx_mode(struct net_device *dev)
1834 {
1835         struct mlx5e_priv *priv = netdev_priv(dev);
1836
1837         schedule_work(&priv->set_rx_mode_work);
1838 }
1839
1840 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1841 {
1842         struct mlx5e_priv *priv = netdev_priv(netdev);
1843         struct sockaddr *saddr = addr;
1844
1845         if (!is_valid_ether_addr(saddr->sa_data))
1846                 return -EADDRNOTAVAIL;
1847
1848         netif_addr_lock_bh(netdev);
1849         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1850         netif_addr_unlock_bh(netdev);
1851
1852         schedule_work(&priv->set_rx_mode_work);
1853
1854         return 0;
1855 }
1856
1857 static int mlx5e_set_features(struct net_device *netdev,
1858                               netdev_features_t features)
1859 {
1860         struct mlx5e_priv *priv = netdev_priv(netdev);
1861         int err = 0;
1862         netdev_features_t changes = features ^ netdev->features;
1863
1864         mutex_lock(&priv->state_lock);
1865
1866         if (changes & NETIF_F_LRO) {
1867                 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1868
1869                 if (was_opened)
1870                         mlx5e_close_locked(priv->netdev);
1871
1872                 priv->params.lro_en = !!(features & NETIF_F_LRO);
1873                 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV4_TCP);
1874                 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV6_TCP);
1875
1876                 if (was_opened)
1877                         err = mlx5e_open_locked(priv->netdev);
1878         }
1879
1880         mutex_unlock(&priv->state_lock);
1881
1882         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1883                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1884                         mlx5e_enable_vlan_filter(priv);
1885                 else
1886                         mlx5e_disable_vlan_filter(priv);
1887         }
1888
1889         return err;
1890 }
1891
1892 #define MXL5_HW_MIN_MTU 64
1893 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
1894
1895 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1896 {
1897         struct mlx5e_priv *priv = netdev_priv(netdev);
1898         struct mlx5_core_dev *mdev = priv->mdev;
1899         bool was_opened;
1900         u16 max_mtu;
1901         u16 min_mtu;
1902         int err = 0;
1903
1904         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1905
1906         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
1907         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
1908
1909         if (new_mtu > max_mtu || new_mtu < min_mtu) {
1910                 netdev_err(netdev,
1911                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
1912                            __func__, new_mtu, min_mtu, max_mtu);
1913                 return -EINVAL;
1914         }
1915
1916         mutex_lock(&priv->state_lock);
1917
1918         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1919         if (was_opened)
1920                 mlx5e_close_locked(netdev);
1921
1922         netdev->mtu = new_mtu;
1923
1924         if (was_opened)
1925                 err = mlx5e_open_locked(netdev);
1926
1927         mutex_unlock(&priv->state_lock);
1928
1929         return err;
1930 }
1931
1932 static struct net_device_ops mlx5e_netdev_ops = {
1933         .ndo_open                = mlx5e_open,
1934         .ndo_stop                = mlx5e_close,
1935         .ndo_start_xmit          = mlx5e_xmit,
1936         .ndo_get_stats64         = mlx5e_get_stats,
1937         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
1938         .ndo_set_mac_address     = mlx5e_set_mac,
1939         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
1940         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
1941         .ndo_set_features        = mlx5e_set_features,
1942         .ndo_change_mtu          = mlx5e_change_mtu,
1943 };
1944
1945 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1946 {
1947         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1948                 return -ENOTSUPP;
1949         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1950             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1951             !MLX5_CAP_ETH(mdev, csum_cap) ||
1952             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1953             !MLX5_CAP_ETH(mdev, vlan_cap) ||
1954             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
1955             MLX5_CAP_FLOWTABLE(mdev,
1956                                flow_table_properties_nic_receive.max_ft_level)
1957                                < 3) {
1958                 mlx5_core_warn(mdev,
1959                                "Not creating net device, some required device capabilities are missing\n");
1960                 return -ENOTSUPP;
1961         }
1962         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
1963                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
1964         if (!MLX5_CAP_GEN(mdev, cq_moderation))
1965                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
1966
1967         return 0;
1968 }
1969
1970 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
1971 {
1972         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1973
1974         return bf_buf_size -
1975                sizeof(struct mlx5e_tx_wqe) +
1976                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
1977 }
1978
1979 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1980                                     struct net_device *netdev,
1981                                     int num_channels)
1982 {
1983         struct mlx5e_priv *priv = netdev_priv(netdev);
1984         int i;
1985
1986         priv->params.log_sq_size           =
1987                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1988         priv->params.log_rq_size           =
1989                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
1990         priv->params.rx_cq_moderation_usec =
1991                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
1992         priv->params.rx_cq_moderation_pkts =
1993                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
1994         priv->params.tx_cq_moderation_usec =
1995                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
1996         priv->params.tx_cq_moderation_pkts =
1997                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
1998         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
1999         priv->params.min_rx_wqes           =
2000                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2001         priv->params.num_tc                = 1;
2002         priv->params.default_vlan_prio     = 0;
2003         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2004
2005         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2006                             sizeof(priv->params.toeplitz_hash_key));
2007
2008         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++)
2009                 priv->params.indirection_rqt[i] = i % num_channels;
2010
2011         priv->params.lro_wqe_sz            =
2012                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2013
2014         priv->mdev                         = mdev;
2015         priv->netdev                       = netdev;
2016         priv->params.num_channels          = num_channels;
2017         priv->default_vlan_prio            = priv->params.default_vlan_prio;
2018
2019         spin_lock_init(&priv->async_events_spinlock);
2020         mutex_init(&priv->state_lock);
2021
2022         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2023         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2024         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2025 }
2026
2027 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2028 {
2029         struct mlx5e_priv *priv = netdev_priv(netdev);
2030
2031         mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
2032 }
2033
2034 static void mlx5e_build_netdev(struct net_device *netdev)
2035 {
2036         struct mlx5e_priv *priv = netdev_priv(netdev);
2037         struct mlx5_core_dev *mdev = priv->mdev;
2038
2039         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2040
2041         if (priv->params.num_tc > 1)
2042                 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
2043
2044         netdev->netdev_ops        = &mlx5e_netdev_ops;
2045         netdev->watchdog_timeo    = 15 * HZ;
2046
2047         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2048
2049         netdev->vlan_features    |= NETIF_F_SG;
2050         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2051         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2052         netdev->vlan_features    |= NETIF_F_GRO;
2053         netdev->vlan_features    |= NETIF_F_TSO;
2054         netdev->vlan_features    |= NETIF_F_TSO6;
2055         netdev->vlan_features    |= NETIF_F_RXCSUM;
2056         netdev->vlan_features    |= NETIF_F_RXHASH;
2057
2058         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2059                 netdev->vlan_features    |= NETIF_F_LRO;
2060
2061         netdev->hw_features       = netdev->vlan_features;
2062         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2063         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2064         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2065
2066         netdev->features          = netdev->hw_features;
2067         if (!priv->params.lro_en)
2068                 netdev->features  &= ~NETIF_F_LRO;
2069
2070         netdev->features         |= NETIF_F_HIGHDMA;
2071
2072         netdev->priv_flags       |= IFF_UNICAST_FLT;
2073
2074         mlx5e_set_netdev_dev_addr(netdev);
2075 }
2076
2077 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2078                              struct mlx5_core_mr *mr)
2079 {
2080         struct mlx5_core_dev *mdev = priv->mdev;
2081         struct mlx5_create_mkey_mbox_in *in;
2082         int err;
2083
2084         in = mlx5_vzalloc(sizeof(*in));
2085         if (!in)
2086                 return -ENOMEM;
2087
2088         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2089                         MLX5_PERM_LOCAL_READ  |
2090                         MLX5_ACCESS_MODE_PA;
2091         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2092         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2093
2094         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2095                                     NULL);
2096
2097         kvfree(in);
2098
2099         return err;
2100 }
2101
2102 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2103 {
2104         struct net_device *netdev;
2105         struct mlx5e_priv *priv;
2106         int nch = mlx5e_get_max_num_channels(mdev);
2107         int err;
2108
2109         if (mlx5e_check_required_hca_cap(mdev))
2110                 return NULL;
2111
2112         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), nch, nch);
2113         if (!netdev) {
2114                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2115                 return NULL;
2116         }
2117
2118         mlx5e_build_netdev_priv(mdev, netdev, nch);
2119         mlx5e_build_netdev(netdev);
2120
2121         netif_carrier_off(netdev);
2122
2123         priv = netdev_priv(netdev);
2124
2125         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2126         if (err) {
2127                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2128                 goto err_free_netdev;
2129         }
2130
2131         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2132         if (err) {
2133                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2134                 goto err_unmap_free_uar;
2135         }
2136
2137         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2138         if (err) {
2139                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2140                 goto err_dealloc_pd;
2141         }
2142
2143         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2144         if (err) {
2145                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2146                 goto err_dealloc_transport_domain;
2147         }
2148
2149         err = mlx5e_create_tises(priv);
2150         if (err) {
2151                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2152                 goto err_destroy_mkey;
2153         }
2154
2155         err = mlx5e_open_drop_rq(priv);
2156         if (err) {
2157                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2158                 goto err_destroy_tises;
2159         }
2160
2161         err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2162         if (err) {
2163                 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2164                 goto err_close_drop_rq;
2165         }
2166
2167         err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2168         if (err) {
2169                 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2170                 goto err_destroy_rqt_indir;
2171         }
2172
2173         err = mlx5e_create_tirs(priv);
2174         if (err) {
2175                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2176                 goto err_destroy_rqt_single;
2177         }
2178
2179         err = mlx5e_create_flow_tables(priv);
2180         if (err) {
2181                 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2182                 goto err_destroy_tirs;
2183         }
2184
2185         mlx5e_init_eth_addr(priv);
2186
2187         err = register_netdev(netdev);
2188         if (err) {
2189                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2190                 goto err_destroy_flow_tables;
2191         }
2192
2193         mlx5e_enable_async_events(priv);
2194         schedule_work(&priv->set_rx_mode_work);
2195
2196         return priv;
2197
2198 err_destroy_flow_tables:
2199         mlx5e_destroy_flow_tables(priv);
2200
2201 err_destroy_tirs:
2202         mlx5e_destroy_tirs(priv);
2203
2204 err_destroy_rqt_single:
2205         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2206
2207 err_destroy_rqt_indir:
2208         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2209
2210 err_close_drop_rq:
2211         mlx5e_close_drop_rq(priv);
2212
2213 err_destroy_tises:
2214         mlx5e_destroy_tises(priv);
2215
2216 err_destroy_mkey:
2217         mlx5_core_destroy_mkey(mdev, &priv->mr);
2218
2219 err_dealloc_transport_domain:
2220         mlx5_dealloc_transport_domain(mdev, priv->tdn);
2221
2222 err_dealloc_pd:
2223         mlx5_core_dealloc_pd(mdev, priv->pdn);
2224
2225 err_unmap_free_uar:
2226         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2227
2228 err_free_netdev:
2229         free_netdev(netdev);
2230
2231         return NULL;
2232 }
2233
2234 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2235 {
2236         struct mlx5e_priv *priv = vpriv;
2237         struct net_device *netdev = priv->netdev;
2238
2239         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2240
2241         schedule_work(&priv->set_rx_mode_work);
2242         mlx5e_disable_async_events(priv);
2243         flush_scheduled_work();
2244         unregister_netdev(netdev);
2245         mlx5e_destroy_flow_tables(priv);
2246         mlx5e_destroy_tirs(priv);
2247         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2248         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2249         mlx5e_close_drop_rq(priv);
2250         mlx5e_destroy_tises(priv);
2251         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
2252         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
2253         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2254         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2255         free_netdev(netdev);
2256 }
2257
2258 static void *mlx5e_get_netdev(void *vpriv)
2259 {
2260         struct mlx5e_priv *priv = vpriv;
2261
2262         return priv->netdev;
2263 }
2264
2265 static struct mlx5_interface mlx5e_interface = {
2266         .add       = mlx5e_create_netdev,
2267         .remove    = mlx5e_destroy_netdev,
2268         .event     = mlx5e_async_event,
2269         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2270         .get_dev   = mlx5e_get_netdev,
2271 };
2272
2273 void mlx5e_init(void)
2274 {
2275         mlx5_register_interface(&mlx5e_interface);
2276 }
2277
2278 void mlx5e_cleanup(void)
2279 {
2280         mlx5_unregister_interface(&mlx5e_interface);
2281 }