kernel/drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         NUM_LONG_LISTS    = 2,
  58         NUM_MED_LISTS     = 64,
  59         LONG_LIST_SIZE    = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
  60                                 MLX5_CMD_DATA_BLOCK_SIZE,
  61         MED_LIST_SIZE     = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
  62 };
  63
  64 enum {
  65         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  66         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  67         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  68         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  69         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  70         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  71         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  72         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  73         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  74         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  75         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  76 };
  77
  78 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  79                                            struct mlx5_cmd_msg *in,
  80                                            struct mlx5_cmd_msg *out,
  81                                            void *uout, int uout_size,
  82                                            mlx5_cmd_cbk_t cbk,
  83                                            void *context, int page_queue)
  84 {
  85         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  86         struct mlx5_cmd_work_ent *ent;
  87
  88         ent = kzalloc(sizeof(*ent), alloc_flags);
  89         if (!ent)
  90                 return ERR_PTR(-ENOMEM);
  91
  92         ent->in         = in;
  93         ent->out        = out;
  94         ent->uout       = uout;
  95         ent->uout_size  = uout_size;
  96         ent->callback   = cbk;
  97         ent->context    = context;
  98         ent->cmd        = cmd;
  99         ent->page_queue = page_queue;
 100
 101         return ent;
 102 }
 103
 104 static u8 alloc_token(struct mlx5_cmd *cmd)
 105 {
 106         u8 token;
 107
 108         spin_lock(&cmd->token_lock);
 109         cmd->token++;
 110         if (cmd->token == 0)
 111                 cmd->token++;
 112         token = cmd->token;
 113         spin_unlock(&cmd->token_lock);
 114
 115         return token;
 116 }
 117
 118 static int alloc_ent(struct mlx5_cmd *cmd)
 119 {
 120         unsigned long flags;
 121         int ret;
 122
 123         spin_lock_irqsave(&cmd->alloc_lock, flags);
 124         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 125         if (ret < cmd->max_reg_cmds)
 126                 clear_bit(ret, &cmd->bitmask);
 127         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 128
 129         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 130 }
 131
 132 static void free_ent(struct mlx5_cmd *cmd, int idx)
 133 {
 134         unsigned long flags;
 135
 136         spin_lock_irqsave(&cmd->alloc_lock, flags);
 137         set_bit(idx, &cmd->bitmask);
 138         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 139 }
 140
 141 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 142 {
 143         return cmd->cmd_buf + (idx << cmd->log_stride);
 144 }
 145
 146 static u8 xor8_buf(void *buf, size_t offset, int len)
 147 {
 148         u8 *ptr = buf;
 149         u8 sum = 0;
 150         int i;
 151         int end = len + offset;
 152
 153         for (i = offset; i < end; i++)
 154                 sum ^= ptr[i];
 155
 156         return sum;
 157 }
 158
 159 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 160 {
 161         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 162         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
 163
 164         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
 165                 return -EINVAL;
 166
 167         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
 168                 return -EINVAL;
 169
 170         return 0;
 171 }
 172
 173 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
 174 {
 175         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
 176         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 177
 178         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
 179         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
 180 }
 181
 182 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
 183 {
 184         struct mlx5_cmd_mailbox *next = msg->next;
 185         int size = msg->len;
 186         int blen = size - min_t(int, sizeof(msg->first.data), size);
 187         int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
 188                 / MLX5_CMD_DATA_BLOCK_SIZE;
 189         int i = 0;
 190
 191         for (i = 0; i < n && next; i++)  {
 192                 calc_block_sig(next->buf);
 193                 next = next->next;
 194         }
 195 }
 196
 197 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 198 {
 199         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
 200         if (csum) {
 201                 calc_chain_sig(ent->in);
 202                 calc_chain_sig(ent->out);
 203         }
 204 }
 205
 206 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 207 {
 208         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 209         u8 own;
 210
 211         do {
 212                 own = ent->lay->status_own;
 213                 if (!(own & CMD_OWNER_HW)) {
 214                         ent->ret = 0;
 215                         return;
 216                 }
 217                 usleep_range(5000, 10000);
 218         } while (time_before(jiffies, poll_end));
 219
 220         ent->ret = -ETIMEDOUT;
 221 }
 222
 223 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 224 {
 225         kfree(ent);
 226 }
 227
 228
 229 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 230 {
 231         struct mlx5_cmd_mailbox *next = ent->out->next;
 232         int err;
 233         u8 sig;
 234         int size = ent->out->len;
 235         int blen = size - min_t(int, sizeof(ent->out->first.data), size);
 236         int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
 237                 / MLX5_CMD_DATA_BLOCK_SIZE;
 238         int i = 0;
 239
 240         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
 241         if (sig != 0xff)
 242                 return -EINVAL;
 243
 244         for (i = 0; i < n && next; i++) {
 245                 err = verify_block_sig(next->buf);
 246                 if (err)
 247                         return err;
 248
 249                 next = next->next;
 250         }
 251
 252         return 0;
 253 }
 254
 255 static void dump_buf(void *buf, int size, int data_only, int offset)
 256 {
 257         __be32 *p = buf;
 258         int i;
 259
 260         for (i = 0; i < size; i += 16) {
 261                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 262                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 263                          be32_to_cpu(p[3]));
 264                 p += 4;
 265                 offset += 16;
 266         }
 267         if (!data_only)
 268                 pr_debug("\n");
 269 }
 270
 271 enum {
 272         MLX5_DRIVER_STATUS_ABORTED = 0xfe,
 273         MLX5_DRIVER_SYND = 0xbadd00de,
 274 };
 275
 276 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 277                                        u32 *synd, u8 *status)
 278 {
 279         *synd = 0;
 280         *status = 0;
 281
 282         switch (op) {
 283         case MLX5_CMD_OP_TEARDOWN_HCA:
 284         case MLX5_CMD_OP_DISABLE_HCA:
 285         case MLX5_CMD_OP_MANAGE_PAGES:
 286         case MLX5_CMD_OP_DESTROY_MKEY:
 287         case MLX5_CMD_OP_DESTROY_EQ:
 288         case MLX5_CMD_OP_DESTROY_CQ:
 289         case MLX5_CMD_OP_DESTROY_QP:
 290         case MLX5_CMD_OP_DESTROY_PSV:
 291         case MLX5_CMD_OP_DESTROY_SRQ:
 292         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 293         case MLX5_CMD_OP_DESTROY_DCT:
 294         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 295         case MLX5_CMD_OP_DEALLOC_PD:
 296         case MLX5_CMD_OP_DEALLOC_UAR:
 297         case MLX5_CMD_OP_DETTACH_FROM_MCG:
 298         case MLX5_CMD_OP_DEALLOC_XRCD:
 299         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 300         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 301         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 302         case MLX5_CMD_OP_DESTROY_TIR:
 303         case MLX5_CMD_OP_DESTROY_SQ:
 304         case MLX5_CMD_OP_DESTROY_RQ:
 305         case MLX5_CMD_OP_DESTROY_RMP:
 306         case MLX5_CMD_OP_DESTROY_TIS:
 307         case MLX5_CMD_OP_DESTROY_RQT:
 308         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 309         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 310         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 311                 return MLX5_CMD_STAT_OK;
 312
 313         case MLX5_CMD_OP_QUERY_HCA_CAP:
 314         case MLX5_CMD_OP_QUERY_ADAPTER:
 315         case MLX5_CMD_OP_INIT_HCA:
 316         case MLX5_CMD_OP_ENABLE_HCA:
 317         case MLX5_CMD_OP_QUERY_PAGES:
 318         case MLX5_CMD_OP_SET_HCA_CAP:
 319         case MLX5_CMD_OP_QUERY_ISSI:
 320         case MLX5_CMD_OP_SET_ISSI:
 321         case MLX5_CMD_OP_CREATE_MKEY:
 322         case MLX5_CMD_OP_QUERY_MKEY:
 323         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 324         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 325         case MLX5_CMD_OP_CREATE_EQ:
 326         case MLX5_CMD_OP_QUERY_EQ:
 327         case MLX5_CMD_OP_GEN_EQE:
 328         case MLX5_CMD_OP_CREATE_CQ:
 329         case MLX5_CMD_OP_QUERY_CQ:
 330         case MLX5_CMD_OP_MODIFY_CQ:
 331         case MLX5_CMD_OP_CREATE_QP:
 332         case MLX5_CMD_OP_RST2INIT_QP:
 333         case MLX5_CMD_OP_INIT2RTR_QP:
 334         case MLX5_CMD_OP_RTR2RTS_QP:
 335         case MLX5_CMD_OP_RTS2RTS_QP:
 336         case MLX5_CMD_OP_SQERR2RTS_QP:
 337         case MLX5_CMD_OP_2ERR_QP:
 338         case MLX5_CMD_OP_2RST_QP:
 339         case MLX5_CMD_OP_QUERY_QP:
 340         case MLX5_CMD_OP_SQD_RTS_QP:
 341         case MLX5_CMD_OP_INIT2INIT_QP:
 342         case MLX5_CMD_OP_CREATE_PSV:
 343         case MLX5_CMD_OP_CREATE_SRQ:
 344         case MLX5_CMD_OP_QUERY_SRQ:
 345         case MLX5_CMD_OP_ARM_RQ:
 346         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 347         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 348         case MLX5_CMD_OP_ARM_XRC_SRQ:
 349         case MLX5_CMD_OP_CREATE_DCT:
 350         case MLX5_CMD_OP_DRAIN_DCT:
 351         case MLX5_CMD_OP_QUERY_DCT:
 352         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 353         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 354         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 355         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 356         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 357         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 358         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 359         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 360         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 361         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 362         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 363         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 364         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 365         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 366         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 367         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 368         case MLX5_CMD_OP_ALLOC_PD:
 369         case MLX5_CMD_OP_ALLOC_UAR:
 370         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 371         case MLX5_CMD_OP_ACCESS_REG:
 372         case MLX5_CMD_OP_ATTACH_TO_MCG:
 373         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 374         case MLX5_CMD_OP_MAD_IFC:
 375         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 376         case MLX5_CMD_OP_SET_MAD_DEMUX:
 377         case MLX5_CMD_OP_NOP:
 378         case MLX5_CMD_OP_ALLOC_XRCD:
 379         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 380         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 381         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 382         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 383         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 384         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 385         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 386         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 387         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 388         case MLX5_CMD_OP_CREATE_TIR:
 389         case MLX5_CMD_OP_MODIFY_TIR:
 390         case MLX5_CMD_OP_QUERY_TIR:
 391         case MLX5_CMD_OP_CREATE_SQ:
 392         case MLX5_CMD_OP_MODIFY_SQ:
 393         case MLX5_CMD_OP_QUERY_SQ:
 394         case MLX5_CMD_OP_CREATE_RQ:
 395         case MLX5_CMD_OP_MODIFY_RQ:
 396         case MLX5_CMD_OP_QUERY_RQ:
 397         case MLX5_CMD_OP_CREATE_RMP:
 398         case MLX5_CMD_OP_MODIFY_RMP:
 399         case MLX5_CMD_OP_QUERY_RMP:
 400         case MLX5_CMD_OP_CREATE_TIS:
 401         case MLX5_CMD_OP_MODIFY_TIS:
 402         case MLX5_CMD_OP_QUERY_TIS:
 403         case MLX5_CMD_OP_CREATE_RQT:
 404         case MLX5_CMD_OP_MODIFY_RQT:
 405         case MLX5_CMD_OP_QUERY_RQT:
 406         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 407         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 408         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 409         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 410         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 411         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 412                 *status = MLX5_DRIVER_STATUS_ABORTED;
 413                 *synd = MLX5_DRIVER_SYND;
 414                 return -EIO;
 415         default:
 416                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 417                 return -EINVAL;
 418         }
 419 }
 420
 421 const char *mlx5_command_str(int command)
 422 {
 423         switch (command) {
 424         case MLX5_CMD_OP_QUERY_HCA_CAP:
 425                 return "QUERY_HCA_CAP";
 426
 427         case MLX5_CMD_OP_SET_HCA_CAP:
 428                 return "SET_HCA_CAP";
 429
 430         case MLX5_CMD_OP_QUERY_ADAPTER:
 431                 return "QUERY_ADAPTER";
 432
 433         case MLX5_CMD_OP_INIT_HCA:
 434                 return "INIT_HCA";
 435
 436         case MLX5_CMD_OP_TEARDOWN_HCA:
 437                 return "TEARDOWN_HCA";
 438
 439         case MLX5_CMD_OP_ENABLE_HCA:
 440                 return "MLX5_CMD_OP_ENABLE_HCA";
 441
 442         case MLX5_CMD_OP_DISABLE_HCA:
 443                 return "MLX5_CMD_OP_DISABLE_HCA";
 444
 445         case MLX5_CMD_OP_QUERY_PAGES:
 446                 return "QUERY_PAGES";
 447
 448         case MLX5_CMD_OP_MANAGE_PAGES:
 449                 return "MANAGE_PAGES";
 450
 451         case MLX5_CMD_OP_CREATE_MKEY:
 452                 return "CREATE_MKEY";
 453
 454         case MLX5_CMD_OP_QUERY_MKEY:
 455                 return "QUERY_MKEY";
 456
 457         case MLX5_CMD_OP_DESTROY_MKEY:
 458                 return "DESTROY_MKEY";
 459
 460         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 461                 return "QUERY_SPECIAL_CONTEXTS";
 462
 463         case MLX5_CMD_OP_CREATE_EQ:
 464                 return "CREATE_EQ";
 465
 466         case MLX5_CMD_OP_DESTROY_EQ:
 467                 return "DESTROY_EQ";
 468
 469         case MLX5_CMD_OP_QUERY_EQ:
 470                 return "QUERY_EQ";
 471
 472         case MLX5_CMD_OP_CREATE_CQ:
 473                 return "CREATE_CQ";
 474
 475         case MLX5_CMD_OP_DESTROY_CQ:
 476                 return "DESTROY_CQ";
 477
 478         case MLX5_CMD_OP_QUERY_CQ:
 479                 return "QUERY_CQ";
 480
 481         case MLX5_CMD_OP_MODIFY_CQ:
 482                 return "MODIFY_CQ";
 483
 484         case MLX5_CMD_OP_CREATE_QP:
 485                 return "CREATE_QP";
 486
 487         case MLX5_CMD_OP_DESTROY_QP:
 488                 return "DESTROY_QP";
 489
 490         case MLX5_CMD_OP_RST2INIT_QP:
 491                 return "RST2INIT_QP";
 492
 493         case MLX5_CMD_OP_INIT2RTR_QP:
 494                 return "INIT2RTR_QP";
 495
 496         case MLX5_CMD_OP_RTR2RTS_QP:
 497                 return "RTR2RTS_QP";
 498
 499         case MLX5_CMD_OP_RTS2RTS_QP:
 500                 return "RTS2RTS_QP";
 501
 502         case MLX5_CMD_OP_SQERR2RTS_QP:
 503                 return "SQERR2RTS_QP";
 504
 505         case MLX5_CMD_OP_2ERR_QP:
 506                 return "2ERR_QP";
 507
 508         case MLX5_CMD_OP_2RST_QP:
 509                 return "2RST_QP";
 510
 511         case MLX5_CMD_OP_QUERY_QP:
 512                 return "QUERY_QP";
 513
 514         case MLX5_CMD_OP_MAD_IFC:
 515                 return "MAD_IFC";
 516
 517         case MLX5_CMD_OP_INIT2INIT_QP:
 518                 return "INIT2INIT_QP";
 519
 520         case MLX5_CMD_OP_CREATE_PSV:
 521                 return "CREATE_PSV";
 522
 523         case MLX5_CMD_OP_DESTROY_PSV:
 524                 return "DESTROY_PSV";
 525
 526         case MLX5_CMD_OP_CREATE_SRQ:
 527                 return "CREATE_SRQ";
 528
 529         case MLX5_CMD_OP_DESTROY_SRQ:
 530                 return "DESTROY_SRQ";
 531
 532         case MLX5_CMD_OP_QUERY_SRQ:
 533                 return "QUERY_SRQ";
 534
 535         case MLX5_CMD_OP_ARM_RQ:
 536                 return "ARM_RQ";
 537
 538         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 539                 return "CREATE_XRC_SRQ";
 540
 541         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 542                 return "DESTROY_XRC_SRQ";
 543
 544         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 545                 return "QUERY_XRC_SRQ";
 546
 547         case MLX5_CMD_OP_ARM_XRC_SRQ:
 548                 return "ARM_XRC_SRQ";
 549
 550         case MLX5_CMD_OP_ALLOC_PD:
 551                 return "ALLOC_PD";
 552
 553         case MLX5_CMD_OP_DEALLOC_PD:
 554                 return "DEALLOC_PD";
 555
 556         case MLX5_CMD_OP_ALLOC_UAR:
 557                 return "ALLOC_UAR";
 558
 559         case MLX5_CMD_OP_DEALLOC_UAR:
 560                 return "DEALLOC_UAR";
 561
 562         case MLX5_CMD_OP_ATTACH_TO_MCG:
 563                 return "ATTACH_TO_MCG";
 564
 565         case MLX5_CMD_OP_DETTACH_FROM_MCG:
 566                 return "DETTACH_FROM_MCG";
 567
 568         case MLX5_CMD_OP_ALLOC_XRCD:
 569                 return "ALLOC_XRCD";
 570
 571         case MLX5_CMD_OP_DEALLOC_XRCD:
 572                 return "DEALLOC_XRCD";
 573
 574         case MLX5_CMD_OP_ACCESS_REG:
 575                 return "MLX5_CMD_OP_ACCESS_REG";
 576
 577         default: return "unknown command opcode";
 578         }
 579 }
 580
 581 static void dump_command(struct mlx5_core_dev *dev,
 582                          struct mlx5_cmd_work_ent *ent, int input)
 583 {
 584         u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
 585         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 586         struct mlx5_cmd_mailbox *next = msg->next;
 587         int data_only;
 588         u32 offset = 0;
 589         int dump_len;
 590
 591         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 592
 593         if (data_only)
 594                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 595                                    "dump command data %s(0x%x) %s\n",
 596                                    mlx5_command_str(op), op,
 597                                    input ? "INPUT" : "OUTPUT");
 598         else
 599                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 600                               mlx5_command_str(op), op,
 601                               input ? "INPUT" : "OUTPUT");
 602
 603         if (data_only) {
 604                 if (input) {
 605                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 606                         offset += sizeof(ent->lay->in);
 607                 } else {
 608                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 609                         offset += sizeof(ent->lay->out);
 610                 }
 611         } else {
 612                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 613                 offset += sizeof(*ent->lay);
 614         }
 615
 616         while (next && offset < msg->len) {
 617                 if (data_only) {
 618                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 619                         dump_buf(next->buf, dump_len, 1, offset);
 620                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 621                 } else {
 622                         mlx5_core_dbg(dev, "command block:\n");
 623                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 624                         offset += sizeof(struct mlx5_cmd_prot_block);
 625                 }
 626                 next = next->next;
 627         }
 628
 629         if (data_only)
 630                 pr_debug("\n");
 631 }
 632
 633 static void cmd_work_handler(struct work_struct *work)
 634 {
 635         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 636         struct mlx5_cmd *cmd = ent->cmd;
 637         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 638         struct mlx5_cmd_layout *lay;
 639         struct semaphore *sem;
 640         unsigned long flags;
 641
 642         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 643         down(sem);
 644         if (!ent->page_queue) {
 645                 ent->idx = alloc_ent(cmd);
 646                 if (ent->idx < 0) {
 647                         mlx5_core_err(dev, "failed to allocate command entry\n");
 648                         up(sem);
 649                         return;
 650                 }
 651         } else {
 652                 ent->idx = cmd->max_reg_cmds;
 653                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 654                 clear_bit(ent->idx, &cmd->bitmask);
 655                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 656         }
 657
 658         cmd->ent_arr[ent->idx] = ent;
 659         lay = get_inst(cmd, ent->idx);
 660         ent->lay = lay;
 661         memset(lay, 0, sizeof(*lay));
 662         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 663         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 664         if (ent->in->next)
 665                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 666         lay->inlen = cpu_to_be32(ent->in->len);
 667         if (ent->out->next)
 668                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 669         lay->outlen = cpu_to_be32(ent->out->len);
 670         lay->type = MLX5_PCI_CMD_XPORT;
 671         lay->token = ent->token;
 672         lay->status_own = CMD_OWNER_HW;
 673         set_signature(ent, !cmd->checksum_disabled);
 674         dump_command(dev, ent, 1);
 675         ent->ts1 = ktime_get_ns();
 676
 677         /* ring doorbell after the descriptor is valid */
 678         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 679         wmb();
 680         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 681         mmiowb();
 682         /* if not in polling don't use ent after this point */
 683         if (cmd->mode == CMD_MODE_POLLING) {
 684                 poll_timeout(ent);
 685                 /* make sure we read the descriptor after ownership is SW */
 686                 rmb();
 687                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
 688         }
 689 }
 690
 691 static const char *deliv_status_to_str(u8 status)
 692 {
 693         switch (status) {
 694         case MLX5_CMD_DELIVERY_STAT_OK:
 695                 return "no errors";
 696         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 697                 return "signature error";
 698         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 699                 return "token error";
 700         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 701                 return "bad block number";
 702         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 703                 return "output pointer not aligned to block size";
 704         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 705                 return "input pointer not aligned to block size";
 706         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 707                 return "firmware internal error";
 708         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 709                 return "command input length error";
 710         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 711                 return "command ouput length error";
 712         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 713                 return "reserved fields not cleared";
 714         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 715                 return "bad command descriptor type";
 716         default:
 717                 return "unknown status code";
 718         }
 719 }
 720
 721 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 722 {
 723         struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
 724
 725         return be16_to_cpu(hdr->opcode);
 726 }
 727
 728 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 729 {
 730         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 731         struct mlx5_cmd *cmd = &dev->cmd;
 732         int err;
 733
 734         if (cmd->mode == CMD_MODE_POLLING) {
 735                 wait_for_completion(&ent->done);
 736                 err = ent->ret;
 737         } else {
 738                 if (!wait_for_completion_timeout(&ent->done, timeout))
 739                         err = -ETIMEDOUT;
 740                 else
 741                         err = 0;
 742         }
 743         if (err == -ETIMEDOUT) {
 744                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 745                                mlx5_command_str(msg_to_opcode(ent->in)),
 746                                msg_to_opcode(ent->in));
 747         }
 748         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 749                       err, deliv_status_to_str(ent->status), ent->status);
 750
 751         return err;
 752 }
 753
 754 static __be32 *get_synd_ptr(struct mlx5_outbox_hdr *out)
 755 {
 756         return &out->syndrome;
 757 }
 758
 759 static u8 *get_status_ptr(struct mlx5_outbox_hdr *out)
 760 {
 761         return &out->status;
 762 }
 763
 764 /*  Notes:
 765  *    1. Callback functions may not sleep
 766  *    2. page queue commands do not support asynchrous completion
 767  */
 768 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 769                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 770                            mlx5_cmd_cbk_t callback,
 771                            void *context, int page_queue, u8 *status,
 772                            u8 token)
 773 {
 774         struct mlx5_cmd *cmd = &dev->cmd;
 775         struct mlx5_cmd_work_ent *ent;
 776         struct mlx5_cmd_stats *stats;
 777         int err = 0;
 778         s64 ds;
 779         u16 op;
 780
 781         if (callback && page_queue)
 782                 return -EINVAL;
 783
 784         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 785                         page_queue);
 786         if (IS_ERR(ent))
 787                 return PTR_ERR(ent);
 788
 789         ent->token = token;
 790
 791         if (!callback)
 792                 init_completion(&ent->done);
 793
 794         INIT_WORK(&ent->work, cmd_work_handler);
 795         if (page_queue) {
 796                 cmd_work_handler(&ent->work);
 797         } else if (!queue_work(cmd->wq, &ent->work)) {
 798                 mlx5_core_warn(dev, "failed to queue work\n");
 799                 err = -ENOMEM;
 800                 goto out_free;
 801         }
 802
 803         if (!callback) {
 804                 err = wait_func(dev, ent);
 805                 if (err == -ETIMEDOUT)
 806                         goto out;
 807
 808                 ds = ent->ts2 - ent->ts1;
 809                 op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
 810                 if (op < ARRAY_SIZE(cmd->stats)) {
 811                         stats = &cmd->stats[op];
 812                         spin_lock_irq(&stats->lock);
 813                         stats->sum += ds;
 814                         ++stats->n;
 815                         spin_unlock_irq(&stats->lock);
 816                 }
 817                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
 818                                    "fw exec time for %s is %lld nsec\n",
 819                                    mlx5_command_str(op), ds);
 820                 *status = ent->status;
 821                 free_cmd(ent);
 822         }
 823
 824         return err;
 825
 826 out_free:
 827         free_cmd(ent);
 828 out:
 829         return err;
 830 }
 831
 832 static ssize_t dbg_write(struct file *filp, const char __user *buf,
 833                          size_t count, loff_t *pos)
 834 {
 835         struct mlx5_core_dev *dev = filp->private_data;
 836         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 837         char lbuf[3];
 838         int err;
 839
 840         if (!dbg->in_msg || !dbg->out_msg)
 841                 return -ENOMEM;
 842
 843         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
 844                 return -EFAULT;
 845
 846         lbuf[sizeof(lbuf) - 1] = 0;
 847
 848         if (strcmp(lbuf, "go"))
 849                 return -EINVAL;
 850
 851         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
 852
 853         return err ? err : count;
 854 }
 855
 856
 857 static const struct file_operations fops = {
 858         .owner  = THIS_MODULE,
 859         .open   = simple_open,
 860         .write  = dbg_write,
 861 };
 862
 863 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
 864                             u8 token)
 865 {
 866         struct mlx5_cmd_prot_block *block;
 867         struct mlx5_cmd_mailbox *next;
 868         int copy;
 869
 870         if (!to || !from)
 871                 return -ENOMEM;
 872
 873         copy = min_t(int, size, sizeof(to->first.data));
 874         memcpy(to->first.data, from, copy);
 875         size -= copy;
 876         from += copy;
 877
 878         next = to->next;
 879         while (size) {
 880                 if (!next) {
 881                         /* this is a BUG */
 882                         return -ENOMEM;
 883                 }
 884
 885                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 886                 block = next->buf;
 887                 memcpy(block->data, from, copy);
 888                 from += copy;
 889                 size -= copy;
 890                 block->token = token;
 891                 next = next->next;
 892         }
 893
 894         return 0;
 895 }
 896
 897 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
 898 {
 899         struct mlx5_cmd_prot_block *block;
 900         struct mlx5_cmd_mailbox *next;
 901         int copy;
 902
 903         if (!to || !from)
 904                 return -ENOMEM;
 905
 906         copy = min_t(int, size, sizeof(from->first.data));
 907         memcpy(to, from->first.data, copy);
 908         size -= copy;
 909         to += copy;
 910
 911         next = from->next;
 912         while (size) {
 913                 if (!next) {
 914                         /* this is a BUG */
 915                         return -ENOMEM;
 916                 }
 917
 918                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 919                 block = next->buf;
 920
 921                 memcpy(to, block->data, copy);
 922                 to += copy;
 923                 size -= copy;
 924                 next = next->next;
 925         }
 926
 927         return 0;
 928 }
 929
 930 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
 931                                               gfp_t flags)
 932 {
 933         struct mlx5_cmd_mailbox *mailbox;
 934
 935         mailbox = kmalloc(sizeof(*mailbox), flags);
 936         if (!mailbox)
 937                 return ERR_PTR(-ENOMEM);
 938
 939         mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
 940                                       &mailbox->dma);
 941         if (!mailbox->buf) {
 942                 mlx5_core_dbg(dev, "failed allocation\n");
 943                 kfree(mailbox);
 944                 return ERR_PTR(-ENOMEM);
 945         }
 946         memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
 947         mailbox->next = NULL;
 948
 949         return mailbox;
 950 }
 951
 952 static void free_cmd_box(struct mlx5_core_dev *dev,
 953                          struct mlx5_cmd_mailbox *mailbox)
 954 {
 955         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 956         kfree(mailbox);
 957 }
 958
 959 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
 960                                                gfp_t flags, int size,
 961                                                u8 token)
 962 {
 963         struct mlx5_cmd_mailbox *tmp, *head = NULL;
 964         struct mlx5_cmd_prot_block *block;
 965         struct mlx5_cmd_msg *msg;
 966         int blen;
 967         int err;
 968         int n;
 969         int i;
 970
 971         msg = kzalloc(sizeof(*msg), flags);
 972         if (!msg)
 973                 return ERR_PTR(-ENOMEM);
 974
 975         blen = size - min_t(int, sizeof(msg->first.data), size);
 976         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
 977
 978         for (i = 0; i < n; i++) {
 979                 tmp = alloc_cmd_box(dev, flags);
 980                 if (IS_ERR(tmp)) {
 981                         mlx5_core_warn(dev, "failed allocating block\n");
 982                         err = PTR_ERR(tmp);
 983                         goto err_alloc;
 984                 }
 985
 986                 block = tmp->buf;
 987                 tmp->next = head;
 988                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
 989                 block->block_num = cpu_to_be32(n - i - 1);
 990                 block->token = token;
 991                 head = tmp;
 992         }
 993         msg->next = head;
 994         msg->len = size;
 995         return msg;
 996
 997 err_alloc:
 998         while (head) {
 999                 tmp = head->next;
1000                 free_cmd_box(dev, head);
1001                 head = tmp;
1002         }
1003         kfree(msg);
1004
1005         return ERR_PTR(err);
1006 }
1007
1008 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1009                                   struct mlx5_cmd_msg *msg)
1010 {
1011         struct mlx5_cmd_mailbox *head = msg->next;
1012         struct mlx5_cmd_mailbox *next;
1013
1014         while (head) {
1015                 next = head->next;
1016                 free_cmd_box(dev, head);
1017                 head = next;
1018         }
1019         kfree(msg);
1020 }
1021
1022 static ssize_t data_write(struct file *filp, const char __user *buf,
1023                           size_t count, loff_t *pos)
1024 {
1025         struct mlx5_core_dev *dev = filp->private_data;
1026         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1027         void *ptr;
1028         int err;
1029
1030         if (*pos != 0)
1031                 return -EINVAL;
1032
1033         kfree(dbg->in_msg);
1034         dbg->in_msg = NULL;
1035         dbg->inlen = 0;
1036
1037         ptr = kzalloc(count, GFP_KERNEL);
1038         if (!ptr)
1039                 return -ENOMEM;
1040
1041         if (copy_from_user(ptr, buf, count)) {
1042                 err = -EFAULT;
1043                 goto out;
1044         }
1045         dbg->in_msg = ptr;
1046         dbg->inlen = count;
1047
1048         *pos = count;
1049
1050         return count;
1051
1052 out:
1053         kfree(ptr);
1054         return err;
1055 }
1056
1057 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1058                          loff_t *pos)
1059 {
1060         struct mlx5_core_dev *dev = filp->private_data;
1061         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1062         int copy;
1063
1064         if (*pos)
1065                 return 0;
1066
1067         if (!dbg->out_msg)
1068                 return -ENOMEM;
1069
1070         copy = min_t(int, count, dbg->outlen);
1071         if (copy_to_user(buf, dbg->out_msg, copy))
1072                 return -EFAULT;
1073
1074         *pos += copy;
1075
1076         return copy;
1077 }
1078
1079 static const struct file_operations dfops = {
1080         .owner  = THIS_MODULE,
1081         .open   = simple_open,
1082         .write  = data_write,
1083         .read   = data_read,
1084 };
1085
1086 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1087                            loff_t *pos)
1088 {
1089         struct mlx5_core_dev *dev = filp->private_data;
1090         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1091         char outlen[8];
1092         int err;
1093
1094         if (*pos)
1095                 return 0;
1096
1097         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1098         if (err < 0)
1099                 return err;
1100
1101         if (copy_to_user(buf, &outlen, err))
1102                 return -EFAULT;
1103
1104         *pos += err;
1105
1106         return err;
1107 }
1108
1109 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1110                             size_t count, loff_t *pos)
1111 {
1112         struct mlx5_core_dev *dev = filp->private_data;
1113         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1114         char outlen_str[8];
1115         int outlen;
1116         void *ptr;
1117         int err;
1118
1119         if (*pos != 0 || count > 6)
1120                 return -EINVAL;
1121
1122         kfree(dbg->out_msg);
1123         dbg->out_msg = NULL;
1124         dbg->outlen = 0;
1125
1126         if (copy_from_user(outlen_str, buf, count))
1127                 return -EFAULT;
1128
1129         outlen_str[7] = 0;
1130
1131         err = sscanf(outlen_str, "%d", &outlen);
1132         if (err < 0)
1133                 return err;
1134
1135         ptr = kzalloc(outlen, GFP_KERNEL);
1136         if (!ptr)
1137                 return -ENOMEM;
1138
1139         dbg->out_msg = ptr;
1140         dbg->outlen = outlen;
1141
1142         *pos = count;
1143
1144         return count;
1145 }
1146
1147 static const struct file_operations olfops = {
1148         .owner  = THIS_MODULE,
1149         .open   = simple_open,
1150         .write  = outlen_write,
1151         .read   = outlen_read,
1152 };
1153
1154 static void set_wqname(struct mlx5_core_dev *dev)
1155 {
1156         struct mlx5_cmd *cmd = &dev->cmd;
1157
1158         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1159                  dev_name(&dev->pdev->dev));
1160 }
1161
1162 static void clean_debug_files(struct mlx5_core_dev *dev)
1163 {
1164         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1165
1166         if (!mlx5_debugfs_root)
1167                 return;
1168
1169         mlx5_cmdif_debugfs_cleanup(dev);
1170         debugfs_remove_recursive(dbg->dbg_root);
1171 }
1172
1173 static int create_debugfs_files(struct mlx5_core_dev *dev)
1174 {
1175         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1176         int err = -ENOMEM;
1177
1178         if (!mlx5_debugfs_root)
1179                 return 0;
1180
1181         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1182         if (!dbg->dbg_root)
1183                 return err;
1184
1185         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1186                                           dev, &dfops);
1187         if (!dbg->dbg_in)
1188                 goto err_dbg;
1189
1190         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1191                                            dev, &dfops);
1192         if (!dbg->dbg_out)
1193                 goto err_dbg;
1194
1195         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1196                                               dev, &olfops);
1197         if (!dbg->dbg_outlen)
1198                 goto err_dbg;
1199
1200         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1201                                             &dbg->status);
1202         if (!dbg->dbg_status)
1203                 goto err_dbg;
1204
1205         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1206         if (!dbg->dbg_run)
1207                 goto err_dbg;
1208
1209         mlx5_cmdif_debugfs_init(dev);
1210
1211         return 0;
1212
1213 err_dbg:
1214         clean_debug_files(dev);
1215         return err;
1216 }
1217
1218 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1219 {
1220         struct mlx5_cmd *cmd = &dev->cmd;
1221         int i;
1222
1223         for (i = 0; i < cmd->max_reg_cmds; i++)
1224                 down(&cmd->sem);
1225
1226         down(&cmd->pages_sem);
1227
1228         flush_workqueue(cmd->wq);
1229
1230         cmd->mode = CMD_MODE_EVENTS;
1231
1232         up(&cmd->pages_sem);
1233         for (i = 0; i < cmd->max_reg_cmds; i++)
1234                 up(&cmd->sem);
1235 }
1236
1237 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1238 {
1239         struct mlx5_cmd *cmd = &dev->cmd;
1240         int i;
1241
1242         for (i = 0; i < cmd->max_reg_cmds; i++)
1243                 down(&cmd->sem);
1244
1245         down(&cmd->pages_sem);
1246
1247         flush_workqueue(cmd->wq);
1248         cmd->mode = CMD_MODE_POLLING;
1249
1250         up(&cmd->pages_sem);
1251         for (i = 0; i < cmd->max_reg_cmds; i++)
1252                 up(&cmd->sem);
1253 }
1254
1255 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1256 {
1257         unsigned long flags;
1258
1259         if (msg->cache) {
1260                 spin_lock_irqsave(&msg->cache->lock, flags);
1261                 list_add_tail(&msg->list, &msg->cache->head);
1262                 spin_unlock_irqrestore(&msg->cache->lock, flags);
1263         } else {
1264                 mlx5_free_cmd_msg(dev, msg);
1265         }
1266 }
1267
1268 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
1269 {
1270         struct mlx5_cmd *cmd = &dev->cmd;
1271         struct mlx5_cmd_work_ent *ent;
1272         mlx5_cmd_cbk_t callback;
1273         void *context;
1274         int err;
1275         int i;
1276         s64 ds;
1277         struct mlx5_cmd_stats *stats;
1278         unsigned long flags;
1279         unsigned long vector;
1280
1281         /* there can be at most 32 command queues */
1282         vector = vec & 0xffffffff;
1283         for (i = 0; i < (1 << cmd->log_sz); i++) {
1284                 if (test_bit(i, &vector)) {
1285                         struct semaphore *sem;
1286
1287                         ent = cmd->ent_arr[i];
1288                         if (ent->page_queue)
1289                                 sem = &cmd->pages_sem;
1290                         else
1291                                 sem = &cmd->sem;
1292                         ent->ts2 = ktime_get_ns();
1293                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1294                         dump_command(dev, ent, 0);
1295                         if (!ent->ret) {
1296                                 if (!cmd->checksum_disabled)
1297                                         ent->ret = verify_signature(ent);
1298                                 else
1299                                         ent->ret = 0;
1300                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1301                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1302                                 else
1303                                         ent->status = ent->lay->status_own >> 1;
1304
1305                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1306                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1307                         }
1308                         free_ent(cmd, ent->idx);
1309
1310                         if (ent->callback) {
1311                                 ds = ent->ts2 - ent->ts1;
1312                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1313                                         stats = &cmd->stats[ent->op];
1314                                         spin_lock_irqsave(&stats->lock, flags);
1315                                         stats->sum += ds;
1316                                         ++stats->n;
1317                                         spin_unlock_irqrestore(&stats->lock, flags);
1318                                 }
1319
1320                                 callback = ent->callback;
1321                                 context = ent->context;
1322                                 err = ent->ret;
1323                                 if (!err)
1324                                         err = mlx5_copy_from_msg(ent->uout,
1325                                                                  ent->out,
1326                                                                  ent->uout_size);
1327
1328                                 mlx5_free_cmd_msg(dev, ent->out);
1329                                 free_msg(dev, ent->in);
1330
1331                                 err = err ? err : ent->status;
1332                                 free_cmd(ent);
1333                                 callback(err, context);
1334                         } else {
1335                                 complete(&ent->done);
1336                         }
1337                         up(sem);
1338                 }
1339         }
1340 }
1341 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1342
1343 static int status_to_err(u8 status)
1344 {
1345         return status ? -1 : 0; /* TBD more meaningful codes */
1346 }
1347
1348 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1349                                       gfp_t gfp)
1350 {
1351         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1352         struct mlx5_cmd *cmd = &dev->cmd;
1353         struct cache_ent *ent = NULL;
1354
1355         if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1356                 ent = &cmd->cache.large;
1357         else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1358                 ent = &cmd->cache.med;
1359
1360         if (ent) {
1361                 spin_lock_irq(&ent->lock);
1362                 if (!list_empty(&ent->head)) {
1363                         msg = list_entry(ent->head.next, typeof(*msg), list);
1364                         /* For cached lists, we must explicitly state what is
1365                          * the real size
1366                          */
1367                         msg->len = in_size;
1368                         list_del(&msg->list);
1369                 }
1370                 spin_unlock_irq(&ent->lock);
1371         }
1372
1373         if (IS_ERR(msg))
1374                 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1375
1376         return msg;
1377 }
1378
1379 static u16 opcode_from_in(struct mlx5_inbox_hdr *in)
1380 {
1381         return be16_to_cpu(in->opcode);
1382 }
1383
1384 static int is_manage_pages(struct mlx5_inbox_hdr *in)
1385 {
1386         return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1387 }
1388
1389 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1390                     int out_size, mlx5_cmd_cbk_t callback, void *context)
1391 {
1392         struct mlx5_cmd_msg *inb;
1393         struct mlx5_cmd_msg *outb;
1394         int pages_queue;
1395         gfp_t gfp;
1396         int err;
1397         u8 status = 0;
1398         u32 drv_synd;
1399         u8 token;
1400
1401         if (pci_channel_offline(dev->pdev) ||
1402             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1403                 err = mlx5_internal_err_ret_value(dev, opcode_from_in(in), &drv_synd, &status);
1404                 *get_synd_ptr(out) = cpu_to_be32(drv_synd);
1405                 *get_status_ptr(out) = status;
1406                 return err;
1407         }
1408
1409         pages_queue = is_manage_pages(in);
1410         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1411
1412         inb = alloc_msg(dev, in_size, gfp);
1413         if (IS_ERR(inb)) {
1414                 err = PTR_ERR(inb);
1415                 return err;
1416         }
1417
1418         token = alloc_token(&dev->cmd);
1419
1420         err = mlx5_copy_to_msg(inb, in, in_size, token);
1421         if (err) {
1422                 mlx5_core_warn(dev, "err %d\n", err);
1423                 goto out_in;
1424         }
1425
1426         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1427         if (IS_ERR(outb)) {
1428                 err = PTR_ERR(outb);
1429                 goto out_in;
1430         }
1431
1432         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1433                               pages_queue, &status, token);
1434         if (err)
1435                 goto out_out;
1436
1437         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1438         if (status) {
1439                 err = status_to_err(status);
1440                 goto out_out;
1441         }
1442
1443         if (!callback)
1444                 err = mlx5_copy_from_msg(out, outb, out_size);
1445
1446 out_out:
1447         if (!callback)
1448                 mlx5_free_cmd_msg(dev, outb);
1449
1450 out_in:
1451         if (!callback)
1452                 free_msg(dev, inb);
1453         return err;
1454 }
1455
1456 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1457                   int out_size)
1458 {
1459         return cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1460 }
1461 EXPORT_SYMBOL(mlx5_cmd_exec);
1462
1463 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1464                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1465                      void *context)
1466 {
1467         return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1468 }
1469 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1470
1471 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1472 {
1473         struct mlx5_cmd *cmd = &dev->cmd;
1474         struct mlx5_cmd_msg *msg;
1475         struct mlx5_cmd_msg *n;
1476
1477         list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1478                 list_del(&msg->list);
1479                 mlx5_free_cmd_msg(dev, msg);
1480         }
1481
1482         list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1483                 list_del(&msg->list);
1484                 mlx5_free_cmd_msg(dev, msg);
1485         }
1486 }
1487
1488 static int create_msg_cache(struct mlx5_core_dev *dev)
1489 {
1490         struct mlx5_cmd *cmd = &dev->cmd;
1491         struct mlx5_cmd_msg *msg;
1492         int err;
1493         int i;
1494
1495         spin_lock_init(&cmd->cache.large.lock);
1496         INIT_LIST_HEAD(&cmd->cache.large.head);
1497         spin_lock_init(&cmd->cache.med.lock);
1498         INIT_LIST_HEAD(&cmd->cache.med.head);
1499
1500         for (i = 0; i < NUM_LONG_LISTS; i++) {
1501                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE, 0);
1502                 if (IS_ERR(msg)) {
1503                         err = PTR_ERR(msg);
1504                         goto ex_err;
1505                 }
1506                 msg->cache = &cmd->cache.large;
1507                 list_add_tail(&msg->list, &cmd->cache.large.head);
1508         }
1509
1510         for (i = 0; i < NUM_MED_LISTS; i++) {
1511                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE, 0);
1512                 if (IS_ERR(msg)) {
1513                         err = PTR_ERR(msg);
1514                         goto ex_err;
1515                 }
1516                 msg->cache = &cmd->cache.med;
1517                 list_add_tail(&msg->list, &cmd->cache.med.head);
1518         }
1519
1520         return 0;
1521
1522 ex_err:
1523         destroy_msg_cache(dev);
1524         return err;
1525 }
1526
1527 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1528 {
1529         struct device *ddev = &dev->pdev->dev;
1530
1531         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1532                                                  &cmd->alloc_dma, GFP_KERNEL);
1533         if (!cmd->cmd_alloc_buf)
1534                 return -ENOMEM;
1535
1536         /* make sure it is aligned to 4K */
1537         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1538                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1539                 cmd->dma = cmd->alloc_dma;
1540                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1541                 return 0;
1542         }
1543
1544         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1545                           cmd->alloc_dma);
1546         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1547                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1548                                                  &cmd->alloc_dma, GFP_KERNEL);
1549         if (!cmd->cmd_alloc_buf)
1550                 return -ENOMEM;
1551
1552         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1553         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1554         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1555         return 0;
1556 }
1557
1558 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1559 {
1560         struct device *ddev = &dev->pdev->dev;
1561
1562         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1563                           cmd->alloc_dma);
1564 }
1565
1566 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1567 {
1568         int size = sizeof(struct mlx5_cmd_prot_block);
1569         int align = roundup_pow_of_two(size);
1570         struct mlx5_cmd *cmd = &dev->cmd;
1571         u32 cmd_h, cmd_l;
1572         u16 cmd_if_rev;
1573         int err;
1574         int i;
1575
1576         memset(cmd, 0, sizeof(*cmd));
1577         cmd_if_rev = cmdif_rev(dev);
1578         if (cmd_if_rev != CMD_IF_REV) {
1579                 dev_err(&dev->pdev->dev,
1580                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1581                         CMD_IF_REV, cmd_if_rev);
1582                 return -EINVAL;
1583         }
1584
1585         cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1586         if (!cmd->pool)
1587                 return -ENOMEM;
1588
1589         err = alloc_cmd_page(dev, cmd);
1590         if (err)
1591                 goto err_free_pool;
1592
1593         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1594         cmd->log_sz = cmd_l >> 4 & 0xf;
1595         cmd->log_stride = cmd_l & 0xf;
1596         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1597                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1598                         1 << cmd->log_sz);
1599                 err = -EINVAL;
1600                 goto err_free_page;
1601         }
1602
1603         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1604                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1605                 err = -EINVAL;
1606                 goto err_free_page;
1607         }
1608
1609         cmd->checksum_disabled = 1;
1610         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1611         cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1612
1613         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1614         if (cmd->cmdif_rev > CMD_IF_REV) {
1615                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1616                         CMD_IF_REV, cmd->cmdif_rev);
1617                 err = -ENOTSUPP;
1618                 goto err_free_page;
1619         }
1620
1621         spin_lock_init(&cmd->alloc_lock);
1622         spin_lock_init(&cmd->token_lock);
1623         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1624                 spin_lock_init(&cmd->stats[i].lock);
1625
1626         sema_init(&cmd->sem, cmd->max_reg_cmds);
1627         sema_init(&cmd->pages_sem, 1);
1628
1629         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1630         cmd_l = (u32)(cmd->dma);
1631         if (cmd_l & 0xfff) {
1632                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1633                 err = -ENOMEM;
1634                 goto err_free_page;
1635         }
1636
1637         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1638         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1639
1640         /* Make sure firmware sees the complete address before we proceed */
1641         wmb();
1642
1643         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1644
1645         cmd->mode = CMD_MODE_POLLING;
1646
1647         err = create_msg_cache(dev);
1648         if (err) {
1649                 dev_err(&dev->pdev->dev, "failed to create command cache\n");
1650                 goto err_free_page;
1651         }
1652
1653         set_wqname(dev);
1654         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1655         if (!cmd->wq) {
1656                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1657                 err = -ENOMEM;
1658                 goto err_cache;
1659         }
1660
1661         err = create_debugfs_files(dev);
1662         if (err) {
1663                 err = -ENOMEM;
1664                 goto err_wq;
1665         }
1666
1667         return 0;
1668
1669 err_wq:
1670         destroy_workqueue(cmd->wq);
1671
1672 err_cache:
1673         destroy_msg_cache(dev);
1674
1675 err_free_page:
1676         free_cmd_page(dev, cmd);
1677
1678 err_free_pool:
1679         pci_pool_destroy(cmd->pool);
1680
1681         return err;
1682 }
1683 EXPORT_SYMBOL(mlx5_cmd_init);
1684
1685 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1686 {
1687         struct mlx5_cmd *cmd = &dev->cmd;
1688
1689         clean_debug_files(dev);
1690         destroy_workqueue(cmd->wq);
1691         destroy_msg_cache(dev);
1692         free_cmd_page(dev, cmd);
1693         pci_pool_destroy(cmd->pool);
1694 }
1695 EXPORT_SYMBOL(mlx5_cmd_cleanup);
1696
1697 static const char *cmd_status_str(u8 status)
1698 {
1699         switch (status) {
1700         case MLX5_CMD_STAT_OK:
1701                 return "OK";
1702         case MLX5_CMD_STAT_INT_ERR:
1703                 return "internal error";
1704         case MLX5_CMD_STAT_BAD_OP_ERR:
1705                 return "bad operation";
1706         case MLX5_CMD_STAT_BAD_PARAM_ERR:
1707                 return "bad parameter";
1708         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1709                 return "bad system state";
1710         case MLX5_CMD_STAT_BAD_RES_ERR:
1711                 return "bad resource";
1712         case MLX5_CMD_STAT_RES_BUSY:
1713                 return "resource busy";
1714         case MLX5_CMD_STAT_LIM_ERR:
1715                 return "limits exceeded";
1716         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1717                 return "bad resource state";
1718         case MLX5_CMD_STAT_IX_ERR:
1719                 return "bad index";
1720         case MLX5_CMD_STAT_NO_RES_ERR:
1721                 return "no resources";
1722         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1723                 return "bad input length";
1724         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1725                 return "bad output length";
1726         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1727                 return "bad QP state";
1728         case MLX5_CMD_STAT_BAD_PKT_ERR:
1729                 return "bad packet (discarded)";
1730         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1731                 return "bad size too many outstanding CQEs";
1732         default:
1733                 return "unknown status";
1734         }
1735 }
1736
1737 static int cmd_status_to_err(u8 status)
1738 {
1739         switch (status) {
1740         case MLX5_CMD_STAT_OK:                          return 0;
1741         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
1742         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
1743         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
1744         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
1745         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
1746         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
1747         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
1748         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
1749         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
1750         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
1751         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
1752         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
1753         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
1754         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
1755         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
1756         default:                                        return -EIO;
1757         }
1758 }
1759
1760 /* this will be available till all the commands use set/get macros */
1761 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1762 {
1763         if (!hdr->status)
1764                 return 0;
1765
1766         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1767                 cmd_status_str(hdr->status), hdr->status,
1768                 be32_to_cpu(hdr->syndrome));
1769
1770         return cmd_status_to_err(hdr->status);
1771 }
1772
1773 int mlx5_cmd_status_to_err_v2(void *ptr)
1774 {
1775         u32     syndrome;
1776         u8      status;
1777
1778         status = be32_to_cpu(*(__be32 *)ptr) >> 24;
1779         if (!status)
1780                 return 0;
1781
1782         syndrome = be32_to_cpu(*(__be32 *)(ptr + 4));
1783
1784         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1785                 cmd_status_str(status), status, syndrome);
1786
1787         return cmd_status_to_err(status);
1788 }