kernel/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2  *
   3  *  Intel 10 Gigabit PCI Express Linux driver
   4  *  Copyright(c) 1999 - 2014 Intel Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms and conditions of the GNU General Public License,
   8  *  version 2, as published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  *  more details.
  14  *
  15  *  The full GNU General Public License is included in this distribution in
  16  *  the file called "COPYING".
  17  *
  18  *  Contact Information:
  19  *  Linux NICS <linux.nics@intel.com>
  20  *  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  *  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  *
  23  ******************************************************************************/
  24 #include "ixgbe_x540.h"
  25 #include "ixgbe_type.h"
  26 #include "ixgbe_common.h"
  27 #include "ixgbe_phy.h"
  28
  29 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
  30  *  @hw: pointer to hardware structure
  31  *
  32  *  Returns error code
  33  */
  34 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
  35 {
  36         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  37
  38         switch (hw->device_id) {
  39         case IXGBE_DEV_ID_X550EM_X_SFP:
  40                 /* set up for CS4227 usage */
  41                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
  42                 if (hw->bus.lan_id) {
  43                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  44                         esdp |= IXGBE_ESDP_SDP1_DIR;
  45                 }
  46                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  47                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  48
  49                 return ixgbe_identify_module_generic(hw);
  50         case IXGBE_DEV_ID_X550EM_X_KX4:
  51                 hw->phy.type = ixgbe_phy_x550em_kx4;
  52                 break;
  53         case IXGBE_DEV_ID_X550EM_X_KR:
  54                 hw->phy.type = ixgbe_phy_x550em_kr;
  55                 break;
  56         case IXGBE_DEV_ID_X550EM_X_1G_T:
  57         case IXGBE_DEV_ID_X550EM_X_10G_T:
  58                 return ixgbe_identify_phy_generic(hw);
  59         default:
  60                 break;
  61         }
  62         return 0;
  63 }
  64
  65 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
  66                                      u32 device_type, u16 *phy_data)
  67 {
  68         return IXGBE_NOT_IMPLEMENTED;
  69 }
  70
  71 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
  72                                       u32 device_type, u16 phy_data)
  73 {
  74         return IXGBE_NOT_IMPLEMENTED;
  75 }
  76
  77 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
  78  *  @hw: pointer to hardware structure
  79  *
  80  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
  81  *  ixgbe_hw struct in order to set up EEPROM access.
  82  **/
  83 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
  84 {
  85         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  86         u32 eec;
  87         u16 eeprom_size;
  88
  89         if (eeprom->type == ixgbe_eeprom_uninitialized) {
  90                 eeprom->semaphore_delay = 10;
  91                 eeprom->type = ixgbe_flash;
  92
  93                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
  94                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
  95                                     IXGBE_EEC_SIZE_SHIFT);
  96                 eeprom->word_size = 1 << (eeprom_size +
  97                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
  98
  99                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 100                        eeprom->type, eeprom->word_size);
 101         }
 102
 103         return 0;
 104 }
 105
 106 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
 107  *  IOSF device
 108  *  @hw: pointer to hardware structure
 109  *  @reg_addr: 32 bit PHY register to write
 110  *  @device_type: 3 bit device type
 111  *  @phy_data: Pointer to read data from the register
 112  **/
 113 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 114                                        u32 device_type, u32 *data)
 115 {
 116         u32 i, command, error;
 117
 118         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 119                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 120
 121         /* Write IOSF control register */
 122         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 123
 124         /* Check every 10 usec to see if the address cycle completed.
 125          * The SB IOSF BUSY bit will clear when the operation is
 126          * complete
 127          */
 128         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 129                 usleep_range(10, 20);
 130
 131                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 132                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 133                         break;
 134         }
 135
 136         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 137                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 138                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 139                 hw_dbg(hw, "Failed to read, error %x\n", error);
 140                 return IXGBE_ERR_PHY;
 141         }
 142
 143         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 144                 hw_dbg(hw, "Read timed out\n");
 145                 return IXGBE_ERR_PHY;
 146         }
 147
 148         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 149
 150         return 0;
 151 }
 152
 153 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
 154  *  command assuming that the semaphore is already obtained.
 155  *  @hw: pointer to hardware structure
 156  *  @offset: offset of  word in the EEPROM to read
 157  *  @data: word read from the EEPROM
 158  *
 159  *  Reads a 16 bit word from the EEPROM using the hostif.
 160  **/
 161 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 162                                           u16 *data)
 163 {
 164         s32 status;
 165         struct ixgbe_hic_read_shadow_ram buffer;
 166
 167         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 168         buffer.hdr.req.buf_lenh = 0;
 169         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 170         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 171
 172         /* convert offset from words to bytes */
 173         buffer.address = cpu_to_be32(offset * 2);
 174         /* one word */
 175         buffer.length = cpu_to_be16(sizeof(u16));
 176
 177         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 178                                               sizeof(buffer),
 179                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 180         if (status)
 181                 return status;
 182
 183         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
 184                                           FW_NVM_DATA_OFFSET);
 185
 186         return 0;
 187 }
 188
 189 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
 190  *  @hw: pointer to hardware structure
 191  *  @offset: offset of  word in the EEPROM to read
 192  *  @words: number of words
 193  *  @data: word(s) read from the EEPROM
 194  *
 195  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
 196  **/
 197 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 198                                             u16 offset, u16 words, u16 *data)
 199 {
 200         struct ixgbe_hic_read_shadow_ram buffer;
 201         u32 current_word = 0;
 202         u16 words_to_read;
 203         s32 status;
 204         u32 i;
 205
 206         /* Take semaphore for the entire operation. */
 207         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 208         if (status) {
 209                 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
 210                 return status;
 211         }
 212
 213         while (words) {
 214                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
 215                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
 216                 else
 217                         words_to_read = words;
 218
 219                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 220                 buffer.hdr.req.buf_lenh = 0;
 221                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 222                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 223
 224                 /* convert offset from words to bytes */
 225                 buffer.address = cpu_to_be32((offset + current_word) * 2);
 226                 buffer.length = cpu_to_be16(words_to_read * 2);
 227
 228                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 229                                                       sizeof(buffer),
 230                                                       IXGBE_HI_COMMAND_TIMEOUT,
 231                                                       false);
 232                 if (status) {
 233                         hw_dbg(hw, "Host interface command failed\n");
 234                         goto out;
 235                 }
 236
 237                 for (i = 0; i < words_to_read; i++) {
 238                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
 239                                   2 * i;
 240                         u32 value = IXGBE_READ_REG(hw, reg);
 241
 242                         data[current_word] = (u16)(value & 0xffff);
 243                         current_word++;
 244                         i++;
 245                         if (i < words_to_read) {
 246                                 value >>= 16;
 247                                 data[current_word] = (u16)(value & 0xffff);
 248                                 current_word++;
 249                         }
 250                 }
 251                 words -= words_to_read;
 252         }
 253
 254 out:
 255         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 256         return status;
 257 }
 258
 259 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
 260  *  @hw: pointer to hardware structure
 261  *  @ptr: pointer offset in eeprom
 262  *  @size: size of section pointed by ptr, if 0 first word will be used as size
 263  *  @csum: address of checksum to update
 264  *
 265  *  Returns error status for any failure
 266  **/
 267 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
 268                                    u16 size, u16 *csum, u16 *buffer,
 269                                    u32 buffer_size)
 270 {
 271         u16 buf[256];
 272         s32 status;
 273         u16 length, bufsz, i, start;
 274         u16 *local_buffer;
 275
 276         bufsz = sizeof(buf) / sizeof(buf[0]);
 277
 278         /* Read a chunk at the pointer location */
 279         if (!buffer) {
 280                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
 281                 if (status) {
 282                         hw_dbg(hw, "Failed to read EEPROM image\n");
 283                         return status;
 284                 }
 285                 local_buffer = buf;
 286         } else {
 287                 if (buffer_size < ptr)
 288                         return  IXGBE_ERR_PARAM;
 289                 local_buffer = &buffer[ptr];
 290         }
 291
 292         if (size) {
 293                 start = 0;
 294                 length = size;
 295         } else {
 296                 start = 1;
 297                 length = local_buffer[0];
 298
 299                 /* Skip pointer section if length is invalid. */
 300                 if (length == 0xFFFF || length == 0 ||
 301                     (ptr + length) >= hw->eeprom.word_size)
 302                         return 0;
 303         }
 304
 305         if (buffer && ((u32)start + (u32)length > buffer_size))
 306                 return IXGBE_ERR_PARAM;
 307
 308         for (i = start; length; i++, length--) {
 309                 if (i == bufsz && !buffer) {
 310                         ptr += bufsz;
 311                         i = 0;
 312                         if (length < bufsz)
 313                                 bufsz = length;
 314
 315                         /* Read a chunk at the pointer location */
 316                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
 317                                                                   bufsz, buf);
 318                         if (status) {
 319                                 hw_dbg(hw, "Failed to read EEPROM image\n");
 320                                 return status;
 321                         }
 322                 }
 323                 *csum += local_buffer[i];
 324         }
 325         return 0;
 326 }
 327
 328 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
 329  *  @hw: pointer to hardware structure
 330  *  @buffer: pointer to buffer containing calculated checksum
 331  *  @buffer_size: size of buffer
 332  *
 333  *  Returns a negative error code on error, or the 16-bit checksum
 334  **/
 335 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
 336                                     u32 buffer_size)
 337 {
 338         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
 339         u16 *local_buffer;
 340         s32 status;
 341         u16 checksum = 0;
 342         u16 pointer, i, size;
 343
 344         hw->eeprom.ops.init_params(hw);
 345
 346         if (!buffer) {
 347                 /* Read pointer area */
 348                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
 349                                                 IXGBE_EEPROM_LAST_WORD + 1,
 350                                                 eeprom_ptrs);
 351                 if (status) {
 352                         hw_dbg(hw, "Failed to read EEPROM image\n");
 353                         return status;
 354                 }
 355                 local_buffer = eeprom_ptrs;
 356         } else {
 357                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
 358                         return IXGBE_ERR_PARAM;
 359                 local_buffer = buffer;
 360         }
 361
 362         /* For X550 hardware include 0x0-0x41 in the checksum, skip the
 363          * checksum word itself
 364          */
 365         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
 366                 if (i != IXGBE_EEPROM_CHECKSUM)
 367                         checksum += local_buffer[i];
 368
 369         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 370          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 371          */
 372         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
 373                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 374                         continue;
 375
 376                 pointer = local_buffer[i];
 377
 378                 /* Skip pointer section if the pointer is invalid. */
 379                 if (pointer == 0xFFFF || pointer == 0 ||
 380                     pointer >= hw->eeprom.word_size)
 381                         continue;
 382
 383                 switch (i) {
 384                 case IXGBE_PCIE_GENERAL_PTR:
 385                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
 386                         break;
 387                 case IXGBE_PCIE_CONFIG0_PTR:
 388                 case IXGBE_PCIE_CONFIG1_PTR:
 389                         size = IXGBE_PCIE_CONFIG_SIZE;
 390                         break;
 391                 default:
 392                         size = 0;
 393                         break;
 394                 }
 395
 396                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
 397                                                  buffer, buffer_size);
 398                 if (status)
 399                         return status;
 400         }
 401
 402         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 403
 404         return (s32)checksum;
 405 }
 406
 407 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
 408  *  @hw: pointer to hardware structure
 409  *
 410  *  Returns a negative error code on error, or the 16-bit checksum
 411  **/
 412 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
 413 {
 414         return ixgbe_calc_checksum_X550(hw, NULL, 0);
 415 }
 416
 417 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
 418  *  @hw: pointer to hardware structure
 419  *  @offset: offset of  word in the EEPROM to read
 420  *  @data: word read from the EEPROM
 421  *
 422  *   Reads a 16 bit word from the EEPROM using the hostif.
 423  **/
 424 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
 425 {
 426         s32 status = 0;
 427
 428         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 429                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
 430                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 431         } else {
 432                 status = IXGBE_ERR_SWFW_SYNC;
 433         }
 434
 435         return status;
 436 }
 437
 438 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
 439  *  @hw: pointer to hardware structure
 440  *  @checksum_val: calculated checksum
 441  *
 442  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 443  *  caller does not need checksum_val, the value can be NULL.
 444  **/
 445 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
 446                                                u16 *checksum_val)
 447 {
 448         s32 status;
 449         u16 checksum;
 450         u16 read_checksum = 0;
 451
 452         /* Read the first word from the EEPROM. If this times out or fails, do
 453          * not continue or we could be in for a very long wait while every
 454          * EEPROM read fails
 455          */
 456         status = hw->eeprom.ops.read(hw, 0, &checksum);
 457         if (status) {
 458                 hw_dbg(hw, "EEPROM read failed\n");
 459                 return status;
 460         }
 461
 462         status = hw->eeprom.ops.calc_checksum(hw);
 463         if (status < 0)
 464                 return status;
 465
 466         checksum = (u16)(status & 0xffff);
 467
 468         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 469                                            &read_checksum);
 470         if (status)
 471                 return status;
 472
 473         /* Verify read checksum from EEPROM is the same as
 474          * calculated checksum
 475          */
 476         if (read_checksum != checksum) {
 477                 status = IXGBE_ERR_EEPROM_CHECKSUM;
 478                 hw_dbg(hw, "Invalid EEPROM checksum");
 479         }
 480
 481         /* If the user cares, return the calculated checksum */
 482         if (checksum_val)
 483                 *checksum_val = checksum;
 484
 485         return status;
 486 }
 487
 488 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 489  *  @hw: pointer to hardware structure
 490  *  @offset: offset of  word in the EEPROM to write
 491  *  @data: word write to the EEPROM
 492  *
 493  *  Write a 16 bit word to the EEPROM using the hostif.
 494  **/
 495 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 496                                            u16 data)
 497 {
 498         s32 status;
 499         struct ixgbe_hic_write_shadow_ram buffer;
 500
 501         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
 502         buffer.hdr.req.buf_lenh = 0;
 503         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
 504         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 505
 506         /* one word */
 507         buffer.length = cpu_to_be16(sizeof(u16));
 508         buffer.data = data;
 509         buffer.address = cpu_to_be32(offset * 2);
 510
 511         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 512                                               sizeof(buffer),
 513                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 514         return status;
 515 }
 516
 517 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 518  *  @hw: pointer to hardware structure
 519  *  @offset: offset of  word in the EEPROM to write
 520  *  @data: word write to the EEPROM
 521  *
 522  *  Write a 16 bit word to the EEPROM using the hostif.
 523  **/
 524 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
 525 {
 526         s32 status = 0;
 527
 528         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 529                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
 530                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 531         } else {
 532                 hw_dbg(hw, "write ee hostif failed to get semaphore");
 533                 status = IXGBE_ERR_SWFW_SYNC;
 534         }
 535
 536         return status;
 537 }
 538
 539 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
 540  *  @hw: pointer to hardware structure
 541  *
 542  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
 543  **/
 544 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
 545 {
 546         s32 status = 0;
 547         union ixgbe_hic_hdr2 buffer;
 548
 549         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
 550         buffer.req.buf_lenh = 0;
 551         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
 552         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
 553
 554         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
 555                                               sizeof(buffer),
 556                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 557         return status;
 558 }
 559
 560 /** ixgbe_disable_rx_x550 - Disable RX unit
 561  *
 562  *  Enables the Rx DMA unit for x550
 563  **/
 564 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
 565 {
 566         u32 rxctrl, pfdtxgswc;
 567         s32 status;
 568         struct ixgbe_hic_disable_rxen fw_cmd;
 569
 570         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 571         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 572                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
 573                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
 574                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
 575                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
 576                         hw->mac.set_lben = true;
 577                 } else {
 578                         hw->mac.set_lben = false;
 579                 }
 580
 581                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
 582                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
 583                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 584                 fw_cmd.port_number = (u8)hw->bus.lan_id;
 585
 586                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
 587                                         sizeof(struct ixgbe_hic_disable_rxen),
 588                                         IXGBE_HI_COMMAND_TIMEOUT, true);
 589
 590                 /* If we fail - disable RX using register write */
 591                 if (status) {
 592                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 593                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 594                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
 595                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
 596                         }
 597                 }
 598         }
 599 }
 600
 601 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
 602  *  @hw: pointer to hardware structure
 603  *
 604  *  After writing EEPROM to shadow RAM using EEWR register, software calculates
 605  *  checksum and updates the EEPROM and instructs the hardware to update
 606  *  the flash.
 607  **/
 608 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
 609 {
 610         s32 status;
 611         u16 checksum = 0;
 612
 613         /* Read the first word from the EEPROM. If this times out or fails, do
 614          * not continue or we could be in for a very long wait while every
 615          * EEPROM read fails
 616          */
 617         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
 618         if (status) {
 619                 hw_dbg(hw, "EEPROM read failed\n");
 620                 return status;
 621         }
 622
 623         status = ixgbe_calc_eeprom_checksum_X550(hw);
 624         if (status < 0)
 625                 return status;
 626
 627         checksum = (u16)(status & 0xffff);
 628
 629         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 630                                             checksum);
 631         if (status)
 632                 return status;
 633
 634         status = ixgbe_update_flash_X550(hw);
 635
 636         return status;
 637 }
 638
 639 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
 640  *  @hw: pointer to hardware structure
 641  *  @offset: offset of  word in the EEPROM to write
 642  *  @words: number of words
 643  *  @data: word(s) write to the EEPROM
 644  *
 645  *
 646  *  Write a 16 bit word(s) to the EEPROM using the hostif.
 647  **/
 648 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 649                                              u16 offset, u16 words,
 650                                              u16 *data)
 651 {
 652         s32 status = 0;
 653         u32 i = 0;
 654
 655         /* Take semaphore for the entire operation. */
 656         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 657         if (status) {
 658                 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
 659                 return status;
 660         }
 661
 662         for (i = 0; i < words; i++) {
 663                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
 664                                                          data[i]);
 665                 if (status) {
 666                         hw_dbg(hw, "Eeprom buffered write failed\n");
 667                         break;
 668                 }
 669         }
 670
 671         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 672
 673         return status;
 674 }
 675
 676 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
 677  *  @hw: pointer to hardware structure
 678  **/
 679 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
 680 {
 681         struct ixgbe_mac_info *mac = &hw->mac;
 682
 683         /* CS4227 does not support autoneg, so disable the laser control
 684          * functions for SFP+ fiber
 685          */
 686         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 687                 mac->ops.disable_tx_laser = NULL;
 688                 mac->ops.enable_tx_laser = NULL;
 689                 mac->ops.flap_tx_laser = NULL;
 690         }
 691 }
 692
 693 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
 694  * @hw: pointer to hardware structure
 695  */
 696 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 697 {
 698         bool setup_linear;
 699         u16 reg_slice, edc_mode;
 700         s32 ret_val;
 701
 702         switch (hw->phy.sfp_type) {
 703         case ixgbe_sfp_type_unknown:
 704                 return 0;
 705         case ixgbe_sfp_type_not_present:
 706                 return IXGBE_ERR_SFP_NOT_PRESENT;
 707         case ixgbe_sfp_type_da_cu_core0:
 708         case ixgbe_sfp_type_da_cu_core1:
 709                 setup_linear = true;
 710                 break;
 711         case ixgbe_sfp_type_srlr_core0:
 712         case ixgbe_sfp_type_srlr_core1:
 713         case ixgbe_sfp_type_da_act_lmt_core0:
 714         case ixgbe_sfp_type_da_act_lmt_core1:
 715         case ixgbe_sfp_type_1g_sx_core0:
 716         case ixgbe_sfp_type_1g_sx_core1:
 717                 setup_linear = false;
 718                 break;
 719         default:
 720                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 721         }
 722
 723         ixgbe_init_mac_link_ops_X550em(hw);
 724         hw->phy.ops.reset = NULL;
 725
 726         /* The CS4227 slice address is the base address + the port-pair reg
 727          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
 728          */
 729         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
 730
 731         if (setup_linear)
 732                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 733         else
 734                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 735
 736         /* Configure CS4227 for connection type. */
 737         ret_val = hw->phy.ops.write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
 738                                                  edc_mode);
 739
 740         if (ret_val)
 741                 ret_val = hw->phy.ops.write_i2c_combined(hw, 0x80, reg_slice,
 742                                                          edc_mode);
 743
 744         return ret_val;
 745 }
 746
 747 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
 748  * @hw: pointer to hardware structure
 749  * @speed: pointer to link speed
 750  * @autoneg: true when autoneg or autotry is enabled
 751  **/
 752 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
 753                                               ixgbe_link_speed *speed,
 754                                               bool *autoneg)
 755 {
 756         /* SFP */
 757         if (hw->phy.media_type == ixgbe_media_type_fiber) {
 758                 /* CS4227 SFP must not enable auto-negotiation */
 759                 *autoneg = false;
 760
 761                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
 762                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
 763                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
 764                         return 0;
 765                 }
 766
 767                 /* Link capabilities are based on SFP */
 768                 if (hw->phy.multispeed_fiber)
 769                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
 770                                  IXGBE_LINK_SPEED_1GB_FULL;
 771                 else
 772                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 773         } else {
 774                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
 775                          IXGBE_LINK_SPEED_1GB_FULL;
 776                 *autoneg = true;
 777         }
 778         return 0;
 779 }
 780
 781 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
 782  *  IOSF device
 783  *
 784  *  @hw: pointer to hardware structure
 785  *  @reg_addr: 32 bit PHY register to write
 786  *  @device_type: 3 bit device type
 787  *  @data: Data to write to the register
 788  **/
 789 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 790                                         u32 device_type, u32 data)
 791 {
 792         u32 i, command, error;
 793
 794         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 795                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 796
 797         /* Write IOSF control register */
 798         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 799
 800         /* Write IOSF data register */
 801         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 802
 803         /* Check every 10 usec to see if the address cycle completed.
 804          * The SB IOSF BUSY bit will clear when the operation is
 805          * complete
 806          */
 807         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 808                 usleep_range(10, 20);
 809
 810                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 811                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 812                         break;
 813         }
 814
 815         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 816                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 817                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 818                 hw_dbg(hw, "Failed to write, error %x\n", error);
 819                 return IXGBE_ERR_PHY;
 820         }
 821
 822         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 823                 hw_dbg(hw, "Write timed out\n");
 824                 return IXGBE_ERR_PHY;
 825         }
 826
 827         return 0;
 828 }
 829
 830 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
 831  *  @hw: pointer to hardware structure
 832  *  @speed: the link speed to force
 833  *
 834  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
 835  *  internal and external PHY at a specific speed, without autonegotiation.
 836  **/
 837 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
 838 {
 839         s32 status;
 840         u32 reg_val;
 841
 842         /* Disable AN and force speed to 10G Serial. */
 843         status = ixgbe_read_iosf_sb_reg_x550(hw,
 844                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 845                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
 846         if (status)
 847                 return status;
 848
 849         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
 850         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
 851
 852         /* Select forced link speed for internal PHY. */
 853         switch (*speed) {
 854         case IXGBE_LINK_SPEED_10GB_FULL:
 855                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
 856                 break;
 857         case IXGBE_LINK_SPEED_1GB_FULL:
 858                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
 859                 break;
 860         default:
 861                 /* Other link speeds are not supported by internal KR PHY. */
 862                 return IXGBE_ERR_LINK_SETUP;
 863         }
 864
 865         status = ixgbe_write_iosf_sb_reg_x550(hw,
 866                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
 867                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
 868         if (status)
 869                 return status;
 870
 871         /* Disable training protocol FSM. */
 872         status = ixgbe_read_iosf_sb_reg_x550(hw,
 873                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
 874                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
 875         if (status)
 876                 return status;
 877
 878         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
 879         status = ixgbe_write_iosf_sb_reg_x550(hw,
 880                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
 881                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
 882         if (status)
 883                 return status;
 884
 885         /* Disable Flex from training TXFFE. */
 886         status = ixgbe_read_iosf_sb_reg_x550(hw,
 887                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
 888                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
 889         if (status)
 890                 return status;
 891
 892         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
 893         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
 894         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
 895         status = ixgbe_write_iosf_sb_reg_x550(hw,
 896                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
 897                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
 898         if (status)
 899                 return status;
 900
 901         status = ixgbe_read_iosf_sb_reg_x550(hw,
 902                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
 903                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
 904         if (status)
 905                 return status;
 906
 907         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
 908         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
 909         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
 910         status = ixgbe_write_iosf_sb_reg_x550(hw,
 911                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
 912                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
 913         if (status)
 914                 return status;
 915
 916         /* Enable override for coefficients. */
 917         status = ixgbe_read_iosf_sb_reg_x550(hw,
 918                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
 919                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
 920         if (status)
 921                 return status;
 922
 923         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
 924         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
 925         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
 926         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
 927         status = ixgbe_write_iosf_sb_reg_x550(hw,
 928                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
 929                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
 930         if (status)
 931                 return status;
 932
 933         /* Toggle port SW reset by AN reset. */
 934         status = ixgbe_read_iosf_sb_reg_x550(hw,
 935                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 936                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
 937         if (status)
 938                 return status;
 939
 940         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
 941         status = ixgbe_write_iosf_sb_reg_x550(hw,
 942                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 943                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
 944
 945         return status;
 946 }
 947
 948 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
 949  *  @hw: pointer to hardware structure
 950  *
 951  *   Configures the integrated KX4 PHY.
 952  **/
 953 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
 954 {
 955         s32 status;
 956         u32 reg_val;
 957
 958         status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
 959                                              IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
 960                                              hw->bus.lan_id, &reg_val);
 961         if (status)
 962                 return status;
 963
 964         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
 965                      IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
 966
 967         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
 968
 969         /* Advertise 10G support. */
 970         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 971                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
 972
 973         /* Advertise 1G support. */
 974         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 975                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
 976
 977         /* Restart auto-negotiation. */
 978         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
 979         status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
 980                                               IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
 981                                               hw->bus.lan_id, reg_val);
 982
 983         return status;
 984 }
 985
 986 /**  ixgbe_setup_kr_x550em - Configure the KR PHY.
 987  *   @hw: pointer to hardware structure
 988  *
 989  *   Configures the integrated KR PHY.
 990  **/
 991 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
 992 {
 993         s32 status;
 994         u32 reg_val;
 995
 996         status = ixgbe_read_iosf_sb_reg_x550(hw,
 997                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 998                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
 999         if (status)
1000                 return status;
1001
1002         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1003         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1004         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1005         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1006                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1007
1008         /* Advertise 10G support. */
1009         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1010                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1011
1012         /* Advertise 1G support. */
1013         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1014                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1015
1016         /* Restart auto-negotiation. */
1017         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1018         status = ixgbe_write_iosf_sb_reg_x550(hw,
1019                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1020                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1021
1022         return status;
1023 }
1024
1025 /** ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY
1026  *  @hw: point to hardware structure
1027  *
1028  *  Configures the integrated KR PHY to talk to the external PHY. The base
1029  *  driver will call this function when it gets notification via interrupt from
1030  *  the external PHY. This function forces the internal PHY into iXFI mode at
1031  *  the correct speed.
1032  *
1033  *  A return of a non-zero value indicates an error, and the base driver should
1034  *  not report link up.
1035  **/
1036 static s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
1037 {
1038         u32 status;
1039         u16 lasi, autoneg_status, speed;
1040         ixgbe_link_speed force_speed;
1041
1042         /* Verify that the external link status has changed */
1043         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS,
1044                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE, &lasi);
1045         if (status)
1046                 return status;
1047
1048         /* If there was no change in link status, we can just exit */
1049         if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM))
1050                 return 0;
1051
1052         /* we read this twice back to back to indicate current status */
1053         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1054                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1055                                       &autoneg_status);
1056         if (status)
1057                 return status;
1058
1059         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1060                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1061                                       &autoneg_status);
1062         if (status)
1063                 return status;
1064
1065         /* If link is not up return an error indicating treat link as down */
1066         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1067                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1068
1069         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1070                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1071                                       &speed);
1072
1073         /* clear everything but the speed and duplex bits */
1074         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1075
1076         switch (speed) {
1077         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1078                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1079                 break;
1080         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1081                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1082                 break;
1083         default:
1084                 /* Internal PHY does not support anything else */
1085                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1086         }
1087
1088         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1089 }
1090
1091 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1092  *  @hw: pointer to hardware structure
1093  *
1094  *  Initialize any function pointers that were not able to be
1095  *  set during init_shared_code because the PHY/SFP type was
1096  *  not known.  Perform the SFP init if necessary.
1097  **/
1098 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1099 {
1100         struct ixgbe_phy_info *phy = &hw->phy;
1101         s32 ret_val;
1102         u32 esdp;
1103
1104         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
1105                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
1106                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1107
1108                 if (hw->bus.lan_id) {
1109                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
1110                         esdp |= IXGBE_ESDP_SDP1_DIR;
1111                 }
1112                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
1113                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
1114         }
1115
1116         /* Identify the PHY or SFP module */
1117         ret_val = phy->ops.identify(hw);
1118
1119         /* Setup function pointers based on detected SFP module and speeds */
1120         ixgbe_init_mac_link_ops_X550em(hw);
1121         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1122                 phy->ops.reset = NULL;
1123
1124         /* Set functions pointers based on phy type */
1125         switch (hw->phy.type) {
1126         case ixgbe_phy_x550em_kx4:
1127                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1128                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1129                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1130                 break;
1131         case ixgbe_phy_x550em_kr:
1132                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1133                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1134                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1135                 break;
1136         case ixgbe_phy_x550em_ext_t:
1137                 phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em;
1138                 break;
1139         default:
1140                 break;
1141         }
1142         return ret_val;
1143 }
1144
1145 /** ixgbe_get_media_type_X550em - Get media type
1146  *  @hw: pointer to hardware structure
1147  *
1148  *  Returns the media type (fiber, copper, backplane)
1149  *
1150  */
1151 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1152 {
1153         enum ixgbe_media_type media_type;
1154
1155         /* Detect if there is a copper PHY attached. */
1156         switch (hw->device_id) {
1157         case IXGBE_DEV_ID_X550EM_X_KR:
1158         case IXGBE_DEV_ID_X550EM_X_KX4:
1159                 media_type = ixgbe_media_type_backplane;
1160                 break;
1161         case IXGBE_DEV_ID_X550EM_X_SFP:
1162                 media_type = ixgbe_media_type_fiber;
1163                 break;
1164         case IXGBE_DEV_ID_X550EM_X_1G_T:
1165         case IXGBE_DEV_ID_X550EM_X_10G_T:
1166                  media_type = ixgbe_media_type_copper;
1167                 break;
1168         default:
1169                 media_type = ixgbe_media_type_unknown;
1170                 break;
1171         }
1172         return media_type;
1173 }
1174
1175 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1176  ** @hw: pointer to hardware structure
1177  **/
1178 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1179 {
1180         u32 status;
1181         u16 reg;
1182         u32 retries = 2;
1183
1184         do {
1185                 /* decrement retries counter and exit if we hit 0 */
1186                 if (retries < 1) {
1187                         hw_dbg(hw, "External PHY not yet finished resetting.");
1188                         return IXGBE_ERR_PHY;
1189                 }
1190                 retries--;
1191
1192                 status = hw->phy.ops.read_reg(hw,
1193                                               IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1194                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1195                                               &reg);
1196                 if (status)
1197                         return status;
1198
1199                 /* Verify PHY FW reset has completed */
1200         } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1);
1201
1202         /* Set port to low power mode */
1203         status = hw->phy.ops.read_reg(hw,
1204                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1205                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1206                                       &reg);
1207         if (status)
1208                 return status;
1209
1210         /* Enable the transmitter */
1211         status = hw->phy.ops.read_reg(hw,
1212                                       IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1213                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1214                                       &reg);
1215         if (status)
1216                 return status;
1217
1218         reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE;
1219
1220         status = hw->phy.ops.write_reg(hw,
1221                                        IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1222                                        IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1223                                        reg);
1224         if (status)
1225                 return status;
1226
1227         /* Un-stall the PHY FW */
1228         status = hw->phy.ops.read_reg(hw,
1229                                       IXGBE_MDIO_GLOBAL_RES_PR_10,
1230                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1231                                       &reg);
1232         if (status)
1233                 return status;
1234
1235         reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1236
1237         status = hw->phy.ops.write_reg(hw,
1238                                        IXGBE_MDIO_GLOBAL_RES_PR_10,
1239                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1240                                        reg);
1241         return status;
1242 }
1243
1244 /**  ixgbe_reset_hw_X550em - Perform hardware reset
1245  **  @hw: pointer to hardware structure
1246  **
1247  **  Resets the hardware by resetting the transmit and receive units, masks
1248  **  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1249  **  reset.
1250  **/
1251 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1252 {
1253         ixgbe_link_speed link_speed;
1254         s32 status;
1255         u32 ctrl = 0;
1256         u32 i;
1257         bool link_up = false;
1258
1259         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1260         status = hw->mac.ops.stop_adapter(hw);
1261         if (status)
1262                 return status;
1263
1264         /* flush pending Tx transactions */
1265         ixgbe_clear_tx_pending(hw);
1266
1267         /* PHY ops must be identified and initialized prior to reset */
1268
1269         /* Identify PHY and related function pointers */
1270         status = hw->phy.ops.init(hw);
1271
1272         /* start the external PHY */
1273         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1274                 status = ixgbe_init_ext_t_x550em(hw);
1275                 if (status)
1276                         return status;
1277         }
1278
1279         /* Setup SFP module if there is one present. */
1280         if (hw->phy.sfp_setup_needed) {
1281                 status = hw->mac.ops.setup_sfp(hw);
1282                 hw->phy.sfp_setup_needed = false;
1283         }
1284
1285         /* Reset PHY */
1286         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1287                 hw->phy.ops.reset(hw);
1288
1289 mac_reset_top:
1290         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1291          * If link reset is used when link is up, it might reset the PHY when
1292          * mng is using it.  If link is down or the flag to force full link
1293          * reset is set, then perform link reset.
1294          */
1295         ctrl = IXGBE_CTRL_LNK_RST;
1296
1297         if (!hw->force_full_reset) {
1298                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1299                 if (link_up)
1300                         ctrl = IXGBE_CTRL_RST;
1301         }
1302
1303         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1304         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1305         IXGBE_WRITE_FLUSH(hw);
1306
1307         /* Poll for reset bit to self-clear meaning reset is complete */
1308         for (i = 0; i < 10; i++) {
1309                 udelay(1);
1310                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1311                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1312                         break;
1313         }
1314
1315         if (ctrl & IXGBE_CTRL_RST_MASK) {
1316                 status = IXGBE_ERR_RESET_FAILED;
1317                 hw_dbg(hw, "Reset polling failed to complete.\n");
1318         }
1319
1320         msleep(50);
1321
1322         /* Double resets are required for recovery from certain error
1323          * clear the multicast table.  Also reset num_rar_entries to 128,
1324          * since we modify this value when programming the SAN MAC address.
1325          */
1326         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1327                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1328                 goto mac_reset_top;
1329         }
1330
1331         /* Store the permanent mac address */
1332         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1333
1334         /* Store MAC address from RAR0, clear receive address registers, and
1335          * clear the multicast table.  Also reset num_rar_entries to 128,
1336          * since we modify this value when programming the SAN MAC address.
1337          */
1338         hw->mac.num_rar_entries = 128;
1339         hw->mac.ops.init_rx_addrs(hw);
1340
1341         return status;
1342 }
1343
1344 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
1345  *      anti-spoofing
1346  *  @hw:  pointer to hardware structure
1347  *  @enable: enable or disable switch for Ethertype anti-spoofing
1348  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1349  **/
1350 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1351                                                    bool enable, int vf)
1352 {
1353         int vf_target_reg = vf >> 3;
1354         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1355         u32 pfvfspoof;
1356
1357         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1358         if (enable)
1359                 pfvfspoof |= (1 << vf_target_shift);
1360         else
1361                 pfvfspoof &= ~(1 << vf_target_shift);
1362
1363         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1364 }
1365
1366 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
1367  *  @hw: pointer to hardware structure
1368  *  @enable: enable or disable source address pruning
1369  *  @pool: Rx pool to set source address pruning for
1370  **/
1371 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
1372                                                   bool enable,
1373                                                   unsigned int pool)
1374 {
1375         u64 pfflp;
1376
1377         /* max rx pool is 63 */
1378         if (pool > 63)
1379                 return;
1380
1381         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1382         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1383
1384         if (enable)
1385                 pfflp |= (1ULL << pool);
1386         else
1387                 pfflp &= ~(1ULL << pool);
1388
1389         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1390         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1391 }
1392
1393 #define X550_COMMON_MAC \
1394         .init_hw                        = &ixgbe_init_hw_generic, \
1395         .start_hw                       = &ixgbe_start_hw_X540, \
1396         .clear_hw_cntrs                 = &ixgbe_clear_hw_cntrs_generic, \
1397         .enable_rx_dma                  = &ixgbe_enable_rx_dma_generic, \
1398         .get_mac_addr                   = &ixgbe_get_mac_addr_generic, \
1399         .get_device_caps                = &ixgbe_get_device_caps_generic, \
1400         .stop_adapter                   = &ixgbe_stop_adapter_generic, \
1401         .get_bus_info                   = &ixgbe_get_bus_info_generic, \
1402         .set_lan_id                     = &ixgbe_set_lan_id_multi_port_pcie, \
1403         .read_analog_reg8               = NULL, \
1404         .write_analog_reg8              = NULL, \
1405         .set_rxpba                      = &ixgbe_set_rxpba_generic, \
1406         .check_link                     = &ixgbe_check_mac_link_generic, \
1407         .led_on                         = &ixgbe_led_on_generic, \
1408         .led_off                        = &ixgbe_led_off_generic, \
1409         .blink_led_start                = &ixgbe_blink_led_start_X540, \
1410         .blink_led_stop                 = &ixgbe_blink_led_stop_X540, \
1411         .set_rar                        = &ixgbe_set_rar_generic, \
1412         .clear_rar                      = &ixgbe_clear_rar_generic, \
1413         .set_vmdq                       = &ixgbe_set_vmdq_generic, \
1414         .set_vmdq_san_mac               = &ixgbe_set_vmdq_san_mac_generic, \
1415         .clear_vmdq                     = &ixgbe_clear_vmdq_generic, \
1416         .init_rx_addrs                  = &ixgbe_init_rx_addrs_generic, \
1417         .update_mc_addr_list            = &ixgbe_update_mc_addr_list_generic, \
1418         .enable_mc                      = &ixgbe_enable_mc_generic, \
1419         .disable_mc                     = &ixgbe_disable_mc_generic, \
1420         .clear_vfta                     = &ixgbe_clear_vfta_generic, \
1421         .set_vfta                       = &ixgbe_set_vfta_generic, \
1422         .fc_enable                      = &ixgbe_fc_enable_generic, \
1423         .set_fw_drv_ver                 = &ixgbe_set_fw_drv_ver_generic, \
1424         .init_uta_tables                = &ixgbe_init_uta_tables_generic, \
1425         .set_mac_anti_spoofing          = &ixgbe_set_mac_anti_spoofing, \
1426         .set_vlan_anti_spoofing         = &ixgbe_set_vlan_anti_spoofing, \
1427         .set_source_address_pruning     = \
1428                                 &ixgbe_set_source_address_pruning_X550, \
1429         .set_ethertype_anti_spoofing    = \
1430                                 &ixgbe_set_ethertype_anti_spoofing_X550, \
1431         .acquire_swfw_sync              = &ixgbe_acquire_swfw_sync_X540, \
1432         .release_swfw_sync              = &ixgbe_release_swfw_sync_X540, \
1433         .disable_rx_buff                = &ixgbe_disable_rx_buff_generic, \
1434         .enable_rx_buff                 = &ixgbe_enable_rx_buff_generic, \
1435         .get_thermal_sensor_data        = NULL, \
1436         .init_thermal_sensor_thresh     = NULL, \
1437         .prot_autoc_read                = &prot_autoc_read_generic, \
1438         .prot_autoc_write               = &prot_autoc_write_generic, \
1439         .enable_rx                      = &ixgbe_enable_rx_generic, \
1440         .disable_rx                     = &ixgbe_disable_rx_x550, \
1441
1442 static struct ixgbe_mac_operations mac_ops_X550 = {
1443         X550_COMMON_MAC
1444         .reset_hw               = &ixgbe_reset_hw_X540,
1445         .get_media_type         = &ixgbe_get_media_type_X540,
1446         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
1447         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
1448         .setup_link             = &ixgbe_setup_mac_link_X540,
1449         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
1450         .setup_sfp              = NULL,
1451 };
1452
1453 static struct ixgbe_mac_operations mac_ops_X550EM_x = {
1454         X550_COMMON_MAC
1455         .reset_hw               = &ixgbe_reset_hw_X550em,
1456         .get_media_type         = &ixgbe_get_media_type_X550em,
1457         .get_san_mac_addr       = NULL,
1458         .get_wwn_prefix         = NULL,
1459         .setup_link             = NULL, /* defined later */
1460         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
1461         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
1462
1463 };
1464
1465 #define X550_COMMON_EEP \
1466         .read                   = &ixgbe_read_ee_hostif_X550, \
1467         .read_buffer            = &ixgbe_read_ee_hostif_buffer_X550, \
1468         .write                  = &ixgbe_write_ee_hostif_X550, \
1469         .write_buffer           = &ixgbe_write_ee_hostif_buffer_X550, \
1470         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X550, \
1471         .update_checksum        = &ixgbe_update_eeprom_checksum_X550, \
1472         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X550, \
1473
1474 static struct ixgbe_eeprom_operations eeprom_ops_X550 = {
1475         X550_COMMON_EEP
1476         .init_params            = &ixgbe_init_eeprom_params_X550,
1477 };
1478
1479 static struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
1480         X550_COMMON_EEP
1481         .init_params            = &ixgbe_init_eeprom_params_X540,
1482 };
1483
1484 #define X550_COMMON_PHY \
1485         .identify_sfp           = &ixgbe_identify_module_generic, \
1486         .reset                  = NULL, \
1487         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic, \
1488         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic, \
1489         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic, \
1490         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic, \
1491         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic, \
1492         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic, \
1493         .check_overtemp         = &ixgbe_tn_check_overtemp, \
1494         .get_firmware_version   = &ixgbe_get_phy_firmware_version_generic,
1495
1496 static struct ixgbe_phy_operations phy_ops_X550 = {
1497         X550_COMMON_PHY
1498         .init                   = NULL,
1499         .identify               = &ixgbe_identify_phy_generic,
1500         .read_reg               = &ixgbe_read_phy_reg_generic,
1501         .write_reg              = &ixgbe_write_phy_reg_generic,
1502         .setup_link             = &ixgbe_setup_phy_link_generic,
1503         .read_i2c_combined      = &ixgbe_read_i2c_combined_generic,
1504         .write_i2c_combined     = &ixgbe_write_i2c_combined_generic,
1505 };
1506
1507 static struct ixgbe_phy_operations phy_ops_X550EM_x = {
1508         X550_COMMON_PHY
1509         .init                   = &ixgbe_init_phy_ops_X550em,
1510         .identify               = &ixgbe_identify_phy_x550em,
1511         .read_reg               = NULL, /* defined later */
1512         .write_reg              = NULL, /* defined later */
1513         .setup_link             = NULL, /* defined later */
1514 };
1515
1516 struct ixgbe_info ixgbe_X550_info = {
1517         .mac                    = ixgbe_mac_X550,
1518         .get_invariants         = &ixgbe_get_invariants_X540,
1519         .mac_ops                = &mac_ops_X550,
1520         .eeprom_ops             = &eeprom_ops_X550,
1521         .phy_ops                = &phy_ops_X550,
1522         .mbx_ops                = &mbx_ops_generic,
1523 };
1524
1525 struct ixgbe_info ixgbe_X550EM_x_info = {
1526         .mac                    = ixgbe_mac_X550EM_x,
1527         .get_invariants         = &ixgbe_get_invariants_X540,
1528         .mac_ops                = &mac_ops_X550EM_x,
1529         .eeprom_ops             = &eeprom_ops_X550EM_x,
1530         .phy_ops                = &phy_ops_X550EM_x,
1531         .mbx_ops                = &mbx_ops_generic,
1532 };