1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 #include "ixgbe_type.h"
33 #define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
34 #define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2
36 /* EEPROM byte offsets */
37 #define IXGBE_SFF_IDENTIFIER 0x0
38 #define IXGBE_SFF_IDENTIFIER_SFP 0x3
39 #define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
40 #define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
41 #define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
42 #define IXGBE_SFF_1GBE_COMP_CODES 0x6
43 #define IXGBE_SFF_10GBE_COMP_CODES 0x3
44 #define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
45 #define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
46 #define IXGBE_SFF_SFF_8472_SWAP 0x5C
47 #define IXGBE_SFF_SFF_8472_COMP 0x5E
48 #define IXGBE_SFF_SFF_8472_OSCB 0x6E
49 #define IXGBE_SFF_SFF_8472_ESCB 0x76
50 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS 0xD
51 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
52 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
53 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
54 #define IXGBE_SFF_QSFP_CONNECTOR 0x82
55 #define IXGBE_SFF_QSFP_10GBE_COMP 0x83
56 #define IXGBE_SFF_QSFP_1GBE_COMP 0x86
57 #define IXGBE_SFF_QSFP_CABLE_LENGTH 0x92
58 #define IXGBE_SFF_QSFP_DEVICE_TECH 0x93
61 #define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
62 #define IXGBE_SFF_DA_ACTIVE_CABLE 0x8
63 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
64 #define IXGBE_SFF_1GBASESX_CAPABLE 0x1
65 #define IXGBE_SFF_1GBASELX_CAPABLE 0x2
66 #define IXGBE_SFF_1GBASET_CAPABLE 0x8
67 #define IXGBE_SFF_10GBASESR_CAPABLE 0x10
68 #define IXGBE_SFF_10GBASELR_CAPABLE 0x20
69 #define IXGBE_SFF_ADDRESSING_MODE 0x4
70 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1
71 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8
72 #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23
73 #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0
74 #define IXGBE_I2C_EEPROM_READ_MASK 0x100
75 #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
76 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
77 #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
78 #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
79 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
80 #define IXGBE_CS4227 0xBE /* CS4227 address */
81 #define IXGBE_CS4227_SPARE24_LSB 0x12B0 /* Reg to program EDC */
82 #define IXGBE_CS4227_EDC_MODE_CX1 0x0002
83 #define IXGBE_CS4227_EDC_MODE_SR 0x0004
85 /* Flow control defines */
86 #define IXGBE_TAF_SYM_PAUSE 0x400
87 #define IXGBE_TAF_ASM_PAUSE 0x800
89 /* Bit-shift macros */
90 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
91 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
92 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
94 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
95 #define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
96 #define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
97 #define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
98 #define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
100 /* I2C SDA and SCL timing parameters for standard mode */
101 #define IXGBE_I2C_T_HD_STA 4
102 #define IXGBE_I2C_T_LOW 5
103 #define IXGBE_I2C_T_HIGH 4
104 #define IXGBE_I2C_T_SU_STA 5
105 #define IXGBE_I2C_T_HD_DATA 5
106 #define IXGBE_I2C_T_SU_DATA 1
107 #define IXGBE_I2C_T_RISE 1
108 #define IXGBE_I2C_T_FALL 1
109 #define IXGBE_I2C_T_SU_STO 4
110 #define IXGBE_I2C_T_BUF 5
112 #define IXGBE_TN_LASI_STATUS_REG 0x9005
113 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
115 /* SFP+ SFF-8472 Compliance code */
116 #define IXGBE_SFF_SFF_8472_UNSUP 0x00
118 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
119 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
120 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
121 u32 device_type, u16 *phy_data);
122 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
123 u32 device_type, u16 phy_data);
124 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
125 u32 device_type, u16 *phy_data);
126 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
127 u32 device_type, u16 phy_data);
128 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
129 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
130 ixgbe_link_speed speed,
131 bool autoneg_wait_to_complete);
132 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
133 ixgbe_link_speed *speed,
135 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
138 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
139 ixgbe_link_speed *speed,
141 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
142 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
143 u16 *firmware_version);
144 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
145 u16 *firmware_version);
147 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
148 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
149 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
150 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
153 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
154 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
155 u8 dev_addr, u8 *data);
156 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
157 u8 dev_addr, u8 data);
158 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
160 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
162 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
164 s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
166 s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
168 #endif /* _IXGBE_PHY_H_ */