1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 #include <linux/if_ether.h>
25 #include <linux/delay.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
30 #include "e1000_mac.h"
34 static s32 igb_set_default_fc(struct e1000_hw *hw);
35 static s32 igb_set_fc_watermarks(struct e1000_hw *hw);
38 * igb_get_bus_info_pcie - Get PCIe bus information
39 * @hw: pointer to the HW structure
41 * Determines and stores the system bus information for a particular
42 * network interface. The following bus information is determined and stored:
43 * bus speed, bus width, type (PCIe), and PCIe function.
45 s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
47 struct e1000_bus_info *bus = &hw->bus;
52 bus->type = e1000_bus_type_pci_express;
54 ret_val = igb_read_pcie_cap_reg(hw,
58 bus->width = e1000_bus_width_unknown;
59 bus->speed = e1000_bus_speed_unknown;
61 switch (pcie_link_status & PCI_EXP_LNKSTA_CLS) {
62 case PCI_EXP_LNKSTA_CLS_2_5GB:
63 bus->speed = e1000_bus_speed_2500;
65 case PCI_EXP_LNKSTA_CLS_5_0GB:
66 bus->speed = e1000_bus_speed_5000;
69 bus->speed = e1000_bus_speed_unknown;
73 bus->width = (enum e1000_bus_width)((pcie_link_status &
74 PCI_EXP_LNKSTA_NLW) >>
75 PCI_EXP_LNKSTA_NLW_SHIFT);
78 reg = rd32(E1000_STATUS);
79 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
85 * igb_clear_vfta - Clear VLAN filter table
86 * @hw: pointer to the HW structure
88 * Clears the register array which contains the VLAN filter table by
89 * setting all the values to 0.
91 void igb_clear_vfta(struct e1000_hw *hw)
95 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
96 array_wr32(E1000_VFTA, offset, 0);
102 * igb_write_vfta - Write value to VLAN filter table
103 * @hw: pointer to the HW structure
104 * @offset: register offset in VLAN filter table
105 * @value: register value written to VLAN filter table
107 * Writes value at the given offset in the register array which stores
108 * the VLAN filter table.
110 static void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
112 array_wr32(E1000_VFTA, offset, value);
116 /* Due to a hw errata, if the host tries to configure the VFTA register
117 * while performing queries from the BMC or DMA, then the VFTA in some
118 * cases won't be written.
122 * igb_clear_vfta_i350 - Clear VLAN filter table
123 * @hw: pointer to the HW structure
125 * Clears the register array which contains the VLAN filter table by
126 * setting all the values to 0.
128 void igb_clear_vfta_i350(struct e1000_hw *hw)
133 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
134 for (i = 0; i < 10; i++)
135 array_wr32(E1000_VFTA, offset, 0);
142 * igb_write_vfta_i350 - Write value to VLAN filter table
143 * @hw: pointer to the HW structure
144 * @offset: register offset in VLAN filter table
145 * @value: register value written to VLAN filter table
147 * Writes value at the given offset in the register array which stores
148 * the VLAN filter table.
150 static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
154 for (i = 0; i < 10; i++)
155 array_wr32(E1000_VFTA, offset, value);
161 * igb_init_rx_addrs - Initialize receive address's
162 * @hw: pointer to the HW structure
163 * @rar_count: receive address registers
165 * Setups the receive address registers by setting the base receive address
166 * register to the devices MAC address and clearing all the other receive
167 * address registers to 0.
169 void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
172 u8 mac_addr[ETH_ALEN] = {0};
174 /* Setup the receive address */
175 hw_dbg("Programming MAC Address into RAR[0]\n");
177 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
179 /* Zero out the other (rar_entry_count - 1) receive addresses */
180 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
181 for (i = 1; i < rar_count; i++)
182 hw->mac.ops.rar_set(hw, mac_addr, i);
186 * igb_vfta_set - enable or disable vlan in VLAN filter table
187 * @hw: pointer to the HW structure
188 * @vid: VLAN id to add or remove
189 * @add: if true add filter, if false remove
191 * Sets or clears a bit in the VLAN filter table array based on VLAN id
192 * and if we are adding or removing the filter
194 s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, bool add)
196 u32 index = (vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
197 u32 mask = 1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
199 struct igb_adapter *adapter = hw->back;
202 vfta = adapter->shadow_vfta[index];
204 /* bit was set/cleared before we started */
205 if ((!!(vfta & mask)) == add) {
206 ret_val = -E1000_ERR_CONFIG;
213 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
214 igb_write_vfta_i350(hw, index, vfta);
216 igb_write_vfta(hw, index, vfta);
217 adapter->shadow_vfta[index] = vfta;
223 * igb_check_alt_mac_addr - Check for alternate MAC addr
224 * @hw: pointer to the HW structure
226 * Checks the nvm for an alternate MAC address. An alternate MAC address
227 * can be setup by pre-boot software and must be treated like a permanent
228 * address and must override the actual permanent MAC address. If an
229 * alternate MAC address is found it is saved in the hw struct and
230 * programmed into RAR0 and the function returns success, otherwise the
231 * function returns an error.
233 s32 igb_check_alt_mac_addr(struct e1000_hw *hw)
237 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
238 u8 alt_mac_addr[ETH_ALEN];
240 /* Alternate MAC address is handled by the option ROM for 82580
241 * and newer. SW support not required.
243 if (hw->mac.type >= e1000_82580)
246 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
247 &nvm_alt_mac_addr_offset);
249 hw_dbg("NVM Read Error\n");
253 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
254 (nvm_alt_mac_addr_offset == 0x0000))
255 /* There is no Alternate MAC Address */
258 if (hw->bus.func == E1000_FUNC_1)
259 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
260 if (hw->bus.func == E1000_FUNC_2)
261 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
263 if (hw->bus.func == E1000_FUNC_3)
264 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
265 for (i = 0; i < ETH_ALEN; i += 2) {
266 offset = nvm_alt_mac_addr_offset + (i >> 1);
267 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
269 hw_dbg("NVM Read Error\n");
273 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
274 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
277 /* if multicast bit is set, the alternate address will not be used */
278 if (is_multicast_ether_addr(alt_mac_addr)) {
279 hw_dbg("Ignoring Alternate Mac Address with MC bit set\n");
283 /* We have a valid alternate MAC address, and we want to treat it the
284 * same as the normal permanent MAC address stored by the HW into the
285 * RAR. Do this by mapping this address into RAR0.
287 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
294 * igb_rar_set - Set receive address register
295 * @hw: pointer to the HW structure
296 * @addr: pointer to the receive address
297 * @index: receive address array register
299 * Sets the receive address array register at index to the address passed
302 void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
304 u32 rar_low, rar_high;
306 /* HW expects these in little endian so we reverse the byte order
307 * from network order (big endian) to little endian
309 rar_low = ((u32) addr[0] |
310 ((u32) addr[1] << 8) |
311 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
313 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
315 /* If MAC address zero, no need to set the AV bit */
316 if (rar_low || rar_high)
317 rar_high |= E1000_RAH_AV;
319 /* Some bridges will combine consecutive 32-bit writes into
320 * a single burst write, which will malfunction on some parts.
321 * The flushes avoid this.
323 wr32(E1000_RAL(index), rar_low);
325 wr32(E1000_RAH(index), rar_high);
330 * igb_mta_set - Set multicast filter table address
331 * @hw: pointer to the HW structure
332 * @hash_value: determines the MTA register and bit to set
334 * The multicast table address is a register array of 32-bit registers.
335 * The hash_value is used to determine what register the bit is in, the
336 * current value is read, the new bit is OR'd in and the new value is
337 * written back into the register.
339 void igb_mta_set(struct e1000_hw *hw, u32 hash_value)
341 u32 hash_bit, hash_reg, mta;
343 /* The MTA is a register array of 32-bit registers. It is
344 * treated like an array of (32*mta_reg_count) bits. We want to
345 * set bit BitArray[hash_value]. So we figure out what register
346 * the bit is in, read it, OR in the new bit, then write
347 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
348 * mask to bits 31:5 of the hash value which gives us the
349 * register we're modifying. The hash bit within that register
350 * is determined by the lower 5 bits of the hash value.
352 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
353 hash_bit = hash_value & 0x1F;
355 mta = array_rd32(E1000_MTA, hash_reg);
357 mta |= (1 << hash_bit);
359 array_wr32(E1000_MTA, hash_reg, mta);
364 * igb_hash_mc_addr - Generate a multicast hash value
365 * @hw: pointer to the HW structure
366 * @mc_addr: pointer to a multicast address
368 * Generates a multicast address hash value which is used to determine
369 * the multicast filter table array address and new table value. See
372 static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
374 u32 hash_value, hash_mask;
377 /* Register count multiplied by bits per register */
378 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
380 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
381 * where 0xFF would still fall within the hash mask.
383 while (hash_mask >> bit_shift != 0xFF)
386 /* The portion of the address that is used for the hash table
387 * is determined by the mc_filter_type setting.
388 * The algorithm is such that there is a total of 8 bits of shifting.
389 * The bit_shift for a mc_filter_type of 0 represents the number of
390 * left-shifts where the MSB of mc_addr[5] would still fall within
391 * the hash_mask. Case 0 does this exactly. Since there are a total
392 * of 8 bits of shifting, then mc_addr[4] will shift right the
393 * remaining number of bits. Thus 8 - bit_shift. The rest of the
394 * cases are a variation of this algorithm...essentially raising the
395 * number of bits to shift mc_addr[5] left, while still keeping the
396 * 8-bit shifting total.
398 * For example, given the following Destination MAC Address and an
399 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
400 * we can see that the bit_shift for case 0 is 4. These are the hash
401 * values resulting from each mc_filter_type...
402 * [0] [1] [2] [3] [4] [5]
406 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
407 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
408 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
409 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
411 switch (hw->mac.mc_filter_type) {
426 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
427 (((u16) mc_addr[5]) << bit_shift)));
433 * igb_update_mc_addr_list - Update Multicast addresses
434 * @hw: pointer to the HW structure
435 * @mc_addr_list: array of multicast addresses to program
436 * @mc_addr_count: number of multicast addresses to program
438 * Updates entire Multicast Table Array.
439 * The caller must have a packed mc_addr_list of multicast addresses.
441 void igb_update_mc_addr_list(struct e1000_hw *hw,
442 u8 *mc_addr_list, u32 mc_addr_count)
444 u32 hash_value, hash_bit, hash_reg;
447 /* clear mta_shadow */
448 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
450 /* update mta_shadow from mc_addr_list */
451 for (i = 0; (u32) i < mc_addr_count; i++) {
452 hash_value = igb_hash_mc_addr(hw, mc_addr_list);
454 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
455 hash_bit = hash_value & 0x1F;
457 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
458 mc_addr_list += (ETH_ALEN);
461 /* replace the entire MTA table */
462 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
463 array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]);
468 * igb_clear_hw_cntrs_base - Clear base hardware counters
469 * @hw: pointer to the HW structure
471 * Clears the base hardware counters by reading the counter registers.
473 void igb_clear_hw_cntrs_base(struct e1000_hw *hw)
515 * igb_check_for_copper_link - Check for link (Copper)
516 * @hw: pointer to the HW structure
518 * Checks to see of the link status of the hardware has changed. If a
519 * change in link status has been detected, then we read the PHY registers
520 * to get the current speed/duplex if link exists.
522 s32 igb_check_for_copper_link(struct e1000_hw *hw)
524 struct e1000_mac_info *mac = &hw->mac;
528 /* We only want to go out to the PHY registers to see if Auto-Neg
529 * has completed and/or if our link status has changed. The
530 * get_link_status flag is set upon receiving a Link Status
531 * Change or Rx Sequence Error interrupt.
533 if (!mac->get_link_status) {
538 /* First we want to see if the MII Status Register reports
539 * link. If so, then we want to get the current speed/duplex
542 ret_val = igb_phy_has_link(hw, 1, 0, &link);
547 goto out; /* No link detected */
549 mac->get_link_status = false;
551 /* Check if there was DownShift, must be checked
552 * immediately after link-up
554 igb_check_downshift(hw);
556 /* If we are forcing speed/duplex, then we simply return since
557 * we have already determined whether we have link or not.
560 ret_val = -E1000_ERR_CONFIG;
564 /* Auto-Neg is enabled. Auto Speed Detection takes care
565 * of MAC speed/duplex configuration. So we only need to
566 * configure Collision Distance in the MAC.
568 igb_config_collision_dist(hw);
570 /* Configure Flow Control now that Auto-Neg has completed.
571 * First, we need to restore the desired flow control
572 * settings because we may have had to re-autoneg with a
573 * different link partner.
575 ret_val = igb_config_fc_after_link_up(hw);
577 hw_dbg("Error configuring flow control\n");
584 * igb_setup_link - Setup flow control and link settings
585 * @hw: pointer to the HW structure
587 * Determines which flow control settings to use, then configures flow
588 * control. Calls the appropriate media-specific link configuration
589 * function. Assuming the adapter has a valid link partner, a valid link
590 * should be established. Assumes the hardware has previously been reset
591 * and the transmitter and receiver are not enabled.
593 s32 igb_setup_link(struct e1000_hw *hw)
597 /* In the case of the phy reset being blocked, we already have a link.
598 * We do not need to set it up again.
600 if (igb_check_reset_block(hw))
603 /* If requested flow control is set to default, set flow control
604 * based on the EEPROM flow control settings.
606 if (hw->fc.requested_mode == e1000_fc_default) {
607 ret_val = igb_set_default_fc(hw);
612 /* We want to save off the original Flow Control configuration just
613 * in case we get disconnected and then reconnected into a different
614 * hub or switch with different Flow Control capabilities.
616 hw->fc.current_mode = hw->fc.requested_mode;
618 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
620 /* Call the necessary media_type subroutine to configure the link. */
621 ret_val = hw->mac.ops.setup_physical_interface(hw);
625 /* Initialize the flow control address, type, and PAUSE timer
626 * registers to their default values. This is done even if flow
627 * control is disabled, because it does not hurt anything to
628 * initialize these registers.
630 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
631 wr32(E1000_FCT, FLOW_CONTROL_TYPE);
632 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
633 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
635 wr32(E1000_FCTTV, hw->fc.pause_time);
637 ret_val = igb_set_fc_watermarks(hw);
645 * igb_config_collision_dist - Configure collision distance
646 * @hw: pointer to the HW structure
648 * Configures the collision distance to the default value and is used
649 * during link setup. Currently no func pointer exists and all
650 * implementations are handled in the generic version of this function.
652 void igb_config_collision_dist(struct e1000_hw *hw)
656 tctl = rd32(E1000_TCTL);
658 tctl &= ~E1000_TCTL_COLD;
659 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
661 wr32(E1000_TCTL, tctl);
666 * igb_set_fc_watermarks - Set flow control high/low watermarks
667 * @hw: pointer to the HW structure
669 * Sets the flow control high/low threshold (watermark) registers. If
670 * flow control XON frame transmission is enabled, then set XON frame
671 * tansmission as well.
673 static s32 igb_set_fc_watermarks(struct e1000_hw *hw)
676 u32 fcrtl = 0, fcrth = 0;
678 /* Set the flow control receive threshold registers. Normally,
679 * these registers will be set to a default threshold that may be
680 * adjusted later by the driver's runtime code. However, if the
681 * ability to transmit pause frames is not enabled, then these
682 * registers will be set to 0.
684 if (hw->fc.current_mode & e1000_fc_tx_pause) {
685 /* We need to set up the Receive Threshold high and low water
686 * marks as well as (optionally) enabling the transmission of
689 fcrtl = hw->fc.low_water;
691 fcrtl |= E1000_FCRTL_XONE;
693 fcrth = hw->fc.high_water;
695 wr32(E1000_FCRTL, fcrtl);
696 wr32(E1000_FCRTH, fcrth);
702 * igb_set_default_fc - Set flow control default values
703 * @hw: pointer to the HW structure
705 * Read the EEPROM for the default values for flow control and store the
708 static s32 igb_set_default_fc(struct e1000_hw *hw)
714 /* Read and store word 0x0F of the EEPROM. This word contains bits
715 * that determine the hardware's default PAUSE (flow control) mode,
716 * a bit that determines whether the HW defaults to enabling or
717 * disabling auto-negotiation, and the direction of the
718 * SW defined pins. If there is no SW over-ride of the flow
719 * control setting, then the variable hw->fc will
720 * be initialized based on a value in the EEPROM.
722 if (hw->mac.type == e1000_i350) {
723 lan_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);
724 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG
725 + lan_offset, 1, &nvm_data);
727 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG,
732 hw_dbg("NVM Read Error\n");
736 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
737 hw->fc.requested_mode = e1000_fc_none;
738 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
740 hw->fc.requested_mode = e1000_fc_tx_pause;
742 hw->fc.requested_mode = e1000_fc_full;
749 * igb_force_mac_fc - Force the MAC's flow control settings
750 * @hw: pointer to the HW structure
752 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
753 * device control register to reflect the adapter settings. TFCE and RFCE
754 * need to be explicitly set by software when a copper PHY is used because
755 * autonegotiation is managed by the PHY rather than the MAC. Software must
756 * also configure these bits when link is forced on a fiber connection.
758 s32 igb_force_mac_fc(struct e1000_hw *hw)
763 ctrl = rd32(E1000_CTRL);
765 /* Because we didn't get link via the internal auto-negotiation
766 * mechanism (we either forced link or we got link via PHY
767 * auto-neg), we have to manually enable/disable transmit an
768 * receive flow control.
770 * The "Case" statement below enables/disable flow control
771 * according to the "hw->fc.current_mode" parameter.
773 * The possible values of the "fc" parameter are:
774 * 0: Flow control is completely disabled
775 * 1: Rx flow control is enabled (we can receive pause
776 * frames but not send pause frames).
777 * 2: Tx flow control is enabled (we can send pause frames
778 * frames but we do not receive pause frames).
779 * 3: Both Rx and TX flow control (symmetric) is enabled.
780 * other: No other values should be possible at this point.
782 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
784 switch (hw->fc.current_mode) {
786 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
788 case e1000_fc_rx_pause:
789 ctrl &= (~E1000_CTRL_TFCE);
790 ctrl |= E1000_CTRL_RFCE;
792 case e1000_fc_tx_pause:
793 ctrl &= (~E1000_CTRL_RFCE);
794 ctrl |= E1000_CTRL_TFCE;
797 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
800 hw_dbg("Flow control param set incorrectly\n");
801 ret_val = -E1000_ERR_CONFIG;
805 wr32(E1000_CTRL, ctrl);
812 * igb_config_fc_after_link_up - Configures flow control after link
813 * @hw: pointer to the HW structure
815 * Checks the status of auto-negotiation after link up to ensure that the
816 * speed and duplex were not forced. If the link needed to be forced, then
817 * flow control needs to be forced also. If auto-negotiation is enabled
818 * and did not fail, then we configure flow control based on our link
821 s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
823 struct e1000_mac_info *mac = &hw->mac;
825 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
826 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
829 /* Check for the case where we have fiber media and auto-neg failed
830 * so we had to force link. In this case, we need to force the
831 * configuration of the MAC to match the "fc" parameter.
833 if (mac->autoneg_failed) {
834 if (hw->phy.media_type == e1000_media_type_internal_serdes)
835 ret_val = igb_force_mac_fc(hw);
837 if (hw->phy.media_type == e1000_media_type_copper)
838 ret_val = igb_force_mac_fc(hw);
842 hw_dbg("Error forcing flow control settings\n");
846 /* Check for the case where we have copper media and auto-neg is
847 * enabled. In this case, we need to check and see if Auto-Neg
848 * has completed, and if so, how the PHY and link partner has
849 * flow control configured.
851 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
852 /* Read the MII Status Register and check to see if AutoNeg
853 * has completed. We read this twice because this reg has
854 * some "sticky" (latched) bits.
856 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
860 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
865 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
866 hw_dbg("Copper PHY and Auto Neg has not completed.\n");
870 /* The AutoNeg process has completed, so we now need to
871 * read both the Auto Negotiation Advertisement
872 * Register (Address 4) and the Auto_Negotiation Base
873 * Page Ability Register (Address 5) to determine how
874 * flow control was negotiated.
876 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
880 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
881 &mii_nway_lp_ability_reg);
885 /* Two bits in the Auto Negotiation Advertisement Register
886 * (Address 4) and two bits in the Auto Negotiation Base
887 * Page Ability Register (Address 5) determine flow control
888 * for both the PHY and the link partner. The following
889 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
890 * 1999, describes these PAUSE resolution bits and how flow
891 * control is determined based upon these settings.
892 * NOTE: DC = Don't Care
894 * LOCAL DEVICE | LINK PARTNER
895 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
896 *-------|---------|-------|---------|--------------------
897 * 0 | 0 | DC | DC | e1000_fc_none
898 * 0 | 1 | 0 | DC | e1000_fc_none
899 * 0 | 1 | 1 | 0 | e1000_fc_none
900 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
901 * 1 | 0 | 0 | DC | e1000_fc_none
902 * 1 | DC | 1 | DC | e1000_fc_full
903 * 1 | 1 | 0 | 0 | e1000_fc_none
904 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
906 * Are both PAUSE bits set to 1? If so, this implies
907 * Symmetric Flow Control is enabled at both ends. The
908 * ASM_DIR bits are irrelevant per the spec.
910 * For Symmetric Flow Control:
912 * LOCAL DEVICE | LINK PARTNER
913 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
914 *-------|---------|-------|---------|--------------------
915 * 1 | DC | 1 | DC | E1000_fc_full
918 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
919 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
920 /* Now we need to check if the user selected RX ONLY
921 * of pause frames. In this case, we had to advertise
922 * FULL flow control because we could not advertise RX
923 * ONLY. Hence, we must now check to see if we need to
924 * turn OFF the TRANSMISSION of PAUSE frames.
926 if (hw->fc.requested_mode == e1000_fc_full) {
927 hw->fc.current_mode = e1000_fc_full;
928 hw_dbg("Flow Control = FULL.\n");
930 hw->fc.current_mode = e1000_fc_rx_pause;
931 hw_dbg("Flow Control = RX PAUSE frames only.\n");
934 /* For receiving PAUSE frames ONLY.
936 * LOCAL DEVICE | LINK PARTNER
937 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
938 *-------|---------|-------|---------|--------------------
939 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
941 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
942 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
943 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
944 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
945 hw->fc.current_mode = e1000_fc_tx_pause;
946 hw_dbg("Flow Control = TX PAUSE frames only.\n");
948 /* For transmitting PAUSE frames ONLY.
950 * LOCAL DEVICE | LINK PARTNER
951 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
952 *-------|---------|-------|---------|--------------------
953 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
955 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
956 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
957 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
958 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
959 hw->fc.current_mode = e1000_fc_rx_pause;
960 hw_dbg("Flow Control = RX PAUSE frames only.\n");
962 /* Per the IEEE spec, at this point flow control should be
963 * disabled. However, we want to consider that we could
964 * be connected to a legacy switch that doesn't advertise
965 * desired flow control, but can be forced on the link
966 * partner. So if we advertised no flow control, that is
967 * what we will resolve to. If we advertised some kind of
968 * receive capability (Rx Pause Only or Full Flow Control)
969 * and the link partner advertised none, we will configure
970 * ourselves to enable Rx Flow Control only. We can do
971 * this safely for two reasons: If the link partner really
972 * didn't want flow control enabled, and we enable Rx, no
973 * harm done since we won't be receiving any PAUSE frames
974 * anyway. If the intent on the link partner was to have
975 * flow control enabled, then by us enabling RX only, we
976 * can at least receive pause frames and process them.
977 * This is a good idea because in most cases, since we are
978 * predominantly a server NIC, more times than not we will
979 * be asked to delay transmission of packets than asking
980 * our link partner to pause transmission of frames.
982 else if ((hw->fc.requested_mode == e1000_fc_none) ||
983 (hw->fc.requested_mode == e1000_fc_tx_pause) ||
984 (hw->fc.strict_ieee)) {
985 hw->fc.current_mode = e1000_fc_none;
986 hw_dbg("Flow Control = NONE.\n");
988 hw->fc.current_mode = e1000_fc_rx_pause;
989 hw_dbg("Flow Control = RX PAUSE frames only.\n");
992 /* Now we need to do one last check... If we auto-
993 * negotiated to HALF DUPLEX, flow control should not be
994 * enabled per IEEE 802.3 spec.
996 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
998 hw_dbg("Error getting link speed and duplex\n");
1002 if (duplex == HALF_DUPLEX)
1003 hw->fc.current_mode = e1000_fc_none;
1005 /* Now we call a subroutine to actually force the MAC
1006 * controller to use the correct flow control settings.
1008 ret_val = igb_force_mac_fc(hw);
1010 hw_dbg("Error forcing flow control settings\n");
1014 /* Check for the case where we have SerDes media and auto-neg is
1015 * enabled. In this case, we need to check and see if Auto-Neg
1016 * has completed, and if so, how the PHY and link partner has
1017 * flow control configured.
1019 if ((hw->phy.media_type == e1000_media_type_internal_serdes)
1021 /* Read the PCS_LSTS and check to see if AutoNeg
1024 pcs_status_reg = rd32(E1000_PCS_LSTAT);
1026 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1027 hw_dbg("PCS Auto Neg has not completed.\n");
1031 /* The AutoNeg process has completed, so we now need to
1032 * read both the Auto Negotiation Advertisement
1033 * Register (PCS_ANADV) and the Auto_Negotiation Base
1034 * Page Ability Register (PCS_LPAB) to determine how
1035 * flow control was negotiated.
1037 pcs_adv_reg = rd32(E1000_PCS_ANADV);
1038 pcs_lp_ability_reg = rd32(E1000_PCS_LPAB);
1040 /* Two bits in the Auto Negotiation Advertisement Register
1041 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1042 * Page Ability Register (PCS_LPAB) determine flow control
1043 * for both the PHY and the link partner. The following
1044 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1045 * 1999, describes these PAUSE resolution bits and how flow
1046 * control is determined based upon these settings.
1047 * NOTE: DC = Don't Care
1049 * LOCAL DEVICE | LINK PARTNER
1050 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1051 *-------|---------|-------|---------|--------------------
1052 * 0 | 0 | DC | DC | e1000_fc_none
1053 * 0 | 1 | 0 | DC | e1000_fc_none
1054 * 0 | 1 | 1 | 0 | e1000_fc_none
1055 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1056 * 1 | 0 | 0 | DC | e1000_fc_none
1057 * 1 | DC | 1 | DC | e1000_fc_full
1058 * 1 | 1 | 0 | 0 | e1000_fc_none
1059 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1061 * Are both PAUSE bits set to 1? If so, this implies
1062 * Symmetric Flow Control is enabled at both ends. The
1063 * ASM_DIR bits are irrelevant per the spec.
1065 * For Symmetric Flow Control:
1067 * LOCAL DEVICE | LINK PARTNER
1068 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1069 *-------|---------|-------|---------|--------------------
1070 * 1 | DC | 1 | DC | e1000_fc_full
1073 if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1074 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1075 /* Now we need to check if the user selected Rx ONLY
1076 * of pause frames. In this case, we had to advertise
1077 * FULL flow control because we could not advertise Rx
1078 * ONLY. Hence, we must now check to see if we need to
1079 * turn OFF the TRANSMISSION of PAUSE frames.
1081 if (hw->fc.requested_mode == e1000_fc_full) {
1082 hw->fc.current_mode = e1000_fc_full;
1083 hw_dbg("Flow Control = FULL.\n");
1085 hw->fc.current_mode = e1000_fc_rx_pause;
1086 hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1089 /* For receiving PAUSE frames ONLY.
1091 * LOCAL DEVICE | LINK PARTNER
1092 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1093 *-------|---------|-------|---------|--------------------
1094 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1096 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1097 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1098 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1099 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1100 hw->fc.current_mode = e1000_fc_tx_pause;
1101 hw_dbg("Flow Control = Tx PAUSE frames only.\n");
1103 /* For transmitting PAUSE frames ONLY.
1105 * LOCAL DEVICE | LINK PARTNER
1106 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1107 *-------|---------|-------|---------|--------------------
1108 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1110 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1111 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1112 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1113 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1114 hw->fc.current_mode = e1000_fc_rx_pause;
1115 hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1117 /* Per the IEEE spec, at this point flow control
1118 * should be disabled.
1120 hw->fc.current_mode = e1000_fc_none;
1121 hw_dbg("Flow Control = NONE.\n");
1124 /* Now we call a subroutine to actually force the MAC
1125 * controller to use the correct flow control settings.
1127 pcs_ctrl_reg = rd32(E1000_PCS_LCTL);
1128 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1129 wr32(E1000_PCS_LCTL, pcs_ctrl_reg);
1131 ret_val = igb_force_mac_fc(hw);
1133 hw_dbg("Error forcing flow control settings\n");
1143 * igb_get_speed_and_duplex_copper - Retrieve current speed/duplex
1144 * @hw: pointer to the HW structure
1145 * @speed: stores the current speed
1146 * @duplex: stores the current duplex
1148 * Read the status register for the current speed/duplex and store the current
1149 * speed and duplex for copper connections.
1151 s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
1156 status = rd32(E1000_STATUS);
1157 if (status & E1000_STATUS_SPEED_1000) {
1158 *speed = SPEED_1000;
1159 hw_dbg("1000 Mbs, ");
1160 } else if (status & E1000_STATUS_SPEED_100) {
1162 hw_dbg("100 Mbs, ");
1168 if (status & E1000_STATUS_FD) {
1169 *duplex = FULL_DUPLEX;
1170 hw_dbg("Full Duplex\n");
1172 *duplex = HALF_DUPLEX;
1173 hw_dbg("Half Duplex\n");
1180 * igb_get_hw_semaphore - Acquire hardware semaphore
1181 * @hw: pointer to the HW structure
1183 * Acquire the HW semaphore to access the PHY or NVM
1185 s32 igb_get_hw_semaphore(struct e1000_hw *hw)
1189 s32 timeout = hw->nvm.word_size + 1;
1192 /* Get the SW semaphore */
1193 while (i < timeout) {
1194 swsm = rd32(E1000_SWSM);
1195 if (!(swsm & E1000_SWSM_SMBI))
1203 hw_dbg("Driver can't access device - SMBI bit is set.\n");
1204 ret_val = -E1000_ERR_NVM;
1208 /* Get the FW semaphore. */
1209 for (i = 0; i < timeout; i++) {
1210 swsm = rd32(E1000_SWSM);
1211 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1213 /* Semaphore acquired if bit latched */
1214 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
1221 /* Release semaphores */
1222 igb_put_hw_semaphore(hw);
1223 hw_dbg("Driver can't access the NVM\n");
1224 ret_val = -E1000_ERR_NVM;
1233 * igb_put_hw_semaphore - Release hardware semaphore
1234 * @hw: pointer to the HW structure
1236 * Release hardware semaphore used to access the PHY or NVM
1238 void igb_put_hw_semaphore(struct e1000_hw *hw)
1242 swsm = rd32(E1000_SWSM);
1244 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1246 wr32(E1000_SWSM, swsm);
1250 * igb_get_auto_rd_done - Check for auto read completion
1251 * @hw: pointer to the HW structure
1253 * Check EEPROM for Auto Read done bit.
1255 s32 igb_get_auto_rd_done(struct e1000_hw *hw)
1261 while (i < AUTO_READ_DONE_TIMEOUT) {
1262 if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD)
1264 usleep_range(1000, 2000);
1268 if (i == AUTO_READ_DONE_TIMEOUT) {
1269 hw_dbg("Auto read by HW from NVM has not completed.\n");
1270 ret_val = -E1000_ERR_RESET;
1279 * igb_valid_led_default - Verify a valid default LED config
1280 * @hw: pointer to the HW structure
1281 * @data: pointer to the NVM (EEPROM)
1283 * Read the EEPROM for the current default LED configuration. If the
1284 * LED configuration is not valid, set to a valid LED configuration.
1286 static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data)
1290 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1292 hw_dbg("NVM Read Error\n");
1296 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1297 switch (hw->phy.media_type) {
1298 case e1000_media_type_internal_serdes:
1299 *data = ID_LED_DEFAULT_82575_SERDES;
1301 case e1000_media_type_copper:
1303 *data = ID_LED_DEFAULT;
1313 * @hw: pointer to the HW structure
1316 s32 igb_id_led_init(struct e1000_hw *hw)
1318 struct e1000_mac_info *mac = &hw->mac;
1320 const u32 ledctl_mask = 0x000000FF;
1321 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1322 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1324 const u16 led_mask = 0x0F;
1326 /* i210 and i211 devices have different LED mechanism */
1327 if ((hw->mac.type == e1000_i210) ||
1328 (hw->mac.type == e1000_i211))
1329 ret_val = igb_valid_led_default_i210(hw, &data);
1331 ret_val = igb_valid_led_default(hw, &data);
1336 mac->ledctl_default = rd32(E1000_LEDCTL);
1337 mac->ledctl_mode1 = mac->ledctl_default;
1338 mac->ledctl_mode2 = mac->ledctl_default;
1340 for (i = 0; i < 4; i++) {
1341 temp = (data >> (i << 2)) & led_mask;
1343 case ID_LED_ON1_DEF2:
1344 case ID_LED_ON1_ON2:
1345 case ID_LED_ON1_OFF2:
1346 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1347 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1349 case ID_LED_OFF1_DEF2:
1350 case ID_LED_OFF1_ON2:
1351 case ID_LED_OFF1_OFF2:
1352 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1353 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1360 case ID_LED_DEF1_ON2:
1361 case ID_LED_ON1_ON2:
1362 case ID_LED_OFF1_ON2:
1363 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1364 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1366 case ID_LED_DEF1_OFF2:
1367 case ID_LED_ON1_OFF2:
1368 case ID_LED_OFF1_OFF2:
1369 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1370 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1383 * igb_cleanup_led - Set LED config to default operation
1384 * @hw: pointer to the HW structure
1386 * Remove the current LED configuration and set the LED configuration
1387 * to the default value, saved from the EEPROM.
1389 s32 igb_cleanup_led(struct e1000_hw *hw)
1391 wr32(E1000_LEDCTL, hw->mac.ledctl_default);
1396 * igb_blink_led - Blink LED
1397 * @hw: pointer to the HW structure
1399 * Blink the led's which are set to be on.
1401 s32 igb_blink_led(struct e1000_hw *hw)
1403 u32 ledctl_blink = 0;
1406 if (hw->phy.media_type == e1000_media_type_fiber) {
1407 /* always blink LED0 for PCI-E fiber */
1408 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1409 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1411 /* Set the blink bit for each LED that's "on" (0x0E)
1412 * (or "off" if inverted) in ledctl_mode2. The blink
1413 * logic in hardware only works when mode is set to "on"
1414 * so it must be changed accordingly when the mode is
1415 * "off" and inverted.
1417 ledctl_blink = hw->mac.ledctl_mode2;
1418 for (i = 0; i < 32; i += 8) {
1419 u32 mode = (hw->mac.ledctl_mode2 >> i) &
1420 E1000_LEDCTL_LED0_MODE_MASK;
1421 u32 led_default = hw->mac.ledctl_default >> i;
1423 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1424 (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1425 ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1426 (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1428 ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1429 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1430 E1000_LEDCTL_MODE_LED_ON) << i;
1435 wr32(E1000_LEDCTL, ledctl_blink);
1441 * igb_led_off - Turn LED off
1442 * @hw: pointer to the HW structure
1446 s32 igb_led_off(struct e1000_hw *hw)
1448 switch (hw->phy.media_type) {
1449 case e1000_media_type_copper:
1450 wr32(E1000_LEDCTL, hw->mac.ledctl_mode1);
1460 * igb_disable_pcie_master - Disables PCI-express master access
1461 * @hw: pointer to the HW structure
1463 * Returns 0 (0) if successful, else returns -10
1464 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1465 * the master requests to be disabled.
1467 * Disables PCI-Express master access and verifies there are no pending
1470 s32 igb_disable_pcie_master(struct e1000_hw *hw)
1473 s32 timeout = MASTER_DISABLE_TIMEOUT;
1476 if (hw->bus.type != e1000_bus_type_pci_express)
1479 ctrl = rd32(E1000_CTRL);
1480 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1481 wr32(E1000_CTRL, ctrl);
1484 if (!(rd32(E1000_STATUS) &
1485 E1000_STATUS_GIO_MASTER_ENABLE))
1492 hw_dbg("Master requests are pending.\n");
1493 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
1502 * igb_validate_mdi_setting - Verify MDI/MDIx settings
1503 * @hw: pointer to the HW structure
1505 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1506 * set, which is forced to MDI mode only.
1508 s32 igb_validate_mdi_setting(struct e1000_hw *hw)
1512 /* All MDI settings are supported on 82580 and newer. */
1513 if (hw->mac.type >= e1000_82580)
1516 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
1517 hw_dbg("Invalid MDI setting detected\n");
1519 ret_val = -E1000_ERR_CONFIG;
1528 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1529 * @hw: pointer to the HW structure
1530 * @reg: 32bit register offset such as E1000_SCTL
1531 * @offset: register offset to write to
1532 * @data: data to write at register offset
1534 * Writes an address/data control type register. There are several of these
1535 * and they all have the format address << 8 | data and bit 31 is polled for
1538 s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
1539 u32 offset, u8 data)
1541 u32 i, regvalue = 0;
1544 /* Set up the address and data */
1545 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
1546 wr32(reg, regvalue);
1548 /* Poll the ready bit to see if the MDI read completed */
1549 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
1551 regvalue = rd32(reg);
1552 if (regvalue & E1000_GEN_CTL_READY)
1555 if (!(regvalue & E1000_GEN_CTL_READY)) {
1556 hw_dbg("Reg %08x did not indicate ready\n", reg);
1557 ret_val = -E1000_ERR_PHY;
1566 * igb_enable_mng_pass_thru - Enable processing of ARP's
1567 * @hw: pointer to the HW structure
1569 * Verifies the hardware needs to leave interface enabled so that frames can
1570 * be directed to and from the management interface.
1572 bool igb_enable_mng_pass_thru(struct e1000_hw *hw)
1576 bool ret_val = false;
1578 if (!hw->mac.asf_firmware_present)
1581 manc = rd32(E1000_MANC);
1583 if (!(manc & E1000_MANC_RCV_TCO_EN))
1586 if (hw->mac.arc_subsystem_valid) {
1587 fwsm = rd32(E1000_FWSM);
1588 factps = rd32(E1000_FACTPS);
1590 if (!(factps & E1000_FACTPS_MNGCG) &&
1591 ((fwsm & E1000_FWSM_MODE_MASK) ==
1592 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
1597 if ((manc & E1000_MANC_SMBUS_EN) &&
1598 !(manc & E1000_MANC_ASF_EN)) {