kernel/drivers/net/ethernet/intel/igb/e1000_hw.h

   1 /* Intel(R) Gigabit Ethernet Linux driver
   2  * Copyright(c) 2007-2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  *
   7  * This program is distributed in the hope it will be useful, but WITHOUT
   8  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   9  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  10  * more details.
  11  *
  12  * You should have received a copy of the GNU General Public License along with
  13  * this program; if not, see <http://www.gnu.org/licenses/>.
  14  *
  15  * The full GNU General Public License is included in this distribution in
  16  * the file called "COPYING".
  17  *
  18  * Contact Information:
  19  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  20  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  21  */
  22
  23 #ifndef _E1000_HW_H_
  24 #define _E1000_HW_H_
  25
  26 #include <linux/types.h>
  27 #include <linux/delay.h>
  28 #include <linux/io.h>
  29 #include <linux/netdevice.h>
  30
  31 #include "e1000_regs.h"
  32 #include "e1000_defines.h"
  33
  34 struct e1000_hw;
  35
  36 #define E1000_DEV_ID_82576                      0x10C9
  37 #define E1000_DEV_ID_82576_FIBER                0x10E6
  38 #define E1000_DEV_ID_82576_SERDES               0x10E7
  39 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
  40 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
  41 #define E1000_DEV_ID_82576_NS                   0x150A
  42 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
  43 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
  44 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
  45 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
  46 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
  47 #define E1000_DEV_ID_82580_COPPER               0x150E
  48 #define E1000_DEV_ID_82580_FIBER                0x150F
  49 #define E1000_DEV_ID_82580_SERDES               0x1510
  50 #define E1000_DEV_ID_82580_SGMII                0x1511
  51 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
  52 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
  53 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
  54 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
  55 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
  56 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
  57 #define E1000_DEV_ID_I350_COPPER                0x1521
  58 #define E1000_DEV_ID_I350_FIBER                 0x1522
  59 #define E1000_DEV_ID_I350_SERDES                0x1523
  60 #define E1000_DEV_ID_I350_SGMII                 0x1524
  61 #define E1000_DEV_ID_I210_COPPER                0x1533
  62 #define E1000_DEV_ID_I210_FIBER                 0x1536
  63 #define E1000_DEV_ID_I210_SERDES                0x1537
  64 #define E1000_DEV_ID_I210_SGMII                 0x1538
  65 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
  66 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
  67 #define E1000_DEV_ID_I211_COPPER                0x1539
  68 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
  69 #define E1000_DEV_ID_I354_SGMII                 0x1F41
  70 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
  71
  72 #define E1000_REVISION_2 2
  73 #define E1000_REVISION_4 4
  74
  75 #define E1000_FUNC_0     0
  76 #define E1000_FUNC_1     1
  77 #define E1000_FUNC_2     2
  78 #define E1000_FUNC_3     3
  79
  80 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
  81 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
  82 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
  83 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9
  84
  85 enum e1000_mac_type {
  86         e1000_undefined = 0,
  87         e1000_82575,
  88         e1000_82576,
  89         e1000_82580,
  90         e1000_i350,
  91         e1000_i354,
  92         e1000_i210,
  93         e1000_i211,
  94         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
  95 };
  96
  97 enum e1000_media_type {
  98         e1000_media_type_unknown = 0,
  99         e1000_media_type_copper = 1,
 100         e1000_media_type_fiber = 2,
 101         e1000_media_type_internal_serdes = 3,
 102         e1000_num_media_types
 103 };
 104
 105 enum e1000_nvm_type {
 106         e1000_nvm_unknown = 0,
 107         e1000_nvm_none,
 108         e1000_nvm_eeprom_spi,
 109         e1000_nvm_flash_hw,
 110         e1000_nvm_invm,
 111         e1000_nvm_flash_sw
 112 };
 113
 114 enum e1000_nvm_override {
 115         e1000_nvm_override_none = 0,
 116         e1000_nvm_override_spi_small,
 117         e1000_nvm_override_spi_large,
 118 };
 119
 120 enum e1000_phy_type {
 121         e1000_phy_unknown = 0,
 122         e1000_phy_none,
 123         e1000_phy_m88,
 124         e1000_phy_igp,
 125         e1000_phy_igp_2,
 126         e1000_phy_gg82563,
 127         e1000_phy_igp_3,
 128         e1000_phy_ife,
 129         e1000_phy_82580,
 130         e1000_phy_i210,
 131 };
 132
 133 enum e1000_bus_type {
 134         e1000_bus_type_unknown = 0,
 135         e1000_bus_type_pci,
 136         e1000_bus_type_pcix,
 137         e1000_bus_type_pci_express,
 138         e1000_bus_type_reserved
 139 };
 140
 141 enum e1000_bus_speed {
 142         e1000_bus_speed_unknown = 0,
 143         e1000_bus_speed_33,
 144         e1000_bus_speed_66,
 145         e1000_bus_speed_100,
 146         e1000_bus_speed_120,
 147         e1000_bus_speed_133,
 148         e1000_bus_speed_2500,
 149         e1000_bus_speed_5000,
 150         e1000_bus_speed_reserved
 151 };
 152
 153 enum e1000_bus_width {
 154         e1000_bus_width_unknown = 0,
 155         e1000_bus_width_pcie_x1,
 156         e1000_bus_width_pcie_x2,
 157         e1000_bus_width_pcie_x4 = 4,
 158         e1000_bus_width_pcie_x8 = 8,
 159         e1000_bus_width_32,
 160         e1000_bus_width_64,
 161         e1000_bus_width_reserved
 162 };
 163
 164 enum e1000_1000t_rx_status {
 165         e1000_1000t_rx_status_not_ok = 0,
 166         e1000_1000t_rx_status_ok,
 167         e1000_1000t_rx_status_undefined = 0xFF
 168 };
 169
 170 enum e1000_rev_polarity {
 171         e1000_rev_polarity_normal = 0,
 172         e1000_rev_polarity_reversed,
 173         e1000_rev_polarity_undefined = 0xFF
 174 };
 175
 176 enum e1000_fc_mode {
 177         e1000_fc_none = 0,
 178         e1000_fc_rx_pause,
 179         e1000_fc_tx_pause,
 180         e1000_fc_full,
 181         e1000_fc_default = 0xFF
 182 };
 183
 184 /* Statistics counters collected by the MAC */
 185 struct e1000_hw_stats {
 186         u64 crcerrs;
 187         u64 algnerrc;
 188         u64 symerrs;
 189         u64 rxerrc;
 190         u64 mpc;
 191         u64 scc;
 192         u64 ecol;
 193         u64 mcc;
 194         u64 latecol;
 195         u64 colc;
 196         u64 dc;
 197         u64 tncrs;
 198         u64 sec;
 199         u64 cexterr;
 200         u64 rlec;
 201         u64 xonrxc;
 202         u64 xontxc;
 203         u64 xoffrxc;
 204         u64 xofftxc;
 205         u64 fcruc;
 206         u64 prc64;
 207         u64 prc127;
 208         u64 prc255;
 209         u64 prc511;
 210         u64 prc1023;
 211         u64 prc1522;
 212         u64 gprc;
 213         u64 bprc;
 214         u64 mprc;
 215         u64 gptc;
 216         u64 gorc;
 217         u64 gotc;
 218         u64 rnbc;
 219         u64 ruc;
 220         u64 rfc;
 221         u64 roc;
 222         u64 rjc;
 223         u64 mgprc;
 224         u64 mgpdc;
 225         u64 mgptc;
 226         u64 tor;
 227         u64 tot;
 228         u64 tpr;
 229         u64 tpt;
 230         u64 ptc64;
 231         u64 ptc127;
 232         u64 ptc255;
 233         u64 ptc511;
 234         u64 ptc1023;
 235         u64 ptc1522;
 236         u64 mptc;
 237         u64 bptc;
 238         u64 tsctc;
 239         u64 tsctfc;
 240         u64 iac;
 241         u64 icrxptc;
 242         u64 icrxatc;
 243         u64 ictxptc;
 244         u64 ictxatc;
 245         u64 ictxqec;
 246         u64 ictxqmtc;
 247         u64 icrxdmtc;
 248         u64 icrxoc;
 249         u64 cbtmpc;
 250         u64 htdpmc;
 251         u64 cbrdpc;
 252         u64 cbrmpc;
 253         u64 rpthc;
 254         u64 hgptc;
 255         u64 htcbdpc;
 256         u64 hgorc;
 257         u64 hgotc;
 258         u64 lenerrs;
 259         u64 scvpc;
 260         u64 hrmpc;
 261         u64 doosync;
 262         u64 o2bgptc;
 263         u64 o2bspc;
 264         u64 b2ospc;
 265         u64 b2ogprc;
 266 };
 267
 268 struct e1000_host_mng_dhcp_cookie {
 269         u32 signature;
 270         u8  status;
 271         u8  reserved0;
 272         u16 vlan_id;
 273         u32 reserved1;
 274         u16 reserved2;
 275         u8  reserved3;
 276         u8  checksum;
 277 };
 278
 279 /* Host Interface "Rev 1" */
 280 struct e1000_host_command_header {
 281         u8 command_id;
 282         u8 command_length;
 283         u8 command_options;
 284         u8 checksum;
 285 };
 286
 287 #define E1000_HI_MAX_DATA_LENGTH     252
 288 struct e1000_host_command_info {
 289         struct e1000_host_command_header command_header;
 290         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 291 };
 292
 293 /* Host Interface "Rev 2" */
 294 struct e1000_host_mng_command_header {
 295         u8  command_id;
 296         u8  checksum;
 297         u16 reserved1;
 298         u16 reserved2;
 299         u16 command_length;
 300 };
 301
 302 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 303 struct e1000_host_mng_command_info {
 304         struct e1000_host_mng_command_header command_header;
 305         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 306 };
 307
 308 #include "e1000_mac.h"
 309 #include "e1000_phy.h"
 310 #include "e1000_nvm.h"
 311 #include "e1000_mbx.h"
 312
 313 struct e1000_mac_operations {
 314         s32 (*check_for_link)(struct e1000_hw *);
 315         s32 (*reset_hw)(struct e1000_hw *);
 316         s32 (*init_hw)(struct e1000_hw *);
 317         bool (*check_mng_mode)(struct e1000_hw *);
 318         s32 (*setup_physical_interface)(struct e1000_hw *);
 319         void (*rar_set)(struct e1000_hw *, u8 *, u32);
 320         s32 (*read_mac_addr)(struct e1000_hw *);
 321         s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
 322         s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
 323         void (*release_swfw_sync)(struct e1000_hw *, u16);
 324 #ifdef CONFIG_IGB_HWMON
 325         s32 (*get_thermal_sensor_data)(struct e1000_hw *);
 326         s32 (*init_thermal_sensor_thresh)(struct e1000_hw *);
 327 #endif
 328
 329 };
 330
 331 struct e1000_phy_operations {
 332         s32 (*acquire)(struct e1000_hw *);
 333         s32 (*check_polarity)(struct e1000_hw *);
 334         s32 (*check_reset_block)(struct e1000_hw *);
 335         s32 (*force_speed_duplex)(struct e1000_hw *);
 336         s32 (*get_cfg_done)(struct e1000_hw *hw);
 337         s32 (*get_cable_length)(struct e1000_hw *);
 338         s32 (*get_phy_info)(struct e1000_hw *);
 339         s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
 340         void (*release)(struct e1000_hw *);
 341         s32 (*reset)(struct e1000_hw *);
 342         s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
 343         s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
 344         s32 (*write_reg)(struct e1000_hw *, u32, u16);
 345         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 346         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 347 };
 348
 349 struct e1000_nvm_operations {
 350         s32 (*acquire)(struct e1000_hw *);
 351         s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
 352         void (*release)(struct e1000_hw *);
 353         s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
 354         s32 (*update)(struct e1000_hw *);
 355         s32 (*validate)(struct e1000_hw *);
 356         s32 (*valid_led_default)(struct e1000_hw *, u16 *);
 357 };
 358
 359 #define E1000_MAX_SENSORS               3
 360
 361 struct e1000_thermal_diode_data {
 362         u8 location;
 363         u8 temp;
 364         u8 caution_thresh;
 365         u8 max_op_thresh;
 366 };
 367
 368 struct e1000_thermal_sensor_data {
 369         struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];
 370 };
 371
 372 struct e1000_info {
 373         s32 (*get_invariants)(struct e1000_hw *);
 374         struct e1000_mac_operations *mac_ops;
 375         struct e1000_phy_operations *phy_ops;
 376         struct e1000_nvm_operations *nvm_ops;
 377 };
 378
 379 extern const struct e1000_info e1000_82575_info;
 380
 381 struct e1000_mac_info {
 382         struct e1000_mac_operations ops;
 383
 384         u8 addr[6];
 385         u8 perm_addr[6];
 386
 387         enum e1000_mac_type type;
 388
 389         u32 ledctl_default;
 390         u32 ledctl_mode1;
 391         u32 ledctl_mode2;
 392         u32 mc_filter_type;
 393         u32 txcw;
 394
 395         u16 mta_reg_count;
 396         u16 uta_reg_count;
 397
 398         /* Maximum size of the MTA register table in all supported adapters */
 399         #define MAX_MTA_REG 128
 400         u32 mta_shadow[MAX_MTA_REG];
 401         u16 rar_entry_count;
 402
 403         u8  forced_speed_duplex;
 404
 405         bool adaptive_ifs;
 406         bool arc_subsystem_valid;
 407         bool asf_firmware_present;
 408         bool autoneg;
 409         bool autoneg_failed;
 410         bool disable_hw_init_bits;
 411         bool get_link_status;
 412         bool ifs_params_forced;
 413         bool in_ifs_mode;
 414         bool report_tx_early;
 415         bool serdes_has_link;
 416         bool tx_pkt_filtering;
 417         struct e1000_thermal_sensor_data thermal_sensor_data;
 418 };
 419
 420 struct e1000_phy_info {
 421         struct e1000_phy_operations ops;
 422
 423         enum e1000_phy_type type;
 424
 425         enum e1000_1000t_rx_status local_rx;
 426         enum e1000_1000t_rx_status remote_rx;
 427         enum e1000_ms_type ms_type;
 428         enum e1000_ms_type original_ms_type;
 429         enum e1000_rev_polarity cable_polarity;
 430         enum e1000_smart_speed smart_speed;
 431
 432         u32 addr;
 433         u32 id;
 434         u32 reset_delay_us; /* in usec */
 435         u32 revision;
 436
 437         enum e1000_media_type media_type;
 438
 439         u16 autoneg_advertised;
 440         u16 autoneg_mask;
 441         u16 cable_length;
 442         u16 max_cable_length;
 443         u16 min_cable_length;
 444
 445         u8 mdix;
 446
 447         bool disable_polarity_correction;
 448         bool is_mdix;
 449         bool polarity_correction;
 450         bool reset_disable;
 451         bool speed_downgraded;
 452         bool autoneg_wait_to_complete;
 453 };
 454
 455 struct e1000_nvm_info {
 456         struct e1000_nvm_operations ops;
 457         enum e1000_nvm_type type;
 458         enum e1000_nvm_override override;
 459
 460         u32 flash_bank_size;
 461         u32 flash_base_addr;
 462
 463         u16 word_size;
 464         u16 delay_usec;
 465         u16 address_bits;
 466         u16 opcode_bits;
 467         u16 page_size;
 468 };
 469
 470 struct e1000_bus_info {
 471         enum e1000_bus_type type;
 472         enum e1000_bus_speed speed;
 473         enum e1000_bus_width width;
 474
 475         u32 snoop;
 476
 477         u16 func;
 478         u16 pci_cmd_word;
 479 };
 480
 481 struct e1000_fc_info {
 482         u32 high_water;     /* Flow control high-water mark */
 483         u32 low_water;      /* Flow control low-water mark */
 484         u16 pause_time;     /* Flow control pause timer */
 485         bool send_xon;      /* Flow control send XON */
 486         bool strict_ieee;   /* Strict IEEE mode */
 487         enum e1000_fc_mode current_mode; /* Type of flow control */
 488         enum e1000_fc_mode requested_mode;
 489 };
 490
 491 struct e1000_mbx_operations {
 492         s32 (*init_params)(struct e1000_hw *hw);
 493         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 494         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 495         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 496         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 497         s32 (*check_for_msg)(struct e1000_hw *, u16);
 498         s32 (*check_for_ack)(struct e1000_hw *, u16);
 499         s32 (*check_for_rst)(struct e1000_hw *, u16);
 500 };
 501
 502 struct e1000_mbx_stats {
 503         u32 msgs_tx;
 504         u32 msgs_rx;
 505
 506         u32 acks;
 507         u32 reqs;
 508         u32 rsts;
 509 };
 510
 511 struct e1000_mbx_info {
 512         struct e1000_mbx_operations ops;
 513         struct e1000_mbx_stats stats;
 514         u32 timeout;
 515         u32 usec_delay;
 516         u16 size;
 517 };
 518
 519 struct e1000_dev_spec_82575 {
 520         bool sgmii_active;
 521         bool global_device_reset;
 522         bool eee_disable;
 523         bool clear_semaphore_once;
 524         struct e1000_sfp_flags eth_flags;
 525         bool module_plugged;
 526         u8 media_port;
 527         bool media_changed;
 528         bool mas_capable;
 529 };
 530
 531 struct e1000_hw {
 532         void *back;
 533
 534         u8 __iomem *hw_addr;
 535         u8 __iomem *flash_address;
 536         unsigned long io_base;
 537
 538         struct e1000_mac_info  mac;
 539         struct e1000_fc_info   fc;
 540         struct e1000_phy_info  phy;
 541         struct e1000_nvm_info  nvm;
 542         struct e1000_bus_info  bus;
 543         struct e1000_mbx_info mbx;
 544         struct e1000_host_mng_dhcp_cookie mng_cookie;
 545
 546         union {
 547                 struct e1000_dev_spec_82575     _82575;
 548         } dev_spec;
 549
 550         u16 device_id;
 551         u16 subsystem_vendor_id;
 552         u16 subsystem_device_id;
 553         u16 vendor_id;
 554
 555         u8  revision_id;
 556 };
 557
 558 struct net_device *igb_get_hw_dev(struct e1000_hw *hw);
 559 #define hw_dbg(format, arg...) \
 560         netdev_dbg(igb_get_hw_dev(hw), format, ##arg)
 561
 562 /* These functions must be implemented by drivers */
 563 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 564 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 565
 566 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 567 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 568 #endif /* _E1000_HW_H_ */