kernel/drivers/net/ethernet/intel/i40evf/i40e_type.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2015 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #ifndef _I40E_TYPE_H_
  28 #define _I40E_TYPE_H_
  29
  30 #include "i40e_status.h"
  31 #include "i40e_osdep.h"
  32 #include "i40e_register.h"
  33 #include "i40e_adminq.h"
  34 #include "i40e_hmc.h"
  35 #include "i40e_lan_hmc.h"
  36
  37 /* Device IDs */
  38 #define I40E_DEV_ID_SFP_XL710           0x1572
  39 #define I40E_DEV_ID_QEMU                0x1574
  40 #define I40E_DEV_ID_KX_A                0x157F
  41 #define I40E_DEV_ID_KX_B                0x1580
  42 #define I40E_DEV_ID_KX_C                0x1581
  43 #define I40E_DEV_ID_QSFP_A              0x1583
  44 #define I40E_DEV_ID_QSFP_B              0x1584
  45 #define I40E_DEV_ID_QSFP_C              0x1585
  46 #define I40E_DEV_ID_10G_BASE_T          0x1586
  47 #define I40E_DEV_ID_20G_KR2             0x1587
  48 #define I40E_DEV_ID_VF                  0x154C
  49 #define I40E_DEV_ID_VF_HV               0x1571
  50
  51 #define i40e_is_40G_device(d)           ((d) == I40E_DEV_ID_QSFP_A  || \
  52                                          (d) == I40E_DEV_ID_QSFP_B  || \
  53                                          (d) == I40E_DEV_ID_QSFP_C)
  54
  55 /* I40E_MASK is a macro used on 32 bit registers */
  56 #define I40E_MASK(mask, shift) (mask << shift)
  57
  58 #define I40E_MAX_VSI_QP                 16
  59 #define I40E_MAX_VF_VSI                 3
  60 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  61 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  62
  63 /* Max default timeout in ms, */
  64 #define I40E_MAX_NVM_TIMEOUT            18000
  65
  66 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  67 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  68
  69 /* forward declaration */
  70 struct i40e_hw;
  71 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  72
  73 /* Data type manipulation macros. */
  74
  75 #define I40E_DESC_UNUSED(R)     \
  76         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  77         (R)->next_to_clean - (R)->next_to_use - 1)
  78
  79 /* bitfields for Tx queue mapping in QTX_CTL */
  80 #define I40E_QTX_CTL_VF_QUEUE   0x0
  81 #define I40E_QTX_CTL_VM_QUEUE   0x1
  82 #define I40E_QTX_CTL_PF_QUEUE   0x2
  83
  84 /* debug masks - set these bits in hw->debug_mask to control output */
  85 enum i40e_debug_mask {
  86         I40E_DEBUG_INIT                 = 0x00000001,
  87         I40E_DEBUG_RELEASE              = 0x00000002,
  88
  89         I40E_DEBUG_LINK                 = 0x00000010,
  90         I40E_DEBUG_PHY                  = 0x00000020,
  91         I40E_DEBUG_HMC                  = 0x00000040,
  92         I40E_DEBUG_NVM                  = 0x00000080,
  93         I40E_DEBUG_LAN                  = 0x00000100,
  94         I40E_DEBUG_FLOW                 = 0x00000200,
  95         I40E_DEBUG_DCB                  = 0x00000400,
  96         I40E_DEBUG_DIAG                 = 0x00000800,
  97         I40E_DEBUG_FD                   = 0x00001000,
  98
  99         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 100         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 101         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 102         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 103         I40E_DEBUG_AQ                   = 0x0F000000,
 104
 105         I40E_DEBUG_USER                 = 0xF0000000,
 106
 107         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 108 };
 109
 110 /* These are structs for managing the hardware information and the operations.
 111  * The structures of function pointers are filled out at init time when we
 112  * know for sure exactly which hardware we're working with.  This gives us the
 113  * flexibility of using the same main driver code but adapting to slightly
 114  * different hardware needs as new parts are developed.  For this architecture,
 115  * the Firmware and AdminQ are intended to insulate the driver from most of the
 116  * future changes, but these structures will also do part of the job.
 117  */
 118 enum i40e_mac_type {
 119         I40E_MAC_UNKNOWN = 0,
 120         I40E_MAC_X710,
 121         I40E_MAC_XL710,
 122         I40E_MAC_VF,
 123         I40E_MAC_GENERIC,
 124 };
 125
 126 enum i40e_media_type {
 127         I40E_MEDIA_TYPE_UNKNOWN = 0,
 128         I40E_MEDIA_TYPE_FIBER,
 129         I40E_MEDIA_TYPE_BASET,
 130         I40E_MEDIA_TYPE_BACKPLANE,
 131         I40E_MEDIA_TYPE_CX4,
 132         I40E_MEDIA_TYPE_DA,
 133         I40E_MEDIA_TYPE_VIRTUAL
 134 };
 135
 136 enum i40e_fc_mode {
 137         I40E_FC_NONE = 0,
 138         I40E_FC_RX_PAUSE,
 139         I40E_FC_TX_PAUSE,
 140         I40E_FC_FULL,
 141         I40E_FC_PFC,
 142         I40E_FC_DEFAULT
 143 };
 144
 145 enum i40e_set_fc_aq_failures {
 146         I40E_SET_FC_AQ_FAIL_NONE = 0,
 147         I40E_SET_FC_AQ_FAIL_GET = 1,
 148         I40E_SET_FC_AQ_FAIL_SET = 2,
 149         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 150         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 151 };
 152
 153 enum i40e_vsi_type {
 154         I40E_VSI_MAIN = 0,
 155         I40E_VSI_VMDQ1,
 156         I40E_VSI_VMDQ2,
 157         I40E_VSI_CTRL,
 158         I40E_VSI_FCOE,
 159         I40E_VSI_MIRROR,
 160         I40E_VSI_SRIOV,
 161         I40E_VSI_FDIR,
 162         I40E_VSI_TYPE_UNKNOWN
 163 };
 164
 165 enum i40e_queue_type {
 166         I40E_QUEUE_TYPE_RX = 0,
 167         I40E_QUEUE_TYPE_TX,
 168         I40E_QUEUE_TYPE_PE_CEQ,
 169         I40E_QUEUE_TYPE_UNKNOWN
 170 };
 171
 172 struct i40e_link_status {
 173         enum i40e_aq_phy_type phy_type;
 174         enum i40e_aq_link_speed link_speed;
 175         u8 link_info;
 176         u8 an_info;
 177         u8 ext_info;
 178         u8 loopback;
 179         /* is Link Status Event notification to SW enabled */
 180         bool lse_enable;
 181         u16 max_frame_size;
 182         bool crc_enable;
 183         u8 pacing;
 184         u8 requested_speeds;
 185 };
 186
 187 struct i40e_phy_info {
 188         struct i40e_link_status link_info;
 189         struct i40e_link_status link_info_old;
 190         u32 autoneg_advertised;
 191         u32 phy_id;
 192         u32 module_type;
 193         bool get_link_info;
 194         enum i40e_media_type media_type;
 195 };
 196
 197 #define I40E_HW_CAP_MAX_GPIO                    30
 198 /* Capabilities of a PF or a VF or the whole device */
 199 struct i40e_hw_capabilities {
 200         u32  switch_mode;
 201 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 202 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 203 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 204
 205         u32  management_mode;
 206         u32  npar_enable;
 207         u32  os2bmc;
 208         u32  valid_functions;
 209         bool sr_iov_1_1;
 210         bool vmdq;
 211         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 212         bool evb_802_1_qbh; /* Bridge Port Extension */
 213         bool dcb;
 214         bool fcoe;
 215         bool iscsi; /* Indicates iSCSI enabled */
 216         bool mfp_mode_1;
 217         bool mgmt_cem;
 218         bool ieee_1588;
 219         bool iwarp;
 220         bool fd;
 221         u32 fd_filters_guaranteed;
 222         u32 fd_filters_best_effort;
 223         bool rss;
 224         u32 rss_table_size;
 225         u32 rss_table_entry_width;
 226         bool led[I40E_HW_CAP_MAX_GPIO];
 227         bool sdp[I40E_HW_CAP_MAX_GPIO];
 228         u32 nvm_image_type;
 229         u32 num_flow_director_filters;
 230         u32 num_vfs;
 231         u32 vf_base_id;
 232         u32 num_vsis;
 233         u32 num_rx_qp;
 234         u32 num_tx_qp;
 235         u32 base_queue;
 236         u32 num_msix_vectors;
 237         u32 num_msix_vectors_vf;
 238         u32 led_pin_num;
 239         u32 sdp_pin_num;
 240         u32 mdio_port_num;
 241         u32 mdio_port_mode;
 242         u8 rx_buf_chain_len;
 243         u32 enabled_tcmap;
 244         u32 maxtc;
 245         u64 wr_csr_prot;
 246 };
 247
 248 struct i40e_mac_info {
 249         enum i40e_mac_type type;
 250         u8 addr[ETH_ALEN];
 251         u8 perm_addr[ETH_ALEN];
 252         u8 san_addr[ETH_ALEN];
 253         u16 max_fcoeq;
 254 };
 255
 256 enum i40e_aq_resources_ids {
 257         I40E_NVM_RESOURCE_ID = 1
 258 };
 259
 260 enum i40e_aq_resource_access_type {
 261         I40E_RESOURCE_READ = 1,
 262         I40E_RESOURCE_WRITE
 263 };
 264
 265 struct i40e_nvm_info {
 266         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 267         u32 timeout;              /* [ms] */
 268         u16 sr_size;              /* Shadow RAM size in words */
 269         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 270         u16 version;              /* NVM package version */
 271         u32 eetrack;              /* NVM data version */
 272 };
 273
 274 /* definitions used in NVM update support */
 275
 276 enum i40e_nvmupd_cmd {
 277         I40E_NVMUPD_INVALID,
 278         I40E_NVMUPD_READ_CON,
 279         I40E_NVMUPD_READ_SNT,
 280         I40E_NVMUPD_READ_LCB,
 281         I40E_NVMUPD_READ_SA,
 282         I40E_NVMUPD_WRITE_ERA,
 283         I40E_NVMUPD_WRITE_CON,
 284         I40E_NVMUPD_WRITE_SNT,
 285         I40E_NVMUPD_WRITE_LCB,
 286         I40E_NVMUPD_WRITE_SA,
 287         I40E_NVMUPD_CSUM_CON,
 288         I40E_NVMUPD_CSUM_SA,
 289         I40E_NVMUPD_CSUM_LCB,
 290 };
 291
 292 enum i40e_nvmupd_state {
 293         I40E_NVMUPD_STATE_INIT,
 294         I40E_NVMUPD_STATE_READING,
 295         I40E_NVMUPD_STATE_WRITING
 296 };
 297
 298 /* nvm_access definition and its masks/shifts need to be accessible to
 299  * application, core driver, and shared code.  Where is the right file?
 300  */
 301 #define I40E_NVM_READ   0xB
 302 #define I40E_NVM_WRITE  0xC
 303
 304 #define I40E_NVM_MOD_PNT_MASK 0xFF
 305
 306 #define I40E_NVM_TRANS_SHIFT    8
 307 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 308 #define I40E_NVM_CON            0x0
 309 #define I40E_NVM_SNT            0x1
 310 #define I40E_NVM_LCB            0x2
 311 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 312 #define I40E_NVM_ERA            0x4
 313 #define I40E_NVM_CSUM           0x8
 314
 315 #define I40E_NVM_ADAPT_SHIFT    16
 316 #define I40E_NVM_ADAPT_MASK     (0xffff << I40E_NVM_ADAPT_SHIFT)
 317
 318 #define I40E_NVMUPD_MAX_DATA    4096
 319 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 320
 321 struct i40e_nvm_access {
 322         u32 command;
 323         u32 config;
 324         u32 offset;     /* in bytes */
 325         u32 data_size;  /* in bytes */
 326         u8 data[1];
 327 };
 328
 329 /* PCI bus types */
 330 enum i40e_bus_type {
 331         i40e_bus_type_unknown = 0,
 332         i40e_bus_type_pci,
 333         i40e_bus_type_pcix,
 334         i40e_bus_type_pci_express,
 335         i40e_bus_type_reserved
 336 };
 337
 338 /* PCI bus speeds */
 339 enum i40e_bus_speed {
 340         i40e_bus_speed_unknown  = 0,
 341         i40e_bus_speed_33       = 33,
 342         i40e_bus_speed_66       = 66,
 343         i40e_bus_speed_100      = 100,
 344         i40e_bus_speed_120      = 120,
 345         i40e_bus_speed_133      = 133,
 346         i40e_bus_speed_2500     = 2500,
 347         i40e_bus_speed_5000     = 5000,
 348         i40e_bus_speed_8000     = 8000,
 349         i40e_bus_speed_reserved
 350 };
 351
 352 /* PCI bus widths */
 353 enum i40e_bus_width {
 354         i40e_bus_width_unknown  = 0,
 355         i40e_bus_width_pcie_x1  = 1,
 356         i40e_bus_width_pcie_x2  = 2,
 357         i40e_bus_width_pcie_x4  = 4,
 358         i40e_bus_width_pcie_x8  = 8,
 359         i40e_bus_width_32       = 32,
 360         i40e_bus_width_64       = 64,
 361         i40e_bus_width_reserved
 362 };
 363
 364 /* Bus parameters */
 365 struct i40e_bus_info {
 366         enum i40e_bus_speed speed;
 367         enum i40e_bus_width width;
 368         enum i40e_bus_type type;
 369
 370         u16 func;
 371         u16 device;
 372         u16 lan_id;
 373 };
 374
 375 /* Flow control (FC) parameters */
 376 struct i40e_fc_info {
 377         enum i40e_fc_mode current_mode; /* FC mode in effect */
 378         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 379 };
 380
 381 #define I40E_MAX_TRAFFIC_CLASS          8
 382 #define I40E_MAX_USER_PRIORITY          8
 383 #define I40E_DCBX_MAX_APPS              32
 384 #define I40E_LLDPDU_SIZE                1500
 385
 386 /* IEEE 802.1Qaz ETS Configuration data */
 387 struct i40e_ieee_ets_config {
 388         u8 willing;
 389         u8 cbs;
 390         u8 maxtcs;
 391         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 392         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 393         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 394 };
 395
 396 /* IEEE 802.1Qaz ETS Recommendation data */
 397 struct i40e_ieee_ets_recommend {
 398         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 399         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 400         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 401 };
 402
 403 /* IEEE 802.1Qaz PFC Configuration data */
 404 struct i40e_ieee_pfc_config {
 405         u8 willing;
 406         u8 mbc;
 407         u8 pfccap;
 408         u8 pfcenable;
 409 };
 410
 411 /* IEEE 802.1Qaz Application Priority data */
 412 struct i40e_ieee_app_priority_table {
 413         u8  priority;
 414         u8  selector;
 415         u16 protocolid;
 416 };
 417
 418 struct i40e_dcbx_config {
 419         u32 numapps;
 420         struct i40e_ieee_ets_config etscfg;
 421         struct i40e_ieee_ets_recommend etsrec;
 422         struct i40e_ieee_pfc_config pfc;
 423         struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
 424 };
 425
 426 /* Port hardware description */
 427 struct i40e_hw {
 428         u8 __iomem *hw_addr;
 429         void *back;
 430
 431         /* subsystem structs */
 432         struct i40e_phy_info phy;
 433         struct i40e_mac_info mac;
 434         struct i40e_bus_info bus;
 435         struct i40e_nvm_info nvm;
 436         struct i40e_fc_info fc;
 437
 438         /* pci info */
 439         u16 device_id;
 440         u16 vendor_id;
 441         u16 subsystem_device_id;
 442         u16 subsystem_vendor_id;
 443         u8 revision_id;
 444         u8 port;
 445         bool adapter_stopped;
 446
 447         /* capabilities for entire device and PCI func */
 448         struct i40e_hw_capabilities dev_caps;
 449         struct i40e_hw_capabilities func_caps;
 450
 451         /* Flow Director shared filter space */
 452         u16 fdir_shared_filter_count;
 453
 454         /* device profile info */
 455         u8  pf_id;
 456         u16 main_vsi_seid;
 457
 458         /* for multi-function MACs */
 459         u16 partition_id;
 460         u16 num_partitions;
 461         u16 num_ports;
 462
 463         /* Closest numa node to the device */
 464         u16 numa_node;
 465
 466         /* Admin Queue info */
 467         struct i40e_adminq_info aq;
 468
 469         /* state of nvm update process */
 470         enum i40e_nvmupd_state nvmupd_state;
 471
 472         /* HMC info */
 473         struct i40e_hmc_info hmc; /* HMC info struct */
 474
 475         /* LLDP/DCBX Status */
 476         u16 dcbx_status;
 477
 478         /* DCBX info */
 479         struct i40e_dcbx_config local_dcbx_config;
 480         struct i40e_dcbx_config remote_dcbx_config;
 481
 482         /* debug mask */
 483         u32 debug_mask;
 484 };
 485
 486 static inline bool i40e_is_vf(struct i40e_hw *hw)
 487 {
 488         return hw->mac.type == I40E_MAC_VF;
 489 }
 490
 491 struct i40e_driver_version {
 492         u8 major_version;
 493         u8 minor_version;
 494         u8 build_version;
 495         u8 subbuild_version;
 496         u8 driver_string[32];
 497 };
 498
 499 /* RX Descriptors */
 500 union i40e_16byte_rx_desc {
 501         struct {
 502                 __le64 pkt_addr; /* Packet buffer address */
 503                 __le64 hdr_addr; /* Header buffer address */
 504         } read;
 505         struct {
 506                 struct {
 507                         struct {
 508                                 union {
 509                                         __le16 mirroring_status;
 510                                         __le16 fcoe_ctx_id;
 511                                 } mirr_fcoe;
 512                                 __le16 l2tag1;
 513                         } lo_dword;
 514                         union {
 515                                 __le32 rss; /* RSS Hash */
 516                                 __le32 fd_id; /* Flow director filter id */
 517                                 __le32 fcoe_param; /* FCoE DDP Context id */
 518                         } hi_dword;
 519                 } qword0;
 520                 struct {
 521                         /* ext status/error/pktype/length */
 522                         __le64 status_error_len;
 523                 } qword1;
 524         } wb;  /* writeback */
 525 };
 526
 527 union i40e_32byte_rx_desc {
 528         struct {
 529                 __le64  pkt_addr; /* Packet buffer address */
 530                 __le64  hdr_addr; /* Header buffer address */
 531                         /* bit 0 of hdr_buffer_addr is DD bit */
 532                 __le64  rsvd1;
 533                 __le64  rsvd2;
 534         } read;
 535         struct {
 536                 struct {
 537                         struct {
 538                                 union {
 539                                         __le16 mirroring_status;
 540                                         __le16 fcoe_ctx_id;
 541                                 } mirr_fcoe;
 542                                 __le16 l2tag1;
 543                         } lo_dword;
 544                         union {
 545                                 __le32 rss; /* RSS Hash */
 546                                 __le32 fcoe_param; /* FCoE DDP Context id */
 547                                 /* Flow director filter id in case of
 548                                  * Programming status desc WB
 549                                  */
 550                                 __le32 fd_id;
 551                         } hi_dword;
 552                 } qword0;
 553                 struct {
 554                         /* status/error/pktype/length */
 555                         __le64 status_error_len;
 556                 } qword1;
 557                 struct {
 558                         __le16 ext_status; /* extended status */
 559                         __le16 rsvd;
 560                         __le16 l2tag2_1;
 561                         __le16 l2tag2_2;
 562                 } qword2;
 563                 struct {
 564                         union {
 565                                 __le32 flex_bytes_lo;
 566                                 __le32 pe_status;
 567                         } lo_dword;
 568                         union {
 569                                 __le32 flex_bytes_hi;
 570                                 __le32 fd_id;
 571                         } hi_dword;
 572                 } qword3;
 573         } wb;  /* writeback */
 574 };
 575
 576 enum i40e_rx_desc_status_bits {
 577         /* Note: These are predefined bit offsets */
 578         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 579         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 580         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 581         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 582         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 583         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 584         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 585         I40E_RX_DESC_STATUS_PIF_SHIFT           = 8,
 586         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 587         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 588         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 589         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 590         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 591         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 592         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 593         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 594 };
 595
 596 #define I40E_RXD_QW1_STATUS_SHIFT       0
 597 #define I40E_RXD_QW1_STATUS_MASK        (((1 << I40E_RX_DESC_STATUS_LAST) - 1) \
 598                                          << I40E_RXD_QW1_STATUS_SHIFT)
 599
 600 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 601 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 602                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 603
 604 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 605 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK      (0x1UL << \
 606                                          I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 607
 608 enum i40e_rx_desc_fltstat_values {
 609         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 610         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 611         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 612         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 613 };
 614
 615 #define I40E_RXD_QW1_ERROR_SHIFT        19
 616 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 617
 618 enum i40e_rx_desc_error_bits {
 619         /* Note: These are predefined bit offsets */
 620         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 621         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 622         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 623         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 624         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 625         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 626         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 627         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 628         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 629 };
 630
 631 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 632         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 633         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 634         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 635         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 636         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 637 };
 638
 639 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 640 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 641
 642 /* Packet type non-ip values */
 643 enum i40e_rx_l2_ptype {
 644         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 645         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 646         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 647         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 648         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 649         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 650         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 651         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 652         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 653         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 654         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 655         I40E_RX_PTYPE_L2_ARP                            = 11,
 656         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 657         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 658         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 659         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 660         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 661         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 662         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 663         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 664         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 665         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 666         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 667         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 668         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 669         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 670 };
 671
 672 struct i40e_rx_ptype_decoded {
 673         u32 ptype:8;
 674         u32 known:1;
 675         u32 outer_ip:1;
 676         u32 outer_ip_ver:1;
 677         u32 outer_frag:1;
 678         u32 tunnel_type:3;
 679         u32 tunnel_end_prot:2;
 680         u32 tunnel_end_frag:1;
 681         u32 inner_prot:4;
 682         u32 payload_layer:3;
 683 };
 684
 685 enum i40e_rx_ptype_outer_ip {
 686         I40E_RX_PTYPE_OUTER_L2  = 0,
 687         I40E_RX_PTYPE_OUTER_IP  = 1
 688 };
 689
 690 enum i40e_rx_ptype_outer_ip_ver {
 691         I40E_RX_PTYPE_OUTER_NONE        = 0,
 692         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 693         I40E_RX_PTYPE_OUTER_IPV6        = 1
 694 };
 695
 696 enum i40e_rx_ptype_outer_fragmented {
 697         I40E_RX_PTYPE_NOT_FRAG  = 0,
 698         I40E_RX_PTYPE_FRAG      = 1
 699 };
 700
 701 enum i40e_rx_ptype_tunnel_type {
 702         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 703         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 704         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 705         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 706         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 707 };
 708
 709 enum i40e_rx_ptype_tunnel_end_prot {
 710         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 711         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 712         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 713 };
 714
 715 enum i40e_rx_ptype_inner_prot {
 716         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 717         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 718         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 719         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 720         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 721         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 722 };
 723
 724 enum i40e_rx_ptype_payload_layer {
 725         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 726         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 727         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 728         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 729 };
 730
 731 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 732 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 733                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 734
 735 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 736 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 737                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 738
 739 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 740 #define I40E_RXD_QW1_LENGTH_SPH_MASK    (0x1ULL << \
 741                                          I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 742
 743 enum i40e_rx_desc_ext_status_bits {
 744         /* Note: These are predefined bit offsets */
 745         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 746         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 747         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 748         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 749         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 750         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 751         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 752 };
 753
 754 enum i40e_rx_desc_pe_status_bits {
 755         /* Note: These are predefined bit offsets */
 756         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 757         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 758         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 759         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 760         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 761         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 762         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 763         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 764         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 765 };
 766
 767 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 768 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 769
 770 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 771 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 772                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 773
 774 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 775 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 776                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 777
 778 enum i40e_rx_prog_status_desc_status_bits {
 779         /* Note: These are predefined bit offsets */
 780         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 781         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 782 };
 783
 784 enum i40e_rx_prog_status_desc_prog_id_masks {
 785         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 786         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 787         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 788 };
 789
 790 enum i40e_rx_prog_status_desc_error_bits {
 791         /* Note: These are predefined bit offsets */
 792         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 793         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 794         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 795         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 796 };
 797
 798 /* TX Descriptor */
 799 struct i40e_tx_desc {
 800         __le64 buffer_addr; /* Address of descriptor's data buf */
 801         __le64 cmd_type_offset_bsz;
 802 };
 803
 804 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 805 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 806
 807 enum i40e_tx_desc_dtype_value {
 808         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 809         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 810         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 811         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 812         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 813         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 814         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 815         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 816         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 817         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 818 };
 819
 820 #define I40E_TXD_QW1_CMD_SHIFT  4
 821 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 822
 823 enum i40e_tx_desc_cmd_bits {
 824         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 825         I40E_TX_DESC_CMD_RS                     = 0x0002,
 826         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 827         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 828         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 829         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 830         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 831         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 832         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 833         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 834         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 835         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 836         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 837         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 838         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 839         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 840         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 841         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 842 };
 843
 844 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 845 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 846                                          I40E_TXD_QW1_OFFSET_SHIFT)
 847
 848 enum i40e_tx_desc_length_fields {
 849         /* Note: These are predefined bit offsets */
 850         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 851         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 852         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 853 };
 854
 855 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 856 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 857                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 858
 859 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 860 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 861
 862 /* Context descriptors */
 863 struct i40e_tx_context_desc {
 864         __le32 tunneling_params;
 865         __le16 l2tag2;
 866         __le16 rsvd;
 867         __le64 type_cmd_tso_mss;
 868 };
 869
 870 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 871 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 872
 873 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 874 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 875
 876 enum i40e_tx_ctx_desc_cmd_bits {
 877         I40E_TX_CTX_DESC_TSO            = 0x01,
 878         I40E_TX_CTX_DESC_TSYN           = 0x02,
 879         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 880         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 881         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 882         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 883         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 884         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 885         I40E_TX_CTX_DESC_SWPE           = 0x40
 886 };
 887
 888 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 889 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 890                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 891
 892 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 893 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 894                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 895
 896 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 897 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 898
 899 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 900 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 901                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 902
 903 enum i40e_tx_ctx_desc_eipt_offload {
 904         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 905         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 906         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 907         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 908 };
 909
 910 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 911 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 912                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
 913
 914 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
 915 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 916
 917 #define I40E_TXD_CTX_UDP_TUNNELING      (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 918 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 919
 920 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
 921 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
 922                                          I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 923
 924 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
 925
 926 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
 927 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
 928                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
 929
 930 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
 931 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
 932                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 933
 934 struct i40e_filter_program_desc {
 935         __le32 qindex_flex_ptype_vsi;
 936         __le32 rsvd;
 937         __le32 dtype_cmd_cntindex;
 938         __le32 fd_id;
 939 };
 940 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
 941 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
 942                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
 943 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
 944 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
 945                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
 946 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
 947 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
 948                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
 949
 950 /* Packet Classifier Types for filters */
 951 enum i40e_filter_pctype {
 952         /* Note: Values 0-30 are reserved for future use */
 953         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
 954         /* Note: Value 32 is reserved for future use */
 955         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
 956         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
 957         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
 958         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
 959         /* Note: Values 37-40 are reserved for future use */
 960         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
 961         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
 962         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
 963         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
 964         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
 965         /* Note: Value 47 is reserved for future use */
 966         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
 967         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
 968         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
 969         /* Note: Values 51-62 are reserved for future use */
 970         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
 971 };
 972
 973 enum i40e_filter_program_desc_dest {
 974         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
 975         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
 976         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
 977 };
 978
 979 enum i40e_filter_program_desc_fd_status {
 980         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
 981         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
 982         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
 983         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
 984 };
 985
 986 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
 987 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
 988                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
 989
 990 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
 991 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
 992                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
 993
 994 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 995 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
 996
 997 enum i40e_filter_program_desc_pcmd {
 998         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
 999         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1000 };
1001
1002 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1003 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1004
1005 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1006 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  (0x1ULL << \
1007                                          I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1008
1009 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1010                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1011 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1012                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1013
1014 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1015 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1016                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1017
1018 enum i40e_filter_type {
1019         I40E_FLOW_DIRECTOR_FLTR = 0,
1020         I40E_PE_QUAD_HASH_FLTR = 1,
1021         I40E_ETHERTYPE_FLTR,
1022         I40E_FCOE_CTX_FLTR,
1023         I40E_MAC_VLAN_FLTR,
1024         I40E_HASH_FLTR
1025 };
1026
1027 struct i40e_vsi_context {
1028         u16 seid;
1029         u16 uplink_seid;
1030         u16 vsi_number;
1031         u16 vsis_allocated;
1032         u16 vsis_unallocated;
1033         u16 flags;
1034         u8 pf_num;
1035         u8 vf_num;
1036         u8 connection_type;
1037         struct i40e_aqc_vsi_properties_data info;
1038 };
1039
1040 struct i40e_veb_context {
1041         u16 seid;
1042         u16 uplink_seid;
1043         u16 veb_number;
1044         u16 vebs_allocated;
1045         u16 vebs_unallocated;
1046         u16 flags;
1047         struct i40e_aqc_get_veb_parameters_completion info;
1048 };
1049
1050 /* Statistics collected by each port, VSI, VEB, and S-channel */
1051 struct i40e_eth_stats {
1052         u64 rx_bytes;                   /* gorc */
1053         u64 rx_unicast;                 /* uprc */
1054         u64 rx_multicast;               /* mprc */
1055         u64 rx_broadcast;               /* bprc */
1056         u64 rx_discards;                /* rdpc */
1057         u64 rx_unknown_protocol;        /* rupp */
1058         u64 tx_bytes;                   /* gotc */
1059         u64 tx_unicast;                 /* uptc */
1060         u64 tx_multicast;               /* mptc */
1061         u64 tx_broadcast;               /* bptc */
1062         u64 tx_discards;                /* tdpc */
1063         u64 tx_errors;                  /* tepc */
1064 };
1065
1066 /* Statistics collected by the MAC */
1067 struct i40e_hw_port_stats {
1068         /* eth stats collected by the port */
1069         struct i40e_eth_stats eth;
1070
1071         /* additional port specific stats */
1072         u64 tx_dropped_link_down;       /* tdold */
1073         u64 crc_errors;                 /* crcerrs */
1074         u64 illegal_bytes;              /* illerrc */
1075         u64 error_bytes;                /* errbc */
1076         u64 mac_local_faults;           /* mlfc */
1077         u64 mac_remote_faults;          /* mrfc */
1078         u64 rx_length_errors;           /* rlec */
1079         u64 link_xon_rx;                /* lxonrxc */
1080         u64 link_xoff_rx;               /* lxoffrxc */
1081         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1082         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1083         u64 link_xon_tx;                /* lxontxc */
1084         u64 link_xoff_tx;               /* lxofftxc */
1085         u64 priority_xon_tx[8];         /* pxontxc[8] */
1086         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1087         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1088         u64 rx_size_64;                 /* prc64 */
1089         u64 rx_size_127;                /* prc127 */
1090         u64 rx_size_255;                /* prc255 */
1091         u64 rx_size_511;                /* prc511 */
1092         u64 rx_size_1023;               /* prc1023 */
1093         u64 rx_size_1522;               /* prc1522 */
1094         u64 rx_size_big;                /* prc9522 */
1095         u64 rx_undersize;               /* ruc */
1096         u64 rx_fragments;               /* rfc */
1097         u64 rx_oversize;                /* roc */
1098         u64 rx_jabber;                  /* rjc */
1099         u64 tx_size_64;                 /* ptc64 */
1100         u64 tx_size_127;                /* ptc127 */
1101         u64 tx_size_255;                /* ptc255 */
1102         u64 tx_size_511;                /* ptc511 */
1103         u64 tx_size_1023;               /* ptc1023 */
1104         u64 tx_size_1522;               /* ptc1522 */
1105         u64 tx_size_big;                /* ptc9522 */
1106         u64 mac_short_packet_dropped;   /* mspdc */
1107         u64 checksum_error;             /* xec */
1108         /* flow director stats */
1109         u64 fd_atr_match;
1110         u64 fd_sb_match;
1111         /* EEE LPI */
1112         u32 tx_lpi_status;
1113         u32 rx_lpi_status;
1114         u64 tx_lpi_count;               /* etlpic */
1115         u64 rx_lpi_count;               /* erlpic */
1116 };
1117
1118 /* Checksum and Shadow RAM pointers */
1119 #define I40E_SR_NVM_CONTROL_WORD                0x00
1120 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1121 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1122 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1123 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1124 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1125 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1126 #define I40E_SR_VPD_PTR                         0x2F
1127 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1128 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1129
1130 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1131 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1132 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1133 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1134 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1135
1136 /* Shadow RAM related */
1137 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1138 #define I40E_SR_WORDS_IN_1KB            512
1139 /* Checksum should be calculated such that after adding all the words,
1140  * including the checksum word itself, the sum should be 0xBABA.
1141  */
1142 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1143
1144 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1145
1146 enum i40e_switch_element_types {
1147         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1148         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1149         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1150         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1151         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1152         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1153         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1154         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1155         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1156 };
1157
1158 /* Supported EtherType filters */
1159 enum i40e_ether_type_index {
1160         I40E_ETHER_TYPE_1588            = 0,
1161         I40E_ETHER_TYPE_FIP             = 1,
1162         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1163         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1164         I40E_ETHER_TYPE_LLDP            = 4,
1165         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1166         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1167         I40E_ETHER_TYPE_QCN_CNM         = 7,
1168         I40E_ETHER_TYPE_8021X           = 8,
1169         I40E_ETHER_TYPE_ARP             = 9,
1170         I40E_ETHER_TYPE_RSV1            = 10,
1171         I40E_ETHER_TYPE_RSV2            = 11,
1172 };
1173
1174 /* Filter context base size is 1K */
1175 #define I40E_HASH_FILTER_BASE_SIZE      1024
1176 /* Supported Hash filter values */
1177 enum i40e_hash_filter_size {
1178         I40E_HASH_FILTER_SIZE_1K        = 0,
1179         I40E_HASH_FILTER_SIZE_2K        = 1,
1180         I40E_HASH_FILTER_SIZE_4K        = 2,
1181         I40E_HASH_FILTER_SIZE_8K        = 3,
1182         I40E_HASH_FILTER_SIZE_16K       = 4,
1183         I40E_HASH_FILTER_SIZE_32K       = 5,
1184         I40E_HASH_FILTER_SIZE_64K       = 6,
1185         I40E_HASH_FILTER_SIZE_128K      = 7,
1186         I40E_HASH_FILTER_SIZE_256K      = 8,
1187         I40E_HASH_FILTER_SIZE_512K      = 9,
1188         I40E_HASH_FILTER_SIZE_1M        = 10,
1189 };
1190
1191 /* DMA context base size is 0.5K */
1192 #define I40E_DMA_CNTX_BASE_SIZE         512
1193 /* Supported DMA context values */
1194 enum i40e_dma_cntx_size {
1195         I40E_DMA_CNTX_SIZE_512          = 0,
1196         I40E_DMA_CNTX_SIZE_1K           = 1,
1197         I40E_DMA_CNTX_SIZE_2K           = 2,
1198         I40E_DMA_CNTX_SIZE_4K           = 3,
1199         I40E_DMA_CNTX_SIZE_8K           = 4,
1200         I40E_DMA_CNTX_SIZE_16K          = 5,
1201         I40E_DMA_CNTX_SIZE_32K          = 6,
1202         I40E_DMA_CNTX_SIZE_64K          = 7,
1203         I40E_DMA_CNTX_SIZE_128K         = 8,
1204         I40E_DMA_CNTX_SIZE_256K         = 9,
1205 };
1206
1207 /* Supported Hash look up table (LUT) sizes */
1208 enum i40e_hash_lut_size {
1209         I40E_HASH_LUT_SIZE_128          = 0,
1210         I40E_HASH_LUT_SIZE_512          = 1,
1211 };
1212
1213 /* Structure to hold a per PF filter control settings */
1214 struct i40e_filter_control_settings {
1215         /* number of PE Quad Hash filter buckets */
1216         enum i40e_hash_filter_size pe_filt_num;
1217         /* number of PE Quad Hash contexts */
1218         enum i40e_dma_cntx_size pe_cntx_num;
1219         /* number of FCoE filter buckets */
1220         enum i40e_hash_filter_size fcoe_filt_num;
1221         /* number of FCoE DDP contexts */
1222         enum i40e_dma_cntx_size fcoe_cntx_num;
1223         /* size of the Hash LUT */
1224         enum i40e_hash_lut_size hash_lut_size;
1225         /* enable FDIR filters for PF and its VFs */
1226         bool enable_fdir;
1227         /* enable Ethertype filters for PF and its VFs */
1228         bool enable_ethtype;
1229         /* enable MAC/VLAN filters for PF and its VFs */
1230         bool enable_macvlan;
1231 };
1232
1233 /* Structure to hold device level control filter counts */
1234 struct i40e_control_filter_stats {
1235         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1236         u16 etype_used;       /* Used perfect EtherType filters */
1237         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1238         u16 etype_free;       /* Un-used perfect EtherType filters */
1239 };
1240
1241 enum i40e_reset_type {
1242         I40E_RESET_POR          = 0,
1243         I40E_RESET_CORER        = 1,
1244         I40E_RESET_GLOBR        = 2,
1245         I40E_RESET_EMPR         = 3,
1246 };
1247
1248 /* RSS Hash Table Size */
1249 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1250 #endif /* _I40E_TYPE_H_ */