kernel/drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29
  30 #include "i40evf.h"
  31 #include "i40e_prototype.h"
  32
  33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  34                                 u32 td_tag)
  35 {
  36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  41 }
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 /**
  46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  47  * @ring:      the ring that owns the buffer
  48  * @tx_buffer: the buffer to free
  49  **/
  50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  51                                             struct i40e_tx_buffer *tx_buffer)
  52 {
  53         if (tx_buffer->skb) {
  54                 dev_kfree_skb_any(tx_buffer->skb);
  55                 if (dma_unmap_len(tx_buffer, len))
  56                         dma_unmap_single(ring->dev,
  57                                          dma_unmap_addr(tx_buffer, dma),
  58                                          dma_unmap_len(tx_buffer, len),
  59                                          DMA_TO_DEVICE);
  60         } else if (dma_unmap_len(tx_buffer, len)) {
  61                 dma_unmap_page(ring->dev,
  62                                dma_unmap_addr(tx_buffer, dma),
  63                                dma_unmap_len(tx_buffer, len),
  64                                DMA_TO_DEVICE);
  65         }
  66
  67         if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
  68                 kfree(tx_buffer->raw_buf);
  69
  70         tx_buffer->next_to_watch = NULL;
  71         tx_buffer->skb = NULL;
  72         dma_unmap_len_set(tx_buffer, len, 0);
  73         /* tx_buffer must be completely set up in the transmit path */
  74 }
  75
  76 /**
  77  * i40evf_clean_tx_ring - Free any empty Tx buffers
  78  * @tx_ring: ring to be cleaned
  79  **/
  80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  81 {
  82         unsigned long bi_size;
  83         u16 i;
  84
  85         /* ring already cleared, nothing to do */
  86         if (!tx_ring->tx_bi)
  87                 return;
  88
  89         /* Free all the Tx ring sk_buffs */
  90         for (i = 0; i < tx_ring->count; i++)
  91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  92
  93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  94         memset(tx_ring->tx_bi, 0, bi_size);
  95
  96         /* Zero out the descriptor ring */
  97         memset(tx_ring->desc, 0, tx_ring->size);
  98
  99         tx_ring->next_to_use = 0;
 100         tx_ring->next_to_clean = 0;
 101
 102         if (!tx_ring->netdev)
 103                 return;
 104
 105         /* cleanup Tx queue statistics */
 106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 107                                                   tx_ring->queue_index));
 108 }
 109
 110 /**
 111  * i40evf_free_tx_resources - Free Tx resources per queue
 112  * @tx_ring: Tx descriptor ring for a specific queue
 113  *
 114  * Free all transmit software resources
 115  **/
 116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 117 {
 118         i40evf_clean_tx_ring(tx_ring);
 119         kfree(tx_ring->tx_bi);
 120         tx_ring->tx_bi = NULL;
 121
 122         if (tx_ring->desc) {
 123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 124                                   tx_ring->desc, tx_ring->dma);
 125                 tx_ring->desc = NULL;
 126         }
 127 }
 128
 129 /**
 130  * i40e_get_head - Retrieve head from head writeback
 131  * @tx_ring:  tx ring to fetch head of
 132  *
 133  * Returns value of Tx ring head based on value stored
 134  * in head write-back location
 135  **/
 136 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
 137 {
 138         void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
 139
 140         return le32_to_cpu(*(volatile __le32 *)head);
 141 }
 142
 143 #define WB_STRIDE 0x3
 144
 145 /**
 146  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 147  * @tx_ring:  tx ring to clean
 148  * @budget:   how many cleans we're allowed
 149  *
 150  * Returns true if there's any budget left (e.g. the clean is finished)
 151  **/
 152 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 153 {
 154         u16 i = tx_ring->next_to_clean;
 155         struct i40e_tx_buffer *tx_buf;
 156         struct i40e_tx_desc *tx_head;
 157         struct i40e_tx_desc *tx_desc;
 158         unsigned int total_packets = 0;
 159         unsigned int total_bytes = 0;
 160
 161         tx_buf = &tx_ring->tx_bi[i];
 162         tx_desc = I40E_TX_DESC(tx_ring, i);
 163         i -= tx_ring->count;
 164
 165         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 166
 167         do {
 168                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 169
 170                 /* if next_to_watch is not set then there is no work pending */
 171                 if (!eop_desc)
 172                         break;
 173
 174                 /* prevent any other reads prior to eop_desc */
 175                 read_barrier_depends();
 176
 177                 /* we have caught up to head, no work left to do */
 178                 if (tx_head == tx_desc)
 179                         break;
 180
 181                 /* clear next_to_watch to prevent false hangs */
 182                 tx_buf->next_to_watch = NULL;
 183
 184                 /* update the statistics for this packet */
 185                 total_bytes += tx_buf->bytecount;
 186                 total_packets += tx_buf->gso_segs;
 187
 188                 /* free the skb */
 189                 dev_kfree_skb_any(tx_buf->skb);
 190
 191                 /* unmap skb header data */
 192                 dma_unmap_single(tx_ring->dev,
 193                                  dma_unmap_addr(tx_buf, dma),
 194                                  dma_unmap_len(tx_buf, len),
 195                                  DMA_TO_DEVICE);
 196
 197                 /* clear tx_buffer data */
 198                 tx_buf->skb = NULL;
 199                 dma_unmap_len_set(tx_buf, len, 0);
 200
 201                 /* unmap remaining buffers */
 202                 while (tx_desc != eop_desc) {
 203
 204                         tx_buf++;
 205                         tx_desc++;
 206                         i++;
 207                         if (unlikely(!i)) {
 208                                 i -= tx_ring->count;
 209                                 tx_buf = tx_ring->tx_bi;
 210                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 211                         }
 212
 213                         /* unmap any remaining paged data */
 214                         if (dma_unmap_len(tx_buf, len)) {
 215                                 dma_unmap_page(tx_ring->dev,
 216                                                dma_unmap_addr(tx_buf, dma),
 217                                                dma_unmap_len(tx_buf, len),
 218                                                DMA_TO_DEVICE);
 219                                 dma_unmap_len_set(tx_buf, len, 0);
 220                         }
 221                 }
 222
 223                 /* move us one more past the eop_desc for start of next pkt */
 224                 tx_buf++;
 225                 tx_desc++;
 226                 i++;
 227                 if (unlikely(!i)) {
 228                         i -= tx_ring->count;
 229                         tx_buf = tx_ring->tx_bi;
 230                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 231                 }
 232
 233                 prefetch(tx_desc);
 234
 235                 /* update budget accounting */
 236                 budget--;
 237         } while (likely(budget));
 238
 239         i += tx_ring->count;
 240         tx_ring->next_to_clean = i;
 241         u64_stats_update_begin(&tx_ring->syncp);
 242         tx_ring->stats.bytes += total_bytes;
 243         tx_ring->stats.packets += total_packets;
 244         u64_stats_update_end(&tx_ring->syncp);
 245         tx_ring->q_vector->tx.total_bytes += total_bytes;
 246         tx_ring->q_vector->tx.total_packets += total_packets;
 247
 248         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 249                                                       tx_ring->queue_index),
 250                                   total_packets, total_bytes);
 251
 252 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 253         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 254                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 255                 /* Make sure that anybody stopping the queue after this
 256                  * sees the new next_to_clean.
 257                  */
 258                 smp_mb();
 259                 if (__netif_subqueue_stopped(tx_ring->netdev,
 260                                              tx_ring->queue_index) &&
 261                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 262                         netif_wake_subqueue(tx_ring->netdev,
 263                                             tx_ring->queue_index);
 264                         ++tx_ring->tx_stats.restart_queue;
 265                 }
 266         }
 267
 268         return !!budget;
 269 }
 270
 271 /**
 272  * i40evf_force_wb -Arm hardware to do a wb on noncache aligned descriptors
 273  * @vsi: the VSI we care about
 274  * @q_vector: the vector  on which to force writeback
 275  *
 276  **/
 277 static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 278 {
 279         u16 flags = q_vector->tx.ring[0].flags;
 280
 281         if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 282                 u32 val;
 283
 284                 if (q_vector->arm_wb_state)
 285                         return;
 286
 287                 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK;
 288
 289                 wr32(&vsi->back->hw,
 290                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 291                                           vsi->base_vector - 1),
 292                      val);
 293                 q_vector->arm_wb_state = true;
 294         } else {
 295                 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 296                           I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 297                           I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 298                           I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK;
 299                           /* allow 00 to be written to the index */
 300
 301                 wr32(&vsi->back->hw,
 302                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 303                                           vsi->base_vector - 1), val);
 304         }
 305 }
 306
 307 /**
 308  * i40e_set_new_dynamic_itr - Find new ITR level
 309  * @rc: structure containing ring performance data
 310  *
 311  * Returns true if ITR changed, false if not
 312  *
 313  * Stores a new ITR value based on packets and byte counts during
 314  * the last interrupt.  The advantage of per interrupt computation
 315  * is faster updates and more accurate ITR for the current traffic
 316  * pattern.  Constants in this function were computed based on
 317  * theoretical maximum wire speed and thresholds were set based on
 318  * testing data as well as attempting to minimize response time
 319  * while increasing bulk throughput.
 320  **/
 321 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 322 {
 323         enum i40e_latency_range new_latency_range = rc->latency_range;
 324         struct i40e_q_vector *qv = rc->ring->q_vector;
 325         u32 new_itr = rc->itr;
 326         int bytes_per_int;
 327         int usecs;
 328
 329         if (rc->total_packets == 0 || !rc->itr)
 330                 return false;
 331
 332         /* simple throttlerate management
 333          *   0-10MB/s   lowest (50000 ints/s)
 334          *  10-20MB/s   low    (20000 ints/s)
 335          *  20-1249MB/s bulk   (18000 ints/s)
 336          *  > 40000 Rx packets per second (8000 ints/s)
 337          *
 338          * The math works out because the divisor is in 10^(-6) which
 339          * turns the bytes/us input value into MB/s values, but
 340          * make sure to use usecs, as the register values written
 341          * are in 2 usec increments in the ITR registers, and make sure
 342          * to use the smoothed values that the countdown timer gives us.
 343          */
 344         usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
 345         bytes_per_int = rc->total_bytes / usecs;
 346
 347         switch (new_latency_range) {
 348         case I40E_LOWEST_LATENCY:
 349                 if (bytes_per_int > 10)
 350                         new_latency_range = I40E_LOW_LATENCY;
 351                 break;
 352         case I40E_LOW_LATENCY:
 353                 if (bytes_per_int > 20)
 354                         new_latency_range = I40E_BULK_LATENCY;
 355                 else if (bytes_per_int <= 10)
 356                         new_latency_range = I40E_LOWEST_LATENCY;
 357                 break;
 358         case I40E_BULK_LATENCY:
 359         case I40E_ULTRA_LATENCY:
 360         default:
 361                 if (bytes_per_int <= 20)
 362                         new_latency_range = I40E_LOW_LATENCY;
 363                 break;
 364         }
 365
 366         /* this is to adjust RX more aggressively when streaming small
 367          * packets.  The value of 40000 was picked as it is just beyond
 368          * what the hardware can receive per second if in low latency
 369          * mode.
 370          */
 371 #define RX_ULTRA_PACKET_RATE 40000
 372
 373         if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
 374             (&qv->rx == rc))
 375                 new_latency_range = I40E_ULTRA_LATENCY;
 376
 377         rc->latency_range = new_latency_range;
 378
 379         switch (new_latency_range) {
 380         case I40E_LOWEST_LATENCY:
 381                 new_itr = I40E_ITR_50K;
 382                 break;
 383         case I40E_LOW_LATENCY:
 384                 new_itr = I40E_ITR_20K;
 385                 break;
 386         case I40E_BULK_LATENCY:
 387                 new_itr = I40E_ITR_18K;
 388                 break;
 389         case I40E_ULTRA_LATENCY:
 390                 new_itr = I40E_ITR_8K;
 391                 break;
 392         default:
 393                 break;
 394         }
 395
 396         rc->total_bytes = 0;
 397         rc->total_packets = 0;
 398
 399         if (new_itr != rc->itr) {
 400                 rc->itr = new_itr;
 401                 return true;
 402         }
 403
 404         return false;
 405 }
 406
 407 /*
 408  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 409  * @tx_ring: the tx ring to set up
 410  *
 411  * Return 0 on success, negative on error
 412  **/
 413 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 414 {
 415         struct device *dev = tx_ring->dev;
 416         int bi_size;
 417
 418         if (!dev)
 419                 return -ENOMEM;
 420
 421         /* warn if we are about to overwrite the pointer */
 422         WARN_ON(tx_ring->tx_bi);
 423         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 424         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 425         if (!tx_ring->tx_bi)
 426                 goto err;
 427
 428         /* round up to nearest 4K */
 429         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 430         /* add u32 for head writeback, align after this takes care of
 431          * guaranteeing this is at least one cache line in size
 432          */
 433         tx_ring->size += sizeof(u32);
 434         tx_ring->size = ALIGN(tx_ring->size, 4096);
 435         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 436                                            &tx_ring->dma, GFP_KERNEL);
 437         if (!tx_ring->desc) {
 438                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 439                          tx_ring->size);
 440                 goto err;
 441         }
 442
 443         tx_ring->next_to_use = 0;
 444         tx_ring->next_to_clean = 0;
 445         return 0;
 446
 447 err:
 448         kfree(tx_ring->tx_bi);
 449         tx_ring->tx_bi = NULL;
 450         return -ENOMEM;
 451 }
 452
 453 /**
 454  * i40evf_clean_rx_ring - Free Rx buffers
 455  * @rx_ring: ring to be cleaned
 456  **/
 457 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 458 {
 459         struct device *dev = rx_ring->dev;
 460         struct i40e_rx_buffer *rx_bi;
 461         unsigned long bi_size;
 462         u16 i;
 463
 464         /* ring already cleared, nothing to do */
 465         if (!rx_ring->rx_bi)
 466                 return;
 467
 468         if (ring_is_ps_enabled(rx_ring)) {
 469                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 470
 471                 rx_bi = &rx_ring->rx_bi[0];
 472                 if (rx_bi->hdr_buf) {
 473                         dma_free_coherent(dev,
 474                                           bufsz,
 475                                           rx_bi->hdr_buf,
 476                                           rx_bi->dma);
 477                         for (i = 0; i < rx_ring->count; i++) {
 478                                 rx_bi = &rx_ring->rx_bi[i];
 479                                 rx_bi->dma = 0;
 480                                 rx_bi->hdr_buf = NULL;
 481                         }
 482                 }
 483         }
 484         /* Free all the Rx ring sk_buffs */
 485         for (i = 0; i < rx_ring->count; i++) {
 486                 rx_bi = &rx_ring->rx_bi[i];
 487                 if (rx_bi->dma) {
 488                         dma_unmap_single(dev,
 489                                          rx_bi->dma,
 490                                          rx_ring->rx_buf_len,
 491                                          DMA_FROM_DEVICE);
 492                         rx_bi->dma = 0;
 493                 }
 494                 if (rx_bi->skb) {
 495                         dev_kfree_skb(rx_bi->skb);
 496                         rx_bi->skb = NULL;
 497                 }
 498                 if (rx_bi->page) {
 499                         if (rx_bi->page_dma) {
 500                                 dma_unmap_page(dev,
 501                                                rx_bi->page_dma,
 502                                                PAGE_SIZE / 2,
 503                                                DMA_FROM_DEVICE);
 504                                 rx_bi->page_dma = 0;
 505                         }
 506                         __free_page(rx_bi->page);
 507                         rx_bi->page = NULL;
 508                         rx_bi->page_offset = 0;
 509                 }
 510         }
 511
 512         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 513         memset(rx_ring->rx_bi, 0, bi_size);
 514
 515         /* Zero out the descriptor ring */
 516         memset(rx_ring->desc, 0, rx_ring->size);
 517
 518         rx_ring->next_to_clean = 0;
 519         rx_ring->next_to_use = 0;
 520 }
 521
 522 /**
 523  * i40evf_free_rx_resources - Free Rx resources
 524  * @rx_ring: ring to clean the resources from
 525  *
 526  * Free all receive software resources
 527  **/
 528 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 529 {
 530         i40evf_clean_rx_ring(rx_ring);
 531         kfree(rx_ring->rx_bi);
 532         rx_ring->rx_bi = NULL;
 533
 534         if (rx_ring->desc) {
 535                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 536                                   rx_ring->desc, rx_ring->dma);
 537                 rx_ring->desc = NULL;
 538         }
 539 }
 540
 541 /**
 542  * i40evf_alloc_rx_headers - allocate rx header buffers
 543  * @rx_ring: ring to alloc buffers
 544  *
 545  * Allocate rx header buffers for the entire ring. As these are static,
 546  * this is only called when setting up a new ring.
 547  **/
 548 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
 549 {
 550         struct device *dev = rx_ring->dev;
 551         struct i40e_rx_buffer *rx_bi;
 552         dma_addr_t dma;
 553         void *buffer;
 554         int buf_size;
 555         int i;
 556
 557         if (rx_ring->rx_bi[0].hdr_buf)
 558                 return;
 559         /* Make sure the buffers don't cross cache line boundaries. */
 560         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
 561         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
 562                                     &dma, GFP_KERNEL);
 563         if (!buffer)
 564                 return;
 565         for (i = 0; i < rx_ring->count; i++) {
 566                 rx_bi = &rx_ring->rx_bi[i];
 567                 rx_bi->dma = dma + (i * buf_size);
 568                 rx_bi->hdr_buf = buffer + (i * buf_size);
 569         }
 570 }
 571
 572 /**
 573  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 574  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 575  *
 576  * Returns 0 on success, negative on failure
 577  **/
 578 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 579 {
 580         struct device *dev = rx_ring->dev;
 581         int bi_size;
 582
 583         /* warn if we are about to overwrite the pointer */
 584         WARN_ON(rx_ring->rx_bi);
 585         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 586         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 587         if (!rx_ring->rx_bi)
 588                 goto err;
 589
 590         u64_stats_init(&rx_ring->syncp);
 591
 592         /* Round up to nearest 4K */
 593         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 594                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 595                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 596         rx_ring->size = ALIGN(rx_ring->size, 4096);
 597         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 598                                            &rx_ring->dma, GFP_KERNEL);
 599
 600         if (!rx_ring->desc) {
 601                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 602                          rx_ring->size);
 603                 goto err;
 604         }
 605
 606         rx_ring->next_to_clean = 0;
 607         rx_ring->next_to_use = 0;
 608
 609         return 0;
 610 err:
 611         kfree(rx_ring->rx_bi);
 612         rx_ring->rx_bi = NULL;
 613         return -ENOMEM;
 614 }
 615
 616 /**
 617  * i40e_release_rx_desc - Store the new tail and head values
 618  * @rx_ring: ring to bump
 619  * @val: new head index
 620  **/
 621 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 622 {
 623         rx_ring->next_to_use = val;
 624         /* Force memory writes to complete before letting h/w
 625          * know there are new descriptors to fetch.  (Only
 626          * applicable for weak-ordered memory model archs,
 627          * such as IA-64).
 628          */
 629         wmb();
 630         writel(val, rx_ring->tail);
 631 }
 632
 633 /**
 634  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
 635  * @rx_ring: ring to place buffers on
 636  * @cleaned_count: number of buffers to replace
 637  **/
 638 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
 639 {
 640         u16 i = rx_ring->next_to_use;
 641         union i40e_rx_desc *rx_desc;
 642         struct i40e_rx_buffer *bi;
 643
 644         /* do nothing if no valid netdev defined */
 645         if (!rx_ring->netdev || !cleaned_count)
 646                 return;
 647
 648         while (cleaned_count--) {
 649                 rx_desc = I40E_RX_DESC(rx_ring, i);
 650                 bi = &rx_ring->rx_bi[i];
 651
 652                 if (bi->skb) /* desc is in use */
 653                         goto no_buffers;
 654                 if (!bi->page) {
 655                         bi->page = alloc_page(GFP_ATOMIC);
 656                         if (!bi->page) {
 657                                 rx_ring->rx_stats.alloc_page_failed++;
 658                                 goto no_buffers;
 659                         }
 660                 }
 661
 662                 if (!bi->page_dma) {
 663                         /* use a half page if we're re-using */
 664                         bi->page_offset ^= PAGE_SIZE / 2;
 665                         bi->page_dma = dma_map_page(rx_ring->dev,
 666                                                     bi->page,
 667                                                     bi->page_offset,
 668                                                     PAGE_SIZE / 2,
 669                                                     DMA_FROM_DEVICE);
 670                         if (dma_mapping_error(rx_ring->dev,
 671                                               bi->page_dma)) {
 672                                 rx_ring->rx_stats.alloc_page_failed++;
 673                                 bi->page_dma = 0;
 674                                 goto no_buffers;
 675                         }
 676                 }
 677
 678                 dma_sync_single_range_for_device(rx_ring->dev,
 679                                                  bi->dma,
 680                                                  0,
 681                                                  rx_ring->rx_hdr_len,
 682                                                  DMA_FROM_DEVICE);
 683                 /* Refresh the desc even if buffer_addrs didn't change
 684                  * because each write-back erases this info.
 685                  */
 686                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 687                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 688                 i++;
 689                 if (i == rx_ring->count)
 690                         i = 0;
 691         }
 692
 693 no_buffers:
 694         if (rx_ring->next_to_use != i)
 695                 i40e_release_rx_desc(rx_ring, i);
 696 }
 697
 698 /**
 699  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
 700  * @rx_ring: ring to place buffers on
 701  * @cleaned_count: number of buffers to replace
 702  **/
 703 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
 704 {
 705         u16 i = rx_ring->next_to_use;
 706         union i40e_rx_desc *rx_desc;
 707         struct i40e_rx_buffer *bi;
 708         struct sk_buff *skb;
 709
 710         /* do nothing if no valid netdev defined */
 711         if (!rx_ring->netdev || !cleaned_count)
 712                 return;
 713
 714         while (cleaned_count--) {
 715                 rx_desc = I40E_RX_DESC(rx_ring, i);
 716                 bi = &rx_ring->rx_bi[i];
 717                 skb = bi->skb;
 718
 719                 if (!skb) {
 720                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 721                                                         rx_ring->rx_buf_len);
 722                         if (!skb) {
 723                                 rx_ring->rx_stats.alloc_buff_failed++;
 724                                 goto no_buffers;
 725                         }
 726                         /* initialize queue mapping */
 727                         skb_record_rx_queue(skb, rx_ring->queue_index);
 728                         bi->skb = skb;
 729                 }
 730
 731                 if (!bi->dma) {
 732                         bi->dma = dma_map_single(rx_ring->dev,
 733                                                  skb->data,
 734                                                  rx_ring->rx_buf_len,
 735                                                  DMA_FROM_DEVICE);
 736                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 737                                 rx_ring->rx_stats.alloc_buff_failed++;
 738                                 bi->dma = 0;
 739                                 goto no_buffers;
 740                         }
 741                 }
 742
 743                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 744                 rx_desc->read.hdr_addr = 0;
 745                 i++;
 746                 if (i == rx_ring->count)
 747                         i = 0;
 748         }
 749
 750 no_buffers:
 751         if (rx_ring->next_to_use != i)
 752                 i40e_release_rx_desc(rx_ring, i);
 753 }
 754
 755 /**
 756  * i40e_receive_skb - Send a completed packet up the stack
 757  * @rx_ring:  rx ring in play
 758  * @skb: packet to send up
 759  * @vlan_tag: vlan tag for packet
 760  **/
 761 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 762                              struct sk_buff *skb, u16 vlan_tag)
 763 {
 764         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 765
 766         if (vlan_tag & VLAN_VID_MASK)
 767                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 768
 769         napi_gro_receive(&q_vector->napi, skb);
 770 }
 771
 772 /**
 773  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 774  * @vsi: the VSI we care about
 775  * @skb: skb currently being received and modified
 776  * @rx_status: status value of last descriptor in packet
 777  * @rx_error: error value of last descriptor in packet
 778  * @rx_ptype: ptype value of last descriptor in packet
 779  **/
 780 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 781                                     struct sk_buff *skb,
 782                                     u32 rx_status,
 783                                     u32 rx_error,
 784                                     u16 rx_ptype)
 785 {
 786         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 787         bool ipv4 = false, ipv6 = false;
 788         bool ipv4_tunnel, ipv6_tunnel;
 789         __wsum rx_udp_csum;
 790         struct iphdr *iph;
 791         __sum16 csum;
 792
 793         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 794                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 795         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 796                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 797
 798         skb->ip_summed = CHECKSUM_NONE;
 799
 800         /* Rx csum enabled and ip headers found? */
 801         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 802                 return;
 803
 804         /* did the hardware decode the packet and checksum? */
 805         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 806                 return;
 807
 808         /* both known and outer_ip must be set for the below code to work */
 809         if (!(decoded.known && decoded.outer_ip))
 810                 return;
 811
 812         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 813             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
 814                 ipv4 = true;
 815         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 816                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 817                 ipv6 = true;
 818
 819         if (ipv4 &&
 820             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
 821                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 822                 goto checksum_fail;
 823
 824         /* likely incorrect csum if alternate IP extension headers found */
 825         if (ipv6 &&
 826             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 827                 /* don't increment checksum err here, non-fatal err */
 828                 return;
 829
 830         /* there was some L4 error, count error and punt packet to the stack */
 831         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
 832                 goto checksum_fail;
 833
 834         /* handle packets that were not able to be checksummed due
 835          * to arrival speed, in this case the stack can compute
 836          * the csum.
 837          */
 838         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
 839                 return;
 840
 841         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 842          * it in the driver, hardware does not do it for us.
 843          * Since L3L4P bit was set we assume a valid IHL value (>=5)
 844          * so the total length of IPv4 header is IHL*4 bytes
 845          * The UDP_0 bit *may* bet set if the *inner* header is UDP
 846          */
 847         if (ipv4_tunnel) {
 848                 skb->transport_header = skb->mac_header +
 849                                         sizeof(struct ethhdr) +
 850                                         (ip_hdr(skb)->ihl * 4);
 851
 852                 /* Add 4 bytes for VLAN tagged packets */
 853                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 854                                           skb->protocol == htons(ETH_P_8021AD))
 855                                           ? VLAN_HLEN : 0;
 856
 857                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
 858                     (udp_hdr(skb)->check != 0)) {
 859                         rx_udp_csum = udp_csum(skb);
 860                         iph = ip_hdr(skb);
 861                         csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
 862                                                  (skb->len -
 863                                                   skb_transport_offset(skb)),
 864                                                  IPPROTO_UDP, rx_udp_csum);
 865
 866                         if (udp_hdr(skb)->check != csum)
 867                                 goto checksum_fail;
 868
 869                 } /* else its GRE and so no outer UDP header */
 870         }
 871
 872         skb->ip_summed = CHECKSUM_UNNECESSARY;
 873         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 874
 875         return;
 876
 877 checksum_fail:
 878         vsi->back->hw_csum_rx_error++;
 879 }
 880
 881 /**
 882  * i40e_ptype_to_htype - get a hash type
 883  * @ptype: the ptype value from the descriptor
 884  *
 885  * Returns a hash type to be used by skb_set_hash
 886  **/
 887 static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype)
 888 {
 889         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 890
 891         if (!decoded.known)
 892                 return PKT_HASH_TYPE_NONE;
 893
 894         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 895             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 896                 return PKT_HASH_TYPE_L4;
 897         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 898                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 899                 return PKT_HASH_TYPE_L3;
 900         else
 901                 return PKT_HASH_TYPE_L2;
 902 }
 903
 904 /**
 905  * i40e_rx_hash - set the hash value in the skb
 906  * @ring: descriptor ring
 907  * @rx_desc: specific descriptor
 908  **/
 909 static inline void i40e_rx_hash(struct i40e_ring *ring,
 910                                 union i40e_rx_desc *rx_desc,
 911                                 struct sk_buff *skb,
 912                                 u8 rx_ptype)
 913 {
 914         u32 hash;
 915         const __le64 rss_mask  =
 916                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 917                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 918
 919         if (ring->netdev->features & NETIF_F_RXHASH)
 920                 return;
 921
 922         if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
 923                 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 924                 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
 925         }
 926 }
 927
 928 /**
 929  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
 930  * @rx_ring:  rx ring to clean
 931  * @budget:   how many cleans we're allowed
 932  *
 933  * Returns true if there's any budget left (e.g. the clean is finished)
 934  **/
 935 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
 936 {
 937         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 938         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
 939         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
 940         const int current_node = numa_mem_id();
 941         struct i40e_vsi *vsi = rx_ring->vsi;
 942         u16 i = rx_ring->next_to_clean;
 943         union i40e_rx_desc *rx_desc;
 944         u32 rx_error, rx_status;
 945         u8 rx_ptype;
 946         u64 qword;
 947
 948         do {
 949                 struct i40e_rx_buffer *rx_bi;
 950                 struct sk_buff *skb;
 951                 u16 vlan_tag;
 952                 /* return some buffers to hardware, one at a time is too slow */
 953                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
 954                         i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
 955                         cleaned_count = 0;
 956                 }
 957
 958                 i = rx_ring->next_to_clean;
 959                 rx_desc = I40E_RX_DESC(rx_ring, i);
 960                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 961                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
 962                         I40E_RXD_QW1_STATUS_SHIFT;
 963
 964                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
 965                         break;
 966
 967                 /* This memory barrier is needed to keep us from reading
 968                  * any other fields out of the rx_desc until we know the
 969                  * DD bit is set.
 970                  */
 971                 dma_rmb();
 972                 rx_bi = &rx_ring->rx_bi[i];
 973                 skb = rx_bi->skb;
 974                 if (likely(!skb)) {
 975                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 976                                                         rx_ring->rx_hdr_len);
 977                         if (!skb) {
 978                                 rx_ring->rx_stats.alloc_buff_failed++;
 979                                 break;
 980                         }
 981
 982                         /* initialize queue mapping */
 983                         skb_record_rx_queue(skb, rx_ring->queue_index);
 984                         /* we are reusing so sync this buffer for CPU use */
 985                         dma_sync_single_range_for_cpu(rx_ring->dev,
 986                                                       rx_bi->dma,
 987                                                       0,
 988                                                       rx_ring->rx_hdr_len,
 989                                                       DMA_FROM_DEVICE);
 990                 }
 991                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 992                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 993                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
 994                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
 995                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
 996                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
 997
 998                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
 999                            I40E_RXD_QW1_ERROR_SHIFT;
1000                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1001                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1002
1003                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1004                            I40E_RXD_QW1_PTYPE_SHIFT;
1005                 prefetch(rx_bi->page);
1006                 rx_bi->skb = NULL;
1007                 cleaned_count++;
1008                 if (rx_hbo || rx_sph) {
1009                         int len;
1010
1011                         if (rx_hbo)
1012                                 len = I40E_RX_HDR_SIZE;
1013                         else
1014                                 len = rx_header_len;
1015                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1016                 } else if (skb->len == 0) {
1017                         int len;
1018
1019                         len = (rx_packet_len > skb_headlen(skb) ?
1020                                 skb_headlen(skb) : rx_packet_len);
1021                         memcpy(__skb_put(skb, len),
1022                                rx_bi->page + rx_bi->page_offset,
1023                                len);
1024                         rx_bi->page_offset += len;
1025                         rx_packet_len -= len;
1026                 }
1027
1028                 /* Get the rest of the data if this was a header split */
1029                 if (rx_packet_len) {
1030                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1031                                            rx_bi->page,
1032                                            rx_bi->page_offset,
1033                                            rx_packet_len);
1034
1035                         skb->len += rx_packet_len;
1036                         skb->data_len += rx_packet_len;
1037                         skb->truesize += rx_packet_len;
1038
1039                         if ((page_count(rx_bi->page) == 1) &&
1040                             (page_to_nid(rx_bi->page) == current_node))
1041                                 get_page(rx_bi->page);
1042                         else
1043                                 rx_bi->page = NULL;
1044
1045                         dma_unmap_page(rx_ring->dev,
1046                                        rx_bi->page_dma,
1047                                        PAGE_SIZE / 2,
1048                                        DMA_FROM_DEVICE);
1049                         rx_bi->page_dma = 0;
1050                 }
1051                 I40E_RX_INCREMENT(rx_ring, i);
1052
1053                 if (unlikely(
1054                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1055                         struct i40e_rx_buffer *next_buffer;
1056
1057                         next_buffer = &rx_ring->rx_bi[i];
1058                         next_buffer->skb = skb;
1059                         rx_ring->rx_stats.non_eop_descs++;
1060                         continue;
1061                 }
1062
1063                 /* ERR_MASK will only have valid bits if EOP set */
1064                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1065                         dev_kfree_skb_any(skb);
1066                         continue;
1067                 }
1068
1069                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1070
1071                 /* probably a little skewed due to removing CRC */
1072                 total_rx_bytes += skb->len;
1073                 total_rx_packets++;
1074
1075                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1076
1077                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1078
1079                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1080                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1081                          : 0;
1082 #ifdef I40E_FCOE
1083                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1084                         dev_kfree_skb_any(skb);
1085                         continue;
1086                 }
1087 #endif
1088                 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
1089                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1090
1091                 rx_desc->wb.qword1.status_error_len = 0;
1092
1093         } while (likely(total_rx_packets < budget));
1094
1095         u64_stats_update_begin(&rx_ring->syncp);
1096         rx_ring->stats.packets += total_rx_packets;
1097         rx_ring->stats.bytes += total_rx_bytes;
1098         u64_stats_update_end(&rx_ring->syncp);
1099         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1100         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1101
1102         return total_rx_packets;
1103 }
1104
1105 /**
1106  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1107  * @rx_ring:  rx ring to clean
1108  * @budget:   how many cleans we're allowed
1109  *
1110  * Returns number of packets cleaned
1111  **/
1112 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1113 {
1114         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1115         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1116         struct i40e_vsi *vsi = rx_ring->vsi;
1117         union i40e_rx_desc *rx_desc;
1118         u32 rx_error, rx_status;
1119         u16 rx_packet_len;
1120         u8 rx_ptype;
1121         u64 qword;
1122         u16 i;
1123
1124         do {
1125                 struct i40e_rx_buffer *rx_bi;
1126                 struct sk_buff *skb;
1127                 u16 vlan_tag;
1128                 /* return some buffers to hardware, one at a time is too slow */
1129                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1130                         i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1131                         cleaned_count = 0;
1132                 }
1133
1134                 i = rx_ring->next_to_clean;
1135                 rx_desc = I40E_RX_DESC(rx_ring, i);
1136                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1137                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1138                         I40E_RXD_QW1_STATUS_SHIFT;
1139
1140                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1141                         break;
1142
1143                 /* This memory barrier is needed to keep us from reading
1144                  * any other fields out of the rx_desc until we know the
1145                  * DD bit is set.
1146                  */
1147                 dma_rmb();
1148
1149                 rx_bi = &rx_ring->rx_bi[i];
1150                 skb = rx_bi->skb;
1151                 prefetch(skb->data);
1152
1153                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1154                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1155
1156                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1157                            I40E_RXD_QW1_ERROR_SHIFT;
1158                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1159
1160                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1161                            I40E_RXD_QW1_PTYPE_SHIFT;
1162                 rx_bi->skb = NULL;
1163                 cleaned_count++;
1164
1165                 /* Get the header and possibly the whole packet
1166                  * If this is an skb from previous receive dma will be 0
1167                  */
1168                 skb_put(skb, rx_packet_len);
1169                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1170                                  DMA_FROM_DEVICE);
1171                 rx_bi->dma = 0;
1172
1173                 I40E_RX_INCREMENT(rx_ring, i);
1174
1175                 if (unlikely(
1176                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1177                         rx_ring->rx_stats.non_eop_descs++;
1178                         continue;
1179                 }
1180
1181                 /* ERR_MASK will only have valid bits if EOP set */
1182                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1183                         dev_kfree_skb_any(skb);
1184                         continue;
1185                 }
1186
1187                 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1188                 /* probably a little skewed due to removing CRC */
1189                 total_rx_bytes += skb->len;
1190                 total_rx_packets++;
1191
1192                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1193
1194                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1195
1196                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1197                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1198                          : 0;
1199                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1200
1201                 rx_desc->wb.qword1.status_error_len = 0;
1202         } while (likely(total_rx_packets < budget));
1203
1204         u64_stats_update_begin(&rx_ring->syncp);
1205         rx_ring->stats.packets += total_rx_packets;
1206         rx_ring->stats.bytes += total_rx_bytes;
1207         u64_stats_update_end(&rx_ring->syncp);
1208         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1209         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1210
1211         return total_rx_packets;
1212 }
1213
1214 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1215 {
1216         u32 val;
1217
1218         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1219               I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1220               (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1221               (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1222
1223         return val;
1224 }
1225
1226 /* a small macro to shorten up some long lines */
1227 #define INTREG I40E_VFINT_DYN_CTLN1
1228
1229 /**
1230  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1231  * @vsi: the VSI we care about
1232  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1233  *
1234  **/
1235 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1236                                           struct i40e_q_vector *q_vector)
1237 {
1238         struct i40e_hw *hw = &vsi->back->hw;
1239         bool rx = false, tx = false;
1240         u32 rxval, txval;
1241         int vector;
1242
1243         vector = (q_vector->v_idx + vsi->base_vector);
1244
1245         /* avoid dynamic calculation if in countdown mode OR if
1246          * all dynamic is disabled
1247          */
1248         rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1249
1250         if (q_vector->itr_countdown > 0 ||
1251             (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1252              !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1253                 goto enable_int;
1254         }
1255
1256         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1257                 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1258                 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1259         }
1260         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1261                 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1262                 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1263         }
1264         if (rx || tx) {
1265                 /* get the higher of the two ITR adjustments and
1266                  * use the same value for both ITR registers
1267                  * when in adaptive mode (Rx and/or Tx)
1268                  */
1269                 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1270
1271                 q_vector->tx.itr = q_vector->rx.itr = itr;
1272                 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1273                 tx = true;
1274                 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1275                 rx = true;
1276         }
1277
1278         /* only need to enable the interrupt once, but need
1279          * to possibly update both ITR values
1280          */
1281         if (rx) {
1282                 /* set the INTENA_MSK_MASK so that this first write
1283                  * won't actually enable the interrupt, instead just
1284                  * updating the ITR (it's bit 31 PF and VF)
1285                  */
1286                 rxval |= BIT(31);
1287                 /* don't check _DOWN because interrupt isn't being enabled */
1288                 wr32(hw, INTREG(vector - 1), rxval);
1289         }
1290
1291 enable_int:
1292         if (!test_bit(__I40E_DOWN, &vsi->state))
1293                 wr32(hw, INTREG(vector - 1), txval);
1294
1295         if (q_vector->itr_countdown)
1296                 q_vector->itr_countdown--;
1297         else
1298                 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1299
1300 }
1301
1302 /**
1303  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1304  * @napi: napi struct with our devices info in it
1305  * @budget: amount of work driver is allowed to do this pass, in packets
1306  *
1307  * This function will clean all queues associated with a q_vector.
1308  *
1309  * Returns the amount of work done
1310  **/
1311 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1312 {
1313         struct i40e_q_vector *q_vector =
1314                                container_of(napi, struct i40e_q_vector, napi);
1315         struct i40e_vsi *vsi = q_vector->vsi;
1316         struct i40e_ring *ring;
1317         bool clean_complete = true;
1318         bool arm_wb = false;
1319         int budget_per_ring;
1320         int work_done = 0;
1321
1322         if (test_bit(__I40E_DOWN, &vsi->state)) {
1323                 napi_complete(napi);
1324                 return 0;
1325         }
1326
1327         /* Since the actual Tx work is minimal, we can give the Tx a larger
1328          * budget and be more aggressive about cleaning up the Tx descriptors.
1329          */
1330         i40e_for_each_ring(ring, q_vector->tx) {
1331                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1332                 arm_wb |= ring->arm_wb;
1333                 ring->arm_wb = false;
1334         }
1335
1336         /* Handle case where we are called by netpoll with a budget of 0 */
1337         if (budget <= 0)
1338                 goto tx_only;
1339
1340         /* We attempt to distribute budget to each Rx queue fairly, but don't
1341          * allow the budget to go below 1 because that would exit polling early.
1342          */
1343         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1344
1345         i40e_for_each_ring(ring, q_vector->rx) {
1346                 int cleaned;
1347
1348                 if (ring_is_ps_enabled(ring))
1349                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1350                 else
1351                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1352
1353                 work_done += cleaned;
1354                 /* if we didn't clean as many as budgeted, we must be done */
1355                 clean_complete &= (budget_per_ring != cleaned);
1356         }
1357
1358         /* If work not completed, return budget and polling will return */
1359         if (!clean_complete) {
1360 tx_only:
1361                 if (arm_wb)
1362                         i40evf_force_wb(vsi, q_vector);
1363                 return budget;
1364         }
1365
1366         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1367                 q_vector->arm_wb_state = false;
1368
1369         /* Work is done so exit the polling mode and re-enable the interrupt */
1370         napi_complete_done(napi, work_done);
1371         i40e_update_enable_itr(vsi, q_vector);
1372         return 0;
1373 }
1374
1375 /**
1376  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1377  * @skb:     send buffer
1378  * @tx_ring: ring to send buffer on
1379  * @flags:   the tx flags to be set
1380  *
1381  * Checks the skb and set up correspondingly several generic transmit flags
1382  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1383  *
1384  * Returns error code indicate the frame should be dropped upon error and the
1385  * otherwise  returns 0 to indicate the flags has been set properly.
1386  **/
1387 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1388                                                struct i40e_ring *tx_ring,
1389                                                u32 *flags)
1390 {
1391         __be16 protocol = skb->protocol;
1392         u32  tx_flags = 0;
1393
1394         if (protocol == htons(ETH_P_8021Q) &&
1395             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1396                 /* When HW VLAN acceleration is turned off by the user the
1397                  * stack sets the protocol to 8021q so that the driver
1398                  * can take any steps required to support the SW only
1399                  * VLAN handling.  In our case the driver doesn't need
1400                  * to take any further steps so just set the protocol
1401                  * to the encapsulated ethertype.
1402                  */
1403                 skb->protocol = vlan_get_protocol(skb);
1404                 goto out;
1405         }
1406
1407         /* if we have a HW VLAN tag being added, default to the HW one */
1408         if (skb_vlan_tag_present(skb)) {
1409                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1410                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1411         /* else if it is a SW VLAN, check the next protocol and store the tag */
1412         } else if (protocol == htons(ETH_P_8021Q)) {
1413                 struct vlan_hdr *vhdr, _vhdr;
1414
1415                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1416                 if (!vhdr)
1417                         return -EINVAL;
1418
1419                 protocol = vhdr->h_vlan_encapsulated_proto;
1420                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1421                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1422         }
1423
1424 out:
1425         *flags = tx_flags;
1426         return 0;
1427 }
1428
1429 /**
1430  * i40e_tso - set up the tso context descriptor
1431  * @tx_ring:  ptr to the ring to send
1432  * @skb:      ptr to the skb we're sending
1433  * @hdr_len:  ptr to the size of the packet header
1434  * @cd_tunneling: ptr to context descriptor bits
1435  *
1436  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1437  **/
1438 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1439                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
1440                     u32 *cd_tunneling)
1441 {
1442         u32 cd_cmd, cd_tso_len, cd_mss;
1443         struct ipv6hdr *ipv6h;
1444         struct tcphdr *tcph;
1445         struct iphdr *iph;
1446         u32 l4len;
1447         int err;
1448
1449         if (!skb_is_gso(skb))
1450                 return 0;
1451
1452         err = skb_cow_head(skb, 0);
1453         if (err < 0)
1454                 return err;
1455
1456         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1457         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1458
1459         if (iph->version == 4) {
1460                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1461                 iph->tot_len = 0;
1462                 iph->check = 0;
1463                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1464                                                  0, IPPROTO_TCP, 0);
1465         } else if (ipv6h->version == 6) {
1466                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1467                 ipv6h->payload_len = 0;
1468                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1469                                                0, IPPROTO_TCP, 0);
1470         }
1471
1472         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1473         *hdr_len = (skb->encapsulation
1474                     ? (skb_inner_transport_header(skb) - skb->data)
1475                     : skb_transport_offset(skb)) + l4len;
1476
1477         /* find the field values */
1478         cd_cmd = I40E_TX_CTX_DESC_TSO;
1479         cd_tso_len = skb->len - *hdr_len;
1480         cd_mss = skb_shinfo(skb)->gso_size;
1481         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1482                                 ((u64)cd_tso_len <<
1483                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1484                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1485         return 1;
1486 }
1487
1488 /**
1489  * i40e_tx_enable_csum - Enable Tx checksum offloads
1490  * @skb: send buffer
1491  * @tx_flags: pointer to Tx flags currently set
1492  * @td_cmd: Tx descriptor command bits to set
1493  * @td_offset: Tx descriptor header offsets to set
1494  * @cd_tunneling: ptr to context desc bits
1495  **/
1496 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1497                                 u32 *td_cmd, u32 *td_offset,
1498                                 struct i40e_ring *tx_ring,
1499                                 u32 *cd_tunneling)
1500 {
1501         struct ipv6hdr *this_ipv6_hdr;
1502         unsigned int this_tcp_hdrlen;
1503         struct iphdr *this_ip_hdr;
1504         u32 network_hdr_len;
1505         u8 l4_hdr = 0;
1506         struct udphdr *oudph;
1507         struct iphdr *oiph;
1508         u32 l4_tunnel = 0;
1509
1510         if (skb->encapsulation) {
1511                 switch (ip_hdr(skb)->protocol) {
1512                 case IPPROTO_UDP:
1513                         oudph = udp_hdr(skb);
1514                         oiph = ip_hdr(skb);
1515                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1516                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1517                         break;
1518                 default:
1519                         return;
1520                 }
1521                 network_hdr_len = skb_inner_network_header_len(skb);
1522                 this_ip_hdr = inner_ip_hdr(skb);
1523                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1524                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1525
1526                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1527                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
1528                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1529                                 ip_hdr(skb)->check = 0;
1530                         } else {
1531                                 *cd_tunneling |=
1532                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1533                         }
1534                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1535                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1536                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1537                                 ip_hdr(skb)->check = 0;
1538                 }
1539
1540                 /* Now set the ctx descriptor fields */
1541                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1542                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
1543                                    l4_tunnel                             |
1544                                    ((skb_inner_network_offset(skb) -
1545                                         skb_transport_offset(skb)) >> 1) <<
1546                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1547                 if (this_ip_hdr->version == 6) {
1548                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1549                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1550                 }
1551
1552
1553                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1554                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
1555                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1556                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1557                                         oiph->daddr,
1558                                         (skb->len - skb_transport_offset(skb)),
1559                                         IPPROTO_UDP, 0);
1560                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1561                 }
1562         } else {
1563                 network_hdr_len = skb_network_header_len(skb);
1564                 this_ip_hdr = ip_hdr(skb);
1565                 this_ipv6_hdr = ipv6_hdr(skb);
1566                 this_tcp_hdrlen = tcp_hdrlen(skb);
1567         }
1568
1569         /* Enable IP checksum offloads */
1570         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1571                 l4_hdr = this_ip_hdr->protocol;
1572                 /* the stack computes the IP header already, the only time we
1573                  * need the hardware to recompute it is in the case of TSO.
1574                  */
1575                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1576                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1577                         this_ip_hdr->check = 0;
1578                 } else {
1579                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1580                 }
1581                 /* Now set the td_offset for IP header length */
1582                 *td_offset = (network_hdr_len >> 2) <<
1583                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1584         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1585                 l4_hdr = this_ipv6_hdr->nexthdr;
1586                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1587                 /* Now set the td_offset for IP header length */
1588                 *td_offset = (network_hdr_len >> 2) <<
1589                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1590         }
1591         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1592         *td_offset |= (skb_network_offset(skb) >> 1) <<
1593                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1594
1595         /* Enable L4 checksum offloads */
1596         switch (l4_hdr) {
1597         case IPPROTO_TCP:
1598                 /* enable checksum offloads */
1599                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1600                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1601                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1602                 break;
1603         case IPPROTO_SCTP:
1604                 /* enable SCTP checksum offload */
1605                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1606                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1607                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1608                 break;
1609         case IPPROTO_UDP:
1610                 /* enable UDP checksum offload */
1611                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1612                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1613                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1614                 break;
1615         default:
1616                 break;
1617         }
1618 }
1619
1620 /**
1621  * i40e_create_tx_ctx Build the Tx context descriptor
1622  * @tx_ring:  ring to create the descriptor on
1623  * @cd_type_cmd_tso_mss: Quad Word 1
1624  * @cd_tunneling: Quad Word 0 - bits 0-31
1625  * @cd_l2tag2: Quad Word 0 - bits 32-63
1626  **/
1627 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1628                                const u64 cd_type_cmd_tso_mss,
1629                                const u32 cd_tunneling, const u32 cd_l2tag2)
1630 {
1631         struct i40e_tx_context_desc *context_desc;
1632         int i = tx_ring->next_to_use;
1633
1634         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1635             !cd_tunneling && !cd_l2tag2)
1636                 return;
1637
1638         /* grab the next descriptor */
1639         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1640
1641         i++;
1642         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1643
1644         /* cpu_to_le32 and assign to struct fields */
1645         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1646         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1647         context_desc->rsvd = cpu_to_le16(0);
1648         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1649 }
1650
1651  /**
1652  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1653  * @skb:      send buffer
1654  * @tx_flags: collected send information
1655  *
1656  * Note: Our HW can't scatter-gather more than 8 fragments to build
1657  * a packet on the wire and so we need to figure out the cases where we
1658  * need to linearize the skb.
1659  **/
1660 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1661 {
1662         struct skb_frag_struct *frag;
1663         bool linearize = false;
1664         unsigned int size = 0;
1665         u16 num_frags;
1666         u16 gso_segs;
1667
1668         num_frags = skb_shinfo(skb)->nr_frags;
1669         gso_segs = skb_shinfo(skb)->gso_segs;
1670
1671         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1672                 u16 j = 0;
1673
1674                 if (num_frags < (I40E_MAX_BUFFER_TXD))
1675                         goto linearize_chk_done;
1676                 /* try the simple math, if we have too many frags per segment */
1677                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1678                     I40E_MAX_BUFFER_TXD) {
1679                         linearize = true;
1680                         goto linearize_chk_done;
1681                 }
1682                 frag = &skb_shinfo(skb)->frags[0];
1683                 /* we might still have more fragments per segment */
1684                 do {
1685                         size += skb_frag_size(frag);
1686                         frag++; j++;
1687                         if ((size >= skb_shinfo(skb)->gso_size) &&
1688                             (j < I40E_MAX_BUFFER_TXD)) {
1689                                 size = (size % skb_shinfo(skb)->gso_size);
1690                                 j = (size) ? 1 : 0;
1691                         }
1692                         if (j == I40E_MAX_BUFFER_TXD) {
1693                                 linearize = true;
1694                                 break;
1695                         }
1696                         num_frags--;
1697                 } while (num_frags);
1698         } else {
1699                 if (num_frags >= I40E_MAX_BUFFER_TXD)
1700                         linearize = true;
1701         }
1702
1703 linearize_chk_done:
1704         return linearize;
1705 }
1706
1707 /**
1708  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1709  * @tx_ring: the ring to be checked
1710  * @size:    the size buffer we want to assure is available
1711  *
1712  * Returns -EBUSY if a stop is needed, else 0
1713  **/
1714 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1715 {
1716         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1717         /* Memory barrier before checking head and tail */
1718         smp_mb();
1719
1720         /* Check again in a case another CPU has just made room available. */
1721         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1722                 return -EBUSY;
1723
1724         /* A reprieve! - use start_queue because it doesn't call schedule */
1725         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1726         ++tx_ring->tx_stats.restart_queue;
1727         return 0;
1728 }
1729
1730 /**
1731  * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1732  * @tx_ring: the ring to be checked
1733  * @size:    the size buffer we want to assure is available
1734  *
1735  * Returns 0 if stop is not needed
1736  **/
1737 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1738 {
1739         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1740                 return 0;
1741         return __i40evf_maybe_stop_tx(tx_ring, size);
1742 }
1743
1744 /**
1745  * i40evf_tx_map - Build the Tx descriptor
1746  * @tx_ring:  ring to send buffer on
1747  * @skb:      send buffer
1748  * @first:    first buffer info buffer to use
1749  * @tx_flags: collected send information
1750  * @hdr_len:  size of the packet header
1751  * @td_cmd:   the command field in the descriptor
1752  * @td_offset: offset for checksum or crc
1753  **/
1754 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1755                                  struct i40e_tx_buffer *first, u32 tx_flags,
1756                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1757 {
1758         unsigned int data_len = skb->data_len;
1759         unsigned int size = skb_headlen(skb);
1760         struct skb_frag_struct *frag;
1761         struct i40e_tx_buffer *tx_bi;
1762         struct i40e_tx_desc *tx_desc;
1763         u16 i = tx_ring->next_to_use;
1764         u32 td_tag = 0;
1765         dma_addr_t dma;
1766         u16 gso_segs;
1767         u16 desc_count = 0;
1768         bool tail_bump = true;
1769         bool do_rs = false;
1770
1771         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1772                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1773                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1774                          I40E_TX_FLAGS_VLAN_SHIFT;
1775         }
1776
1777         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1778                 gso_segs = skb_shinfo(skb)->gso_segs;
1779         else
1780                 gso_segs = 1;
1781
1782         /* multiply data chunks by size of headers */
1783         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1784         first->gso_segs = gso_segs;
1785         first->skb = skb;
1786         first->tx_flags = tx_flags;
1787
1788         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1789
1790         tx_desc = I40E_TX_DESC(tx_ring, i);
1791         tx_bi = first;
1792
1793         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1794                 if (dma_mapping_error(tx_ring->dev, dma))
1795                         goto dma_error;
1796
1797                 /* record length, and DMA address */
1798                 dma_unmap_len_set(tx_bi, len, size);
1799                 dma_unmap_addr_set(tx_bi, dma, dma);
1800
1801                 tx_desc->buffer_addr = cpu_to_le64(dma);
1802
1803                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1804                         tx_desc->cmd_type_offset_bsz =
1805                                 build_ctob(td_cmd, td_offset,
1806                                            I40E_MAX_DATA_PER_TXD, td_tag);
1807
1808                         tx_desc++;
1809                         i++;
1810                         desc_count++;
1811
1812                         if (i == tx_ring->count) {
1813                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1814                                 i = 0;
1815                         }
1816
1817                         dma += I40E_MAX_DATA_PER_TXD;
1818                         size -= I40E_MAX_DATA_PER_TXD;
1819
1820                         tx_desc->buffer_addr = cpu_to_le64(dma);
1821                 }
1822
1823                 if (likely(!data_len))
1824                         break;
1825
1826                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1827                                                           size, td_tag);
1828
1829                 tx_desc++;
1830                 i++;
1831                 desc_count++;
1832
1833                 if (i == tx_ring->count) {
1834                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1835                         i = 0;
1836                 }
1837
1838                 size = skb_frag_size(frag);
1839                 data_len -= size;
1840
1841                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1842                                        DMA_TO_DEVICE);
1843
1844                 tx_bi = &tx_ring->tx_bi[i];
1845         }
1846
1847 #define WB_STRIDE 0x3
1848         /* set next_to_watch value indicating a packet is present */
1849         first->next_to_watch = tx_desc;
1850
1851         i++;
1852         if (i == tx_ring->count)
1853                 i = 0;
1854
1855         tx_ring->next_to_use = i;
1856
1857         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1858                                                  tx_ring->queue_index),
1859                                                  first->bytecount);
1860         i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1861
1862         /* Algorithm to optimize tail and RS bit setting:
1863          * if xmit_more is supported
1864          *      if xmit_more is true
1865          *              do not update tail and do not mark RS bit.
1866          *      if xmit_more is false and last xmit_more was false
1867          *              if every packet spanned less than 4 desc
1868          *                      then set RS bit on 4th packet and update tail
1869          *                      on every packet
1870          *              else
1871          *                      update tail and set RS bit on every packet.
1872          *      if xmit_more is false and last_xmit_more was true
1873          *              update tail and set RS bit.
1874          * else (kernel < 3.18)
1875          *      if every packet spanned less than 4 desc
1876          *              then set RS bit on 4th packet and update tail
1877          *              on every packet
1878          *      else
1879          *              set RS bit on EOP for every packet and update tail
1880          *
1881          * Optimization: wmb to be issued only in case of tail update.
1882          * Also optimize the Descriptor WB path for RS bit with the same
1883          * algorithm.
1884          *
1885          * Note: If there are less than 4 packets
1886          * pending and interrupts were disabled the service task will
1887          * trigger a force WB.
1888          */
1889         if (skb->xmit_more  &&
1890             !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1891                                                     tx_ring->queue_index))) {
1892                 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1893                 tail_bump = false;
1894         } else if (!skb->xmit_more &&
1895                    !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1896                                                        tx_ring->queue_index)) &&
1897                    (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
1898                    (tx_ring->packet_stride < WB_STRIDE) &&
1899                    (desc_count < WB_STRIDE)) {
1900                 tx_ring->packet_stride++;
1901         } else {
1902                 tx_ring->packet_stride = 0;
1903                 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
1904                 do_rs = true;
1905         }
1906         if (do_rs)
1907                 tx_ring->packet_stride = 0;
1908
1909         tx_desc->cmd_type_offset_bsz =
1910                         build_ctob(td_cmd, td_offset, size, td_tag) |
1911                         cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
1912                                                   I40E_TX_DESC_CMD_EOP) <<
1913                                                   I40E_TXD_QW1_CMD_SHIFT);
1914
1915         /* notify HW of packet */
1916         if (!tail_bump)
1917                 prefetchw(tx_desc + 1);
1918
1919         if (tail_bump) {
1920                 /* Force memory writes to complete before letting h/w
1921                  * know there are new descriptors to fetch.  (Only
1922                  * applicable for weak-ordered memory model archs,
1923                  * such as IA-64).
1924                  */
1925                 wmb();
1926                 writel(i, tx_ring->tail);
1927         }
1928
1929         return;
1930
1931 dma_error:
1932         dev_info(tx_ring->dev, "TX DMA map failed\n");
1933
1934         /* clear dma mappings for failed tx_bi map */
1935         for (;;) {
1936                 tx_bi = &tx_ring->tx_bi[i];
1937                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1938                 if (tx_bi == first)
1939                         break;
1940                 if (i == 0)
1941                         i = tx_ring->count;
1942                 i--;
1943         }
1944
1945         tx_ring->next_to_use = i;
1946 }
1947
1948 /**
1949  * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
1950  * @skb:     send buffer
1951  * @tx_ring: ring to send buffer on
1952  *
1953  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1954  * there is not enough descriptors available in this ring since we need at least
1955  * one descriptor.
1956  **/
1957 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1958                                                struct i40e_ring *tx_ring)
1959 {
1960         unsigned int f;
1961         int count = 0;
1962
1963         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1964          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1965          *       + 4 desc gap to avoid the cache line where head is,
1966          *       + 1 desc for context descriptor,
1967          * otherwise try next time
1968          */
1969         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1970                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1971
1972         count += TXD_USE_COUNT(skb_headlen(skb));
1973         if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1974                 tx_ring->tx_stats.tx_busy++;
1975                 return 0;
1976         }
1977         return count;
1978 }
1979
1980 /**
1981  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1982  * @skb:     send buffer
1983  * @tx_ring: ring to send buffer on
1984  *
1985  * Returns NETDEV_TX_OK if sent, else an error code
1986  **/
1987 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1988                                         struct i40e_ring *tx_ring)
1989 {
1990         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1991         u32 cd_tunneling = 0, cd_l2tag2 = 0;
1992         struct i40e_tx_buffer *first;
1993         u32 td_offset = 0;
1994         u32 tx_flags = 0;
1995         __be16 protocol;
1996         u32 td_cmd = 0;
1997         u8 hdr_len = 0;
1998         int tso;
1999
2000         if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
2001                 return NETDEV_TX_BUSY;
2002
2003         /* prepare the xmit flags */
2004         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2005                 goto out_drop;
2006
2007         /* obtain protocol of skb */
2008         protocol = vlan_get_protocol(skb);
2009
2010         /* record the location of the first descriptor for this packet */
2011         first = &tx_ring->tx_bi[tx_ring->next_to_use];
2012
2013         /* setup IPv4/IPv6 offloads */
2014         if (protocol == htons(ETH_P_IP))
2015                 tx_flags |= I40E_TX_FLAGS_IPV4;
2016         else if (protocol == htons(ETH_P_IPV6))
2017                 tx_flags |= I40E_TX_FLAGS_IPV6;
2018
2019         tso = i40e_tso(tx_ring, skb, &hdr_len,
2020                        &cd_type_cmd_tso_mss, &cd_tunneling);
2021
2022         if (tso < 0)
2023                 goto out_drop;
2024         else if (tso)
2025                 tx_flags |= I40E_TX_FLAGS_TSO;
2026
2027         if (i40e_chk_linearize(skb, tx_flags)) {
2028                 if (skb_linearize(skb))
2029                         goto out_drop;
2030                 tx_ring->tx_stats.tx_linearize++;
2031         }
2032         skb_tx_timestamp(skb);
2033
2034         /* always enable CRC insertion offload */
2035         td_cmd |= I40E_TX_DESC_CMD_ICRC;
2036
2037         /* Always offload the checksum, since it's in the data descriptor */
2038         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2039                 tx_flags |= I40E_TX_FLAGS_CSUM;
2040
2041                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2042                                     tx_ring, &cd_tunneling);
2043         }
2044
2045         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2046                            cd_tunneling, cd_l2tag2);
2047
2048         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2049                       td_cmd, td_offset);
2050
2051         return NETDEV_TX_OK;
2052
2053 out_drop:
2054         dev_kfree_skb_any(skb);
2055         return NETDEV_TX_OK;
2056 }
2057
2058 /**
2059  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2060  * @skb:    send buffer
2061  * @netdev: network interface device structure
2062  *
2063  * Returns NETDEV_TX_OK if sent, else an error code
2064  **/
2065 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2066 {
2067         struct i40evf_adapter *adapter = netdev_priv(netdev);
2068         struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
2069
2070         /* hardware can't handle really short frames, hardware padding works
2071          * beyond this point
2072          */
2073         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2074                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2075                         return NETDEV_TX_OK;
2076                 skb->len = I40E_MIN_TX_LEN;
2077                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2078         }
2079
2080         return i40e_xmit_frame_ring(skb, tx_ring);
2081 }