1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
41 i40e_status status = 0;
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
53 case I40E_DEV_ID_10G_BASE_T:
54 case I40E_DEV_ID_10G_BASE_T4:
55 case I40E_DEV_ID_20G_KR2:
56 case I40E_DEV_ID_20G_KR2_A:
57 hw->mac.type = I40E_MAC_XL710;
59 case I40E_DEV_ID_SFP_X722:
60 case I40E_DEV_ID_1G_BASE_T_X722:
61 case I40E_DEV_ID_10G_BASE_T_X722:
62 hw->mac.type = I40E_MAC_X722;
64 case I40E_DEV_ID_X722_VF:
65 case I40E_DEV_ID_X722_VF_HV:
66 hw->mac.type = I40E_MAC_X722_VF;
69 case I40E_DEV_ID_VF_HV:
70 hw->mac.type = I40E_MAC_VF;
73 hw->mac.type = I40E_MAC_GENERIC;
77 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
80 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
81 hw->mac.type, status);
86 * i40e_aq_str - convert AQ err code to a string
87 * @hw: pointer to the HW structure
88 * @aq_err: the AQ error code to convert
90 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
95 case I40E_AQ_RC_EPERM:
96 return "I40E_AQ_RC_EPERM";
97 case I40E_AQ_RC_ENOENT:
98 return "I40E_AQ_RC_ENOENT";
99 case I40E_AQ_RC_ESRCH:
100 return "I40E_AQ_RC_ESRCH";
101 case I40E_AQ_RC_EINTR:
102 return "I40E_AQ_RC_EINTR";
104 return "I40E_AQ_RC_EIO";
105 case I40E_AQ_RC_ENXIO:
106 return "I40E_AQ_RC_ENXIO";
107 case I40E_AQ_RC_E2BIG:
108 return "I40E_AQ_RC_E2BIG";
109 case I40E_AQ_RC_EAGAIN:
110 return "I40E_AQ_RC_EAGAIN";
111 case I40E_AQ_RC_ENOMEM:
112 return "I40E_AQ_RC_ENOMEM";
113 case I40E_AQ_RC_EACCES:
114 return "I40E_AQ_RC_EACCES";
115 case I40E_AQ_RC_EFAULT:
116 return "I40E_AQ_RC_EFAULT";
117 case I40E_AQ_RC_EBUSY:
118 return "I40E_AQ_RC_EBUSY";
119 case I40E_AQ_RC_EEXIST:
120 return "I40E_AQ_RC_EEXIST";
121 case I40E_AQ_RC_EINVAL:
122 return "I40E_AQ_RC_EINVAL";
123 case I40E_AQ_RC_ENOTTY:
124 return "I40E_AQ_RC_ENOTTY";
125 case I40E_AQ_RC_ENOSPC:
126 return "I40E_AQ_RC_ENOSPC";
127 case I40E_AQ_RC_ENOSYS:
128 return "I40E_AQ_RC_ENOSYS";
129 case I40E_AQ_RC_ERANGE:
130 return "I40E_AQ_RC_ERANGE";
131 case I40E_AQ_RC_EFLUSHED:
132 return "I40E_AQ_RC_EFLUSHED";
133 case I40E_AQ_RC_BAD_ADDR:
134 return "I40E_AQ_RC_BAD_ADDR";
135 case I40E_AQ_RC_EMODE:
136 return "I40E_AQ_RC_EMODE";
137 case I40E_AQ_RC_EFBIG:
138 return "I40E_AQ_RC_EFBIG";
141 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
146 * i40e_stat_str - convert status err code to a string
147 * @hw: pointer to the HW structure
148 * @stat_err: the status error code to convert
150 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
156 return "I40E_ERR_NVM";
157 case I40E_ERR_NVM_CHECKSUM:
158 return "I40E_ERR_NVM_CHECKSUM";
160 return "I40E_ERR_PHY";
161 case I40E_ERR_CONFIG:
162 return "I40E_ERR_CONFIG";
164 return "I40E_ERR_PARAM";
165 case I40E_ERR_MAC_TYPE:
166 return "I40E_ERR_MAC_TYPE";
167 case I40E_ERR_UNKNOWN_PHY:
168 return "I40E_ERR_UNKNOWN_PHY";
169 case I40E_ERR_LINK_SETUP:
170 return "I40E_ERR_LINK_SETUP";
171 case I40E_ERR_ADAPTER_STOPPED:
172 return "I40E_ERR_ADAPTER_STOPPED";
173 case I40E_ERR_INVALID_MAC_ADDR:
174 return "I40E_ERR_INVALID_MAC_ADDR";
175 case I40E_ERR_DEVICE_NOT_SUPPORTED:
176 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
177 case I40E_ERR_MASTER_REQUESTS_PENDING:
178 return "I40E_ERR_MASTER_REQUESTS_PENDING";
179 case I40E_ERR_INVALID_LINK_SETTINGS:
180 return "I40E_ERR_INVALID_LINK_SETTINGS";
181 case I40E_ERR_AUTONEG_NOT_COMPLETE:
182 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
183 case I40E_ERR_RESET_FAILED:
184 return "I40E_ERR_RESET_FAILED";
185 case I40E_ERR_SWFW_SYNC:
186 return "I40E_ERR_SWFW_SYNC";
187 case I40E_ERR_NO_AVAILABLE_VSI:
188 return "I40E_ERR_NO_AVAILABLE_VSI";
189 case I40E_ERR_NO_MEMORY:
190 return "I40E_ERR_NO_MEMORY";
191 case I40E_ERR_BAD_PTR:
192 return "I40E_ERR_BAD_PTR";
193 case I40E_ERR_RING_FULL:
194 return "I40E_ERR_RING_FULL";
195 case I40E_ERR_INVALID_PD_ID:
196 return "I40E_ERR_INVALID_PD_ID";
197 case I40E_ERR_INVALID_QP_ID:
198 return "I40E_ERR_INVALID_QP_ID";
199 case I40E_ERR_INVALID_CQ_ID:
200 return "I40E_ERR_INVALID_CQ_ID";
201 case I40E_ERR_INVALID_CEQ_ID:
202 return "I40E_ERR_INVALID_CEQ_ID";
203 case I40E_ERR_INVALID_AEQ_ID:
204 return "I40E_ERR_INVALID_AEQ_ID";
205 case I40E_ERR_INVALID_SIZE:
206 return "I40E_ERR_INVALID_SIZE";
207 case I40E_ERR_INVALID_ARP_INDEX:
208 return "I40E_ERR_INVALID_ARP_INDEX";
209 case I40E_ERR_INVALID_FPM_FUNC_ID:
210 return "I40E_ERR_INVALID_FPM_FUNC_ID";
211 case I40E_ERR_QP_INVALID_MSG_SIZE:
212 return "I40E_ERR_QP_INVALID_MSG_SIZE";
213 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
214 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
215 case I40E_ERR_INVALID_FRAG_COUNT:
216 return "I40E_ERR_INVALID_FRAG_COUNT";
217 case I40E_ERR_QUEUE_EMPTY:
218 return "I40E_ERR_QUEUE_EMPTY";
219 case I40E_ERR_INVALID_ALIGNMENT:
220 return "I40E_ERR_INVALID_ALIGNMENT";
221 case I40E_ERR_FLUSHED_QUEUE:
222 return "I40E_ERR_FLUSHED_QUEUE";
223 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
224 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
225 case I40E_ERR_INVALID_IMM_DATA_SIZE:
226 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
227 case I40E_ERR_TIMEOUT:
228 return "I40E_ERR_TIMEOUT";
229 case I40E_ERR_OPCODE_MISMATCH:
230 return "I40E_ERR_OPCODE_MISMATCH";
231 case I40E_ERR_CQP_COMPL_ERROR:
232 return "I40E_ERR_CQP_COMPL_ERROR";
233 case I40E_ERR_INVALID_VF_ID:
234 return "I40E_ERR_INVALID_VF_ID";
235 case I40E_ERR_INVALID_HMCFN_ID:
236 return "I40E_ERR_INVALID_HMCFN_ID";
237 case I40E_ERR_BACKING_PAGE_ERROR:
238 return "I40E_ERR_BACKING_PAGE_ERROR";
239 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
240 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
241 case I40E_ERR_INVALID_PBLE_INDEX:
242 return "I40E_ERR_INVALID_PBLE_INDEX";
243 case I40E_ERR_INVALID_SD_INDEX:
244 return "I40E_ERR_INVALID_SD_INDEX";
245 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
246 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
247 case I40E_ERR_INVALID_SD_TYPE:
248 return "I40E_ERR_INVALID_SD_TYPE";
249 case I40E_ERR_MEMCPY_FAILED:
250 return "I40E_ERR_MEMCPY_FAILED";
251 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
252 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
253 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
254 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
255 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
256 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
257 case I40E_ERR_SRQ_ENABLED:
258 return "I40E_ERR_SRQ_ENABLED";
259 case I40E_ERR_ADMIN_QUEUE_ERROR:
260 return "I40E_ERR_ADMIN_QUEUE_ERROR";
261 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
262 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
263 case I40E_ERR_BUF_TOO_SHORT:
264 return "I40E_ERR_BUF_TOO_SHORT";
265 case I40E_ERR_ADMIN_QUEUE_FULL:
266 return "I40E_ERR_ADMIN_QUEUE_FULL";
267 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
268 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
269 case I40E_ERR_BAD_IWARP_CQE:
270 return "I40E_ERR_BAD_IWARP_CQE";
271 case I40E_ERR_NVM_BLANK_MODE:
272 return "I40E_ERR_NVM_BLANK_MODE";
273 case I40E_ERR_NOT_IMPLEMENTED:
274 return "I40E_ERR_NOT_IMPLEMENTED";
275 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
276 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
277 case I40E_ERR_DIAG_TEST_FAILED:
278 return "I40E_ERR_DIAG_TEST_FAILED";
279 case I40E_ERR_NOT_READY:
280 return "I40E_ERR_NOT_READY";
281 case I40E_NOT_SUPPORTED:
282 return "I40E_NOT_SUPPORTED";
283 case I40E_ERR_FIRMWARE_API_VERSION:
284 return "I40E_ERR_FIRMWARE_API_VERSION";
287 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
293 * @hw: debug mask related to admin queue
295 * @desc: pointer to admin queue descriptor
296 * @buffer: pointer to command buffer
297 * @buf_len: max length of buffer
299 * Dumps debug log about adminq command with descriptor contents.
301 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
302 void *buffer, u16 buf_len)
304 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
306 u8 *buf = (u8 *)buffer;
309 if ((!(mask & hw->debug_mask)) || (desc == NULL))
312 len = le16_to_cpu(aq_desc->datalen);
315 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
316 le16_to_cpu(aq_desc->opcode),
317 le16_to_cpu(aq_desc->flags),
318 le16_to_cpu(aq_desc->datalen),
319 le16_to_cpu(aq_desc->retval));
320 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
321 le32_to_cpu(aq_desc->cookie_high),
322 le32_to_cpu(aq_desc->cookie_low));
323 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
324 le32_to_cpu(aq_desc->params.internal.param0),
325 le32_to_cpu(aq_desc->params.internal.param1));
326 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
327 le32_to_cpu(aq_desc->params.external.addr_high),
328 le32_to_cpu(aq_desc->params.external.addr_low));
330 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
331 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
334 /* write the full 16-byte chunks */
335 for (i = 0; i < (len - 16); i += 16)
336 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i);
337 /* write whatever's left over without overrunning the buffer */
339 i40e_debug(hw, mask, "\t0x%04X %*ph\n",
340 i, len - i, buf + i);
345 * i40e_check_asq_alive
346 * @hw: pointer to the hw struct
348 * Returns true if Queue is enabled else false.
350 bool i40e_check_asq_alive(struct i40e_hw *hw)
353 return !!(rd32(hw, hw->aq.asq.len) &
354 I40E_PF_ATQLEN_ATQENABLE_MASK);
360 * i40e_aq_queue_shutdown
361 * @hw: pointer to the hw struct
362 * @unloading: is the driver unloading itself
364 * Tell the Firmware that we're shutting down the AdminQ and whether
365 * or not the driver is unloading as well.
367 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
370 struct i40e_aq_desc desc;
371 struct i40e_aqc_queue_shutdown *cmd =
372 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
375 i40e_fill_default_direct_cmd_desc(&desc,
376 i40e_aqc_opc_queue_shutdown);
379 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
380 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
386 * i40e_aq_get_set_rss_lut
387 * @hw: pointer to the hardware structure
388 * @vsi_id: vsi fw index
389 * @pf_lut: for PF table set true, for VSI table set false
390 * @lut: pointer to the lut buffer provided by the caller
391 * @lut_size: size of the lut buffer
392 * @set: set true to set the table, false to get the table
394 * Internal function to get or set RSS look up table
396 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
397 u16 vsi_id, bool pf_lut,
398 u8 *lut, u16 lut_size,
402 struct i40e_aq_desc desc;
403 struct i40e_aqc_get_set_rss_lut *cmd_resp =
404 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
407 i40e_fill_default_direct_cmd_desc(&desc,
408 i40e_aqc_opc_set_rss_lut);
410 i40e_fill_default_direct_cmd_desc(&desc,
411 i40e_aqc_opc_get_rss_lut);
413 /* Indirect command */
414 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
415 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
418 cpu_to_le16((u16)((vsi_id <<
419 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
420 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
421 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
424 cmd_resp->flags |= cpu_to_le16((u16)
425 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
426 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
427 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
429 cmd_resp->flags |= cpu_to_le16((u16)
430 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
431 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
432 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
434 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
440 * i40e_aq_get_rss_lut
441 * @hw: pointer to the hardware structure
442 * @vsi_id: vsi fw index
443 * @pf_lut: for PF table set true, for VSI table set false
444 * @lut: pointer to the lut buffer provided by the caller
445 * @lut_size: size of the lut buffer
447 * get the RSS lookup table, PF or VSI type
449 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
450 bool pf_lut, u8 *lut, u16 lut_size)
452 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
457 * i40e_aq_set_rss_lut
458 * @hw: pointer to the hardware structure
459 * @vsi_id: vsi fw index
460 * @pf_lut: for PF table set true, for VSI table set false
461 * @lut: pointer to the lut buffer provided by the caller
462 * @lut_size: size of the lut buffer
464 * set the RSS lookup table, PF or VSI type
466 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
467 bool pf_lut, u8 *lut, u16 lut_size)
469 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
473 * i40e_aq_get_set_rss_key
474 * @hw: pointer to the hw struct
475 * @vsi_id: vsi fw index
476 * @key: pointer to key info struct
477 * @set: set true to set the key, false to get the key
479 * get the RSS key per VSI
481 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
483 struct i40e_aqc_get_set_rss_key_data *key,
487 struct i40e_aq_desc desc;
488 struct i40e_aqc_get_set_rss_key *cmd_resp =
489 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
490 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
493 i40e_fill_default_direct_cmd_desc(&desc,
494 i40e_aqc_opc_set_rss_key);
496 i40e_fill_default_direct_cmd_desc(&desc,
497 i40e_aqc_opc_get_rss_key);
499 /* Indirect command */
500 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
501 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
504 cpu_to_le16((u16)((vsi_id <<
505 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
506 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
507 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
509 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
515 * i40e_aq_get_rss_key
516 * @hw: pointer to the hw struct
517 * @vsi_id: vsi fw index
518 * @key: pointer to key info struct
521 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
523 struct i40e_aqc_get_set_rss_key_data *key)
525 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
529 * i40e_aq_set_rss_key
530 * @hw: pointer to the hw struct
531 * @vsi_id: vsi fw index
532 * @key: pointer to key info struct
534 * set the RSS key per VSI
536 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
538 struct i40e_aqc_get_set_rss_key_data *key)
540 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
543 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
544 * hardware to a bit-field that can be used by SW to more easily determine the
547 * Macros are used to shorten the table lines and make this table human
550 * We store the PTYPE in the top byte of the bit field - this is just so that
551 * we can check that the table doesn't have a row missing, as the index into
552 * the table should be the PTYPE.
556 * IF NOT i40e_ptype_lookup[ptype].known
559 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
560 * Use the rest of the fields to look at the tunnels, inner protocols, etc
562 * Use the enum i40e_rx_l2_ptype to decode the packet type
566 /* macro to make the table lines short */
567 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
570 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
571 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
572 I40E_RX_PTYPE_##OUTER_FRAG, \
573 I40E_RX_PTYPE_TUNNEL_##T, \
574 I40E_RX_PTYPE_TUNNEL_END_##TE, \
575 I40E_RX_PTYPE_##TEF, \
576 I40E_RX_PTYPE_INNER_PROT_##I, \
577 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
579 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
580 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
582 /* shorter macros makes the table fit but are terse */
583 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
584 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
585 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
587 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
588 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
589 /* L2 Packet types */
590 I40E_PTT_UNUSED_ENTRY(0),
591 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
592 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
593 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
594 I40E_PTT_UNUSED_ENTRY(4),
595 I40E_PTT_UNUSED_ENTRY(5),
596 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
597 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
598 I40E_PTT_UNUSED_ENTRY(8),
599 I40E_PTT_UNUSED_ENTRY(9),
600 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
601 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
602 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
604 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
605 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
606 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
607 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
608 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
609 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
610 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
611 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
613 /* Non Tunneled IPv4 */
614 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
615 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
616 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
617 I40E_PTT_UNUSED_ENTRY(25),
618 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
619 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
620 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
623 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
624 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
625 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
626 I40E_PTT_UNUSED_ENTRY(32),
627 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
628 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
629 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
632 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
633 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
634 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
635 I40E_PTT_UNUSED_ENTRY(39),
636 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
637 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
638 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
640 /* IPv4 --> GRE/NAT */
641 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
643 /* IPv4 --> GRE/NAT --> IPv4 */
644 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
645 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
646 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
647 I40E_PTT_UNUSED_ENTRY(47),
648 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
649 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
650 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
652 /* IPv4 --> GRE/NAT --> IPv6 */
653 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
654 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
655 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
656 I40E_PTT_UNUSED_ENTRY(54),
657 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
658 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
659 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
661 /* IPv4 --> GRE/NAT --> MAC */
662 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
664 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
665 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
666 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
667 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
668 I40E_PTT_UNUSED_ENTRY(62),
669 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
670 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
671 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
673 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
674 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
675 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
676 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
677 I40E_PTT_UNUSED_ENTRY(69),
678 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
679 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
680 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
682 /* IPv4 --> GRE/NAT --> MAC/VLAN */
683 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
685 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
686 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
687 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
688 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
689 I40E_PTT_UNUSED_ENTRY(77),
690 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
691 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
692 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
694 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
695 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
696 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
697 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
698 I40E_PTT_UNUSED_ENTRY(84),
699 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
700 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
701 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
703 /* Non Tunneled IPv6 */
704 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
705 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
706 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
707 I40E_PTT_UNUSED_ENTRY(91),
708 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
709 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
710 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
713 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
714 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
715 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
716 I40E_PTT_UNUSED_ENTRY(98),
717 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
718 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
719 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
722 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
723 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
724 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
725 I40E_PTT_UNUSED_ENTRY(105),
726 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
727 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
728 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
730 /* IPv6 --> GRE/NAT */
731 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
733 /* IPv6 --> GRE/NAT -> IPv4 */
734 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
735 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
736 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
737 I40E_PTT_UNUSED_ENTRY(113),
738 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
739 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
740 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
742 /* IPv6 --> GRE/NAT -> IPv6 */
743 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
744 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
745 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
746 I40E_PTT_UNUSED_ENTRY(120),
747 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
748 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
749 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
751 /* IPv6 --> GRE/NAT -> MAC */
752 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
754 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
755 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
756 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
757 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
758 I40E_PTT_UNUSED_ENTRY(128),
759 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
760 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
761 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
763 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
764 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
765 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
766 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
767 I40E_PTT_UNUSED_ENTRY(135),
768 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
769 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
770 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
772 /* IPv6 --> GRE/NAT -> MAC/VLAN */
773 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
775 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
776 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
777 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
778 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
779 I40E_PTT_UNUSED_ENTRY(143),
780 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
781 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
782 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
784 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
785 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
786 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
787 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
788 I40E_PTT_UNUSED_ENTRY(150),
789 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
790 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
791 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
794 I40E_PTT_UNUSED_ENTRY(154),
795 I40E_PTT_UNUSED_ENTRY(155),
796 I40E_PTT_UNUSED_ENTRY(156),
797 I40E_PTT_UNUSED_ENTRY(157),
798 I40E_PTT_UNUSED_ENTRY(158),
799 I40E_PTT_UNUSED_ENTRY(159),
801 I40E_PTT_UNUSED_ENTRY(160),
802 I40E_PTT_UNUSED_ENTRY(161),
803 I40E_PTT_UNUSED_ENTRY(162),
804 I40E_PTT_UNUSED_ENTRY(163),
805 I40E_PTT_UNUSED_ENTRY(164),
806 I40E_PTT_UNUSED_ENTRY(165),
807 I40E_PTT_UNUSED_ENTRY(166),
808 I40E_PTT_UNUSED_ENTRY(167),
809 I40E_PTT_UNUSED_ENTRY(168),
810 I40E_PTT_UNUSED_ENTRY(169),
812 I40E_PTT_UNUSED_ENTRY(170),
813 I40E_PTT_UNUSED_ENTRY(171),
814 I40E_PTT_UNUSED_ENTRY(172),
815 I40E_PTT_UNUSED_ENTRY(173),
816 I40E_PTT_UNUSED_ENTRY(174),
817 I40E_PTT_UNUSED_ENTRY(175),
818 I40E_PTT_UNUSED_ENTRY(176),
819 I40E_PTT_UNUSED_ENTRY(177),
820 I40E_PTT_UNUSED_ENTRY(178),
821 I40E_PTT_UNUSED_ENTRY(179),
823 I40E_PTT_UNUSED_ENTRY(180),
824 I40E_PTT_UNUSED_ENTRY(181),
825 I40E_PTT_UNUSED_ENTRY(182),
826 I40E_PTT_UNUSED_ENTRY(183),
827 I40E_PTT_UNUSED_ENTRY(184),
828 I40E_PTT_UNUSED_ENTRY(185),
829 I40E_PTT_UNUSED_ENTRY(186),
830 I40E_PTT_UNUSED_ENTRY(187),
831 I40E_PTT_UNUSED_ENTRY(188),
832 I40E_PTT_UNUSED_ENTRY(189),
834 I40E_PTT_UNUSED_ENTRY(190),
835 I40E_PTT_UNUSED_ENTRY(191),
836 I40E_PTT_UNUSED_ENTRY(192),
837 I40E_PTT_UNUSED_ENTRY(193),
838 I40E_PTT_UNUSED_ENTRY(194),
839 I40E_PTT_UNUSED_ENTRY(195),
840 I40E_PTT_UNUSED_ENTRY(196),
841 I40E_PTT_UNUSED_ENTRY(197),
842 I40E_PTT_UNUSED_ENTRY(198),
843 I40E_PTT_UNUSED_ENTRY(199),
845 I40E_PTT_UNUSED_ENTRY(200),
846 I40E_PTT_UNUSED_ENTRY(201),
847 I40E_PTT_UNUSED_ENTRY(202),
848 I40E_PTT_UNUSED_ENTRY(203),
849 I40E_PTT_UNUSED_ENTRY(204),
850 I40E_PTT_UNUSED_ENTRY(205),
851 I40E_PTT_UNUSED_ENTRY(206),
852 I40E_PTT_UNUSED_ENTRY(207),
853 I40E_PTT_UNUSED_ENTRY(208),
854 I40E_PTT_UNUSED_ENTRY(209),
856 I40E_PTT_UNUSED_ENTRY(210),
857 I40E_PTT_UNUSED_ENTRY(211),
858 I40E_PTT_UNUSED_ENTRY(212),
859 I40E_PTT_UNUSED_ENTRY(213),
860 I40E_PTT_UNUSED_ENTRY(214),
861 I40E_PTT_UNUSED_ENTRY(215),
862 I40E_PTT_UNUSED_ENTRY(216),
863 I40E_PTT_UNUSED_ENTRY(217),
864 I40E_PTT_UNUSED_ENTRY(218),
865 I40E_PTT_UNUSED_ENTRY(219),
867 I40E_PTT_UNUSED_ENTRY(220),
868 I40E_PTT_UNUSED_ENTRY(221),
869 I40E_PTT_UNUSED_ENTRY(222),
870 I40E_PTT_UNUSED_ENTRY(223),
871 I40E_PTT_UNUSED_ENTRY(224),
872 I40E_PTT_UNUSED_ENTRY(225),
873 I40E_PTT_UNUSED_ENTRY(226),
874 I40E_PTT_UNUSED_ENTRY(227),
875 I40E_PTT_UNUSED_ENTRY(228),
876 I40E_PTT_UNUSED_ENTRY(229),
878 I40E_PTT_UNUSED_ENTRY(230),
879 I40E_PTT_UNUSED_ENTRY(231),
880 I40E_PTT_UNUSED_ENTRY(232),
881 I40E_PTT_UNUSED_ENTRY(233),
882 I40E_PTT_UNUSED_ENTRY(234),
883 I40E_PTT_UNUSED_ENTRY(235),
884 I40E_PTT_UNUSED_ENTRY(236),
885 I40E_PTT_UNUSED_ENTRY(237),
886 I40E_PTT_UNUSED_ENTRY(238),
887 I40E_PTT_UNUSED_ENTRY(239),
889 I40E_PTT_UNUSED_ENTRY(240),
890 I40E_PTT_UNUSED_ENTRY(241),
891 I40E_PTT_UNUSED_ENTRY(242),
892 I40E_PTT_UNUSED_ENTRY(243),
893 I40E_PTT_UNUSED_ENTRY(244),
894 I40E_PTT_UNUSED_ENTRY(245),
895 I40E_PTT_UNUSED_ENTRY(246),
896 I40E_PTT_UNUSED_ENTRY(247),
897 I40E_PTT_UNUSED_ENTRY(248),
898 I40E_PTT_UNUSED_ENTRY(249),
900 I40E_PTT_UNUSED_ENTRY(250),
901 I40E_PTT_UNUSED_ENTRY(251),
902 I40E_PTT_UNUSED_ENTRY(252),
903 I40E_PTT_UNUSED_ENTRY(253),
904 I40E_PTT_UNUSED_ENTRY(254),
905 I40E_PTT_UNUSED_ENTRY(255)
909 * i40e_init_shared_code - Initialize the shared code
910 * @hw: pointer to hardware structure
912 * This assigns the MAC type and PHY code and inits the NVM.
913 * Does not touch the hardware. This function must be called prior to any
914 * other function in the shared code. The i40e_hw structure should be
915 * memset to 0 prior to calling this function. The following fields in
916 * hw structure should be filled in prior to calling this function:
917 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
918 * subsystem_vendor_id, and revision_id
920 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
922 i40e_status status = 0;
923 u32 port, ari, func_rid;
925 i40e_set_mac_type(hw);
927 switch (hw->mac.type) {
932 return I40E_ERR_DEVICE_NOT_SUPPORTED;
935 hw->phy.get_link_info = true;
937 /* Determine port number and PF number*/
938 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
939 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
941 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
942 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
943 func_rid = rd32(hw, I40E_PF_FUNC_RID);
945 hw->pf_id = (u8)(func_rid & 0xff);
947 hw->pf_id = (u8)(func_rid & 0x7);
949 if (hw->mac.type == I40E_MAC_X722)
950 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
952 status = i40e_init_nvm(hw);
957 * i40e_aq_mac_address_read - Retrieve the MAC addresses
958 * @hw: pointer to the hw struct
959 * @flags: a return indicator of what addresses were added to the addr store
960 * @addrs: the requestor's mac addr store
961 * @cmd_details: pointer to command details structure or NULL
963 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
965 struct i40e_aqc_mac_address_read_data *addrs,
966 struct i40e_asq_cmd_details *cmd_details)
968 struct i40e_aq_desc desc;
969 struct i40e_aqc_mac_address_read *cmd_data =
970 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
973 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
974 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
976 status = i40e_asq_send_command(hw, &desc, addrs,
977 sizeof(*addrs), cmd_details);
978 *flags = le16_to_cpu(cmd_data->command_flags);
984 * i40e_aq_mac_address_write - Change the MAC addresses
985 * @hw: pointer to the hw struct
986 * @flags: indicates which MAC to be written
987 * @mac_addr: address to write
988 * @cmd_details: pointer to command details structure or NULL
990 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
991 u16 flags, u8 *mac_addr,
992 struct i40e_asq_cmd_details *cmd_details)
994 struct i40e_aq_desc desc;
995 struct i40e_aqc_mac_address_write *cmd_data =
996 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
999 i40e_fill_default_direct_cmd_desc(&desc,
1000 i40e_aqc_opc_mac_address_write);
1001 cmd_data->command_flags = cpu_to_le16(flags);
1002 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
1003 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
1004 ((u32)mac_addr[3] << 16) |
1005 ((u32)mac_addr[4] << 8) |
1008 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1014 * i40e_get_mac_addr - get MAC address
1015 * @hw: pointer to the HW structure
1016 * @mac_addr: pointer to MAC address
1018 * Reads the adapter's MAC address from register
1020 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1022 struct i40e_aqc_mac_address_read_data addrs;
1026 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1028 if (flags & I40E_AQC_LAN_ADDR_VALID)
1029 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1035 * i40e_get_port_mac_addr - get Port MAC address
1036 * @hw: pointer to the HW structure
1037 * @mac_addr: pointer to Port MAC address
1039 * Reads the adapter's Port MAC address
1041 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1043 struct i40e_aqc_mac_address_read_data addrs;
1047 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1051 if (flags & I40E_AQC_PORT_ADDR_VALID)
1052 ether_addr_copy(mac_addr, addrs.port_mac);
1054 status = I40E_ERR_INVALID_MAC_ADDR;
1060 * i40e_pre_tx_queue_cfg - pre tx queue configure
1061 * @hw: pointer to the HW structure
1062 * @queue: target PF queue index
1063 * @enable: state change request
1065 * Handles hw requirement to indicate intention to enable
1066 * or disable target queue.
1068 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1070 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1074 if (abs_queue_idx >= 128) {
1075 reg_block = abs_queue_idx / 128;
1076 abs_queue_idx %= 128;
1079 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1080 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1081 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1084 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1086 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1088 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1093 * i40e_get_san_mac_addr - get SAN MAC address
1094 * @hw: pointer to the HW structure
1095 * @mac_addr: pointer to SAN MAC address
1097 * Reads the adapter's SAN MAC address from NVM
1099 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1101 struct i40e_aqc_mac_address_read_data addrs;
1105 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1109 if (flags & I40E_AQC_SAN_ADDR_VALID)
1110 ether_addr_copy(mac_addr, addrs.pf_san_mac);
1112 status = I40E_ERR_INVALID_MAC_ADDR;
1119 * i40e_read_pba_string - Reads part number string from EEPROM
1120 * @hw: pointer to hardware structure
1121 * @pba_num: stores the part number string from the EEPROM
1122 * @pba_num_size: part number string buffer length
1124 * Reads the part number string from the EEPROM.
1126 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1129 i40e_status status = 0;
1135 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1136 if (status || (pba_word != 0xFAFA)) {
1137 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1141 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1143 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1147 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1149 hw_dbg(hw, "Failed to read PBA Block size.\n");
1153 /* Subtract one to get PBA word count (PBA Size word is included in
1157 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1158 hw_dbg(hw, "Buffer to small for PBA data.\n");
1159 return I40E_ERR_PARAM;
1162 for (i = 0; i < pba_size; i++) {
1163 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1165 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1169 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1170 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1172 pba_num[(pba_size * 2)] = '\0';
1178 * i40e_get_media_type - Gets media type
1179 * @hw: pointer to the hardware structure
1181 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1183 enum i40e_media_type media;
1185 switch (hw->phy.link_info.phy_type) {
1186 case I40E_PHY_TYPE_10GBASE_SR:
1187 case I40E_PHY_TYPE_10GBASE_LR:
1188 case I40E_PHY_TYPE_1000BASE_SX:
1189 case I40E_PHY_TYPE_1000BASE_LX:
1190 case I40E_PHY_TYPE_40GBASE_SR4:
1191 case I40E_PHY_TYPE_40GBASE_LR4:
1192 media = I40E_MEDIA_TYPE_FIBER;
1194 case I40E_PHY_TYPE_100BASE_TX:
1195 case I40E_PHY_TYPE_1000BASE_T:
1196 case I40E_PHY_TYPE_10GBASE_T:
1197 media = I40E_MEDIA_TYPE_BASET;
1199 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1200 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1201 case I40E_PHY_TYPE_10GBASE_CR1:
1202 case I40E_PHY_TYPE_40GBASE_CR4:
1203 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1204 case I40E_PHY_TYPE_40GBASE_AOC:
1205 case I40E_PHY_TYPE_10GBASE_AOC:
1206 media = I40E_MEDIA_TYPE_DA;
1208 case I40E_PHY_TYPE_1000BASE_KX:
1209 case I40E_PHY_TYPE_10GBASE_KX4:
1210 case I40E_PHY_TYPE_10GBASE_KR:
1211 case I40E_PHY_TYPE_40GBASE_KR4:
1212 case I40E_PHY_TYPE_20GBASE_KR2:
1213 media = I40E_MEDIA_TYPE_BACKPLANE;
1215 case I40E_PHY_TYPE_SGMII:
1216 case I40E_PHY_TYPE_XAUI:
1217 case I40E_PHY_TYPE_XFI:
1218 case I40E_PHY_TYPE_XLAUI:
1219 case I40E_PHY_TYPE_XLPPI:
1221 media = I40E_MEDIA_TYPE_UNKNOWN;
1228 #define I40E_PF_RESET_WAIT_COUNT_A0 200
1229 #define I40E_PF_RESET_WAIT_COUNT 200
1231 * i40e_pf_reset - Reset the PF
1232 * @hw: pointer to the hardware structure
1234 * Assuming someone else has triggered a global reset,
1235 * assure the global reset is complete and then reset the PF
1237 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1244 /* Poll for Global Reset steady state in case of recent GRST.
1245 * The grst delay value is in 100ms units, and we'll wait a
1246 * couple counts longer to be sure we don't just miss the end.
1248 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1249 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1250 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1251 for (cnt = 0; cnt < grst_del + 10; cnt++) {
1252 reg = rd32(hw, I40E_GLGEN_RSTAT);
1253 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1257 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1258 hw_dbg(hw, "Global reset polling failed to complete.\n");
1259 return I40E_ERR_RESET_FAILED;
1262 /* Now Wait for the FW to be ready */
1263 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1264 reg = rd32(hw, I40E_GLNVM_ULD);
1265 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1266 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1267 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1268 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1269 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1272 usleep_range(10000, 20000);
1274 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1275 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1276 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1277 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1278 return I40E_ERR_RESET_FAILED;
1281 /* If there was a Global Reset in progress when we got here,
1282 * we don't need to do the PF Reset
1285 if (hw->revision_id == 0)
1286 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1288 cnt = I40E_PF_RESET_WAIT_COUNT;
1289 reg = rd32(hw, I40E_PFGEN_CTRL);
1290 wr32(hw, I40E_PFGEN_CTRL,
1291 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1292 for (; cnt; cnt--) {
1293 reg = rd32(hw, I40E_PFGEN_CTRL);
1294 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1296 usleep_range(1000, 2000);
1298 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1299 hw_dbg(hw, "PF reset polling failed to complete.\n");
1300 return I40E_ERR_RESET_FAILED;
1304 i40e_clear_pxe_mode(hw);
1310 * i40e_clear_hw - clear out any left over hw state
1311 * @hw: pointer to the hw struct
1313 * Clear queues and interrupts, typically called at init time,
1314 * but after the capabilities have been found so we know how many
1315 * queues and msix vectors have been allocated.
1317 void i40e_clear_hw(struct i40e_hw *hw)
1319 u32 num_queues, base_queue;
1327 /* get number of interrupts, queues, and VFs */
1328 val = rd32(hw, I40E_GLPCI_CNF2);
1329 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1330 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1331 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1332 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1334 val = rd32(hw, I40E_PFLAN_QALLOC);
1335 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1336 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1337 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1338 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1339 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1340 num_queues = (j - base_queue) + 1;
1344 val = rd32(hw, I40E_PF_VT_PFALLOC);
1345 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1346 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1347 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1348 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1349 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1350 num_vfs = (j - i) + 1;
1354 /* stop all the interrupts */
1355 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1356 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1357 for (i = 0; i < num_pf_int - 2; i++)
1358 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1360 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1361 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1362 wr32(hw, I40E_PFINT_LNKLST0, val);
1363 for (i = 0; i < num_pf_int - 2; i++)
1364 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1365 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1366 for (i = 0; i < num_vfs; i++)
1367 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1368 for (i = 0; i < num_vf_int - 2; i++)
1369 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1371 /* warn the HW of the coming Tx disables */
1372 for (i = 0; i < num_queues; i++) {
1373 u32 abs_queue_idx = base_queue + i;
1376 if (abs_queue_idx >= 128) {
1377 reg_block = abs_queue_idx / 128;
1378 abs_queue_idx %= 128;
1381 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1382 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1383 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1384 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1386 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1390 /* stop all the queues */
1391 for (i = 0; i < num_queues; i++) {
1392 wr32(hw, I40E_QINT_TQCTL(i), 0);
1393 wr32(hw, I40E_QTX_ENA(i), 0);
1394 wr32(hw, I40E_QINT_RQCTL(i), 0);
1395 wr32(hw, I40E_QRX_ENA(i), 0);
1398 /* short wait for all queue disables to settle */
1403 * i40e_clear_pxe_mode - clear pxe operations mode
1404 * @hw: pointer to the hw struct
1406 * Make sure all PXE mode settings are cleared, including things
1407 * like descriptor fetch/write-back mode.
1409 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1413 if (i40e_check_asq_alive(hw))
1414 i40e_aq_clear_pxe_mode(hw, NULL);
1416 /* Clear single descriptor fetch/write-back mode */
1417 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1419 if (hw->revision_id == 0) {
1420 /* As a work around clear PXE_MODE instead of setting it */
1421 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1423 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1428 * i40e_led_is_mine - helper to find matching led
1429 * @hw: pointer to the hw struct
1430 * @idx: index into GPIO registers
1432 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1434 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1439 if (!hw->func_caps.led[idx])
1442 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1443 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1444 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1446 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1447 * if it is not our port then ignore
1449 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1456 #define I40E_COMBINED_ACTIVITY 0xA
1457 #define I40E_FILTER_ACTIVITY 0xE
1458 #define I40E_LINK_ACTIVITY 0xC
1459 #define I40E_MAC_ACTIVITY 0xD
1460 #define I40E_LED0 22
1463 * i40e_led_get - return current on/off mode
1464 * @hw: pointer to the hw struct
1466 * The value returned is the 'mode' field as defined in the
1467 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1468 * values are variations of possible behaviors relating to
1469 * blink, link, and wire.
1471 u32 i40e_led_get(struct i40e_hw *hw)
1473 u32 current_mode = 0;
1477 /* as per the documentation GPIO 22-29 are the LED
1478 * GPIO pins named LED0..LED7
1480 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1481 u32 gpio_val = i40e_led_is_mine(hw, i);
1486 /* ignore gpio LED src mode entries related to the activity
1489 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1490 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1491 switch (current_mode) {
1492 case I40E_COMBINED_ACTIVITY:
1493 case I40E_FILTER_ACTIVITY:
1494 case I40E_MAC_ACTIVITY:
1500 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1501 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1509 * i40e_led_set - set new on/off mode
1510 * @hw: pointer to the hw struct
1511 * @mode: 0=off, 0xf=on (else see manual for mode details)
1512 * @blink: true if the LED should blink when on, false if steady
1514 * if this function is used to turn on the blink it should
1515 * be used to disable the blink when restoring the original state.
1517 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1519 u32 current_mode = 0;
1522 if (mode & 0xfffffff0)
1523 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1525 /* as per the documentation GPIO 22-29 are the LED
1526 * GPIO pins named LED0..LED7
1528 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1529 u32 gpio_val = i40e_led_is_mine(hw, i);
1534 /* ignore gpio LED src mode entries related to the activity
1537 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1538 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1539 switch (current_mode) {
1540 case I40E_COMBINED_ACTIVITY:
1541 case I40E_FILTER_ACTIVITY:
1542 case I40E_MAC_ACTIVITY:
1548 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1549 /* this & is a bit of paranoia, but serves as a range check */
1550 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1551 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1553 if (mode == I40E_LINK_ACTIVITY)
1557 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1559 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1561 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1566 /* Admin command wrappers */
1569 * i40e_aq_get_phy_capabilities
1570 * @hw: pointer to the hw struct
1571 * @abilities: structure for PHY capabilities to be filled
1572 * @qualified_modules: report Qualified Modules
1573 * @report_init: report init capabilities (active are default)
1574 * @cmd_details: pointer to command details structure or NULL
1576 * Returns the various PHY abilities supported on the Port.
1578 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1579 bool qualified_modules, bool report_init,
1580 struct i40e_aq_get_phy_abilities_resp *abilities,
1581 struct i40e_asq_cmd_details *cmd_details)
1583 struct i40e_aq_desc desc;
1585 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1588 return I40E_ERR_PARAM;
1590 i40e_fill_default_direct_cmd_desc(&desc,
1591 i40e_aqc_opc_get_phy_abilities);
1593 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1594 if (abilities_size > I40E_AQ_LARGE_BUF)
1595 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1597 if (qualified_modules)
1598 desc.params.external.param0 |=
1599 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1602 desc.params.external.param0 |=
1603 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1605 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1608 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1609 status = I40E_ERR_UNKNOWN_PHY;
1612 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1618 * i40e_aq_set_phy_config
1619 * @hw: pointer to the hw struct
1620 * @config: structure with PHY configuration to be set
1621 * @cmd_details: pointer to command details structure or NULL
1623 * Set the various PHY configuration parameters
1624 * supported on the Port.One or more of the Set PHY config parameters may be
1625 * ignored in an MFP mode as the PF may not have the privilege to set some
1626 * of the PHY Config parameters. This status will be indicated by the
1629 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1630 struct i40e_aq_set_phy_config *config,
1631 struct i40e_asq_cmd_details *cmd_details)
1633 struct i40e_aq_desc desc;
1634 struct i40e_aq_set_phy_config *cmd =
1635 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1636 enum i40e_status_code status;
1639 return I40E_ERR_PARAM;
1641 i40e_fill_default_direct_cmd_desc(&desc,
1642 i40e_aqc_opc_set_phy_config);
1646 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1653 * @hw: pointer to the hw struct
1655 * Set the requested flow control mode using set_phy_config.
1657 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1658 bool atomic_restart)
1660 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1661 struct i40e_aq_get_phy_abilities_resp abilities;
1662 struct i40e_aq_set_phy_config config;
1663 enum i40e_status_code status;
1664 u8 pause_mask = 0x0;
1670 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1671 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1673 case I40E_FC_RX_PAUSE:
1674 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1676 case I40E_FC_TX_PAUSE:
1677 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1683 /* Get the current phy config */
1684 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1687 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1691 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1692 /* clear the old pause settings */
1693 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1694 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1695 /* set the new abilities */
1696 config.abilities |= pause_mask;
1697 /* If the abilities have changed, then set the new config */
1698 if (config.abilities != abilities.abilities) {
1699 /* Auto restart link so settings take effect */
1701 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1702 /* Copy over all the old settings */
1703 config.phy_type = abilities.phy_type;
1704 config.link_speed = abilities.link_speed;
1705 config.eee_capability = abilities.eee_capability;
1706 config.eeer = abilities.eeer_val;
1707 config.low_power_ctrl = abilities.d3_lpan;
1708 status = i40e_aq_set_phy_config(hw, &config, NULL);
1711 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1713 /* Update the link info */
1714 status = i40e_update_link_info(hw);
1716 /* Wait a little bit (on 40G cards it sometimes takes a really
1717 * long time for link to come back from the atomic reset)
1721 status = i40e_update_link_info(hw);
1724 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1730 * i40e_aq_clear_pxe_mode
1731 * @hw: pointer to the hw struct
1732 * @cmd_details: pointer to command details structure or NULL
1734 * Tell the firmware that the driver is taking over from PXE
1736 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1737 struct i40e_asq_cmd_details *cmd_details)
1740 struct i40e_aq_desc desc;
1741 struct i40e_aqc_clear_pxe *cmd =
1742 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1744 i40e_fill_default_direct_cmd_desc(&desc,
1745 i40e_aqc_opc_clear_pxe_mode);
1749 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1751 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1757 * i40e_aq_set_link_restart_an
1758 * @hw: pointer to the hw struct
1759 * @enable_link: if true: enable link, if false: disable link
1760 * @cmd_details: pointer to command details structure or NULL
1762 * Sets up the link and restarts the Auto-Negotiation over the link.
1764 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1766 struct i40e_asq_cmd_details *cmd_details)
1768 struct i40e_aq_desc desc;
1769 struct i40e_aqc_set_link_restart_an *cmd =
1770 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1773 i40e_fill_default_direct_cmd_desc(&desc,
1774 i40e_aqc_opc_set_link_restart_an);
1776 cmd->command = I40E_AQ_PHY_RESTART_AN;
1778 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1780 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1782 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1788 * i40e_aq_get_link_info
1789 * @hw: pointer to the hw struct
1790 * @enable_lse: enable/disable LinkStatusEvent reporting
1791 * @link: pointer to link status structure - optional
1792 * @cmd_details: pointer to command details structure or NULL
1794 * Returns the link status of the adapter.
1796 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1797 bool enable_lse, struct i40e_link_status *link,
1798 struct i40e_asq_cmd_details *cmd_details)
1800 struct i40e_aq_desc desc;
1801 struct i40e_aqc_get_link_status *resp =
1802 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1803 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1805 bool tx_pause, rx_pause;
1808 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1811 command_flags = I40E_AQ_LSE_ENABLE;
1813 command_flags = I40E_AQ_LSE_DISABLE;
1814 resp->command_flags = cpu_to_le16(command_flags);
1816 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1819 goto aq_get_link_info_exit;
1821 /* save off old link status information */
1822 hw->phy.link_info_old = *hw_link_info;
1824 /* update link status */
1825 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1826 hw->phy.media_type = i40e_get_media_type(hw);
1827 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1828 hw_link_info->link_info = resp->link_info;
1829 hw_link_info->an_info = resp->an_info;
1830 hw_link_info->ext_info = resp->ext_info;
1831 hw_link_info->loopback = resp->loopback;
1832 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1833 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1835 /* update fc info */
1836 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1837 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1838 if (tx_pause & rx_pause)
1839 hw->fc.current_mode = I40E_FC_FULL;
1841 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1843 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1845 hw->fc.current_mode = I40E_FC_NONE;
1847 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1848 hw_link_info->crc_enable = true;
1850 hw_link_info->crc_enable = false;
1852 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1853 hw_link_info->lse_enable = true;
1855 hw_link_info->lse_enable = false;
1857 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1858 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1859 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1861 /* save link status information */
1863 *link = *hw_link_info;
1865 /* flag cleared so helper functions don't call AQ again */
1866 hw->phy.get_link_info = false;
1868 aq_get_link_info_exit:
1873 * i40e_aq_set_phy_int_mask
1874 * @hw: pointer to the hw struct
1875 * @mask: interrupt mask to be set
1876 * @cmd_details: pointer to command details structure or NULL
1878 * Set link interrupt mask.
1880 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1882 struct i40e_asq_cmd_details *cmd_details)
1884 struct i40e_aq_desc desc;
1885 struct i40e_aqc_set_phy_int_mask *cmd =
1886 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1889 i40e_fill_default_direct_cmd_desc(&desc,
1890 i40e_aqc_opc_set_phy_int_mask);
1892 cmd->event_mask = cpu_to_le16(mask);
1894 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1901 * @hw: pointer to the hw struct
1902 * @vsi_ctx: pointer to a vsi context struct
1903 * @cmd_details: pointer to command details structure or NULL
1905 * Add a VSI context to the hardware.
1907 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1908 struct i40e_vsi_context *vsi_ctx,
1909 struct i40e_asq_cmd_details *cmd_details)
1911 struct i40e_aq_desc desc;
1912 struct i40e_aqc_add_get_update_vsi *cmd =
1913 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1914 struct i40e_aqc_add_get_update_vsi_completion *resp =
1915 (struct i40e_aqc_add_get_update_vsi_completion *)
1919 i40e_fill_default_direct_cmd_desc(&desc,
1920 i40e_aqc_opc_add_vsi);
1922 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1923 cmd->connection_type = vsi_ctx->connection_type;
1924 cmd->vf_id = vsi_ctx->vf_num;
1925 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1927 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1929 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1930 sizeof(vsi_ctx->info), cmd_details);
1933 goto aq_add_vsi_exit;
1935 vsi_ctx->seid = le16_to_cpu(resp->seid);
1936 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1937 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1938 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1945 * i40e_aq_set_vsi_unicast_promiscuous
1946 * @hw: pointer to the hw struct
1948 * @set: set unicast promiscuous enable/disable
1949 * @cmd_details: pointer to command details structure or NULL
1951 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1953 struct i40e_asq_cmd_details *cmd_details)
1955 struct i40e_aq_desc desc;
1956 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1957 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1961 i40e_fill_default_direct_cmd_desc(&desc,
1962 i40e_aqc_opc_set_vsi_promiscuous_modes);
1965 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1967 cmd->promiscuous_flags = cpu_to_le16(flags);
1969 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1971 cmd->seid = cpu_to_le16(seid);
1972 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1978 * i40e_aq_set_vsi_multicast_promiscuous
1979 * @hw: pointer to the hw struct
1981 * @set: set multicast promiscuous enable/disable
1982 * @cmd_details: pointer to command details structure or NULL
1984 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1985 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1987 struct i40e_aq_desc desc;
1988 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1989 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1993 i40e_fill_default_direct_cmd_desc(&desc,
1994 i40e_aqc_opc_set_vsi_promiscuous_modes);
1997 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1999 cmd->promiscuous_flags = cpu_to_le16(flags);
2001 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2003 cmd->seid = cpu_to_le16(seid);
2004 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2010 * i40e_aq_set_vsi_broadcast
2011 * @hw: pointer to the hw struct
2013 * @set_filter: true to set filter, false to clear filter
2014 * @cmd_details: pointer to command details structure or NULL
2016 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2018 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2019 u16 seid, bool set_filter,
2020 struct i40e_asq_cmd_details *cmd_details)
2022 struct i40e_aq_desc desc;
2023 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2024 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2027 i40e_fill_default_direct_cmd_desc(&desc,
2028 i40e_aqc_opc_set_vsi_promiscuous_modes);
2031 cmd->promiscuous_flags
2032 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2034 cmd->promiscuous_flags
2035 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2037 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2038 cmd->seid = cpu_to_le16(seid);
2039 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2045 * i40e_get_vsi_params - get VSI configuration info
2046 * @hw: pointer to the hw struct
2047 * @vsi_ctx: pointer to a vsi context struct
2048 * @cmd_details: pointer to command details structure or NULL
2050 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2051 struct i40e_vsi_context *vsi_ctx,
2052 struct i40e_asq_cmd_details *cmd_details)
2054 struct i40e_aq_desc desc;
2055 struct i40e_aqc_add_get_update_vsi *cmd =
2056 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2057 struct i40e_aqc_add_get_update_vsi_completion *resp =
2058 (struct i40e_aqc_add_get_update_vsi_completion *)
2062 i40e_fill_default_direct_cmd_desc(&desc,
2063 i40e_aqc_opc_get_vsi_parameters);
2065 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2067 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2069 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2070 sizeof(vsi_ctx->info), NULL);
2073 goto aq_get_vsi_params_exit;
2075 vsi_ctx->seid = le16_to_cpu(resp->seid);
2076 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2077 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2078 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2080 aq_get_vsi_params_exit:
2085 * i40e_aq_update_vsi_params
2086 * @hw: pointer to the hw struct
2087 * @vsi_ctx: pointer to a vsi context struct
2088 * @cmd_details: pointer to command details structure or NULL
2090 * Update a VSI context.
2092 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2093 struct i40e_vsi_context *vsi_ctx,
2094 struct i40e_asq_cmd_details *cmd_details)
2096 struct i40e_aq_desc desc;
2097 struct i40e_aqc_add_get_update_vsi *cmd =
2098 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2101 i40e_fill_default_direct_cmd_desc(&desc,
2102 i40e_aqc_opc_update_vsi_parameters);
2103 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2105 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2107 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2108 sizeof(vsi_ctx->info), cmd_details);
2114 * i40e_aq_get_switch_config
2115 * @hw: pointer to the hardware structure
2116 * @buf: pointer to the result buffer
2117 * @buf_size: length of input buffer
2118 * @start_seid: seid to start for the report, 0 == beginning
2119 * @cmd_details: pointer to command details structure or NULL
2121 * Fill the buf with switch configuration returned from AdminQ command
2123 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2124 struct i40e_aqc_get_switch_config_resp *buf,
2125 u16 buf_size, u16 *start_seid,
2126 struct i40e_asq_cmd_details *cmd_details)
2128 struct i40e_aq_desc desc;
2129 struct i40e_aqc_switch_seid *scfg =
2130 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2133 i40e_fill_default_direct_cmd_desc(&desc,
2134 i40e_aqc_opc_get_switch_config);
2135 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2136 if (buf_size > I40E_AQ_LARGE_BUF)
2137 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2138 scfg->seid = cpu_to_le16(*start_seid);
2140 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2141 *start_seid = le16_to_cpu(scfg->seid);
2147 * i40e_aq_get_firmware_version
2148 * @hw: pointer to the hw struct
2149 * @fw_major_version: firmware major version
2150 * @fw_minor_version: firmware minor version
2151 * @fw_build: firmware build number
2152 * @api_major_version: major queue version
2153 * @api_minor_version: minor queue version
2154 * @cmd_details: pointer to command details structure or NULL
2156 * Get the firmware version from the admin queue commands
2158 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2159 u16 *fw_major_version, u16 *fw_minor_version,
2161 u16 *api_major_version, u16 *api_minor_version,
2162 struct i40e_asq_cmd_details *cmd_details)
2164 struct i40e_aq_desc desc;
2165 struct i40e_aqc_get_version *resp =
2166 (struct i40e_aqc_get_version *)&desc.params.raw;
2169 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2171 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2174 if (fw_major_version)
2175 *fw_major_version = le16_to_cpu(resp->fw_major);
2176 if (fw_minor_version)
2177 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2179 *fw_build = le32_to_cpu(resp->fw_build);
2180 if (api_major_version)
2181 *api_major_version = le16_to_cpu(resp->api_major);
2182 if (api_minor_version)
2183 *api_minor_version = le16_to_cpu(resp->api_minor);
2190 * i40e_aq_send_driver_version
2191 * @hw: pointer to the hw struct
2192 * @dv: driver's major, minor version
2193 * @cmd_details: pointer to command details structure or NULL
2195 * Send the driver version to the firmware
2197 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2198 struct i40e_driver_version *dv,
2199 struct i40e_asq_cmd_details *cmd_details)
2201 struct i40e_aq_desc desc;
2202 struct i40e_aqc_driver_version *cmd =
2203 (struct i40e_aqc_driver_version *)&desc.params.raw;
2208 return I40E_ERR_PARAM;
2210 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2212 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2213 cmd->driver_major_ver = dv->major_version;
2214 cmd->driver_minor_ver = dv->minor_version;
2215 cmd->driver_build_ver = dv->build_version;
2216 cmd->driver_subbuild_ver = dv->subbuild_version;
2219 while (len < sizeof(dv->driver_string) &&
2220 (dv->driver_string[len] < 0x80) &&
2221 dv->driver_string[len])
2223 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2230 * i40e_get_link_status - get status of the HW network link
2231 * @hw: pointer to the hw struct
2232 * @link_up: pointer to bool (true/false = linkup/linkdown)
2234 * Variable link_up true if link is up, false if link is down.
2235 * The variable link_up is invalid if returned value of status != 0
2237 * Side effect: LinkStatusEvent reporting becomes enabled
2239 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2241 i40e_status status = 0;
2243 if (hw->phy.get_link_info) {
2244 status = i40e_update_link_info(hw);
2247 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2251 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2257 * i40e_updatelink_status - update status of the HW network link
2258 * @hw: pointer to the hw struct
2260 i40e_status i40e_update_link_info(struct i40e_hw *hw)
2262 struct i40e_aq_get_phy_abilities_resp abilities;
2263 i40e_status status = 0;
2265 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2269 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2270 status = i40e_aq_get_phy_capabilities(hw, false, false,
2275 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2276 sizeof(hw->phy.link_info.module_type));
2283 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2284 * @hw: pointer to the hw struct
2285 * @uplink_seid: the MAC or other gizmo SEID
2286 * @downlink_seid: the VSI SEID
2287 * @enabled_tc: bitmap of TCs to be enabled
2288 * @default_port: true for default port VSI, false for control port
2289 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2290 * @veb_seid: pointer to where to put the resulting VEB SEID
2291 * @cmd_details: pointer to command details structure or NULL
2293 * This asks the FW to add a VEB between the uplink and downlink
2294 * elements. If the uplink SEID is 0, this will be a floating VEB.
2296 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2297 u16 downlink_seid, u8 enabled_tc,
2298 bool default_port, bool enable_l2_filtering,
2300 struct i40e_asq_cmd_details *cmd_details)
2302 struct i40e_aq_desc desc;
2303 struct i40e_aqc_add_veb *cmd =
2304 (struct i40e_aqc_add_veb *)&desc.params.raw;
2305 struct i40e_aqc_add_veb_completion *resp =
2306 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2310 /* SEIDs need to either both be set or both be 0 for floating VEB */
2311 if (!!uplink_seid != !!downlink_seid)
2312 return I40E_ERR_PARAM;
2314 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2316 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2317 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2318 cmd->enable_tcs = enabled_tc;
2320 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2322 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2324 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2326 if (enable_l2_filtering)
2327 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2329 cmd->veb_flags = cpu_to_le16(veb_flags);
2331 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2333 if (!status && veb_seid)
2334 *veb_seid = le16_to_cpu(resp->veb_seid);
2340 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2341 * @hw: pointer to the hw struct
2342 * @veb_seid: the SEID of the VEB to query
2343 * @switch_id: the uplink switch id
2344 * @floating: set to true if the VEB is floating
2345 * @statistic_index: index of the stats counter block for this VEB
2346 * @vebs_used: number of VEB's used by function
2347 * @vebs_free: total VEB's not reserved by any function
2348 * @cmd_details: pointer to command details structure or NULL
2350 * This retrieves the parameters for a particular VEB, specified by
2351 * uplink_seid, and returns them to the caller.
2353 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2354 u16 veb_seid, u16 *switch_id,
2355 bool *floating, u16 *statistic_index,
2356 u16 *vebs_used, u16 *vebs_free,
2357 struct i40e_asq_cmd_details *cmd_details)
2359 struct i40e_aq_desc desc;
2360 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2361 (struct i40e_aqc_get_veb_parameters_completion *)
2366 return I40E_ERR_PARAM;
2368 i40e_fill_default_direct_cmd_desc(&desc,
2369 i40e_aqc_opc_get_veb_parameters);
2370 cmd_resp->seid = cpu_to_le16(veb_seid);
2372 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2377 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2378 if (statistic_index)
2379 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2381 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2383 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2385 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2387 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2398 * i40e_aq_add_macvlan
2399 * @hw: pointer to the hw struct
2400 * @seid: VSI for the mac address
2401 * @mv_list: list of macvlans to be added
2402 * @count: length of the list
2403 * @cmd_details: pointer to command details structure or NULL
2405 * Add MAC/VLAN addresses to the HW filtering
2407 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2408 struct i40e_aqc_add_macvlan_element_data *mv_list,
2409 u16 count, struct i40e_asq_cmd_details *cmd_details)
2411 struct i40e_aq_desc desc;
2412 struct i40e_aqc_macvlan *cmd =
2413 (struct i40e_aqc_macvlan *)&desc.params.raw;
2417 if (count == 0 || !mv_list || !hw)
2418 return I40E_ERR_PARAM;
2420 buf_size = count * sizeof(*mv_list);
2422 /* prep the rest of the request */
2423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2424 cmd->num_addresses = cpu_to_le16(count);
2425 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2429 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2430 if (buf_size > I40E_AQ_LARGE_BUF)
2431 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2433 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2440 * i40e_aq_remove_macvlan
2441 * @hw: pointer to the hw struct
2442 * @seid: VSI for the mac address
2443 * @mv_list: list of macvlans to be removed
2444 * @count: length of the list
2445 * @cmd_details: pointer to command details structure or NULL
2447 * Remove MAC/VLAN addresses from the HW filtering
2449 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2450 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2451 u16 count, struct i40e_asq_cmd_details *cmd_details)
2453 struct i40e_aq_desc desc;
2454 struct i40e_aqc_macvlan *cmd =
2455 (struct i40e_aqc_macvlan *)&desc.params.raw;
2459 if (count == 0 || !mv_list || !hw)
2460 return I40E_ERR_PARAM;
2462 buf_size = count * sizeof(*mv_list);
2464 /* prep the rest of the request */
2465 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2466 cmd->num_addresses = cpu_to_le16(count);
2467 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2471 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2472 if (buf_size > I40E_AQ_LARGE_BUF)
2473 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2475 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2482 * i40e_aq_send_msg_to_vf
2483 * @hw: pointer to the hardware structure
2484 * @vfid: VF id to send msg
2485 * @v_opcode: opcodes for VF-PF communication
2486 * @v_retval: return error code
2487 * @msg: pointer to the msg buffer
2488 * @msglen: msg length
2489 * @cmd_details: pointer to command details
2493 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2494 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2495 struct i40e_asq_cmd_details *cmd_details)
2497 struct i40e_aq_desc desc;
2498 struct i40e_aqc_pf_vf_message *cmd =
2499 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2502 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2503 cmd->id = cpu_to_le32(vfid);
2504 desc.cookie_high = cpu_to_le32(v_opcode);
2505 desc.cookie_low = cpu_to_le32(v_retval);
2506 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2508 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2510 if (msglen > I40E_AQ_LARGE_BUF)
2511 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2512 desc.datalen = cpu_to_le16(msglen);
2514 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2520 * i40e_aq_debug_read_register
2521 * @hw: pointer to the hw struct
2522 * @reg_addr: register address
2523 * @reg_val: register value
2524 * @cmd_details: pointer to command details structure or NULL
2526 * Read the register using the admin queue commands
2528 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2529 u32 reg_addr, u64 *reg_val,
2530 struct i40e_asq_cmd_details *cmd_details)
2532 struct i40e_aq_desc desc;
2533 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2534 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2537 if (reg_val == NULL)
2538 return I40E_ERR_PARAM;
2540 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2542 cmd_resp->address = cpu_to_le32(reg_addr);
2544 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2547 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2548 (u64)le32_to_cpu(cmd_resp->value_low);
2555 * i40e_aq_debug_write_register
2556 * @hw: pointer to the hw struct
2557 * @reg_addr: register address
2558 * @reg_val: register value
2559 * @cmd_details: pointer to command details structure or NULL
2561 * Write to a register using the admin queue commands
2563 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2564 u32 reg_addr, u64 reg_val,
2565 struct i40e_asq_cmd_details *cmd_details)
2567 struct i40e_aq_desc desc;
2568 struct i40e_aqc_debug_reg_read_write *cmd =
2569 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2572 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2574 cmd->address = cpu_to_le32(reg_addr);
2575 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2576 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2578 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2584 * i40e_aq_set_hmc_resource_profile
2585 * @hw: pointer to the hw struct
2586 * @profile: type of profile the HMC is to be set as
2587 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2588 * @cmd_details: pointer to command details structure or NULL
2590 * set the HMC profile of the device.
2592 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2593 enum i40e_aq_hmc_profile profile,
2594 u8 pe_vf_enabled_count,
2595 struct i40e_asq_cmd_details *cmd_details)
2597 struct i40e_aq_desc desc;
2598 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2599 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2602 i40e_fill_default_direct_cmd_desc(&desc,
2603 i40e_aqc_opc_set_hmc_resource_profile);
2605 cmd->pm_profile = (u8)profile;
2606 cmd->pe_vf_enabled = pe_vf_enabled_count;
2608 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2614 * i40e_aq_request_resource
2615 * @hw: pointer to the hw struct
2616 * @resource: resource id
2617 * @access: access type
2618 * @sdp_number: resource number
2619 * @timeout: the maximum time in ms that the driver may hold the resource
2620 * @cmd_details: pointer to command details structure or NULL
2622 * requests common resource using the admin queue commands
2624 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2625 enum i40e_aq_resources_ids resource,
2626 enum i40e_aq_resource_access_type access,
2627 u8 sdp_number, u64 *timeout,
2628 struct i40e_asq_cmd_details *cmd_details)
2630 struct i40e_aq_desc desc;
2631 struct i40e_aqc_request_resource *cmd_resp =
2632 (struct i40e_aqc_request_resource *)&desc.params.raw;
2635 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2637 cmd_resp->resource_id = cpu_to_le16(resource);
2638 cmd_resp->access_type = cpu_to_le16(access);
2639 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2641 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2642 /* The completion specifies the maximum time in ms that the driver
2643 * may hold the resource in the Timeout field.
2644 * If the resource is held by someone else, the command completes with
2645 * busy return value and the timeout field indicates the maximum time
2646 * the current owner of the resource has to free it.
2648 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2649 *timeout = le32_to_cpu(cmd_resp->timeout);
2655 * i40e_aq_release_resource
2656 * @hw: pointer to the hw struct
2657 * @resource: resource id
2658 * @sdp_number: resource number
2659 * @cmd_details: pointer to command details structure or NULL
2661 * release common resource using the admin queue commands
2663 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2664 enum i40e_aq_resources_ids resource,
2666 struct i40e_asq_cmd_details *cmd_details)
2668 struct i40e_aq_desc desc;
2669 struct i40e_aqc_request_resource *cmd =
2670 (struct i40e_aqc_request_resource *)&desc.params.raw;
2673 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2675 cmd->resource_id = cpu_to_le16(resource);
2676 cmd->resource_number = cpu_to_le32(sdp_number);
2678 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2685 * @hw: pointer to the hw struct
2686 * @module_pointer: module pointer location in words from the NVM beginning
2687 * @offset: byte offset from the module beginning
2688 * @length: length of the section to be read (in bytes from the offset)
2689 * @data: command buffer (size [bytes] = length)
2690 * @last_command: tells if this is the last command in a series
2691 * @cmd_details: pointer to command details structure or NULL
2693 * Read the NVM using the admin queue commands
2695 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2696 u32 offset, u16 length, void *data,
2698 struct i40e_asq_cmd_details *cmd_details)
2700 struct i40e_aq_desc desc;
2701 struct i40e_aqc_nvm_update *cmd =
2702 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2705 /* In offset the highest byte must be zeroed. */
2706 if (offset & 0xFF000000) {
2707 status = I40E_ERR_PARAM;
2708 goto i40e_aq_read_nvm_exit;
2711 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2713 /* If this is the last command in a series, set the proper flag. */
2715 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2716 cmd->module_pointer = module_pointer;
2717 cmd->offset = cpu_to_le32(offset);
2718 cmd->length = cpu_to_le16(length);
2720 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2721 if (length > I40E_AQ_LARGE_BUF)
2722 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2724 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2726 i40e_aq_read_nvm_exit:
2732 * @hw: pointer to the hw struct
2733 * @module_pointer: module pointer location in words from the NVM beginning
2734 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2735 * @length: length of the section to be erased (expressed in 4 KB)
2736 * @last_command: tells if this is the last command in a series
2737 * @cmd_details: pointer to command details structure or NULL
2739 * Erase the NVM sector using the admin queue commands
2741 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2742 u32 offset, u16 length, bool last_command,
2743 struct i40e_asq_cmd_details *cmd_details)
2745 struct i40e_aq_desc desc;
2746 struct i40e_aqc_nvm_update *cmd =
2747 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2750 /* In offset the highest byte must be zeroed. */
2751 if (offset & 0xFF000000) {
2752 status = I40E_ERR_PARAM;
2753 goto i40e_aq_erase_nvm_exit;
2756 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2758 /* If this is the last command in a series, set the proper flag. */
2760 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2761 cmd->module_pointer = module_pointer;
2762 cmd->offset = cpu_to_le32(offset);
2763 cmd->length = cpu_to_le16(length);
2765 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2767 i40e_aq_erase_nvm_exit:
2771 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2772 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2773 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2774 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2775 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2776 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2777 #define I40E_DEV_FUNC_CAP_VF 0x13
2778 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2779 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2780 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2781 #define I40E_DEV_FUNC_CAP_VSI 0x17
2782 #define I40E_DEV_FUNC_CAP_DCB 0x18
2783 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2784 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
2785 #define I40E_DEV_FUNC_CAP_RSS 0x40
2786 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2787 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2788 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2789 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2790 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2791 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2792 #define I40E_DEV_FUNC_CAP_FLEX10 0xF1
2793 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2794 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2795 #define I40E_DEV_FUNC_CAP_LED 0x61
2796 #define I40E_DEV_FUNC_CAP_SDP 0x62
2797 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2798 #define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64
2801 * i40e_parse_discover_capabilities
2802 * @hw: pointer to the hw struct
2803 * @buff: pointer to a buffer containing device/function capability records
2804 * @cap_count: number of capability records in the list
2805 * @list_type_opc: type of capabilities list to parse
2807 * Parse the device/function capabilities list.
2809 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2811 enum i40e_admin_queue_opc list_type_opc)
2813 struct i40e_aqc_list_capabilities_element_resp *cap;
2814 u32 valid_functions, num_functions;
2815 u32 number, logical_id, phys_id;
2816 struct i40e_hw_capabilities *p;
2821 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2823 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2825 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2830 for (i = 0; i < cap_count; i++, cap++) {
2831 id = le16_to_cpu(cap->id);
2832 number = le32_to_cpu(cap->number);
2833 logical_id = le32_to_cpu(cap->logical_id);
2834 phys_id = le32_to_cpu(cap->phys_id);
2835 major_rev = cap->major_rev;
2838 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2839 p->switch_mode = number;
2841 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2842 p->management_mode = number;
2844 case I40E_DEV_FUNC_CAP_NPAR:
2845 p->npar_enable = number;
2847 case I40E_DEV_FUNC_CAP_OS2BMC:
2850 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2851 p->valid_functions = number;
2853 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2855 p->sr_iov_1_1 = true;
2857 case I40E_DEV_FUNC_CAP_VF:
2858 p->num_vfs = number;
2859 p->vf_base_id = logical_id;
2861 case I40E_DEV_FUNC_CAP_VMDQ:
2865 case I40E_DEV_FUNC_CAP_802_1_QBG:
2867 p->evb_802_1_qbg = true;
2869 case I40E_DEV_FUNC_CAP_802_1_QBH:
2871 p->evb_802_1_qbh = true;
2873 case I40E_DEV_FUNC_CAP_VSI:
2874 p->num_vsis = number;
2876 case I40E_DEV_FUNC_CAP_DCB:
2879 p->enabled_tcmap = logical_id;
2883 case I40E_DEV_FUNC_CAP_FCOE:
2887 case I40E_DEV_FUNC_CAP_ISCSI:
2891 case I40E_DEV_FUNC_CAP_RSS:
2893 p->rss_table_size = number;
2894 p->rss_table_entry_width = logical_id;
2896 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2897 p->num_rx_qp = number;
2898 p->base_queue = phys_id;
2900 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2901 p->num_tx_qp = number;
2902 p->base_queue = phys_id;
2904 case I40E_DEV_FUNC_CAP_MSIX:
2905 p->num_msix_vectors = number;
2907 case I40E_DEV_FUNC_CAP_MSIX_VF:
2908 p->num_msix_vectors_vf = number;
2910 case I40E_DEV_FUNC_CAP_FLEX10:
2911 if (major_rev == 1) {
2913 p->flex10_enable = true;
2914 p->flex10_capable = true;
2917 /* Capability revision >= 2 */
2919 p->flex10_enable = true;
2921 p->flex10_capable = true;
2923 p->flex10_mode = logical_id;
2924 p->flex10_status = phys_id;
2926 case I40E_DEV_FUNC_CAP_CEM:
2930 case I40E_DEV_FUNC_CAP_IWARP:
2934 case I40E_DEV_FUNC_CAP_LED:
2935 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2936 p->led[phys_id] = true;
2938 case I40E_DEV_FUNC_CAP_SDP:
2939 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2940 p->sdp[phys_id] = true;
2942 case I40E_DEV_FUNC_CAP_MDIO:
2944 p->mdio_port_num = phys_id;
2945 p->mdio_port_mode = logical_id;
2948 case I40E_DEV_FUNC_CAP_IEEE_1588:
2950 p->ieee_1588 = true;
2952 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2954 p->fd_filters_guaranteed = number;
2955 p->fd_filters_best_effort = logical_id;
2957 case I40E_DEV_FUNC_CAP_WR_CSR_PROT:
2958 p->wr_csr_prot = (u64)number;
2959 p->wr_csr_prot |= (u64)logical_id << 32;
2967 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
2969 /* Software override ensuring FCoE is disabled if npar or mfp
2970 * mode because it is not supported in these modes.
2972 if (p->npar_enable || p->flex10_enable)
2975 /* count the enabled ports (aka the "not disabled" ports) */
2977 for (i = 0; i < 4; i++) {
2978 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2981 /* use AQ read to get the physical register offset instead
2982 * of the port relative offset
2984 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2985 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2989 valid_functions = p->valid_functions;
2991 while (valid_functions) {
2992 if (valid_functions & 1)
2994 valid_functions >>= 1;
2997 /* partition id is 1-based, and functions are evenly spread
2998 * across the ports as partitions
3000 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3001 hw->num_partitions = num_functions / hw->num_ports;
3003 /* additional HW specific goodies that might
3004 * someday be HW version specific
3006 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3010 * i40e_aq_discover_capabilities
3011 * @hw: pointer to the hw struct
3012 * @buff: a virtual buffer to hold the capabilities
3013 * @buff_size: Size of the virtual buffer
3014 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3015 * @list_type_opc: capabilities type to discover - pass in the command opcode
3016 * @cmd_details: pointer to command details structure or NULL
3018 * Get the device capabilities descriptions from the firmware
3020 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3021 void *buff, u16 buff_size, u16 *data_size,
3022 enum i40e_admin_queue_opc list_type_opc,
3023 struct i40e_asq_cmd_details *cmd_details)
3025 struct i40e_aqc_list_capabilites *cmd;
3026 struct i40e_aq_desc desc;
3027 i40e_status status = 0;
3029 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3031 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3032 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3033 status = I40E_ERR_PARAM;
3037 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3039 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3040 if (buff_size > I40E_AQ_LARGE_BUF)
3041 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3043 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3044 *data_size = le16_to_cpu(desc.datalen);
3049 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3057 * i40e_aq_update_nvm
3058 * @hw: pointer to the hw struct
3059 * @module_pointer: module pointer location in words from the NVM beginning
3060 * @offset: byte offset from the module beginning
3061 * @length: length of the section to be written (in bytes from the offset)
3062 * @data: command buffer (size [bytes] = length)
3063 * @last_command: tells if this is the last command in a series
3064 * @cmd_details: pointer to command details structure or NULL
3066 * Update the NVM using the admin queue commands
3068 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3069 u32 offset, u16 length, void *data,
3071 struct i40e_asq_cmd_details *cmd_details)
3073 struct i40e_aq_desc desc;
3074 struct i40e_aqc_nvm_update *cmd =
3075 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3078 /* In offset the highest byte must be zeroed. */
3079 if (offset & 0xFF000000) {
3080 status = I40E_ERR_PARAM;
3081 goto i40e_aq_update_nvm_exit;
3084 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3086 /* If this is the last command in a series, set the proper flag. */
3088 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3089 cmd->module_pointer = module_pointer;
3090 cmd->offset = cpu_to_le32(offset);
3091 cmd->length = cpu_to_le16(length);
3093 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3094 if (length > I40E_AQ_LARGE_BUF)
3095 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3097 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3099 i40e_aq_update_nvm_exit:
3104 * i40e_aq_get_lldp_mib
3105 * @hw: pointer to the hw struct
3106 * @bridge_type: type of bridge requested
3107 * @mib_type: Local, Remote or both Local and Remote MIBs
3108 * @buff: pointer to a user supplied buffer to store the MIB block
3109 * @buff_size: size of the buffer (in bytes)
3110 * @local_len : length of the returned Local LLDP MIB
3111 * @remote_len: length of the returned Remote LLDP MIB
3112 * @cmd_details: pointer to command details structure or NULL
3114 * Requests the complete LLDP MIB (entire packet).
3116 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3117 u8 mib_type, void *buff, u16 buff_size,
3118 u16 *local_len, u16 *remote_len,
3119 struct i40e_asq_cmd_details *cmd_details)
3121 struct i40e_aq_desc desc;
3122 struct i40e_aqc_lldp_get_mib *cmd =
3123 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3124 struct i40e_aqc_lldp_get_mib *resp =
3125 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3128 if (buff_size == 0 || !buff)
3129 return I40E_ERR_PARAM;
3131 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3132 /* Indirect Command */
3133 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3135 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3136 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3137 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3139 desc.datalen = cpu_to_le16(buff_size);
3141 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3142 if (buff_size > I40E_AQ_LARGE_BUF)
3143 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3145 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3147 if (local_len != NULL)
3148 *local_len = le16_to_cpu(resp->local_len);
3149 if (remote_len != NULL)
3150 *remote_len = le16_to_cpu(resp->remote_len);
3157 * i40e_aq_cfg_lldp_mib_change_event
3158 * @hw: pointer to the hw struct
3159 * @enable_update: Enable or Disable event posting
3160 * @cmd_details: pointer to command details structure or NULL
3162 * Enable or Disable posting of an event on ARQ when LLDP MIB
3163 * associated with the interface changes
3165 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3167 struct i40e_asq_cmd_details *cmd_details)
3169 struct i40e_aq_desc desc;
3170 struct i40e_aqc_lldp_update_mib *cmd =
3171 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3174 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3177 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3179 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3186 * @hw: pointer to the hw struct
3187 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3188 * @cmd_details: pointer to command details structure or NULL
3190 * Stop or Shutdown the embedded LLDP Agent
3192 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3193 struct i40e_asq_cmd_details *cmd_details)
3195 struct i40e_aq_desc desc;
3196 struct i40e_aqc_lldp_stop *cmd =
3197 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3200 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3203 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3205 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3211 * i40e_aq_start_lldp
3212 * @hw: pointer to the hw struct
3213 * @cmd_details: pointer to command details structure or NULL
3215 * Start the embedded LLDP Agent on all ports.
3217 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3218 struct i40e_asq_cmd_details *cmd_details)
3220 struct i40e_aq_desc desc;
3221 struct i40e_aqc_lldp_start *cmd =
3222 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3225 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3227 cmd->command = I40E_AQ_LLDP_AGENT_START;
3229 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3235 * i40e_aq_get_cee_dcb_config
3236 * @hw: pointer to the hw struct
3237 * @buff: response buffer that stores CEE operational configuration
3238 * @buff_size: size of the buffer passed
3239 * @cmd_details: pointer to command details structure or NULL
3241 * Get CEE DCBX mode operational configuration from firmware
3243 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3244 void *buff, u16 buff_size,
3245 struct i40e_asq_cmd_details *cmd_details)
3247 struct i40e_aq_desc desc;
3250 if (buff_size == 0 || !buff)
3251 return I40E_ERR_PARAM;
3253 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3255 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3256 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3263 * i40e_aq_add_udp_tunnel
3264 * @hw: pointer to the hw struct
3265 * @udp_port: the UDP port to add
3266 * @header_len: length of the tunneling header length in DWords
3267 * @protocol_index: protocol index type
3268 * @filter_index: pointer to filter index
3269 * @cmd_details: pointer to command details structure or NULL
3271 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3272 u16 udp_port, u8 protocol_index,
3274 struct i40e_asq_cmd_details *cmd_details)
3276 struct i40e_aq_desc desc;
3277 struct i40e_aqc_add_udp_tunnel *cmd =
3278 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3279 struct i40e_aqc_del_udp_tunnel_completion *resp =
3280 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3283 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3285 cmd->udp_port = cpu_to_le16(udp_port);
3286 cmd->protocol_type = protocol_index;
3288 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3290 if (!status && filter_index)
3291 *filter_index = resp->index;
3297 * i40e_aq_del_udp_tunnel
3298 * @hw: pointer to the hw struct
3299 * @index: filter index
3300 * @cmd_details: pointer to command details structure or NULL
3302 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3303 struct i40e_asq_cmd_details *cmd_details)
3305 struct i40e_aq_desc desc;
3306 struct i40e_aqc_remove_udp_tunnel *cmd =
3307 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3310 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3314 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3320 * i40e_aq_delete_element - Delete switch element
3321 * @hw: pointer to the hw struct
3322 * @seid: the SEID to delete from the switch
3323 * @cmd_details: pointer to command details structure or NULL
3325 * This deletes a switch element from the switch.
3327 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3328 struct i40e_asq_cmd_details *cmd_details)
3330 struct i40e_aq_desc desc;
3331 struct i40e_aqc_switch_seid *cmd =
3332 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3336 return I40E_ERR_PARAM;
3338 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3340 cmd->seid = cpu_to_le16(seid);
3342 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3348 * i40e_aq_dcb_updated - DCB Updated Command
3349 * @hw: pointer to the hw struct
3350 * @cmd_details: pointer to command details structure or NULL
3352 * EMP will return when the shared RPB settings have been
3353 * recomputed and modified. The retval field in the descriptor
3354 * will be set to 0 when RPB is modified.
3356 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3357 struct i40e_asq_cmd_details *cmd_details)
3359 struct i40e_aq_desc desc;
3362 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3364 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3370 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3371 * @hw: pointer to the hw struct
3372 * @seid: seid for the physical port/switching component/vsi
3373 * @buff: Indirect buffer to hold data parameters and response
3374 * @buff_size: Indirect buffer size
3375 * @opcode: Tx scheduler AQ command opcode
3376 * @cmd_details: pointer to command details structure or NULL
3378 * Generic command handler for Tx scheduler AQ commands
3380 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3381 void *buff, u16 buff_size,
3382 enum i40e_admin_queue_opc opcode,
3383 struct i40e_asq_cmd_details *cmd_details)
3385 struct i40e_aq_desc desc;
3386 struct i40e_aqc_tx_sched_ind *cmd =
3387 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3389 bool cmd_param_flag = false;
3392 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3393 case i40e_aqc_opc_configure_vsi_tc_bw:
3394 case i40e_aqc_opc_enable_switching_comp_ets:
3395 case i40e_aqc_opc_modify_switching_comp_ets:
3396 case i40e_aqc_opc_disable_switching_comp_ets:
3397 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3398 case i40e_aqc_opc_configure_switching_comp_bw_config:
3399 cmd_param_flag = true;
3401 case i40e_aqc_opc_query_vsi_bw_config:
3402 case i40e_aqc_opc_query_vsi_ets_sla_config:
3403 case i40e_aqc_opc_query_switching_comp_ets_config:
3404 case i40e_aqc_opc_query_port_ets_config:
3405 case i40e_aqc_opc_query_switching_comp_bw_config:
3406 cmd_param_flag = false;
3409 return I40E_ERR_PARAM;
3412 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3414 /* Indirect command */
3415 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3417 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3418 if (buff_size > I40E_AQ_LARGE_BUF)
3419 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3421 desc.datalen = cpu_to_le16(buff_size);
3423 cmd->vsi_seid = cpu_to_le16(seid);
3425 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3431 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3432 * @hw: pointer to the hw struct
3434 * @credit: BW limit credits (0 = disabled)
3435 * @max_credit: Max BW limit credits
3436 * @cmd_details: pointer to command details structure or NULL
3438 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3439 u16 seid, u16 credit, u8 max_credit,
3440 struct i40e_asq_cmd_details *cmd_details)
3442 struct i40e_aq_desc desc;
3443 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3444 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3447 i40e_fill_default_direct_cmd_desc(&desc,
3448 i40e_aqc_opc_configure_vsi_bw_limit);
3450 cmd->vsi_seid = cpu_to_le16(seid);
3451 cmd->credit = cpu_to_le16(credit);
3452 cmd->max_credit = max_credit;
3454 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3460 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3461 * @hw: pointer to the hw struct
3463 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3464 * @cmd_details: pointer to command details structure or NULL
3466 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3468 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3469 struct i40e_asq_cmd_details *cmd_details)
3471 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3472 i40e_aqc_opc_configure_vsi_tc_bw,
3477 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3478 * @hw: pointer to the hw struct
3479 * @seid: seid of the switching component connected to Physical Port
3480 * @ets_data: Buffer holding ETS parameters
3481 * @cmd_details: pointer to command details structure or NULL
3483 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3485 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3486 enum i40e_admin_queue_opc opcode,
3487 struct i40e_asq_cmd_details *cmd_details)
3489 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3490 sizeof(*ets_data), opcode, cmd_details);
3494 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3495 * @hw: pointer to the hw struct
3496 * @seid: seid of the switching component
3497 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3498 * @cmd_details: pointer to command details structure or NULL
3500 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3502 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3503 struct i40e_asq_cmd_details *cmd_details)
3505 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3506 i40e_aqc_opc_configure_switching_comp_bw_config,
3511 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3512 * @hw: pointer to the hw struct
3513 * @seid: seid of the VSI
3514 * @bw_data: Buffer to hold VSI BW configuration
3515 * @cmd_details: pointer to command details structure or NULL
3517 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3519 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3520 struct i40e_asq_cmd_details *cmd_details)
3522 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3523 i40e_aqc_opc_query_vsi_bw_config,
3528 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3529 * @hw: pointer to the hw struct
3530 * @seid: seid of the VSI
3531 * @bw_data: Buffer to hold VSI BW configuration per TC
3532 * @cmd_details: pointer to command details structure or NULL
3534 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3536 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3537 struct i40e_asq_cmd_details *cmd_details)
3539 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3540 i40e_aqc_opc_query_vsi_ets_sla_config,
3545 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3546 * @hw: pointer to the hw struct
3547 * @seid: seid of the switching component
3548 * @bw_data: Buffer to hold switching component's per TC BW config
3549 * @cmd_details: pointer to command details structure or NULL
3551 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3553 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3554 struct i40e_asq_cmd_details *cmd_details)
3556 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3557 i40e_aqc_opc_query_switching_comp_ets_config,
3562 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3563 * @hw: pointer to the hw struct
3564 * @seid: seid of the VSI or switching component connected to Physical Port
3565 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3566 * @cmd_details: pointer to command details structure or NULL
3568 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3570 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3571 struct i40e_asq_cmd_details *cmd_details)
3573 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3574 i40e_aqc_opc_query_port_ets_config,
3579 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3580 * @hw: pointer to the hw struct
3581 * @seid: seid of the switching component
3582 * @bw_data: Buffer to hold switching component's BW configuration
3583 * @cmd_details: pointer to command details structure or NULL
3585 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3587 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3588 struct i40e_asq_cmd_details *cmd_details)
3590 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3591 i40e_aqc_opc_query_switching_comp_bw_config,
3596 * i40e_validate_filter_settings
3597 * @hw: pointer to the hardware structure
3598 * @settings: Filter control settings
3600 * Check and validate the filter control settings passed.
3601 * The function checks for the valid filter/context sizes being
3602 * passed for FCoE and PE.
3604 * Returns 0 if the values passed are valid and within
3605 * range else returns an error.
3607 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3608 struct i40e_filter_control_settings *settings)
3610 u32 fcoe_cntx_size, fcoe_filt_size;
3611 u32 pe_cntx_size, pe_filt_size;
3615 /* Validate FCoE settings passed */
3616 switch (settings->fcoe_filt_num) {
3617 case I40E_HASH_FILTER_SIZE_1K:
3618 case I40E_HASH_FILTER_SIZE_2K:
3619 case I40E_HASH_FILTER_SIZE_4K:
3620 case I40E_HASH_FILTER_SIZE_8K:
3621 case I40E_HASH_FILTER_SIZE_16K:
3622 case I40E_HASH_FILTER_SIZE_32K:
3623 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3624 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3627 return I40E_ERR_PARAM;
3630 switch (settings->fcoe_cntx_num) {
3631 case I40E_DMA_CNTX_SIZE_512:
3632 case I40E_DMA_CNTX_SIZE_1K:
3633 case I40E_DMA_CNTX_SIZE_2K:
3634 case I40E_DMA_CNTX_SIZE_4K:
3635 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3636 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3639 return I40E_ERR_PARAM;
3642 /* Validate PE settings passed */
3643 switch (settings->pe_filt_num) {
3644 case I40E_HASH_FILTER_SIZE_1K:
3645 case I40E_HASH_FILTER_SIZE_2K:
3646 case I40E_HASH_FILTER_SIZE_4K:
3647 case I40E_HASH_FILTER_SIZE_8K:
3648 case I40E_HASH_FILTER_SIZE_16K:
3649 case I40E_HASH_FILTER_SIZE_32K:
3650 case I40E_HASH_FILTER_SIZE_64K:
3651 case I40E_HASH_FILTER_SIZE_128K:
3652 case I40E_HASH_FILTER_SIZE_256K:
3653 case I40E_HASH_FILTER_SIZE_512K:
3654 case I40E_HASH_FILTER_SIZE_1M:
3655 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3656 pe_filt_size <<= (u32)settings->pe_filt_num;
3659 return I40E_ERR_PARAM;
3662 switch (settings->pe_cntx_num) {
3663 case I40E_DMA_CNTX_SIZE_512:
3664 case I40E_DMA_CNTX_SIZE_1K:
3665 case I40E_DMA_CNTX_SIZE_2K:
3666 case I40E_DMA_CNTX_SIZE_4K:
3667 case I40E_DMA_CNTX_SIZE_8K:
3668 case I40E_DMA_CNTX_SIZE_16K:
3669 case I40E_DMA_CNTX_SIZE_32K:
3670 case I40E_DMA_CNTX_SIZE_64K:
3671 case I40E_DMA_CNTX_SIZE_128K:
3672 case I40E_DMA_CNTX_SIZE_256K:
3673 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3674 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3677 return I40E_ERR_PARAM;
3680 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3681 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3682 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3683 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3684 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3685 return I40E_ERR_INVALID_SIZE;
3691 * i40e_set_filter_control
3692 * @hw: pointer to the hardware structure
3693 * @settings: Filter control settings
3695 * Set the Queue Filters for PE/FCoE and enable filters required
3696 * for a single PF. It is expected that these settings are programmed
3697 * at the driver initialization time.
3699 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3700 struct i40e_filter_control_settings *settings)
3702 i40e_status ret = 0;
3703 u32 hash_lut_size = 0;
3707 return I40E_ERR_PARAM;
3709 /* Validate the input settings */
3710 ret = i40e_validate_filter_settings(hw, settings);
3714 /* Read the PF Queue Filter control register */
3715 val = rd32(hw, I40E_PFQF_CTL_0);
3717 /* Program required PE hash buckets for the PF */
3718 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3719 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3720 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3721 /* Program required PE contexts for the PF */
3722 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3723 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3724 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3726 /* Program required FCoE hash buckets for the PF */
3727 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3728 val |= ((u32)settings->fcoe_filt_num <<
3729 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3730 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3731 /* Program required FCoE DDP contexts for the PF */
3732 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3733 val |= ((u32)settings->fcoe_cntx_num <<
3734 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3735 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3737 /* Program Hash LUT size for the PF */
3738 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3739 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3741 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3742 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3744 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3745 if (settings->enable_fdir)
3746 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3747 if (settings->enable_ethtype)
3748 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3749 if (settings->enable_macvlan)
3750 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3752 wr32(hw, I40E_PFQF_CTL_0, val);
3758 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3759 * @hw: pointer to the hw struct
3760 * @mac_addr: MAC address to use in the filter
3761 * @ethtype: Ethertype to use in the filter
3762 * @flags: Flags that needs to be applied to the filter
3763 * @vsi_seid: seid of the control VSI
3764 * @queue: VSI queue number to send the packet to
3765 * @is_add: Add control packet filter if True else remove
3766 * @stats: Structure to hold information on control filter counts
3767 * @cmd_details: pointer to command details structure or NULL
3769 * This command will Add or Remove control packet filter for a control VSI.
3770 * In return it will update the total number of perfect filter count in
3773 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3774 u8 *mac_addr, u16 ethtype, u16 flags,
3775 u16 vsi_seid, u16 queue, bool is_add,
3776 struct i40e_control_filter_stats *stats,
3777 struct i40e_asq_cmd_details *cmd_details)
3779 struct i40e_aq_desc desc;
3780 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3781 (struct i40e_aqc_add_remove_control_packet_filter *)
3783 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3784 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3789 return I40E_ERR_PARAM;
3792 i40e_fill_default_direct_cmd_desc(&desc,
3793 i40e_aqc_opc_add_control_packet_filter);
3794 cmd->queue = cpu_to_le16(queue);
3796 i40e_fill_default_direct_cmd_desc(&desc,
3797 i40e_aqc_opc_remove_control_packet_filter);
3801 ether_addr_copy(cmd->mac, mac_addr);
3803 cmd->etype = cpu_to_le16(ethtype);
3804 cmd->flags = cpu_to_le16(flags);
3805 cmd->seid = cpu_to_le16(vsi_seid);
3807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3809 if (!status && stats) {
3810 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3811 stats->etype_used = le16_to_cpu(resp->etype_used);
3812 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3813 stats->etype_free = le16_to_cpu(resp->etype_free);
3820 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
3821 * @hw: pointer to the hw struct
3822 * @seid: VSI seid to add ethertype filter from
3824 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
3825 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
3828 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
3829 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
3830 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
3831 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
3834 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
3835 seid, 0, true, NULL,
3838 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
3842 * i40e_aq_alternate_read
3843 * @hw: pointer to the hardware structure
3844 * @reg_addr0: address of first dword to be read
3845 * @reg_val0: pointer for data read from 'reg_addr0'
3846 * @reg_addr1: address of second dword to be read
3847 * @reg_val1: pointer for data read from 'reg_addr1'
3849 * Read one or two dwords from alternate structure. Fields are indicated
3850 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
3851 * is not passed then only register at 'reg_addr0' is read.
3854 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
3855 u32 reg_addr0, u32 *reg_val0,
3856 u32 reg_addr1, u32 *reg_val1)
3858 struct i40e_aq_desc desc;
3859 struct i40e_aqc_alternate_write *cmd_resp =
3860 (struct i40e_aqc_alternate_write *)&desc.params.raw;
3864 return I40E_ERR_PARAM;
3866 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
3867 cmd_resp->address0 = cpu_to_le32(reg_addr0);
3868 cmd_resp->address1 = cpu_to_le32(reg_addr1);
3870 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3873 *reg_val0 = le32_to_cpu(cmd_resp->data0);
3876 *reg_val1 = le32_to_cpu(cmd_resp->data1);
3883 * i40e_aq_resume_port_tx
3884 * @hw: pointer to the hardware structure
3885 * @cmd_details: pointer to command details structure or NULL
3887 * Resume port's Tx traffic
3889 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
3890 struct i40e_asq_cmd_details *cmd_details)
3892 struct i40e_aq_desc desc;
3895 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
3897 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3903 * i40e_set_pci_config_data - store PCI bus info
3904 * @hw: pointer to hardware structure
3905 * @link_status: the link status word from PCI config space
3907 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3909 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3911 hw->bus.type = i40e_bus_type_pci_express;
3913 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3914 case PCI_EXP_LNKSTA_NLW_X1:
3915 hw->bus.width = i40e_bus_width_pcie_x1;
3917 case PCI_EXP_LNKSTA_NLW_X2:
3918 hw->bus.width = i40e_bus_width_pcie_x2;
3920 case PCI_EXP_LNKSTA_NLW_X4:
3921 hw->bus.width = i40e_bus_width_pcie_x4;
3923 case PCI_EXP_LNKSTA_NLW_X8:
3924 hw->bus.width = i40e_bus_width_pcie_x8;
3927 hw->bus.width = i40e_bus_width_unknown;
3931 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3932 case PCI_EXP_LNKSTA_CLS_2_5GB:
3933 hw->bus.speed = i40e_bus_speed_2500;
3935 case PCI_EXP_LNKSTA_CLS_5_0GB:
3936 hw->bus.speed = i40e_bus_speed_5000;
3938 case PCI_EXP_LNKSTA_CLS_8_0GB:
3939 hw->bus.speed = i40e_bus_speed_8000;
3942 hw->bus.speed = i40e_bus_speed_unknown;
3948 * i40e_aq_debug_dump
3949 * @hw: pointer to the hardware structure
3950 * @cluster_id: specific cluster to dump
3951 * @table_id: table id within cluster
3952 * @start_index: index of line in the block to read
3953 * @buff_size: dump buffer size
3954 * @buff: dump buffer
3955 * @ret_buff_size: actual buffer size returned
3956 * @ret_next_table: next block to read
3957 * @ret_next_index: next index to read
3959 * Dump internal FW/HW data for debug purposes.
3962 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
3963 u8 table_id, u32 start_index, u16 buff_size,
3964 void *buff, u16 *ret_buff_size,
3965 u8 *ret_next_table, u32 *ret_next_index,
3966 struct i40e_asq_cmd_details *cmd_details)
3968 struct i40e_aq_desc desc;
3969 struct i40e_aqc_debug_dump_internals *cmd =
3970 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
3971 struct i40e_aqc_debug_dump_internals *resp =
3972 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
3975 if (buff_size == 0 || !buff)
3976 return I40E_ERR_PARAM;
3978 i40e_fill_default_direct_cmd_desc(&desc,
3979 i40e_aqc_opc_debug_dump_internals);
3980 /* Indirect Command */
3981 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3982 if (buff_size > I40E_AQ_LARGE_BUF)
3983 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3985 cmd->cluster_id = cluster_id;
3986 cmd->table_id = table_id;
3987 cmd->idx = cpu_to_le32(start_index);
3989 desc.datalen = cpu_to_le16(buff_size);
3991 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3994 *ret_buff_size = le16_to_cpu(desc.datalen);
3996 *ret_next_table = resp->table_id;
3998 *ret_next_index = le32_to_cpu(resp->idx);
4005 * i40e_read_bw_from_alt_ram
4006 * @hw: pointer to the hardware structure
4007 * @max_bw: pointer for max_bw read
4008 * @min_bw: pointer for min_bw read
4009 * @min_valid: pointer for bool that is true if min_bw is a valid value
4010 * @max_valid: pointer for bool that is true if max_bw is a valid value
4012 * Read bw from the alternate ram for the given pf
4014 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4015 u32 *max_bw, u32 *min_bw,
4016 bool *min_valid, bool *max_valid)
4019 u32 max_bw_addr, min_bw_addr;
4021 /* Calculate the address of the min/max bw registers */
4022 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4023 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4024 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4025 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4026 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4027 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4029 /* Read the bandwidths from alt ram */
4030 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4031 min_bw_addr, min_bw);
4033 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4038 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4047 * i40e_aq_configure_partition_bw
4048 * @hw: pointer to the hardware structure
4049 * @bw_data: Buffer holding valid pfs and bw limits
4050 * @cmd_details: pointer to command details
4052 * Configure partitions guaranteed/max bw
4054 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4055 struct i40e_aqc_configure_partition_bw_data *bw_data,
4056 struct i40e_asq_cmd_details *cmd_details)
4059 struct i40e_aq_desc desc;
4060 u16 bwd_size = sizeof(*bw_data);
4062 i40e_fill_default_direct_cmd_desc(&desc,
4063 i40e_aqc_opc_configure_partition_bw);
4065 /* Indirect command */
4066 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4067 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4069 if (bwd_size > I40E_AQ_LARGE_BUF)
4070 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4072 desc.datalen = cpu_to_le16(bwd_size);
4074 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,