kernel/drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /* Intel PRO/1000 Linux driver
   2  * Copyright(c) 1999 - 2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * The full GNU General Public License is included in this distribution in
  14  * the file called "COPYING".
  15  *
  16  * Contact Information:
  17  * Linux NICS <linux.nics@intel.com>
  18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20  */
  21
  22 /* 82562G 10/100 Network Connection
  23  * 82562G-2 10/100 Network Connection
  24  * 82562GT 10/100 Network Connection
  25  * 82562GT-2 10/100 Network Connection
  26  * 82562V 10/100 Network Connection
  27  * 82562V-2 10/100 Network Connection
  28  * 82566DC-2 Gigabit Network Connection
  29  * 82566DC Gigabit Network Connection
  30  * 82566DM-2 Gigabit Network Connection
  31  * 82566DM Gigabit Network Connection
  32  * 82566MC Gigabit Network Connection
  33  * 82566MM Gigabit Network Connection
  34  * 82567LM Gigabit Network Connection
  35  * 82567LF Gigabit Network Connection
  36  * 82567V Gigabit Network Connection
  37  * 82567LM-2 Gigabit Network Connection
  38  * 82567LF-2 Gigabit Network Connection
  39  * 82567V-2 Gigabit Network Connection
  40  * 82567LF-3 Gigabit Network Connection
  41  * 82567LM-3 Gigabit Network Connection
  42  * 82567LM-4 Gigabit Network Connection
  43  * 82577LM Gigabit Network Connection
  44  * 82577LC Gigabit Network Connection
  45  * 82578DM Gigabit Network Connection
  46  * 82578DC Gigabit Network Connection
  47  * 82579LM Gigabit Network Connection
  48  * 82579V Gigabit Network Connection
  49  * Ethernet Connection I217-LM
  50  * Ethernet Connection I217-V
  51  * Ethernet Connection I218-V
  52  * Ethernet Connection I218-LM
  53  * Ethernet Connection (2) I218-LM
  54  * Ethernet Connection (2) I218-V
  55  * Ethernet Connection (3) I218-LM
  56  * Ethernet Connection (3) I218-V
  57  */
  58
  59 #include "e1000.h"
  60
  61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  62 /* Offset 04h HSFSTS */
  63 union ich8_hws_flash_status {
  64         struct ich8_hsfsts {
  65                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  66                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  67                 u16 dael:1;     /* bit 2 Direct Access error Log */
  68                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  69                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  70                 u16 reserved1:2;        /* bit 13:6 Reserved */
  71                 u16 reserved2:6;        /* bit 13:6 Reserved */
  72                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  73                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  74         } hsf_status;
  75         u16 regval;
  76 };
  77
  78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  79 /* Offset 06h FLCTL */
  80 union ich8_hws_flash_ctrl {
  81         struct ich8_hsflctl {
  82                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  83                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  84                 u16 reserved:5; /* 7:3 Reserved  */
  85                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  86                 u16 flockdn:6;  /* 15:10 Reserved */
  87         } hsf_ctrl;
  88         u16 regval;
  89 };
  90
  91 /* ICH Flash Region Access Permissions */
  92 union ich8_hws_flash_regacc {
  93         struct ich8_flracc {
  94                 u32 grra:8;     /* 0:7 GbE region Read Access */
  95                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  96                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  97                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  98         } hsf_flregacc;
  99         u16 regval;
 100 };
 101
 102 /* ICH Flash Protected Region */
 103 union ich8_flash_protected_range {
 104         struct ich8_pr {
 105                 u32 base:13;    /* 0:12 Protected Range Base */
 106                 u32 reserved1:2;        /* 13:14 Reserved */
 107                 u32 rpe:1;      /* 15 Read Protection Enable */
 108                 u32 limit:13;   /* 16:28 Protected Range Limit */
 109                 u32 reserved2:2;        /* 29:30 Reserved */
 110                 u32 wpe:1;      /* 31 Write Protection Enable */
 111         } range;
 112         u32 regval;
 113 };
 114
 115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 119                                                 u32 offset, u8 byte);
 120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 121                                          u8 *data);
 122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 123                                          u16 *data);
 124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 125                                          u8 size, u16 *data);
 126 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 127                                            u32 *data);
 128 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 129                                           u32 offset, u32 *data);
 130 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 131                                             u32 offset, u32 data);
 132 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 133                                                  u32 offset, u32 dword);
 134 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 135 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 136 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 137 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 138 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 139 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 140 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 141 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 142 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 143 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 144 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 145 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 146 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 147 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 148 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 149 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 150 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 151 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 152 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
 153 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 154 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 155 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
 156 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 157 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
 158
 159 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 160 {
 161         return readw(hw->flash_address + reg);
 162 }
 163
 164 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 165 {
 166         return readl(hw->flash_address + reg);
 167 }
 168
 169 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 170 {
 171         writew(val, hw->flash_address + reg);
 172 }
 173
 174 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 175 {
 176         writel(val, hw->flash_address + reg);
 177 }
 178
 179 #define er16flash(reg)          __er16flash(hw, (reg))
 180 #define er32flash(reg)          __er32flash(hw, (reg))
 181 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 182 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 183
 184 /**
 185  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 186  *  @hw: pointer to the HW structure
 187  *
 188  *  Test access to the PHY registers by reading the PHY ID registers.  If
 189  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 190  *  otherwise assume the read PHY ID is correct if it is valid.
 191  *
 192  *  Assumes the sw/fw/hw semaphore is already acquired.
 193  **/
 194 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 195 {
 196         u16 phy_reg = 0;
 197         u32 phy_id = 0;
 198         s32 ret_val = 0;
 199         u16 retry_count;
 200         u32 mac_reg = 0;
 201
 202         for (retry_count = 0; retry_count < 2; retry_count++) {
 203                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 204                 if (ret_val || (phy_reg == 0xFFFF))
 205                         continue;
 206                 phy_id = (u32)(phy_reg << 16);
 207
 208                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 209                 if (ret_val || (phy_reg == 0xFFFF)) {
 210                         phy_id = 0;
 211                         continue;
 212                 }
 213                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 214                 break;
 215         }
 216
 217         if (hw->phy.id) {
 218                 if (hw->phy.id == phy_id)
 219                         goto out;
 220         } else if (phy_id) {
 221                 hw->phy.id = phy_id;
 222                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 223                 goto out;
 224         }
 225
 226         /* In case the PHY needs to be in mdio slow mode,
 227          * set slow mode and try to get the PHY id again.
 228          */
 229         if (hw->mac.type < e1000_pch_lpt) {
 230                 hw->phy.ops.release(hw);
 231                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 232                 if (!ret_val)
 233                         ret_val = e1000e_get_phy_id(hw);
 234                 hw->phy.ops.acquire(hw);
 235         }
 236
 237         if (ret_val)
 238                 return false;
 239 out:
 240         if ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) {
 241                 /* Only unforce SMBus if ME is not active */
 242                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 243                         /* Unforce SMBus mode in PHY */
 244                         e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 245                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 246                         e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 247
 248                         /* Unforce SMBus mode in MAC */
 249                         mac_reg = er32(CTRL_EXT);
 250                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 251                         ew32(CTRL_EXT, mac_reg);
 252                 }
 253         }
 254
 255         return true;
 256 }
 257
 258 /**
 259  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 260  *  @hw: pointer to the HW structure
 261  *
 262  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 263  *  used to reset the PHY to a quiescent state when necessary.
 264  **/
 265 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 266 {
 267         u32 mac_reg;
 268
 269         /* Set Phy Config Counter to 50msec */
 270         mac_reg = er32(FEXTNVM3);
 271         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 272         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 273         ew32(FEXTNVM3, mac_reg);
 274
 275         /* Toggle LANPHYPC Value bit */
 276         mac_reg = er32(CTRL);
 277         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 278         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 279         ew32(CTRL, mac_reg);
 280         e1e_flush();
 281         usleep_range(10, 20);
 282         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 283         ew32(CTRL, mac_reg);
 284         e1e_flush();
 285
 286         if (hw->mac.type < e1000_pch_lpt) {
 287                 msleep(50);
 288         } else {
 289                 u16 count = 20;
 290
 291                 do {
 292                         usleep_range(5000, 10000);
 293                 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
 294
 295                 msleep(30);
 296         }
 297 }
 298
 299 /**
 300  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 301  *  @hw: pointer to the HW structure
 302  *
 303  *  Workarounds/flow necessary for PHY initialization during driver load
 304  *  and resume paths.
 305  **/
 306 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 307 {
 308         struct e1000_adapter *adapter = hw->adapter;
 309         u32 mac_reg, fwsm = er32(FWSM);
 310         s32 ret_val;
 311
 312         /* Gate automatic PHY configuration by hardware on managed and
 313          * non-managed 82579 and newer adapters.
 314          */
 315         e1000_gate_hw_phy_config_ich8lan(hw, true);
 316
 317         /* It is not possible to be certain of the current state of ULP
 318          * so forcibly disable it.
 319          */
 320         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 321         e1000_disable_ulp_lpt_lp(hw, true);
 322
 323         ret_val = hw->phy.ops.acquire(hw);
 324         if (ret_val) {
 325                 e_dbg("Failed to initialize PHY flow\n");
 326                 goto out;
 327         }
 328
 329         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 330          * inaccessible and resetting the PHY is not blocked, toggle the
 331          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 332          */
 333         switch (hw->mac.type) {
 334         case e1000_pch_lpt:
 335         case e1000_pch_spt:
 336                 if (e1000_phy_is_accessible_pchlan(hw))
 337                         break;
 338
 339                 /* Before toggling LANPHYPC, see if PHY is accessible by
 340                  * forcing MAC to SMBus mode first.
 341                  */
 342                 mac_reg = er32(CTRL_EXT);
 343                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 344                 ew32(CTRL_EXT, mac_reg);
 345
 346                 /* Wait 50 milliseconds for MAC to finish any retries
 347                  * that it might be trying to perform from previous
 348                  * attempts to acknowledge any phy read requests.
 349                  */
 350                 msleep(50);
 351
 352                 /* fall-through */
 353         case e1000_pch2lan:
 354                 if (e1000_phy_is_accessible_pchlan(hw))
 355                         break;
 356
 357                 /* fall-through */
 358         case e1000_pchlan:
 359                 if ((hw->mac.type == e1000_pchlan) &&
 360                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 361                         break;
 362
 363                 if (hw->phy.ops.check_reset_block(hw)) {
 364                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 365                         ret_val = -E1000_ERR_PHY;
 366                         break;
 367                 }
 368
 369                 /* Toggle LANPHYPC Value bit */
 370                 e1000_toggle_lanphypc_pch_lpt(hw);
 371                 if (hw->mac.type >= e1000_pch_lpt) {
 372                         if (e1000_phy_is_accessible_pchlan(hw))
 373                                 break;
 374
 375                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 376                          * so ensure that the MAC is also out of SMBus mode
 377                          */
 378                         mac_reg = er32(CTRL_EXT);
 379                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 380                         ew32(CTRL_EXT, mac_reg);
 381
 382                         if (e1000_phy_is_accessible_pchlan(hw))
 383                                 break;
 384
 385                         ret_val = -E1000_ERR_PHY;
 386                 }
 387                 break;
 388         default:
 389                 break;
 390         }
 391
 392         hw->phy.ops.release(hw);
 393         if (!ret_val) {
 394
 395                 /* Check to see if able to reset PHY.  Print error if not */
 396                 if (hw->phy.ops.check_reset_block(hw)) {
 397                         e_err("Reset blocked by ME\n");
 398                         goto out;
 399                 }
 400
 401                 /* Reset the PHY before any access to it.  Doing so, ensures
 402                  * that the PHY is in a known good state before we read/write
 403                  * PHY registers.  The generic reset is sufficient here,
 404                  * because we haven't determined the PHY type yet.
 405                  */
 406                 ret_val = e1000e_phy_hw_reset_generic(hw);
 407                 if (ret_val)
 408                         goto out;
 409
 410                 /* On a successful reset, possibly need to wait for the PHY
 411                  * to quiesce to an accessible state before returning control
 412                  * to the calling function.  If the PHY does not quiesce, then
 413                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 414                  *  the PHY is in.
 415                  */
 416                 ret_val = hw->phy.ops.check_reset_block(hw);
 417                 if (ret_val)
 418                         e_err("ME blocked access to PHY after reset\n");
 419         }
 420
 421 out:
 422         /* Ungate automatic PHY configuration on non-managed 82579 */
 423         if ((hw->mac.type == e1000_pch2lan) &&
 424             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 425                 usleep_range(10000, 20000);
 426                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 427         }
 428
 429         return ret_val;
 430 }
 431
 432 /**
 433  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 434  *  @hw: pointer to the HW structure
 435  *
 436  *  Initialize family-specific PHY parameters and function pointers.
 437  **/
 438 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 439 {
 440         struct e1000_phy_info *phy = &hw->phy;
 441         s32 ret_val;
 442
 443         phy->addr = 1;
 444         phy->reset_delay_us = 100;
 445
 446         phy->ops.set_page = e1000_set_page_igp;
 447         phy->ops.read_reg = e1000_read_phy_reg_hv;
 448         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 449         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 450         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 451         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 452         phy->ops.write_reg = e1000_write_phy_reg_hv;
 453         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 454         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 455         phy->ops.power_up = e1000_power_up_phy_copper;
 456         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 457         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 458
 459         phy->id = e1000_phy_unknown;
 460
 461         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 462         if (ret_val)
 463                 return ret_val;
 464
 465         if (phy->id == e1000_phy_unknown)
 466                 switch (hw->mac.type) {
 467                 default:
 468                         ret_val = e1000e_get_phy_id(hw);
 469                         if (ret_val)
 470                                 return ret_val;
 471                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 472                                 break;
 473                         /* fall-through */
 474                 case e1000_pch2lan:
 475                 case e1000_pch_lpt:
 476                 case e1000_pch_spt:
 477                         /* In case the PHY needs to be in mdio slow mode,
 478                          * set slow mode and try to get the PHY id again.
 479                          */
 480                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 481                         if (ret_val)
 482                                 return ret_val;
 483                         ret_val = e1000e_get_phy_id(hw);
 484                         if (ret_val)
 485                                 return ret_val;
 486                         break;
 487                 }
 488         phy->type = e1000e_get_phy_type_from_id(phy->id);
 489
 490         switch (phy->type) {
 491         case e1000_phy_82577:
 492         case e1000_phy_82579:
 493         case e1000_phy_i217:
 494                 phy->ops.check_polarity = e1000_check_polarity_82577;
 495                 phy->ops.force_speed_duplex =
 496                     e1000_phy_force_speed_duplex_82577;
 497                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 498                 phy->ops.get_info = e1000_get_phy_info_82577;
 499                 phy->ops.commit = e1000e_phy_sw_reset;
 500                 break;
 501         case e1000_phy_82578:
 502                 phy->ops.check_polarity = e1000_check_polarity_m88;
 503                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 504                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 505                 phy->ops.get_info = e1000e_get_phy_info_m88;
 506                 break;
 507         default:
 508                 ret_val = -E1000_ERR_PHY;
 509                 break;
 510         }
 511
 512         return ret_val;
 513 }
 514
 515 /**
 516  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 517  *  @hw: pointer to the HW structure
 518  *
 519  *  Initialize family-specific PHY parameters and function pointers.
 520  **/
 521 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 522 {
 523         struct e1000_phy_info *phy = &hw->phy;
 524         s32 ret_val;
 525         u16 i = 0;
 526
 527         phy->addr = 1;
 528         phy->reset_delay_us = 100;
 529
 530         phy->ops.power_up = e1000_power_up_phy_copper;
 531         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 532
 533         /* We may need to do this twice - once for IGP and if that fails,
 534          * we'll set BM func pointers and try again
 535          */
 536         ret_val = e1000e_determine_phy_address(hw);
 537         if (ret_val) {
 538                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 539                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 540                 ret_val = e1000e_determine_phy_address(hw);
 541                 if (ret_val) {
 542                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 543                         return ret_val;
 544                 }
 545         }
 546
 547         phy->id = 0;
 548         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 549                (i++ < 100)) {
 550                 usleep_range(1000, 2000);
 551                 ret_val = e1000e_get_phy_id(hw);
 552                 if (ret_val)
 553                         return ret_val;
 554         }
 555
 556         /* Verify phy id */
 557         switch (phy->id) {
 558         case IGP03E1000_E_PHY_ID:
 559                 phy->type = e1000_phy_igp_3;
 560                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 561                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 562                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 563                 phy->ops.get_info = e1000e_get_phy_info_igp;
 564                 phy->ops.check_polarity = e1000_check_polarity_igp;
 565                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 566                 break;
 567         case IFE_E_PHY_ID:
 568         case IFE_PLUS_E_PHY_ID:
 569         case IFE_C_E_PHY_ID:
 570                 phy->type = e1000_phy_ife;
 571                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 572                 phy->ops.get_info = e1000_get_phy_info_ife;
 573                 phy->ops.check_polarity = e1000_check_polarity_ife;
 574                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 575                 break;
 576         case BME1000_E_PHY_ID:
 577                 phy->type = e1000_phy_bm;
 578                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 579                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 580                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 581                 phy->ops.commit = e1000e_phy_sw_reset;
 582                 phy->ops.get_info = e1000e_get_phy_info_m88;
 583                 phy->ops.check_polarity = e1000_check_polarity_m88;
 584                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 585                 break;
 586         default:
 587                 return -E1000_ERR_PHY;
 588         }
 589
 590         return 0;
 591 }
 592
 593 /**
 594  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 595  *  @hw: pointer to the HW structure
 596  *
 597  *  Initialize family-specific NVM parameters and function
 598  *  pointers.
 599  **/
 600 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 601 {
 602         struct e1000_nvm_info *nvm = &hw->nvm;
 603         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 604         u32 gfpreg, sector_base_addr, sector_end_addr;
 605         u16 i;
 606         u32 nvm_size;
 607
 608         nvm->type = e1000_nvm_flash_sw;
 609
 610         if (hw->mac.type == e1000_pch_spt) {
 611                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 612                  * STRAP register. This is because in SPT the GbE Flash region
 613                  * is no longer accessed through the flash registers. Instead,
 614                  * the mechanism has changed, and the Flash region access
 615                  * registers are now implemented in GbE memory space.
 616                  */
 617                 nvm->flash_base_addr = 0;
 618                 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
 619                     * NVM_SIZE_MULTIPLIER;
 620                 nvm->flash_bank_size = nvm_size / 2;
 621                 /* Adjust to word count */
 622                 nvm->flash_bank_size /= sizeof(u16);
 623                 /* Set the base address for flash register access */
 624                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 625         } else {
 626                 /* Can't read flash registers if register set isn't mapped. */
 627                 if (!hw->flash_address) {
 628                         e_dbg("ERROR: Flash registers not mapped\n");
 629                         return -E1000_ERR_CONFIG;
 630                 }
 631
 632                 gfpreg = er32flash(ICH_FLASH_GFPREG);
 633
 634                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 635                  * Add 1 to sector_end_addr since this sector is included in
 636                  * the overall size.
 637                  */
 638                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 639                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 640
 641                 /* flash_base_addr is byte-aligned */
 642                 nvm->flash_base_addr = sector_base_addr
 643                     << FLASH_SECTOR_ADDR_SHIFT;
 644
 645                 /* find total size of the NVM, then cut in half since the total
 646                  * size represents two separate NVM banks.
 647                  */
 648                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 649                                         << FLASH_SECTOR_ADDR_SHIFT);
 650                 nvm->flash_bank_size /= 2;
 651                 /* Adjust to word count */
 652                 nvm->flash_bank_size /= sizeof(u16);
 653         }
 654
 655         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 656
 657         /* Clear shadow ram */
 658         for (i = 0; i < nvm->word_size; i++) {
 659                 dev_spec->shadow_ram[i].modified = false;
 660                 dev_spec->shadow_ram[i].value = 0xFFFF;
 661         }
 662
 663         return 0;
 664 }
 665
 666 /**
 667  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 668  *  @hw: pointer to the HW structure
 669  *
 670  *  Initialize family-specific MAC parameters and function
 671  *  pointers.
 672  **/
 673 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 674 {
 675         struct e1000_mac_info *mac = &hw->mac;
 676
 677         /* Set media type function pointer */
 678         hw->phy.media_type = e1000_media_type_copper;
 679
 680         /* Set mta register count */
 681         mac->mta_reg_count = 32;
 682         /* Set rar entry count */
 683         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 684         if (mac->type == e1000_ich8lan)
 685                 mac->rar_entry_count--;
 686         /* FWSM register */
 687         mac->has_fwsm = true;
 688         /* ARC subsystem not supported */
 689         mac->arc_subsystem_valid = false;
 690         /* Adaptive IFS supported */
 691         mac->adaptive_ifs = true;
 692
 693         /* LED and other operations */
 694         switch (mac->type) {
 695         case e1000_ich8lan:
 696         case e1000_ich9lan:
 697         case e1000_ich10lan:
 698                 /* check management mode */
 699                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 700                 /* ID LED init */
 701                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 702                 /* blink LED */
 703                 mac->ops.blink_led = e1000e_blink_led_generic;
 704                 /* setup LED */
 705                 mac->ops.setup_led = e1000e_setup_led_generic;
 706                 /* cleanup LED */
 707                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 708                 /* turn on/off LED */
 709                 mac->ops.led_on = e1000_led_on_ich8lan;
 710                 mac->ops.led_off = e1000_led_off_ich8lan;
 711                 break;
 712         case e1000_pch2lan:
 713                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 714                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 715                 /* fall-through */
 716         case e1000_pch_lpt:
 717         case e1000_pch_spt:
 718         case e1000_pchlan:
 719                 /* check management mode */
 720                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 721                 /* ID LED init */
 722                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 723                 /* setup LED */
 724                 mac->ops.setup_led = e1000_setup_led_pchlan;
 725                 /* cleanup LED */
 726                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 727                 /* turn on/off LED */
 728                 mac->ops.led_on = e1000_led_on_pchlan;
 729                 mac->ops.led_off = e1000_led_off_pchlan;
 730                 break;
 731         default:
 732                 break;
 733         }
 734
 735         if ((mac->type == e1000_pch_lpt) || (mac->type == e1000_pch_spt)) {
 736                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 737                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 738                 mac->ops.setup_physical_interface =
 739                     e1000_setup_copper_link_pch_lpt;
 740                 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
 741         }
 742
 743         /* Enable PCS Lock-loss workaround for ICH8 */
 744         if (mac->type == e1000_ich8lan)
 745                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 746
 747         return 0;
 748 }
 749
 750 /**
 751  *  __e1000_access_emi_reg_locked - Read/write EMI register
 752  *  @hw: pointer to the HW structure
 753  *  @addr: EMI address to program
 754  *  @data: pointer to value to read/write from/to the EMI address
 755  *  @read: boolean flag to indicate read or write
 756  *
 757  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 758  **/
 759 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 760                                          u16 *data, bool read)
 761 {
 762         s32 ret_val;
 763
 764         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 765         if (ret_val)
 766                 return ret_val;
 767
 768         if (read)
 769                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 770         else
 771                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 772
 773         return ret_val;
 774 }
 775
 776 /**
 777  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 778  *  @hw: pointer to the HW structure
 779  *  @addr: EMI address to program
 780  *  @data: value to be read from the EMI address
 781  *
 782  *  Assumes the SW/FW/HW Semaphore is already acquired.
 783  **/
 784 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 785 {
 786         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 787 }
 788
 789 /**
 790  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 791  *  @hw: pointer to the HW structure
 792  *  @addr: EMI address to program
 793  *  @data: value to be written to the EMI address
 794  *
 795  *  Assumes the SW/FW/HW Semaphore is already acquired.
 796  **/
 797 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 798 {
 799         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 800 }
 801
 802 /**
 803  *  e1000_set_eee_pchlan - Enable/disable EEE support
 804  *  @hw: pointer to the HW structure
 805  *
 806  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 807  *  the link and the EEE capabilities of the link partner.  The LPI Control
 808  *  register bits will remain set only if/when link is up.
 809  *
 810  *  EEE LPI must not be asserted earlier than one second after link is up.
 811  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 812  *  can be link issues with some switches.  Other devices can have EEE LPI
 813  *  enabled immediately upon link up since they have a timer in hardware which
 814  *  prevents LPI from being asserted too early.
 815  **/
 816 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 817 {
 818         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 819         s32 ret_val;
 820         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 821
 822         switch (hw->phy.type) {
 823         case e1000_phy_82579:
 824                 lpa = I82579_EEE_LP_ABILITY;
 825                 pcs_status = I82579_EEE_PCS_STATUS;
 826                 adv_addr = I82579_EEE_ADVERTISEMENT;
 827                 break;
 828         case e1000_phy_i217:
 829                 lpa = I217_EEE_LP_ABILITY;
 830                 pcs_status = I217_EEE_PCS_STATUS;
 831                 adv_addr = I217_EEE_ADVERTISEMENT;
 832                 break;
 833         default:
 834                 return 0;
 835         }
 836
 837         ret_val = hw->phy.ops.acquire(hw);
 838         if (ret_val)
 839                 return ret_val;
 840
 841         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 842         if (ret_val)
 843                 goto release;
 844
 845         /* Clear bits that enable EEE in various speeds */
 846         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 847
 848         /* Enable EEE if not disabled by user */
 849         if (!dev_spec->eee_disable) {
 850                 /* Save off link partner's EEE ability */
 851                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 852                                                     &dev_spec->eee_lp_ability);
 853                 if (ret_val)
 854                         goto release;
 855
 856                 /* Read EEE advertisement */
 857                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 858                 if (ret_val)
 859                         goto release;
 860
 861                 /* Enable EEE only for speeds in which the link partner is
 862                  * EEE capable and for which we advertise EEE.
 863                  */
 864                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 865                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 866
 867                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 868                         e1e_rphy_locked(hw, MII_LPA, &data);
 869                         if (data & LPA_100FULL)
 870                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 871                         else
 872                                 /* EEE is not supported in 100Half, so ignore
 873                                  * partner's EEE in 100 ability if full-duplex
 874                                  * is not advertised.
 875                                  */
 876                                 dev_spec->eee_lp_ability &=
 877                                     ~I82579_EEE_100_SUPPORTED;
 878                 }
 879         }
 880
 881         if (hw->phy.type == e1000_phy_82579) {
 882                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 883                                                     &data);
 884                 if (ret_val)
 885                         goto release;
 886
 887                 data &= ~I82579_LPI_100_PLL_SHUT;
 888                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 889                                                      data);
 890         }
 891
 892         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 893         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 894         if (ret_val)
 895                 goto release;
 896
 897         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 898 release:
 899         hw->phy.ops.release(hw);
 900
 901         return ret_val;
 902 }
 903
 904 /**
 905  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 906  *  @hw:   pointer to the HW structure
 907  *  @link: link up bool flag
 908  *
 909  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 910  *  preventing further DMA write requests.  Workaround the issue by disabling
 911  *  the de-assertion of the clock request when in 1Gpbs mode.
 912  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 913  *  speeds in order to avoid Tx hangs.
 914  **/
 915 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 916 {
 917         u32 fextnvm6 = er32(FEXTNVM6);
 918         u32 status = er32(STATUS);
 919         s32 ret_val = 0;
 920         u16 reg;
 921
 922         if (link && (status & E1000_STATUS_SPEED_1000)) {
 923                 ret_val = hw->phy.ops.acquire(hw);
 924                 if (ret_val)
 925                         return ret_val;
 926
 927                 ret_val =
 928                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 929                                                 &reg);
 930                 if (ret_val)
 931                         goto release;
 932
 933                 ret_val =
 934                     e1000e_write_kmrn_reg_locked(hw,
 935                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 936                                                  reg &
 937                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 938                 if (ret_val)
 939                         goto release;
 940
 941                 usleep_range(10, 20);
 942
 943                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 944
 945                 ret_val =
 946                     e1000e_write_kmrn_reg_locked(hw,
 947                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 948                                                  reg);
 949 release:
 950                 hw->phy.ops.release(hw);
 951         } else {
 952                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 953                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 954
 955                 if ((hw->phy.revision > 5) || !link ||
 956                     ((status & E1000_STATUS_SPEED_100) &&
 957                      (status & E1000_STATUS_FD)))
 958                         goto update_fextnvm6;
 959
 960                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 961                 if (ret_val)
 962                         return ret_val;
 963
 964                 /* Clear link status transmit timeout */
 965                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 966
 967                 if (status & E1000_STATUS_SPEED_100) {
 968                         /* Set inband Tx timeout to 5x10us for 100Half */
 969                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 970
 971                         /* Do not extend the K1 entry latency for 100Half */
 972                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 973                 } else {
 974                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 975                         reg |= 50 <<
 976                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 977
 978                         /* Extend the K1 entry latency for 10 Mbps */
 979                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 980                 }
 981
 982                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 983                 if (ret_val)
 984                         return ret_val;
 985
 986 update_fextnvm6:
 987                 ew32(FEXTNVM6, fextnvm6);
 988         }
 989
 990         return ret_val;
 991 }
 992
 993 /**
 994  *  e1000_platform_pm_pch_lpt - Set platform power management values
 995  *  @hw: pointer to the HW structure
 996  *  @link: bool indicating link status
 997  *
 998  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
 999  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1000  *  when link is up (which must not exceed the maximum latency supported
1001  *  by the platform), otherwise specify there is no LTR requirement.
1002  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1003  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
1004  *  Capability register set, on this device LTR is set by writing the
1005  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1006  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1007  *  message to the PMC.
1008  **/
1009 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1010 {
1011         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1012             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1013         u16 lat_enc = 0;        /* latency encoded */
1014
1015         if (link) {
1016                 u16 speed, duplex, scale = 0;
1017                 u16 max_snoop, max_nosnoop;
1018                 u16 max_ltr_enc;        /* max LTR latency encoded */
1019                 u64 value;
1020                 u32 rxa;
1021
1022                 if (!hw->adapter->max_frame_size) {
1023                         e_dbg("max_frame_size not set.\n");
1024                         return -E1000_ERR_CONFIG;
1025                 }
1026
1027                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1028                 if (!speed) {
1029                         e_dbg("Speed not set.\n");
1030                         return -E1000_ERR_CONFIG;
1031                 }
1032
1033                 /* Rx Packet Buffer Allocation size (KB) */
1034                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1035
1036                 /* Determine the maximum latency tolerated by the device.
1037                  *
1038                  * Per the PCIe spec, the tolerated latencies are encoded as
1039                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1040                  * a 10-bit value (0-1023) to provide a range from 1 ns to
1041                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1042                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1043                  */
1044                 rxa *= 512;
1045                 value = (rxa > hw->adapter->max_frame_size) ?
1046                         (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1047                         0;
1048
1049                 while (value > PCI_LTR_VALUE_MASK) {
1050                         scale++;
1051                         value = DIV_ROUND_UP(value, (1 << 5));
1052                 }
1053                 if (scale > E1000_LTRV_SCALE_MAX) {
1054                         e_dbg("Invalid LTR latency scale %d\n", scale);
1055                         return -E1000_ERR_CONFIG;
1056                 }
1057                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1058
1059                 /* Determine the maximum latency tolerated by the platform */
1060                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1061                                      &max_snoop);
1062                 pci_read_config_word(hw->adapter->pdev,
1063                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1064                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1065
1066                 if (lat_enc > max_ltr_enc)
1067                         lat_enc = max_ltr_enc;
1068         }
1069
1070         /* Set Snoop and No-Snoop latencies the same */
1071         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1072         ew32(LTRV, reg);
1073
1074         return 0;
1075 }
1076
1077 /**
1078  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1079  *  @hw: pointer to the HW structure
1080  *  @to_sx: boolean indicating a system power state transition to Sx
1081  *
1082  *  When link is down, configure ULP mode to significantly reduce the power
1083  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1084  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1085  *  system, configure the ULP mode by software.
1086  */
1087 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1088 {
1089         u32 mac_reg;
1090         s32 ret_val = 0;
1091         u16 phy_reg;
1092         u16 oem_reg = 0;
1093
1094         if ((hw->mac.type < e1000_pch_lpt) ||
1095             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1096             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1097             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1098             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1099             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1100                 return 0;
1101
1102         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1103                 /* Request ME configure ULP mode in the PHY */
1104                 mac_reg = er32(H2ME);
1105                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1106                 ew32(H2ME, mac_reg);
1107
1108                 goto out;
1109         }
1110
1111         if (!to_sx) {
1112                 int i = 0;
1113
1114                 /* Poll up to 5 seconds for Cable Disconnected indication */
1115                 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1116                         /* Bail if link is re-acquired */
1117                         if (er32(STATUS) & E1000_STATUS_LU)
1118                                 return -E1000_ERR_PHY;
1119
1120                         if (i++ == 100)
1121                                 break;
1122
1123                         msleep(50);
1124                 }
1125                 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1126                       (er32(FEXT) &
1127                        E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1128         }
1129
1130         ret_val = hw->phy.ops.acquire(hw);
1131         if (ret_val)
1132                 goto out;
1133
1134         /* Force SMBus mode in PHY */
1135         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1136         if (ret_val)
1137                 goto release;
1138         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1139         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1140
1141         /* Force SMBus mode in MAC */
1142         mac_reg = er32(CTRL_EXT);
1143         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1144         ew32(CTRL_EXT, mac_reg);
1145
1146         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1147          * LPLU and disable Gig speed when entering ULP
1148          */
1149         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1150                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1151                                                        &oem_reg);
1152                 if (ret_val)
1153                         goto release;
1154
1155                 phy_reg = oem_reg;
1156                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1157
1158                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1159                                                         phy_reg);
1160
1161                 if (ret_val)
1162                         goto release;
1163         }
1164
1165         /* Set Inband ULP Exit, Reset to SMBus mode and
1166          * Disable SMBus Release on PERST# in PHY
1167          */
1168         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1169         if (ret_val)
1170                 goto release;
1171         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1172                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1173         if (to_sx) {
1174                 if (er32(WUFC) & E1000_WUFC_LNKC)
1175                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1176                 else
1177                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1178
1179                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1180                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1181         } else {
1182                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1183                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1184                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1185         }
1186         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1187
1188         /* Set Disable SMBus Release on PERST# in MAC */
1189         mac_reg = er32(FEXTNVM7);
1190         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1191         ew32(FEXTNVM7, mac_reg);
1192
1193         /* Commit ULP changes in PHY by starting auto ULP configuration */
1194         phy_reg |= I218_ULP_CONFIG1_START;
1195         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1196
1197         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1198             to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1199                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1200                                                         oem_reg);
1201                 if (ret_val)
1202                         goto release;
1203         }
1204
1205 release:
1206         hw->phy.ops.release(hw);
1207 out:
1208         if (ret_val)
1209                 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1210         else
1211                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1212
1213         return ret_val;
1214 }
1215
1216 /**
1217  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1218  *  @hw: pointer to the HW structure
1219  *  @force: boolean indicating whether or not to force disabling ULP
1220  *
1221  *  Un-configure ULP mode when link is up, the system is transitioned from
1222  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1223  *  system, poll for an indication from ME that ULP has been un-configured.
1224  *  If not on an ME enabled system, un-configure the ULP mode by software.
1225  *
1226  *  During nominal operation, this function is called when link is acquired
1227  *  to disable ULP mode (force=false); otherwise, for example when unloading
1228  *  the driver or during Sx->S0 transitions, this is called with force=true
1229  *  to forcibly disable ULP.
1230  */
1231 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1232 {
1233         s32 ret_val = 0;
1234         u32 mac_reg;
1235         u16 phy_reg;
1236         int i = 0;
1237
1238         if ((hw->mac.type < e1000_pch_lpt) ||
1239             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1240             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1241             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1242             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1243             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1244                 return 0;
1245
1246         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1247                 if (force) {
1248                         /* Request ME un-configure ULP mode in the PHY */
1249                         mac_reg = er32(H2ME);
1250                         mac_reg &= ~E1000_H2ME_ULP;
1251                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1252                         ew32(H2ME, mac_reg);
1253                 }
1254
1255                 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1256                 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1257                         if (i++ == 10) {
1258                                 ret_val = -E1000_ERR_PHY;
1259                                 goto out;
1260                         }
1261
1262                         usleep_range(10000, 20000);
1263                 }
1264                 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1265
1266                 if (force) {
1267                         mac_reg = er32(H2ME);
1268                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1269                         ew32(H2ME, mac_reg);
1270                 } else {
1271                         /* Clear H2ME.ULP after ME ULP configuration */
1272                         mac_reg = er32(H2ME);
1273                         mac_reg &= ~E1000_H2ME_ULP;
1274                         ew32(H2ME, mac_reg);
1275                 }
1276
1277                 goto out;
1278         }
1279
1280         ret_val = hw->phy.ops.acquire(hw);
1281         if (ret_val)
1282                 goto out;
1283
1284         if (force)
1285                 /* Toggle LANPHYPC Value bit */
1286                 e1000_toggle_lanphypc_pch_lpt(hw);
1287
1288         /* Unforce SMBus mode in PHY */
1289         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1290         if (ret_val) {
1291                 /* The MAC might be in PCIe mode, so temporarily force to
1292                  * SMBus mode in order to access the PHY.
1293                  */
1294                 mac_reg = er32(CTRL_EXT);
1295                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1296                 ew32(CTRL_EXT, mac_reg);
1297
1298                 msleep(50);
1299
1300                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1301                                                        &phy_reg);
1302                 if (ret_val)
1303                         goto release;
1304         }
1305         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1306         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1307
1308         /* Unforce SMBus mode in MAC */
1309         mac_reg = er32(CTRL_EXT);
1310         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1311         ew32(CTRL_EXT, mac_reg);
1312
1313         /* When ULP mode was previously entered, K1 was disabled by the
1314          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1315          */
1316         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1317         if (ret_val)
1318                 goto release;
1319         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1320         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1321
1322         /* Clear ULP enabled configuration */
1323         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1324         if (ret_val)
1325                 goto release;
1326         phy_reg &= ~(I218_ULP_CONFIG1_IND |
1327                      I218_ULP_CONFIG1_STICKY_ULP |
1328                      I218_ULP_CONFIG1_RESET_TO_SMBUS |
1329                      I218_ULP_CONFIG1_WOL_HOST |
1330                      I218_ULP_CONFIG1_INBAND_EXIT |
1331                      I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1332         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1333
1334         /* Commit ULP changes by starting auto ULP configuration */
1335         phy_reg |= I218_ULP_CONFIG1_START;
1336         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1337
1338         /* Clear Disable SMBus Release on PERST# in MAC */
1339         mac_reg = er32(FEXTNVM7);
1340         mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1341         ew32(FEXTNVM7, mac_reg);
1342
1343 release:
1344         hw->phy.ops.release(hw);
1345         if (force) {
1346                 e1000_phy_hw_reset(hw);
1347                 msleep(50);
1348         }
1349 out:
1350         if (ret_val)
1351                 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1352         else
1353                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1354
1355         return ret_val;
1356 }
1357
1358 /**
1359  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1360  *  @hw: pointer to the HW structure
1361  *
1362  *  Checks to see of the link status of the hardware has changed.  If a
1363  *  change in link status has been detected, then we read the PHY registers
1364  *  to get the current speed/duplex if link exists.
1365  **/
1366 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1367 {
1368         struct e1000_mac_info *mac = &hw->mac;
1369         s32 ret_val, tipg_reg = 0;
1370         u16 emi_addr, emi_val = 0;
1371         bool link;
1372         u16 phy_reg;
1373
1374         /* We only want to go out to the PHY registers to see if Auto-Neg
1375          * has completed and/or if our link status has changed.  The
1376          * get_link_status flag is set upon receiving a Link Status
1377          * Change or Rx Sequence Error interrupt.
1378          */
1379         if (!mac->get_link_status)
1380                 return 0;
1381
1382         /* First we want to see if the MII Status Register reports
1383          * link.  If so, then we want to get the current speed/duplex
1384          * of the PHY.
1385          */
1386         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1387         if (ret_val)
1388                 return ret_val;
1389
1390         if (hw->mac.type == e1000_pchlan) {
1391                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1392                 if (ret_val)
1393                         return ret_val;
1394         }
1395
1396         /* When connected at 10Mbps half-duplex, some parts are excessively
1397          * aggressive resulting in many collisions. To avoid this, increase
1398          * the IPG and reduce Rx latency in the PHY.
1399          */
1400         if (((hw->mac.type == e1000_pch2lan) ||
1401              (hw->mac.type == e1000_pch_lpt) ||
1402              (hw->mac.type == e1000_pch_spt)) && link) {
1403                 u16 speed, duplex;
1404
1405                 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1406                 tipg_reg = er32(TIPG);
1407                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1408
1409                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1410                         tipg_reg |= 0xFF;
1411                         /* Reduce Rx latency in analog PHY */
1412                         emi_val = 0;
1413                 } else if (hw->mac.type == e1000_pch_spt &&
1414                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1415                         tipg_reg |= 0xC;
1416                         emi_val = 1;
1417                 } else {
1418
1419                         /* Roll back the default values */
1420                         tipg_reg |= 0x08;
1421                         emi_val = 1;
1422                 }
1423
1424                 ew32(TIPG, tipg_reg);
1425
1426                 ret_val = hw->phy.ops.acquire(hw);
1427                 if (ret_val)
1428                         return ret_val;
1429
1430                 if (hw->mac.type == e1000_pch2lan)
1431                         emi_addr = I82579_RX_CONFIG;
1432                 else
1433                         emi_addr = I217_RX_CONFIG;
1434                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1435
1436                 hw->phy.ops.release(hw);
1437
1438                 if (ret_val)
1439                         return ret_val;
1440
1441                 if (hw->mac.type == e1000_pch_spt) {
1442                         u16 data;
1443                         u16 ptr_gap;
1444
1445                         if (speed == SPEED_1000) {
1446                                 ret_val = hw->phy.ops.acquire(hw);
1447                                 if (ret_val)
1448                                         return ret_val;
1449
1450                                 ret_val = e1e_rphy_locked(hw,
1451                                                           PHY_REG(776, 20),
1452                                                           &data);
1453                                 if (ret_val) {
1454                                         hw->phy.ops.release(hw);
1455                                         return ret_val;
1456                                 }
1457
1458                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1459                                 if (ptr_gap < 0x18) {
1460                                         data &= ~(0x3FF << 2);
1461                                         data |= (0x18 << 2);
1462                                         ret_val =
1463                                             e1e_wphy_locked(hw,
1464                                                             PHY_REG(776, 20),
1465                                                             data);
1466                                 }
1467                                 hw->phy.ops.release(hw);
1468                                 if (ret_val)
1469                                         return ret_val;
1470                         }
1471                 }
1472         }
1473
1474         /* I217 Packet Loss issue:
1475          * ensure that FEXTNVM4 Beacon Duration is set correctly
1476          * on power up.
1477          * Set the Beacon Duration for I217 to 8 usec
1478          */
1479         if ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) {
1480                 u32 mac_reg;
1481
1482                 mac_reg = er32(FEXTNVM4);
1483                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1484                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1485                 ew32(FEXTNVM4, mac_reg);
1486         }
1487
1488         /* Work-around I218 hang issue */
1489         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1490             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1491             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1492             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1493                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1494                 if (ret_val)
1495                         return ret_val;
1496         }
1497         if ((hw->mac.type == e1000_pch_lpt) ||
1498             (hw->mac.type == e1000_pch_spt)) {
1499                 /* Set platform power management values for
1500                  * Latency Tolerance Reporting (LTR)
1501                  */
1502                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1503                 if (ret_val)
1504                         return ret_val;
1505         }
1506
1507         /* Clear link partner's EEE ability */
1508         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1509
1510         /* FEXTNVM6 K1-off workaround */
1511         if (hw->mac.type == e1000_pch_spt) {
1512                 u32 pcieanacfg = er32(PCIEANACFG);
1513                 u32 fextnvm6 = er32(FEXTNVM6);
1514
1515                 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1516                         fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1517                 else
1518                         fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1519
1520                 ew32(FEXTNVM6, fextnvm6);
1521         }
1522
1523         if (!link)
1524                 return 0;       /* No link detected */
1525
1526         mac->get_link_status = false;
1527
1528         switch (hw->mac.type) {
1529         case e1000_pch2lan:
1530                 ret_val = e1000_k1_workaround_lv(hw);
1531                 if (ret_val)
1532                         return ret_val;
1533                 /* fall-thru */
1534         case e1000_pchlan:
1535                 if (hw->phy.type == e1000_phy_82578) {
1536                         ret_val = e1000_link_stall_workaround_hv(hw);
1537                         if (ret_val)
1538                                 return ret_val;
1539                 }
1540
1541                 /* Workaround for PCHx parts in half-duplex:
1542                  * Set the number of preambles removed from the packet
1543                  * when it is passed from the PHY to the MAC to prevent
1544                  * the MAC from misinterpreting the packet type.
1545                  */
1546                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1547                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1548
1549                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1550                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1551
1552                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1553                 break;
1554         default:
1555                 break;
1556         }
1557
1558         /* Check if there was DownShift, must be checked
1559          * immediately after link-up
1560          */
1561         e1000e_check_downshift(hw);
1562
1563         /* Enable/Disable EEE after link up */
1564         if (hw->phy.type > e1000_phy_82579) {
1565                 ret_val = e1000_set_eee_pchlan(hw);
1566                 if (ret_val)
1567                         return ret_val;
1568         }
1569
1570         /* If we are forcing speed/duplex, then we simply return since
1571          * we have already determined whether we have link or not.
1572          */
1573         if (!mac->autoneg)
1574                 return -E1000_ERR_CONFIG;
1575
1576         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1577          * of MAC speed/duplex configuration.  So we only need to
1578          * configure Collision Distance in the MAC.
1579          */
1580         mac->ops.config_collision_dist(hw);
1581
1582         /* Configure Flow Control now that Auto-Neg has completed.
1583          * First, we need to restore the desired flow control
1584          * settings because we may have had to re-autoneg with a
1585          * different link partner.
1586          */
1587         ret_val = e1000e_config_fc_after_link_up(hw);
1588         if (ret_val)
1589                 e_dbg("Error configuring flow control\n");
1590
1591         return ret_val;
1592 }
1593
1594 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1595 {
1596         struct e1000_hw *hw = &adapter->hw;
1597         s32 rc;
1598
1599         rc = e1000_init_mac_params_ich8lan(hw);
1600         if (rc)
1601                 return rc;
1602
1603         rc = e1000_init_nvm_params_ich8lan(hw);
1604         if (rc)
1605                 return rc;
1606
1607         switch (hw->mac.type) {
1608         case e1000_ich8lan:
1609         case e1000_ich9lan:
1610         case e1000_ich10lan:
1611                 rc = e1000_init_phy_params_ich8lan(hw);
1612                 break;
1613         case e1000_pchlan:
1614         case e1000_pch2lan:
1615         case e1000_pch_lpt:
1616         case e1000_pch_spt:
1617                 rc = e1000_init_phy_params_pchlan(hw);
1618                 break;
1619         default:
1620                 break;
1621         }
1622         if (rc)
1623                 return rc;
1624
1625         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1626          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1627          */
1628         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1629             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1630              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1631                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1632                 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1633
1634                 hw->mac.ops.blink_led = NULL;
1635         }
1636
1637         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1638             (adapter->hw.phy.type != e1000_phy_ife))
1639                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1640
1641         /* Enable workaround for 82579 w/ ME enabled */
1642         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1643             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1644                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1645
1646         return 0;
1647 }
1648
1649 static DEFINE_MUTEX(nvm_mutex);
1650
1651 /**
1652  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1653  *  @hw: pointer to the HW structure
1654  *
1655  *  Acquires the mutex for performing NVM operations.
1656  **/
1657 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1658 {
1659         mutex_lock(&nvm_mutex);
1660
1661         return 0;
1662 }
1663
1664 /**
1665  *  e1000_release_nvm_ich8lan - Release NVM mutex
1666  *  @hw: pointer to the HW structure
1667  *
1668  *  Releases the mutex used while performing NVM operations.
1669  **/
1670 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1671 {
1672         mutex_unlock(&nvm_mutex);
1673 }
1674
1675 /**
1676  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1677  *  @hw: pointer to the HW structure
1678  *
1679  *  Acquires the software control flag for performing PHY and select
1680  *  MAC CSR accesses.
1681  **/
1682 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1683 {
1684         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1685         s32 ret_val = 0;
1686
1687         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1688                              &hw->adapter->state)) {
1689                 e_dbg("contention for Phy access\n");
1690                 return -E1000_ERR_PHY;
1691         }
1692
1693         while (timeout) {
1694                 extcnf_ctrl = er32(EXTCNF_CTRL);
1695                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1696                         break;
1697
1698                 mdelay(1);
1699                 timeout--;
1700         }
1701
1702         if (!timeout) {
1703                 e_dbg("SW has already locked the resource.\n");
1704                 ret_val = -E1000_ERR_CONFIG;
1705                 goto out;
1706         }
1707
1708         timeout = SW_FLAG_TIMEOUT;
1709
1710         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1711         ew32(EXTCNF_CTRL, extcnf_ctrl);
1712
1713         while (timeout) {
1714                 extcnf_ctrl = er32(EXTCNF_CTRL);
1715                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1716                         break;
1717
1718                 mdelay(1);
1719                 timeout--;
1720         }
1721
1722         if (!timeout) {
1723                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1724                       er32(FWSM), extcnf_ctrl);
1725                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1726                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1727                 ret_val = -E1000_ERR_CONFIG;
1728                 goto out;
1729         }
1730
1731 out:
1732         if (ret_val)
1733                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1734
1735         return ret_val;
1736 }
1737
1738 /**
1739  *  e1000_release_swflag_ich8lan - Release software control flag
1740  *  @hw: pointer to the HW structure
1741  *
1742  *  Releases the software control flag for performing PHY and select
1743  *  MAC CSR accesses.
1744  **/
1745 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1746 {
1747         u32 extcnf_ctrl;
1748
1749         extcnf_ctrl = er32(EXTCNF_CTRL);
1750
1751         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1752                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1753                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1754         } else {
1755                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1756         }
1757
1758         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1759 }
1760
1761 /**
1762  *  e1000_check_mng_mode_ich8lan - Checks management mode
1763  *  @hw: pointer to the HW structure
1764  *
1765  *  This checks if the adapter has any manageability enabled.
1766  *  This is a function pointer entry point only called by read/write
1767  *  routines for the PHY and NVM parts.
1768  **/
1769 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1770 {
1771         u32 fwsm;
1772
1773         fwsm = er32(FWSM);
1774         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1775                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1776                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1777 }
1778
1779 /**
1780  *  e1000_check_mng_mode_pchlan - Checks management mode
1781  *  @hw: pointer to the HW structure
1782  *
1783  *  This checks if the adapter has iAMT enabled.
1784  *  This is a function pointer entry point only called by read/write
1785  *  routines for the PHY and NVM parts.
1786  **/
1787 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1788 {
1789         u32 fwsm;
1790
1791         fwsm = er32(FWSM);
1792         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1793             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1794 }
1795
1796 /**
1797  *  e1000_rar_set_pch2lan - Set receive address register
1798  *  @hw: pointer to the HW structure
1799  *  @addr: pointer to the receive address
1800  *  @index: receive address array register
1801  *
1802  *  Sets the receive address array register at index to the address passed
1803  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1804  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1805  *  Use SHRA[0-3] in place of those reserved for ME.
1806  **/
1807 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1808 {
1809         u32 rar_low, rar_high;
1810
1811         /* HW expects these in little endian so we reverse the byte order
1812          * from network order (big endian) to little endian
1813          */
1814         rar_low = ((u32)addr[0] |
1815                    ((u32)addr[1] << 8) |
1816                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1817
1818         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1819
1820         /* If MAC address zero, no need to set the AV bit */
1821         if (rar_low || rar_high)
1822                 rar_high |= E1000_RAH_AV;
1823
1824         if (index == 0) {
1825                 ew32(RAL(index), rar_low);
1826                 e1e_flush();
1827                 ew32(RAH(index), rar_high);
1828                 e1e_flush();
1829                 return 0;
1830         }
1831
1832         /* RAR[1-6] are owned by manageability.  Skip those and program the
1833          * next address into the SHRA register array.
1834          */
1835         if (index < (u32)(hw->mac.rar_entry_count)) {
1836                 s32 ret_val;
1837
1838                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1839                 if (ret_val)
1840                         goto out;
1841
1842                 ew32(SHRAL(index - 1), rar_low);
1843                 e1e_flush();
1844                 ew32(SHRAH(index - 1), rar_high);
1845                 e1e_flush();
1846
1847                 e1000_release_swflag_ich8lan(hw);
1848
1849                 /* verify the register updates */
1850                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1851                     (er32(SHRAH(index - 1)) == rar_high))
1852                         return 0;
1853
1854                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1855                       (index - 1), er32(FWSM));
1856         }
1857
1858 out:
1859         e_dbg("Failed to write receive address at index %d\n", index);
1860         return -E1000_ERR_CONFIG;
1861 }
1862
1863 /**
1864  *  e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1865  *  @hw: pointer to the HW structure
1866  *
1867  *  Get the number of available receive registers that the Host can
1868  *  program. SHRA[0-10] are the shared receive address registers
1869  *  that are shared between the Host and manageability engine (ME).
1870  *  ME can reserve any number of addresses and the host needs to be
1871  *  able to tell how many available registers it has access to.
1872  **/
1873 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1874 {
1875         u32 wlock_mac;
1876         u32 num_entries;
1877
1878         wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1879         wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1880
1881         switch (wlock_mac) {
1882         case 0:
1883                 /* All SHRA[0..10] and RAR[0] available */
1884                 num_entries = hw->mac.rar_entry_count;
1885                 break;
1886         case 1:
1887                 /* Only RAR[0] available */
1888                 num_entries = 1;
1889                 break;
1890         default:
1891                 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1892                 num_entries = wlock_mac + 1;
1893                 break;
1894         }
1895
1896         return num_entries;
1897 }
1898
1899 /**
1900  *  e1000_rar_set_pch_lpt - Set receive address registers
1901  *  @hw: pointer to the HW structure
1902  *  @addr: pointer to the receive address
1903  *  @index: receive address array register
1904  *
1905  *  Sets the receive address register array at index to the address passed
1906  *  in by addr. For LPT, RAR[0] is the base address register that is to
1907  *  contain the MAC address. SHRA[0-10] are the shared receive address
1908  *  registers that are shared between the Host and manageability engine (ME).
1909  **/
1910 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1911 {
1912         u32 rar_low, rar_high;
1913         u32 wlock_mac;
1914
1915         /* HW expects these in little endian so we reverse the byte order
1916          * from network order (big endian) to little endian
1917          */
1918         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1919                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1920
1921         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1922
1923         /* If MAC address zero, no need to set the AV bit */
1924         if (rar_low || rar_high)
1925                 rar_high |= E1000_RAH_AV;
1926
1927         if (index == 0) {
1928                 ew32(RAL(index), rar_low);
1929                 e1e_flush();
1930                 ew32(RAH(index), rar_high);
1931                 e1e_flush();
1932                 return 0;
1933         }
1934
1935         /* The manageability engine (ME) can lock certain SHRAR registers that
1936          * it is using - those registers are unavailable for use.
1937          */
1938         if (index < hw->mac.rar_entry_count) {
1939                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1940                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1941
1942                 /* Check if all SHRAR registers are locked */
1943                 if (wlock_mac == 1)
1944                         goto out;
1945
1946                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1947                         s32 ret_val;
1948
1949                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1950
1951                         if (ret_val)
1952                                 goto out;
1953
1954                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1955                         e1e_flush();
1956                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1957                         e1e_flush();
1958
1959                         e1000_release_swflag_ich8lan(hw);
1960
1961                         /* verify the register updates */
1962                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1963                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1964                                 return 0;
1965                 }
1966         }
1967
1968 out:
1969         e_dbg("Failed to write receive address at index %d\n", index);
1970         return -E1000_ERR_CONFIG;
1971 }
1972
1973 /**
1974  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1975  *  @hw: pointer to the HW structure
1976  *
1977  *  Checks if firmware is blocking the reset of the PHY.
1978  *  This is a function pointer entry point only called by
1979  *  reset routines.
1980  **/
1981 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1982 {
1983         bool blocked = false;
1984         int i = 0;
1985
1986         while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
1987                (i++ < 10))
1988                 usleep_range(10000, 20000);
1989         return blocked ? E1000_BLK_PHY_RESET : 0;
1990 }
1991
1992 /**
1993  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1994  *  @hw: pointer to the HW structure
1995  *
1996  *  Assumes semaphore already acquired.
1997  *
1998  **/
1999 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2000 {
2001         u16 phy_data;
2002         u32 strap = er32(STRAP);
2003         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2004             E1000_STRAP_SMT_FREQ_SHIFT;
2005         s32 ret_val;
2006
2007         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2008
2009         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2010         if (ret_val)
2011                 return ret_val;
2012
2013         phy_data &= ~HV_SMB_ADDR_MASK;
2014         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2015         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2016
2017         if (hw->phy.type == e1000_phy_i217) {
2018                 /* Restore SMBus frequency */
2019                 if (freq--) {
2020                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2021                         phy_data |= (freq & (1 << 0)) <<
2022                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
2023                         phy_data |= (freq & (1 << 1)) <<
2024                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2025                 } else {
2026                         e_dbg("Unsupported SMB frequency in PHY\n");
2027                 }
2028         }
2029
2030         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2031 }
2032
2033 /**
2034  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2035  *  @hw:   pointer to the HW structure
2036  *
2037  *  SW should configure the LCD from the NVM extended configuration region
2038  *  as a workaround for certain parts.
2039  **/
2040 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2041 {
2042         struct e1000_phy_info *phy = &hw->phy;
2043         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2044         s32 ret_val = 0;
2045         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2046
2047         /* Initialize the PHY from the NVM on ICH platforms.  This
2048          * is needed due to an issue where the NVM configuration is
2049          * not properly autoloaded after power transitions.
2050          * Therefore, after each PHY reset, we will load the
2051          * configuration data out of the NVM manually.
2052          */
2053         switch (hw->mac.type) {
2054         case e1000_ich8lan:
2055                 if (phy->type != e1000_phy_igp_3)
2056                         return ret_val;
2057
2058                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2059                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2060                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2061                         break;
2062                 }
2063                 /* Fall-thru */
2064         case e1000_pchlan:
2065         case e1000_pch2lan:
2066         case e1000_pch_lpt:
2067         case e1000_pch_spt:
2068                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2069                 break;
2070         default:
2071                 return ret_val;
2072         }
2073
2074         ret_val = hw->phy.ops.acquire(hw);
2075         if (ret_val)
2076                 return ret_val;
2077
2078         data = er32(FEXTNVM);
2079         if (!(data & sw_cfg_mask))
2080                 goto release;
2081
2082         /* Make sure HW does not configure LCD from PHY
2083          * extended configuration before SW configuration
2084          */
2085         data = er32(EXTCNF_CTRL);
2086         if ((hw->mac.type < e1000_pch2lan) &&
2087             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2088                 goto release;
2089
2090         cnf_size = er32(EXTCNF_SIZE);
2091         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2092         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2093         if (!cnf_size)
2094                 goto release;
2095
2096         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2097         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2098
2099         if (((hw->mac.type == e1000_pchlan) &&
2100              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2101             (hw->mac.type > e1000_pchlan)) {
2102                 /* HW configures the SMBus address and LEDs when the
2103                  * OEM and LCD Write Enable bits are set in the NVM.
2104                  * When both NVM bits are cleared, SW will configure
2105                  * them instead.
2106                  */
2107                 ret_val = e1000_write_smbus_addr(hw);
2108                 if (ret_val)
2109                         goto release;
2110
2111                 data = er32(LEDCTL);
2112                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2113                                                         (u16)data);
2114                 if (ret_val)
2115                         goto release;
2116         }
2117
2118         /* Configure LCD from extended configuration region. */
2119
2120         /* cnf_base_addr is in DWORD */
2121         word_addr = (u16)(cnf_base_addr << 1);
2122
2123         for (i = 0; i < cnf_size; i++) {
2124                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
2125                 if (ret_val)
2126                         goto release;
2127
2128                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2129                                          1, &reg_addr);
2130                 if (ret_val)
2131                         goto release;
2132
2133                 /* Save off the PHY page for future writes. */
2134                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2135                         phy_page = reg_data;
2136                         continue;
2137                 }
2138
2139                 reg_addr &= PHY_REG_MASK;
2140                 reg_addr |= phy_page;
2141
2142                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2143                 if (ret_val)
2144                         goto release;
2145         }
2146
2147 release:
2148         hw->phy.ops.release(hw);
2149         return ret_val;
2150 }
2151
2152 /**
2153  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2154  *  @hw:   pointer to the HW structure
2155  *  @link: link up bool flag
2156  *
2157  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2158  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2159  *  If link is down, the function will restore the default K1 setting located
2160  *  in the NVM.
2161  **/
2162 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2163 {
2164         s32 ret_val = 0;
2165         u16 status_reg = 0;
2166         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2167
2168         if (hw->mac.type != e1000_pchlan)
2169                 return 0;
2170
2171         /* Wrap the whole flow with the sw flag */
2172         ret_val = hw->phy.ops.acquire(hw);
2173         if (ret_val)
2174                 return ret_val;
2175
2176         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2177         if (link) {
2178                 if (hw->phy.type == e1000_phy_82578) {
2179                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2180                                                   &status_reg);
2181                         if (ret_val)
2182                                 goto release;
2183
2184                         status_reg &= (BM_CS_STATUS_LINK_UP |
2185                                        BM_CS_STATUS_RESOLVED |
2186                                        BM_CS_STATUS_SPEED_MASK);
2187
2188                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2189                                            BM_CS_STATUS_RESOLVED |
2190                                            BM_CS_STATUS_SPEED_1000))
2191                                 k1_enable = false;
2192                 }
2193
2194                 if (hw->phy.type == e1000_phy_82577) {
2195                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2196                         if (ret_val)
2197                                 goto release;
2198
2199                         status_reg &= (HV_M_STATUS_LINK_UP |
2200                                        HV_M_STATUS_AUTONEG_COMPLETE |
2201                                        HV_M_STATUS_SPEED_MASK);
2202
2203                         if (status_reg == (HV_M_STATUS_LINK_UP |
2204                                            HV_M_STATUS_AUTONEG_COMPLETE |
2205                                            HV_M_STATUS_SPEED_1000))
2206                                 k1_enable = false;
2207                 }
2208
2209                 /* Link stall fix for link up */
2210                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2211                 if (ret_val)
2212                         goto release;
2213
2214         } else {
2215                 /* Link stall fix for link down */
2216                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2217                 if (ret_val)
2218                         goto release;
2219         }
2220
2221         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2222
2223 release:
2224         hw->phy.ops.release(hw);
2225
2226         return ret_val;
2227 }
2228
2229 /**
2230  *  e1000_configure_k1_ich8lan - Configure K1 power state
2231  *  @hw: pointer to the HW structure
2232  *  @enable: K1 state to configure
2233  *
2234  *  Configure the K1 power state based on the provided parameter.
2235  *  Assumes semaphore already acquired.
2236  *
2237  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2238  **/
2239 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2240 {
2241         s32 ret_val;
2242         u32 ctrl_reg = 0;
2243         u32 ctrl_ext = 0;
2244         u32 reg = 0;
2245         u16 kmrn_reg = 0;
2246
2247         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2248                                               &kmrn_reg);
2249         if (ret_val)
2250                 return ret_val;
2251
2252         if (k1_enable)
2253                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2254         else
2255                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2256
2257         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2258                                                kmrn_reg);
2259         if (ret_val)
2260                 return ret_val;
2261
2262         usleep_range(20, 40);
2263         ctrl_ext = er32(CTRL_EXT);
2264         ctrl_reg = er32(CTRL);
2265
2266         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2267         reg |= E1000_CTRL_FRCSPD;
2268         ew32(CTRL, reg);
2269
2270         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2271         e1e_flush();
2272         usleep_range(20, 40);
2273         ew32(CTRL, ctrl_reg);
2274         ew32(CTRL_EXT, ctrl_ext);
2275         e1e_flush();
2276         usleep_range(20, 40);
2277
2278         return 0;
2279 }
2280
2281 /**
2282  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2283  *  @hw:       pointer to the HW structure
2284  *  @d0_state: boolean if entering d0 or d3 device state
2285  *
2286  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2287  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2288  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2289  **/
2290 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2291 {
2292         s32 ret_val = 0;
2293         u32 mac_reg;
2294         u16 oem_reg;
2295
2296         if (hw->mac.type < e1000_pchlan)
2297                 return ret_val;
2298
2299         ret_val = hw->phy.ops.acquire(hw);
2300         if (ret_val)
2301                 return ret_val;
2302
2303         if (hw->mac.type == e1000_pchlan) {
2304                 mac_reg = er32(EXTCNF_CTRL);
2305                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2306                         goto release;
2307         }
2308
2309         mac_reg = er32(FEXTNVM);
2310         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2311                 goto release;
2312
2313         mac_reg = er32(PHY_CTRL);
2314
2315         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2316         if (ret_val)
2317                 goto release;
2318
2319         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2320
2321         if (d0_state) {
2322                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2323                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2324
2325                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2326                         oem_reg |= HV_OEM_BITS_LPLU;
2327         } else {
2328                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2329                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2330                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2331
2332                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2333                                E1000_PHY_CTRL_NOND0A_LPLU))
2334                         oem_reg |= HV_OEM_BITS_LPLU;
2335         }
2336
2337         /* Set Restart auto-neg to activate the bits */
2338         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2339             !hw->phy.ops.check_reset_block(hw))
2340                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2341
2342         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2343
2344 release:
2345         hw->phy.ops.release(hw);
2346
2347         return ret_val;
2348 }
2349
2350 /**
2351  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2352  *  @hw:   pointer to the HW structure
2353  **/
2354 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2355 {
2356         s32 ret_val;
2357         u16 data;
2358
2359         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2360         if (ret_val)
2361                 return ret_val;
2362
2363         data |= HV_KMRN_MDIO_SLOW;
2364
2365         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2366
2367         return ret_val;
2368 }
2369
2370 /**
2371  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2372  *  done after every PHY reset.
2373  **/
2374 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2375 {
2376         s32 ret_val = 0;
2377         u16 phy_data;
2378
2379         if (hw->mac.type != e1000_pchlan)
2380                 return 0;
2381
2382         /* Set MDIO slow mode before any other MDIO access */
2383         if (hw->phy.type == e1000_phy_82577) {
2384                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2385                 if (ret_val)
2386                         return ret_val;
2387         }
2388
2389         if (((hw->phy.type == e1000_phy_82577) &&
2390              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2391             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2392                 /* Disable generation of early preamble */
2393                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2394                 if (ret_val)
2395                         return ret_val;
2396
2397                 /* Preamble tuning for SSC */
2398                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2399                 if (ret_val)
2400                         return ret_val;
2401         }
2402
2403         if (hw->phy.type == e1000_phy_82578) {
2404                 /* Return registers to default by doing a soft reset then
2405                  * writing 0x3140 to the control register.
2406                  */
2407                 if (hw->phy.revision < 2) {
2408                         e1000e_phy_sw_reset(hw);
2409                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2410                 }
2411         }
2412
2413         /* Select page 0 */
2414         ret_val = hw->phy.ops.acquire(hw);
2415         if (ret_val)
2416                 return ret_val;
2417
2418         hw->phy.addr = 1;
2419         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2420         hw->phy.ops.release(hw);
2421         if (ret_val)
2422                 return ret_val;
2423
2424         /* Configure the K1 Si workaround during phy reset assuming there is
2425          * link so that it disables K1 if link is in 1Gbps.
2426          */
2427         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2428         if (ret_val)
2429                 return ret_val;
2430
2431         /* Workaround for link disconnects on a busy hub in half duplex */
2432         ret_val = hw->phy.ops.acquire(hw);
2433         if (ret_val)
2434                 return ret_val;
2435         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2436         if (ret_val)
2437                 goto release;
2438         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2439         if (ret_val)
2440                 goto release;
2441
2442         /* set MSE higher to enable link to stay up when noise is high */
2443         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2444 release:
2445         hw->phy.ops.release(hw);
2446
2447         return ret_val;
2448 }
2449
2450 /**
2451  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2452  *  @hw:   pointer to the HW structure
2453  **/
2454 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2455 {
2456         u32 mac_reg;
2457         u16 i, phy_reg = 0;
2458         s32 ret_val;
2459
2460         ret_val = hw->phy.ops.acquire(hw);
2461         if (ret_val)
2462                 return;
2463         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2464         if (ret_val)
2465                 goto release;
2466
2467         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2468         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2469                 mac_reg = er32(RAL(i));
2470                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2471                                            (u16)(mac_reg & 0xFFFF));
2472                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2473                                            (u16)((mac_reg >> 16) & 0xFFFF));
2474
2475                 mac_reg = er32(RAH(i));
2476                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2477                                            (u16)(mac_reg & 0xFFFF));
2478                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2479                                            (u16)((mac_reg & E1000_RAH_AV)
2480                                                  >> 16));
2481         }
2482
2483         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2484
2485 release:
2486         hw->phy.ops.release(hw);
2487 }
2488
2489 /**
2490  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2491  *  with 82579 PHY
2492  *  @hw: pointer to the HW structure
2493  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2494  **/
2495 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2496 {
2497         s32 ret_val = 0;
2498         u16 phy_reg, data;
2499         u32 mac_reg;
2500         u16 i;
2501
2502         if (hw->mac.type < e1000_pch2lan)
2503                 return 0;
2504
2505         /* disable Rx path while enabling/disabling workaround */
2506         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2507         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
2508         if (ret_val)
2509                 return ret_val;
2510
2511         if (enable) {
2512                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2513                  * SHRAL/H) and initial CRC values to the MAC
2514                  */
2515                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2516                         u8 mac_addr[ETH_ALEN] = { 0 };
2517                         u32 addr_high, addr_low;
2518
2519                         addr_high = er32(RAH(i));
2520                         if (!(addr_high & E1000_RAH_AV))
2521                                 continue;
2522                         addr_low = er32(RAL(i));
2523                         mac_addr[0] = (addr_low & 0xFF);
2524                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2525                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2526                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2527                         mac_addr[4] = (addr_high & 0xFF);
2528                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2529
2530                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2531                 }
2532
2533                 /* Write Rx addresses to the PHY */
2534                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2535
2536                 /* Enable jumbo frame workaround in the MAC */
2537                 mac_reg = er32(FFLT_DBG);
2538                 mac_reg &= ~(1 << 14);
2539                 mac_reg |= (7 << 15);
2540                 ew32(FFLT_DBG, mac_reg);
2541
2542                 mac_reg = er32(RCTL);
2543                 mac_reg |= E1000_RCTL_SECRC;
2544                 ew32(RCTL, mac_reg);
2545
2546                 ret_val = e1000e_read_kmrn_reg(hw,
2547                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2548                                                &data);
2549                 if (ret_val)
2550                         return ret_val;
2551                 ret_val = e1000e_write_kmrn_reg(hw,
2552                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2553                                                 data | (1 << 0));
2554                 if (ret_val)
2555                         return ret_val;
2556                 ret_val = e1000e_read_kmrn_reg(hw,
2557                                                E1000_KMRNCTRLSTA_HD_CTRL,
2558                                                &data);
2559                 if (ret_val)
2560                         return ret_val;
2561                 data &= ~(0xF << 8);
2562                 data |= (0xB << 8);
2563                 ret_val = e1000e_write_kmrn_reg(hw,
2564                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2565                                                 data);
2566                 if (ret_val)
2567                         return ret_val;
2568
2569                 /* Enable jumbo frame workaround in the PHY */
2570                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2571                 data &= ~(0x7F << 5);
2572                 data |= (0x37 << 5);
2573                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2574                 if (ret_val)
2575                         return ret_val;
2576                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2577                 data &= ~(1 << 13);
2578                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2579                 if (ret_val)
2580                         return ret_val;
2581                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2582                 data &= ~(0x3FF << 2);
2583                 data |= (E1000_TX_PTR_GAP << 2);
2584                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2585                 if (ret_val)
2586                         return ret_val;
2587                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2588                 if (ret_val)
2589                         return ret_val;
2590                 e1e_rphy(hw, HV_PM_CTRL, &data);
2591                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
2592                 if (ret_val)
2593                         return ret_val;
2594         } else {
2595                 /* Write MAC register values back to h/w defaults */
2596                 mac_reg = er32(FFLT_DBG);
2597                 mac_reg &= ~(0xF << 14);
2598                 ew32(FFLT_DBG, mac_reg);
2599
2600                 mac_reg = er32(RCTL);
2601                 mac_reg &= ~E1000_RCTL_SECRC;
2602                 ew32(RCTL, mac_reg);
2603
2604                 ret_val = e1000e_read_kmrn_reg(hw,
2605                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2606                                                &data);
2607                 if (ret_val)
2608                         return ret_val;
2609                 ret_val = e1000e_write_kmrn_reg(hw,
2610                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2611                                                 data & ~(1 << 0));
2612                 if (ret_val)
2613                         return ret_val;
2614                 ret_val = e1000e_read_kmrn_reg(hw,
2615                                                E1000_KMRNCTRLSTA_HD_CTRL,
2616                                                &data);
2617                 if (ret_val)
2618                         return ret_val;
2619                 data &= ~(0xF << 8);
2620                 data |= (0xB << 8);
2621                 ret_val = e1000e_write_kmrn_reg(hw,
2622                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2623                                                 data);
2624                 if (ret_val)
2625                         return ret_val;
2626
2627                 /* Write PHY register values back to h/w defaults */
2628                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2629                 data &= ~(0x7F << 5);
2630                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2631                 if (ret_val)
2632                         return ret_val;
2633                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2634                 data |= (1 << 13);
2635                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2636                 if (ret_val)
2637                         return ret_val;
2638                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2639                 data &= ~(0x3FF << 2);
2640                 data |= (0x8 << 2);
2641                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2642                 if (ret_val)
2643                         return ret_val;
2644                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2645                 if (ret_val)
2646                         return ret_val;
2647                 e1e_rphy(hw, HV_PM_CTRL, &data);
2648                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2649                 if (ret_val)
2650                         return ret_val;
2651         }
2652
2653         /* re-enable Rx path after enabling/disabling workaround */
2654         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2655 }
2656
2657 /**
2658  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2659  *  done after every PHY reset.
2660  **/
2661 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2662 {
2663         s32 ret_val = 0;
2664
2665         if (hw->mac.type != e1000_pch2lan)
2666                 return 0;
2667
2668         /* Set MDIO slow mode before any other MDIO access */
2669         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2670         if (ret_val)
2671                 return ret_val;
2672
2673         ret_val = hw->phy.ops.acquire(hw);
2674         if (ret_val)
2675                 return ret_val;
2676         /* set MSE higher to enable link to stay up when noise is high */
2677         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2678         if (ret_val)
2679                 goto release;
2680         /* drop link after 5 times MSE threshold was reached */
2681         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2682 release:
2683         hw->phy.ops.release(hw);
2684
2685         return ret_val;
2686 }
2687
2688 /**
2689  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2690  *  @hw:   pointer to the HW structure
2691  *
2692  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2693  *  Disable K1 in 1000Mbps and 100Mbps
2694  **/
2695 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2696 {
2697         s32 ret_val = 0;
2698         u16 status_reg = 0;
2699
2700         if (hw->mac.type != e1000_pch2lan)
2701                 return 0;
2702
2703         /* Set K1 beacon duration based on 10Mbs speed */
2704         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2705         if (ret_val)
2706                 return ret_val;
2707
2708         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2709             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2710                 if (status_reg &
2711                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2712                         u16 pm_phy_reg;
2713
2714                         /* LV 1G/100 Packet drop issue wa  */
2715                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2716                         if (ret_val)
2717                                 return ret_val;
2718                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2719                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2720                         if (ret_val)
2721                                 return ret_val;
2722                 } else {
2723                         u32 mac_reg;
2724
2725                         mac_reg = er32(FEXTNVM4);
2726                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2727                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2728                         ew32(FEXTNVM4, mac_reg);
2729                 }
2730         }
2731
2732         return ret_val;
2733 }
2734
2735 /**
2736  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2737  *  @hw:   pointer to the HW structure
2738  *  @gate: boolean set to true to gate, false to ungate
2739  *
2740  *  Gate/ungate the automatic PHY configuration via hardware; perform
2741  *  the configuration via software instead.
2742  **/
2743 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2744 {
2745         u32 extcnf_ctrl;
2746
2747         if (hw->mac.type < e1000_pch2lan)
2748                 return;
2749
2750         extcnf_ctrl = er32(EXTCNF_CTRL);
2751
2752         if (gate)
2753                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2754         else
2755                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2756
2757         ew32(EXTCNF_CTRL, extcnf_ctrl);
2758 }
2759
2760 /**
2761  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2762  *  @hw: pointer to the HW structure
2763  *
2764  *  Check the appropriate indication the MAC has finished configuring the
2765  *  PHY after a software reset.
2766  **/
2767 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2768 {
2769         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2770
2771         /* Wait for basic configuration completes before proceeding */
2772         do {
2773                 data = er32(STATUS);
2774                 data &= E1000_STATUS_LAN_INIT_DONE;
2775                 usleep_range(100, 200);
2776         } while ((!data) && --loop);
2777
2778         /* If basic configuration is incomplete before the above loop
2779          * count reaches 0, loading the configuration from NVM will
2780          * leave the PHY in a bad state possibly resulting in no link.
2781          */
2782         if (loop == 0)
2783                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2784
2785         /* Clear the Init Done bit for the next init event */
2786         data = er32(STATUS);
2787         data &= ~E1000_STATUS_LAN_INIT_DONE;
2788         ew32(STATUS, data);
2789 }
2790
2791 /**
2792  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2793  *  @hw: pointer to the HW structure
2794  **/
2795 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2796 {
2797         s32 ret_val = 0;
2798         u16 reg;
2799
2800         if (hw->phy.ops.check_reset_block(hw))
2801                 return 0;
2802
2803         /* Allow time for h/w to get to quiescent state after reset */
2804         usleep_range(10000, 20000);
2805
2806         /* Perform any necessary post-reset workarounds */
2807         switch (hw->mac.type) {
2808         case e1000_pchlan:
2809                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2810                 if (ret_val)
2811                         return ret_val;
2812                 break;
2813         case e1000_pch2lan:
2814                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2815                 if (ret_val)
2816                         return ret_val;
2817                 break;
2818         default:
2819                 break;
2820         }
2821
2822         /* Clear the host wakeup bit after lcd reset */
2823         if (hw->mac.type >= e1000_pchlan) {
2824                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2825                 reg &= ~BM_WUC_HOST_WU_BIT;
2826                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2827         }
2828
2829         /* Configure the LCD with the extended configuration region in NVM */
2830         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2831         if (ret_val)
2832                 return ret_val;
2833
2834         /* Configure the LCD with the OEM bits in NVM */
2835         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2836
2837         if (hw->mac.type == e1000_pch2lan) {
2838                 /* Ungate automatic PHY configuration on non-managed 82579 */
2839                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2840                         usleep_range(10000, 20000);
2841                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2842                 }
2843
2844                 /* Set EEE LPI Update Timer to 200usec */
2845                 ret_val = hw->phy.ops.acquire(hw);
2846                 if (ret_val)
2847                         return ret_val;
2848                 ret_val = e1000_write_emi_reg_locked(hw,
2849                                                      I82579_LPI_UPDATE_TIMER,
2850                                                      0x1387);
2851                 hw->phy.ops.release(hw);
2852         }
2853
2854         return ret_val;
2855 }
2856
2857 /**
2858  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2859  *  @hw: pointer to the HW structure
2860  *
2861  *  Resets the PHY
2862  *  This is a function pointer entry point called by drivers
2863  *  or other shared routines.
2864  **/
2865 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2866 {
2867         s32 ret_val = 0;
2868
2869         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2870         if ((hw->mac.type == e1000_pch2lan) &&
2871             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2872                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2873
2874         ret_val = e1000e_phy_hw_reset_generic(hw);
2875         if (ret_val)
2876                 return ret_val;
2877
2878         return e1000_post_phy_reset_ich8lan(hw);
2879 }
2880
2881 /**
2882  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2883  *  @hw: pointer to the HW structure
2884  *  @active: true to enable LPLU, false to disable
2885  *
2886  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2887  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2888  *  the phy speed. This function will manually set the LPLU bit and restart
2889  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2890  *  since it configures the same bit.
2891  **/
2892 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2893 {
2894         s32 ret_val;
2895         u16 oem_reg;
2896
2897         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2898         if (ret_val)
2899                 return ret_val;
2900
2901         if (active)
2902                 oem_reg |= HV_OEM_BITS_LPLU;
2903         else
2904                 oem_reg &= ~HV_OEM_BITS_LPLU;
2905
2906         if (!hw->phy.ops.check_reset_block(hw))
2907                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2908
2909         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2910 }
2911
2912 /**
2913  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2914  *  @hw: pointer to the HW structure
2915  *  @active: true to enable LPLU, false to disable
2916  *
2917  *  Sets the LPLU D0 state according to the active flag.  When
2918  *  activating LPLU this function also disables smart speed
2919  *  and vice versa.  LPLU will not be activated unless the
2920  *  device autonegotiation advertisement meets standards of
2921  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2922  *  This is a function pointer entry point only called by
2923  *  PHY setup routines.
2924  **/
2925 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2926 {
2927         struct e1000_phy_info *phy = &hw->phy;
2928         u32 phy_ctrl;
2929         s32 ret_val = 0;
2930         u16 data;
2931
2932         if (phy->type == e1000_phy_ife)
2933                 return 0;
2934
2935         phy_ctrl = er32(PHY_CTRL);
2936
2937         if (active) {
2938                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2939                 ew32(PHY_CTRL, phy_ctrl);
2940
2941                 if (phy->type != e1000_phy_igp_3)
2942                         return 0;
2943
2944                 /* Call gig speed drop workaround on LPLU before accessing
2945                  * any PHY registers
2946                  */
2947                 if (hw->mac.type == e1000_ich8lan)
2948                         e1000e_gig_downshift_workaround_ich8lan(hw);
2949
2950                 /* When LPLU is enabled, we should disable SmartSpeed */
2951                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2952                 if (ret_val)
2953                         return ret_val;
2954                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2955                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2956                 if (ret_val)
2957                         return ret_val;
2958         } else {
2959                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2960                 ew32(PHY_CTRL, phy_ctrl);
2961
2962                 if (phy->type != e1000_phy_igp_3)
2963                         return 0;
2964
2965                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2966                  * during Dx states where the power conservation is most
2967                  * important.  During driver activity we should enable
2968                  * SmartSpeed, so performance is maintained.
2969                  */
2970                 if (phy->smart_speed == e1000_smart_speed_on) {
2971                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2972                                            &data);
2973                         if (ret_val)
2974                                 return ret_val;
2975
2976                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2977                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2978                                            data);
2979                         if (ret_val)
2980                                 return ret_val;
2981                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2982                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2983                                            &data);
2984                         if (ret_val)
2985                                 return ret_val;
2986
2987                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2988                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2989                                            data);
2990                         if (ret_val)
2991                                 return ret_val;
2992                 }
2993         }
2994
2995         return 0;
2996 }
2997
2998 /**
2999  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3000  *  @hw: pointer to the HW structure
3001  *  @active: true to enable LPLU, false to disable
3002  *
3003  *  Sets the LPLU D3 state according to the active flag.  When
3004  *  activating LPLU this function also disables smart speed
3005  *  and vice versa.  LPLU will not be activated unless the
3006  *  device autonegotiation advertisement meets standards of
3007  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3008  *  This is a function pointer entry point only called by
3009  *  PHY setup routines.
3010  **/
3011 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3012 {
3013         struct e1000_phy_info *phy = &hw->phy;
3014         u32 phy_ctrl;
3015         s32 ret_val = 0;
3016         u16 data;
3017
3018         phy_ctrl = er32(PHY_CTRL);
3019
3020         if (!active) {
3021                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3022                 ew32(PHY_CTRL, phy_ctrl);
3023
3024                 if (phy->type != e1000_phy_igp_3)
3025                         return 0;
3026
3027                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3028                  * during Dx states where the power conservation is most
3029                  * important.  During driver activity we should enable
3030                  * SmartSpeed, so performance is maintained.
3031                  */
3032                 if (phy->smart_speed == e1000_smart_speed_on) {
3033                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3034                                            &data);
3035                         if (ret_val)
3036                                 return ret_val;
3037
3038                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3039                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3040                                            data);
3041                         if (ret_val)
3042                                 return ret_val;
3043                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3044                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3045                                            &data);
3046                         if (ret_val)
3047                                 return ret_val;
3048
3049                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3050                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3051                                            data);
3052                         if (ret_val)
3053                                 return ret_val;
3054                 }
3055         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3056                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3057                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3058                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3059                 ew32(PHY_CTRL, phy_ctrl);
3060
3061                 if (phy->type != e1000_phy_igp_3)
3062                         return 0;
3063
3064                 /* Call gig speed drop workaround on LPLU before accessing
3065                  * any PHY registers
3066                  */
3067                 if (hw->mac.type == e1000_ich8lan)
3068                         e1000e_gig_downshift_workaround_ich8lan(hw);
3069
3070                 /* When LPLU is enabled, we should disable SmartSpeed */
3071                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3072                 if (ret_val)
3073                         return ret_val;
3074
3075                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3076                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3077         }
3078
3079         return ret_val;
3080 }
3081
3082 /**
3083  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3084  *  @hw: pointer to the HW structure
3085  *  @bank:  pointer to the variable that returns the active bank
3086  *
3087  *  Reads signature byte from the NVM using the flash access registers.
3088  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3089  **/
3090 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3091 {
3092         u32 eecd;
3093         struct e1000_nvm_info *nvm = &hw->nvm;
3094         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3095         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3096         u8 sig_byte = 0;
3097         s32 ret_val;
3098
3099         switch (hw->mac.type) {
3100                 /* In SPT, read from the CTRL_EXT reg instead of
3101                  * accessing the sector valid bits from the nvm
3102                  */
3103         case e1000_pch_spt:
3104                 *bank = er32(CTRL_EXT)
3105                     & E1000_CTRL_EXT_NVMVS;
3106                 if ((*bank == 0) || (*bank == 1)) {
3107                         e_dbg("ERROR: No valid NVM bank present\n");
3108                         return -E1000_ERR_NVM;
3109                 } else {
3110                         *bank = *bank - 2;
3111                         return 0;
3112                 }
3113                 break;
3114         case e1000_ich8lan:
3115         case e1000_ich9lan:
3116                 eecd = er32(EECD);
3117                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3118                     E1000_EECD_SEC1VAL_VALID_MASK) {
3119                         if (eecd & E1000_EECD_SEC1VAL)
3120                                 *bank = 1;
3121                         else
3122                                 *bank = 0;
3123
3124                         return 0;
3125                 }
3126                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3127                 /* fall-thru */
3128         default:
3129                 /* set bank to 0 in case flash read fails */
3130                 *bank = 0;
3131
3132                 /* Check bank 0 */
3133                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3134                                                         &sig_byte);
3135                 if (ret_val)
3136                         return ret_val;
3137                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3138                     E1000_ICH_NVM_SIG_VALUE) {
3139                         *bank = 0;
3140                         return 0;
3141                 }
3142
3143                 /* Check bank 1 */
3144                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3145                                                         bank1_offset,
3146                                                         &sig_byte);
3147                 if (ret_val)
3148                         return ret_val;
3149                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3150                     E1000_ICH_NVM_SIG_VALUE) {
3151                         *bank = 1;
3152                         return 0;
3153                 }
3154
3155                 e_dbg("ERROR: No valid NVM bank present\n");
3156                 return -E1000_ERR_NVM;
3157         }
3158 }
3159
3160 /**
3161  *  e1000_read_nvm_spt - NVM access for SPT
3162  *  @hw: pointer to the HW structure
3163  *  @offset: The offset (in bytes) of the word(s) to read.
3164  *  @words: Size of data to read in words.
3165  *  @data: pointer to the word(s) to read at offset.
3166  *
3167  *  Reads a word(s) from the NVM
3168  **/
3169 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3170                               u16 *data)
3171 {
3172         struct e1000_nvm_info *nvm = &hw->nvm;
3173         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3174         u32 act_offset;
3175         s32 ret_val = 0;
3176         u32 bank = 0;
3177         u32 dword = 0;
3178         u16 offset_to_read;
3179         u16 i;
3180
3181         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3182             (words == 0)) {
3183                 e_dbg("nvm parameter(s) out of bounds\n");
3184                 ret_val = -E1000_ERR_NVM;
3185                 goto out;
3186         }
3187
3188         nvm->ops.acquire(hw);
3189
3190         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3191         if (ret_val) {
3192                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3193                 bank = 0;
3194         }
3195
3196         act_offset = (bank) ? nvm->flash_bank_size : 0;
3197         act_offset += offset;
3198
3199         ret_val = 0;
3200
3201         for (i = 0; i < words; i += 2) {
3202                 if (words - i == 1) {
3203                         if (dev_spec->shadow_ram[offset + i].modified) {
3204                                 data[i] =
3205                                     dev_spec->shadow_ram[offset + i].value;
3206                         } else {
3207                                 offset_to_read = act_offset + i -
3208                                     ((act_offset + i) % 2);
3209                                 ret_val =
3210                                   e1000_read_flash_dword_ich8lan(hw,
3211                                                                  offset_to_read,
3212                                                                  &dword);
3213                                 if (ret_val)
3214                                         break;
3215                                 if ((act_offset + i) % 2 == 0)
3216                                         data[i] = (u16)(dword & 0xFFFF);
3217                                 else
3218                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3219                         }
3220                 } else {
3221                         offset_to_read = act_offset + i;
3222                         if (!(dev_spec->shadow_ram[offset + i].modified) ||
3223                             !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3224                                 ret_val =
3225                                   e1000_read_flash_dword_ich8lan(hw,
3226                                                                  offset_to_read,
3227                                                                  &dword);
3228                                 if (ret_val)
3229                                         break;
3230                         }
3231                         if (dev_spec->shadow_ram[offset + i].modified)
3232                                 data[i] =
3233                                     dev_spec->shadow_ram[offset + i].value;
3234                         else
3235                                 data[i] = (u16)(dword & 0xFFFF);
3236                         if (dev_spec->shadow_ram[offset + i].modified)
3237                                 data[i + 1] =
3238                                     dev_spec->shadow_ram[offset + i + 1].value;
3239                         else
3240                                 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3241                 }
3242         }
3243
3244         nvm->ops.release(hw);
3245
3246 out:
3247         if (ret_val)
3248                 e_dbg("NVM read error: %d\n", ret_val);
3249
3250         return ret_val;
3251 }
3252
3253 /**
3254  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3255  *  @hw: pointer to the HW structure
3256  *  @offset: The offset (in bytes) of the word(s) to read.
3257  *  @words: Size of data to read in words
3258  *  @data: Pointer to the word(s) to read at offset.
3259  *
3260  *  Reads a word(s) from the NVM using the flash access registers.
3261  **/
3262 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3263                                   u16 *data)
3264 {
3265         struct e1000_nvm_info *nvm = &hw->nvm;
3266         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3267         u32 act_offset;
3268         s32 ret_val = 0;
3269         u32 bank = 0;
3270         u16 i, word;
3271
3272         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3273             (words == 0)) {
3274                 e_dbg("nvm parameter(s) out of bounds\n");
3275                 ret_val = -E1000_ERR_NVM;
3276                 goto out;
3277         }
3278
3279         nvm->ops.acquire(hw);
3280
3281         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3282         if (ret_val) {
3283                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3284                 bank = 0;
3285         }
3286
3287         act_offset = (bank) ? nvm->flash_bank_size : 0;
3288         act_offset += offset;
3289
3290         ret_val = 0;
3291         for (i = 0; i < words; i++) {
3292                 if (dev_spec->shadow_ram[offset + i].modified) {
3293                         data[i] = dev_spec->shadow_ram[offset + i].value;
3294                 } else {
3295                         ret_val = e1000_read_flash_word_ich8lan(hw,
3296                                                                 act_offset + i,
3297                                                                 &word);
3298                         if (ret_val)
3299                                 break;
3300                         data[i] = word;
3301                 }
3302         }
3303
3304         nvm->ops.release(hw);
3305
3306 out:
3307         if (ret_val)
3308                 e_dbg("NVM read error: %d\n", ret_val);
3309
3310         return ret_val;
3311 }
3312
3313 /**
3314  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3315  *  @hw: pointer to the HW structure
3316  *
3317  *  This function does initial flash setup so that a new read/write/erase cycle
3318  *  can be started.
3319  **/
3320 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3321 {
3322         union ich8_hws_flash_status hsfsts;
3323         s32 ret_val = -E1000_ERR_NVM;
3324
3325         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3326
3327         /* Check if the flash descriptor is valid */
3328         if (!hsfsts.hsf_status.fldesvalid) {
3329                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
3330                 return -E1000_ERR_NVM;
3331         }
3332
3333         /* Clear FCERR and DAEL in hw status by writing 1 */
3334         hsfsts.hsf_status.flcerr = 1;
3335         hsfsts.hsf_status.dael = 1;
3336         if (hw->mac.type == e1000_pch_spt)
3337                 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3338         else
3339                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3340
3341         /* Either we should have a hardware SPI cycle in progress
3342          * bit to check against, in order to start a new cycle or
3343          * FDONE bit should be changed in the hardware so that it
3344          * is 1 after hardware reset, which can then be used as an
3345          * indication whether a cycle is in progress or has been
3346          * completed.
3347          */
3348
3349         if (!hsfsts.hsf_status.flcinprog) {
3350                 /* There is no cycle running at present,
3351                  * so we can start a cycle.
3352                  * Begin by setting Flash Cycle Done.
3353                  */
3354                 hsfsts.hsf_status.flcdone = 1;
3355                 if (hw->mac.type == e1000_pch_spt)
3356                         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3357                 else
3358                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3359                 ret_val = 0;
3360         } else {
3361                 s32 i;
3362
3363                 /* Otherwise poll for sometime so the current
3364                  * cycle has a chance to end before giving up.
3365                  */
3366                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3367                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3368                         if (!hsfsts.hsf_status.flcinprog) {
3369                                 ret_val = 0;
3370                                 break;
3371                         }
3372                         udelay(1);
3373                 }
3374                 if (!ret_val) {
3375                         /* Successful in waiting for previous cycle to timeout,
3376                          * now set the Flash Cycle Done.
3377                          */
3378                         hsfsts.hsf_status.flcdone = 1;
3379                         if (hw->mac.type == e1000_pch_spt)
3380                                 ew32flash(ICH_FLASH_HSFSTS,
3381                                           hsfsts.regval & 0xFFFF);
3382                         else
3383                                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3384                 } else {
3385                         e_dbg("Flash controller busy, cannot get access\n");
3386                 }
3387         }
3388
3389         return ret_val;
3390 }
3391
3392 /**
3393  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3394  *  @hw: pointer to the HW structure
3395  *  @timeout: maximum time to wait for completion
3396  *
3397  *  This function starts a flash cycle and waits for its completion.
3398  **/
3399 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3400 {
3401         union ich8_hws_flash_ctrl hsflctl;
3402         union ich8_hws_flash_status hsfsts;
3403         u32 i = 0;
3404
3405         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3406         if (hw->mac.type == e1000_pch_spt)
3407                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3408         else
3409                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3410         hsflctl.hsf_ctrl.flcgo = 1;
3411
3412         if (hw->mac.type == e1000_pch_spt)
3413                 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3414         else
3415                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3416
3417         /* wait till FDONE bit is set to 1 */
3418         do {
3419                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3420                 if (hsfsts.hsf_status.flcdone)
3421                         break;
3422                 udelay(1);
3423         } while (i++ < timeout);
3424
3425         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3426                 return 0;
3427
3428         return -E1000_ERR_NVM;
3429 }
3430
3431 /**
3432  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3433  *  @hw: pointer to the HW structure
3434  *  @offset: offset to data location
3435  *  @data: pointer to the location for storing the data
3436  *
3437  *  Reads the flash dword at offset into data.  Offset is converted
3438  *  to bytes before read.
3439  **/
3440 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3441                                           u32 *data)
3442 {
3443         /* Must convert word offset into bytes. */
3444         offset <<= 1;
3445         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3446 }
3447
3448 /**
3449  *  e1000_read_flash_word_ich8lan - Read word from flash
3450  *  @hw: pointer to the HW structure
3451  *  @offset: offset to data location
3452  *  @data: pointer to the location for storing the data
3453  *
3454  *  Reads the flash word at offset into data.  Offset is converted
3455  *  to bytes before read.
3456  **/
3457 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3458                                          u16 *data)
3459 {
3460         /* Must convert offset into bytes. */
3461         offset <<= 1;
3462
3463         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3464 }
3465
3466 /**
3467  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3468  *  @hw: pointer to the HW structure
3469  *  @offset: The offset of the byte to read.
3470  *  @data: Pointer to a byte to store the value read.
3471  *
3472  *  Reads a single byte from the NVM using the flash access registers.
3473  **/
3474 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3475                                          u8 *data)
3476 {
3477         s32 ret_val;
3478         u16 word = 0;
3479
3480         /* In SPT, only 32 bits access is supported,
3481          * so this function should not be called.
3482          */
3483         if (hw->mac.type == e1000_pch_spt)
3484                 return -E1000_ERR_NVM;
3485         else
3486                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3487
3488         if (ret_val)
3489                 return ret_val;
3490
3491         *data = (u8)word;
3492
3493         return 0;
3494 }
3495
3496 /**
3497  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3498  *  @hw: pointer to the HW structure
3499  *  @offset: The offset (in bytes) of the byte or word to read.
3500  *  @size: Size of data to read, 1=byte 2=word
3501  *  @data: Pointer to the word to store the value read.
3502  *
3503  *  Reads a byte or word from the NVM using the flash access registers.
3504  **/
3505 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3506                                          u8 size, u16 *data)
3507 {
3508         union ich8_hws_flash_status hsfsts;
3509         union ich8_hws_flash_ctrl hsflctl;
3510         u32 flash_linear_addr;
3511         u32 flash_data = 0;
3512         s32 ret_val = -E1000_ERR_NVM;
3513         u8 count = 0;
3514
3515         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3516                 return -E1000_ERR_NVM;
3517
3518         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3519                              hw->nvm.flash_base_addr);
3520
3521         do {
3522                 udelay(1);
3523                 /* Steps */
3524                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3525                 if (ret_val)
3526                         break;
3527
3528                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3529                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3530                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3531                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3532                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3533
3534                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3535
3536                 ret_val =
3537                     e1000_flash_cycle_ich8lan(hw,
3538                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3539
3540                 /* Check if FCERR is set to 1, if set to 1, clear it
3541                  * and try the whole sequence a few more times, else
3542                  * read in (shift in) the Flash Data0, the order is
3543                  * least significant byte first msb to lsb
3544                  */
3545                 if (!ret_val) {
3546                         flash_data = er32flash(ICH_FLASH_FDATA0);
3547                         if (size == 1)
3548                                 *data = (u8)(flash_data & 0x000000FF);
3549                         else if (size == 2)
3550                                 *data = (u16)(flash_data & 0x0000FFFF);
3551                         break;
3552                 } else {
3553                         /* If we've gotten here, then things are probably
3554                          * completely hosed, but if the error condition is
3555                          * detected, it won't hurt to give it another try...
3556                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3557                          */
3558                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3559                         if (hsfsts.hsf_status.flcerr) {
3560                                 /* Repeat for some time before giving up. */
3561                                 continue;
3562                         } else if (!hsfsts.hsf_status.flcdone) {
3563                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3564                                 break;
3565                         }
3566                 }
3567         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3568
3569         return ret_val;
3570 }
3571
3572 /**
3573  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3574  *  @hw: pointer to the HW structure
3575  *  @offset: The offset (in bytes) of the dword to read.
3576  *  @data: Pointer to the dword to store the value read.
3577  *
3578  *  Reads a byte or word from the NVM using the flash access registers.
3579  **/
3580
3581 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3582                                            u32 *data)
3583 {
3584         union ich8_hws_flash_status hsfsts;
3585         union ich8_hws_flash_ctrl hsflctl;
3586         u32 flash_linear_addr;
3587         s32 ret_val = -E1000_ERR_NVM;
3588         u8 count = 0;
3589
3590         if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3591             hw->mac.type != e1000_pch_spt)
3592                 return -E1000_ERR_NVM;
3593         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3594                              hw->nvm.flash_base_addr);
3595
3596         do {
3597                 udelay(1);
3598                 /* Steps */
3599                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3600                 if (ret_val)
3601                         break;
3602                 /* In SPT, This register is in Lan memory space, not flash.
3603                  * Therefore, only 32 bit access is supported
3604                  */
3605                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3606
3607                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3608                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3609                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3610                 /* In SPT, This register is in Lan memory space, not flash.
3611                  * Therefore, only 32 bit access is supported
3612                  */
3613                 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3614                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3615
3616                 ret_val =
3617                    e1000_flash_cycle_ich8lan(hw,
3618                                              ICH_FLASH_READ_COMMAND_TIMEOUT);
3619
3620                 /* Check if FCERR is set to 1, if set to 1, clear it
3621                  * and try the whole sequence a few more times, else
3622                  * read in (shift in) the Flash Data0, the order is
3623                  * least significant byte first msb to lsb
3624                  */
3625                 if (!ret_val) {
3626                         *data = er32flash(ICH_FLASH_FDATA0);
3627                         break;
3628                 } else {
3629                         /* If we've gotten here, then things are probably
3630                          * completely hosed, but if the error condition is
3631                          * detected, it won't hurt to give it another try...
3632                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3633                          */
3634                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3635                         if (hsfsts.hsf_status.flcerr) {
3636                                 /* Repeat for some time before giving up. */
3637                                 continue;
3638                         } else if (!hsfsts.hsf_status.flcdone) {
3639                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3640                                 break;
3641                         }
3642                 }
3643         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3644
3645         return ret_val;
3646 }
3647
3648 /**
3649  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3650  *  @hw: pointer to the HW structure
3651  *  @offset: The offset (in bytes) of the word(s) to write.
3652  *  @words: Size of data to write in words
3653  *  @data: Pointer to the word(s) to write at offset.
3654  *
3655  *  Writes a byte or word to the NVM using the flash access registers.
3656  **/
3657 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3658                                    u16 *data)
3659 {
3660         struct e1000_nvm_info *nvm = &hw->nvm;
3661         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3662         u16 i;
3663
3664         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3665             (words == 0)) {
3666                 e_dbg("nvm parameter(s) out of bounds\n");
3667                 return -E1000_ERR_NVM;
3668         }
3669
3670         nvm->ops.acquire(hw);
3671
3672         for (i = 0; i < words; i++) {
3673                 dev_spec->shadow_ram[offset + i].modified = true;
3674                 dev_spec->shadow_ram[offset + i].value = data[i];
3675         }
3676
3677         nvm->ops.release(hw);
3678
3679         return 0;
3680 }
3681
3682 /**
3683  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3684  *  @hw: pointer to the HW structure
3685  *
3686  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3687  *  which writes the checksum to the shadow ram.  The changes in the shadow
3688  *  ram are then committed to the EEPROM by processing each bank at a time
3689  *  checking for the modified bit and writing only the pending changes.
3690  *  After a successful commit, the shadow ram is cleared and is ready for
3691  *  future writes.
3692  **/
3693 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3694 {
3695         struct e1000_nvm_info *nvm = &hw->nvm;
3696         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3697         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3698         s32 ret_val;
3699         u32 dword = 0;
3700
3701         ret_val = e1000e_update_nvm_checksum_generic(hw);
3702         if (ret_val)
3703                 goto out;
3704
3705         if (nvm->type != e1000_nvm_flash_sw)
3706                 goto out;
3707
3708         nvm->ops.acquire(hw);
3709
3710         /* We're writing to the opposite bank so if we're on bank 1,
3711          * write to bank 0 etc.  We also need to erase the segment that
3712          * is going to be written
3713          */
3714         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3715         if (ret_val) {
3716                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3717                 bank = 0;
3718         }
3719
3720         if (bank == 0) {
3721                 new_bank_offset = nvm->flash_bank_size;
3722                 old_bank_offset = 0;
3723                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3724                 if (ret_val)
3725                         goto release;
3726         } else {
3727                 old_bank_offset = nvm->flash_bank_size;
3728                 new_bank_offset = 0;
3729                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3730                 if (ret_val)
3731                         goto release;
3732         }
3733         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3734                 /* Determine whether to write the value stored
3735                  * in the other NVM bank or a modified value stored
3736                  * in the shadow RAM
3737                  */
3738                 ret_val = e1000_read_flash_dword_ich8lan(hw,
3739                                                          i + old_bank_offset,
3740                                                          &dword);
3741
3742                 if (dev_spec->shadow_ram[i].modified) {
3743                         dword &= 0xffff0000;
3744                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3745                 }
3746                 if (dev_spec->shadow_ram[i + 1].modified) {
3747                         dword &= 0x0000ffff;
3748                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3749                                   << 16);
3750                 }
3751                 if (ret_val)
3752                         break;
3753
3754                 /* If the word is 0x13, then make sure the signature bits
3755                  * (15:14) are 11b until the commit has completed.
3756                  * This will allow us to write 10b which indicates the
3757                  * signature is valid.  We want to do this after the write
3758                  * has completed so that we don't mark the segment valid
3759                  * while the write is still in progress
3760                  */
3761                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3762                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
3763
3764                 /* Convert offset to bytes. */
3765                 act_offset = (i + new_bank_offset) << 1;
3766
3767                 usleep_range(100, 200);
3768
3769                 /* Write the data to the new bank. Offset in words */
3770                 act_offset = i + new_bank_offset;
3771                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3772                                                                 dword);
3773                 if (ret_val)
3774                         break;
3775         }
3776
3777         /* Don't bother writing the segment valid bits if sector
3778          * programming failed.
3779          */
3780         if (ret_val) {
3781                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3782                 e_dbg("Flash commit failed.\n");
3783                 goto release;
3784         }
3785
3786         /* Finally validate the new segment by setting bit 15:14
3787          * to 10b in word 0x13 , this can be done without an
3788          * erase as well since these bits are 11 to start with
3789          * and we need to change bit 14 to 0b
3790          */
3791         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3792
3793         /*offset in words but we read dword */
3794         --act_offset;
3795         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3796
3797         if (ret_val)
3798                 goto release;
3799
3800         dword &= 0xBFFFFFFF;
3801         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3802
3803         if (ret_val)
3804                 goto release;
3805
3806         /* And invalidate the previously valid segment by setting
3807          * its signature word (0x13) high_byte to 0b. This can be
3808          * done without an erase because flash erase sets all bits
3809          * to 1's. We can write 1's to 0's without an erase
3810          */
3811         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3812
3813         /* offset in words but we read dword */
3814         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3815         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3816
3817         if (ret_val)
3818                 goto release;
3819
3820         dword &= 0x00FFFFFF;
3821         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3822
3823         if (ret_val)
3824                 goto release;
3825
3826         /* Great!  Everything worked, we can now clear the cached entries. */
3827         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3828                 dev_spec->shadow_ram[i].modified = false;
3829                 dev_spec->shadow_ram[i].value = 0xFFFF;
3830         }
3831
3832 release:
3833         nvm->ops.release(hw);
3834
3835         /* Reload the EEPROM, or else modifications will not appear
3836          * until after the next adapter reset.
3837          */
3838         if (!ret_val) {
3839                 nvm->ops.reload(hw);
3840                 usleep_range(10000, 20000);
3841         }
3842
3843 out:
3844         if (ret_val)
3845                 e_dbg("NVM update error: %d\n", ret_val);
3846
3847         return ret_val;
3848 }
3849
3850 /**
3851  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3852  *  @hw: pointer to the HW structure
3853  *
3854  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3855  *  which writes the checksum to the shadow ram.  The changes in the shadow
3856  *  ram are then committed to the EEPROM by processing each bank at a time
3857  *  checking for the modified bit and writing only the pending changes.
3858  *  After a successful commit, the shadow ram is cleared and is ready for
3859  *  future writes.
3860  **/
3861 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3862 {
3863         struct e1000_nvm_info *nvm = &hw->nvm;
3864         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3865         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3866         s32 ret_val;
3867         u16 data = 0;
3868
3869         ret_val = e1000e_update_nvm_checksum_generic(hw);
3870         if (ret_val)
3871                 goto out;
3872
3873         if (nvm->type != e1000_nvm_flash_sw)
3874                 goto out;
3875
3876         nvm->ops.acquire(hw);
3877
3878         /* We're writing to the opposite bank so if we're on bank 1,
3879          * write to bank 0 etc.  We also need to erase the segment that
3880          * is going to be written
3881          */
3882         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3883         if (ret_val) {
3884                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3885                 bank = 0;
3886         }
3887
3888         if (bank == 0) {
3889                 new_bank_offset = nvm->flash_bank_size;
3890                 old_bank_offset = 0;
3891                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3892                 if (ret_val)
3893                         goto release;
3894         } else {
3895                 old_bank_offset = nvm->flash_bank_size;
3896                 new_bank_offset = 0;
3897                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3898                 if (ret_val)
3899                         goto release;
3900         }
3901         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3902                 if (dev_spec->shadow_ram[i].modified) {
3903                         data = dev_spec->shadow_ram[i].value;
3904                 } else {
3905                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3906                                                                 old_bank_offset,
3907                                                                 &data);
3908                         if (ret_val)
3909                                 break;
3910                 }
3911
3912                 /* If the word is 0x13, then make sure the signature bits
3913                  * (15:14) are 11b until the commit has completed.
3914                  * This will allow us to write 10b which indicates the
3915                  * signature is valid.  We want to do this after the write
3916                  * has completed so that we don't mark the segment valid
3917                  * while the write is still in progress
3918                  */
3919                 if (i == E1000_ICH_NVM_SIG_WORD)
3920                         data |= E1000_ICH_NVM_SIG_MASK;
3921
3922                 /* Convert offset to bytes. */
3923                 act_offset = (i + new_bank_offset) << 1;
3924
3925                 usleep_range(100, 200);
3926                 /* Write the bytes to the new bank. */
3927                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3928                                                                act_offset,
3929                                                                (u8)data);
3930                 if (ret_val)
3931                         break;
3932
3933                 usleep_range(100, 200);
3934                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3935                                                                act_offset + 1,
3936                                                                (u8)(data >> 8));
3937                 if (ret_val)
3938                         break;
3939         }
3940
3941         /* Don't bother writing the segment valid bits if sector
3942          * programming failed.
3943          */
3944         if (ret_val) {
3945                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3946                 e_dbg("Flash commit failed.\n");
3947                 goto release;
3948         }
3949
3950         /* Finally validate the new segment by setting bit 15:14
3951          * to 10b in word 0x13 , this can be done without an
3952          * erase as well since these bits are 11 to start with
3953          * and we need to change bit 14 to 0b
3954          */
3955         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3956         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3957         if (ret_val)
3958                 goto release;
3959
3960         data &= 0xBFFF;
3961         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3962                                                        act_offset * 2 + 1,
3963                                                        (u8)(data >> 8));
3964         if (ret_val)
3965                 goto release;
3966
3967         /* And invalidate the previously valid segment by setting
3968          * its signature word (0x13) high_byte to 0b. This can be
3969          * done without an erase because flash erase sets all bits
3970          * to 1's. We can write 1's to 0's without an erase
3971          */
3972         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3973         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3974         if (ret_val)
3975                 goto release;
3976
3977         /* Great!  Everything worked, we can now clear the cached entries. */
3978         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3979                 dev_spec->shadow_ram[i].modified = false;
3980                 dev_spec->shadow_ram[i].value = 0xFFFF;
3981         }
3982
3983 release:
3984         nvm->ops.release(hw);
3985
3986         /* Reload the EEPROM, or else modifications will not appear
3987          * until after the next adapter reset.
3988          */
3989         if (!ret_val) {
3990                 nvm->ops.reload(hw);
3991                 usleep_range(10000, 20000);
3992         }
3993
3994 out:
3995         if (ret_val)
3996                 e_dbg("NVM update error: %d\n", ret_val);
3997
3998         return ret_val;
3999 }
4000
4001 /**
4002  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4003  *  @hw: pointer to the HW structure
4004  *
4005  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4006  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4007  *  calculated, in which case we need to calculate the checksum and set bit 6.
4008  **/
4009 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4010 {
4011         s32 ret_val;
4012         u16 data;
4013         u16 word;
4014         u16 valid_csum_mask;
4015
4016         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4017          * the checksum needs to be fixed.  This bit is an indication that
4018          * the NVM was prepared by OEM software and did not calculate
4019          * the checksum...a likely scenario.
4020          */
4021         switch (hw->mac.type) {
4022         case e1000_pch_lpt:
4023         case e1000_pch_spt:
4024                 word = NVM_COMPAT;
4025                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4026                 break;
4027         default:
4028                 word = NVM_FUTURE_INIT_WORD1;
4029                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4030                 break;
4031         }
4032
4033         ret_val = e1000_read_nvm(hw, word, 1, &data);
4034         if (ret_val)
4035                 return ret_val;
4036
4037         if (!(data & valid_csum_mask)) {
4038                 data |= valid_csum_mask;
4039                 ret_val = e1000_write_nvm(hw, word, 1, &data);
4040                 if (ret_val)
4041                         return ret_val;
4042                 ret_val = e1000e_update_nvm_checksum(hw);
4043                 if (ret_val)
4044                         return ret_val;
4045         }
4046
4047         return e1000e_validate_nvm_checksum_generic(hw);
4048 }
4049
4050 /**
4051  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4052  *  @hw: pointer to the HW structure
4053  *
4054  *  To prevent malicious write/erase of the NVM, set it to be read-only
4055  *  so that the hardware ignores all write/erase cycles of the NVM via
4056  *  the flash control registers.  The shadow-ram copy of the NVM will
4057  *  still be updated, however any updates to this copy will not stick
4058  *  across driver reloads.
4059  **/
4060 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4061 {
4062         struct e1000_nvm_info *nvm = &hw->nvm;
4063         union ich8_flash_protected_range pr0;
4064         union ich8_hws_flash_status hsfsts;
4065         u32 gfpreg;
4066
4067         nvm->ops.acquire(hw);
4068
4069         gfpreg = er32flash(ICH_FLASH_GFPREG);
4070
4071         /* Write-protect GbE Sector of NVM */
4072         pr0.regval = er32flash(ICH_FLASH_PR0);
4073         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4074         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4075         pr0.range.wpe = true;
4076         ew32flash(ICH_FLASH_PR0, pr0.regval);
4077
4078         /* Lock down a subset of GbE Flash Control Registers, e.g.
4079          * PR0 to prevent the write-protection from being lifted.
4080          * Once FLOCKDN is set, the registers protected by it cannot
4081          * be written until FLOCKDN is cleared by a hardware reset.
4082          */
4083         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4084         hsfsts.hsf_status.flockdn = true;
4085         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4086
4087         nvm->ops.release(hw);
4088 }
4089
4090 /**
4091  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4092  *  @hw: pointer to the HW structure
4093  *  @offset: The offset (in bytes) of the byte/word to read.
4094  *  @size: Size of data to read, 1=byte 2=word
4095  *  @data: The byte(s) to write to the NVM.
4096  *
4097  *  Writes one/two bytes to the NVM using the flash access registers.
4098  **/
4099 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4100                                           u8 size, u16 data)
4101 {
4102         union ich8_hws_flash_status hsfsts;
4103         union ich8_hws_flash_ctrl hsflctl;
4104         u32 flash_linear_addr;
4105         u32 flash_data = 0;
4106         s32 ret_val;
4107         u8 count = 0;
4108
4109         if (hw->mac.type == e1000_pch_spt) {
4110                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4111                         return -E1000_ERR_NVM;
4112         } else {
4113                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4114                         return -E1000_ERR_NVM;
4115         }
4116
4117         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4118                              hw->nvm.flash_base_addr);
4119
4120         do {
4121                 udelay(1);
4122                 /* Steps */
4123                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4124                 if (ret_val)
4125                         break;
4126                 /* In SPT, This register is in Lan memory space, not
4127                  * flash.  Therefore, only 32 bit access is supported
4128                  */
4129                 if (hw->mac.type == e1000_pch_spt)
4130                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4131                 else
4132                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4133
4134                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4135                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4136                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4137                 /* In SPT, This register is in Lan memory space,
4138                  * not flash.  Therefore, only 32 bit access is
4139                  * supported
4140                  */
4141                 if (hw->mac.type == e1000_pch_spt)
4142                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4143                 else
4144                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4145
4146                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4147
4148                 if (size == 1)
4149                         flash_data = (u32)data & 0x00FF;
4150                 else
4151                         flash_data = (u32)data;
4152
4153                 ew32flash(ICH_FLASH_FDATA0, flash_data);
4154
4155                 /* check if FCERR is set to 1 , if set to 1, clear it
4156                  * and try the whole sequence a few more times else done
4157                  */
4158                 ret_val =
4159                     e1000_flash_cycle_ich8lan(hw,
4160                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4161                 if (!ret_val)
4162                         break;
4163
4164                 /* If we're here, then things are most likely
4165                  * completely hosed, but if the error condition
4166                  * is detected, it won't hurt to give it another
4167                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4168                  */
4169                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4170                 if (hsfsts.hsf_status.flcerr)
4171                         /* Repeat for some time before giving up. */
4172                         continue;
4173                 if (!hsfsts.hsf_status.flcdone) {
4174                         e_dbg("Timeout error - flash cycle did not complete.\n");
4175                         break;
4176                 }
4177         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4178
4179         return ret_val;
4180 }
4181
4182 /**
4183 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4184 *  @hw: pointer to the HW structure
4185 *  @offset: The offset (in bytes) of the dwords to read.
4186 *  @data: The 4 bytes to write to the NVM.
4187 *
4188 *  Writes one/two/four bytes to the NVM using the flash access registers.
4189 **/
4190 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4191                                             u32 data)
4192 {
4193         union ich8_hws_flash_status hsfsts;
4194         union ich8_hws_flash_ctrl hsflctl;
4195         u32 flash_linear_addr;
4196         s32 ret_val;
4197         u8 count = 0;
4198
4199         if (hw->mac.type == e1000_pch_spt) {
4200                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4201                         return -E1000_ERR_NVM;
4202         }
4203         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4204                              hw->nvm.flash_base_addr);
4205         do {
4206                 udelay(1);
4207                 /* Steps */
4208                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4209                 if (ret_val)
4210                         break;
4211
4212                 /* In SPT, This register is in Lan memory space, not
4213                  * flash.  Therefore, only 32 bit access is supported
4214                  */
4215                 if (hw->mac.type == e1000_pch_spt)
4216                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4217                             >> 16;
4218                 else
4219                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4220
4221                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4222                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4223
4224                 /* In SPT, This register is in Lan memory space,
4225                  * not flash.  Therefore, only 32 bit access is
4226                  * supported
4227                  */
4228                 if (hw->mac.type == e1000_pch_spt)
4229                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4230                 else
4231                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4232
4233                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4234
4235                 ew32flash(ICH_FLASH_FDATA0, data);
4236
4237                 /* check if FCERR is set to 1 , if set to 1, clear it
4238                  * and try the whole sequence a few more times else done
4239                  */
4240                 ret_val =
4241                    e1000_flash_cycle_ich8lan(hw,
4242                                              ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4243
4244                 if (!ret_val)
4245                         break;
4246
4247                 /* If we're here, then things are most likely
4248                  * completely hosed, but if the error condition
4249                  * is detected, it won't hurt to give it another
4250                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4251                  */
4252                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4253
4254                 if (hsfsts.hsf_status.flcerr)
4255                         /* Repeat for some time before giving up. */
4256                         continue;
4257                 if (!hsfsts.hsf_status.flcdone) {
4258                         e_dbg("Timeout error - flash cycle did not complete.\n");
4259                         break;
4260                 }
4261         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4262
4263         return ret_val;
4264 }
4265
4266 /**
4267  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4268  *  @hw: pointer to the HW structure
4269  *  @offset: The index of the byte to read.
4270  *  @data: The byte to write to the NVM.
4271  *
4272  *  Writes a single byte to the NVM using the flash access registers.
4273  **/
4274 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4275                                           u8 data)
4276 {
4277         u16 word = (u16)data;
4278
4279         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4280 }
4281
4282 /**
4283 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4284 *  @hw: pointer to the HW structure
4285 *  @offset: The offset of the word to write.
4286 *  @dword: The dword to write to the NVM.
4287 *
4288 *  Writes a single dword to the NVM using the flash access registers.
4289 *  Goes through a retry algorithm before giving up.
4290 **/
4291 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4292                                                  u32 offset, u32 dword)
4293 {
4294         s32 ret_val;
4295         u16 program_retries;
4296
4297         /* Must convert word offset into bytes. */
4298         offset <<= 1;
4299         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4300
4301         if (!ret_val)
4302                 return ret_val;
4303         for (program_retries = 0; program_retries < 100; program_retries++) {
4304                 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4305                 usleep_range(100, 200);
4306                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4307                 if (!ret_val)
4308                         break;
4309         }
4310         if (program_retries == 100)
4311                 return -E1000_ERR_NVM;
4312
4313         return 0;
4314 }
4315
4316 /**
4317  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4318  *  @hw: pointer to the HW structure
4319  *  @offset: The offset of the byte to write.
4320  *  @byte: The byte to write to the NVM.
4321  *
4322  *  Writes a single byte to the NVM using the flash access registers.
4323  *  Goes through a retry algorithm before giving up.
4324  **/
4325 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4326                                                 u32 offset, u8 byte)
4327 {
4328         s32 ret_val;
4329         u16 program_retries;
4330
4331         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4332         if (!ret_val)
4333                 return ret_val;
4334
4335         for (program_retries = 0; program_retries < 100; program_retries++) {
4336                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4337                 usleep_range(100, 200);
4338                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4339                 if (!ret_val)
4340                         break;
4341         }
4342         if (program_retries == 100)
4343                 return -E1000_ERR_NVM;
4344
4345         return 0;
4346 }
4347
4348 /**
4349  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4350  *  @hw: pointer to the HW structure
4351  *  @bank: 0 for first bank, 1 for second bank, etc.
4352  *
4353  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4354  *  bank N is 4096 * N + flash_reg_addr.
4355  **/
4356 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4357 {
4358         struct e1000_nvm_info *nvm = &hw->nvm;
4359         union ich8_hws_flash_status hsfsts;
4360         union ich8_hws_flash_ctrl hsflctl;
4361         u32 flash_linear_addr;
4362         /* bank size is in 16bit words - adjust to bytes */
4363         u32 flash_bank_size = nvm->flash_bank_size * 2;
4364         s32 ret_val;
4365         s32 count = 0;
4366         s32 j, iteration, sector_size;
4367
4368         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4369
4370         /* Determine HW Sector size: Read BERASE bits of hw flash status
4371          * register
4372          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4373          *     consecutive sectors.  The start index for the nth Hw sector
4374          *     can be calculated as = bank * 4096 + n * 256
4375          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4376          *     The start index for the nth Hw sector can be calculated
4377          *     as = bank * 4096
4378          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4379          *     (ich9 only, otherwise error condition)
4380          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4381          */
4382         switch (hsfsts.hsf_status.berasesz) {
4383         case 0:
4384                 /* Hw sector size 256 */
4385                 sector_size = ICH_FLASH_SEG_SIZE_256;
4386                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4387                 break;
4388         case 1:
4389                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4390                 iteration = 1;
4391                 break;
4392         case 2:
4393                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4394                 iteration = 1;
4395                 break;
4396         case 3:
4397                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4398                 iteration = 1;
4399                 break;
4400         default:
4401                 return -E1000_ERR_NVM;
4402         }
4403
4404         /* Start with the base address, then add the sector offset. */
4405         flash_linear_addr = hw->nvm.flash_base_addr;
4406         flash_linear_addr += (bank) ? flash_bank_size : 0;
4407
4408         for (j = 0; j < iteration; j++) {
4409                 do {
4410                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4411
4412                         /* Steps */
4413                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4414                         if (ret_val)
4415                                 return ret_val;
4416
4417                         /* Write a value 11 (block Erase) in Flash
4418                          * Cycle field in hw flash control
4419                          */
4420                         if (hw->mac.type == e1000_pch_spt)
4421                                 hsflctl.regval =
4422                                     er32flash(ICH_FLASH_HSFSTS) >> 16;
4423                         else
4424                                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4425
4426                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4427                         if (hw->mac.type == e1000_pch_spt)
4428                                 ew32flash(ICH_FLASH_HSFSTS,
4429                                           hsflctl.regval << 16);
4430                         else
4431                                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4432
4433                         /* Write the last 24 bits of an index within the
4434                          * block into Flash Linear address field in Flash
4435                          * Address.
4436                          */
4437                         flash_linear_addr += (j * sector_size);
4438                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4439
4440                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4441                         if (!ret_val)
4442                                 break;
4443
4444                         /* Check if FCERR is set to 1.  If 1,
4445                          * clear it and try the whole sequence
4446                          * a few more times else Done
4447                          */
4448                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4449                         if (hsfsts.hsf_status.flcerr)
4450                                 /* repeat for some time before giving up */
4451                                 continue;
4452                         else if (!hsfsts.hsf_status.flcdone)
4453                                 return ret_val;
4454                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4455         }
4456
4457         return 0;
4458 }
4459
4460 /**
4461  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4462  *  @hw: pointer to the HW structure
4463  *  @data: Pointer to the LED settings
4464  *
4465  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4466  *  settings is all 0's or F's, set the LED default to a valid LED default
4467  *  setting.
4468  **/
4469 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4470 {
4471         s32 ret_val;
4472
4473         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4474         if (ret_val) {
4475                 e_dbg("NVM Read Error\n");
4476                 return ret_val;
4477         }
4478
4479         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4480                 *data = ID_LED_DEFAULT_ICH8LAN;
4481
4482         return 0;
4483 }
4484
4485 /**
4486  *  e1000_id_led_init_pchlan - store LED configurations
4487  *  @hw: pointer to the HW structure
4488  *
4489  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4490  *  the PHY LED configuration register.
4491  *
4492  *  PCH also does not have an "always on" or "always off" mode which
4493  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4494  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4495  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4496  *  link based on logic in e1000_led_[on|off]_pchlan().
4497  **/
4498 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4499 {
4500         struct e1000_mac_info *mac = &hw->mac;
4501         s32 ret_val;
4502         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4503         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4504         u16 data, i, temp, shift;
4505
4506         /* Get default ID LED modes */
4507         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4508         if (ret_val)
4509                 return ret_val;
4510
4511         mac->ledctl_default = er32(LEDCTL);
4512         mac->ledctl_mode1 = mac->ledctl_default;
4513         mac->ledctl_mode2 = mac->ledctl_default;
4514
4515         for (i = 0; i < 4; i++) {
4516                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4517                 shift = (i * 5);
4518                 switch (temp) {
4519                 case ID_LED_ON1_DEF2:
4520                 case ID_LED_ON1_ON2:
4521                 case ID_LED_ON1_OFF2:
4522                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4523                         mac->ledctl_mode1 |= (ledctl_on << shift);
4524                         break;
4525                 case ID_LED_OFF1_DEF2:
4526                 case ID_LED_OFF1_ON2:
4527                 case ID_LED_OFF1_OFF2:
4528                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4529                         mac->ledctl_mode1 |= (ledctl_off << shift);
4530                         break;
4531                 default:
4532                         /* Do nothing */
4533                         break;
4534                 }
4535                 switch (temp) {
4536                 case ID_LED_DEF1_ON2:
4537                 case ID_LED_ON1_ON2:
4538                 case ID_LED_OFF1_ON2:
4539                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4540                         mac->ledctl_mode2 |= (ledctl_on << shift);
4541                         break;
4542                 case ID_LED_DEF1_OFF2:
4543                 case ID_LED_ON1_OFF2:
4544                 case ID_LED_OFF1_OFF2:
4545                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4546                         mac->ledctl_mode2 |= (ledctl_off << shift);
4547                         break;
4548                 default:
4549                         /* Do nothing */
4550                         break;
4551                 }
4552         }
4553
4554         return 0;
4555 }
4556
4557 /**
4558  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4559  *  @hw: pointer to the HW structure
4560  *
4561  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4562  *  register, so the the bus width is hard coded.
4563  **/
4564 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4565 {
4566         struct e1000_bus_info *bus = &hw->bus;
4567         s32 ret_val;
4568
4569         ret_val = e1000e_get_bus_info_pcie(hw);
4570
4571         /* ICH devices are "PCI Express"-ish.  They have
4572          * a configuration space, but do not contain
4573          * PCI Express Capability registers, so bus width
4574          * must be hardcoded.
4575          */
4576         if (bus->width == e1000_bus_width_unknown)
4577                 bus->width = e1000_bus_width_pcie_x1;
4578
4579         return ret_val;
4580 }
4581
4582 /**
4583  *  e1000_reset_hw_ich8lan - Reset the hardware
4584  *  @hw: pointer to the HW structure
4585  *
4586  *  Does a full reset of the hardware which includes a reset of the PHY and
4587  *  MAC.
4588  **/
4589 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4590 {
4591         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4592         u16 kum_cfg;
4593         u32 ctrl, reg;
4594         s32 ret_val;
4595
4596         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4597          * on the last TLP read/write transaction when MAC is reset.
4598          */
4599         ret_val = e1000e_disable_pcie_master(hw);
4600         if (ret_val)
4601                 e_dbg("PCI-E Master disable polling has failed.\n");
4602
4603         e_dbg("Masking off all interrupts\n");
4604         ew32(IMC, 0xffffffff);
4605
4606         /* Disable the Transmit and Receive units.  Then delay to allow
4607          * any pending transactions to complete before we hit the MAC
4608          * with the global reset.
4609          */
4610         ew32(RCTL, 0);
4611         ew32(TCTL, E1000_TCTL_PSP);
4612         e1e_flush();
4613
4614         usleep_range(10000, 20000);
4615
4616         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4617         if (hw->mac.type == e1000_ich8lan) {
4618                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4619                 ew32(PBA, E1000_PBA_8K);
4620                 /* Set Packet Buffer Size to 16k. */
4621                 ew32(PBS, E1000_PBS_16K);
4622         }
4623
4624         if (hw->mac.type == e1000_pchlan) {
4625                 /* Save the NVM K1 bit setting */
4626                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4627                 if (ret_val)
4628                         return ret_val;
4629
4630                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4631                         dev_spec->nvm_k1_enabled = true;
4632                 else
4633                         dev_spec->nvm_k1_enabled = false;
4634         }
4635
4636         ctrl = er32(CTRL);
4637
4638         if (!hw->phy.ops.check_reset_block(hw)) {
4639                 /* Full-chip reset requires MAC and PHY reset at the same
4640                  * time to make sure the interface between MAC and the
4641                  * external PHY is reset.
4642                  */
4643                 ctrl |= E1000_CTRL_PHY_RST;
4644
4645                 /* Gate automatic PHY configuration by hardware on
4646                  * non-managed 82579
4647                  */
4648                 if ((hw->mac.type == e1000_pch2lan) &&
4649                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4650                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4651         }
4652         ret_val = e1000_acquire_swflag_ich8lan(hw);
4653         e_dbg("Issuing a global reset to ich8lan\n");
4654         ew32(CTRL, (ctrl | E1000_CTRL_RST));
4655         /* cannot issue a flush here because it hangs the hardware */
4656         msleep(20);
4657
4658         /* Set Phy Config Counter to 50msec */
4659         if (hw->mac.type == e1000_pch2lan) {
4660                 reg = er32(FEXTNVM3);
4661                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4662                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4663                 ew32(FEXTNVM3, reg);
4664         }
4665
4666         if (!ret_val)
4667                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4668
4669         if (ctrl & E1000_CTRL_PHY_RST) {
4670                 ret_val = hw->phy.ops.get_cfg_done(hw);
4671                 if (ret_val)
4672                         return ret_val;
4673
4674                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4675                 if (ret_val)
4676                         return ret_val;
4677         }
4678
4679         /* For PCH, this write will make sure that any noise
4680          * will be detected as a CRC error and be dropped rather than show up
4681          * as a bad packet to the DMA engine.
4682          */
4683         if (hw->mac.type == e1000_pchlan)
4684                 ew32(CRC_OFFSET, 0x65656565);
4685
4686         ew32(IMC, 0xffffffff);
4687         er32(ICR);
4688
4689         reg = er32(KABGTXD);
4690         reg |= E1000_KABGTXD_BGSQLBIAS;
4691         ew32(KABGTXD, reg);
4692
4693         return 0;
4694 }
4695
4696 /**
4697  *  e1000_init_hw_ich8lan - Initialize the hardware
4698  *  @hw: pointer to the HW structure
4699  *
4700  *  Prepares the hardware for transmit and receive by doing the following:
4701  *   - initialize hardware bits
4702  *   - initialize LED identification
4703  *   - setup receive address registers
4704  *   - setup flow control
4705  *   - setup transmit descriptors
4706  *   - clear statistics
4707  **/
4708 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4709 {
4710         struct e1000_mac_info *mac = &hw->mac;
4711         u32 ctrl_ext, txdctl, snoop;
4712         s32 ret_val;
4713         u16 i;
4714
4715         e1000_initialize_hw_bits_ich8lan(hw);
4716
4717         /* Initialize identification LED */
4718         ret_val = mac->ops.id_led_init(hw);
4719         /* An error is not fatal and we should not stop init due to this */
4720         if (ret_val)
4721                 e_dbg("Error initializing identification LED\n");
4722
4723         /* Setup the receive address. */
4724         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4725
4726         /* Zero out the Multicast HASH table */
4727         e_dbg("Zeroing the MTA\n");
4728         for (i = 0; i < mac->mta_reg_count; i++)
4729                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4730
4731         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4732          * the ME.  Disable wakeup by clearing the host wakeup bit.
4733          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4734          */
4735         if (hw->phy.type == e1000_phy_82578) {
4736                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4737                 i &= ~BM_WUC_HOST_WU_BIT;
4738                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4739                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4740                 if (ret_val)
4741                         return ret_val;
4742         }
4743
4744         /* Setup link and flow control */
4745         ret_val = mac->ops.setup_link(hw);
4746
4747         /* Set the transmit descriptor write-back policy for both queues */
4748         txdctl = er32(TXDCTL(0));
4749         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4750                   E1000_TXDCTL_FULL_TX_DESC_WB);
4751         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4752                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4753         ew32(TXDCTL(0), txdctl);
4754         txdctl = er32(TXDCTL(1));
4755         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4756                   E1000_TXDCTL_FULL_TX_DESC_WB);
4757         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4758                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4759         ew32(TXDCTL(1), txdctl);
4760
4761         /* ICH8 has opposite polarity of no_snoop bits.
4762          * By default, we should use snoop behavior.
4763          */
4764         if (mac->type == e1000_ich8lan)
4765                 snoop = PCIE_ICH8_SNOOP_ALL;
4766         else
4767                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4768         e1000e_set_pcie_no_snoop(hw, snoop);
4769
4770         ctrl_ext = er32(CTRL_EXT);
4771         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4772         ew32(CTRL_EXT, ctrl_ext);
4773
4774         /* Clear all of the statistics registers (clear on read).  It is
4775          * important that we do this after we have tried to establish link
4776          * because the symbol error count will increment wildly if there
4777          * is no link.
4778          */
4779         e1000_clear_hw_cntrs_ich8lan(hw);
4780
4781         return ret_val;
4782 }
4783
4784 /**
4785  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4786  *  @hw: pointer to the HW structure
4787  *
4788  *  Sets/Clears required hardware bits necessary for correctly setting up the
4789  *  hardware for transmit and receive.
4790  **/
4791 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4792 {
4793         u32 reg;
4794
4795         /* Extended Device Control */
4796         reg = er32(CTRL_EXT);
4797         reg |= (1 << 22);
4798         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4799         if (hw->mac.type >= e1000_pchlan)
4800                 reg |= E1000_CTRL_EXT_PHYPDEN;
4801         ew32(CTRL_EXT, reg);
4802
4803         /* Transmit Descriptor Control 0 */
4804         reg = er32(TXDCTL(0));
4805         reg |= (1 << 22);
4806         ew32(TXDCTL(0), reg);
4807
4808         /* Transmit Descriptor Control 1 */
4809         reg = er32(TXDCTL(1));
4810         reg |= (1 << 22);
4811         ew32(TXDCTL(1), reg);
4812
4813         /* Transmit Arbitration Control 0 */
4814         reg = er32(TARC(0));
4815         if (hw->mac.type == e1000_ich8lan)
4816                 reg |= (1 << 28) | (1 << 29);
4817         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4818         ew32(TARC(0), reg);
4819
4820         /* Transmit Arbitration Control 1 */
4821         reg = er32(TARC(1));
4822         if (er32(TCTL) & E1000_TCTL_MULR)
4823                 reg &= ~(1 << 28);
4824         else
4825                 reg |= (1 << 28);
4826         reg |= (1 << 24) | (1 << 26) | (1 << 30);
4827         ew32(TARC(1), reg);
4828
4829         /* Device Status */
4830         if (hw->mac.type == e1000_ich8lan) {
4831                 reg = er32(STATUS);
4832                 reg &= ~(1 << 31);
4833                 ew32(STATUS, reg);
4834         }
4835
4836         /* work-around descriptor data corruption issue during nfs v2 udp
4837          * traffic, just disable the nfs filtering capability
4838          */
4839         reg = er32(RFCTL);
4840         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4841
4842         /* Disable IPv6 extension header parsing because some malformed
4843          * IPv6 headers can hang the Rx.
4844          */
4845         if (hw->mac.type == e1000_ich8lan)
4846                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4847         ew32(RFCTL, reg);
4848
4849         /* Enable ECC on Lynxpoint */
4850         if ((hw->mac.type == e1000_pch_lpt) ||
4851             (hw->mac.type == e1000_pch_spt)) {
4852                 reg = er32(PBECCSTS);
4853                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4854                 ew32(PBECCSTS, reg);
4855
4856                 reg = er32(CTRL);
4857                 reg |= E1000_CTRL_MEHE;
4858                 ew32(CTRL, reg);
4859         }
4860 }
4861
4862 /**
4863  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4864  *  @hw: pointer to the HW structure
4865  *
4866  *  Determines which flow control settings to use, then configures flow
4867  *  control.  Calls the appropriate media-specific link configuration
4868  *  function.  Assuming the adapter has a valid link partner, a valid link
4869  *  should be established.  Assumes the hardware has previously been reset
4870  *  and the transmitter and receiver are not enabled.
4871  **/
4872 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4873 {
4874         s32 ret_val;
4875
4876         if (hw->phy.ops.check_reset_block(hw))
4877                 return 0;
4878
4879         /* ICH parts do not have a word in the NVM to determine
4880          * the default flow control setting, so we explicitly
4881          * set it to full.
4882          */
4883         if (hw->fc.requested_mode == e1000_fc_default) {
4884                 /* Workaround h/w hang when Tx flow control enabled */
4885                 if (hw->mac.type == e1000_pchlan)
4886                         hw->fc.requested_mode = e1000_fc_rx_pause;
4887                 else
4888                         hw->fc.requested_mode = e1000_fc_full;
4889         }
4890
4891         /* Save off the requested flow control mode for use later.  Depending
4892          * on the link partner's capabilities, we may or may not use this mode.
4893          */
4894         hw->fc.current_mode = hw->fc.requested_mode;
4895
4896         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4897
4898         /* Continue to configure the copper link. */
4899         ret_val = hw->mac.ops.setup_physical_interface(hw);
4900         if (ret_val)
4901                 return ret_val;
4902
4903         ew32(FCTTV, hw->fc.pause_time);
4904         if ((hw->phy.type == e1000_phy_82578) ||
4905             (hw->phy.type == e1000_phy_82579) ||
4906             (hw->phy.type == e1000_phy_i217) ||
4907             (hw->phy.type == e1000_phy_82577)) {
4908                 ew32(FCRTV_PCH, hw->fc.refresh_time);
4909
4910                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4911                                    hw->fc.pause_time);
4912                 if (ret_val)
4913                         return ret_val;
4914         }
4915
4916         return e1000e_set_fc_watermarks(hw);
4917 }
4918
4919 /**
4920  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4921  *  @hw: pointer to the HW structure
4922  *
4923  *  Configures the kumeran interface to the PHY to wait the appropriate time
4924  *  when polling the PHY, then call the generic setup_copper_link to finish
4925  *  configuring the copper link.
4926  **/
4927 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4928 {
4929         u32 ctrl;
4930         s32 ret_val;
4931         u16 reg_data;
4932
4933         ctrl = er32(CTRL);
4934         ctrl |= E1000_CTRL_SLU;
4935         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4936         ew32(CTRL, ctrl);
4937
4938         /* Set the mac to wait the maximum time between each iteration
4939          * and increase the max iterations when polling the phy;
4940          * this fixes erroneous timeouts at 10Mbps.
4941          */
4942         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
4943         if (ret_val)
4944                 return ret_val;
4945         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4946                                        &reg_data);
4947         if (ret_val)
4948                 return ret_val;
4949         reg_data |= 0x3F;
4950         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4951                                         reg_data);
4952         if (ret_val)
4953                 return ret_val;
4954
4955         switch (hw->phy.type) {
4956         case e1000_phy_igp_3:
4957                 ret_val = e1000e_copper_link_setup_igp(hw);
4958                 if (ret_val)
4959                         return ret_val;
4960                 break;
4961         case e1000_phy_bm:
4962         case e1000_phy_82578:
4963                 ret_val = e1000e_copper_link_setup_m88(hw);
4964                 if (ret_val)
4965                         return ret_val;
4966                 break;
4967         case e1000_phy_82577:
4968         case e1000_phy_82579:
4969                 ret_val = e1000_copper_link_setup_82577(hw);
4970                 if (ret_val)
4971                         return ret_val;
4972                 break;
4973         case e1000_phy_ife:
4974                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
4975                 if (ret_val)
4976                         return ret_val;
4977
4978                 reg_data &= ~IFE_PMC_AUTO_MDIX;
4979
4980                 switch (hw->phy.mdix) {
4981                 case 1:
4982                         reg_data &= ~IFE_PMC_FORCE_MDIX;
4983                         break;
4984                 case 2:
4985                         reg_data |= IFE_PMC_FORCE_MDIX;
4986                         break;
4987                 case 0:
4988                 default:
4989                         reg_data |= IFE_PMC_AUTO_MDIX;
4990                         break;
4991                 }
4992                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
4993                 if (ret_val)
4994                         return ret_val;
4995                 break;
4996         default:
4997                 break;
4998         }
4999
5000         return e1000e_setup_copper_link(hw);
5001 }
5002
5003 /**
5004  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5005  *  @hw: pointer to the HW structure
5006  *
5007  *  Calls the PHY specific link setup function and then calls the
5008  *  generic setup_copper_link to finish configuring the link for
5009  *  Lynxpoint PCH devices
5010  **/
5011 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5012 {
5013         u32 ctrl;
5014         s32 ret_val;
5015
5016         ctrl = er32(CTRL);
5017         ctrl |= E1000_CTRL_SLU;
5018         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5019         ew32(CTRL, ctrl);
5020
5021         ret_val = e1000_copper_link_setup_82577(hw);
5022         if (ret_val)
5023                 return ret_val;
5024
5025         return e1000e_setup_copper_link(hw);
5026 }
5027
5028 /**
5029  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5030  *  @hw: pointer to the HW structure
5031  *  @speed: pointer to store current link speed
5032  *  @duplex: pointer to store the current link duplex
5033  *
5034  *  Calls the generic get_speed_and_duplex to retrieve the current link
5035  *  information and then calls the Kumeran lock loss workaround for links at
5036  *  gigabit speeds.
5037  **/
5038 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5039                                           u16 *duplex)
5040 {
5041         s32 ret_val;
5042
5043         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5044         if (ret_val)
5045                 return ret_val;
5046
5047         if ((hw->mac.type == e1000_ich8lan) &&
5048             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5049                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5050         }
5051
5052         return ret_val;
5053 }
5054
5055 /**
5056  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5057  *  @hw: pointer to the HW structure
5058  *
5059  *  Work-around for 82566 Kumeran PCS lock loss:
5060  *  On link status change (i.e. PCI reset, speed change) and link is up and
5061  *  speed is gigabit-
5062  *    0) if workaround is optionally disabled do nothing
5063  *    1) wait 1ms for Kumeran link to come up
5064  *    2) check Kumeran Diagnostic register PCS lock loss bit
5065  *    3) if not set the link is locked (all is good), otherwise...
5066  *    4) reset the PHY
5067  *    5) repeat up to 10 times
5068  *  Note: this is only called for IGP3 copper when speed is 1gb.
5069  **/
5070 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5071 {
5072         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5073         u32 phy_ctrl;
5074         s32 ret_val;
5075         u16 i, data;
5076         bool link;
5077
5078         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5079                 return 0;
5080
5081         /* Make sure link is up before proceeding.  If not just return.
5082          * Attempting this while link is negotiating fouled up link
5083          * stability
5084          */
5085         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5086         if (!link)
5087                 return 0;
5088
5089         for (i = 0; i < 10; i++) {
5090                 /* read once to clear */
5091                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5092                 if (ret_val)
5093                         return ret_val;
5094                 /* and again to get new status */
5095                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5096                 if (ret_val)
5097                         return ret_val;
5098
5099                 /* check for PCS lock */
5100                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5101                         return 0;
5102
5103                 /* Issue PHY reset */
5104                 e1000_phy_hw_reset(hw);
5105                 mdelay(5);
5106         }
5107         /* Disable GigE link negotiation */
5108         phy_ctrl = er32(PHY_CTRL);
5109         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5110                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5111         ew32(PHY_CTRL, phy_ctrl);
5112
5113         /* Call gig speed drop workaround on Gig disable before accessing
5114          * any PHY registers
5115          */
5116         e1000e_gig_downshift_workaround_ich8lan(hw);
5117
5118         /* unable to acquire PCS lock */
5119         return -E1000_ERR_PHY;
5120 }
5121
5122 /**
5123  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5124  *  @hw: pointer to the HW structure
5125  *  @state: boolean value used to set the current Kumeran workaround state
5126  *
5127  *  If ICH8, set the current Kumeran workaround state (enabled - true
5128  *  /disabled - false).
5129  **/
5130 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5131                                                   bool state)
5132 {
5133         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5134
5135         if (hw->mac.type != e1000_ich8lan) {
5136                 e_dbg("Workaround applies to ICH8 only.\n");
5137                 return;
5138         }
5139
5140         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5141 }
5142
5143 /**
5144  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5145  *  @hw: pointer to the HW structure
5146  *
5147  *  Workaround for 82566 power-down on D3 entry:
5148  *    1) disable gigabit link
5149  *    2) write VR power-down enable
5150  *    3) read it back
5151  *  Continue if successful, else issue LCD reset and repeat
5152  **/
5153 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5154 {
5155         u32 reg;
5156         u16 data;
5157         u8 retry = 0;
5158
5159         if (hw->phy.type != e1000_phy_igp_3)
5160                 return;
5161
5162         /* Try the workaround twice (if needed) */
5163         do {
5164                 /* Disable link */
5165                 reg = er32(PHY_CTRL);
5166                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5167                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5168                 ew32(PHY_CTRL, reg);
5169
5170                 /* Call gig speed drop workaround on Gig disable before
5171                  * accessing any PHY registers
5172                  */
5173                 if (hw->mac.type == e1000_ich8lan)
5174                         e1000e_gig_downshift_workaround_ich8lan(hw);
5175
5176                 /* Write VR power-down enable */
5177                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5178                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5179                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5180
5181                 /* Read it back and test */
5182                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5183                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5184                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5185                         break;
5186
5187                 /* Issue PHY reset and repeat at most one more time */
5188                 reg = er32(CTRL);
5189                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5190                 retry++;
5191         } while (retry);
5192 }
5193
5194 /**
5195  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5196  *  @hw: pointer to the HW structure
5197  *
5198  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5199  *  LPLU, Gig disable, MDIC PHY reset):
5200  *    1) Set Kumeran Near-end loopback
5201  *    2) Clear Kumeran Near-end loopback
5202  *  Should only be called for ICH8[m] devices with any 1G Phy.
5203  **/
5204 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5205 {
5206         s32 ret_val;
5207         u16 reg_data;
5208
5209         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5210                 return;
5211
5212         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5213                                        &reg_data);
5214         if (ret_val)
5215                 return;
5216         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5217         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5218                                         reg_data);
5219         if (ret_val)
5220                 return;
5221         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5222         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5223 }
5224
5225 /**
5226  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5227  *  @hw: pointer to the HW structure
5228  *
5229  *  During S0 to Sx transition, it is possible the link remains at gig
5230  *  instead of negotiating to a lower speed.  Before going to Sx, set
5231  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5232  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5233  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5234  *  needs to be written.
5235  *  Parts that support (and are linked to a partner which support) EEE in
5236  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5237  *  than 10Mbps w/o EEE.
5238  **/
5239 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5240 {
5241         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5242         u32 phy_ctrl;
5243         s32 ret_val;
5244
5245         phy_ctrl = er32(PHY_CTRL);
5246         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5247
5248         if (hw->phy.type == e1000_phy_i217) {
5249                 u16 phy_reg, device_id = hw->adapter->pdev->device;
5250
5251                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5252                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5253                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5254                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5255                     (hw->mac.type == e1000_pch_spt)) {
5256                         u32 fextnvm6 = er32(FEXTNVM6);
5257
5258                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5259                 }
5260
5261                 ret_val = hw->phy.ops.acquire(hw);
5262                 if (ret_val)
5263                         goto out;
5264
5265                 if (!dev_spec->eee_disable) {
5266                         u16 eee_advert;
5267
5268                         ret_val =
5269                             e1000_read_emi_reg_locked(hw,
5270                                                       I217_EEE_ADVERTISEMENT,
5271                                                       &eee_advert);
5272                         if (ret_val)
5273                                 goto release;
5274
5275                         /* Disable LPLU if both link partners support 100BaseT
5276                          * EEE and 100Full is advertised on both ends of the
5277                          * link, and enable Auto Enable LPI since there will
5278                          * be no driver to enable LPI while in Sx.
5279                          */
5280                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5281                             (dev_spec->eee_lp_ability &
5282                              I82579_EEE_100_SUPPORTED) &&
5283                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5284                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5285                                               E1000_PHY_CTRL_NOND0A_LPLU);
5286
5287                                 /* Set Auto Enable LPI after link up */
5288                                 e1e_rphy_locked(hw,
5289                                                 I217_LPI_GPIO_CTRL, &phy_reg);
5290                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5291                                 e1e_wphy_locked(hw,
5292                                                 I217_LPI_GPIO_CTRL, phy_reg);
5293                         }
5294                 }
5295
5296                 /* For i217 Intel Rapid Start Technology support,
5297                  * when the system is going into Sx and no manageability engine
5298                  * is present, the driver must configure proxy to reset only on
5299                  * power good.  LPI (Low Power Idle) state must also reset only
5300                  * on power good, as well as the MTA (Multicast table array).
5301                  * The SMBus release must also be disabled on LCD reset.
5302                  */
5303                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5304                         /* Enable proxy to reset only on power good. */
5305                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5306                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5307                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5308
5309                         /* Set bit enable LPI (EEE) to reset only on
5310                          * power good.
5311                          */
5312                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5313                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5314                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5315
5316                         /* Disable the SMB release on LCD reset. */
5317                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5318                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5319                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5320                 }
5321
5322                 /* Enable MTA to reset for Intel Rapid Start Technology
5323                  * Support
5324                  */
5325                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5326                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5327                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5328
5329 release:
5330                 hw->phy.ops.release(hw);
5331         }
5332 out:
5333         ew32(PHY_CTRL, phy_ctrl);
5334
5335         if (hw->mac.type == e1000_ich8lan)
5336                 e1000e_gig_downshift_workaround_ich8lan(hw);
5337
5338         if (hw->mac.type >= e1000_pchlan) {
5339                 e1000_oem_bits_config_ich8lan(hw, false);
5340
5341                 /* Reset PHY to activate OEM bits on 82577/8 */
5342                 if (hw->mac.type == e1000_pchlan)
5343                         e1000e_phy_hw_reset_generic(hw);
5344
5345                 ret_val = hw->phy.ops.acquire(hw);
5346                 if (ret_val)
5347                         return;
5348                 e1000_write_smbus_addr(hw);
5349                 hw->phy.ops.release(hw);
5350         }
5351 }
5352
5353 /**
5354  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5355  *  @hw: pointer to the HW structure
5356  *
5357  *  During Sx to S0 transitions on non-managed devices or managed devices
5358  *  on which PHY resets are not blocked, if the PHY registers cannot be
5359  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5360  *  the PHY.
5361  *  On i217, setup Intel Rapid Start Technology.
5362  **/
5363 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5364 {
5365         s32 ret_val;
5366
5367         if (hw->mac.type < e1000_pch2lan)
5368                 return;
5369
5370         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5371         if (ret_val) {
5372                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5373                 return;
5374         }
5375
5376         /* For i217 Intel Rapid Start Technology support when the system
5377          * is transitioning from Sx and no manageability engine is present
5378          * configure SMBus to restore on reset, disable proxy, and enable
5379          * the reset on MTA (Multicast table array).
5380          */
5381         if (hw->phy.type == e1000_phy_i217) {
5382                 u16 phy_reg;
5383
5384                 ret_val = hw->phy.ops.acquire(hw);
5385                 if (ret_val) {
5386                         e_dbg("Failed to setup iRST\n");
5387                         return;
5388                 }
5389
5390                 /* Clear Auto Enable LPI after link up */
5391                 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5392                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5393                 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5394
5395                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5396                         /* Restore clear on SMB if no manageability engine
5397                          * is present
5398                          */
5399                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5400                         if (ret_val)
5401                                 goto release;
5402                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5403                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5404
5405                         /* Disable Proxy */
5406                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5407                 }
5408                 /* Enable reset on MTA */
5409                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5410                 if (ret_val)
5411                         goto release;
5412                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5413                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5414 release:
5415                 if (ret_val)
5416                         e_dbg("Error %d in resume workarounds\n", ret_val);
5417                 hw->phy.ops.release(hw);
5418         }
5419 }
5420
5421 /**
5422  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5423  *  @hw: pointer to the HW structure
5424  *
5425  *  Return the LED back to the default configuration.
5426  **/
5427 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5428 {
5429         if (hw->phy.type == e1000_phy_ife)
5430                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5431
5432         ew32(LEDCTL, hw->mac.ledctl_default);
5433         return 0;
5434 }
5435
5436 /**
5437  *  e1000_led_on_ich8lan - Turn LEDs on
5438  *  @hw: pointer to the HW structure
5439  *
5440  *  Turn on the LEDs.
5441  **/
5442 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5443 {
5444         if (hw->phy.type == e1000_phy_ife)
5445                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5446                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5447
5448         ew32(LEDCTL, hw->mac.ledctl_mode2);
5449         return 0;
5450 }
5451
5452 /**
5453  *  e1000_led_off_ich8lan - Turn LEDs off
5454  *  @hw: pointer to the HW structure
5455  *
5456  *  Turn off the LEDs.
5457  **/
5458 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5459 {
5460         if (hw->phy.type == e1000_phy_ife)
5461                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5462                                 (IFE_PSCL_PROBE_MODE |
5463                                  IFE_PSCL_PROBE_LEDS_OFF));
5464
5465         ew32(LEDCTL, hw->mac.ledctl_mode1);
5466         return 0;
5467 }
5468
5469 /**
5470  *  e1000_setup_led_pchlan - Configures SW controllable LED
5471  *  @hw: pointer to the HW structure
5472  *
5473  *  This prepares the SW controllable LED for use.
5474  **/
5475 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5476 {
5477         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5478 }
5479
5480 /**
5481  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5482  *  @hw: pointer to the HW structure
5483  *
5484  *  Return the LED back to the default configuration.
5485  **/
5486 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5487 {
5488         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5489 }
5490
5491 /**
5492  *  e1000_led_on_pchlan - Turn LEDs on
5493  *  @hw: pointer to the HW structure
5494  *
5495  *  Turn on the LEDs.
5496  **/
5497 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5498 {
5499         u16 data = (u16)hw->mac.ledctl_mode2;
5500         u32 i, led;
5501
5502         /* If no link, then turn LED on by setting the invert bit
5503          * for each LED that's mode is "link_up" in ledctl_mode2.
5504          */
5505         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5506                 for (i = 0; i < 3; i++) {
5507                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5508                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5509                             E1000_LEDCTL_MODE_LINK_UP)
5510                                 continue;
5511                         if (led & E1000_PHY_LED0_IVRT)
5512                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5513                         else
5514                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5515                 }
5516         }
5517
5518         return e1e_wphy(hw, HV_LED_CONFIG, data);
5519 }
5520
5521 /**
5522  *  e1000_led_off_pchlan - Turn LEDs off
5523  *  @hw: pointer to the HW structure
5524  *
5525  *  Turn off the LEDs.
5526  **/
5527 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5528 {
5529         u16 data = (u16)hw->mac.ledctl_mode1;
5530         u32 i, led;
5531
5532         /* If no link, then turn LED off by clearing the invert bit
5533          * for each LED that's mode is "link_up" in ledctl_mode1.
5534          */
5535         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5536                 for (i = 0; i < 3; i++) {
5537                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5538                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5539                             E1000_LEDCTL_MODE_LINK_UP)
5540                                 continue;
5541                         if (led & E1000_PHY_LED0_IVRT)
5542                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5543                         else
5544                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5545                 }
5546         }
5547
5548         return e1e_wphy(hw, HV_LED_CONFIG, data);
5549 }
5550
5551 /**
5552  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5553  *  @hw: pointer to the HW structure
5554  *
5555  *  Read appropriate register for the config done bit for completion status
5556  *  and configure the PHY through s/w for EEPROM-less parts.
5557  *
5558  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5559  *  config done bit, so only an error is logged and continues.  If we were
5560  *  to return with error, EEPROM-less silicon would not be able to be reset
5561  *  or change link.
5562  **/
5563 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5564 {
5565         s32 ret_val = 0;
5566         u32 bank = 0;
5567         u32 status;
5568
5569         e1000e_get_cfg_done_generic(hw);
5570
5571         /* Wait for indication from h/w that it has completed basic config */
5572         if (hw->mac.type >= e1000_ich10lan) {
5573                 e1000_lan_init_done_ich8lan(hw);
5574         } else {
5575                 ret_val = e1000e_get_auto_rd_done(hw);
5576                 if (ret_val) {
5577                         /* When auto config read does not complete, do not
5578                          * return with an error. This can happen in situations
5579                          * where there is no eeprom and prevents getting link.
5580                          */
5581                         e_dbg("Auto Read Done did not complete\n");
5582                         ret_val = 0;
5583                 }
5584         }
5585
5586         /* Clear PHY Reset Asserted bit */
5587         status = er32(STATUS);
5588         if (status & E1000_STATUS_PHYRA)
5589                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5590         else
5591                 e_dbg("PHY Reset Asserted not set - needs delay\n");
5592
5593         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5594         if (hw->mac.type <= e1000_ich9lan) {
5595                 if (!(er32(EECD) & E1000_EECD_PRES) &&
5596                     (hw->phy.type == e1000_phy_igp_3)) {
5597                         e1000e_phy_init_script_igp3(hw);
5598                 }
5599         } else {
5600                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5601                         /* Maybe we should do a basic PHY config */
5602                         e_dbg("EEPROM not present\n");
5603                         ret_val = -E1000_ERR_CONFIG;
5604                 }
5605         }
5606
5607         return ret_val;
5608 }
5609
5610 /**
5611  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5612  * @hw: pointer to the HW structure
5613  *
5614  * In the case of a PHY power down to save power, or to turn off link during a
5615  * driver unload, or wake on lan is not enabled, remove the link.
5616  **/
5617 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5618 {
5619         /* If the management interface is not enabled, then power down */
5620         if (!(hw->mac.ops.check_mng_mode(hw) ||
5621               hw->phy.ops.check_reset_block(hw)))
5622                 e1000_power_down_phy_copper(hw);
5623 }
5624
5625 /**
5626  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5627  *  @hw: pointer to the HW structure
5628  *
5629  *  Clears hardware counters specific to the silicon family and calls
5630  *  clear_hw_cntrs_generic to clear all general purpose counters.
5631  **/
5632 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5633 {
5634         u16 phy_data;
5635         s32 ret_val;
5636
5637         e1000e_clear_hw_cntrs_base(hw);
5638
5639         er32(ALGNERRC);
5640         er32(RXERRC);
5641         er32(TNCRS);
5642         er32(CEXTERR);
5643         er32(TSCTC);
5644         er32(TSCTFC);
5645
5646         er32(MGTPRC);
5647         er32(MGTPDC);
5648         er32(MGTPTC);
5649
5650         er32(IAC);
5651         er32(ICRXOC);
5652
5653         /* Clear PHY statistics registers */
5654         if ((hw->phy.type == e1000_phy_82578) ||
5655             (hw->phy.type == e1000_phy_82579) ||
5656             (hw->phy.type == e1000_phy_i217) ||
5657             (hw->phy.type == e1000_phy_82577)) {
5658                 ret_val = hw->phy.ops.acquire(hw);
5659                 if (ret_val)
5660                         return;
5661                 ret_val = hw->phy.ops.set_page(hw,
5662                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5663                 if (ret_val)
5664                         goto release;
5665                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5666                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5667                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5668                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5669                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5670                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5671                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5672                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5673                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5674                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5675                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5676                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5677                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5678                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5679 release:
5680                 hw->phy.ops.release(hw);
5681         }
5682 }
5683
5684 static const struct e1000_mac_operations ich8_mac_ops = {
5685         /* check_mng_mode dependent on mac type */
5686         .check_for_link         = e1000_check_for_copper_link_ich8lan,
5687         /* cleanup_led dependent on mac type */
5688         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
5689         .get_bus_info           = e1000_get_bus_info_ich8lan,
5690         .set_lan_id             = e1000_set_lan_id_single_port,
5691         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
5692         /* led_on dependent on mac type */
5693         /* led_off dependent on mac type */
5694         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
5695         .reset_hw               = e1000_reset_hw_ich8lan,
5696         .init_hw                = e1000_init_hw_ich8lan,
5697         .setup_link             = e1000_setup_link_ich8lan,
5698         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5699         /* id_led_init dependent on mac type */
5700         .config_collision_dist  = e1000e_config_collision_dist_generic,
5701         .rar_set                = e1000e_rar_set_generic,
5702         .rar_get_count          = e1000e_rar_get_count_generic,
5703 };
5704
5705 static const struct e1000_phy_operations ich8_phy_ops = {
5706         .acquire                = e1000_acquire_swflag_ich8lan,
5707         .check_reset_block      = e1000_check_reset_block_ich8lan,
5708         .commit                 = NULL,
5709         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
5710         .get_cable_length       = e1000e_get_cable_length_igp_2,
5711         .read_reg               = e1000e_read_phy_reg_igp,
5712         .release                = e1000_release_swflag_ich8lan,
5713         .reset                  = e1000_phy_hw_reset_ich8lan,
5714         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
5715         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
5716         .write_reg              = e1000e_write_phy_reg_igp,
5717 };
5718
5719 static const struct e1000_nvm_operations ich8_nvm_ops = {
5720         .acquire                = e1000_acquire_nvm_ich8lan,
5721         .read                   = e1000_read_nvm_ich8lan,
5722         .release                = e1000_release_nvm_ich8lan,
5723         .reload                 = e1000e_reload_nvm_generic,
5724         .update                 = e1000_update_nvm_checksum_ich8lan,
5725         .valid_led_default      = e1000_valid_led_default_ich8lan,
5726         .validate               = e1000_validate_nvm_checksum_ich8lan,
5727         .write                  = e1000_write_nvm_ich8lan,
5728 };
5729
5730 static const struct e1000_nvm_operations spt_nvm_ops = {
5731         .acquire                = e1000_acquire_nvm_ich8lan,
5732         .release                = e1000_release_nvm_ich8lan,
5733         .read                   = e1000_read_nvm_spt,
5734         .update                 = e1000_update_nvm_checksum_spt,
5735         .reload                 = e1000e_reload_nvm_generic,
5736         .valid_led_default      = e1000_valid_led_default_ich8lan,
5737         .validate               = e1000_validate_nvm_checksum_ich8lan,
5738         .write                  = e1000_write_nvm_ich8lan,
5739 };
5740
5741 const struct e1000_info e1000_ich8_info = {
5742         .mac                    = e1000_ich8lan,
5743         .flags                  = FLAG_HAS_WOL
5744                                   | FLAG_IS_ICH
5745                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5746                                   | FLAG_HAS_AMT
5747                                   | FLAG_HAS_FLASH
5748                                   | FLAG_APME_IN_WUC,
5749         .pba                    = 8,
5750         .max_hw_frame_size      = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5751         .get_variants           = e1000_get_variants_ich8lan,
5752         .mac_ops                = &ich8_mac_ops,
5753         .phy_ops                = &ich8_phy_ops,
5754         .nvm_ops                = &ich8_nvm_ops,
5755 };
5756
5757 const struct e1000_info e1000_ich9_info = {
5758         .mac                    = e1000_ich9lan,
5759         .flags                  = FLAG_HAS_JUMBO_FRAMES
5760                                   | FLAG_IS_ICH
5761                                   | FLAG_HAS_WOL
5762                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5763                                   | FLAG_HAS_AMT
5764                                   | FLAG_HAS_FLASH
5765                                   | FLAG_APME_IN_WUC,
5766         .pba                    = 18,
5767         .max_hw_frame_size      = DEFAULT_JUMBO,
5768         .get_variants           = e1000_get_variants_ich8lan,
5769         .mac_ops                = &ich8_mac_ops,
5770         .phy_ops                = &ich8_phy_ops,
5771         .nvm_ops                = &ich8_nvm_ops,
5772 };
5773
5774 const struct e1000_info e1000_ich10_info = {
5775         .mac                    = e1000_ich10lan,
5776         .flags                  = FLAG_HAS_JUMBO_FRAMES
5777                                   | FLAG_IS_ICH
5778                                   | FLAG_HAS_WOL
5779                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5780                                   | FLAG_HAS_AMT
5781                                   | FLAG_HAS_FLASH
5782                                   | FLAG_APME_IN_WUC,
5783         .pba                    = 18,
5784         .max_hw_frame_size      = DEFAULT_JUMBO,
5785         .get_variants           = e1000_get_variants_ich8lan,
5786         .mac_ops                = &ich8_mac_ops,
5787         .phy_ops                = &ich8_phy_ops,
5788         .nvm_ops                = &ich8_nvm_ops,
5789 };
5790
5791 const struct e1000_info e1000_pch_info = {
5792         .mac                    = e1000_pchlan,
5793         .flags                  = FLAG_IS_ICH
5794                                   | FLAG_HAS_WOL
5795                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5796                                   | FLAG_HAS_AMT
5797                                   | FLAG_HAS_FLASH
5798                                   | FLAG_HAS_JUMBO_FRAMES
5799                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5800                                   | FLAG_APME_IN_WUC,
5801         .flags2                 = FLAG2_HAS_PHY_STATS,
5802         .pba                    = 26,
5803         .max_hw_frame_size      = 4096,
5804         .get_variants           = e1000_get_variants_ich8lan,
5805         .mac_ops                = &ich8_mac_ops,
5806         .phy_ops                = &ich8_phy_ops,
5807         .nvm_ops                = &ich8_nvm_ops,
5808 };
5809
5810 const struct e1000_info e1000_pch2_info = {
5811         .mac                    = e1000_pch2lan,
5812         .flags                  = FLAG_IS_ICH
5813                                   | FLAG_HAS_WOL
5814                                   | FLAG_HAS_HW_TIMESTAMP
5815                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5816                                   | FLAG_HAS_AMT
5817                                   | FLAG_HAS_FLASH
5818                                   | FLAG_HAS_JUMBO_FRAMES
5819                                   | FLAG_APME_IN_WUC,
5820         .flags2                 = FLAG2_HAS_PHY_STATS
5821                                   | FLAG2_HAS_EEE,
5822         .pba                    = 26,
5823         .max_hw_frame_size      = 9022,
5824         .get_variants           = e1000_get_variants_ich8lan,
5825         .mac_ops                = &ich8_mac_ops,
5826         .phy_ops                = &ich8_phy_ops,
5827         .nvm_ops                = &ich8_nvm_ops,
5828 };
5829
5830 const struct e1000_info e1000_pch_lpt_info = {
5831         .mac                    = e1000_pch_lpt,
5832         .flags                  = FLAG_IS_ICH
5833                                   | FLAG_HAS_WOL
5834                                   | FLAG_HAS_HW_TIMESTAMP
5835                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5836                                   | FLAG_HAS_AMT
5837                                   | FLAG_HAS_FLASH
5838                                   | FLAG_HAS_JUMBO_FRAMES
5839                                   | FLAG_APME_IN_WUC,
5840         .flags2                 = FLAG2_HAS_PHY_STATS
5841                                   | FLAG2_HAS_EEE,
5842         .pba                    = 26,
5843         .max_hw_frame_size      = 9022,
5844         .get_variants           = e1000_get_variants_ich8lan,
5845         .mac_ops                = &ich8_mac_ops,
5846         .phy_ops                = &ich8_phy_ops,
5847         .nvm_ops                = &ich8_nvm_ops,
5848 };
5849
5850 const struct e1000_info e1000_pch_spt_info = {
5851         .mac                    = e1000_pch_spt,
5852         .flags                  = FLAG_IS_ICH
5853                                   | FLAG_HAS_WOL
5854                                   | FLAG_HAS_HW_TIMESTAMP
5855                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5856                                   | FLAG_HAS_AMT
5857                                   | FLAG_HAS_FLASH
5858                                   | FLAG_HAS_JUMBO_FRAMES
5859                                   | FLAG_APME_IN_WUC,
5860         .flags2                 = FLAG2_HAS_PHY_STATS
5861                                   | FLAG2_HAS_EEE,
5862         .pba                    = 26,
5863         .max_hw_frame_size      = 9022,
5864         .get_variants           = e1000_get_variants_ich8lan,
5865         .mac_ops                = &ich8_mac_ops,
5866         .phy_ops                = &ich8_phy_ops,
5867         .nvm_ops                = &spt_nvm_ops,
5868 };