kernel/drivers/net/ethernet/intel/e1000e/80003es2lan.c

   1 /* Intel PRO/1000 Linux driver
   2  * Copyright(c) 1999 - 2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * The full GNU General Public License is included in this distribution in
  14  * the file called "COPYING".
  15  *
  16  * Contact Information:
  17  * Linux NICS <linux.nics@intel.com>
  18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20  */
  21
  22 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
  23  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  24  */
  25
  26 #include "e1000.h"
  27
  28 /* A table for the GG82563 cable length where the range is defined
  29  * with a lower bound at "index" and the upper bound at
  30  * "index + 5".
  31  */
  32 static const u16 e1000_gg82563_cable_length_table[] = {
  33         0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF
  34 };
  35
  36 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
  37                 ARRAY_SIZE(e1000_gg82563_cable_length_table)
  38
  39 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
  40 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  41 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  42 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
  43 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
  44 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
  45 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
  46 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  47                                            u16 *data);
  48 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  49                                             u16 data);
  50 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
  51
  52 /**
  53  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
  54  *  @hw: pointer to the HW structure
  55  **/
  56 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
  57 {
  58         struct e1000_phy_info *phy = &hw->phy;
  59         s32 ret_val;
  60
  61         if (hw->phy.media_type != e1000_media_type_copper) {
  62                 phy->type = e1000_phy_none;
  63                 return 0;
  64         } else {
  65                 phy->ops.power_up = e1000_power_up_phy_copper;
  66                 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
  67         }
  68
  69         phy->addr = 1;
  70         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  71         phy->reset_delay_us = 100;
  72         phy->type = e1000_phy_gg82563;
  73
  74         /* This can only be done after all function pointers are setup. */
  75         ret_val = e1000e_get_phy_id(hw);
  76
  77         /* Verify phy id */
  78         if (phy->id != GG82563_E_PHY_ID)
  79                 return -E1000_ERR_PHY;
  80
  81         return ret_val;
  82 }
  83
  84 /**
  85  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
  86  *  @hw: pointer to the HW structure
  87  **/
  88 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
  89 {
  90         struct e1000_nvm_info *nvm = &hw->nvm;
  91         u32 eecd = er32(EECD);
  92         u16 size;
  93
  94         nvm->opcode_bits = 8;
  95         nvm->delay_usec = 1;
  96         switch (nvm->override) {
  97         case e1000_nvm_override_spi_large:
  98                 nvm->page_size = 32;
  99                 nvm->address_bits = 16;
 100                 break;
 101         case e1000_nvm_override_spi_small:
 102                 nvm->page_size = 8;
 103                 nvm->address_bits = 8;
 104                 break;
 105         default:
 106                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 107                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 108                 break;
 109         }
 110
 111         nvm->type = e1000_nvm_eeprom_spi;
 112
 113         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 114                      E1000_EECD_SIZE_EX_SHIFT);
 115
 116         /* Added to a constant, "size" becomes the left-shift value
 117          * for setting word_size.
 118          */
 119         size += NVM_WORD_SIZE_BASE_SHIFT;
 120
 121         /* EEPROM access above 16k is unsupported */
 122         if (size > 14)
 123                 size = 14;
 124         nvm->word_size = 1 << size;
 125
 126         return 0;
 127 }
 128
 129 /**
 130  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 131  *  @hw: pointer to the HW structure
 132  **/
 133 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 134 {
 135         struct e1000_mac_info *mac = &hw->mac;
 136
 137         /* Set media type and media-dependent function pointers */
 138         switch (hw->adapter->pdev->device) {
 139         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 140                 hw->phy.media_type = e1000_media_type_internal_serdes;
 141                 mac->ops.check_for_link = e1000e_check_for_serdes_link;
 142                 mac->ops.setup_physical_interface =
 143                     e1000e_setup_fiber_serdes_link;
 144                 break;
 145         default:
 146                 hw->phy.media_type = e1000_media_type_copper;
 147                 mac->ops.check_for_link = e1000e_check_for_copper_link;
 148                 mac->ops.setup_physical_interface =
 149                     e1000_setup_copper_link_80003es2lan;
 150                 break;
 151         }
 152
 153         /* Set mta register count */
 154         mac->mta_reg_count = 128;
 155         /* Set rar entry count */
 156         mac->rar_entry_count = E1000_RAR_ENTRIES;
 157         /* FWSM register */
 158         mac->has_fwsm = true;
 159         /* ARC supported; valid only if manageability features are enabled. */
 160         mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
 161         /* Adaptive IFS not supported */
 162         mac->adaptive_ifs = false;
 163
 164         /* set lan id for port to determine which phy lock to use */
 165         hw->mac.ops.set_lan_id(hw);
 166
 167         return 0;
 168 }
 169
 170 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
 171 {
 172         struct e1000_hw *hw = &adapter->hw;
 173         s32 rc;
 174
 175         rc = e1000_init_mac_params_80003es2lan(hw);
 176         if (rc)
 177                 return rc;
 178
 179         rc = e1000_init_nvm_params_80003es2lan(hw);
 180         if (rc)
 181                 return rc;
 182
 183         rc = e1000_init_phy_params_80003es2lan(hw);
 184         if (rc)
 185                 return rc;
 186
 187         return 0;
 188 }
 189
 190 /**
 191  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 192  *  @hw: pointer to the HW structure
 193  *
 194  *  A wrapper to acquire access rights to the correct PHY.
 195  **/
 196 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 197 {
 198         u16 mask;
 199
 200         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 201         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 202 }
 203
 204 /**
 205  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 206  *  @hw: pointer to the HW structure
 207  *
 208  *  A wrapper to release access rights to the correct PHY.
 209  **/
 210 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 211 {
 212         u16 mask;
 213
 214         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 215         e1000_release_swfw_sync_80003es2lan(hw, mask);
 216 }
 217
 218 /**
 219  *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
 220  *  @hw: pointer to the HW structure
 221  *
 222  *  Acquire the semaphore to access the Kumeran interface.
 223  *
 224  **/
 225 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 226 {
 227         u16 mask;
 228
 229         mask = E1000_SWFW_CSR_SM;
 230
 231         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 232 }
 233
 234 /**
 235  *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
 236  *  @hw: pointer to the HW structure
 237  *
 238  *  Release the semaphore used to access the Kumeran interface
 239  **/
 240 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 241 {
 242         u16 mask;
 243
 244         mask = E1000_SWFW_CSR_SM;
 245
 246         e1000_release_swfw_sync_80003es2lan(hw, mask);
 247 }
 248
 249 /**
 250  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 251  *  @hw: pointer to the HW structure
 252  *
 253  *  Acquire the semaphore to access the EEPROM.
 254  **/
 255 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 256 {
 257         s32 ret_val;
 258
 259         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 260         if (ret_val)
 261                 return ret_val;
 262
 263         ret_val = e1000e_acquire_nvm(hw);
 264
 265         if (ret_val)
 266                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 267
 268         return ret_val;
 269 }
 270
 271 /**
 272  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 273  *  @hw: pointer to the HW structure
 274  *
 275  *  Release the semaphore used to access the EEPROM.
 276  **/
 277 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 278 {
 279         e1000e_release_nvm(hw);
 280         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 281 }
 282
 283 /**
 284  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 285  *  @hw: pointer to the HW structure
 286  *  @mask: specifies which semaphore to acquire
 287  *
 288  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 289  *  will also specify which port we're acquiring the lock for.
 290  **/
 291 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 292 {
 293         u32 swfw_sync;
 294         u32 swmask = mask;
 295         u32 fwmask = mask << 16;
 296         s32 i = 0;
 297         s32 timeout = 50;
 298
 299         while (i < timeout) {
 300                 if (e1000e_get_hw_semaphore(hw))
 301                         return -E1000_ERR_SWFW_SYNC;
 302
 303                 swfw_sync = er32(SW_FW_SYNC);
 304                 if (!(swfw_sync & (fwmask | swmask)))
 305                         break;
 306
 307                 /* Firmware currently using resource (fwmask)
 308                  * or other software thread using resource (swmask)
 309                  */
 310                 e1000e_put_hw_semaphore(hw);
 311                 mdelay(5);
 312                 i++;
 313         }
 314
 315         if (i == timeout) {
 316                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
 317                 return -E1000_ERR_SWFW_SYNC;
 318         }
 319
 320         swfw_sync |= swmask;
 321         ew32(SW_FW_SYNC, swfw_sync);
 322
 323         e1000e_put_hw_semaphore(hw);
 324
 325         return 0;
 326 }
 327
 328 /**
 329  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 330  *  @hw: pointer to the HW structure
 331  *  @mask: specifies which semaphore to acquire
 332  *
 333  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 334  *  will also specify which port we're releasing the lock for.
 335  **/
 336 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 337 {
 338         u32 swfw_sync;
 339
 340         while (e1000e_get_hw_semaphore(hw) != 0)
 341                 ; /* Empty */
 342
 343         swfw_sync = er32(SW_FW_SYNC);
 344         swfw_sync &= ~mask;
 345         ew32(SW_FW_SYNC, swfw_sync);
 346
 347         e1000e_put_hw_semaphore(hw);
 348 }
 349
 350 /**
 351  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 352  *  @hw: pointer to the HW structure
 353  *  @offset: offset of the register to read
 354  *  @data: pointer to the data returned from the operation
 355  *
 356  *  Read the GG82563 PHY register.
 357  **/
 358 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 359                                                   u32 offset, u16 *data)
 360 {
 361         s32 ret_val;
 362         u32 page_select;
 363         u16 temp;
 364
 365         ret_val = e1000_acquire_phy_80003es2lan(hw);
 366         if (ret_val)
 367                 return ret_val;
 368
 369         /* Select Configuration Page */
 370         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 371                 page_select = GG82563_PHY_PAGE_SELECT;
 372         } else {
 373                 /* Use Alternative Page Select register to access
 374                  * registers 30 and 31
 375                  */
 376                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 377         }
 378
 379         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 380         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 381         if (ret_val) {
 382                 e1000_release_phy_80003es2lan(hw);
 383                 return ret_val;
 384         }
 385
 386         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
 387                 /* The "ready" bit in the MDIC register may be incorrectly set
 388                  * before the device has completed the "Page Select" MDI
 389                  * transaction.  So we wait 200us after each MDI command...
 390                  */
 391                 usleep_range(200, 400);
 392
 393                 /* ...and verify the command was successful. */
 394                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 395
 396                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 397                         e1000_release_phy_80003es2lan(hw);
 398                         return -E1000_ERR_PHY;
 399                 }
 400
 401                 usleep_range(200, 400);
 402
 403                 ret_val = e1000e_read_phy_reg_mdic(hw,
 404                                                    MAX_PHY_REG_ADDRESS & offset,
 405                                                    data);
 406
 407                 usleep_range(200, 400);
 408         } else {
 409                 ret_val = e1000e_read_phy_reg_mdic(hw,
 410                                                    MAX_PHY_REG_ADDRESS & offset,
 411                                                    data);
 412         }
 413
 414         e1000_release_phy_80003es2lan(hw);
 415
 416         return ret_val;
 417 }
 418
 419 /**
 420  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 421  *  @hw: pointer to the HW structure
 422  *  @offset: offset of the register to read
 423  *  @data: value to write to the register
 424  *
 425  *  Write to the GG82563 PHY register.
 426  **/
 427 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 428                                                    u32 offset, u16 data)
 429 {
 430         s32 ret_val;
 431         u32 page_select;
 432         u16 temp;
 433
 434         ret_val = e1000_acquire_phy_80003es2lan(hw);
 435         if (ret_val)
 436                 return ret_val;
 437
 438         /* Select Configuration Page */
 439         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 440                 page_select = GG82563_PHY_PAGE_SELECT;
 441         } else {
 442                 /* Use Alternative Page Select register to access
 443                  * registers 30 and 31
 444                  */
 445                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 446         }
 447
 448         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 449         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 450         if (ret_val) {
 451                 e1000_release_phy_80003es2lan(hw);
 452                 return ret_val;
 453         }
 454
 455         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
 456                 /* The "ready" bit in the MDIC register may be incorrectly set
 457                  * before the device has completed the "Page Select" MDI
 458                  * transaction.  So we wait 200us after each MDI command...
 459                  */
 460                 usleep_range(200, 400);
 461
 462                 /* ...and verify the command was successful. */
 463                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 464
 465                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 466                         e1000_release_phy_80003es2lan(hw);
 467                         return -E1000_ERR_PHY;
 468                 }
 469
 470                 usleep_range(200, 400);
 471
 472                 ret_val = e1000e_write_phy_reg_mdic(hw,
 473                                                     MAX_PHY_REG_ADDRESS &
 474                                                     offset, data);
 475
 476                 usleep_range(200, 400);
 477         } else {
 478                 ret_val = e1000e_write_phy_reg_mdic(hw,
 479                                                     MAX_PHY_REG_ADDRESS &
 480                                                     offset, data);
 481         }
 482
 483         e1000_release_phy_80003es2lan(hw);
 484
 485         return ret_val;
 486 }
 487
 488 /**
 489  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 490  *  @hw: pointer to the HW structure
 491  *  @offset: offset of the register to read
 492  *  @words: number of words to write
 493  *  @data: buffer of data to write to the NVM
 494  *
 495  *  Write "words" of data to the ESB2 NVM.
 496  **/
 497 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 498                                        u16 words, u16 *data)
 499 {
 500         return e1000e_write_nvm_spi(hw, offset, words, data);
 501 }
 502
 503 /**
 504  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 505  *  @hw: pointer to the HW structure
 506  *
 507  *  Wait a specific amount of time for manageability processes to complete.
 508  *  This is a function pointer entry point called by the phy module.
 509  **/
 510 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 511 {
 512         s32 timeout = PHY_CFG_TIMEOUT;
 513         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 514
 515         if (hw->bus.func == 1)
 516                 mask = E1000_NVM_CFG_DONE_PORT_1;
 517
 518         while (timeout) {
 519                 if (er32(EEMNGCTL) & mask)
 520                         break;
 521                 usleep_range(1000, 2000);
 522                 timeout--;
 523         }
 524         if (!timeout) {
 525                 e_dbg("MNG configuration cycle has not completed.\n");
 526                 return -E1000_ERR_RESET;
 527         }
 528
 529         return 0;
 530 }
 531
 532 /**
 533  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 534  *  @hw: pointer to the HW structure
 535  *
 536  *  Force the speed and duplex settings onto the PHY.  This is a
 537  *  function pointer entry point called by the phy module.
 538  **/
 539 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 540 {
 541         s32 ret_val;
 542         u16 phy_data;
 543         bool link;
 544
 545         /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 546          * forced whenever speed and duplex are forced.
 547          */
 548         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 549         if (ret_val)
 550                 return ret_val;
 551
 552         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 553         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 554         if (ret_val)
 555                 return ret_val;
 556
 557         e_dbg("GG82563 PSCR: %X\n", phy_data);
 558
 559         ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
 560         if (ret_val)
 561                 return ret_val;
 562
 563         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 564
 565         /* Reset the phy to commit changes. */
 566         phy_data |= BMCR_RESET;
 567
 568         ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
 569         if (ret_val)
 570                 return ret_val;
 571
 572         udelay(1);
 573
 574         if (hw->phy.autoneg_wait_to_complete) {
 575                 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
 576
 577                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 578                                                       100000, &link);
 579                 if (ret_val)
 580                         return ret_val;
 581
 582                 if (!link) {
 583                         /* We didn't get link.
 584                          * Reset the DSP and cross our fingers.
 585                          */
 586                         ret_val = e1000e_phy_reset_dsp(hw);
 587                         if (ret_val)
 588                                 return ret_val;
 589                 }
 590
 591                 /* Try once more */
 592                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 593                                                       100000, &link);
 594                 if (ret_val)
 595                         return ret_val;
 596         }
 597
 598         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 599         if (ret_val)
 600                 return ret_val;
 601
 602         /* Resetting the phy means we need to verify the TX_CLK corresponds
 603          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 604          */
 605         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 606         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 607                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 608         else
 609                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 610
 611         /* In addition, we must re-enable CRS on Tx for both half and full
 612          * duplex.
 613          */
 614         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 615         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 616
 617         return ret_val;
 618 }
 619
 620 /**
 621  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 622  *  @hw: pointer to the HW structure
 623  *
 624  *  Find the approximate cable length as measured by the GG82563 PHY.
 625  *  This is a function pointer entry point called by the phy module.
 626  **/
 627 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 628 {
 629         struct e1000_phy_info *phy = &hw->phy;
 630         s32 ret_val;
 631         u16 phy_data, index;
 632
 633         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 634         if (ret_val)
 635                 return ret_val;
 636
 637         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 638
 639         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
 640                 return -E1000_ERR_PHY;
 641
 642         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 643         phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
 644
 645         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 646
 647         return 0;
 648 }
 649
 650 /**
 651  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 652  *  @hw: pointer to the HW structure
 653  *  @speed: pointer to speed buffer
 654  *  @duplex: pointer to duplex buffer
 655  *
 656  *  Retrieve the current speed and duplex configuration.
 657  **/
 658 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 659                                               u16 *duplex)
 660 {
 661         s32 ret_val;
 662
 663         if (hw->phy.media_type == e1000_media_type_copper) {
 664                 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
 665                 hw->phy.ops.cfg_on_link_up(hw);
 666         } else {
 667                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 668                                                                    speed,
 669                                                                    duplex);
 670         }
 671
 672         return ret_val;
 673 }
 674
 675 /**
 676  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 677  *  @hw: pointer to the HW structure
 678  *
 679  *  Perform a global reset to the ESB2 controller.
 680  **/
 681 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 682 {
 683         u32 ctrl;
 684         s32 ret_val;
 685         u16 kum_reg_data;
 686
 687         /* Prevent the PCI-E bus from sticking if there is no TLP connection
 688          * on the last TLP read/write transaction when MAC is reset.
 689          */
 690         ret_val = e1000e_disable_pcie_master(hw);
 691         if (ret_val)
 692                 e_dbg("PCI-E Master disable polling has failed.\n");
 693
 694         e_dbg("Masking off all interrupts\n");
 695         ew32(IMC, 0xffffffff);
 696
 697         ew32(RCTL, 0);
 698         ew32(TCTL, E1000_TCTL_PSP);
 699         e1e_flush();
 700
 701         usleep_range(10000, 20000);
 702
 703         ctrl = er32(CTRL);
 704
 705         ret_val = e1000_acquire_phy_80003es2lan(hw);
 706         if (ret_val)
 707                 return ret_val;
 708
 709         e_dbg("Issuing a global reset to MAC\n");
 710         ew32(CTRL, ctrl | E1000_CTRL_RST);
 711         e1000_release_phy_80003es2lan(hw);
 712
 713         /* Disable IBIST slave mode (far-end loopback) */
 714         ret_val =
 715             e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 716                                             &kum_reg_data);
 717         if (ret_val)
 718                 return ret_val;
 719         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 720         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 721                                          kum_reg_data);
 722
 723         ret_val = e1000e_get_auto_rd_done(hw);
 724         if (ret_val)
 725                 /* We don't want to continue accessing MAC registers. */
 726                 return ret_val;
 727
 728         /* Clear any pending interrupt events. */
 729         ew32(IMC, 0xffffffff);
 730         er32(ICR);
 731
 732         return e1000_check_alt_mac_addr_generic(hw);
 733 }
 734
 735 /**
 736  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 737  *  @hw: pointer to the HW structure
 738  *
 739  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 740  **/
 741 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 742 {
 743         struct e1000_mac_info *mac = &hw->mac;
 744         u32 reg_data;
 745         s32 ret_val;
 746         u16 kum_reg_data;
 747         u16 i;
 748
 749         e1000_initialize_hw_bits_80003es2lan(hw);
 750
 751         /* Initialize identification LED */
 752         ret_val = mac->ops.id_led_init(hw);
 753         /* An error is not fatal and we should not stop init due to this */
 754         if (ret_val)
 755                 e_dbg("Error initializing identification LED\n");
 756
 757         /* Disabling VLAN filtering */
 758         e_dbg("Initializing the IEEE VLAN\n");
 759         mac->ops.clear_vfta(hw);
 760
 761         /* Setup the receive address. */
 762         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 763
 764         /* Zero out the Multicast HASH table */
 765         e_dbg("Zeroing the MTA\n");
 766         for (i = 0; i < mac->mta_reg_count; i++)
 767                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 768
 769         /* Setup link and flow control */
 770         ret_val = mac->ops.setup_link(hw);
 771         if (ret_val)
 772                 return ret_val;
 773
 774         /* Disable IBIST slave mode (far-end loopback) */
 775         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 776                                         &kum_reg_data);
 777         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 778         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 779                                          kum_reg_data);
 780
 781         /* Set the transmit descriptor write-back policy */
 782         reg_data = er32(TXDCTL(0));
 783         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
 784                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
 785         ew32(TXDCTL(0), reg_data);
 786
 787         /* ...for both queues. */
 788         reg_data = er32(TXDCTL(1));
 789         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
 790                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
 791         ew32(TXDCTL(1), reg_data);
 792
 793         /* Enable retransmit on late collisions */
 794         reg_data = er32(TCTL);
 795         reg_data |= E1000_TCTL_RTLC;
 796         ew32(TCTL, reg_data);
 797
 798         /* Configure Gigabit Carry Extend Padding */
 799         reg_data = er32(TCTL_EXT);
 800         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 801         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 802         ew32(TCTL_EXT, reg_data);
 803
 804         /* Configure Transmit Inter-Packet Gap */
 805         reg_data = er32(TIPG);
 806         reg_data &= ~E1000_TIPG_IPGT_MASK;
 807         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 808         ew32(TIPG, reg_data);
 809
 810         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 811         reg_data &= ~0x00100000;
 812         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 813
 814         /* default to true to enable the MDIC W/A */
 815         hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
 816
 817         ret_val =
 818             e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
 819                                             E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
 820         if (!ret_val) {
 821                 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 822                     E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
 823                         hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
 824         }
 825
 826         /* Clear all of the statistics registers (clear on read).  It is
 827          * important that we do this after we have tried to establish link
 828          * because the symbol error count will increment wildly if there
 829          * is no link.
 830          */
 831         e1000_clear_hw_cntrs_80003es2lan(hw);
 832
 833         return ret_val;
 834 }
 835
 836 /**
 837  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 838  *  @hw: pointer to the HW structure
 839  *
 840  *  Initializes required hardware-dependent bits needed for normal operation.
 841  **/
 842 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 843 {
 844         u32 reg;
 845
 846         /* Transmit Descriptor Control 0 */
 847         reg = er32(TXDCTL(0));
 848         reg |= (1 << 22);
 849         ew32(TXDCTL(0), reg);
 850
 851         /* Transmit Descriptor Control 1 */
 852         reg = er32(TXDCTL(1));
 853         reg |= (1 << 22);
 854         ew32(TXDCTL(1), reg);
 855
 856         /* Transmit Arbitration Control 0 */
 857         reg = er32(TARC(0));
 858         reg &= ~(0xF << 27);    /* 30:27 */
 859         if (hw->phy.media_type != e1000_media_type_copper)
 860                 reg &= ~(1 << 20);
 861         ew32(TARC(0), reg);
 862
 863         /* Transmit Arbitration Control 1 */
 864         reg = er32(TARC(1));
 865         if (er32(TCTL) & E1000_TCTL_MULR)
 866                 reg &= ~(1 << 28);
 867         else
 868                 reg |= (1 << 28);
 869         ew32(TARC(1), reg);
 870
 871         /* Disable IPv6 extension header parsing because some malformed
 872          * IPv6 headers can hang the Rx.
 873          */
 874         reg = er32(RFCTL);
 875         reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
 876         ew32(RFCTL, reg);
 877 }
 878
 879 /**
 880  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 881  *  @hw: pointer to the HW structure
 882  *
 883  *  Setup some GG82563 PHY registers for obtaining link
 884  **/
 885 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 886 {
 887         struct e1000_phy_info *phy = &hw->phy;
 888         s32 ret_val;
 889         u32 reg;
 890         u16 data;
 891
 892         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 893         if (ret_val)
 894                 return ret_val;
 895
 896         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 897         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 898         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 899
 900         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 901         if (ret_val)
 902                 return ret_val;
 903
 904         /* Options:
 905          *   MDI/MDI-X = 0 (default)
 906          *   0 - Auto for all speeds
 907          *   1 - MDI mode
 908          *   2 - MDI-X mode
 909          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 910          */
 911         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 912         if (ret_val)
 913                 return ret_val;
 914
 915         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 916
 917         switch (phy->mdix) {
 918         case 1:
 919                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 920                 break;
 921         case 2:
 922                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 923                 break;
 924         case 0:
 925         default:
 926                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 927                 break;
 928         }
 929
 930         /* Options:
 931          *   disable_polarity_correction = 0 (default)
 932          *       Automatic Correction for Reversed Cable Polarity
 933          *   0 - Disabled
 934          *   1 - Enabled
 935          */
 936         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 937         if (phy->disable_polarity_correction)
 938                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 939
 940         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
 941         if (ret_val)
 942                 return ret_val;
 943
 944         /* SW Reset the PHY so all changes take effect */
 945         ret_val = hw->phy.ops.commit(hw);
 946         if (ret_val) {
 947                 e_dbg("Error Resetting the PHY\n");
 948                 return ret_val;
 949         }
 950
 951         /* Bypass Rx and Tx FIFO's */
 952         reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
 953         data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
 954                 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
 955         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
 956         if (ret_val)
 957                 return ret_val;
 958
 959         reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
 960         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
 961         if (ret_val)
 962                 return ret_val;
 963         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
 964         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
 965         if (ret_val)
 966                 return ret_val;
 967
 968         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
 969         if (ret_val)
 970                 return ret_val;
 971
 972         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
 973         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
 974         if (ret_val)
 975                 return ret_val;
 976
 977         reg = er32(CTRL_EXT);
 978         reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
 979         ew32(CTRL_EXT, reg);
 980
 981         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
 982         if (ret_val)
 983                 return ret_val;
 984
 985         /* Do not init these registers when the HW is in IAMT mode, since the
 986          * firmware will have already initialized them.  We only initialize
 987          * them if the HW is not in IAMT mode.
 988          */
 989         if (!hw->mac.ops.check_mng_mode(hw)) {
 990                 /* Enable Electrical Idle on the PHY */
 991                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
 992                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
 993                 if (ret_val)
 994                         return ret_val;
 995
 996                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
 997                 if (ret_val)
 998                         return ret_val;
 999
1000                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1001                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1002                 if (ret_val)
1003                         return ret_val;
1004         }
1005
1006         /* Workaround: Disable padding in Kumeran interface in the MAC
1007          * and in the PHY to avoid CRC errors.
1008          */
1009         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1010         if (ret_val)
1011                 return ret_val;
1012
1013         data |= GG82563_ICR_DIS_PADDING;
1014         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1015         if (ret_val)
1016                 return ret_val;
1017
1018         return 0;
1019 }
1020
1021 /**
1022  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1023  *  @hw: pointer to the HW structure
1024  *
1025  *  Essentially a wrapper for setting up all things "copper" related.
1026  *  This is a function pointer entry point called by the mac module.
1027  **/
1028 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1029 {
1030         u32 ctrl;
1031         s32 ret_val;
1032         u16 reg_data;
1033
1034         ctrl = er32(CTRL);
1035         ctrl |= E1000_CTRL_SLU;
1036         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1037         ew32(CTRL, ctrl);
1038
1039         /* Set the mac to wait the maximum time between each
1040          * iteration and increase the max iterations when
1041          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1042          */
1043         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1044                                                    0xFFFF);
1045         if (ret_val)
1046                 return ret_val;
1047         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1048                                                   &reg_data);
1049         if (ret_val)
1050                 return ret_val;
1051         reg_data |= 0x3F;
1052         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1053                                                    reg_data);
1054         if (ret_val)
1055                 return ret_val;
1056         ret_val =
1057             e1000_read_kmrn_reg_80003es2lan(hw,
1058                                             E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1059                                             &reg_data);
1060         if (ret_val)
1061                 return ret_val;
1062         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1063         ret_val =
1064             e1000_write_kmrn_reg_80003es2lan(hw,
1065                                              E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1066                                              reg_data);
1067         if (ret_val)
1068                 return ret_val;
1069
1070         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1071         if (ret_val)
1072                 return ret_val;
1073
1074         return e1000e_setup_copper_link(hw);
1075 }
1076
1077 /**
1078  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1079  *  @hw: pointer to the HW structure
1080  *  @duplex: current duplex setting
1081  *
1082  *  Configure the KMRN interface by applying last minute quirks for
1083  *  10/100 operation.
1084  **/
1085 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1086 {
1087         s32 ret_val = 0;
1088         u16 speed;
1089         u16 duplex;
1090
1091         if (hw->phy.media_type == e1000_media_type_copper) {
1092                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1093                                                              &duplex);
1094                 if (ret_val)
1095                         return ret_val;
1096
1097                 if (speed == SPEED_1000)
1098                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1099                 else
1100                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1101         }
1102
1103         return ret_val;
1104 }
1105
1106 /**
1107  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1108  *  @hw: pointer to the HW structure
1109  *  @duplex: current duplex setting
1110  *
1111  *  Configure the KMRN interface by applying last minute quirks for
1112  *  10/100 operation.
1113  **/
1114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1115 {
1116         s32 ret_val;
1117         u32 tipg;
1118         u32 i = 0;
1119         u16 reg_data, reg_data2;
1120
1121         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1122         ret_val =
1123             e1000_write_kmrn_reg_80003es2lan(hw,
1124                                              E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1125                                              reg_data);
1126         if (ret_val)
1127                 return ret_val;
1128
1129         /* Configure Transmit Inter-Packet Gap */
1130         tipg = er32(TIPG);
1131         tipg &= ~E1000_TIPG_IPGT_MASK;
1132         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1133         ew32(TIPG, tipg);
1134
1135         do {
1136                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1137                 if (ret_val)
1138                         return ret_val;
1139
1140                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1141                 if (ret_val)
1142                         return ret_val;
1143                 i++;
1144         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1145
1146         if (duplex == HALF_DUPLEX)
1147                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1148         else
1149                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1150
1151         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1152 }
1153
1154 /**
1155  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1156  *  @hw: pointer to the HW structure
1157  *
1158  *  Configure the KMRN interface by applying last minute quirks for
1159  *  gigabit operation.
1160  **/
1161 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1162 {
1163         s32 ret_val;
1164         u16 reg_data, reg_data2;
1165         u32 tipg;
1166         u32 i = 0;
1167
1168         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1169         ret_val =
1170             e1000_write_kmrn_reg_80003es2lan(hw,
1171                                              E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1172                                              reg_data);
1173         if (ret_val)
1174                 return ret_val;
1175
1176         /* Configure Transmit Inter-Packet Gap */
1177         tipg = er32(TIPG);
1178         tipg &= ~E1000_TIPG_IPGT_MASK;
1179         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1180         ew32(TIPG, tipg);
1181
1182         do {
1183                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1184                 if (ret_val)
1185                         return ret_val;
1186
1187                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1188                 if (ret_val)
1189                         return ret_val;
1190                 i++;
1191         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1192
1193         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1194
1195         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1196 }
1197
1198 /**
1199  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1200  *  @hw: pointer to the HW structure
1201  *  @offset: register offset to be read
1202  *  @data: pointer to the read data
1203  *
1204  *  Acquire semaphore, then read the PHY register at offset
1205  *  using the kumeran interface.  The information retrieved is stored in data.
1206  *  Release the semaphore before exiting.
1207  **/
1208 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1209                                            u16 *data)
1210 {
1211         u32 kmrnctrlsta;
1212         s32 ret_val;
1213
1214         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1215         if (ret_val)
1216                 return ret_val;
1217
1218         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1219                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1220         ew32(KMRNCTRLSTA, kmrnctrlsta);
1221         e1e_flush();
1222
1223         udelay(2);
1224
1225         kmrnctrlsta = er32(KMRNCTRLSTA);
1226         *data = (u16)kmrnctrlsta;
1227
1228         e1000_release_mac_csr_80003es2lan(hw);
1229
1230         return ret_val;
1231 }
1232
1233 /**
1234  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1235  *  @hw: pointer to the HW structure
1236  *  @offset: register offset to write to
1237  *  @data: data to write at register offset
1238  *
1239  *  Acquire semaphore, then write the data to PHY register
1240  *  at the offset using the kumeran interface.  Release semaphore
1241  *  before exiting.
1242  **/
1243 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1244                                             u16 data)
1245 {
1246         u32 kmrnctrlsta;
1247         s32 ret_val;
1248
1249         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1250         if (ret_val)
1251                 return ret_val;
1252
1253         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1254                        E1000_KMRNCTRLSTA_OFFSET) | data;
1255         ew32(KMRNCTRLSTA, kmrnctrlsta);
1256         e1e_flush();
1257
1258         udelay(2);
1259
1260         e1000_release_mac_csr_80003es2lan(hw);
1261
1262         return ret_val;
1263 }
1264
1265 /**
1266  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1267  *  @hw: pointer to the HW structure
1268  **/
1269 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1270 {
1271         s32 ret_val;
1272
1273         /* If there's an alternate MAC address place it in RAR0
1274          * so that it will override the Si installed default perm
1275          * address.
1276          */
1277         ret_val = e1000_check_alt_mac_addr_generic(hw);
1278         if (ret_val)
1279                 return ret_val;
1280
1281         return e1000_read_mac_addr_generic(hw);
1282 }
1283
1284 /**
1285  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1286  * @hw: pointer to the HW structure
1287  *
1288  * In the case of a PHY power down to save power, or to turn off link during a
1289  * driver unload, or wake on lan is not enabled, remove the link.
1290  **/
1291 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1292 {
1293         /* If the management interface is not enabled, then power down */
1294         if (!(hw->mac.ops.check_mng_mode(hw) ||
1295               hw->phy.ops.check_reset_block(hw)))
1296                 e1000_power_down_phy_copper(hw);
1297 }
1298
1299 /**
1300  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1301  *  @hw: pointer to the HW structure
1302  *
1303  *  Clears the hardware counters by reading the counter registers.
1304  **/
1305 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1306 {
1307         e1000e_clear_hw_cntrs_base(hw);
1308
1309         er32(PRC64);
1310         er32(PRC127);
1311         er32(PRC255);
1312         er32(PRC511);
1313         er32(PRC1023);
1314         er32(PRC1522);
1315         er32(PTC64);
1316         er32(PTC127);
1317         er32(PTC255);
1318         er32(PTC511);
1319         er32(PTC1023);
1320         er32(PTC1522);
1321
1322         er32(ALGNERRC);
1323         er32(RXERRC);
1324         er32(TNCRS);
1325         er32(CEXTERR);
1326         er32(TSCTC);
1327         er32(TSCTFC);
1328
1329         er32(MGTPRC);
1330         er32(MGTPDC);
1331         er32(MGTPTC);
1332
1333         er32(IAC);
1334         er32(ICRXOC);
1335
1336         er32(ICRXPTC);
1337         er32(ICRXATC);
1338         er32(ICTXPTC);
1339         er32(ICTXATC);
1340         er32(ICTXQEC);
1341         er32(ICTXQMTC);
1342         er32(ICRXDMTC);
1343 }
1344
1345 static const struct e1000_mac_operations es2_mac_ops = {
1346         .read_mac_addr          = e1000_read_mac_addr_80003es2lan,
1347         .id_led_init            = e1000e_id_led_init_generic,
1348         .blink_led              = e1000e_blink_led_generic,
1349         .check_mng_mode         = e1000e_check_mng_mode_generic,
1350         /* check_for_link dependent on media type */
1351         .cleanup_led            = e1000e_cleanup_led_generic,
1352         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1353         .get_bus_info           = e1000e_get_bus_info_pcie,
1354         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1355         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1356         .led_on                 = e1000e_led_on_generic,
1357         .led_off                = e1000e_led_off_generic,
1358         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1359         .write_vfta             = e1000_write_vfta_generic,
1360         .clear_vfta             = e1000_clear_vfta_generic,
1361         .reset_hw               = e1000_reset_hw_80003es2lan,
1362         .init_hw                = e1000_init_hw_80003es2lan,
1363         .setup_link             = e1000e_setup_link_generic,
1364         /* setup_physical_interface dependent on media type */
1365         .setup_led              = e1000e_setup_led_generic,
1366         .config_collision_dist  = e1000e_config_collision_dist_generic,
1367         .rar_set                = e1000e_rar_set_generic,
1368         .rar_get_count          = e1000e_rar_get_count_generic,
1369 };
1370
1371 static const struct e1000_phy_operations es2_phy_ops = {
1372         .acquire                = e1000_acquire_phy_80003es2lan,
1373         .check_polarity         = e1000_check_polarity_m88,
1374         .check_reset_block      = e1000e_check_reset_block_generic,
1375         .commit                 = e1000e_phy_sw_reset,
1376         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1377         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1378         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1379         .get_info               = e1000e_get_phy_info_m88,
1380         .read_reg               = e1000_read_phy_reg_gg82563_80003es2lan,
1381         .release                = e1000_release_phy_80003es2lan,
1382         .reset                  = e1000e_phy_hw_reset_generic,
1383         .set_d0_lplu_state      = NULL,
1384         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1385         .write_reg              = e1000_write_phy_reg_gg82563_80003es2lan,
1386         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1387 };
1388
1389 static const struct e1000_nvm_operations es2_nvm_ops = {
1390         .acquire                = e1000_acquire_nvm_80003es2lan,
1391         .read                   = e1000e_read_nvm_eerd,
1392         .release                = e1000_release_nvm_80003es2lan,
1393         .reload                 = e1000e_reload_nvm_generic,
1394         .update                 = e1000e_update_nvm_checksum_generic,
1395         .valid_led_default      = e1000e_valid_led_default,
1396         .validate               = e1000e_validate_nvm_checksum_generic,
1397         .write                  = e1000_write_nvm_80003es2lan,
1398 };
1399
1400 const struct e1000_info e1000_es2_info = {
1401         .mac                    = e1000_80003es2lan,
1402         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1403                                   | FLAG_HAS_JUMBO_FRAMES
1404                                   | FLAG_HAS_WOL
1405                                   | FLAG_APME_IN_CTRL3
1406                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1407                                   | FLAG_RX_NEEDS_RESTART /* errata */
1408                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1409                                   | FLAG_APME_CHECK_PORT_B
1410                                   | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1411         .flags2                 = FLAG2_DMA_BURST,
1412         .pba                    = 38,
1413         .max_hw_frame_size      = DEFAULT_JUMBO,
1414         .get_variants           = e1000_get_variants_80003es2lan,
1415         .mac_ops                = &es2_mac_ops,
1416         .phy_ops                = &es2_phy_ops,
1417         .nvm_ops                = &es2_nvm_ops,
1418 };