kernel/drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/delay.h>
  74 #include <linux/netdevice.h>
  75 #include <linux/etherdevice.h>
  76 #include <linux/skbuff.h>
  77 #include <linux/if_vlan.h>
  78 #include <linux/spinlock.h>
  79 #include <linux/mm.h>
  80 #include <linux/of_address.h>
  81 #include <linux/of_irq.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #ifdef CONFIG_PPC
  92 #include <asm/reg.h>
  93 #include <asm/mpc85xx.h>
  94 #endif
  95 #include <asm/irq.h>
  96 #include <asm/uaccess.h>
  97 #include <linux/module.h>
  98 #include <linux/dma-mapping.h>
  99 #include <linux/crc32.h>
 100 #include <linux/mii.h>
 101 #include <linux/phy.h>
 102 #include <linux/phy_fixed.h>
 103 #include <linux/of.h>
 104 #include <linux/of_net.h>
 105 #include <linux/of_address.h>
 106 #include <linux/of_irq.h>
 107
 108 #include "gianfar.h"
 109
 110 #define TX_TIMEOUT      (5*HZ)
 111
 112 const char gfar_driver_version[] = "2.0";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_reset_task(struct work_struct *work);
 117 static void gfar_timeout(struct net_device *dev);
 118 static int gfar_close(struct net_device *dev);
 119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
 120                                 int alloc_cnt);
 121 static int gfar_set_mac_address(struct net_device *dev);
 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 123 static irqreturn_t gfar_error(int irq, void *dev_id);
 124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 126 static void adjust_link(struct net_device *dev);
 127 static noinline void gfar_update_link_state(struct gfar_private *priv);
 128 static int init_phy(struct net_device *dev);
 129 static int gfar_probe(struct platform_device *ofdev);
 130 static int gfar_remove(struct platform_device *ofdev);
 131 static void free_skb_resources(struct gfar_private *priv);
 132 static void gfar_set_multi(struct net_device *dev);
 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 134 static void gfar_configure_serdes(struct net_device *dev);
 135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
 136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
 137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
 138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
 139 #ifdef CONFIG_NET_POLL_CONTROLLER
 140 static void gfar_netpoll(struct net_device *dev);
 141 #endif
 142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
 145 static void gfar_halt_nodisable(struct gfar_private *priv);
 146 static void gfar_clear_exact_match(struct net_device *dev);
 147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 148                                   const u8 *addr);
 149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 150
 151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 153 MODULE_LICENSE("GPL");
 154
 155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 156                             dma_addr_t buf)
 157 {
 158         u32 lstatus;
 159
 160         bdp->bufPtr = cpu_to_be32(buf);
 161
 162         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 163         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 164                 lstatus |= BD_LFLAG(RXBD_WRAP);
 165
 166         gfar_wmb();
 167
 168         bdp->lstatus = cpu_to_be32(lstatus);
 169 }
 170
 171 static void gfar_init_bds(struct net_device *ndev)
 172 {
 173         struct gfar_private *priv = netdev_priv(ndev);
 174         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 175         struct gfar_priv_tx_q *tx_queue = NULL;
 176         struct gfar_priv_rx_q *rx_queue = NULL;
 177         struct txbd8 *txbdp;
 178         u32 __iomem *rfbptr;
 179         int i, j;
 180
 181         for (i = 0; i < priv->num_tx_queues; i++) {
 182                 tx_queue = priv->tx_queue[i];
 183                 /* Initialize some variables in our dev structure */
 184                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 185                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 186                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 187                 tx_queue->skb_curtx = 0;
 188                 tx_queue->skb_dirtytx = 0;
 189
 190                 /* Initialize Transmit Descriptor Ring */
 191                 txbdp = tx_queue->tx_bd_base;
 192                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 193                         txbdp->lstatus = 0;
 194                         txbdp->bufPtr = 0;
 195                         txbdp++;
 196                 }
 197
 198                 /* Set the last descriptor in the ring to indicate wrap */
 199                 txbdp--;
 200                 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
 201                                             TXBD_WRAP);
 202         }
 203
 204         rfbptr = &regs->rfbptr0;
 205         for (i = 0; i < priv->num_rx_queues; i++) {
 206                 rx_queue = priv->rx_queue[i];
 207
 208                 rx_queue->next_to_clean = 0;
 209                 rx_queue->next_to_use = 0;
 210                 rx_queue->next_to_alloc = 0;
 211
 212                 /* make sure next_to_clean != next_to_use after this
 213                  * by leaving at least 1 unused descriptor
 214                  */
 215                 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
 216
 217                 rx_queue->rfbptr = rfbptr;
 218                 rfbptr += 2;
 219         }
 220 }
 221
 222 static int gfar_alloc_skb_resources(struct net_device *ndev)
 223 {
 224         void *vaddr;
 225         dma_addr_t addr;
 226         int i, j;
 227         struct gfar_private *priv = netdev_priv(ndev);
 228         struct device *dev = priv->dev;
 229         struct gfar_priv_tx_q *tx_queue = NULL;
 230         struct gfar_priv_rx_q *rx_queue = NULL;
 231
 232         priv->total_tx_ring_size = 0;
 233         for (i = 0; i < priv->num_tx_queues; i++)
 234                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 235
 236         priv->total_rx_ring_size = 0;
 237         for (i = 0; i < priv->num_rx_queues; i++)
 238                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 239
 240         /* Allocate memory for the buffer descriptors */
 241         vaddr = dma_alloc_coherent(dev,
 242                                    (priv->total_tx_ring_size *
 243                                     sizeof(struct txbd8)) +
 244                                    (priv->total_rx_ring_size *
 245                                     sizeof(struct rxbd8)),
 246                                    &addr, GFP_KERNEL);
 247         if (!vaddr)
 248                 return -ENOMEM;
 249
 250         for (i = 0; i < priv->num_tx_queues; i++) {
 251                 tx_queue = priv->tx_queue[i];
 252                 tx_queue->tx_bd_base = vaddr;
 253                 tx_queue->tx_bd_dma_base = addr;
 254                 tx_queue->dev = ndev;
 255                 /* enet DMA only understands physical addresses */
 256                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 257                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 258         }
 259
 260         /* Start the rx descriptor ring where the tx ring leaves off */
 261         for (i = 0; i < priv->num_rx_queues; i++) {
 262                 rx_queue = priv->rx_queue[i];
 263                 rx_queue->rx_bd_base = vaddr;
 264                 rx_queue->rx_bd_dma_base = addr;
 265                 rx_queue->ndev = ndev;
 266                 rx_queue->dev = dev;
 267                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 268                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 269         }
 270
 271         /* Setup the skbuff rings */
 272         for (i = 0; i < priv->num_tx_queues; i++) {
 273                 tx_queue = priv->tx_queue[i];
 274                 tx_queue->tx_skbuff =
 275                         kmalloc_array(tx_queue->tx_ring_size,
 276                                       sizeof(*tx_queue->tx_skbuff),
 277                                       GFP_KERNEL);
 278                 if (!tx_queue->tx_skbuff)
 279                         goto cleanup;
 280
 281                 for (j = 0; j < tx_queue->tx_ring_size; j++)
 282                         tx_queue->tx_skbuff[j] = NULL;
 283         }
 284
 285         for (i = 0; i < priv->num_rx_queues; i++) {
 286                 rx_queue = priv->rx_queue[i];
 287                 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
 288                                             sizeof(*rx_queue->rx_buff),
 289                                             GFP_KERNEL);
 290                 if (!rx_queue->rx_buff)
 291                         goto cleanup;
 292         }
 293
 294         gfar_init_bds(ndev);
 295
 296         return 0;
 297
 298 cleanup:
 299         free_skb_resources(priv);
 300         return -ENOMEM;
 301 }
 302
 303 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 304 {
 305         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 306         u32 __iomem *baddr;
 307         int i;
 308
 309         baddr = &regs->tbase0;
 310         for (i = 0; i < priv->num_tx_queues; i++) {
 311                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 312                 baddr += 2;
 313         }
 314
 315         baddr = &regs->rbase0;
 316         for (i = 0; i < priv->num_rx_queues; i++) {
 317                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 318                 baddr += 2;
 319         }
 320 }
 321
 322 static void gfar_init_rqprm(struct gfar_private *priv)
 323 {
 324         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 325         u32 __iomem *baddr;
 326         int i;
 327
 328         baddr = &regs->rqprm0;
 329         for (i = 0; i < priv->num_rx_queues; i++) {
 330                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 331                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 332                 baddr++;
 333         }
 334 }
 335
 336 static void gfar_rx_offload_en(struct gfar_private *priv)
 337 {
 338         /* set this when rx hw offload (TOE) functions are being used */
 339         priv->uses_rxfcb = 0;
 340
 341         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 342                 priv->uses_rxfcb = 1;
 343
 344         if (priv->hwts_rx_en || priv->rx_filer_enable)
 345                 priv->uses_rxfcb = 1;
 346 }
 347
 348 static void gfar_mac_rx_config(struct gfar_private *priv)
 349 {
 350         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 351         u32 rctrl = 0;
 352
 353         if (priv->rx_filer_enable) {
 354                 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
 355                 /* Program the RIR0 reg with the required distribution */
 356                 if (priv->poll_mode == GFAR_SQ_POLLING)
 357                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 358                 else /* GFAR_MQ_POLLING */
 359                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 360         }
 361
 362         /* Restore PROMISC mode */
 363         if (priv->ndev->flags & IFF_PROMISC)
 364                 rctrl |= RCTRL_PROM;
 365
 366         if (priv->ndev->features & NETIF_F_RXCSUM)
 367                 rctrl |= RCTRL_CHECKSUMMING;
 368
 369         if (priv->extended_hash)
 370                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Enable HW time stamping if requested from user space */
 378         if (priv->hwts_rx_en)
 379                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 380
 381         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 382                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 383
 384         /* Clear the LFC bit */
 385         gfar_write(&regs->rctrl, rctrl);
 386         /* Init flow control threshold values */
 387         gfar_init_rqprm(priv);
 388         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 389         rctrl |= RCTRL_LFC;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393 }
 394
 395 static void gfar_mac_tx_config(struct gfar_private *priv)
 396 {
 397         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 398         u32 tctrl = 0;
 399
 400         if (priv->ndev->features & NETIF_F_IP_CSUM)
 401                 tctrl |= TCTRL_INIT_CSUM;
 402
 403         if (priv->prio_sched_en)
 404                 tctrl |= TCTRL_TXSCHED_PRIO;
 405         else {
 406                 tctrl |= TCTRL_TXSCHED_WRRS;
 407                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 408                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 409         }
 410
 411         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 412                 tctrl |= TCTRL_VLINS;
 413
 414         gfar_write(&regs->tctrl, tctrl);
 415 }
 416
 417 static void gfar_configure_coalescing(struct gfar_private *priv,
 418                                unsigned long tx_mask, unsigned long rx_mask)
 419 {
 420         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 421         u32 __iomem *baddr;
 422
 423         if (priv->mode == MQ_MG_MODE) {
 424                 int i = 0;
 425
 426                 baddr = &regs->txic0;
 427                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 428                         gfar_write(baddr + i, 0);
 429                         if (likely(priv->tx_queue[i]->txcoalescing))
 430                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 431                 }
 432
 433                 baddr = &regs->rxic0;
 434                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 435                         gfar_write(baddr + i, 0);
 436                         if (likely(priv->rx_queue[i]->rxcoalescing))
 437                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 438                 }
 439         } else {
 440                 /* Backward compatible case -- even if we enable
 441                  * multiple queues, there's only single reg to program
 442                  */
 443                 gfar_write(&regs->txic, 0);
 444                 if (likely(priv->tx_queue[0]->txcoalescing))
 445                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 446
 447                 gfar_write(&regs->rxic, 0);
 448                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 449                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 450         }
 451 }
 452
 453 void gfar_configure_coalescing_all(struct gfar_private *priv)
 454 {
 455         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 456 }
 457
 458 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 459 {
 460         struct gfar_private *priv = netdev_priv(dev);
 461         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 462         unsigned long tx_packets = 0, tx_bytes = 0;
 463         int i;
 464
 465         for (i = 0; i < priv->num_rx_queues; i++) {
 466                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 467                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 468                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 469         }
 470
 471         dev->stats.rx_packets = rx_packets;
 472         dev->stats.rx_bytes   = rx_bytes;
 473         dev->stats.rx_dropped = rx_dropped;
 474
 475         for (i = 0; i < priv->num_tx_queues; i++) {
 476                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 477                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 478         }
 479
 480         dev->stats.tx_bytes   = tx_bytes;
 481         dev->stats.tx_packets = tx_packets;
 482
 483         return &dev->stats;
 484 }
 485
 486 static int gfar_set_mac_addr(struct net_device *dev, void *p)
 487 {
 488         eth_mac_addr(dev, p);
 489
 490         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 491
 492         return 0;
 493 }
 494
 495 static const struct net_device_ops gfar_netdev_ops = {
 496         .ndo_open = gfar_enet_open,
 497         .ndo_start_xmit = gfar_start_xmit,
 498         .ndo_stop = gfar_close,
 499         .ndo_change_mtu = gfar_change_mtu,
 500         .ndo_set_features = gfar_set_features,
 501         .ndo_set_rx_mode = gfar_set_multi,
 502         .ndo_tx_timeout = gfar_timeout,
 503         .ndo_do_ioctl = gfar_ioctl,
 504         .ndo_get_stats = gfar_get_stats,
 505         .ndo_set_mac_address = gfar_set_mac_addr,
 506         .ndo_validate_addr = eth_validate_addr,
 507 #ifdef CONFIG_NET_POLL_CONTROLLER
 508         .ndo_poll_controller = gfar_netpoll,
 509 #endif
 510 };
 511
 512 static void gfar_ints_disable(struct gfar_private *priv)
 513 {
 514         int i;
 515         for (i = 0; i < priv->num_grps; i++) {
 516                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 517                 /* Clear IEVENT */
 518                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 519
 520                 /* Initialize IMASK */
 521                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 522         }
 523 }
 524
 525 static void gfar_ints_enable(struct gfar_private *priv)
 526 {
 527         int i;
 528         for (i = 0; i < priv->num_grps; i++) {
 529                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 530                 /* Unmask the interrupts we look for */
 531                 gfar_write(&regs->imask, IMASK_DEFAULT);
 532         }
 533 }
 534
 535 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 536 {
 537         int i;
 538
 539         for (i = 0; i < priv->num_tx_queues; i++) {
 540                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 541                                             GFP_KERNEL);
 542                 if (!priv->tx_queue[i])
 543                         return -ENOMEM;
 544
 545                 priv->tx_queue[i]->tx_skbuff = NULL;
 546                 priv->tx_queue[i]->qindex = i;
 547                 priv->tx_queue[i]->dev = priv->ndev;
 548                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 549         }
 550         return 0;
 551 }
 552
 553 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 554 {
 555         int i;
 556
 557         for (i = 0; i < priv->num_rx_queues; i++) {
 558                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 559                                             GFP_KERNEL);
 560                 if (!priv->rx_queue[i])
 561                         return -ENOMEM;
 562
 563                 priv->rx_queue[i]->qindex = i;
 564                 priv->rx_queue[i]->ndev = priv->ndev;
 565         }
 566         return 0;
 567 }
 568
 569 static void gfar_free_tx_queues(struct gfar_private *priv)
 570 {
 571         int i;
 572
 573         for (i = 0; i < priv->num_tx_queues; i++)
 574                 kfree(priv->tx_queue[i]);
 575 }
 576
 577 static void gfar_free_rx_queues(struct gfar_private *priv)
 578 {
 579         int i;
 580
 581         for (i = 0; i < priv->num_rx_queues; i++)
 582                 kfree(priv->rx_queue[i]);
 583 }
 584
 585 static void unmap_group_regs(struct gfar_private *priv)
 586 {
 587         int i;
 588
 589         for (i = 0; i < MAXGROUPS; i++)
 590                 if (priv->gfargrp[i].regs)
 591                         iounmap(priv->gfargrp[i].regs);
 592 }
 593
 594 static void free_gfar_dev(struct gfar_private *priv)
 595 {
 596         int i, j;
 597
 598         for (i = 0; i < priv->num_grps; i++)
 599                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 600                         kfree(priv->gfargrp[i].irqinfo[j]);
 601                         priv->gfargrp[i].irqinfo[j] = NULL;
 602                 }
 603
 604         free_netdev(priv->ndev);
 605 }
 606
 607 static void disable_napi(struct gfar_private *priv)
 608 {
 609         int i;
 610
 611         for (i = 0; i < priv->num_grps; i++) {
 612                 napi_disable(&priv->gfargrp[i].napi_rx);
 613                 napi_disable(&priv->gfargrp[i].napi_tx);
 614         }
 615 }
 616
 617 static void enable_napi(struct gfar_private *priv)
 618 {
 619         int i;
 620
 621         for (i = 0; i < priv->num_grps; i++) {
 622                 napi_enable(&priv->gfargrp[i].napi_rx);
 623                 napi_enable(&priv->gfargrp[i].napi_tx);
 624         }
 625 }
 626
 627 static int gfar_parse_group(struct device_node *np,
 628                             struct gfar_private *priv, const char *model)
 629 {
 630         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 631         int i;
 632
 633         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 634                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 635                                           GFP_KERNEL);
 636                 if (!grp->irqinfo[i])
 637                         return -ENOMEM;
 638         }
 639
 640         grp->regs = of_iomap(np, 0);
 641         if (!grp->regs)
 642                 return -ENOMEM;
 643
 644         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 645
 646         /* If we aren't the FEC we have multiple interrupts */
 647         if (model && strcasecmp(model, "FEC")) {
 648                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 649                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 650                 if (!gfar_irq(grp, TX)->irq ||
 651                     !gfar_irq(grp, RX)->irq ||
 652                     !gfar_irq(grp, ER)->irq)
 653                         return -EINVAL;
 654         }
 655
 656         grp->priv = priv;
 657         spin_lock_init(&grp->grplock);
 658         if (priv->mode == MQ_MG_MODE) {
 659                 u32 rxq_mask, txq_mask;
 660                 int ret;
 661
 662                 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 663                 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 664
 665                 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
 666                 if (!ret) {
 667                         grp->rx_bit_map = rxq_mask ?
 668                         rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 669                 }
 670
 671                 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
 672                 if (!ret) {
 673                         grp->tx_bit_map = txq_mask ?
 674                         txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 675                 }
 676
 677                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 678                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 679                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 680                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 681                 }
 682         } else {
 683                 grp->rx_bit_map = 0xFF;
 684                 grp->tx_bit_map = 0xFF;
 685         }
 686
 687         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 688          * right to left, so we need to revert the 8 bits to get the q index
 689          */
 690         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 691         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 692
 693         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 694          * also assign queues to groups
 695          */
 696         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 697                 if (!grp->rx_queue)
 698                         grp->rx_queue = priv->rx_queue[i];
 699                 grp->num_rx_queues++;
 700                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 701                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 702                 priv->rx_queue[i]->grp = grp;
 703         }
 704
 705         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 706                 if (!grp->tx_queue)
 707                         grp->tx_queue = priv->tx_queue[i];
 708                 grp->num_tx_queues++;
 709                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 710                 priv->tqueue |= (TQUEUE_EN0 >> i);
 711                 priv->tx_queue[i]->grp = grp;
 712         }
 713
 714         priv->num_grps++;
 715
 716         return 0;
 717 }
 718
 719 static int gfar_of_group_count(struct device_node *np)
 720 {
 721         struct device_node *child;
 722         int num = 0;
 723
 724         for_each_available_child_of_node(np, child)
 725                 if (!of_node_cmp(child->name, "queue-group"))
 726                         num++;
 727
 728         return num;
 729 }
 730
 731 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 732 {
 733         const char *model;
 734         const char *ctype;
 735         const void *mac_addr;
 736         int err = 0, i;
 737         struct net_device *dev = NULL;
 738         struct gfar_private *priv = NULL;
 739         struct device_node *np = ofdev->dev.of_node;
 740         struct device_node *child = NULL;
 741         struct property *stash;
 742         u32 stash_len = 0;
 743         u32 stash_idx = 0;
 744         unsigned int num_tx_qs, num_rx_qs;
 745         unsigned short mode, poll_mode;
 746
 747         if (!np)
 748                 return -ENODEV;
 749
 750         if (of_device_is_compatible(np, "fsl,etsec2")) {
 751                 mode = MQ_MG_MODE;
 752                 poll_mode = GFAR_SQ_POLLING;
 753         } else {
 754                 mode = SQ_SG_MODE;
 755                 poll_mode = GFAR_SQ_POLLING;
 756         }
 757
 758         if (mode == SQ_SG_MODE) {
 759                 num_tx_qs = 1;
 760                 num_rx_qs = 1;
 761         } else { /* MQ_MG_MODE */
 762                 /* get the actual number of supported groups */
 763                 unsigned int num_grps = gfar_of_group_count(np);
 764
 765                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 766                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 767                                 num_grps);
 768                         pr_err("Cannot do alloc_etherdev, aborting\n");
 769                         return -EINVAL;
 770                 }
 771
 772                 if (poll_mode == GFAR_SQ_POLLING) {
 773                         num_tx_qs = num_grps; /* one txq per int group */
 774                         num_rx_qs = num_grps; /* one rxq per int group */
 775                 } else { /* GFAR_MQ_POLLING */
 776                         u32 tx_queues, rx_queues;
 777                         int ret;
 778
 779                         /* parse the num of HW tx and rx queues */
 780                         ret = of_property_read_u32(np, "fsl,num_tx_queues",
 781                                                    &tx_queues);
 782                         num_tx_qs = ret ? 1 : tx_queues;
 783
 784                         ret = of_property_read_u32(np, "fsl,num_rx_queues",
 785                                                    &rx_queues);
 786                         num_rx_qs = ret ? 1 : rx_queues;
 787                 }
 788         }
 789
 790         if (num_tx_qs > MAX_TX_QS) {
 791                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 792                        num_tx_qs, MAX_TX_QS);
 793                 pr_err("Cannot do alloc_etherdev, aborting\n");
 794                 return -EINVAL;
 795         }
 796
 797         if (num_rx_qs > MAX_RX_QS) {
 798                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 799                        num_rx_qs, MAX_RX_QS);
 800                 pr_err("Cannot do alloc_etherdev, aborting\n");
 801                 return -EINVAL;
 802         }
 803
 804         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 805         dev = *pdev;
 806         if (NULL == dev)
 807                 return -ENOMEM;
 808
 809         priv = netdev_priv(dev);
 810         priv->ndev = dev;
 811
 812         priv->mode = mode;
 813         priv->poll_mode = poll_mode;
 814
 815         priv->num_tx_queues = num_tx_qs;
 816         netif_set_real_num_rx_queues(dev, num_rx_qs);
 817         priv->num_rx_queues = num_rx_qs;
 818
 819         err = gfar_alloc_tx_queues(priv);
 820         if (err)
 821                 goto tx_alloc_failed;
 822
 823         err = gfar_alloc_rx_queues(priv);
 824         if (err)
 825                 goto rx_alloc_failed;
 826
 827         err = of_property_read_string(np, "model", &model);
 828         if (err) {
 829                 pr_err("Device model property missing, aborting\n");
 830                 goto rx_alloc_failed;
 831         }
 832
 833         /* Init Rx queue filer rule set linked list */
 834         INIT_LIST_HEAD(&priv->rx_list.list);
 835         priv->rx_list.count = 0;
 836         mutex_init(&priv->rx_queue_access);
 837
 838         for (i = 0; i < MAXGROUPS; i++)
 839                 priv->gfargrp[i].regs = NULL;
 840
 841         /* Parse and initialize group specific information */
 842         if (priv->mode == MQ_MG_MODE) {
 843                 for_each_available_child_of_node(np, child) {
 844                         if (of_node_cmp(child->name, "queue-group"))
 845                                 continue;
 846
 847                         err = gfar_parse_group(child, priv, model);
 848                         if (err)
 849                                 goto err_grp_init;
 850                 }
 851         } else { /* SQ_SG_MODE */
 852                 err = gfar_parse_group(np, priv, model);
 853                 if (err)
 854                         goto err_grp_init;
 855         }
 856
 857         stash = of_find_property(np, "bd-stash", NULL);
 858
 859         if (stash) {
 860                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 861                 priv->bd_stash_en = 1;
 862         }
 863
 864         err = of_property_read_u32(np, "rx-stash-len", &stash_len);
 865
 866         if (err == 0)
 867                 priv->rx_stash_size = stash_len;
 868
 869         err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
 870
 871         if (err == 0)
 872                 priv->rx_stash_index = stash_idx;
 873
 874         if (stash_len || stash_idx)
 875                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 876
 877         mac_addr = of_get_mac_address(np);
 878
 879         if (mac_addr)
 880                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 881
 882         if (model && !strcasecmp(model, "TSEC"))
 883                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 884                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 885                                      FSL_GIANFAR_DEV_HAS_RMON |
 886                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 887
 888         if (model && !strcasecmp(model, "eTSEC"))
 889                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 890                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 891                                      FSL_GIANFAR_DEV_HAS_RMON |
 892                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 893                                      FSL_GIANFAR_DEV_HAS_CSUM |
 894                                      FSL_GIANFAR_DEV_HAS_VLAN |
 895                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 896                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 897                                      FSL_GIANFAR_DEV_HAS_TIMER |
 898                                      FSL_GIANFAR_DEV_HAS_RX_FILER;
 899
 900         err = of_property_read_string(np, "phy-connection-type", &ctype);
 901
 902         /* We only care about rgmii-id.  The rest are autodetected */
 903         if (err == 0 && !strcmp(ctype, "rgmii-id"))
 904                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 905         else
 906                 priv->interface = PHY_INTERFACE_MODE_MII;
 907
 908         if (of_find_property(np, "fsl,magic-packet", NULL))
 909                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 910
 911         if (of_get_property(np, "fsl,wake-on-filer", NULL))
 912                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
 913
 914         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 915
 916         /* In the case of a fixed PHY, the DT node associated
 917          * to the PHY is the Ethernet MAC DT node.
 918          */
 919         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 920                 err = of_phy_register_fixed_link(np);
 921                 if (err)
 922                         goto err_grp_init;
 923
 924                 priv->phy_node = of_node_get(np);
 925         }
 926
 927         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 928         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 929
 930         return 0;
 931
 932 err_grp_init:
 933         unmap_group_regs(priv);
 934 rx_alloc_failed:
 935         gfar_free_rx_queues(priv);
 936 tx_alloc_failed:
 937         gfar_free_tx_queues(priv);
 938         free_gfar_dev(priv);
 939         return err;
 940 }
 941
 942 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 943 {
 944         struct hwtstamp_config config;
 945         struct gfar_private *priv = netdev_priv(netdev);
 946
 947         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 948                 return -EFAULT;
 949
 950         /* reserved for future extensions */
 951         if (config.flags)
 952                 return -EINVAL;
 953
 954         switch (config.tx_type) {
 955         case HWTSTAMP_TX_OFF:
 956                 priv->hwts_tx_en = 0;
 957                 break;
 958         case HWTSTAMP_TX_ON:
 959                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 960                         return -ERANGE;
 961                 priv->hwts_tx_en = 1;
 962                 break;
 963         default:
 964                 return -ERANGE;
 965         }
 966
 967         switch (config.rx_filter) {
 968         case HWTSTAMP_FILTER_NONE:
 969                 if (priv->hwts_rx_en) {
 970                         priv->hwts_rx_en = 0;
 971                         reset_gfar(netdev);
 972                 }
 973                 break;
 974         default:
 975                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 976                         return -ERANGE;
 977                 if (!priv->hwts_rx_en) {
 978                         priv->hwts_rx_en = 1;
 979                         reset_gfar(netdev);
 980                 }
 981                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 982                 break;
 983         }
 984
 985         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 986                 -EFAULT : 0;
 987 }
 988
 989 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 990 {
 991         struct hwtstamp_config config;
 992         struct gfar_private *priv = netdev_priv(netdev);
 993
 994         config.flags = 0;
 995         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 996         config.rx_filter = (priv->hwts_rx_en ?
 997                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
 998
 999         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1000                 -EFAULT : 0;
1001 }
1002
1003 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1004 {
1005         struct gfar_private *priv = netdev_priv(dev);
1006
1007         if (!netif_running(dev))
1008                 return -EINVAL;
1009
1010         if (cmd == SIOCSHWTSTAMP)
1011                 return gfar_hwtstamp_set(dev, rq);
1012         if (cmd == SIOCGHWTSTAMP)
1013                 return gfar_hwtstamp_get(dev, rq);
1014
1015         if (!priv->phydev)
1016                 return -ENODEV;
1017
1018         return phy_mii_ioctl(priv->phydev, rq, cmd);
1019 }
1020
1021 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1022                                    u32 class)
1023 {
1024         u32 rqfpr = FPR_FILER_MASK;
1025         u32 rqfcr = 0x0;
1026
1027         rqfar--;
1028         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1029         priv->ftp_rqfpr[rqfar] = rqfpr;
1030         priv->ftp_rqfcr[rqfar] = rqfcr;
1031         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1032
1033         rqfar--;
1034         rqfcr = RQFCR_CMP_NOMATCH;
1035         priv->ftp_rqfpr[rqfar] = rqfpr;
1036         priv->ftp_rqfcr[rqfar] = rqfcr;
1037         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1038
1039         rqfar--;
1040         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1041         rqfpr = class;
1042         priv->ftp_rqfcr[rqfar] = rqfcr;
1043         priv->ftp_rqfpr[rqfar] = rqfpr;
1044         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1045
1046         rqfar--;
1047         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1048         rqfpr = class;
1049         priv->ftp_rqfcr[rqfar] = rqfcr;
1050         priv->ftp_rqfpr[rqfar] = rqfpr;
1051         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1052
1053         return rqfar;
1054 }
1055
1056 static void gfar_init_filer_table(struct gfar_private *priv)
1057 {
1058         int i = 0x0;
1059         u32 rqfar = MAX_FILER_IDX;
1060         u32 rqfcr = 0x0;
1061         u32 rqfpr = FPR_FILER_MASK;
1062
1063         /* Default rule */
1064         rqfcr = RQFCR_CMP_MATCH;
1065         priv->ftp_rqfcr[rqfar] = rqfcr;
1066         priv->ftp_rqfpr[rqfar] = rqfpr;
1067         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1068
1069         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1070         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1071         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1072         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1073         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1074         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1075
1076         /* cur_filer_idx indicated the first non-masked rule */
1077         priv->cur_filer_idx = rqfar;
1078
1079         /* Rest are masked rules */
1080         rqfcr = RQFCR_CMP_NOMATCH;
1081         for (i = 0; i < rqfar; i++) {
1082                 priv->ftp_rqfcr[i] = rqfcr;
1083                 priv->ftp_rqfpr[i] = rqfpr;
1084                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1085         }
1086 }
1087
1088 #ifdef CONFIG_PPC
1089 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1090 {
1091         unsigned int pvr = mfspr(SPRN_PVR);
1092         unsigned int svr = mfspr(SPRN_SVR);
1093         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1094         unsigned int rev = svr & 0xffff;
1095
1096         /* MPC8313 Rev 2.0 and higher; All MPC837x */
1097         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1098             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1099                 priv->errata |= GFAR_ERRATA_74;
1100
1101         /* MPC8313 and MPC837x all rev */
1102         if ((pvr == 0x80850010 && mod == 0x80b0) ||
1103             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1104                 priv->errata |= GFAR_ERRATA_76;
1105
1106         /* MPC8313 Rev < 2.0 */
1107         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1108                 priv->errata |= GFAR_ERRATA_12;
1109 }
1110
1111 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1112 {
1113         unsigned int svr = mfspr(SPRN_SVR);
1114
1115         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1116                 priv->errata |= GFAR_ERRATA_12;
1117         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1118             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1119                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1120 }
1121 #endif
1122
1123 static void gfar_detect_errata(struct gfar_private *priv)
1124 {
1125         struct device *dev = &priv->ofdev->dev;
1126
1127         /* no plans to fix */
1128         priv->errata |= GFAR_ERRATA_A002;
1129
1130 #ifdef CONFIG_PPC
1131         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1132                 __gfar_detect_errata_85xx(priv);
1133         else /* non-mpc85xx parts, i.e. e300 core based */
1134                 __gfar_detect_errata_83xx(priv);
1135 #endif
1136
1137         if (priv->errata)
1138                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1139                          priv->errata);
1140 }
1141
1142 void gfar_mac_reset(struct gfar_private *priv)
1143 {
1144         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1145         u32 tempval;
1146
1147         /* Reset MAC layer */
1148         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1149
1150         /* We need to delay at least 3 TX clocks */
1151         udelay(3);
1152
1153         /* the soft reset bit is not self-resetting, so we need to
1154          * clear it before resuming normal operation
1155          */
1156         gfar_write(&regs->maccfg1, 0);
1157
1158         udelay(3);
1159
1160         gfar_rx_offload_en(priv);
1161
1162         /* Initialize the max receive frame/buffer lengths */
1163         gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1164         gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
1165
1166         /* Initialize the Minimum Frame Length Register */
1167         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1168
1169         /* Initialize MACCFG2. */
1170         tempval = MACCFG2_INIT_SETTINGS;
1171
1172         /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1173          * are marked as truncated.  Avoid this by MACCFG2[Huge Frame]=1,
1174          * and by checking RxBD[LG] and discarding larger than MAXFRM.
1175          */
1176         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1177                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1178
1179         gfar_write(&regs->maccfg2, tempval);
1180
1181         /* Clear mac addr hash registers */
1182         gfar_write(&regs->igaddr0, 0);
1183         gfar_write(&regs->igaddr1, 0);
1184         gfar_write(&regs->igaddr2, 0);
1185         gfar_write(&regs->igaddr3, 0);
1186         gfar_write(&regs->igaddr4, 0);
1187         gfar_write(&regs->igaddr5, 0);
1188         gfar_write(&regs->igaddr6, 0);
1189         gfar_write(&regs->igaddr7, 0);
1190
1191         gfar_write(&regs->gaddr0, 0);
1192         gfar_write(&regs->gaddr1, 0);
1193         gfar_write(&regs->gaddr2, 0);
1194         gfar_write(&regs->gaddr3, 0);
1195         gfar_write(&regs->gaddr4, 0);
1196         gfar_write(&regs->gaddr5, 0);
1197         gfar_write(&regs->gaddr6, 0);
1198         gfar_write(&regs->gaddr7, 0);
1199
1200         if (priv->extended_hash)
1201                 gfar_clear_exact_match(priv->ndev);
1202
1203         gfar_mac_rx_config(priv);
1204
1205         gfar_mac_tx_config(priv);
1206
1207         gfar_set_mac_address(priv->ndev);
1208
1209         gfar_set_multi(priv->ndev);
1210
1211         /* clear ievent and imask before configuring coalescing */
1212         gfar_ints_disable(priv);
1213
1214         /* Configure the coalescing support */
1215         gfar_configure_coalescing_all(priv);
1216 }
1217
1218 static void gfar_hw_init(struct gfar_private *priv)
1219 {
1220         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1221         u32 attrs;
1222
1223         /* Stop the DMA engine now, in case it was running before
1224          * (The firmware could have used it, and left it running).
1225          */
1226         gfar_halt(priv);
1227
1228         gfar_mac_reset(priv);
1229
1230         /* Zero out the rmon mib registers if it has them */
1231         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1232                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1233
1234                 /* Mask off the CAM interrupts */
1235                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1236                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1237         }
1238
1239         /* Initialize ECNTRL */
1240         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1241
1242         /* Set the extraction length and index */
1243         attrs = ATTRELI_EL(priv->rx_stash_size) |
1244                 ATTRELI_EI(priv->rx_stash_index);
1245
1246         gfar_write(&regs->attreli, attrs);
1247
1248         /* Start with defaults, and add stashing
1249          * depending on driver parameters
1250          */
1251         attrs = ATTR_INIT_SETTINGS;
1252
1253         if (priv->bd_stash_en)
1254                 attrs |= ATTR_BDSTASH;
1255
1256         if (priv->rx_stash_size != 0)
1257                 attrs |= ATTR_BUFSTASH;
1258
1259         gfar_write(&regs->attr, attrs);
1260
1261         /* FIFO configs */
1262         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1263         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1264         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1265
1266         /* Program the interrupt steering regs, only for MG devices */
1267         if (priv->num_grps > 1)
1268                 gfar_write_isrg(priv);
1269 }
1270
1271 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1272 {
1273         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1274
1275         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1276                 priv->extended_hash = 1;
1277                 priv->hash_width = 9;
1278
1279                 priv->hash_regs[0] = &regs->igaddr0;
1280                 priv->hash_regs[1] = &regs->igaddr1;
1281                 priv->hash_regs[2] = &regs->igaddr2;
1282                 priv->hash_regs[3] = &regs->igaddr3;
1283                 priv->hash_regs[4] = &regs->igaddr4;
1284                 priv->hash_regs[5] = &regs->igaddr5;
1285                 priv->hash_regs[6] = &regs->igaddr6;
1286                 priv->hash_regs[7] = &regs->igaddr7;
1287                 priv->hash_regs[8] = &regs->gaddr0;
1288                 priv->hash_regs[9] = &regs->gaddr1;
1289                 priv->hash_regs[10] = &regs->gaddr2;
1290                 priv->hash_regs[11] = &regs->gaddr3;
1291                 priv->hash_regs[12] = &regs->gaddr4;
1292                 priv->hash_regs[13] = &regs->gaddr5;
1293                 priv->hash_regs[14] = &regs->gaddr6;
1294                 priv->hash_regs[15] = &regs->gaddr7;
1295
1296         } else {
1297                 priv->extended_hash = 0;
1298                 priv->hash_width = 8;
1299
1300                 priv->hash_regs[0] = &regs->gaddr0;
1301                 priv->hash_regs[1] = &regs->gaddr1;
1302                 priv->hash_regs[2] = &regs->gaddr2;
1303                 priv->hash_regs[3] = &regs->gaddr3;
1304                 priv->hash_regs[4] = &regs->gaddr4;
1305                 priv->hash_regs[5] = &regs->gaddr5;
1306                 priv->hash_regs[6] = &regs->gaddr6;
1307                 priv->hash_regs[7] = &regs->gaddr7;
1308         }
1309 }
1310
1311 /* Set up the ethernet device structure, private data,
1312  * and anything else we need before we start
1313  */
1314 static int gfar_probe(struct platform_device *ofdev)
1315 {
1316         struct net_device *dev = NULL;
1317         struct gfar_private *priv = NULL;
1318         int err = 0, i;
1319
1320         err = gfar_of_init(ofdev, &dev);
1321
1322         if (err)
1323                 return err;
1324
1325         priv = netdev_priv(dev);
1326         priv->ndev = dev;
1327         priv->ofdev = ofdev;
1328         priv->dev = &ofdev->dev;
1329         SET_NETDEV_DEV(dev, &ofdev->dev);
1330
1331         INIT_WORK(&priv->reset_task, gfar_reset_task);
1332
1333         platform_set_drvdata(ofdev, priv);
1334
1335         gfar_detect_errata(priv);
1336
1337         /* Set the dev->base_addr to the gfar reg region */
1338         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1339
1340         /* Fill in the dev structure */
1341         dev->watchdog_timeo = TX_TIMEOUT;
1342         dev->mtu = 1500;
1343         dev->netdev_ops = &gfar_netdev_ops;
1344         dev->ethtool_ops = &gfar_ethtool_ops;
1345
1346         /* Register for napi ...We are registering NAPI for each grp */
1347         for (i = 0; i < priv->num_grps; i++) {
1348                 if (priv->poll_mode == GFAR_SQ_POLLING) {
1349                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1350                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1351                         netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1352                                        gfar_poll_tx_sq, 2);
1353                 } else {
1354                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1355                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
1356                         netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1357                                        gfar_poll_tx, 2);
1358                 }
1359         }
1360
1361         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1362                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1363                                    NETIF_F_RXCSUM;
1364                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1365                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1366         }
1367
1368         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1369                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1370                                     NETIF_F_HW_VLAN_CTAG_RX;
1371                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1372         }
1373
1374         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1375
1376         gfar_init_addr_hash_table(priv);
1377
1378         /* Insert receive time stamps into padding alignment bytes */
1379         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1380                 priv->padding = 8;
1381
1382         if (dev->features & NETIF_F_IP_CSUM ||
1383             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1384                 dev->needed_headroom = GMAC_FCB_LEN;
1385
1386         /* Initializing some of the rx/tx queue level parameters */
1387         for (i = 0; i < priv->num_tx_queues; i++) {
1388                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1389                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1390                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1391                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1392         }
1393
1394         for (i = 0; i < priv->num_rx_queues; i++) {
1395                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1396                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1397                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1398         }
1399
1400         /* Always enable rx filer if available */
1401         priv->rx_filer_enable =
1402             (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
1403         /* Enable most messages by default */
1404         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1405         /* use pritority h/w tx queue scheduling for single queue devices */
1406         if (priv->num_tx_queues == 1)
1407                 priv->prio_sched_en = 1;
1408
1409         set_bit(GFAR_DOWN, &priv->state);
1410
1411         gfar_hw_init(priv);
1412
1413         /* Carrier starts down, phylib will bring it up */
1414         netif_carrier_off(dev);
1415
1416         err = register_netdev(dev);
1417
1418         if (err) {
1419                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1420                 goto register_fail;
1421         }
1422
1423         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
1424                 priv->wol_supported |= GFAR_WOL_MAGIC;
1425
1426         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
1427             priv->rx_filer_enable)
1428                 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
1429
1430         device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
1431
1432         /* fill out IRQ number and name fields */
1433         for (i = 0; i < priv->num_grps; i++) {
1434                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1435                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1436                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1437                                 dev->name, "_g", '0' + i, "_tx");
1438                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1439                                 dev->name, "_g", '0' + i, "_rx");
1440                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1441                                 dev->name, "_g", '0' + i, "_er");
1442                 } else
1443                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1444         }
1445
1446         /* Initialize the filer table */
1447         gfar_init_filer_table(priv);
1448
1449         /* Print out the device info */
1450         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1451
1452         /* Even more device info helps when determining which kernel
1453          * provided which set of benchmarks.
1454          */
1455         netdev_info(dev, "Running with NAPI enabled\n");
1456         for (i = 0; i < priv->num_rx_queues; i++)
1457                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1458                             i, priv->rx_queue[i]->rx_ring_size);
1459         for (i = 0; i < priv->num_tx_queues; i++)
1460                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1461                             i, priv->tx_queue[i]->tx_ring_size);
1462
1463         return 0;
1464
1465 register_fail:
1466         unmap_group_regs(priv);
1467         gfar_free_rx_queues(priv);
1468         gfar_free_tx_queues(priv);
1469         of_node_put(priv->phy_node);
1470         of_node_put(priv->tbi_node);
1471         free_gfar_dev(priv);
1472         return err;
1473 }
1474
1475 static int gfar_remove(struct platform_device *ofdev)
1476 {
1477         struct gfar_private *priv = platform_get_drvdata(ofdev);
1478
1479         of_node_put(priv->phy_node);
1480         of_node_put(priv->tbi_node);
1481
1482         unregister_netdev(priv->ndev);
1483         unmap_group_regs(priv);
1484         gfar_free_rx_queues(priv);
1485         gfar_free_tx_queues(priv);
1486         free_gfar_dev(priv);
1487
1488         return 0;
1489 }
1490
1491 #ifdef CONFIG_PM
1492
1493 static void __gfar_filer_disable(struct gfar_private *priv)
1494 {
1495         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1496         u32 temp;
1497
1498         temp = gfar_read(&regs->rctrl);
1499         temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
1500         gfar_write(&regs->rctrl, temp);
1501 }
1502
1503 static void __gfar_filer_enable(struct gfar_private *priv)
1504 {
1505         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1506         u32 temp;
1507
1508         temp = gfar_read(&regs->rctrl);
1509         temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1510         gfar_write(&regs->rctrl, temp);
1511 }
1512
1513 /* Filer rules implementing wol capabilities */
1514 static void gfar_filer_config_wol(struct gfar_private *priv)
1515 {
1516         unsigned int i;
1517         u32 rqfcr;
1518
1519         __gfar_filer_disable(priv);
1520
1521         /* clear the filer table, reject any packet by default */
1522         rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
1523         for (i = 0; i <= MAX_FILER_IDX; i++)
1524                 gfar_write_filer(priv, i, rqfcr, 0);
1525
1526         i = 0;
1527         if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
1528                 /* unicast packet, accept it */
1529                 struct net_device *ndev = priv->ndev;
1530                 /* get the default rx queue index */
1531                 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
1532                 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
1533                                     (ndev->dev_addr[1] << 8) |
1534                                      ndev->dev_addr[2];
1535
1536                 rqfcr = (qindex << 10) | RQFCR_AND |
1537                         RQFCR_CMP_EXACT | RQFCR_PID_DAH;
1538
1539                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1540
1541                 dest_mac_addr = (ndev->dev_addr[3] << 16) |
1542                                 (ndev->dev_addr[4] << 8) |
1543                                  ndev->dev_addr[5];
1544                 rqfcr = (qindex << 10) | RQFCR_GPI |
1545                         RQFCR_CMP_EXACT | RQFCR_PID_DAL;
1546                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1547         }
1548
1549         __gfar_filer_enable(priv);
1550 }
1551
1552 static void gfar_filer_restore_table(struct gfar_private *priv)
1553 {
1554         u32 rqfcr, rqfpr;
1555         unsigned int i;
1556
1557         __gfar_filer_disable(priv);
1558
1559         for (i = 0; i <= MAX_FILER_IDX; i++) {
1560                 rqfcr = priv->ftp_rqfcr[i];
1561                 rqfpr = priv->ftp_rqfpr[i];
1562                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1563         }
1564
1565         __gfar_filer_enable(priv);
1566 }
1567
1568 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
1569 static void gfar_start_wol_filer(struct gfar_private *priv)
1570 {
1571         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1572         u32 tempval;
1573         int i = 0;
1574
1575         /* Enable Rx hw queues */
1576         gfar_write(&regs->rqueue, priv->rqueue);
1577
1578         /* Initialize DMACTRL to have WWR and WOP */
1579         tempval = gfar_read(&regs->dmactrl);
1580         tempval |= DMACTRL_INIT_SETTINGS;
1581         gfar_write(&regs->dmactrl, tempval);
1582
1583         /* Make sure we aren't stopped */
1584         tempval = gfar_read(&regs->dmactrl);
1585         tempval &= ~DMACTRL_GRS;
1586         gfar_write(&regs->dmactrl, tempval);
1587
1588         for (i = 0; i < priv->num_grps; i++) {
1589                 regs = priv->gfargrp[i].regs;
1590                 /* Clear RHLT, so that the DMA starts polling now */
1591                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1592                 /* enable the Filer General Purpose Interrupt */
1593                 gfar_write(&regs->imask, IMASK_FGPI);
1594         }
1595
1596         /* Enable Rx DMA */
1597         tempval = gfar_read(&regs->maccfg1);
1598         tempval |= MACCFG1_RX_EN;
1599         gfar_write(&regs->maccfg1, tempval);
1600 }
1601
1602 static int gfar_suspend(struct device *dev)
1603 {
1604         struct gfar_private *priv = dev_get_drvdata(dev);
1605         struct net_device *ndev = priv->ndev;
1606         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1607         u32 tempval;
1608         u16 wol = priv->wol_opts;
1609
1610         if (!netif_running(ndev))
1611                 return 0;
1612
1613         disable_napi(priv);
1614         netif_tx_lock(ndev);
1615         netif_device_detach(ndev);
1616         netif_tx_unlock(ndev);
1617
1618         gfar_halt(priv);
1619
1620         if (wol & GFAR_WOL_MAGIC) {
1621                 /* Enable interrupt on Magic Packet */
1622                 gfar_write(&regs->imask, IMASK_MAG);
1623
1624                 /* Enable Magic Packet mode */
1625                 tempval = gfar_read(&regs->maccfg2);
1626                 tempval |= MACCFG2_MPEN;
1627                 gfar_write(&regs->maccfg2, tempval);
1628
1629                 /* re-enable the Rx block */
1630                 tempval = gfar_read(&regs->maccfg1);
1631                 tempval |= MACCFG1_RX_EN;
1632                 gfar_write(&regs->maccfg1, tempval);
1633
1634         } else if (wol & GFAR_WOL_FILER_UCAST) {
1635                 gfar_filer_config_wol(priv);
1636                 gfar_start_wol_filer(priv);
1637
1638         } else {
1639                 phy_stop(priv->phydev);
1640         }
1641
1642         return 0;
1643 }
1644
1645 static int gfar_resume(struct device *dev)
1646 {
1647         struct gfar_private *priv = dev_get_drvdata(dev);
1648         struct net_device *ndev = priv->ndev;
1649         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1650         u32 tempval;
1651         u16 wol = priv->wol_opts;
1652
1653         if (!netif_running(ndev))
1654                 return 0;
1655
1656         if (wol & GFAR_WOL_MAGIC) {
1657                 /* Disable Magic Packet mode */
1658                 tempval = gfar_read(&regs->maccfg2);
1659                 tempval &= ~MACCFG2_MPEN;
1660                 gfar_write(&regs->maccfg2, tempval);
1661
1662         } else if (wol & GFAR_WOL_FILER_UCAST) {
1663                 /* need to stop rx only, tx is already down */
1664                 gfar_halt(priv);
1665                 gfar_filer_restore_table(priv);
1666
1667         } else {
1668                 phy_start(priv->phydev);
1669         }
1670
1671         gfar_start(priv);
1672
1673         netif_device_attach(ndev);
1674         enable_napi(priv);
1675
1676         return 0;
1677 }
1678
1679 static int gfar_restore(struct device *dev)
1680 {
1681         struct gfar_private *priv = dev_get_drvdata(dev);
1682         struct net_device *ndev = priv->ndev;
1683
1684         if (!netif_running(ndev)) {
1685                 netif_device_attach(ndev);
1686
1687                 return 0;
1688         }
1689
1690         gfar_init_bds(ndev);
1691
1692         gfar_mac_reset(priv);
1693
1694         gfar_init_tx_rx_base(priv);
1695
1696         gfar_start(priv);
1697
1698         priv->oldlink = 0;
1699         priv->oldspeed = 0;
1700         priv->oldduplex = -1;
1701
1702         if (priv->phydev)
1703                 phy_start(priv->phydev);
1704
1705         netif_device_attach(ndev);
1706         enable_napi(priv);
1707
1708         return 0;
1709 }
1710
1711 static struct dev_pm_ops gfar_pm_ops = {
1712         .suspend = gfar_suspend,
1713         .resume = gfar_resume,
1714         .freeze = gfar_suspend,
1715         .thaw = gfar_resume,
1716         .restore = gfar_restore,
1717 };
1718
1719 #define GFAR_PM_OPS (&gfar_pm_ops)
1720
1721 #else
1722
1723 #define GFAR_PM_OPS NULL
1724
1725 #endif
1726
1727 /* Reads the controller's registers to determine what interface
1728  * connects it to the PHY.
1729  */
1730 static phy_interface_t gfar_get_interface(struct net_device *dev)
1731 {
1732         struct gfar_private *priv = netdev_priv(dev);
1733         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1734         u32 ecntrl;
1735
1736         ecntrl = gfar_read(&regs->ecntrl);
1737
1738         if (ecntrl & ECNTRL_SGMII_MODE)
1739                 return PHY_INTERFACE_MODE_SGMII;
1740
1741         if (ecntrl & ECNTRL_TBI_MODE) {
1742                 if (ecntrl & ECNTRL_REDUCED_MODE)
1743                         return PHY_INTERFACE_MODE_RTBI;
1744                 else
1745                         return PHY_INTERFACE_MODE_TBI;
1746         }
1747
1748         if (ecntrl & ECNTRL_REDUCED_MODE) {
1749                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1750                         return PHY_INTERFACE_MODE_RMII;
1751                 }
1752                 else {
1753                         phy_interface_t interface = priv->interface;
1754
1755                         /* This isn't autodetected right now, so it must
1756                          * be set by the device tree or platform code.
1757                          */
1758                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1759                                 return PHY_INTERFACE_MODE_RGMII_ID;
1760
1761                         return PHY_INTERFACE_MODE_RGMII;
1762                 }
1763         }
1764
1765         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1766                 return PHY_INTERFACE_MODE_GMII;
1767
1768         return PHY_INTERFACE_MODE_MII;
1769 }
1770
1771
1772 /* Initializes driver's PHY state, and attaches to the PHY.
1773  * Returns 0 on success.
1774  */
1775 static int init_phy(struct net_device *dev)
1776 {
1777         struct gfar_private *priv = netdev_priv(dev);
1778         uint gigabit_support =
1779                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1780                 GFAR_SUPPORTED_GBIT : 0;
1781         phy_interface_t interface;
1782
1783         priv->oldlink = 0;
1784         priv->oldspeed = 0;
1785         priv->oldduplex = -1;
1786
1787         interface = gfar_get_interface(dev);
1788
1789         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1790                                       interface);
1791         if (!priv->phydev) {
1792                 dev_err(&dev->dev, "could not attach to PHY\n");
1793                 return -ENODEV;
1794         }
1795
1796         if (interface == PHY_INTERFACE_MODE_SGMII)
1797                 gfar_configure_serdes(dev);
1798
1799         /* Remove any features not supported by the controller */
1800         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1801         priv->phydev->advertising = priv->phydev->supported;
1802
1803         /* Add support for flow control, but don't advertise it by default */
1804         priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1805
1806         return 0;
1807 }
1808
1809 /* Initialize TBI PHY interface for communicating with the
1810  * SERDES lynx PHY on the chip.  We communicate with this PHY
1811  * through the MDIO bus on each controller, treating it as a
1812  * "normal" PHY at the address found in the TBIPA register.  We assume
1813  * that the TBIPA register is valid.  Either the MDIO bus code will set
1814  * it to a value that doesn't conflict with other PHYs on the bus, or the
1815  * value doesn't matter, as there are no other PHYs on the bus.
1816  */
1817 static void gfar_configure_serdes(struct net_device *dev)
1818 {
1819         struct gfar_private *priv = netdev_priv(dev);
1820         struct phy_device *tbiphy;
1821
1822         if (!priv->tbi_node) {
1823                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1824                                     "device tree specify a tbi-handle\n");
1825                 return;
1826         }
1827
1828         tbiphy = of_phy_find_device(priv->tbi_node);
1829         if (!tbiphy) {
1830                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1831                 return;
1832         }
1833
1834         /* If the link is already up, we must already be ok, and don't need to
1835          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1836          * everything for us?  Resetting it takes the link down and requires
1837          * several seconds for it to come back.
1838          */
1839         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1840                 put_device(&tbiphy->dev);
1841                 return;
1842         }
1843
1844         /* Single clk mode, mii mode off(for serdes communication) */
1845         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1846
1847         phy_write(tbiphy, MII_ADVERTISE,
1848                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1849                   ADVERTISE_1000XPSE_ASYM);
1850
1851         phy_write(tbiphy, MII_BMCR,
1852                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1853                   BMCR_SPEED1000);
1854
1855         put_device(&tbiphy->dev);
1856 }
1857
1858 static int __gfar_is_rx_idle(struct gfar_private *priv)
1859 {
1860         u32 res;
1861
1862         /* Normaly TSEC should not hang on GRS commands, so we should
1863          * actually wait for IEVENT_GRSC flag.
1864          */
1865         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1866                 return 0;
1867
1868         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1869          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1870          * and the Rx can be safely reset.
1871          */
1872         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1873         res &= 0x7f807f80;
1874         if ((res & 0xffff) == (res >> 16))
1875                 return 1;
1876
1877         return 0;
1878 }
1879
1880 /* Halt the receive and transmit queues */
1881 static void gfar_halt_nodisable(struct gfar_private *priv)
1882 {
1883         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1884         u32 tempval;
1885         unsigned int timeout;
1886         int stopped;
1887
1888         gfar_ints_disable(priv);
1889
1890         if (gfar_is_dma_stopped(priv))
1891                 return;
1892
1893         /* Stop the DMA, and wait for it to stop */
1894         tempval = gfar_read(&regs->dmactrl);
1895         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1896         gfar_write(&regs->dmactrl, tempval);
1897
1898 retry:
1899         timeout = 1000;
1900         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1901                 cpu_relax();
1902                 timeout--;
1903         }
1904
1905         if (!timeout)
1906                 stopped = gfar_is_dma_stopped(priv);
1907
1908         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1909             !__gfar_is_rx_idle(priv))
1910                 goto retry;
1911 }
1912
1913 /* Halt the receive and transmit queues */
1914 void gfar_halt(struct gfar_private *priv)
1915 {
1916         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1917         u32 tempval;
1918
1919         /* Dissable the Rx/Tx hw queues */
1920         gfar_write(&regs->rqueue, 0);
1921         gfar_write(&regs->tqueue, 0);
1922
1923         mdelay(10);
1924
1925         gfar_halt_nodisable(priv);
1926
1927         /* Disable Rx/Tx DMA */
1928         tempval = gfar_read(&regs->maccfg1);
1929         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1930         gfar_write(&regs->maccfg1, tempval);
1931 }
1932
1933 void stop_gfar(struct net_device *dev)
1934 {
1935         struct gfar_private *priv = netdev_priv(dev);
1936
1937         netif_tx_stop_all_queues(dev);
1938
1939         smp_mb__before_atomic();
1940         set_bit(GFAR_DOWN, &priv->state);
1941         smp_mb__after_atomic();
1942
1943         disable_napi(priv);
1944
1945         /* disable ints and gracefully shut down Rx/Tx DMA */
1946         gfar_halt(priv);
1947
1948         phy_stop(priv->phydev);
1949
1950         free_skb_resources(priv);
1951 }
1952
1953 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1954 {
1955         struct txbd8 *txbdp;
1956         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1957         int i, j;
1958
1959         txbdp = tx_queue->tx_bd_base;
1960
1961         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1962                 if (!tx_queue->tx_skbuff[i])
1963                         continue;
1964
1965                 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1966                                  be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1967                 txbdp->lstatus = 0;
1968                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1969                      j++) {
1970                         txbdp++;
1971                         dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1972                                        be16_to_cpu(txbdp->length),
1973                                        DMA_TO_DEVICE);
1974                 }
1975                 txbdp++;
1976                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1977                 tx_queue->tx_skbuff[i] = NULL;
1978         }
1979         kfree(tx_queue->tx_skbuff);
1980         tx_queue->tx_skbuff = NULL;
1981 }
1982
1983 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1984 {
1985         int i;
1986
1987         struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1988
1989         if (rx_queue->skb)
1990                 dev_kfree_skb(rx_queue->skb);
1991
1992         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1993                 struct  gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1994
1995                 rxbdp->lstatus = 0;
1996                 rxbdp->bufPtr = 0;
1997                 rxbdp++;
1998
1999                 if (!rxb->page)
2000                         continue;
2001
2002                 dma_unmap_single(rx_queue->dev, rxb->dma,
2003                                  PAGE_SIZE, DMA_FROM_DEVICE);
2004                 __free_page(rxb->page);
2005
2006                 rxb->page = NULL;
2007         }
2008
2009         kfree(rx_queue->rx_buff);
2010         rx_queue->rx_buff = NULL;
2011 }
2012
2013 /* If there are any tx skbs or rx skbs still around, free them.
2014  * Then free tx_skbuff and rx_skbuff
2015  */
2016 static void free_skb_resources(struct gfar_private *priv)
2017 {
2018         struct gfar_priv_tx_q *tx_queue = NULL;
2019         struct gfar_priv_rx_q *rx_queue = NULL;
2020         int i;
2021
2022         /* Go through all the buffer descriptors and free their data buffers */
2023         for (i = 0; i < priv->num_tx_queues; i++) {
2024                 struct netdev_queue *txq;
2025
2026                 tx_queue = priv->tx_queue[i];
2027                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
2028                 if (tx_queue->tx_skbuff)
2029                         free_skb_tx_queue(tx_queue);
2030                 netdev_tx_reset_queue(txq);
2031         }
2032
2033         for (i = 0; i < priv->num_rx_queues; i++) {
2034                 rx_queue = priv->rx_queue[i];
2035                 if (rx_queue->rx_buff)
2036                         free_skb_rx_queue(rx_queue);
2037         }
2038
2039         dma_free_coherent(priv->dev,
2040                           sizeof(struct txbd8) * priv->total_tx_ring_size +
2041                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
2042                           priv->tx_queue[0]->tx_bd_base,
2043                           priv->tx_queue[0]->tx_bd_dma_base);
2044 }
2045
2046 void gfar_start(struct gfar_private *priv)
2047 {
2048         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2049         u32 tempval;
2050         int i = 0;
2051
2052         /* Enable Rx/Tx hw queues */
2053         gfar_write(&regs->rqueue, priv->rqueue);
2054         gfar_write(&regs->tqueue, priv->tqueue);
2055
2056         /* Initialize DMACTRL to have WWR and WOP */
2057         tempval = gfar_read(&regs->dmactrl);
2058         tempval |= DMACTRL_INIT_SETTINGS;
2059         gfar_write(&regs->dmactrl, tempval);
2060
2061         /* Make sure we aren't stopped */
2062         tempval = gfar_read(&regs->dmactrl);
2063         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
2064         gfar_write(&regs->dmactrl, tempval);
2065
2066         for (i = 0; i < priv->num_grps; i++) {
2067                 regs = priv->gfargrp[i].regs;
2068                 /* Clear THLT/RHLT, so that the DMA starts polling now */
2069                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
2070                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
2071         }
2072
2073         /* Enable Rx/Tx DMA */
2074         tempval = gfar_read(&regs->maccfg1);
2075         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2076         gfar_write(&regs->maccfg1, tempval);
2077
2078         gfar_ints_enable(priv);
2079
2080         priv->ndev->trans_start = jiffies; /* prevent tx timeout */
2081 }
2082
2083 static void free_grp_irqs(struct gfar_priv_grp *grp)
2084 {
2085         free_irq(gfar_irq(grp, TX)->irq, grp);
2086         free_irq(gfar_irq(grp, RX)->irq, grp);
2087         free_irq(gfar_irq(grp, ER)->irq, grp);
2088 }
2089
2090 static int register_grp_irqs(struct gfar_priv_grp *grp)
2091 {
2092         struct gfar_private *priv = grp->priv;
2093         struct net_device *dev = priv->ndev;
2094         int err;
2095
2096         /* If the device has multiple interrupts, register for
2097          * them.  Otherwise, only register for the one
2098          */
2099         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2100                 /* Install our interrupt handlers for Error,
2101                  * Transmit, and Receive
2102                  */
2103                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2104                                   gfar_irq(grp, ER)->name, grp);
2105                 if (err < 0) {
2106                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2107                                   gfar_irq(grp, ER)->irq);
2108
2109                         goto err_irq_fail;
2110                 }
2111                 enable_irq_wake(gfar_irq(grp, ER)->irq);
2112
2113                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2114                                   gfar_irq(grp, TX)->name, grp);
2115                 if (err < 0) {
2116                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2117                                   gfar_irq(grp, TX)->irq);
2118                         goto tx_irq_fail;
2119                 }
2120                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2121                                   gfar_irq(grp, RX)->name, grp);
2122                 if (err < 0) {
2123                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2124                                   gfar_irq(grp, RX)->irq);
2125                         goto rx_irq_fail;
2126                 }
2127                 enable_irq_wake(gfar_irq(grp, RX)->irq);
2128
2129         } else {
2130                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2131                                   gfar_irq(grp, TX)->name, grp);
2132                 if (err < 0) {
2133                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2134                                   gfar_irq(grp, TX)->irq);
2135                         goto err_irq_fail;
2136                 }
2137                 enable_irq_wake(gfar_irq(grp, TX)->irq);
2138         }
2139
2140         return 0;
2141
2142 rx_irq_fail:
2143         free_irq(gfar_irq(grp, TX)->irq, grp);
2144 tx_irq_fail:
2145         free_irq(gfar_irq(grp, ER)->irq, grp);
2146 err_irq_fail:
2147         return err;
2148
2149 }
2150
2151 static void gfar_free_irq(struct gfar_private *priv)
2152 {
2153         int i;
2154
2155         /* Free the IRQs */
2156         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2157                 for (i = 0; i < priv->num_grps; i++)
2158                         free_grp_irqs(&priv->gfargrp[i]);
2159         } else {
2160                 for (i = 0; i < priv->num_grps; i++)
2161                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2162                                  &priv->gfargrp[i]);
2163         }
2164 }
2165
2166 static int gfar_request_irq(struct gfar_private *priv)
2167 {
2168         int err, i, j;
2169
2170         for (i = 0; i < priv->num_grps; i++) {
2171                 err = register_grp_irqs(&priv->gfargrp[i]);
2172                 if (err) {
2173                         for (j = 0; j < i; j++)
2174                                 free_grp_irqs(&priv->gfargrp[j]);
2175                         return err;
2176                 }
2177         }
2178
2179         return 0;
2180 }
2181
2182 /* Bring the controller up and running */
2183 int startup_gfar(struct net_device *ndev)
2184 {
2185         struct gfar_private *priv = netdev_priv(ndev);
2186         int err;
2187
2188         gfar_mac_reset(priv);
2189
2190         err = gfar_alloc_skb_resources(ndev);
2191         if (err)
2192                 return err;
2193
2194         gfar_init_tx_rx_base(priv);
2195
2196         smp_mb__before_atomic();
2197         clear_bit(GFAR_DOWN, &priv->state);
2198         smp_mb__after_atomic();
2199
2200         /* Start Rx/Tx DMA and enable the interrupts */
2201         gfar_start(priv);
2202
2203         /* force link state update after mac reset */
2204         priv->oldlink = 0;
2205         priv->oldspeed = 0;
2206         priv->oldduplex = -1;
2207
2208         phy_start(priv->phydev);
2209
2210         enable_napi(priv);
2211
2212         netif_tx_wake_all_queues(ndev);
2213
2214         return 0;
2215 }
2216
2217 /* Called when something needs to use the ethernet device
2218  * Returns 0 for success.
2219  */
2220 static int gfar_enet_open(struct net_device *dev)
2221 {
2222         struct gfar_private *priv = netdev_priv(dev);
2223         int err;
2224
2225         err = init_phy(dev);
2226         if (err)
2227                 return err;
2228
2229         err = gfar_request_irq(priv);
2230         if (err)
2231                 return err;
2232
2233         err = startup_gfar(dev);
2234         if (err)
2235                 return err;
2236
2237         return err;
2238 }
2239
2240 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2241 {
2242         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2243
2244         memset(fcb, 0, GMAC_FCB_LEN);
2245
2246         return fcb;
2247 }
2248
2249 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2250                                     int fcb_length)
2251 {
2252         /* If we're here, it's a IP packet with a TCP or UDP
2253          * payload.  We set it to checksum, using a pseudo-header
2254          * we provide
2255          */
2256         u8 flags = TXFCB_DEFAULT;
2257
2258         /* Tell the controller what the protocol is
2259          * And provide the already calculated phcs
2260          */
2261         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2262                 flags |= TXFCB_UDP;
2263                 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2264         } else
2265                 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2266
2267         /* l3os is the distance between the start of the
2268          * frame (skb->data) and the start of the IP hdr.
2269          * l4os is the distance between the start of the
2270          * l3 hdr and the l4 hdr
2271          */
2272         fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2273         fcb->l4os = skb_network_header_len(skb);
2274
2275         fcb->flags = flags;
2276 }
2277
2278 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2279 {
2280         fcb->flags |= TXFCB_VLN;
2281         fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2282 }
2283
2284 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2285                                       struct txbd8 *base, int ring_size)
2286 {
2287         struct txbd8 *new_bd = bdp + stride;
2288
2289         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2290 }
2291
2292 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2293                                       int ring_size)
2294 {
2295         return skip_txbd(bdp, 1, base, ring_size);
2296 }
2297
2298 /* eTSEC12: csum generation not supported for some fcb offsets */
2299 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2300                                        unsigned long fcb_addr)
2301 {
2302         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2303                (fcb_addr % 0x20) > 0x18);
2304 }
2305
2306 /* eTSEC76: csum generation for frames larger than 2500 may
2307  * cause excess delays before start of transmission
2308  */
2309 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2310                                        unsigned int len)
2311 {
2312         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2313                (len > 2500));
2314 }
2315
2316 /* This is called by the kernel when a frame is ready for transmission.
2317  * It is pointed to by the dev->hard_start_xmit function pointer
2318  */
2319 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2320 {
2321         struct gfar_private *priv = netdev_priv(dev);
2322         struct gfar_priv_tx_q *tx_queue = NULL;
2323         struct netdev_queue *txq;
2324         struct gfar __iomem *regs = NULL;
2325         struct txfcb *fcb = NULL;
2326         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2327         u32 lstatus;
2328         int i, rq = 0;
2329         int do_tstamp, do_csum, do_vlan;
2330         u32 bufaddr;
2331         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2332
2333         rq = skb->queue_mapping;
2334         tx_queue = priv->tx_queue[rq];
2335         txq = netdev_get_tx_queue(dev, rq);
2336         base = tx_queue->tx_bd_base;
2337         regs = tx_queue->grp->regs;
2338
2339         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2340         do_vlan = skb_vlan_tag_present(skb);
2341         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2342                     priv->hwts_tx_en;
2343
2344         if (do_csum || do_vlan)
2345                 fcb_len = GMAC_FCB_LEN;
2346
2347         /* check if time stamp should be generated */
2348         if (unlikely(do_tstamp))
2349                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2350
2351         /* make space for additional header when fcb is needed */
2352         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2353                 struct sk_buff *skb_new;
2354
2355                 skb_new = skb_realloc_headroom(skb, fcb_len);
2356                 if (!skb_new) {
2357                         dev->stats.tx_errors++;
2358                         dev_kfree_skb_any(skb);
2359                         return NETDEV_TX_OK;
2360                 }
2361
2362                 if (skb->sk)
2363                         skb_set_owner_w(skb_new, skb->sk);
2364                 dev_consume_skb_any(skb);
2365                 skb = skb_new;
2366         }
2367
2368         /* total number of fragments in the SKB */
2369         nr_frags = skb_shinfo(skb)->nr_frags;
2370
2371         /* calculate the required number of TxBDs for this skb */
2372         if (unlikely(do_tstamp))
2373                 nr_txbds = nr_frags + 2;
2374         else
2375                 nr_txbds = nr_frags + 1;
2376
2377         /* check if there is space to queue this packet */
2378         if (nr_txbds > tx_queue->num_txbdfree) {
2379                 /* no space, stop the queue */
2380                 netif_tx_stop_queue(txq);
2381                 dev->stats.tx_fifo_errors++;
2382                 return NETDEV_TX_BUSY;
2383         }
2384
2385         /* Update transmit stats */
2386         bytes_sent = skb->len;
2387         tx_queue->stats.tx_bytes += bytes_sent;
2388         /* keep Tx bytes on wire for BQL accounting */
2389         GFAR_CB(skb)->bytes_sent = bytes_sent;
2390         tx_queue->stats.tx_packets++;
2391
2392         txbdp = txbdp_start = tx_queue->cur_tx;
2393         lstatus = be32_to_cpu(txbdp->lstatus);
2394
2395         /* Time stamp insertion requires one additional TxBD */
2396         if (unlikely(do_tstamp))
2397                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2398                                                  tx_queue->tx_ring_size);
2399
2400         if (nr_frags == 0) {
2401                 if (unlikely(do_tstamp)) {
2402                         u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2403
2404                         lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2405                         txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2406                 } else {
2407                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2408                 }
2409         } else {
2410                 /* Place the fragment addresses and lengths into the TxBDs */
2411                 for (i = 0; i < nr_frags; i++) {
2412                         unsigned int frag_len;
2413                         /* Point at the next BD, wrapping as needed */
2414                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2415
2416                         frag_len = skb_shinfo(skb)->frags[i].size;
2417
2418                         lstatus = be32_to_cpu(txbdp->lstatus) | frag_len |
2419                                   BD_LFLAG(TXBD_READY);
2420
2421                         /* Handle the last BD specially */
2422                         if (i == nr_frags - 1)
2423                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2424
2425                         bufaddr = skb_frag_dma_map(priv->dev,
2426                                                    &skb_shinfo(skb)->frags[i],
2427                                                    0,
2428                                                    frag_len,
2429                                                    DMA_TO_DEVICE);
2430                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2431                                 goto dma_map_err;
2432
2433                         /* set the TxBD length and buffer pointer */
2434                         txbdp->bufPtr = cpu_to_be32(bufaddr);
2435                         txbdp->lstatus = cpu_to_be32(lstatus);
2436                 }
2437
2438                 lstatus = be32_to_cpu(txbdp_start->lstatus);
2439         }
2440
2441         /* Add TxPAL between FCB and frame if required */
2442         if (unlikely(do_tstamp)) {
2443                 skb_push(skb, GMAC_TXPAL_LEN);
2444                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2445         }
2446
2447         /* Add TxFCB if required */
2448         if (fcb_len) {
2449                 fcb = gfar_add_fcb(skb);
2450                 lstatus |= BD_LFLAG(TXBD_TOE);
2451         }
2452
2453         /* Set up checksumming */
2454         if (do_csum) {
2455                 gfar_tx_checksum(skb, fcb, fcb_len);
2456
2457                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2458                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2459                         __skb_pull(skb, GMAC_FCB_LEN);
2460                         skb_checksum_help(skb);
2461                         if (do_vlan || do_tstamp) {
2462                                 /* put back a new fcb for vlan/tstamp TOE */
2463                                 fcb = gfar_add_fcb(skb);
2464                         } else {
2465                                 /* Tx TOE not used */
2466                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2467                                 fcb = NULL;
2468                         }
2469                 }
2470         }
2471
2472         if (do_vlan)
2473                 gfar_tx_vlan(skb, fcb);
2474
2475         /* Setup tx hardware time stamping if requested */
2476         if (unlikely(do_tstamp)) {
2477                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2478                 fcb->ptp = 1;
2479         }
2480
2481         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2482                                  DMA_TO_DEVICE);
2483         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2484                 goto dma_map_err;
2485
2486         txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2487
2488         /* If time stamping is requested one additional TxBD must be set up. The
2489          * first TxBD points to the FCB and must have a data length of
2490          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2491          * the full frame length.
2492          */
2493         if (unlikely(do_tstamp)) {
2494                 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2495
2496                 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2497                 bufaddr += fcb_len;
2498                 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2499                               (skb_headlen(skb) - fcb_len);
2500
2501                 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2502                 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2503                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2504         } else {
2505                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2506         }
2507
2508         netdev_tx_sent_queue(txq, bytes_sent);
2509
2510         gfar_wmb();
2511
2512         txbdp_start->lstatus = cpu_to_be32(lstatus);
2513
2514         gfar_wmb(); /* force lstatus write before tx_skbuff */
2515
2516         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2517
2518         /* Update the current skb pointer to the next entry we will use
2519          * (wrapping if necessary)
2520          */
2521         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2522                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2523
2524         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2525
2526         /* We can work in parallel with gfar_clean_tx_ring(), except
2527          * when modifying num_txbdfree. Note that we didn't grab the lock
2528          * when we were reading the num_txbdfree and checking for available
2529          * space, that's because outside of this function it can only grow.
2530          */
2531         spin_lock_bh(&tx_queue->txlock);
2532         /* reduce TxBD free count */
2533         tx_queue->num_txbdfree -= (nr_txbds);
2534         spin_unlock_bh(&tx_queue->txlock);
2535
2536         /* If the next BD still needs to be cleaned up, then the bds
2537          * are full.  We need to tell the kernel to stop sending us stuff.
2538          */
2539         if (!tx_queue->num_txbdfree) {
2540                 netif_tx_stop_queue(txq);
2541
2542                 dev->stats.tx_fifo_errors++;
2543         }
2544
2545         /* Tell the DMA to go go go */
2546         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2547
2548         return NETDEV_TX_OK;
2549
2550 dma_map_err:
2551         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2552         if (do_tstamp)
2553                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2554         for (i = 0; i < nr_frags; i++) {
2555                 lstatus = be32_to_cpu(txbdp->lstatus);
2556                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2557                         break;
2558
2559                 lstatus &= ~BD_LFLAG(TXBD_READY);
2560                 txbdp->lstatus = cpu_to_be32(lstatus);
2561                 bufaddr = be32_to_cpu(txbdp->bufPtr);
2562                 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2563                                DMA_TO_DEVICE);
2564                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2565         }
2566         gfar_wmb();
2567         dev_kfree_skb_any(skb);
2568         return NETDEV_TX_OK;
2569 }
2570
2571 /* Stops the kernel queue, and halts the controller */
2572 static int gfar_close(struct net_device *dev)
2573 {
2574         struct gfar_private *priv = netdev_priv(dev);
2575
2576         cancel_work_sync(&priv->reset_task);
2577         stop_gfar(dev);
2578
2579         /* Disconnect from the PHY */
2580         phy_disconnect(priv->phydev);
2581         priv->phydev = NULL;
2582
2583         gfar_free_irq(priv);
2584
2585         return 0;
2586 }
2587
2588 /* Changes the mac address if the controller is not running. */
2589 static int gfar_set_mac_address(struct net_device *dev)
2590 {
2591         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2592
2593         return 0;
2594 }
2595
2596 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2597 {
2598         struct gfar_private *priv = netdev_priv(dev);
2599         int frame_size = new_mtu + ETH_HLEN;
2600
2601         if ((frame_size < 64) || (frame_size > GFAR_JUMBO_FRAME_SIZE)) {
2602                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2603                 return -EINVAL;
2604         }
2605
2606         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2607                 cpu_relax();
2608
2609         if (dev->flags & IFF_UP)
2610                 stop_gfar(dev);
2611
2612         dev->mtu = new_mtu;
2613
2614         if (dev->flags & IFF_UP)
2615                 startup_gfar(dev);
2616
2617         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2618
2619         return 0;
2620 }
2621
2622 void reset_gfar(struct net_device *ndev)
2623 {
2624         struct gfar_private *priv = netdev_priv(ndev);
2625
2626         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2627                 cpu_relax();
2628
2629         stop_gfar(ndev);
2630         startup_gfar(ndev);
2631
2632         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2633 }
2634
2635 /* gfar_reset_task gets scheduled when a packet has not been
2636  * transmitted after a set amount of time.
2637  * For now, assume that clearing out all the structures, and
2638  * starting over will fix the problem.
2639  */
2640 static void gfar_reset_task(struct work_struct *work)
2641 {
2642         struct gfar_private *priv = container_of(work, struct gfar_private,
2643                                                  reset_task);
2644         reset_gfar(priv->ndev);
2645 }
2646
2647 static void gfar_timeout(struct net_device *dev)
2648 {
2649         struct gfar_private *priv = netdev_priv(dev);
2650
2651         dev->stats.tx_errors++;
2652         schedule_work(&priv->reset_task);
2653 }
2654
2655 /* Interrupt Handler for Transmit complete */
2656 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2657 {
2658         struct net_device *dev = tx_queue->dev;
2659         struct netdev_queue *txq;
2660         struct gfar_private *priv = netdev_priv(dev);
2661         struct txbd8 *bdp, *next = NULL;
2662         struct txbd8 *lbdp = NULL;
2663         struct txbd8 *base = tx_queue->tx_bd_base;
2664         struct sk_buff *skb;
2665         int skb_dirtytx;
2666         int tx_ring_size = tx_queue->tx_ring_size;
2667         int frags = 0, nr_txbds = 0;
2668         int i;
2669         int howmany = 0;
2670         int tqi = tx_queue->qindex;
2671         unsigned int bytes_sent = 0;
2672         u32 lstatus;
2673         size_t buflen;
2674
2675         txq = netdev_get_tx_queue(dev, tqi);
2676         bdp = tx_queue->dirty_tx;
2677         skb_dirtytx = tx_queue->skb_dirtytx;
2678
2679         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2680
2681                 frags = skb_shinfo(skb)->nr_frags;
2682
2683                 /* When time stamping, one additional TxBD must be freed.
2684                  * Also, we need to dma_unmap_single() the TxPAL.
2685                  */
2686                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2687                         nr_txbds = frags + 2;
2688                 else
2689                         nr_txbds = frags + 1;
2690
2691                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2692
2693                 lstatus = be32_to_cpu(lbdp->lstatus);
2694
2695                 /* Only clean completed frames */
2696                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2697                     (lstatus & BD_LENGTH_MASK))
2698                         break;
2699
2700                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2701                         next = next_txbd(bdp, base, tx_ring_size);
2702                         buflen = be16_to_cpu(next->length) +
2703                                  GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2704                 } else
2705                         buflen = be16_to_cpu(bdp->length);
2706
2707                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2708                                  buflen, DMA_TO_DEVICE);
2709
2710                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2711                         struct skb_shared_hwtstamps shhwtstamps;
2712                         u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2713                                           ~0x7UL);
2714
2715                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2716                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2717                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2718                         skb_tstamp_tx(skb, &shhwtstamps);
2719                         gfar_clear_txbd_status(bdp);
2720                         bdp = next;
2721                 }
2722
2723                 gfar_clear_txbd_status(bdp);
2724                 bdp = next_txbd(bdp, base, tx_ring_size);
2725
2726                 for (i = 0; i < frags; i++) {
2727                         dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2728                                        be16_to_cpu(bdp->length),
2729                                        DMA_TO_DEVICE);
2730                         gfar_clear_txbd_status(bdp);
2731                         bdp = next_txbd(bdp, base, tx_ring_size);
2732                 }
2733
2734                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2735
2736                 dev_kfree_skb_any(skb);
2737
2738                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2739
2740                 skb_dirtytx = (skb_dirtytx + 1) &
2741                               TX_RING_MOD_MASK(tx_ring_size);
2742
2743                 howmany++;
2744                 spin_lock(&tx_queue->txlock);
2745                 tx_queue->num_txbdfree += nr_txbds;
2746                 spin_unlock(&tx_queue->txlock);
2747         }
2748
2749         /* If we freed a buffer, we can restart transmission, if necessary */
2750         if (tx_queue->num_txbdfree &&
2751             netif_tx_queue_stopped(txq) &&
2752             !(test_bit(GFAR_DOWN, &priv->state)))
2753                 netif_wake_subqueue(priv->ndev, tqi);
2754
2755         /* Update dirty indicators */
2756         tx_queue->skb_dirtytx = skb_dirtytx;
2757         tx_queue->dirty_tx = bdp;
2758
2759         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2760 }
2761
2762 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2763 {
2764         struct page *page;
2765         dma_addr_t addr;
2766
2767         page = dev_alloc_page();
2768         if (unlikely(!page))
2769                 return false;
2770
2771         addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2772         if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2773                 __free_page(page);
2774
2775                 return false;
2776         }
2777
2778         rxb->dma = addr;
2779         rxb->page = page;
2780         rxb->page_offset = 0;
2781
2782         return true;
2783 }
2784
2785 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2786 {
2787         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2788         struct gfar_extra_stats *estats = &priv->extra_stats;
2789
2790         netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2791         atomic64_inc(&estats->rx_alloc_err);
2792 }
2793
2794 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2795                                 int alloc_cnt)
2796 {
2797         struct rxbd8 *bdp;
2798         struct gfar_rx_buff *rxb;
2799         int i;
2800
2801         i = rx_queue->next_to_use;
2802         bdp = &rx_queue->rx_bd_base[i];
2803         rxb = &rx_queue->rx_buff[i];
2804
2805         while (alloc_cnt--) {
2806                 /* try reuse page */
2807                 if (unlikely(!rxb->page)) {
2808                         if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2809                                 gfar_rx_alloc_err(rx_queue);
2810                                 break;
2811                         }
2812                 }
2813
2814                 /* Setup the new RxBD */
2815                 gfar_init_rxbdp(rx_queue, bdp,
2816                                 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2817
2818                 /* Update to the next pointer */
2819                 bdp++;
2820                 rxb++;
2821
2822                 if (unlikely(++i == rx_queue->rx_ring_size)) {
2823                         i = 0;
2824                         bdp = rx_queue->rx_bd_base;
2825                         rxb = rx_queue->rx_buff;
2826                 }
2827         }
2828
2829         rx_queue->next_to_use = i;
2830         rx_queue->next_to_alloc = i;
2831 }
2832
2833 static void count_errors(u32 lstatus, struct net_device *ndev)
2834 {
2835         struct gfar_private *priv = netdev_priv(ndev);
2836         struct net_device_stats *stats = &ndev->stats;
2837         struct gfar_extra_stats *estats = &priv->extra_stats;
2838
2839         /* If the packet was truncated, none of the other errors matter */
2840         if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2841                 stats->rx_length_errors++;
2842
2843                 atomic64_inc(&estats->rx_trunc);
2844
2845                 return;
2846         }
2847         /* Count the errors, if there were any */
2848         if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2849                 stats->rx_length_errors++;
2850
2851                 if (lstatus & BD_LFLAG(RXBD_LARGE))
2852                         atomic64_inc(&estats->rx_large);
2853                 else
2854                         atomic64_inc(&estats->rx_short);
2855         }
2856         if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2857                 stats->rx_frame_errors++;
2858                 atomic64_inc(&estats->rx_nonoctet);
2859         }
2860         if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2861                 atomic64_inc(&estats->rx_crcerr);
2862                 stats->rx_crc_errors++;
2863         }
2864         if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2865                 atomic64_inc(&estats->rx_overrun);
2866                 stats->rx_over_errors++;
2867         }
2868 }
2869
2870 irqreturn_t gfar_receive(int irq, void *grp_id)
2871 {
2872         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2873         unsigned long flags;
2874         u32 imask, ievent;
2875
2876         ievent = gfar_read(&grp->regs->ievent);
2877
2878         if (unlikely(ievent & IEVENT_FGPI)) {
2879                 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2880                 return IRQ_HANDLED;
2881         }
2882
2883         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2884                 spin_lock_irqsave(&grp->grplock, flags);
2885                 imask = gfar_read(&grp->regs->imask);
2886                 imask &= IMASK_RX_DISABLED;
2887                 gfar_write(&grp->regs->imask, imask);
2888                 spin_unlock_irqrestore(&grp->grplock, flags);
2889                 __napi_schedule(&grp->napi_rx);
2890         } else {
2891                 /* Clear IEVENT, so interrupts aren't called again
2892                  * because of the packets that have already arrived.
2893                  */
2894                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2895         }
2896
2897         return IRQ_HANDLED;
2898 }
2899
2900 /* Interrupt Handler for Transmit complete */
2901 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2902 {
2903         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2904         unsigned long flags;
2905         u32 imask;
2906
2907         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2908                 spin_lock_irqsave(&grp->grplock, flags);
2909                 imask = gfar_read(&grp->regs->imask);
2910                 imask &= IMASK_TX_DISABLED;
2911                 gfar_write(&grp->regs->imask, imask);
2912                 spin_unlock_irqrestore(&grp->grplock, flags);
2913                 __napi_schedule(&grp->napi_tx);
2914         } else {
2915                 /* Clear IEVENT, so interrupts aren't called again
2916                  * because of the packets that have already arrived.
2917                  */
2918                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2919         }
2920
2921         return IRQ_HANDLED;
2922 }
2923
2924 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2925                              struct sk_buff *skb, bool first)
2926 {
2927         unsigned int size = lstatus & BD_LENGTH_MASK;
2928         struct page *page = rxb->page;
2929
2930         /* Remove the FCS from the packet length */
2931         if (likely(lstatus & BD_LFLAG(RXBD_LAST)))
2932                 size -= ETH_FCS_LEN;
2933
2934         if (likely(first))
2935                 skb_put(skb, size);
2936         else
2937                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2938                                 rxb->page_offset + RXBUF_ALIGNMENT,
2939                                 size, GFAR_RXB_TRUESIZE);
2940
2941         /* try reuse page */
2942         if (unlikely(page_count(page) != 1))
2943                 return false;
2944
2945         /* change offset to the other half */
2946         rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2947
2948         atomic_inc(&page->_count);
2949
2950         return true;
2951 }
2952
2953 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2954                                struct gfar_rx_buff *old_rxb)
2955 {
2956         struct gfar_rx_buff *new_rxb;
2957         u16 nta = rxq->next_to_alloc;
2958
2959         new_rxb = &rxq->rx_buff[nta];
2960
2961         /* find next buf that can reuse a page */
2962         nta++;
2963         rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2964
2965         /* copy page reference */
2966         *new_rxb = *old_rxb;
2967
2968         /* sync for use by the device */
2969         dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2970                                          old_rxb->page_offset,
2971                                          GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2972 }
2973
2974 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2975                                             u32 lstatus, struct sk_buff *skb)
2976 {
2977         struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2978         struct page *page = rxb->page;
2979         bool first = false;
2980
2981         if (likely(!skb)) {
2982                 void *buff_addr = page_address(page) + rxb->page_offset;
2983
2984                 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2985                 if (unlikely(!skb)) {
2986                         gfar_rx_alloc_err(rx_queue);
2987                         return NULL;
2988                 }
2989                 skb_reserve(skb, RXBUF_ALIGNMENT);
2990                 first = true;
2991         }
2992
2993         dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2994                                       GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2995
2996         if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2997                 /* reuse the free half of the page */
2998                 gfar_reuse_rx_page(rx_queue, rxb);
2999         } else {
3000                 /* page cannot be reused, unmap it */
3001                 dma_unmap_page(rx_queue->dev, rxb->dma,
3002                                PAGE_SIZE, DMA_FROM_DEVICE);
3003         }
3004
3005         /* clear rxb content */
3006         rxb->page = NULL;
3007
3008         return skb;
3009 }
3010
3011 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
3012 {
3013         /* If valid headers were found, and valid sums
3014          * were verified, then we tell the kernel that no
3015          * checksumming is necessary.  Otherwise, it is [FIXME]
3016          */
3017         if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
3018             (RXFCB_CIP | RXFCB_CTU))
3019                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3020         else
3021                 skb_checksum_none_assert(skb);
3022 }
3023
3024 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
3025 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
3026 {
3027         struct gfar_private *priv = netdev_priv(ndev);
3028         struct rxfcb *fcb = NULL;
3029
3030         /* fcb is at the beginning if exists */
3031         fcb = (struct rxfcb *)skb->data;
3032
3033         /* Remove the FCB from the skb
3034          * Remove the padded bytes, if there are any
3035          */
3036         if (priv->uses_rxfcb)
3037                 skb_pull(skb, GMAC_FCB_LEN);
3038
3039         /* Get receive timestamp from the skb */
3040         if (priv->hwts_rx_en) {
3041                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
3042                 u64 *ns = (u64 *) skb->data;
3043
3044                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3045                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
3046         }
3047
3048         if (priv->padding)
3049                 skb_pull(skb, priv->padding);
3050
3051         if (ndev->features & NETIF_F_RXCSUM)
3052                 gfar_rx_checksum(skb, fcb);
3053
3054         /* Tell the skb what kind of packet this is */
3055         skb->protocol = eth_type_trans(skb, ndev);
3056
3057         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
3058          * Even if vlan rx accel is disabled, on some chips
3059          * RXFCB_VLN is pseudo randomly set.
3060          */
3061         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3062             be16_to_cpu(fcb->flags) & RXFCB_VLN)
3063                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3064                                        be16_to_cpu(fcb->vlctl));
3065 }
3066
3067 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
3068  * until the budget/quota has been reached. Returns the number
3069  * of frames handled
3070  */
3071 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
3072 {
3073         struct net_device *ndev = rx_queue->ndev;
3074         struct gfar_private *priv = netdev_priv(ndev);
3075         struct rxbd8 *bdp;
3076         int i, howmany = 0;
3077         struct sk_buff *skb = rx_queue->skb;
3078         int cleaned_cnt = gfar_rxbd_unused(rx_queue);
3079         unsigned int total_bytes = 0, total_pkts = 0;
3080
3081         /* Get the first full descriptor */
3082         i = rx_queue->next_to_clean;
3083
3084         while (rx_work_limit--) {
3085                 u32 lstatus;
3086
3087                 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
3088                         gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3089                         cleaned_cnt = 0;
3090                 }
3091
3092                 bdp = &rx_queue->rx_bd_base[i];
3093                 lstatus = be32_to_cpu(bdp->lstatus);
3094                 if (lstatus & BD_LFLAG(RXBD_EMPTY))
3095                         break;
3096
3097                 /* order rx buffer descriptor reads */
3098                 rmb();
3099
3100                 /* fetch next to clean buffer from the ring */
3101                 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
3102                 if (unlikely(!skb))
3103                         break;
3104
3105                 cleaned_cnt++;
3106                 howmany++;
3107
3108                 if (unlikely(++i == rx_queue->rx_ring_size))
3109                         i = 0;
3110
3111                 rx_queue->next_to_clean = i;
3112
3113                 /* fetch next buffer if not the last in frame */
3114                 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
3115                         continue;
3116
3117                 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
3118                         count_errors(lstatus, ndev);
3119
3120                         /* discard faulty buffer */
3121                         dev_kfree_skb(skb);
3122                         skb = NULL;
3123                         rx_queue->stats.rx_dropped++;
3124                         continue;
3125                 }
3126
3127                 /* Increment the number of packets */
3128                 total_pkts++;
3129                 total_bytes += skb->len;
3130
3131                 skb_record_rx_queue(skb, rx_queue->qindex);
3132
3133                 gfar_process_frame(ndev, skb);
3134
3135                 /* Send the packet up the stack */
3136                 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3137
3138                 skb = NULL;
3139         }
3140
3141         /* Store incomplete frames for completion */
3142         rx_queue->skb = skb;
3143
3144         rx_queue->stats.rx_packets += total_pkts;
3145         rx_queue->stats.rx_bytes += total_bytes;
3146
3147         if (cleaned_cnt)
3148                 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3149
3150         /* Update Last Free RxBD pointer for LFC */
3151         if (unlikely(priv->tx_actual_en)) {
3152                 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3153
3154                 gfar_write(rx_queue->rfbptr, bdp_dma);
3155         }
3156
3157         return howmany;
3158 }
3159
3160 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3161 {
3162         struct gfar_priv_grp *gfargrp =
3163                 container_of(napi, struct gfar_priv_grp, napi_rx);
3164         struct gfar __iomem *regs = gfargrp->regs;
3165         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3166         int work_done = 0;
3167
3168         /* Clear IEVENT, so interrupts aren't called again
3169          * because of the packets that have already arrived
3170          */
3171         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3172
3173         work_done = gfar_clean_rx_ring(rx_queue, budget);
3174
3175         if (work_done < budget) {
3176                 u32 imask;
3177                 napi_complete(napi);
3178                 /* Clear the halt bit in RSTAT */
3179                 gfar_write(&regs->rstat, gfargrp->rstat);
3180
3181                 spin_lock_irq(&gfargrp->grplock);
3182                 imask = gfar_read(&regs->imask);
3183                 imask |= IMASK_RX_DEFAULT;
3184                 gfar_write(&regs->imask, imask);
3185                 spin_unlock_irq(&gfargrp->grplock);
3186         }
3187
3188         return work_done;
3189 }
3190
3191 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3192 {
3193         struct gfar_priv_grp *gfargrp =
3194                 container_of(napi, struct gfar_priv_grp, napi_tx);
3195         struct gfar __iomem *regs = gfargrp->regs;
3196         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3197         u32 imask;
3198
3199         /* Clear IEVENT, so interrupts aren't called again
3200          * because of the packets that have already arrived
3201          */
3202         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3203
3204         /* run Tx cleanup to completion */
3205         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3206                 gfar_clean_tx_ring(tx_queue);
3207
3208         napi_complete(napi);
3209
3210         spin_lock_irq(&gfargrp->grplock);
3211         imask = gfar_read(&regs->imask);
3212         imask |= IMASK_TX_DEFAULT;
3213         gfar_write(&regs->imask, imask);
3214         spin_unlock_irq(&gfargrp->grplock);
3215
3216         return 0;
3217 }
3218
3219 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3220 {
3221         struct gfar_priv_grp *gfargrp =
3222                 container_of(napi, struct gfar_priv_grp, napi_rx);
3223         struct gfar_private *priv = gfargrp->priv;
3224         struct gfar __iomem *regs = gfargrp->regs;
3225         struct gfar_priv_rx_q *rx_queue = NULL;
3226         int work_done = 0, work_done_per_q = 0;
3227         int i, budget_per_q = 0;
3228         unsigned long rstat_rxf;
3229         int num_act_queues;
3230
3231         /* Clear IEVENT, so interrupts aren't called again
3232          * because of the packets that have already arrived
3233          */
3234         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3235
3236         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3237
3238         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3239         if (num_act_queues)
3240                 budget_per_q = budget/num_act_queues;
3241
3242         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3243                 /* skip queue if not active */
3244                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3245                         continue;
3246
3247                 rx_queue = priv->rx_queue[i];
3248                 work_done_per_q =
3249                         gfar_clean_rx_ring(rx_queue, budget_per_q);
3250                 work_done += work_done_per_q;
3251
3252                 /* finished processing this queue */
3253                 if (work_done_per_q < budget_per_q) {
3254                         /* clear active queue hw indication */
3255                         gfar_write(&regs->rstat,
3256                                    RSTAT_CLEAR_RXF0 >> i);
3257                         num_act_queues--;
3258
3259                         if (!num_act_queues)
3260                                 break;
3261                 }
3262         }
3263
3264         if (!num_act_queues) {
3265                 u32 imask;
3266                 napi_complete(napi);
3267
3268                 /* Clear the halt bit in RSTAT */
3269                 gfar_write(&regs->rstat, gfargrp->rstat);
3270
3271                 spin_lock_irq(&gfargrp->grplock);
3272                 imask = gfar_read(&regs->imask);
3273                 imask |= IMASK_RX_DEFAULT;
3274                 gfar_write(&regs->imask, imask);
3275                 spin_unlock_irq(&gfargrp->grplock);
3276         }
3277
3278         return work_done;
3279 }
3280
3281 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3282 {
3283         struct gfar_priv_grp *gfargrp =
3284                 container_of(napi, struct gfar_priv_grp, napi_tx);
3285         struct gfar_private *priv = gfargrp->priv;
3286         struct gfar __iomem *regs = gfargrp->regs;
3287         struct gfar_priv_tx_q *tx_queue = NULL;
3288         int has_tx_work = 0;
3289         int i;
3290
3291         /* Clear IEVENT, so interrupts aren't called again
3292          * because of the packets that have already arrived
3293          */
3294         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3295
3296         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3297                 tx_queue = priv->tx_queue[i];
3298                 /* run Tx cleanup to completion */
3299                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3300                         gfar_clean_tx_ring(tx_queue);
3301                         has_tx_work = 1;
3302                 }
3303         }
3304
3305         if (!has_tx_work) {
3306                 u32 imask;
3307                 napi_complete(napi);
3308
3309                 spin_lock_irq(&gfargrp->grplock);
3310                 imask = gfar_read(&regs->imask);
3311                 imask |= IMASK_TX_DEFAULT;
3312                 gfar_write(&regs->imask, imask);
3313                 spin_unlock_irq(&gfargrp->grplock);
3314         }
3315
3316         return 0;
3317 }
3318
3319
3320 #ifdef CONFIG_NET_POLL_CONTROLLER
3321 /* Polling 'interrupt' - used by things like netconsole to send skbs
3322  * without having to re-enable interrupts. It's not called while
3323  * the interrupt routine is executing.
3324  */
3325 static void gfar_netpoll(struct net_device *dev)
3326 {
3327         struct gfar_private *priv = netdev_priv(dev);
3328         int i;
3329
3330         /* If the device has multiple interrupts, run tx/rx */
3331         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3332                 for (i = 0; i < priv->num_grps; i++) {
3333                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3334
3335                         disable_irq(gfar_irq(grp, TX)->irq);
3336                         disable_irq(gfar_irq(grp, RX)->irq);
3337                         disable_irq(gfar_irq(grp, ER)->irq);
3338                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3339                         enable_irq(gfar_irq(grp, ER)->irq);
3340                         enable_irq(gfar_irq(grp, RX)->irq);
3341                         enable_irq(gfar_irq(grp, TX)->irq);
3342                 }
3343         } else {
3344                 for (i = 0; i < priv->num_grps; i++) {
3345                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3346
3347                         disable_irq(gfar_irq(grp, TX)->irq);
3348                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3349                         enable_irq(gfar_irq(grp, TX)->irq);
3350                 }
3351         }
3352 }
3353 #endif
3354
3355 /* The interrupt handler for devices with one interrupt */
3356 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3357 {
3358         struct gfar_priv_grp *gfargrp = grp_id;
3359
3360         /* Save ievent for future reference */
3361         u32 events = gfar_read(&gfargrp->regs->ievent);
3362
3363         /* Check for reception */
3364         if (events & IEVENT_RX_MASK)
3365                 gfar_receive(irq, grp_id);
3366
3367         /* Check for transmit completion */
3368         if (events & IEVENT_TX_MASK)
3369                 gfar_transmit(irq, grp_id);
3370
3371         /* Check for errors */
3372         if (events & IEVENT_ERR_MASK)
3373                 gfar_error(irq, grp_id);
3374
3375         return IRQ_HANDLED;
3376 }
3377
3378 /* Called every time the controller might need to be made
3379  * aware of new link state.  The PHY code conveys this
3380  * information through variables in the phydev structure, and this
3381  * function converts those variables into the appropriate
3382  * register values, and can bring down the device if needed.
3383  */
3384 static void adjust_link(struct net_device *dev)
3385 {
3386         struct gfar_private *priv = netdev_priv(dev);
3387         struct phy_device *phydev = priv->phydev;
3388
3389         if (unlikely(phydev->link != priv->oldlink ||
3390                      (phydev->link && (phydev->duplex != priv->oldduplex ||
3391                                        phydev->speed != priv->oldspeed))))
3392                 gfar_update_link_state(priv);
3393 }
3394
3395 /* Update the hash table based on the current list of multicast
3396  * addresses we subscribe to.  Also, change the promiscuity of
3397  * the device based on the flags (this function is called
3398  * whenever dev->flags is changed
3399  */
3400 static void gfar_set_multi(struct net_device *dev)
3401 {
3402         struct netdev_hw_addr *ha;
3403         struct gfar_private *priv = netdev_priv(dev);
3404         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3405         u32 tempval;
3406
3407         if (dev->flags & IFF_PROMISC) {
3408                 /* Set RCTRL to PROM */
3409                 tempval = gfar_read(&regs->rctrl);
3410                 tempval |= RCTRL_PROM;
3411                 gfar_write(&regs->rctrl, tempval);
3412         } else {
3413                 /* Set RCTRL to not PROM */
3414                 tempval = gfar_read(&regs->rctrl);
3415                 tempval &= ~(RCTRL_PROM);
3416                 gfar_write(&regs->rctrl, tempval);
3417         }
3418
3419         if (dev->flags & IFF_ALLMULTI) {
3420                 /* Set the hash to rx all multicast frames */
3421                 gfar_write(&regs->igaddr0, 0xffffffff);
3422                 gfar_write(&regs->igaddr1, 0xffffffff);
3423                 gfar_write(&regs->igaddr2, 0xffffffff);
3424                 gfar_write(&regs->igaddr3, 0xffffffff);
3425                 gfar_write(&regs->igaddr4, 0xffffffff);
3426                 gfar_write(&regs->igaddr5, 0xffffffff);
3427                 gfar_write(&regs->igaddr6, 0xffffffff);
3428                 gfar_write(&regs->igaddr7, 0xffffffff);
3429                 gfar_write(&regs->gaddr0, 0xffffffff);
3430                 gfar_write(&regs->gaddr1, 0xffffffff);
3431                 gfar_write(&regs->gaddr2, 0xffffffff);
3432                 gfar_write(&regs->gaddr3, 0xffffffff);
3433                 gfar_write(&regs->gaddr4, 0xffffffff);
3434                 gfar_write(&regs->gaddr5, 0xffffffff);
3435                 gfar_write(&regs->gaddr6, 0xffffffff);
3436                 gfar_write(&regs->gaddr7, 0xffffffff);
3437         } else {
3438                 int em_num;
3439                 int idx;
3440
3441                 /* zero out the hash */
3442                 gfar_write(&regs->igaddr0, 0x0);
3443                 gfar_write(&regs->igaddr1, 0x0);
3444                 gfar_write(&regs->igaddr2, 0x0);
3445                 gfar_write(&regs->igaddr3, 0x0);
3446                 gfar_write(&regs->igaddr4, 0x0);
3447                 gfar_write(&regs->igaddr5, 0x0);
3448                 gfar_write(&regs->igaddr6, 0x0);
3449                 gfar_write(&regs->igaddr7, 0x0);
3450                 gfar_write(&regs->gaddr0, 0x0);
3451                 gfar_write(&regs->gaddr1, 0x0);
3452                 gfar_write(&regs->gaddr2, 0x0);
3453                 gfar_write(&regs->gaddr3, 0x0);
3454                 gfar_write(&regs->gaddr4, 0x0);
3455                 gfar_write(&regs->gaddr5, 0x0);
3456                 gfar_write(&regs->gaddr6, 0x0);
3457                 gfar_write(&regs->gaddr7, 0x0);
3458
3459                 /* If we have extended hash tables, we need to
3460                  * clear the exact match registers to prepare for
3461                  * setting them
3462                  */
3463                 if (priv->extended_hash) {
3464                         em_num = GFAR_EM_NUM + 1;
3465                         gfar_clear_exact_match(dev);
3466                         idx = 1;
3467                 } else {
3468                         idx = 0;
3469                         em_num = 0;
3470                 }
3471
3472                 if (netdev_mc_empty(dev))
3473                         return;
3474
3475                 /* Parse the list, and set the appropriate bits */
3476                 netdev_for_each_mc_addr(ha, dev) {
3477                         if (idx < em_num) {
3478                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3479                                 idx++;
3480                         } else
3481                                 gfar_set_hash_for_addr(dev, ha->addr);
3482                 }
3483         }
3484 }
3485
3486
3487 /* Clears each of the exact match registers to zero, so they
3488  * don't interfere with normal reception
3489  */
3490 static void gfar_clear_exact_match(struct net_device *dev)
3491 {
3492         int idx;
3493         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3494
3495         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3496                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3497 }
3498
3499 /* Set the appropriate hash bit for the given addr */
3500 /* The algorithm works like so:
3501  * 1) Take the Destination Address (ie the multicast address), and
3502  * do a CRC on it (little endian), and reverse the bits of the
3503  * result.
3504  * 2) Use the 8 most significant bits as a hash into a 256-entry
3505  * table.  The table is controlled through 8 32-bit registers:
3506  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3507  * gaddr7.  This means that the 3 most significant bits in the
3508  * hash index which gaddr register to use, and the 5 other bits
3509  * indicate which bit (assuming an IBM numbering scheme, which
3510  * for PowerPC (tm) is usually the case) in the register holds
3511  * the entry.
3512  */
3513 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3514 {
3515         u32 tempval;
3516         struct gfar_private *priv = netdev_priv(dev);
3517         u32 result = ether_crc(ETH_ALEN, addr);
3518         int width = priv->hash_width;
3519         u8 whichbit = (result >> (32 - width)) & 0x1f;
3520         u8 whichreg = result >> (32 - width + 5);
3521         u32 value = (1 << (31-whichbit));
3522
3523         tempval = gfar_read(priv->hash_regs[whichreg]);
3524         tempval |= value;
3525         gfar_write(priv->hash_regs[whichreg], tempval);
3526 }
3527
3528
3529 /* There are multiple MAC Address register pairs on some controllers
3530  * This function sets the numth pair to a given address
3531  */
3532 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3533                                   const u8 *addr)
3534 {
3535         struct gfar_private *priv = netdev_priv(dev);
3536         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3537         u32 tempval;
3538         u32 __iomem *macptr = &regs->macstnaddr1;
3539
3540         macptr += num*2;
3541
3542         /* For a station address of 0x12345678ABCD in transmission
3543          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3544          * MACnADDR2 is set to 0x34120000.
3545          */
3546         tempval = (addr[5] << 24) | (addr[4] << 16) |
3547                   (addr[3] << 8)  |  addr[2];
3548
3549         gfar_write(macptr, tempval);
3550
3551         tempval = (addr[1] << 24) | (addr[0] << 16);
3552
3553         gfar_write(macptr+1, tempval);
3554 }
3555
3556 /* GFAR error interrupt handler */
3557 static irqreturn_t gfar_error(int irq, void *grp_id)
3558 {
3559         struct gfar_priv_grp *gfargrp = grp_id;
3560         struct gfar __iomem *regs = gfargrp->regs;
3561         struct gfar_private *priv= gfargrp->priv;
3562         struct net_device *dev = priv->ndev;
3563
3564         /* Save ievent for future reference */
3565         u32 events = gfar_read(&regs->ievent);
3566
3567         /* Clear IEVENT */
3568         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3569
3570         /* Magic Packet is not an error. */
3571         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3572             (events & IEVENT_MAG))
3573                 events &= ~IEVENT_MAG;
3574
3575         /* Hmm... */
3576         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3577                 netdev_dbg(dev,
3578                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3579                            events, gfar_read(&regs->imask));
3580
3581         /* Update the error counters */
3582         if (events & IEVENT_TXE) {
3583                 dev->stats.tx_errors++;
3584
3585                 if (events & IEVENT_LC)
3586                         dev->stats.tx_window_errors++;
3587                 if (events & IEVENT_CRL)
3588                         dev->stats.tx_aborted_errors++;
3589                 if (events & IEVENT_XFUN) {
3590                         netif_dbg(priv, tx_err, dev,
3591                                   "TX FIFO underrun, packet dropped\n");
3592                         dev->stats.tx_dropped++;
3593                         atomic64_inc(&priv->extra_stats.tx_underrun);
3594
3595                         schedule_work(&priv->reset_task);
3596                 }
3597                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3598         }
3599         if (events & IEVENT_BSY) {
3600                 dev->stats.rx_over_errors++;
3601                 atomic64_inc(&priv->extra_stats.rx_bsy);
3602
3603                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3604                           gfar_read(&regs->rstat));
3605         }
3606         if (events & IEVENT_BABR) {
3607                 dev->stats.rx_errors++;
3608                 atomic64_inc(&priv->extra_stats.rx_babr);
3609
3610                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3611         }
3612         if (events & IEVENT_EBERR) {
3613                 atomic64_inc(&priv->extra_stats.eberr);
3614                 netif_dbg(priv, rx_err, dev, "bus error\n");
3615         }
3616         if (events & IEVENT_RXC)
3617                 netif_dbg(priv, rx_status, dev, "control frame\n");
3618
3619         if (events & IEVENT_BABT) {
3620                 atomic64_inc(&priv->extra_stats.tx_babt);
3621                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3622         }
3623         return IRQ_HANDLED;
3624 }
3625
3626 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3627 {
3628         struct phy_device *phydev = priv->phydev;
3629         u32 val = 0;
3630
3631         if (!phydev->duplex)
3632                 return val;
3633
3634         if (!priv->pause_aneg_en) {
3635                 if (priv->tx_pause_en)
3636                         val |= MACCFG1_TX_FLOW;
3637                 if (priv->rx_pause_en)
3638                         val |= MACCFG1_RX_FLOW;
3639         } else {
3640                 u16 lcl_adv, rmt_adv;
3641                 u8 flowctrl;
3642                 /* get link partner capabilities */
3643                 rmt_adv = 0;
3644                 if (phydev->pause)
3645                         rmt_adv = LPA_PAUSE_CAP;
3646                 if (phydev->asym_pause)
3647                         rmt_adv |= LPA_PAUSE_ASYM;
3648
3649                 lcl_adv = 0;
3650                 if (phydev->advertising & ADVERTISED_Pause)
3651                         lcl_adv |= ADVERTISE_PAUSE_CAP;
3652                 if (phydev->advertising & ADVERTISED_Asym_Pause)
3653                         lcl_adv |= ADVERTISE_PAUSE_ASYM;
3654
3655                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3656                 if (flowctrl & FLOW_CTRL_TX)
3657                         val |= MACCFG1_TX_FLOW;
3658                 if (flowctrl & FLOW_CTRL_RX)
3659                         val |= MACCFG1_RX_FLOW;
3660         }
3661
3662         return val;
3663 }
3664
3665 static noinline void gfar_update_link_state(struct gfar_private *priv)
3666 {
3667         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3668         struct phy_device *phydev = priv->phydev;
3669         struct gfar_priv_rx_q *rx_queue = NULL;
3670         int i;
3671
3672         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3673                 return;
3674
3675         if (phydev->link) {
3676                 u32 tempval1 = gfar_read(&regs->maccfg1);
3677                 u32 tempval = gfar_read(&regs->maccfg2);
3678                 u32 ecntrl = gfar_read(&regs->ecntrl);
3679                 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3680
3681                 if (phydev->duplex != priv->oldduplex) {
3682                         if (!(phydev->duplex))
3683                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3684                         else
3685                                 tempval |= MACCFG2_FULL_DUPLEX;
3686
3687                         priv->oldduplex = phydev->duplex;
3688                 }
3689
3690                 if (phydev->speed != priv->oldspeed) {
3691                         switch (phydev->speed) {
3692                         case 1000:
3693                                 tempval =
3694                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3695
3696                                 ecntrl &= ~(ECNTRL_R100);
3697                                 break;
3698                         case 100:
3699                         case 10:
3700                                 tempval =
3701                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3702
3703                                 /* Reduced mode distinguishes
3704                                  * between 10 and 100
3705                                  */
3706                                 if (phydev->speed == SPEED_100)
3707                                         ecntrl |= ECNTRL_R100;
3708                                 else
3709                                         ecntrl &= ~(ECNTRL_R100);
3710                                 break;
3711                         default:
3712                                 netif_warn(priv, link, priv->ndev,
3713                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3714                                            phydev->speed);
3715                                 break;
3716                         }
3717
3718                         priv->oldspeed = phydev->speed;
3719                 }
3720
3721                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3722                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3723
3724                 /* Turn last free buffer recording on */
3725                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3726                         for (i = 0; i < priv->num_rx_queues; i++) {
3727                                 u32 bdp_dma;
3728
3729                                 rx_queue = priv->rx_queue[i];
3730                                 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3731                                 gfar_write(rx_queue->rfbptr, bdp_dma);
3732                         }
3733
3734                         priv->tx_actual_en = 1;
3735                 }
3736
3737                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3738                         priv->tx_actual_en = 0;
3739
3740                 gfar_write(&regs->maccfg1, tempval1);
3741                 gfar_write(&regs->maccfg2, tempval);
3742                 gfar_write(&regs->ecntrl, ecntrl);
3743
3744                 if (!priv->oldlink)
3745                         priv->oldlink = 1;
3746
3747         } else if (priv->oldlink) {
3748                 priv->oldlink = 0;
3749                 priv->oldspeed = 0;
3750                 priv->oldduplex = -1;
3751         }
3752
3753         if (netif_msg_link(priv))
3754                 phy_print_status(phydev);
3755 }
3756
3757 static const struct of_device_id gfar_match[] =
3758 {
3759         {
3760                 .type = "network",
3761                 .compatible = "gianfar",
3762         },
3763         {
3764                 .compatible = "fsl,etsec2",
3765         },
3766         {},
3767 };
3768 MODULE_DEVICE_TABLE(of, gfar_match);
3769
3770 /* Structure for a device driver */
3771 static struct platform_driver gfar_driver = {
3772         .driver = {
3773                 .name = "fsl-gianfar",
3774                 .pm = GFAR_PM_OPS,
3775                 .of_match_table = gfar_match,
3776         },
3777         .probe = gfar_probe,
3778         .remove = gfar_remove,
3779 };
3780
3781 module_platform_driver(gfar_driver);