2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <net/addrconf.h>
66 #include <asm/uaccess.h>
70 #include "t4_values.h"
73 #include "t4fw_version.h"
74 #include "cxgb4_dcb.h"
75 #include "cxgb4_debugfs.h"
79 char cxgb4_driver_name[] = KBUILD_MODNAME;
84 #define DRV_VERSION "2.0.0-ko"
85 const char cxgb4_driver_version[] = DRV_VERSION;
86 #define DRV_DESC "Chelsio T4/T5 Network Driver"
88 /* Host shadow copy of ingress filter entry. This is in host native format
89 * and doesn't match the ordering or bit order, etc. of the hardware of the
90 * firmware command. The use of bit-field structure elements is purely to
91 * remind ourselves of the field size limitations and save memory in the case
92 * where the filter table is large.
95 /* Administrative fields for filter.
97 u32 valid:1; /* filter allocated and valid */
98 u32 locked:1; /* filter is administratively locked */
100 u32 pending:1; /* filter action is pending firmware reply */
101 u32 smtidx:8; /* Source MAC Table index for smac */
102 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
104 /* The filter itself. Most of this is a straight copy of information
105 * provided by the extended ioctl(). Some fields are translated to
106 * internal forms -- for instance the Ingress Queue ID passed in from
107 * the ioctl() is translated into the Absolute Ingress Queue ID.
109 struct ch_filter_specification fs;
112 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
113 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
114 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
116 /* Macros needed to support the PCI Device ID Table ...
118 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
119 static const struct pci_device_id cxgb4_pci_tbl[] = {
120 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
122 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
125 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
127 #define CH_PCI_ID_TABLE_ENTRY(devid) \
128 {PCI_VDEVICE(CHELSIO, (devid)), 4}
130 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
134 #include "t4_pci_id_tbl.h"
136 #define FW4_FNAME "cxgb4/t4fw.bin"
137 #define FW5_FNAME "cxgb4/t5fw.bin"
138 #define FW4_CFNAME "cxgb4/t4-config.txt"
139 #define FW5_CFNAME "cxgb4/t5-config.txt"
141 MODULE_DESCRIPTION(DRV_DESC);
142 MODULE_AUTHOR("Chelsio Communications");
143 MODULE_LICENSE("Dual BSD/GPL");
144 MODULE_VERSION(DRV_VERSION);
145 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
146 MODULE_FIRMWARE(FW4_FNAME);
147 MODULE_FIRMWARE(FW5_FNAME);
150 * Normally we're willing to become the firmware's Master PF but will be happy
151 * if another PF has already become the Master and initialized the adapter.
152 * Setting "force_init" will cause this driver to forcibly establish itself as
153 * the Master PF and initialize the adapter.
155 static uint force_init;
157 module_param(force_init, uint, 0644);
158 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
161 * Normally if the firmware we connect to has Configuration File support, we
162 * use that and only fall back to the old Driver-based initialization if the
163 * Configuration File fails for some reason. If force_old_init is set, then
164 * we'll always use the old Driver-based initialization sequence.
166 static uint force_old_init;
168 module_param(force_old_init, uint, 0644);
169 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence, deprecated"
172 static int dflt_msg_enable = DFLT_MSG_ENABLE;
174 module_param(dflt_msg_enable, int, 0644);
175 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
178 * The driver uses the best interrupt scheme available on a platform in the
179 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
180 * of these schemes the driver may consider as follows:
182 * msi = 2: choose from among all three options
183 * msi = 1: only consider MSI and INTx interrupts
184 * msi = 0: force INTx interrupts
188 module_param(msi, int, 0644);
189 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
192 * Queue interrupt hold-off timer values. Queues default to the first of these
195 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
197 module_param_array(intr_holdoff, uint, NULL, 0644);
198 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
199 "0..4 in microseconds, deprecated parameter");
201 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
203 module_param_array(intr_cnt, uint, NULL, 0644);
204 MODULE_PARM_DESC(intr_cnt,
205 "thresholds 1..3 for queue interrupt packet counters, "
206 "deprecated parameter");
209 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
210 * offset by 2 bytes in order to have the IP headers line up on 4-byte
211 * boundaries. This is a requirement for many architectures which will throw
212 * a machine check fault if an attempt is made to access one of the 4-byte IP
213 * header fields on a non-4-byte boundary. And it's a major performance issue
214 * even on some architectures which allow it like some implementations of the
215 * x86 ISA. However, some architectures don't mind this and for some very
216 * edge-case performance sensitive applications (like forwarding large volumes
217 * of small packets), setting this DMA offset to 0 will decrease the number of
218 * PCI-E Bus transfers enough to measurably affect performance.
220 static int rx_dma_offset = 2;
224 #ifdef CONFIG_PCI_IOV
225 module_param(vf_acls, bool, 0644);
226 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement, "
227 "deprecated parameter");
229 /* Configure the number of PCI-E Virtual Function which are to be instantiated
230 * on SR-IOV Capable Physical Functions.
232 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
234 module_param_array(num_vf, uint, NULL, 0644);
235 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
238 /* TX Queue select used to determine what algorithm to use for selecting TX
239 * queue. Select between the kernel provided function (select_queue=0) or user
240 * cxgb_select_queue function (select_queue=1)
242 * Default: select_queue=0
244 static int select_queue;
245 module_param(select_queue, int, 0644);
246 MODULE_PARM_DESC(select_queue,
247 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
249 static unsigned int tp_vlan_pri_map = HW_TPL_FR_MT_PR_IV_P_FC;
251 module_param(tp_vlan_pri_map, uint, 0644);
252 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration, "
253 "deprecated parameter");
255 static struct dentry *cxgb4_debugfs_root;
257 static LIST_HEAD(adapter_list);
258 static DEFINE_MUTEX(uld_mutex);
259 /* Adapter list to be accessed from atomic context */
260 static LIST_HEAD(adap_rcu_list);
261 static DEFINE_SPINLOCK(adap_rcu_lock);
262 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
263 static const char *uld_str[] = { "RDMA", "iSCSI" };
265 static void link_report(struct net_device *dev)
267 if (!netif_carrier_ok(dev))
268 netdev_info(dev, "link down\n");
270 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
272 const char *s = "10Mbps";
273 const struct port_info *p = netdev_priv(dev);
275 switch (p->link_cfg.speed) {
290 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
295 #ifdef CONFIG_CHELSIO_T4_DCB
296 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
297 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
299 struct port_info *pi = netdev_priv(dev);
300 struct adapter *adap = pi->adapter;
301 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
304 /* We use a simple mapping of Port TX Queue Index to DCB
305 * Priority when we're enabling DCB.
307 for (i = 0; i < pi->nqsets; i++, txq++) {
311 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
313 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
314 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
315 value = enable ? i : 0xffffffff;
317 /* Since we can be called while atomic (from "interrupt
318 * level") we need to issue the Set Parameters Commannd
319 * without sleeping (timeout < 0).
321 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
325 dev_err(adap->pdev_dev,
326 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
327 enable ? "set" : "unset", pi->port_id, i, -err);
329 txq->dcb_prio = value;
332 #endif /* CONFIG_CHELSIO_T4_DCB */
334 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
336 struct net_device *dev = adapter->port[port_id];
338 /* Skip changes from disabled ports. */
339 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
341 netif_carrier_on(dev);
343 #ifdef CONFIG_CHELSIO_T4_DCB
344 cxgb4_dcb_state_init(dev);
345 dcb_tx_queue_prio_enable(dev, false);
346 #endif /* CONFIG_CHELSIO_T4_DCB */
347 netif_carrier_off(dev);
354 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
356 static const char *mod_str[] = {
357 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
360 const struct net_device *dev = adap->port[port_id];
361 const struct port_info *pi = netdev_priv(dev);
363 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
364 netdev_info(dev, "port module unplugged\n");
365 else if (pi->mod_type < ARRAY_SIZE(mod_str))
366 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
370 * Configure the exact and hash address filters to handle a port's multicast
371 * and secondary unicast MAC addresses.
373 static int set_addr_filters(const struct net_device *dev, bool sleep)
381 const struct netdev_hw_addr *ha;
382 int uc_cnt = netdev_uc_count(dev);
383 int mc_cnt = netdev_mc_count(dev);
384 const struct port_info *pi = netdev_priv(dev);
385 unsigned int mb = pi->adapter->fn;
387 /* first do the secondary unicast addresses */
388 netdev_for_each_uc_addr(ha, dev) {
389 addr[naddr++] = ha->addr;
390 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
391 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
392 naddr, addr, filt_idx, &uhash, sleep);
401 /* next set up the multicast addresses */
402 netdev_for_each_mc_addr(ha, dev) {
403 addr[naddr++] = ha->addr;
404 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
405 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
406 naddr, addr, filt_idx, &mhash, sleep);
415 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
416 uhash | mhash, sleep);
419 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
420 module_param(dbfifo_int_thresh, int, 0644);
421 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
424 * usecs to sleep while draining the dbfifo
426 static int dbfifo_drain_delay = 1000;
427 module_param(dbfifo_drain_delay, int, 0644);
428 MODULE_PARM_DESC(dbfifo_drain_delay,
429 "usecs to sleep while draining the dbfifo");
432 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
433 * If @mtu is -1 it is left unchanged.
435 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
438 struct port_info *pi = netdev_priv(dev);
440 ret = set_addr_filters(dev, sleep_ok);
442 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
443 (dev->flags & IFF_PROMISC) ? 1 : 0,
444 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
450 * link_start - enable a port
451 * @dev: the port to enable
453 * Performs the MAC and PHY actions needed to enable a port.
455 static int link_start(struct net_device *dev)
458 struct port_info *pi = netdev_priv(dev);
459 unsigned int mb = pi->adapter->fn;
462 * We do not set address filters and promiscuity here, the stack does
463 * that step explicitly.
465 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
466 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
468 ret = t4_change_mac(pi->adapter, mb, pi->viid,
469 pi->xact_addr_filt, dev->dev_addr, true,
472 pi->xact_addr_filt = ret;
477 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
481 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
482 true, CXGB4_DCB_ENABLED);
489 int cxgb4_dcb_enabled(const struct net_device *dev)
491 #ifdef CONFIG_CHELSIO_T4_DCB
492 struct port_info *pi = netdev_priv(dev);
494 if (!pi->dcb.enabled)
497 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
498 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
503 EXPORT_SYMBOL(cxgb4_dcb_enabled);
505 #ifdef CONFIG_CHELSIO_T4_DCB
506 /* Handle a Data Center Bridging update message from the firmware. */
507 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
509 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
510 struct net_device *dev = adap->port[port];
511 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
514 cxgb4_dcb_handle_fw_update(adap, pcmd);
515 new_dcb_enabled = cxgb4_dcb_enabled(dev);
517 /* If the DCB has become enabled or disabled on the port then we're
518 * going to need to set up/tear down DCB Priority parameters for the
519 * TX Queues associated with the port.
521 if (new_dcb_enabled != old_dcb_enabled)
522 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
524 #endif /* CONFIG_CHELSIO_T4_DCB */
526 /* Clear a filter and release any of its resources that we own. This also
527 * clears the filter's "pending" status.
529 static void clear_filter(struct adapter *adap, struct filter_entry *f)
531 /* If the new or old filter have loopback rewriteing rules then we'll
532 * need to free any existing Layer Two Table (L2T) entries of the old
533 * filter rule. The firmware will handle freeing up any Source MAC
534 * Table (SMT) entries used for rewriting Source MAC Addresses in
538 cxgb4_l2t_release(f->l2t);
540 /* The zeroing of the filter rule below clears the filter valid,
541 * pending, locked flags, l2t pointer, etc. so it's all we need for
544 memset(f, 0, sizeof(*f));
547 /* Handle a filter write/deletion reply.
549 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
551 unsigned int idx = GET_TID(rpl);
552 unsigned int nidx = idx - adap->tids.ftid_base;
554 struct filter_entry *f;
556 if (idx >= adap->tids.ftid_base && nidx <
557 (adap->tids.nftids + adap->tids.nsftids)) {
559 ret = TCB_COOKIE_G(rpl->cookie);
560 f = &adap->tids.ftid_tab[idx];
562 if (ret == FW_FILTER_WR_FLT_DELETED) {
563 /* Clear the filter when we get confirmation from the
564 * hardware that the filter has been deleted.
566 clear_filter(adap, f);
567 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
568 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
570 clear_filter(adap, f);
571 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
572 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
573 f->pending = 0; /* asynchronous setup completed */
576 /* Something went wrong. Issue a warning about the
577 * problem and clear everything out.
579 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
581 clear_filter(adap, f);
586 /* Response queue handler for the FW event queue.
588 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
589 const struct pkt_gl *gl)
591 u8 opcode = ((const struct rss_header *)rsp)->opcode;
593 rsp++; /* skip RSS header */
595 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
597 if (unlikely(opcode == CPL_FW4_MSG &&
598 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
600 opcode = ((const struct rss_header *)rsp)->opcode;
602 if (opcode != CPL_SGE_EGR_UPDATE) {
603 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
609 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
610 const struct cpl_sge_egr_update *p = (void *)rsp;
611 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
614 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
616 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
617 struct sge_eth_txq *eq;
619 eq = container_of(txq, struct sge_eth_txq, q);
620 netif_tx_wake_queue(eq->txq);
622 struct sge_ofld_txq *oq;
624 oq = container_of(txq, struct sge_ofld_txq, q);
625 tasklet_schedule(&oq->qresume_tsk);
627 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
628 const struct cpl_fw6_msg *p = (void *)rsp;
630 #ifdef CONFIG_CHELSIO_T4_DCB
631 const struct fw_port_cmd *pcmd = (const void *)p->data;
632 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
633 unsigned int action =
634 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
636 if (cmd == FW_PORT_CMD &&
637 action == FW_PORT_ACTION_GET_PORT_INFO) {
638 int port = FW_PORT_CMD_PORTID_G(
639 be32_to_cpu(pcmd->op_to_portid));
640 struct net_device *dev = q->adap->port[port];
641 int state_input = ((pcmd->u.info.dcbxdis_pkd &
642 FW_PORT_CMD_DCBXDIS_F)
643 ? CXGB4_DCB_INPUT_FW_DISABLED
644 : CXGB4_DCB_INPUT_FW_ENABLED);
646 cxgb4_dcb_state_fsm(dev, state_input);
649 if (cmd == FW_PORT_CMD &&
650 action == FW_PORT_ACTION_L2_DCB_CFG)
651 dcb_rpl(q->adap, pcmd);
655 t4_handle_fw_rpl(q->adap, p->data);
656 } else if (opcode == CPL_L2T_WRITE_RPL) {
657 const struct cpl_l2t_write_rpl *p = (void *)rsp;
659 do_l2t_write_rpl(q->adap, p);
660 } else if (opcode == CPL_SET_TCB_RPL) {
661 const struct cpl_set_tcb_rpl *p = (void *)rsp;
663 filter_rpl(q->adap, p);
665 dev_err(q->adap->pdev_dev,
666 "unexpected CPL %#x on FW event queue\n", opcode);
672 * uldrx_handler - response queue handler for ULD queues
673 * @q: the response queue that received the packet
674 * @rsp: the response queue descriptor holding the offload message
675 * @gl: the gather list of packet fragments
677 * Deliver an ingress offload packet to a ULD. All processing is done by
678 * the ULD, we just maintain statistics.
680 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
681 const struct pkt_gl *gl)
683 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
685 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
687 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
688 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
691 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
697 else if (gl == CXGB4_MSG_AN)
704 static void disable_msi(struct adapter *adapter)
706 if (adapter->flags & USING_MSIX) {
707 pci_disable_msix(adapter->pdev);
708 adapter->flags &= ~USING_MSIX;
709 } else if (adapter->flags & USING_MSI) {
710 pci_disable_msi(adapter->pdev);
711 adapter->flags &= ~USING_MSI;
716 * Interrupt handler for non-data events used with MSI-X.
718 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
720 struct adapter *adap = cookie;
721 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
725 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
727 if (adap->flags & MASTER_PF)
728 t4_slow_intr_handler(adap);
733 * Name the MSI-X interrupts.
735 static void name_msix_vecs(struct adapter *adap)
737 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
739 /* non-data interrupts */
740 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
743 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
744 adap->port[0]->name);
746 /* Ethernet queues */
747 for_each_port(adap, j) {
748 struct net_device *d = adap->port[j];
749 const struct port_info *pi = netdev_priv(d);
751 for (i = 0; i < pi->nqsets; i++, msi_idx++)
752 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
757 for_each_ofldrxq(&adap->sge, i)
758 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
759 adap->port[0]->name, i);
761 for_each_rdmarxq(&adap->sge, i)
762 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
763 adap->port[0]->name, i);
765 for_each_rdmaciq(&adap->sge, i)
766 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
767 adap->port[0]->name, i);
770 static int request_msix_queue_irqs(struct adapter *adap)
772 struct sge *s = &adap->sge;
773 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
776 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
777 adap->msix_info[1].desc, &s->fw_evtq);
781 for_each_ethrxq(s, ethqidx) {
782 err = request_irq(adap->msix_info[msi_index].vec,
784 adap->msix_info[msi_index].desc,
785 &s->ethrxq[ethqidx].rspq);
790 for_each_ofldrxq(s, ofldqidx) {
791 err = request_irq(adap->msix_info[msi_index].vec,
793 adap->msix_info[msi_index].desc,
794 &s->ofldrxq[ofldqidx].rspq);
799 for_each_rdmarxq(s, rdmaqidx) {
800 err = request_irq(adap->msix_info[msi_index].vec,
802 adap->msix_info[msi_index].desc,
803 &s->rdmarxq[rdmaqidx].rspq);
808 for_each_rdmaciq(s, rdmaciqqidx) {
809 err = request_irq(adap->msix_info[msi_index].vec,
811 adap->msix_info[msi_index].desc,
812 &s->rdmaciq[rdmaciqqidx].rspq);
820 while (--rdmaciqqidx >= 0)
821 free_irq(adap->msix_info[--msi_index].vec,
822 &s->rdmaciq[rdmaciqqidx].rspq);
823 while (--rdmaqidx >= 0)
824 free_irq(adap->msix_info[--msi_index].vec,
825 &s->rdmarxq[rdmaqidx].rspq);
826 while (--ofldqidx >= 0)
827 free_irq(adap->msix_info[--msi_index].vec,
828 &s->ofldrxq[ofldqidx].rspq);
829 while (--ethqidx >= 0)
830 free_irq(adap->msix_info[--msi_index].vec,
831 &s->ethrxq[ethqidx].rspq);
832 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
836 static void free_msix_queue_irqs(struct adapter *adap)
838 int i, msi_index = 2;
839 struct sge *s = &adap->sge;
841 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
842 for_each_ethrxq(s, i)
843 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
844 for_each_ofldrxq(s, i)
845 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
846 for_each_rdmarxq(s, i)
847 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
848 for_each_rdmaciq(s, i)
849 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
853 * cxgb4_write_rss - write the RSS table for a given port
855 * @queues: array of queue indices for RSS
857 * Sets up the portion of the HW RSS table for the port's VI to distribute
858 * packets to the Rx queues in @queues.
860 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
864 const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
866 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
870 /* map the queue indices to queue ids */
871 for (i = 0; i < pi->rss_size; i++, queues++)
872 rss[i] = q[*queues].rspq.abs_id;
874 err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
875 pi->rss_size, rss, pi->rss_size);
881 * setup_rss - configure RSS
884 * Sets up RSS for each port.
886 static int setup_rss(struct adapter *adap)
890 for_each_port(adap, i) {
891 const struct port_info *pi = adap2pinfo(adap, i);
893 err = cxgb4_write_rss(pi, pi->rss);
901 * Return the channel of the ingress queue with the given qid.
903 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
905 qid -= p->ingr_start;
906 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
910 * Wait until all NAPI handlers are descheduled.
912 static void quiesce_rx(struct adapter *adap)
916 for (i = 0; i < adap->sge.ingr_sz; i++) {
917 struct sge_rspq *q = adap->sge.ingr_map[i];
919 if (q && q->handler) {
920 napi_disable(&q->napi);
922 while (!cxgb_poll_lock_napi(q))
930 /* Disable interrupt and napi handler */
931 static void disable_interrupts(struct adapter *adap)
933 if (adap->flags & FULL_INIT_DONE) {
934 t4_intr_disable(adap);
935 if (adap->flags & USING_MSIX) {
936 free_msix_queue_irqs(adap);
937 free_irq(adap->msix_info[0].vec, adap);
939 free_irq(adap->pdev->irq, adap);
946 * Enable NAPI scheduling and interrupt generation for all Rx queues.
948 static void enable_rx(struct adapter *adap)
952 for (i = 0; i < adap->sge.ingr_sz; i++) {
953 struct sge_rspq *q = adap->sge.ingr_map[i];
958 cxgb_busy_poll_init_lock(q);
959 napi_enable(&q->napi);
961 /* 0-increment GTS to start the timer and enable interrupts */
962 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
963 SEINTARM_V(q->intr_params) |
964 INGRESSQID_V(q->cntxt_id));
968 static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q,
969 unsigned int nq, unsigned int per_chan, int msi_idx,
974 for (i = 0; i < nq; i++, q++) {
977 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
978 adap->port[i / per_chan],
979 msi_idx, q->fl.size ? &q->fl : NULL,
983 memset(&q->stats, 0, sizeof(q->stats));
985 ids[i] = q->rspq.abs_id;
991 * setup_sge_queues - configure SGE Tx/Rx/response queues
994 * Determines how many sets of SGE queues to use and initializes them.
995 * We support multiple queue sets per port if we have MSI-X, otherwise
996 * just one queue set per port.
998 static int setup_sge_queues(struct adapter *adap)
1000 int err, msi_idx, i, j;
1001 struct sge *s = &adap->sge;
1003 bitmap_zero(s->starving_fl, s->egr_sz);
1004 bitmap_zero(s->txq_maperr, s->egr_sz);
1006 if (adap->flags & USING_MSIX)
1007 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1009 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1013 msi_idx = -((int)s->intrq.abs_id + 1);
1016 /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here,
1017 * don't forget to update the following which need to be
1018 * synchronized to and changes here.
1020 * 1. The calculations of MAX_INGQ in cxgb4.h.
1022 * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs
1023 * to accommodate any new/deleted Ingress Queues
1024 * which need MSI-X Vectors.
1026 * 3. Update sge_qinfo_show() to include information on the
1027 * new/deleted queues.
1029 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1030 msi_idx, NULL, fwevtq_handler);
1032 freeout: t4_free_sge_resources(adap);
1036 for_each_port(adap, i) {
1037 struct net_device *dev = adap->port[i];
1038 struct port_info *pi = netdev_priv(dev);
1039 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1040 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1042 for (j = 0; j < pi->nqsets; j++, q++) {
1045 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1051 memset(&q->stats, 0, sizeof(q->stats));
1053 for (j = 0; j < pi->nqsets; j++, t++) {
1054 err = t4_sge_alloc_eth_txq(adap, t, dev,
1055 netdev_get_tx_queue(dev, j),
1056 s->fw_evtq.cntxt_id);
1062 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1063 for_each_ofldrxq(s, i) {
1064 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i],
1066 s->fw_evtq.cntxt_id);
1071 #define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids) do { \
1072 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids); \
1079 ALLOC_OFLD_RXQS(s->ofldrxq, s->ofldqsets, j, s->ofld_rxq);
1080 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq);
1081 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */
1082 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq);
1084 #undef ALLOC_OFLD_RXQS
1086 for_each_port(adap, i) {
1088 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1089 * have RDMA queues, and that's the right value.
1091 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1092 s->fw_evtq.cntxt_id,
1093 s->rdmarxq[i].rspq.cntxt_id);
1098 t4_write_reg(adap, is_t4(adap->params.chip) ?
1099 MPS_TRC_RSS_CONTROL_A :
1100 MPS_T5_TRC_RSS_CONTROL_A,
1101 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1102 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1107 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1108 * The allocated memory is cleared.
1110 void *t4_alloc_mem(size_t size)
1112 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1120 * Free memory allocated through alloc_mem().
1122 void t4_free_mem(void *addr)
1124 if (is_vmalloc_addr(addr))
1130 /* Send a Work Request to write the filter at a specified index. We construct
1131 * a Firmware Filter Work Request to have the work done and put the indicated
1132 * filter into "pending" mode which will prevent any further actions against
1133 * it till we get a reply from the firmware on the completion status of the
1136 static int set_filter_wr(struct adapter *adapter, int fidx)
1138 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1139 struct sk_buff *skb;
1140 struct fw_filter_wr *fwr;
1143 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL);
1147 /* If the new filter requires loopback Destination MAC and/or VLAN
1148 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1151 if (f->fs.newdmac || f->fs.newvlan) {
1152 /* allocate L2T entry for new filter */
1153 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1154 if (f->l2t == NULL) {
1158 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1159 f->fs.eport, f->fs.dmac)) {
1160 cxgb4_l2t_release(f->l2t);
1167 ftid = adapter->tids.ftid_base + fidx;
1169 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1170 memset(fwr, 0, sizeof(*fwr));
1172 /* It would be nice to put most of the following in t4_hw.c but most
1173 * of the work is translating the cxgbtool ch_filter_specification
1174 * into the Work Request and the definition of that structure is
1175 * currently in cxgbtool.h which isn't appropriate to pull into the
1176 * common code. We may eventually try to come up with a more neutral
1177 * filter specification structure but for now it's easiest to simply
1178 * put this fairly direct code in line ...
1180 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1181 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
1183 htonl(FW_FILTER_WR_TID_V(ftid) |
1184 FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1185 FW_FILTER_WR_NOREPLY_V(0) |
1186 FW_FILTER_WR_IQ_V(f->fs.iq));
1187 fwr->del_filter_to_l2tix =
1188 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1189 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1190 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1191 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1192 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1193 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1194 FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1195 FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1196 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
1197 f->fs.newvlan == VLAN_REWRITE) |
1198 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
1199 f->fs.newvlan == VLAN_REWRITE) |
1200 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1201 FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1202 FW_FILTER_WR_PRIO_V(f->fs.prio) |
1203 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
1204 fwr->ethtype = htons(f->fs.val.ethtype);
1205 fwr->ethtypem = htons(f->fs.mask.ethtype);
1206 fwr->frag_to_ovlan_vldm =
1207 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1208 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1209 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1210 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1211 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1212 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
1214 fwr->rx_chan_rx_rpl_iq =
1215 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1216 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
1217 fwr->maci_to_matchtypem =
1218 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1219 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1220 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1221 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1222 FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1223 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1224 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1225 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
1226 fwr->ptcl = f->fs.val.proto;
1227 fwr->ptclm = f->fs.mask.proto;
1228 fwr->ttyp = f->fs.val.tos;
1229 fwr->ttypm = f->fs.mask.tos;
1230 fwr->ivlan = htons(f->fs.val.ivlan);
1231 fwr->ivlanm = htons(f->fs.mask.ivlan);
1232 fwr->ovlan = htons(f->fs.val.ovlan);
1233 fwr->ovlanm = htons(f->fs.mask.ovlan);
1234 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1235 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1236 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1237 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1238 fwr->lp = htons(f->fs.val.lport);
1239 fwr->lpm = htons(f->fs.mask.lport);
1240 fwr->fp = htons(f->fs.val.fport);
1241 fwr->fpm = htons(f->fs.mask.fport);
1243 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1245 /* Mark the filter as "pending" and ship off the Filter Work Request.
1246 * When we get the Work Request Reply we'll clear the pending status.
1249 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1250 t4_ofld_send(adapter, skb);
1254 /* Delete the filter at a specified index.
1256 static int del_filter_wr(struct adapter *adapter, int fidx)
1258 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1259 struct sk_buff *skb;
1260 struct fw_filter_wr *fwr;
1261 unsigned int len, ftid;
1264 ftid = adapter->tids.ftid_base + fidx;
1266 skb = alloc_skb(len, GFP_KERNEL);
1270 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1271 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1273 /* Mark the filter as "pending" and ship off the Filter Work Request.
1274 * When we get the Work Request Reply we'll clear the pending status.
1277 t4_mgmt_tx(adapter, skb);
1281 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1282 void *accel_priv, select_queue_fallback_t fallback)
1286 #ifdef CONFIG_CHELSIO_T4_DCB
1287 /* If a Data Center Bridging has been successfully negotiated on this
1288 * link then we'll use the skb's priority to map it to a TX Queue.
1289 * The skb's priority is determined via the VLAN Tag Priority Code
1292 if (cxgb4_dcb_enabled(dev)) {
1296 err = vlan_get_tag(skb, &vlan_tci);
1297 if (unlikely(err)) {
1298 if (net_ratelimit())
1300 "TX Packet without VLAN Tag on DCB Link\n");
1303 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1304 #ifdef CONFIG_CHELSIO_T4_FCOE
1305 if (skb->protocol == htons(ETH_P_FCOE))
1306 txq = skb->priority & 0x7;
1307 #endif /* CONFIG_CHELSIO_T4_FCOE */
1311 #endif /* CONFIG_CHELSIO_T4_DCB */
1314 txq = (skb_rx_queue_recorded(skb)
1315 ? skb_get_rx_queue(skb)
1316 : smp_processor_id());
1318 while (unlikely(txq >= dev->real_num_tx_queues))
1319 txq -= dev->real_num_tx_queues;
1324 return fallback(dev, skb) % dev->real_num_tx_queues;
1327 static inline int is_offload(const struct adapter *adap)
1329 return adap->params.offload;
1332 static int closest_timer(const struct sge *s, int time)
1334 int i, delta, match = 0, min_delta = INT_MAX;
1336 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1337 delta = time - s->timer_val[i];
1340 if (delta < min_delta) {
1348 static int closest_thres(const struct sge *s, int thres)
1350 int i, delta, match = 0, min_delta = INT_MAX;
1352 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1353 delta = thres - s->counter_val[i];
1356 if (delta < min_delta) {
1365 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1367 * @us: the hold-off time in us, or 0 to disable timer
1368 * @cnt: the hold-off packet count, or 0 to disable counter
1370 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1371 * one of the two needs to be enabled for the queue to generate interrupts.
1373 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1374 unsigned int us, unsigned int cnt)
1376 struct adapter *adap = q->adap;
1378 if ((us | cnt) == 0)
1385 new_idx = closest_thres(&adap->sge, cnt);
1386 if (q->desc && q->pktcnt_idx != new_idx) {
1387 /* the queue has already been created, update it */
1388 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1389 FW_PARAMS_PARAM_X_V(
1390 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1391 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1392 err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
1397 q->pktcnt_idx = new_idx;
1400 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1401 q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
1405 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1407 const struct port_info *pi = netdev_priv(dev);
1408 netdev_features_t changed = dev->features ^ features;
1411 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1414 err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
1416 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1418 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1422 static int setup_debugfs(struct adapter *adap)
1424 if (IS_ERR_OR_NULL(adap->debugfs_root))
1427 #ifdef CONFIG_DEBUG_FS
1428 t4_setup_debugfs(adap);
1434 * upper-layer driver support
1438 * Allocate an active-open TID and set it to the supplied value.
1440 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1444 spin_lock_bh(&t->atid_lock);
1446 union aopen_entry *p = t->afree;
1448 atid = (p - t->atid_tab) + t->atid_base;
1453 spin_unlock_bh(&t->atid_lock);
1456 EXPORT_SYMBOL(cxgb4_alloc_atid);
1459 * Release an active-open TID.
1461 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1463 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1465 spin_lock_bh(&t->atid_lock);
1469 spin_unlock_bh(&t->atid_lock);
1471 EXPORT_SYMBOL(cxgb4_free_atid);
1474 * Allocate a server TID and set it to the supplied value.
1476 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1480 spin_lock_bh(&t->stid_lock);
1481 if (family == PF_INET) {
1482 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1483 if (stid < t->nstids)
1484 __set_bit(stid, t->stid_bmap);
1488 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
1493 t->stid_tab[stid].data = data;
1494 stid += t->stid_base;
1495 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1496 * This is equivalent to 4 TIDs. With CLIP enabled it
1499 if (family == PF_INET)
1502 t->stids_in_use += 4;
1504 spin_unlock_bh(&t->stid_lock);
1507 EXPORT_SYMBOL(cxgb4_alloc_stid);
1509 /* Allocate a server filter TID and set it to the supplied value.
1511 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1515 spin_lock_bh(&t->stid_lock);
1516 if (family == PF_INET) {
1517 stid = find_next_zero_bit(t->stid_bmap,
1518 t->nstids + t->nsftids, t->nstids);
1519 if (stid < (t->nstids + t->nsftids))
1520 __set_bit(stid, t->stid_bmap);
1527 t->stid_tab[stid].data = data;
1529 stid += t->sftid_base;
1532 spin_unlock_bh(&t->stid_lock);
1535 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1537 /* Release a server TID.
1539 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1541 /* Is it a server filter TID? */
1542 if (t->nsftids && (stid >= t->sftid_base)) {
1543 stid -= t->sftid_base;
1546 stid -= t->stid_base;
1549 spin_lock_bh(&t->stid_lock);
1550 if (family == PF_INET)
1551 __clear_bit(stid, t->stid_bmap);
1553 bitmap_release_region(t->stid_bmap, stid, 2);
1554 t->stid_tab[stid].data = NULL;
1555 if (family == PF_INET)
1558 t->stids_in_use -= 4;
1559 spin_unlock_bh(&t->stid_lock);
1561 EXPORT_SYMBOL(cxgb4_free_stid);
1564 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1566 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1569 struct cpl_tid_release *req;
1571 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1572 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1573 INIT_TP_WR(req, tid);
1574 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1578 * Queue a TID release request and if necessary schedule a work queue to
1581 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1584 void **p = &t->tid_tab[tid];
1585 struct adapter *adap = container_of(t, struct adapter, tids);
1587 spin_lock_bh(&adap->tid_release_lock);
1588 *p = adap->tid_release_head;
1589 /* Low 2 bits encode the Tx channel number */
1590 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1591 if (!adap->tid_release_task_busy) {
1592 adap->tid_release_task_busy = true;
1593 queue_work(adap->workq, &adap->tid_release_task);
1595 spin_unlock_bh(&adap->tid_release_lock);
1599 * Process the list of pending TID release requests.
1601 static void process_tid_release_list(struct work_struct *work)
1603 struct sk_buff *skb;
1604 struct adapter *adap;
1606 adap = container_of(work, struct adapter, tid_release_task);
1608 spin_lock_bh(&adap->tid_release_lock);
1609 while (adap->tid_release_head) {
1610 void **p = adap->tid_release_head;
1611 unsigned int chan = (uintptr_t)p & 3;
1612 p = (void *)p - chan;
1614 adap->tid_release_head = *p;
1616 spin_unlock_bh(&adap->tid_release_lock);
1618 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1620 schedule_timeout_uninterruptible(1);
1622 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1623 t4_ofld_send(adap, skb);
1624 spin_lock_bh(&adap->tid_release_lock);
1626 adap->tid_release_task_busy = false;
1627 spin_unlock_bh(&adap->tid_release_lock);
1631 * Release a TID and inform HW. If we are unable to allocate the release
1632 * message we defer to a work queue.
1634 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
1637 struct sk_buff *skb;
1638 struct adapter *adap = container_of(t, struct adapter, tids);
1640 old = t->tid_tab[tid];
1641 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1643 t->tid_tab[tid] = NULL;
1644 mk_tid_release(skb, chan, tid);
1645 t4_ofld_send(adap, skb);
1647 cxgb4_queue_tid_release(t, chan, tid);
1649 atomic_dec(&t->tids_in_use);
1651 EXPORT_SYMBOL(cxgb4_remove_tid);
1654 * Allocate and initialize the TID tables. Returns 0 on success.
1656 static int tid_init(struct tid_info *t)
1659 unsigned int stid_bmap_size;
1660 unsigned int natids = t->natids;
1661 struct adapter *adap = container_of(t, struct adapter, tids);
1663 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1664 size = t->ntids * sizeof(*t->tid_tab) +
1665 natids * sizeof(*t->atid_tab) +
1666 t->nstids * sizeof(*t->stid_tab) +
1667 t->nsftids * sizeof(*t->stid_tab) +
1668 stid_bmap_size * sizeof(long) +
1669 t->nftids * sizeof(*t->ftid_tab) +
1670 t->nsftids * sizeof(*t->ftid_tab);
1672 t->tid_tab = t4_alloc_mem(size);
1676 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1677 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1678 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1679 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1680 spin_lock_init(&t->stid_lock);
1681 spin_lock_init(&t->atid_lock);
1683 t->stids_in_use = 0;
1685 t->atids_in_use = 0;
1686 atomic_set(&t->tids_in_use, 0);
1688 /* Setup the free list for atid_tab and clear the stid bitmap. */
1691 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1692 t->afree = t->atid_tab;
1694 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1695 /* Reserve stid 0 for T4/T5 adapters */
1696 if (!t->stid_base &&
1697 (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
1698 __set_bit(0, t->stid_bmap);
1704 * cxgb4_create_server - create an IP server
1706 * @stid: the server TID
1707 * @sip: local IP address to bind server to
1708 * @sport: the server's TCP port
1709 * @queue: queue to direct messages from this server to
1711 * Create an IP server for the given port and address.
1712 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1714 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1715 __be32 sip, __be16 sport, __be16 vlan,
1719 struct sk_buff *skb;
1720 struct adapter *adap;
1721 struct cpl_pass_open_req *req;
1724 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1728 adap = netdev2adap(dev);
1729 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
1731 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1732 req->local_port = sport;
1733 req->peer_port = htons(0);
1734 req->local_ip = sip;
1735 req->peer_ip = htonl(0);
1736 chan = rxq_to_chan(&adap->sge, queue);
1737 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1738 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1739 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1740 ret = t4_mgmt_tx(adap, skb);
1741 return net_xmit_eval(ret);
1743 EXPORT_SYMBOL(cxgb4_create_server);
1745 /* cxgb4_create_server6 - create an IPv6 server
1747 * @stid: the server TID
1748 * @sip: local IPv6 address to bind server to
1749 * @sport: the server's TCP port
1750 * @queue: queue to direct messages from this server to
1752 * Create an IPv6 server for the given port and address.
1753 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1755 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1756 const struct in6_addr *sip, __be16 sport,
1760 struct sk_buff *skb;
1761 struct adapter *adap;
1762 struct cpl_pass_open_req6 *req;
1765 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1769 adap = netdev2adap(dev);
1770 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
1772 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1773 req->local_port = sport;
1774 req->peer_port = htons(0);
1775 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1776 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1777 req->peer_ip_hi = cpu_to_be64(0);
1778 req->peer_ip_lo = cpu_to_be64(0);
1779 chan = rxq_to_chan(&adap->sge, queue);
1780 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1781 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1782 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1783 ret = t4_mgmt_tx(adap, skb);
1784 return net_xmit_eval(ret);
1786 EXPORT_SYMBOL(cxgb4_create_server6);
1788 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1789 unsigned int queue, bool ipv6)
1791 struct sk_buff *skb;
1792 struct adapter *adap;
1793 struct cpl_close_listsvr_req *req;
1796 adap = netdev2adap(dev);
1798 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1802 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
1804 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1805 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1806 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1807 ret = t4_mgmt_tx(adap, skb);
1808 return net_xmit_eval(ret);
1810 EXPORT_SYMBOL(cxgb4_remove_server);
1813 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1814 * @mtus: the HW MTU table
1815 * @mtu: the target MTU
1816 * @idx: index of selected entry in the MTU table
1818 * Returns the index and the value in the HW MTU table that is closest to
1819 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1820 * table, in which case that smallest available value is selected.
1822 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1827 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1833 EXPORT_SYMBOL(cxgb4_best_mtu);
1836 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1837 * @mtus: the HW MTU table
1838 * @header_size: Header Size
1839 * @data_size_max: maximum Data Segment Size
1840 * @data_size_align: desired Data Segment Size Alignment (2^N)
1841 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1843 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1844 * MTU Table based solely on a Maximum MTU parameter, we break that
1845 * parameter up into a Header Size and Maximum Data Segment Size, and
1846 * provide a desired Data Segment Size Alignment. If we find an MTU in
1847 * the Hardware MTU Table which will result in a Data Segment Size with
1848 * the requested alignment _and_ that MTU isn't "too far" from the
1849 * closest MTU, then we'll return that rather than the closest MTU.
1851 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1852 unsigned short header_size,
1853 unsigned short data_size_max,
1854 unsigned short data_size_align,
1855 unsigned int *mtu_idxp)
1857 unsigned short max_mtu = header_size + data_size_max;
1858 unsigned short data_size_align_mask = data_size_align - 1;
1859 int mtu_idx, aligned_mtu_idx;
1861 /* Scan the MTU Table till we find an MTU which is larger than our
1862 * Maximum MTU or we reach the end of the table. Along the way,
1863 * record the last MTU found, if any, which will result in a Data
1864 * Segment Length matching the requested alignment.
1866 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1867 unsigned short data_size = mtus[mtu_idx] - header_size;
1869 /* If this MTU minus the Header Size would result in a
1870 * Data Segment Size of the desired alignment, remember it.
1872 if ((data_size & data_size_align_mask) == 0)
1873 aligned_mtu_idx = mtu_idx;
1875 /* If we're not at the end of the Hardware MTU Table and the
1876 * next element is larger than our Maximum MTU, drop out of
1879 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1883 /* If we fell out of the loop because we ran to the end of the table,
1884 * then we just have to use the last [largest] entry.
1886 if (mtu_idx == NMTUS)
1889 /* If we found an MTU which resulted in the requested Data Segment
1890 * Length alignment and that's "not far" from the largest MTU which is
1891 * less than or equal to the maximum MTU, then use that.
1893 if (aligned_mtu_idx >= 0 &&
1894 mtu_idx - aligned_mtu_idx <= 1)
1895 mtu_idx = aligned_mtu_idx;
1897 /* If the caller has passed in an MTU Index pointer, pass the
1898 * MTU Index back. Return the MTU value.
1901 *mtu_idxp = mtu_idx;
1902 return mtus[mtu_idx];
1904 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1907 * cxgb4_port_chan - get the HW channel of a port
1908 * @dev: the net device for the port
1910 * Return the HW Tx channel of the given port.
1912 unsigned int cxgb4_port_chan(const struct net_device *dev)
1914 return netdev2pinfo(dev)->tx_chan;
1916 EXPORT_SYMBOL(cxgb4_port_chan);
1918 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1920 struct adapter *adap = netdev2adap(dev);
1921 u32 v1, v2, lp_count, hp_count;
1923 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1924 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1925 if (is_t4(adap->params.chip)) {
1926 lp_count = LP_COUNT_G(v1);
1927 hp_count = HP_COUNT_G(v1);
1929 lp_count = LP_COUNT_T5_G(v1);
1930 hp_count = HP_COUNT_T5_G(v2);
1932 return lpfifo ? lp_count : hp_count;
1934 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1937 * cxgb4_port_viid - get the VI id of a port
1938 * @dev: the net device for the port
1940 * Return the VI id of the given port.
1942 unsigned int cxgb4_port_viid(const struct net_device *dev)
1944 return netdev2pinfo(dev)->viid;
1946 EXPORT_SYMBOL(cxgb4_port_viid);
1949 * cxgb4_port_idx - get the index of a port
1950 * @dev: the net device for the port
1952 * Return the index of the given port.
1954 unsigned int cxgb4_port_idx(const struct net_device *dev)
1956 return netdev2pinfo(dev)->port_id;
1958 EXPORT_SYMBOL(cxgb4_port_idx);
1960 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1961 struct tp_tcp_stats *v6)
1963 struct adapter *adap = pci_get_drvdata(pdev);
1965 spin_lock(&adap->stats_lock);
1966 t4_tp_get_tcp_stats(adap, v4, v6);
1967 spin_unlock(&adap->stats_lock);
1969 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1971 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1972 const unsigned int *pgsz_order)
1974 struct adapter *adap = netdev2adap(dev);
1976 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1977 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1978 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1979 HPZ3_V(pgsz_order[3]));
1981 EXPORT_SYMBOL(cxgb4_iscsi_init);
1983 int cxgb4_flush_eq_cache(struct net_device *dev)
1985 struct adapter *adap = netdev2adap(dev);
1988 ret = t4_fwaddrspace_write(adap, adap->mbox,
1989 0xe1000000 + SGE_CTXT_CMD_A, 0x20000000);
1992 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1994 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1996 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
2000 spin_lock(&adap->win0_lock);
2001 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
2002 sizeof(indices), (__be32 *)&indices,
2004 spin_unlock(&adap->win0_lock);
2006 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
2007 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
2012 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
2015 struct adapter *adap = netdev2adap(dev);
2016 u16 hw_pidx, hw_cidx;
2019 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
2023 if (pidx != hw_pidx) {
2027 if (pidx >= hw_pidx)
2028 delta = pidx - hw_pidx;
2030 delta = size - hw_pidx + pidx;
2032 if (is_t4(adap->params.chip))
2033 val = PIDX_V(delta);
2035 val = PIDX_T5_V(delta);
2037 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2043 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
2045 void cxgb4_disable_db_coalescing(struct net_device *dev)
2047 struct adapter *adap;
2049 adap = netdev2adap(dev);
2050 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F,
2053 EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
2055 void cxgb4_enable_db_coalescing(struct net_device *dev)
2057 struct adapter *adap;
2059 adap = netdev2adap(dev);
2060 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F, 0);
2062 EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
2064 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2066 struct adapter *adap;
2067 u32 offset, memtype, memaddr;
2068 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
2069 u32 edc0_end, edc1_end, mc0_end, mc1_end;
2072 adap = netdev2adap(dev);
2074 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
2076 /* Figure out where the offset lands in the Memory Type/Address scheme.
2077 * This code assumes that the memory is laid out starting at offset 0
2078 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
2079 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
2080 * MC0, and some have both MC0 and MC1.
2082 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
2083 edc0_size = EDRAM0_SIZE_G(size) << 20;
2084 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2085 edc1_size = EDRAM1_SIZE_G(size) << 20;
2086 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2087 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
2089 edc0_end = edc0_size;
2090 edc1_end = edc0_end + edc1_size;
2091 mc0_end = edc1_end + mc0_size;
2093 if (offset < edc0_end) {
2096 } else if (offset < edc1_end) {
2098 memaddr = offset - edc0_end;
2100 if (offset < mc0_end) {
2102 memaddr = offset - edc1_end;
2103 } else if (is_t4(adap->params.chip)) {
2104 /* T4 only has a single memory channel */
2107 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2108 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
2109 mc1_end = mc0_end + mc1_size;
2110 if (offset < mc1_end) {
2112 memaddr = offset - mc0_end;
2114 /* offset beyond the end of any memory */
2120 spin_lock(&adap->win0_lock);
2121 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2122 spin_unlock(&adap->win0_lock);
2126 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2130 EXPORT_SYMBOL(cxgb4_read_tpte);
2132 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2135 struct adapter *adap;
2137 adap = netdev2adap(dev);
2138 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2139 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
2141 return ((u64)hi << 32) | (u64)lo;
2143 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2145 int cxgb4_bar2_sge_qregs(struct net_device *dev,
2147 enum cxgb4_bar2_qtype qtype,
2149 unsigned int *pbar2_qid)
2151 return cxgb4_t4_bar2_sge_qregs(netdev2adap(dev),
2153 (qtype == CXGB4_BAR2_QTYPE_EGRESS
2154 ? T4_BAR2_QTYPE_EGRESS
2155 : T4_BAR2_QTYPE_INGRESS),
2159 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2161 static struct pci_driver cxgb4_driver;
2163 static void check_neigh_update(struct neighbour *neigh)
2165 const struct device *parent;
2166 const struct net_device *netdev = neigh->dev;
2168 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2169 netdev = vlan_dev_real_dev(netdev);
2170 parent = netdev->dev.parent;
2171 if (parent && parent->driver == &cxgb4_driver.driver)
2172 t4_l2t_update(dev_get_drvdata(parent), neigh);
2175 static int netevent_cb(struct notifier_block *nb, unsigned long event,
2179 case NETEVENT_NEIGH_UPDATE:
2180 check_neigh_update(data);
2182 case NETEVENT_REDIRECT:
2189 static bool netevent_registered;
2190 static struct notifier_block cxgb4_netevent_nb = {
2191 .notifier_call = netevent_cb
2194 static void drain_db_fifo(struct adapter *adap, int usecs)
2196 u32 v1, v2, lp_count, hp_count;
2199 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2200 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2201 if (is_t4(adap->params.chip)) {
2202 lp_count = LP_COUNT_G(v1);
2203 hp_count = HP_COUNT_G(v1);
2205 lp_count = LP_COUNT_T5_G(v1);
2206 hp_count = HP_COUNT_T5_G(v2);
2209 if (lp_count == 0 && hp_count == 0)
2211 set_current_state(TASK_UNINTERRUPTIBLE);
2212 schedule_timeout(usecs_to_jiffies(usecs));
2216 static void disable_txq_db(struct sge_txq *q)
2218 unsigned long flags;
2220 spin_lock_irqsave(&q->db_lock, flags);
2222 spin_unlock_irqrestore(&q->db_lock, flags);
2225 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
2227 spin_lock_irq(&q->db_lock);
2228 if (q->db_pidx_inc) {
2229 /* Make sure that all writes to the TX descriptors
2230 * are committed before we tell HW about them.
2233 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2234 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
2238 spin_unlock_irq(&q->db_lock);
2241 static void disable_dbs(struct adapter *adap)
2245 for_each_ethrxq(&adap->sge, i)
2246 disable_txq_db(&adap->sge.ethtxq[i].q);
2247 for_each_ofldrxq(&adap->sge, i)
2248 disable_txq_db(&adap->sge.ofldtxq[i].q);
2249 for_each_port(adap, i)
2250 disable_txq_db(&adap->sge.ctrlq[i].q);
2253 static void enable_dbs(struct adapter *adap)
2257 for_each_ethrxq(&adap->sge, i)
2258 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
2259 for_each_ofldrxq(&adap->sge, i)
2260 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
2261 for_each_port(adap, i)
2262 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2265 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2267 if (adap->uld_handle[CXGB4_ULD_RDMA])
2268 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
2272 static void process_db_full(struct work_struct *work)
2274 struct adapter *adap;
2276 adap = container_of(work, struct adapter, db_full_task);
2278 drain_db_fifo(adap, dbfifo_drain_delay);
2280 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2281 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2282 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2283 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2286 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2288 u16 hw_pidx, hw_cidx;
2291 spin_lock_irq(&q->db_lock);
2292 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2295 if (q->db_pidx != hw_pidx) {
2299 if (q->db_pidx >= hw_pidx)
2300 delta = q->db_pidx - hw_pidx;
2302 delta = q->size - hw_pidx + q->db_pidx;
2304 if (is_t4(adap->params.chip))
2305 val = PIDX_V(delta);
2307 val = PIDX_T5_V(delta);
2309 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2310 QID_V(q->cntxt_id) | val);
2315 spin_unlock_irq(&q->db_lock);
2317 CH_WARN(adap, "DB drop recovery failed.\n");
2319 static void recover_all_queues(struct adapter *adap)
2323 for_each_ethrxq(&adap->sge, i)
2324 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2325 for_each_ofldrxq(&adap->sge, i)
2326 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
2327 for_each_port(adap, i)
2328 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2331 static void process_db_drop(struct work_struct *work)
2333 struct adapter *adap;
2335 adap = container_of(work, struct adapter, db_drop_task);
2337 if (is_t4(adap->params.chip)) {
2338 drain_db_fifo(adap, dbfifo_drain_delay);
2339 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2340 drain_db_fifo(adap, dbfifo_drain_delay);
2341 recover_all_queues(adap);
2342 drain_db_fifo(adap, dbfifo_drain_delay);
2344 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2346 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2347 u16 qid = (dropped_db >> 15) & 0x1ffff;
2348 u16 pidx_inc = dropped_db & 0x1fff;
2350 unsigned int bar2_qid;
2353 ret = cxgb4_t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2354 &bar2_qoffset, &bar2_qid);
2356 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2357 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2359 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2360 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2362 /* Re-enable BAR2 WC */
2363 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2366 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2369 void t4_db_full(struct adapter *adap)
2371 if (is_t4(adap->params.chip)) {
2373 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2374 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2375 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2376 queue_work(adap->workq, &adap->db_full_task);
2380 void t4_db_dropped(struct adapter *adap)
2382 if (is_t4(adap->params.chip)) {
2384 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2386 queue_work(adap->workq, &adap->db_drop_task);
2389 static void uld_attach(struct adapter *adap, unsigned int uld)
2392 struct cxgb4_lld_info lli;
2395 lli.pdev = adap->pdev;
2397 lli.l2t = adap->l2t;
2398 lli.tids = &adap->tids;
2399 lli.ports = adap->port;
2400 lli.vr = &adap->vres;
2401 lli.mtus = adap->params.mtus;
2402 if (uld == CXGB4_ULD_RDMA) {
2403 lli.rxq_ids = adap->sge.rdma_rxq;
2404 lli.ciq_ids = adap->sge.rdma_ciq;
2405 lli.nrxq = adap->sge.rdmaqs;
2406 lli.nciq = adap->sge.rdmaciqs;
2407 } else if (uld == CXGB4_ULD_ISCSI) {
2408 lli.rxq_ids = adap->sge.ofld_rxq;
2409 lli.nrxq = adap->sge.ofldqsets;
2411 lli.ntxq = adap->sge.ofldqsets;
2412 lli.nchan = adap->params.nports;
2413 lli.nports = adap->params.nports;
2414 lli.wr_cred = adap->params.ofldq_wr_cred;
2415 lli.adapter_type = adap->params.chip;
2416 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
2417 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
2418 lli.udb_density = 1 << adap->params.sge.eq_qpp;
2419 lli.ucq_density = 1 << adap->params.sge.iq_qpp;
2420 lli.filt_mode = adap->params.tp.vlan_pri_map;
2421 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
2422 for (i = 0; i < NCHAN; i++)
2424 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
2425 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
2426 lli.fw_vers = adap->params.fw_vers;
2427 lli.dbfifo_int_thresh = dbfifo_int_thresh;
2428 lli.sge_ingpadboundary = adap->sge.fl_align;
2429 lli.sge_egrstatuspagesize = adap->sge.stat_len;
2430 lli.sge_pktshift = adap->sge.pktshift;
2431 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
2432 lli.max_ordird_qp = adap->params.max_ordird_qp;
2433 lli.max_ird_adapter = adap->params.max_ird_adapter;
2434 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
2436 handle = ulds[uld].add(&lli);
2437 if (IS_ERR(handle)) {
2438 dev_warn(adap->pdev_dev,
2439 "could not attach to the %s driver, error %ld\n",
2440 uld_str[uld], PTR_ERR(handle));
2444 adap->uld_handle[uld] = handle;
2446 if (!netevent_registered) {
2447 register_netevent_notifier(&cxgb4_netevent_nb);
2448 netevent_registered = true;
2451 if (adap->flags & FULL_INIT_DONE)
2452 ulds[uld].state_change(handle, CXGB4_STATE_UP);
2455 static void attach_ulds(struct adapter *adap)
2459 spin_lock(&adap_rcu_lock);
2460 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
2461 spin_unlock(&adap_rcu_lock);
2463 mutex_lock(&uld_mutex);
2464 list_add_tail(&adap->list_node, &adapter_list);
2465 for (i = 0; i < CXGB4_ULD_MAX; i++)
2467 uld_attach(adap, i);
2468 mutex_unlock(&uld_mutex);
2471 static void detach_ulds(struct adapter *adap)
2475 mutex_lock(&uld_mutex);
2476 list_del(&adap->list_node);
2477 for (i = 0; i < CXGB4_ULD_MAX; i++)
2478 if (adap->uld_handle[i]) {
2479 ulds[i].state_change(adap->uld_handle[i],
2480 CXGB4_STATE_DETACH);
2481 adap->uld_handle[i] = NULL;
2483 if (netevent_registered && list_empty(&adapter_list)) {
2484 unregister_netevent_notifier(&cxgb4_netevent_nb);
2485 netevent_registered = false;
2487 mutex_unlock(&uld_mutex);
2489 spin_lock(&adap_rcu_lock);
2490 list_del_rcu(&adap->rcu_node);
2491 spin_unlock(&adap_rcu_lock);
2494 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2498 mutex_lock(&uld_mutex);
2499 for (i = 0; i < CXGB4_ULD_MAX; i++)
2500 if (adap->uld_handle[i])
2501 ulds[i].state_change(adap->uld_handle[i], new_state);
2502 mutex_unlock(&uld_mutex);
2506 * cxgb4_register_uld - register an upper-layer driver
2507 * @type: the ULD type
2508 * @p: the ULD methods
2510 * Registers an upper-layer driver with this driver and notifies the ULD
2511 * about any presently available devices that support its type. Returns
2512 * %-EBUSY if a ULD of the same type is already registered.
2514 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2517 struct adapter *adap;
2519 if (type >= CXGB4_ULD_MAX)
2521 mutex_lock(&uld_mutex);
2522 if (ulds[type].add) {
2527 list_for_each_entry(adap, &adapter_list, list_node)
2528 uld_attach(adap, type);
2529 out: mutex_unlock(&uld_mutex);
2532 EXPORT_SYMBOL(cxgb4_register_uld);
2535 * cxgb4_unregister_uld - unregister an upper-layer driver
2536 * @type: the ULD type
2538 * Unregisters an existing upper-layer driver.
2540 int cxgb4_unregister_uld(enum cxgb4_uld type)
2542 struct adapter *adap;
2544 if (type >= CXGB4_ULD_MAX)
2546 mutex_lock(&uld_mutex);
2547 list_for_each_entry(adap, &adapter_list, list_node)
2548 adap->uld_handle[type] = NULL;
2549 ulds[type].add = NULL;
2550 mutex_unlock(&uld_mutex);
2553 EXPORT_SYMBOL(cxgb4_unregister_uld);
2555 #if IS_ENABLED(CONFIG_IPV6)
2556 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2557 unsigned long event, void *data)
2559 struct inet6_ifaddr *ifa = data;
2560 struct net_device *event_dev = ifa->idev->dev;
2561 const struct device *parent = NULL;
2562 #if IS_ENABLED(CONFIG_BONDING)
2563 struct adapter *adap;
2565 if (event_dev->priv_flags & IFF_802_1Q_VLAN)
2566 event_dev = vlan_dev_real_dev(event_dev);
2567 #if IS_ENABLED(CONFIG_BONDING)
2568 if (event_dev->flags & IFF_MASTER) {
2569 list_for_each_entry(adap, &adapter_list, list_node) {
2572 cxgb4_clip_get(adap->port[0],
2573 (const u32 *)ifa, 1);
2576 cxgb4_clip_release(adap->port[0],
2577 (const u32 *)ifa, 1);
2588 parent = event_dev->dev.parent;
2590 if (parent && parent->driver == &cxgb4_driver.driver) {
2593 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2596 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2605 static bool inet6addr_registered;
2606 static struct notifier_block cxgb4_inet6addr_notifier = {
2607 .notifier_call = cxgb4_inet6addr_handler
2610 static void update_clip(const struct adapter *adap)
2613 struct net_device *dev;
2618 for (i = 0; i < MAX_NPORTS; i++) {
2619 dev = adap->port[i];
2623 ret = cxgb4_update_root_dev_clip(dev);
2630 #endif /* IS_ENABLED(CONFIG_IPV6) */
2633 * cxgb_up - enable the adapter
2634 * @adap: adapter being enabled
2636 * Called when the first port is enabled, this function performs the
2637 * actions necessary to make an adapter operational, such as completing
2638 * the initialization of HW modules, and enabling interrupts.
2640 * Must be called with the rtnl lock held.
2642 static int cxgb_up(struct adapter *adap)
2646 err = setup_sge_queues(adap);
2649 err = setup_rss(adap);
2653 if (adap->flags & USING_MSIX) {
2654 name_msix_vecs(adap);
2655 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2656 adap->msix_info[0].desc, adap);
2660 err = request_msix_queue_irqs(adap);
2662 free_irq(adap->msix_info[0].vec, adap);
2666 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2667 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2668 adap->port[0]->name, adap);
2674 t4_intr_enable(adap);
2675 adap->flags |= FULL_INIT_DONE;
2676 notify_ulds(adap, CXGB4_STATE_UP);
2677 #if IS_ENABLED(CONFIG_IPV6)
2683 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2685 t4_free_sge_resources(adap);
2689 static void cxgb_down(struct adapter *adapter)
2691 cancel_work_sync(&adapter->tid_release_task);
2692 cancel_work_sync(&adapter->db_full_task);
2693 cancel_work_sync(&adapter->db_drop_task);
2694 adapter->tid_release_task_busy = false;
2695 adapter->tid_release_head = NULL;
2697 t4_sge_stop(adapter);
2698 t4_free_sge_resources(adapter);
2699 adapter->flags &= ~FULL_INIT_DONE;
2703 * net_device operations
2705 static int cxgb_open(struct net_device *dev)
2708 struct port_info *pi = netdev_priv(dev);
2709 struct adapter *adapter = pi->adapter;
2711 netif_carrier_off(dev);
2713 if (!(adapter->flags & FULL_INIT_DONE)) {
2714 err = cxgb_up(adapter);
2719 err = link_start(dev);
2721 netif_tx_start_all_queues(dev);
2725 static int cxgb_close(struct net_device *dev)
2727 struct port_info *pi = netdev_priv(dev);
2728 struct adapter *adapter = pi->adapter;
2730 netif_tx_stop_all_queues(dev);
2731 netif_carrier_off(dev);
2732 return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
2735 /* Return an error number if the indicated filter isn't writable ...
2737 static int writable_filter(struct filter_entry *f)
2747 /* Delete the filter at the specified index (if valid). The checks for all
2748 * the common problems with doing this like the filter being locked, currently
2749 * pending in another operation, etc.
2751 static int delete_filter(struct adapter *adapter, unsigned int fidx)
2753 struct filter_entry *f;
2756 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
2759 f = &adapter->tids.ftid_tab[fidx];
2760 ret = writable_filter(f);
2764 return del_filter_wr(adapter, fidx);
2769 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2770 __be32 sip, __be16 sport, __be16 vlan,
2771 unsigned int queue, unsigned char port, unsigned char mask)
2774 struct filter_entry *f;
2775 struct adapter *adap;
2779 adap = netdev2adap(dev);
2781 /* Adjust stid to correct filter index */
2782 stid -= adap->tids.sftid_base;
2783 stid += adap->tids.nftids;
2785 /* Check to make sure the filter requested is writable ...
2787 f = &adap->tids.ftid_tab[stid];
2788 ret = writable_filter(f);
2792 /* Clear out any old resources being used by the filter before
2793 * we start constructing the new filter.
2796 clear_filter(adap, f);
2798 /* Clear out filter specifications */
2799 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2800 f->fs.val.lport = cpu_to_be16(sport);
2801 f->fs.mask.lport = ~0;
2803 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2804 for (i = 0; i < 4; i++) {
2805 f->fs.val.lip[i] = val[i];
2806 f->fs.mask.lip[i] = ~0;
2808 if (adap->params.tp.vlan_pri_map & PORT_F) {
2809 f->fs.val.iport = port;
2810 f->fs.mask.iport = mask;
2814 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2815 f->fs.val.proto = IPPROTO_TCP;
2816 f->fs.mask.proto = ~0;
2821 /* Mark filter as locked */
2825 ret = set_filter_wr(adap, stid);
2827 clear_filter(adap, f);
2833 EXPORT_SYMBOL(cxgb4_create_server_filter);
2835 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2836 unsigned int queue, bool ipv6)
2839 struct filter_entry *f;
2840 struct adapter *adap;
2842 adap = netdev2adap(dev);
2844 /* Adjust stid to correct filter index */
2845 stid -= adap->tids.sftid_base;
2846 stid += adap->tids.nftids;
2848 f = &adap->tids.ftid_tab[stid];
2849 /* Unlock the filter */
2852 ret = delete_filter(adap, stid);
2858 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2860 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2861 struct rtnl_link_stats64 *ns)
2863 struct port_stats stats;
2864 struct port_info *p = netdev_priv(dev);
2865 struct adapter *adapter = p->adapter;
2867 /* Block retrieving statistics during EEH error
2868 * recovery. Otherwise, the recovery might fail
2869 * and the PCI device will be removed permanently
2871 spin_lock(&adapter->stats_lock);
2872 if (!netif_device_present(dev)) {
2873 spin_unlock(&adapter->stats_lock);
2876 t4_get_port_stats(adapter, p->tx_chan, &stats);
2877 spin_unlock(&adapter->stats_lock);
2879 ns->tx_bytes = stats.tx_octets;
2880 ns->tx_packets = stats.tx_frames;
2881 ns->rx_bytes = stats.rx_octets;
2882 ns->rx_packets = stats.rx_frames;
2883 ns->multicast = stats.rx_mcast_frames;
2885 /* detailed rx_errors */
2886 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2888 ns->rx_over_errors = 0;
2889 ns->rx_crc_errors = stats.rx_fcs_err;
2890 ns->rx_frame_errors = stats.rx_symbol_err;
2891 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2892 stats.rx_ovflow2 + stats.rx_ovflow3 +
2893 stats.rx_trunc0 + stats.rx_trunc1 +
2894 stats.rx_trunc2 + stats.rx_trunc3;
2895 ns->rx_missed_errors = 0;
2897 /* detailed tx_errors */
2898 ns->tx_aborted_errors = 0;
2899 ns->tx_carrier_errors = 0;
2900 ns->tx_fifo_errors = 0;
2901 ns->tx_heartbeat_errors = 0;
2902 ns->tx_window_errors = 0;
2904 ns->tx_errors = stats.tx_error_frames;
2905 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2906 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2910 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2913 int ret = 0, prtad, devad;
2914 struct port_info *pi = netdev_priv(dev);
2915 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2919 if (pi->mdio_addr < 0)
2921 data->phy_id = pi->mdio_addr;
2925 if (mdio_phy_id_is_c45(data->phy_id)) {
2926 prtad = mdio_phy_id_prtad(data->phy_id);
2927 devad = mdio_phy_id_devad(data->phy_id);
2928 } else if (data->phy_id < 32) {
2929 prtad = data->phy_id;
2931 data->reg_num &= 0x1f;
2935 mbox = pi->adapter->fn;
2936 if (cmd == SIOCGMIIREG)
2937 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2938 data->reg_num, &data->val_out);
2940 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2941 data->reg_num, data->val_in);
2949 static void cxgb_set_rxmode(struct net_device *dev)
2951 /* unfortunately we can't return errors to the stack */
2952 set_rxmode(dev, -1, false);
2955 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2958 struct port_info *pi = netdev_priv(dev);
2960 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
2962 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
2969 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2972 struct sockaddr *addr = p;
2973 struct port_info *pi = netdev_priv(dev);
2975 if (!is_valid_ether_addr(addr->sa_data))
2976 return -EADDRNOTAVAIL;
2978 ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
2979 pi->xact_addr_filt, addr->sa_data, true, true);
2983 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2984 pi->xact_addr_filt = ret;
2988 #ifdef CONFIG_NET_POLL_CONTROLLER
2989 static void cxgb_netpoll(struct net_device *dev)
2991 struct port_info *pi = netdev_priv(dev);
2992 struct adapter *adap = pi->adapter;
2994 if (adap->flags & USING_MSIX) {
2996 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2998 for (i = pi->nqsets; i; i--, rx++)
2999 t4_sge_intr_msix(0, &rx->rspq);
3001 t4_intr_handler(adap)(0, adap);
3005 static const struct net_device_ops cxgb4_netdev_ops = {
3006 .ndo_open = cxgb_open,
3007 .ndo_stop = cxgb_close,
3008 .ndo_start_xmit = t4_eth_xmit,
3009 .ndo_select_queue = cxgb_select_queue,
3010 .ndo_get_stats64 = cxgb_get_stats,
3011 .ndo_set_rx_mode = cxgb_set_rxmode,
3012 .ndo_set_mac_address = cxgb_set_mac_addr,
3013 .ndo_set_features = cxgb_set_features,
3014 .ndo_validate_addr = eth_validate_addr,
3015 .ndo_do_ioctl = cxgb_ioctl,
3016 .ndo_change_mtu = cxgb_change_mtu,
3017 #ifdef CONFIG_NET_POLL_CONTROLLER
3018 .ndo_poll_controller = cxgb_netpoll,
3020 #ifdef CONFIG_CHELSIO_T4_FCOE
3021 .ndo_fcoe_enable = cxgb_fcoe_enable,
3022 .ndo_fcoe_disable = cxgb_fcoe_disable,
3023 #endif /* CONFIG_CHELSIO_T4_FCOE */
3024 #ifdef CONFIG_NET_RX_BUSY_POLL
3025 .ndo_busy_poll = cxgb_busy_poll,
3030 void t4_fatal_err(struct adapter *adap)
3032 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
3033 t4_intr_disable(adap);
3034 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3037 /* Return the specified PCI-E Configuration Space register from our Physical
3038 * Function. We try first via a Firmware LDST Command since we prefer to let
3039 * the firmware own all of these registers, but if that fails we go for it
3040 * directly ourselves.
3042 static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
3044 struct fw_ldst_cmd ldst_cmd;
3048 /* Construct and send the Firmware LDST Command to retrieve the
3049 * specified PCI-E Configuration Space register.
3051 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
3052 ldst_cmd.op_to_addrspace =
3053 htonl(FW_CMD_OP_V(FW_LDST_CMD) |
3056 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE));
3057 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
3058 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
3059 ldst_cmd.u.pcie.ctrl_to_fn =
3060 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->fn));
3061 ldst_cmd.u.pcie.r = reg;
3062 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
3065 /* If the LDST Command suucceeded, exctract the returned register
3066 * value. Otherwise read it directly ourself.
3069 val = ntohl(ldst_cmd.u.pcie.data[0]);
3071 t4_hw_pci_read_cfg4(adap, reg, &val);
3076 static void setup_memwin(struct adapter *adap)
3078 u32 mem_win0_base, mem_win1_base, mem_win2_base, mem_win2_aperture;
3080 if (is_t4(adap->params.chip)) {
3083 /* Truncation intentional: we only read the bottom 32-bits of
3084 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
3085 * mechanism to read BAR0 instead of using
3086 * pci_resource_start() because we could be operating from
3087 * within a Virtual Machine which is trapping our accesses to
3088 * our Configuration Space and we need to set up the PCI-E
3089 * Memory Window decoders with the actual addresses which will
3090 * be coming across the PCI-E link.
3092 bar0 = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_0);
3093 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
3094 adap->t4_bar0 = bar0;
3096 mem_win0_base = bar0 + MEMWIN0_BASE;
3097 mem_win1_base = bar0 + MEMWIN1_BASE;
3098 mem_win2_base = bar0 + MEMWIN2_BASE;
3099 mem_win2_aperture = MEMWIN2_APERTURE;
3101 /* For T5, only relative offset inside the PCIe BAR is passed */
3102 mem_win0_base = MEMWIN0_BASE;
3103 mem_win1_base = MEMWIN1_BASE;
3104 mem_win2_base = MEMWIN2_BASE_T5;
3105 mem_win2_aperture = MEMWIN2_APERTURE_T5;
3107 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 0),
3108 mem_win0_base | BIR_V(0) |
3109 WINDOW_V(ilog2(MEMWIN0_APERTURE) - 10));
3110 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 1),
3111 mem_win1_base | BIR_V(0) |
3112 WINDOW_V(ilog2(MEMWIN1_APERTURE) - 10));
3113 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2),
3114 mem_win2_base | BIR_V(0) |
3115 WINDOW_V(ilog2(mem_win2_aperture) - 10));
3116 t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2));
3119 static void setup_memwin_rdma(struct adapter *adap)
3121 if (adap->vres.ocq.size) {
3125 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3126 start &= PCI_BASE_ADDRESS_MEM_MASK;
3127 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3128 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3130 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3131 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3133 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3134 adap->vres.ocq.start);
3136 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3140 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3145 /* get device capabilities */
3146 memset(c, 0, sizeof(*c));
3147 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3148 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3149 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3150 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
3154 /* select capabilities we'll be using */
3155 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
3157 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
3159 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
3160 } else if (vf_acls) {
3161 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
3164 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3165 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3166 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
3170 ret = t4_config_glbl_rss(adap, adap->fn,
3171 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3172 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3173 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3177 ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, adap->sge.egr_sz, 64,
3178 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3185 /* tweak some settings */
3186 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3187 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3188 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3189 v = t4_read_reg(adap, TP_PIO_DATA_A);
3190 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3192 /* first 4 Tx modulation queues point to consecutive Tx channels */
3193 adap->params.tp.tx_modq_map = 0xE4;
3194 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3195 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3197 /* associate each Tx modulation queue with consecutive Tx channels */
3199 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3200 &v, 1, TP_TX_SCHED_HDR_A);
3201 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3202 &v, 1, TP_TX_SCHED_FIFO_A);
3203 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3204 &v, 1, TP_TX_SCHED_PCMD_A);
3206 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3207 if (is_offload(adap)) {
3208 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3209 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3210 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3211 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3212 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3213 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3214 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3215 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3216 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3217 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3220 /* get basic stuff going */
3221 return t4_early_init(adap, adap->fn);
3225 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3227 #define MAX_ATIDS 8192U
3230 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3232 * If the firmware we're dealing with has Configuration File support, then
3233 * we use that to perform all configuration
3237 * Tweak configuration based on module parameters, etc. Most of these have
3238 * defaults assigned to them by Firmware Configuration Files (if we're using
3239 * them) but need to be explicitly set if we're using hard-coded
3240 * initialization. But even in the case of using Firmware Configuration
3241 * Files, we'd like to expose the ability to change these via module
3242 * parameters so these are essentially common tweaks/settings for
3243 * Configuration Files and hard-coded initialization ...
3245 static int adap_init0_tweaks(struct adapter *adapter)
3248 * Fix up various Host-Dependent Parameters like Page Size, Cache
3249 * Line Size, etc. The firmware default is for a 4KB Page Size and
3250 * 64B Cache Line Size ...
3252 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3255 * Process module parameters which affect early initialization.
3257 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3258 dev_err(&adapter->pdev->dev,
3259 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3263 t4_set_reg_field(adapter, SGE_CONTROL_A,
3264 PKTSHIFT_V(PKTSHIFT_M),
3265 PKTSHIFT_V(rx_dma_offset));
3268 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3269 * adds the pseudo header itself.
3271 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3272 CSUM_HAS_PSEUDO_HDR_F, 0);
3278 * Attempt to initialize the adapter via a Firmware Configuration File.
3280 static int adap_init0_config(struct adapter *adapter, int reset)
3282 struct fw_caps_config_cmd caps_cmd;
3283 const struct firmware *cf;
3284 unsigned long mtype = 0, maddr = 0;
3285 u32 finiver, finicsum, cfcsum;
3287 int config_issued = 0;
3288 char *fw_config_file, fw_config_file_path[256];
3289 char *config_name = NULL;
3292 * Reset device if necessary.
3295 ret = t4_fw_reset(adapter, adapter->mbox,
3296 PIORSTMODE_F | PIORST_F);
3302 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3303 * then use that. Otherwise, use the configuration file stored
3304 * in the adapter flash ...
3306 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3308 fw_config_file = FW4_CFNAME;
3311 fw_config_file = FW5_CFNAME;
3314 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3315 adapter->pdev->device);
3320 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3322 config_name = "On FLASH";
3323 mtype = FW_MEMTYPE_CF_FLASH;
3324 maddr = t4_flash_cfg_addr(adapter);
3326 u32 params[7], val[7];
3328 sprintf(fw_config_file_path,
3329 "/lib/firmware/%s", fw_config_file);
3330 config_name = fw_config_file_path;
3332 if (cf->size >= FLASH_CFG_MAX_SIZE)
3335 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3336 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3337 ret = t4_query_params(adapter, adapter->mbox,
3338 adapter->fn, 0, 1, params, val);
3341 * For t4_memory_rw() below addresses and
3342 * sizes have to be in terms of multiples of 4
3343 * bytes. So, if the Configuration File isn't
3344 * a multiple of 4 bytes in length we'll have
3345 * to write that out separately since we can't
3346 * guarantee that the bytes following the
3347 * residual byte in the buffer returned by
3348 * request_firmware() are zeroed out ...
3350 size_t resid = cf->size & 0x3;
3351 size_t size = cf->size & ~0x3;
3352 __be32 *data = (__be32 *)cf->data;
3354 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3355 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3357 spin_lock(&adapter->win0_lock);
3358 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3359 size, data, T4_MEMORY_WRITE);
3360 if (ret == 0 && resid != 0) {
3367 last.word = data[size >> 2];
3368 for (i = resid; i < 4; i++)
3370 ret = t4_memory_rw(adapter, 0, mtype,
3375 spin_unlock(&adapter->win0_lock);
3379 release_firmware(cf);
3385 * Issue a Capability Configuration command to the firmware to get it
3386 * to parse the Configuration File. We don't use t4_fw_config_file()
3387 * because we want the ability to modify various features after we've
3388 * processed the configuration file ...
3390 memset(&caps_cmd, 0, sizeof(caps_cmd));
3391 caps_cmd.op_to_write =
3392 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3395 caps_cmd.cfvalid_to_len16 =
3396 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3397 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3398 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
3399 FW_LEN16(caps_cmd));
3400 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3403 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3404 * Configuration File in FLASH), our last gasp effort is to use the
3405 * Firmware Configuration File which is embedded in the firmware. A
3406 * very few early versions of the firmware didn't have one embedded
3407 * but we can ignore those.
3409 if (ret == -ENOENT) {
3410 memset(&caps_cmd, 0, sizeof(caps_cmd));
3411 caps_cmd.op_to_write =
3412 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3415 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3416 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3417 sizeof(caps_cmd), &caps_cmd);
3418 config_name = "Firmware Default";
3425 finiver = ntohl(caps_cmd.finiver);
3426 finicsum = ntohl(caps_cmd.finicsum);
3427 cfcsum = ntohl(caps_cmd.cfcsum);
3428 if (finicsum != cfcsum)
3429 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3430 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3434 * And now tell the firmware to use the configuration we just loaded.
3436 caps_cmd.op_to_write =
3437 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3440 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3441 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3447 * Tweak configuration based on system architecture, module
3450 ret = adap_init0_tweaks(adapter);
3455 * And finally tell the firmware to initialize itself using the
3456 * parameters from the Configuration File.
3458 ret = t4_fw_initialize(adapter, adapter->mbox);
3462 /* Emit Firmware Configuration File information and return
3465 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
3466 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3467 config_name, finiver, cfcsum);
3471 * Something bad happened. Return the error ... (If the "error"
3472 * is that there's no Configuration File on the adapter we don't
3473 * want to issue a warning since this is fairly common.)
3476 if (config_issued && ret != -ENOENT)
3477 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3482 static struct fw_info fw_info_array[] = {
3485 .fs_name = FW4_CFNAME,
3486 .fw_mod_name = FW4_FNAME,
3488 .chip = FW_HDR_CHIP_T4,
3489 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3490 .intfver_nic = FW_INTFVER(T4, NIC),
3491 .intfver_vnic = FW_INTFVER(T4, VNIC),
3492 .intfver_ri = FW_INTFVER(T4, RI),
3493 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3494 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3498 .fs_name = FW5_CFNAME,
3499 .fw_mod_name = FW5_FNAME,
3501 .chip = FW_HDR_CHIP_T5,
3502 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3503 .intfver_nic = FW_INTFVER(T5, NIC),
3504 .intfver_vnic = FW_INTFVER(T5, VNIC),
3505 .intfver_ri = FW_INTFVER(T5, RI),
3506 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3507 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3512 static struct fw_info *find_fw_info(int chip)
3516 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3517 if (fw_info_array[i].chip == chip)
3518 return &fw_info_array[i];
3524 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3526 static int adap_init0(struct adapter *adap)
3530 enum dev_state state;
3531 u32 params[7], val[7];
3532 struct fw_caps_config_cmd caps_cmd;
3535 /* Grab Firmware Device Log parameters as early as possible so we have
3536 * access to it for debugging, etc.
3538 ret = t4_init_devlog_params(adap);
3542 /* Contact FW, advertising Master capability */
3543 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
3545 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3549 if (ret == adap->mbox)
3550 adap->flags |= MASTER_PF;
3553 * If we're the Master PF Driver and the device is uninitialized,
3554 * then let's consider upgrading the firmware ... (We always want
3555 * to check the firmware version number in order to A. get it for
3556 * later reporting and B. to warn if the currently loaded firmware
3557 * is excessively mismatched relative to the driver.)
3559 t4_get_fw_version(adap, &adap->params.fw_vers);
3560 t4_get_tp_version(adap, &adap->params.tp_vers);
3561 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
3562 struct fw_info *fw_info;
3563 struct fw_hdr *card_fw;
3564 const struct firmware *fw;
3565 const u8 *fw_data = NULL;
3566 unsigned int fw_size = 0;
3568 /* This is the firmware whose headers the driver was compiled
3571 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3572 if (fw_info == NULL) {
3573 dev_err(adap->pdev_dev,
3574 "unable to get firmware info for chip %d.\n",
3575 CHELSIO_CHIP_VERSION(adap->params.chip));
3579 /* allocate memory to read the header of the firmware on the
3582 card_fw = t4_alloc_mem(sizeof(*card_fw));
3584 /* Get FW from from /lib/firmware/ */
3585 ret = request_firmware(&fw, fw_info->fw_mod_name,
3588 dev_err(adap->pdev_dev,
3589 "unable to load firmware image %s, error %d\n",
3590 fw_info->fw_mod_name, ret);
3596 /* upgrade FW logic */
3597 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3601 release_firmware(fw);
3602 t4_free_mem(card_fw);
3609 * Grab VPD parameters. This should be done after we establish a
3610 * connection to the firmware since some of the VPD parameters
3611 * (notably the Core Clock frequency) are retrieved via requests to
3612 * the firmware. On the other hand, we need these fairly early on
3613 * so we do this right after getting ahold of the firmware.
3615 ret = get_vpd_params(adap, &adap->params.vpd);
3620 * Find out what ports are available to us. Note that we need to do
3621 * this before calling adap_init0_no_config() since it needs nports
3625 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3626 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
3627 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
3631 adap->params.nports = hweight32(port_vec);
3632 adap->params.portvec = port_vec;
3634 /* If the firmware is initialized already, emit a simply note to that
3635 * effect. Otherwise, it's time to try initializing the adapter.
3637 if (state == DEV_STATE_INIT) {
3638 dev_info(adap->pdev_dev, "Coming up as %s: "\
3639 "Adapter already initialized\n",
3640 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
3642 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3643 "Initializing adapter\n");
3645 /* Find out whether we're dealing with a version of the
3646 * firmware which has configuration file support.
3648 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3649 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3650 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
3653 /* If the firmware doesn't support Configuration Files,
3657 dev_err(adap->pdev_dev, "firmware doesn't support "
3658 "Firmware Configuration Files\n");
3662 /* The firmware provides us with a memory buffer where we can
3663 * load a Configuration File from the host if we want to
3664 * override the Configuration File in flash.
3666 ret = adap_init0_config(adap, reset);
3667 if (ret == -ENOENT) {
3668 dev_err(adap->pdev_dev, "no Configuration File "
3669 "present on adapter.\n");
3673 dev_err(adap->pdev_dev, "could not initialize "
3674 "adapter, error %d\n", -ret);
3679 /* Give the SGE code a chance to pull in anything that it needs ...
3680 * Note that this must be called after we retrieve our VPD parameters
3681 * in order to know how to convert core ticks to seconds, etc.
3683 ret = t4_sge_init(adap);
3687 if (is_bypass_device(adap->pdev->device))
3688 adap->params.bypass = 1;
3691 * Grab some of our basic fundamental operating parameters.
3693 #define FW_PARAM_DEV(param) \
3694 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3695 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
3697 #define FW_PARAM_PFVF(param) \
3698 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3699 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
3700 FW_PARAMS_PARAM_Y_V(0) | \
3701 FW_PARAMS_PARAM_Z_V(0)
3703 params[0] = FW_PARAM_PFVF(EQ_START);
3704 params[1] = FW_PARAM_PFVF(L2T_START);
3705 params[2] = FW_PARAM_PFVF(L2T_END);
3706 params[3] = FW_PARAM_PFVF(FILTER_START);
3707 params[4] = FW_PARAM_PFVF(FILTER_END);
3708 params[5] = FW_PARAM_PFVF(IQFLINT_START);
3709 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
3712 adap->sge.egr_start = val[0];
3713 adap->l2t_start = val[1];
3714 adap->l2t_end = val[2];
3715 adap->tids.ftid_base = val[3];
3716 adap->tids.nftids = val[4] - val[3] + 1;
3717 adap->sge.ingr_start = val[5];
3719 /* qids (ingress/egress) returned from firmware can be anywhere
3720 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3721 * Hence driver needs to allocate memory for this range to
3722 * store the queue info. Get the highest IQFLINT/EQ index returned
3723 * in FW_EQ_*_CMD.alloc command.
3725 params[0] = FW_PARAM_PFVF(EQ_END);
3726 params[1] = FW_PARAM_PFVF(IQFLINT_END);
3727 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
3730 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3731 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3733 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3734 sizeof(*adap->sge.egr_map), GFP_KERNEL);
3735 if (!adap->sge.egr_map) {
3740 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3741 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3742 if (!adap->sge.ingr_map) {
3747 /* Allocate the memory for the vaious egress queue bitmaps
3748 * ie starving_fl and txq_maperr.
3750 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3751 sizeof(long), GFP_KERNEL);
3752 if (!adap->sge.starving_fl) {
3757 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3758 sizeof(long), GFP_KERNEL);
3759 if (!adap->sge.txq_maperr) {
3764 params[0] = FW_PARAM_PFVF(CLIP_START);
3765 params[1] = FW_PARAM_PFVF(CLIP_END);
3766 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
3769 adap->clipt_start = val[0];
3770 adap->clipt_end = val[1];
3772 /* query params related to active filter region */
3773 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3774 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
3775 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
3776 /* If Active filter size is set we enable establishing
3777 * offload connection through firmware work request
3779 if ((val[0] != val[1]) && (ret >= 0)) {
3780 adap->flags |= FW_OFLD_CONN;
3781 adap->tids.aftid_base = val[0];
3782 adap->tids.aftid_end = val[1];
3785 /* If we're running on newer firmware, let it know that we're
3786 * prepared to deal with encapsulated CPL messages. Older
3787 * firmware won't understand this and we'll just get
3788 * unencapsulated messages ...
3790 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3792 (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
3795 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3796 * capability. Earlier versions of the firmware didn't have the
3797 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3798 * permission to use ULPTX MEMWRITE DSGL.
3800 if (is_t4(adap->params.chip)) {
3801 adap->params.ulptx_memwrite_dsgl = false;
3803 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
3804 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
3806 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3810 * Get device capabilities so we can determine what resources we need
3813 memset(&caps_cmd, 0, sizeof(caps_cmd));
3814 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3815 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3816 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3817 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3822 if (caps_cmd.ofldcaps) {
3823 /* query offload-related parameters */
3824 params[0] = FW_PARAM_DEV(NTID);
3825 params[1] = FW_PARAM_PFVF(SERVER_START);
3826 params[2] = FW_PARAM_PFVF(SERVER_END);
3827 params[3] = FW_PARAM_PFVF(TDDP_START);
3828 params[4] = FW_PARAM_PFVF(TDDP_END);
3829 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3830 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
3834 adap->tids.ntids = val[0];
3835 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3836 adap->tids.stid_base = val[1];
3837 adap->tids.nstids = val[2] - val[1] + 1;
3839 * Setup server filter region. Divide the available filter
3840 * region into two parts. Regular filters get 1/3rd and server
3841 * filters get 2/3rd part. This is only enabled if workarond
3843 * 1. For regular filters.
3844 * 2. Server filter: This are special filters which are used
3845 * to redirect SYN packets to offload queue.
3847 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
3848 adap->tids.sftid_base = adap->tids.ftid_base +
3849 DIV_ROUND_UP(adap->tids.nftids, 3);
3850 adap->tids.nsftids = adap->tids.nftids -
3851 DIV_ROUND_UP(adap->tids.nftids, 3);
3852 adap->tids.nftids = adap->tids.sftid_base -
3853 adap->tids.ftid_base;
3855 adap->vres.ddp.start = val[3];
3856 adap->vres.ddp.size = val[4] - val[3] + 1;
3857 adap->params.ofldq_wr_cred = val[5];
3859 adap->params.offload = 1;
3861 if (caps_cmd.rdmacaps) {
3862 params[0] = FW_PARAM_PFVF(STAG_START);
3863 params[1] = FW_PARAM_PFVF(STAG_END);
3864 params[2] = FW_PARAM_PFVF(RQ_START);
3865 params[3] = FW_PARAM_PFVF(RQ_END);
3866 params[4] = FW_PARAM_PFVF(PBL_START);
3867 params[5] = FW_PARAM_PFVF(PBL_END);
3868 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
3872 adap->vres.stag.start = val[0];
3873 adap->vres.stag.size = val[1] - val[0] + 1;
3874 adap->vres.rq.start = val[2];
3875 adap->vres.rq.size = val[3] - val[2] + 1;
3876 adap->vres.pbl.start = val[4];
3877 adap->vres.pbl.size = val[5] - val[4] + 1;
3879 params[0] = FW_PARAM_PFVF(SQRQ_START);
3880 params[1] = FW_PARAM_PFVF(SQRQ_END);
3881 params[2] = FW_PARAM_PFVF(CQ_START);
3882 params[3] = FW_PARAM_PFVF(CQ_END);
3883 params[4] = FW_PARAM_PFVF(OCQ_START);
3884 params[5] = FW_PARAM_PFVF(OCQ_END);
3885 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params,
3889 adap->vres.qp.start = val[0];
3890 adap->vres.qp.size = val[1] - val[0] + 1;
3891 adap->vres.cq.start = val[2];
3892 adap->vres.cq.size = val[3] - val[2] + 1;
3893 adap->vres.ocq.start = val[4];
3894 adap->vres.ocq.size = val[5] - val[4] + 1;
3896 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
3897 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
3898 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params,
3901 adap->params.max_ordird_qp = 8;
3902 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
3905 adap->params.max_ordird_qp = val[0];
3906 adap->params.max_ird_adapter = val[1];
3908 dev_info(adap->pdev_dev,
3909 "max_ordird_qp %d max_ird_adapter %d\n",
3910 adap->params.max_ordird_qp,
3911 adap->params.max_ird_adapter);
3913 if (caps_cmd.iscsicaps) {
3914 params[0] = FW_PARAM_PFVF(ISCSI_START);
3915 params[1] = FW_PARAM_PFVF(ISCSI_END);
3916 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
3920 adap->vres.iscsi.start = val[0];
3921 adap->vres.iscsi.size = val[1] - val[0] + 1;
3923 #undef FW_PARAM_PFVF
3926 /* The MTU/MSS Table is initialized by now, so load their values. If
3927 * we're initializing the adapter, then we'll make any modifications
3928 * we want to the MTU/MSS Table and also initialize the congestion
3931 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
3932 if (state != DEV_STATE_INIT) {
3935 /* The default MTU Table contains values 1492 and 1500.
3936 * However, for TCP, it's better to have two values which are
3937 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
3938 * This allows us to have a TCP Data Payload which is a
3939 * multiple of 8 regardless of what combination of TCP Options
3940 * are in use (always a multiple of 4 bytes) which is
3941 * important for performance reasons. For instance, if no
3942 * options are in use, then we have a 20-byte IP header and a
3943 * 20-byte TCP header. In this case, a 1500-byte MSS would
3944 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
3945 * which is not a multiple of 8. So using an MSS of 1488 in
3946 * this case results in a TCP Data Payload of 1448 bytes which
3947 * is a multiple of 8. On the other hand, if 12-byte TCP Time
3948 * Stamps have been negotiated, then an MTU of 1500 bytes
3949 * results in a TCP Data Payload of 1448 bytes which, as
3950 * above, is a multiple of 8 bytes ...
3952 for (i = 0; i < NMTUS; i++)
3953 if (adap->params.mtus[i] == 1492) {
3954 adap->params.mtus[i] = 1488;
3958 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
3959 adap->params.b_wnd);
3961 t4_init_sge_params(adap);
3962 t4_init_tp_params(adap);
3963 adap->flags |= FW_OK;
3967 * Something bad happened. If a command timed out or failed with EIO
3968 * FW does not operate within its spec or something catastrophic
3969 * happened to HW/FW, stop issuing commands.
3972 kfree(adap->sge.egr_map);
3973 kfree(adap->sge.ingr_map);
3974 kfree(adap->sge.starving_fl);
3975 kfree(adap->sge.txq_maperr);
3976 if (ret != -ETIMEDOUT && ret != -EIO)
3977 t4_fw_bye(adap, adap->mbox);
3983 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
3984 pci_channel_state_t state)
3987 struct adapter *adap = pci_get_drvdata(pdev);
3993 adap->flags &= ~FW_OK;
3994 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
3995 spin_lock(&adap->stats_lock);
3996 for_each_port(adap, i) {
3997 struct net_device *dev = adap->port[i];
3999 netif_device_detach(dev);
4000 netif_carrier_off(dev);
4002 spin_unlock(&adap->stats_lock);
4003 disable_interrupts(adap);
4004 if (adap->flags & FULL_INIT_DONE)
4007 if ((adap->flags & DEV_ENABLED)) {
4008 pci_disable_device(pdev);
4009 adap->flags &= ~DEV_ENABLED;
4011 out: return state == pci_channel_io_perm_failure ?
4012 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4015 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4018 struct fw_caps_config_cmd c;
4019 struct adapter *adap = pci_get_drvdata(pdev);
4022 pci_restore_state(pdev);
4023 pci_save_state(pdev);
4024 return PCI_ERS_RESULT_RECOVERED;
4027 if (!(adap->flags & DEV_ENABLED)) {
4028 if (pci_enable_device(pdev)) {
4029 dev_err(&pdev->dev, "Cannot reenable PCI "
4030 "device after reset\n");
4031 return PCI_ERS_RESULT_DISCONNECT;
4033 adap->flags |= DEV_ENABLED;
4036 pci_set_master(pdev);
4037 pci_restore_state(pdev);
4038 pci_save_state(pdev);
4039 pci_cleanup_aer_uncorrect_error_status(pdev);
4041 if (t4_wait_dev_ready(adap->regs) < 0)
4042 return PCI_ERS_RESULT_DISCONNECT;
4043 if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
4044 return PCI_ERS_RESULT_DISCONNECT;
4045 adap->flags |= FW_OK;
4046 if (adap_init1(adap, &c))
4047 return PCI_ERS_RESULT_DISCONNECT;
4049 for_each_port(adap, i) {
4050 struct port_info *p = adap2pinfo(adap, i);
4052 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
4055 return PCI_ERS_RESULT_DISCONNECT;
4057 p->xact_addr_filt = -1;
4060 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4061 adap->params.b_wnd);
4064 return PCI_ERS_RESULT_DISCONNECT;
4065 return PCI_ERS_RESULT_RECOVERED;
4068 static void eeh_resume(struct pci_dev *pdev)
4071 struct adapter *adap = pci_get_drvdata(pdev);
4077 for_each_port(adap, i) {
4078 struct net_device *dev = adap->port[i];
4080 if (netif_running(dev)) {
4082 cxgb_set_rxmode(dev);
4084 netif_device_attach(dev);
4089 static const struct pci_error_handlers cxgb4_eeh = {
4090 .error_detected = eeh_err_detected,
4091 .slot_reset = eeh_slot_reset,
4092 .resume = eeh_resume,
4095 static inline bool is_x_10g_port(const struct link_config *lc)
4097 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
4098 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
4101 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
4102 unsigned int us, unsigned int cnt,
4103 unsigned int size, unsigned int iqe_size)
4106 cxgb4_set_rspq_intr_params(q, us, cnt);
4107 q->iqe_len = iqe_size;
4112 * Perform default configuration of DMA queues depending on the number and type
4113 * of ports we found and the number of available CPUs. Most settings can be
4114 * modified by the admin prior to actual use.
4116 static void cfg_queues(struct adapter *adap)
4118 struct sge *s = &adap->sge;
4119 int i, n10g = 0, qidx = 0;
4120 #ifndef CONFIG_CHELSIO_T4_DCB
4125 for_each_port(adap, i)
4126 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
4127 #ifdef CONFIG_CHELSIO_T4_DCB
4128 /* For Data Center Bridging support we need to be able to support up
4129 * to 8 Traffic Priorities; each of which will be assigned to its
4130 * own TX Queue in order to prevent Head-Of-Line Blocking.
4132 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4133 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4134 MAX_ETH_QSETS, adap->params.nports * 8);
4138 for_each_port(adap, i) {
4139 struct port_info *pi = adap2pinfo(adap, i);
4141 pi->first_qset = qidx;
4145 #else /* !CONFIG_CHELSIO_T4_DCB */
4147 * We default to 1 queue per non-10G port and up to # of cores queues
4151 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
4152 if (q10g > netif_get_num_default_rss_queues())
4153 q10g = netif_get_num_default_rss_queues();
4155 for_each_port(adap, i) {
4156 struct port_info *pi = adap2pinfo(adap, i);
4158 pi->first_qset = qidx;
4159 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
4162 #endif /* !CONFIG_CHELSIO_T4_DCB */
4165 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4167 if (is_offload(adap)) {
4169 * For offload we use 1 queue/channel if all ports are up to 1G,
4170 * otherwise we divide all available queues amongst the channels
4171 * capped by the number of available cores.
4174 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
4176 s->ofldqsets = roundup(i, adap->params.nports);
4178 s->ofldqsets = adap->params.nports;
4179 /* For RDMA one Rx queue per channel suffices */
4180 s->rdmaqs = adap->params.nports;
4181 /* Try and allow at least 1 CIQ per cpu rounding down
4182 * to the number of ports, with a minimum of 1 per port.
4183 * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port.
4184 * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port.
4185 * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port.
4187 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus());
4188 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) *
4189 adap->params.nports;
4190 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports);
4193 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4194 struct sge_eth_rxq *r = &s->ethrxq[i];
4196 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
4200 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4201 s->ethtxq[i].q.size = 1024;
4203 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4204 s->ctrlq[i].q.size = 512;
4206 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
4207 s->ofldtxq[i].q.size = 1024;
4209 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
4210 struct sge_ofld_rxq *r = &s->ofldrxq[i];
4212 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
4213 r->rspq.uld = CXGB4_ULD_ISCSI;
4217 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
4218 struct sge_ofld_rxq *r = &s->rdmarxq[i];
4220 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
4221 r->rspq.uld = CXGB4_ULD_RDMA;
4225 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
4226 if (ciq_size > SGE_MAX_IQ_SIZE) {
4227 CH_WARN(adap, "CIQ size too small for available IQs\n");
4228 ciq_size = SGE_MAX_IQ_SIZE;
4231 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
4232 struct sge_ofld_rxq *r = &s->rdmaciq[i];
4234 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
4235 r->rspq.uld = CXGB4_ULD_RDMA;
4238 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4239 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
4243 * Reduce the number of Ethernet queues across all ports to at most n.
4244 * n provides at least one queue per port.
4246 static void reduce_ethqs(struct adapter *adap, int n)
4249 struct port_info *pi;
4251 while (n < adap->sge.ethqsets)
4252 for_each_port(adap, i) {
4253 pi = adap2pinfo(adap, i);
4254 if (pi->nqsets > 1) {
4256 adap->sge.ethqsets--;
4257 if (adap->sge.ethqsets <= n)
4263 for_each_port(adap, i) {
4264 pi = adap2pinfo(adap, i);
4270 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4271 #define EXTRA_VECS 2
4273 static int enable_msix(struct adapter *adap)
4276 int i, want, need, allocated;
4277 struct sge *s = &adap->sge;
4278 unsigned int nchan = adap->params.nports;
4279 struct msix_entry *entries;
4281 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1),
4286 for (i = 0; i < MAX_INGQ + 1; ++i)
4287 entries[i].entry = i;
4289 want = s->max_ethqsets + EXTRA_VECS;
4290 if (is_offload(adap)) {
4291 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
4292 /* need nchan for each possible ULD */
4293 ofld_need = 3 * nchan;
4295 #ifdef CONFIG_CHELSIO_T4_DCB
4296 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4299 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
4301 need = adap->params.nports + EXTRA_VECS + ofld_need;
4303 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4304 if (allocated < 0) {
4305 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4306 " not using MSI-X\n");
4311 /* Distribute available vectors to the various queue groups.
4312 * Every group gets its minimum requirement and NIC gets top
4313 * priority for leftovers.
4315 i = allocated - EXTRA_VECS - ofld_need;
4316 if (i < s->max_ethqsets) {
4317 s->max_ethqsets = i;
4318 if (i < s->ethqsets)
4319 reduce_ethqs(adap, i);
4321 if (is_offload(adap)) {
4322 if (allocated < want) {
4324 s->rdmaciqs = nchan;
4327 /* leftovers go to OFLD */
4328 i = allocated - EXTRA_VECS - s->max_ethqsets -
4329 s->rdmaqs - s->rdmaciqs;
4330 s->ofldqsets = (i / nchan) * nchan; /* round down */
4332 for (i = 0; i < allocated; ++i)
4333 adap->msix_info[i].vec = entries[i].vector;
4341 static int init_rss(struct adapter *adap)
4345 for_each_port(adap, i) {
4346 struct port_info *pi = adap2pinfo(adap, i);
4348 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4351 for (j = 0; j < pi->rss_size; j++)
4352 pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
4357 static void print_port_info(const struct net_device *dev)
4361 const char *spd = "";
4362 const struct port_info *pi = netdev_priv(dev);
4363 const struct adapter *adap = pi->adapter;
4365 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4367 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4369 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4372 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4373 bufp += sprintf(bufp, "100/");
4374 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4375 bufp += sprintf(bufp, "1000/");
4376 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4377 bufp += sprintf(bufp, "10G/");
4378 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4379 bufp += sprintf(bufp, "40G/");
4382 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
4384 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
4385 adap->params.vpd.id,
4386 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
4387 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
4388 (adap->flags & USING_MSIX) ? " MSI-X" :
4389 (adap->flags & USING_MSI) ? " MSI" : "");
4390 netdev_info(dev, "S/N: %s, P/N: %s\n",
4391 adap->params.vpd.sn, adap->params.vpd.pn);
4394 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
4396 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
4400 * Free the following resources:
4401 * - memory used for tables
4404 * - resources FW is holding for us
4406 static void free_some_resources(struct adapter *adapter)
4410 t4_free_mem(adapter->l2t);
4411 t4_free_mem(adapter->tids.tid_tab);
4412 kfree(adapter->sge.egr_map);
4413 kfree(adapter->sge.ingr_map);
4414 kfree(adapter->sge.starving_fl);
4415 kfree(adapter->sge.txq_maperr);
4416 disable_msi(adapter);
4418 for_each_port(adapter, i)
4419 if (adapter->port[i]) {
4420 kfree(adap2pinfo(adapter, i)->rss);
4421 free_netdev(adapter->port[i]);
4423 if (adapter->flags & FW_OK)
4424 t4_fw_bye(adapter, adapter->fn);
4427 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
4428 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
4429 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
4430 #define SEGMENT_SIZE 128
4432 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4434 int func, i, err, s_qpp, qpp, num_seg;
4435 struct port_info *pi;
4436 bool highdma = false;
4437 struct adapter *adapter = NULL;
4440 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4442 err = pci_request_regions(pdev, KBUILD_MODNAME);
4444 /* Just info, some other driver may have claimed the device. */
4445 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4449 err = pci_enable_device(pdev);
4451 dev_err(&pdev->dev, "cannot enable PCI device\n");
4452 goto out_release_regions;
4455 regs = pci_ioremap_bar(pdev, 0);
4457 dev_err(&pdev->dev, "cannot map device registers\n");
4459 goto out_disable_device;
4462 err = t4_wait_dev_ready(regs);
4464 goto out_unmap_bar0;
4466 /* We control everything through one PF */
4467 func = SOURCEPF_G(readl(regs + PL_WHOAMI_A));
4468 if (func != ent->driver_data) {
4470 pci_disable_device(pdev);
4471 pci_save_state(pdev); /* to restore SR-IOV later */
4475 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4477 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4479 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4480 "coherent allocations\n");
4481 goto out_unmap_bar0;
4484 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4486 dev_err(&pdev->dev, "no usable DMA configuration\n");
4487 goto out_unmap_bar0;
4491 pci_enable_pcie_error_reporting(pdev);
4492 enable_pcie_relaxed_ordering(pdev);
4493 pci_set_master(pdev);
4494 pci_save_state(pdev);
4496 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4499 goto out_unmap_bar0;
4502 adapter->workq = create_singlethread_workqueue("cxgb4");
4503 if (!adapter->workq) {
4505 goto out_free_adapter;
4508 /* PCI device has been enabled */
4509 adapter->flags |= DEV_ENABLED;
4511 adapter->regs = regs;
4512 adapter->pdev = pdev;
4513 adapter->pdev_dev = &pdev->dev;
4514 adapter->mbox = func;
4516 adapter->msg_enable = dflt_msg_enable;
4517 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4519 spin_lock_init(&adapter->stats_lock);
4520 spin_lock_init(&adapter->tid_release_lock);
4521 spin_lock_init(&adapter->win0_lock);
4523 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
4524 INIT_WORK(&adapter->db_full_task, process_db_full);
4525 INIT_WORK(&adapter->db_drop_task, process_db_drop);
4527 err = t4_prep_adapter(adapter);
4529 goto out_free_adapter;
4532 if (!is_t4(adapter->params.chip)) {
4533 s_qpp = (QUEUESPERPAGEPF0_S +
4534 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
4536 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4537 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
4538 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4540 /* Each segment size is 128B. Write coalescing is enabled only
4541 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4542 * queue is less no of segments that can be accommodated in
4545 if (qpp > num_seg) {
4547 "Incorrect number of egress queues per page\n");
4549 goto out_free_adapter;
4551 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4552 pci_resource_len(pdev, 2));
4553 if (!adapter->bar2) {
4554 dev_err(&pdev->dev, "cannot map device bar2 region\n");
4556 goto out_free_adapter;
4560 setup_memwin(adapter);
4561 err = adap_init0(adapter);
4562 setup_memwin_rdma(adapter);
4566 for_each_port(adapter, i) {
4567 struct net_device *netdev;
4569 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4576 SET_NETDEV_DEV(netdev, &pdev->dev);
4578 adapter->port[i] = netdev;
4579 pi = netdev_priv(netdev);
4580 pi->adapter = adapter;
4581 pi->xact_addr_filt = -1;
4583 netdev->irq = pdev->irq;
4585 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4586 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4587 NETIF_F_RXCSUM | NETIF_F_RXHASH |
4588 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
4590 netdev->hw_features |= NETIF_F_HIGHDMA;
4591 netdev->features |= netdev->hw_features;
4592 netdev->vlan_features = netdev->features & VLAN_FEAT;
4594 netdev->priv_flags |= IFF_UNICAST_FLT;
4596 netdev->netdev_ops = &cxgb4_netdev_ops;
4597 #ifdef CONFIG_CHELSIO_T4_DCB
4598 netdev->dcbnl_ops = &cxgb4_dcb_ops;
4599 cxgb4_dcb_state_init(netdev);
4601 cxgb4_set_ethtool_ops(netdev);
4604 pci_set_drvdata(pdev, adapter);
4606 if (adapter->flags & FW_OK) {
4607 err = t4_port_init(adapter, func, func, 0);
4613 * Configure queues and allocate tables now, they can be needed as
4614 * soon as the first register_netdev completes.
4616 cfg_queues(adapter);
4618 adapter->l2t = t4_init_l2t();
4619 if (!adapter->l2t) {
4620 /* We tolerate a lack of L2T, giving up some functionality */
4621 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
4622 adapter->params.offload = 0;
4625 #if IS_ENABLED(CONFIG_IPV6)
4626 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
4627 adapter->clipt_end);
4628 if (!adapter->clipt) {
4629 /* We tolerate a lack of clip_table, giving up
4630 * some functionality
4632 dev_warn(&pdev->dev,
4633 "could not allocate Clip table, continuing\n");
4634 adapter->params.offload = 0;
4637 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
4638 dev_warn(&pdev->dev, "could not allocate TID table, "
4640 adapter->params.offload = 0;
4643 /* See what interrupts we'll be using */
4644 if (msi > 1 && enable_msix(adapter) == 0)
4645 adapter->flags |= USING_MSIX;
4646 else if (msi > 0 && pci_enable_msi(pdev) == 0)
4647 adapter->flags |= USING_MSI;
4649 err = init_rss(adapter);
4654 * The card is now ready to go. If any errors occur during device
4655 * registration we do not fail the whole card but rather proceed only
4656 * with the ports we manage to register successfully. However we must
4657 * register at least one net device.
4659 for_each_port(adapter, i) {
4660 pi = adap2pinfo(adapter, i);
4661 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
4662 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
4664 err = register_netdev(adapter->port[i]);
4667 adapter->chan_map[pi->tx_chan] = i;
4668 print_port_info(adapter->port[i]);
4671 dev_err(&pdev->dev, "could not register any net devices\n");
4675 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
4679 if (cxgb4_debugfs_root) {
4680 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
4681 cxgb4_debugfs_root);
4682 setup_debugfs(adapter);
4685 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
4686 pdev->needs_freset = 1;
4688 if (is_offload(adapter))
4689 attach_ulds(adapter);
4692 #ifdef CONFIG_PCI_IOV
4693 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
4694 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
4695 dev_info(&pdev->dev,
4696 "instantiated %u virtual functions\n",
4702 free_some_resources(adapter);
4704 if (!is_t4(adapter->params.chip))
4705 iounmap(adapter->bar2);
4708 destroy_workqueue(adapter->workq);
4714 pci_disable_pcie_error_reporting(pdev);
4715 pci_disable_device(pdev);
4716 out_release_regions:
4717 pci_release_regions(pdev);
4721 static void remove_one(struct pci_dev *pdev)
4723 struct adapter *adapter = pci_get_drvdata(pdev);
4725 #ifdef CONFIG_PCI_IOV
4726 pci_disable_sriov(pdev);
4733 /* Tear down per-adapter Work Queue first since it can contain
4734 * references to our adapter data structure.
4736 destroy_workqueue(adapter->workq);
4738 if (is_offload(adapter))
4739 detach_ulds(adapter);
4741 disable_interrupts(adapter);
4743 for_each_port(adapter, i)
4744 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
4745 unregister_netdev(adapter->port[i]);
4747 debugfs_remove_recursive(adapter->debugfs_root);
4749 /* If we allocated filters, free up state associated with any
4752 if (adapter->tids.ftid_tab) {
4753 struct filter_entry *f = &adapter->tids.ftid_tab[0];
4754 for (i = 0; i < (adapter->tids.nftids +
4755 adapter->tids.nsftids); i++, f++)
4757 clear_filter(adapter, f);
4760 if (adapter->flags & FULL_INIT_DONE)
4763 free_some_resources(adapter);
4764 #if IS_ENABLED(CONFIG_IPV6)
4765 t4_cleanup_clip_tbl(adapter);
4767 iounmap(adapter->regs);
4768 if (!is_t4(adapter->params.chip))
4769 iounmap(adapter->bar2);
4770 pci_disable_pcie_error_reporting(pdev);
4771 if ((adapter->flags & DEV_ENABLED)) {
4772 pci_disable_device(pdev);
4773 adapter->flags &= ~DEV_ENABLED;
4775 pci_release_regions(pdev);
4779 pci_release_regions(pdev);
4782 static struct pci_driver cxgb4_driver = {
4783 .name = KBUILD_MODNAME,
4784 .id_table = cxgb4_pci_tbl,
4786 .remove = remove_one,
4787 .shutdown = remove_one,
4788 .err_handler = &cxgb4_eeh,
4791 static int __init cxgb4_init_module(void)
4795 /* Debugfs support is optional, just warn if this fails */
4796 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
4797 if (!cxgb4_debugfs_root)
4798 pr_warn("could not create debugfs entry, continuing\n");
4800 ret = pci_register_driver(&cxgb4_driver);
4802 debugfs_remove(cxgb4_debugfs_root);
4804 #if IS_ENABLED(CONFIG_IPV6)
4805 if (!inet6addr_registered) {
4806 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
4807 inet6addr_registered = true;
4814 static void __exit cxgb4_cleanup_module(void)
4816 #if IS_ENABLED(CONFIG_IPV6)
4817 if (inet6addr_registered) {
4818 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
4819 inet6addr_registered = false;
4822 pci_unregister_driver(&cxgb4_driver);
4823 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
4826 module_init(cxgb4_init_module);
4827 module_exit(cxgb4_cleanup_module);