1 /**********************************************************************
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2015 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * This file may also be available under a different license from Cavium.
20 * Contact Cavium, Inc. for more information
21 **********************************************************************/
23 /*! \file liquidio_common.h
24 * \brief Common: Structures and macros used in PCI-NIC package by core and
28 #ifndef __LIQUIDIO_COMMON_H__
29 #define __LIQUIDIO_COMMON_H__
31 #include "octeon_config.h"
33 #define LIQUIDIO_VERSION "1.1.9"
34 #define LIQUIDIO_MAJOR_VERSION 1
35 #define LIQUIDIO_MINOR_VERSION 1
36 #define LIQUIDIO_MICRO_VERSION 9
39 /** Tag types used by Octeon cores in its work. */
40 enum octeon_tag_type {
47 /* pre-defined host->NIC tag values */
48 #define LIO_CONTROL (0x11111110)
49 #define LIO_DATA(i) (0x11111111 + (i))
51 /* Opcodes used by host driver/apps to perform operations on the core.
52 * These are used to identify the major subsystem that the operation
55 #define OPCODE_CORE 0 /* used for generic core operations */
56 #define OPCODE_NIC 1 /* used for NIC operations */
57 #define OPCODE_LAST OPCODE_NIC
59 /* Subcodes are used by host driver/apps to identify the sub-operation
60 * for the core. They only need to by unique for a given subsystem.
62 #define OPCODE_SUBCODE(op, sub) (((op & 0x0f) << 8) | ((sub) & 0x7f))
64 /** OPCODE_CORE subcodes. For future use. */
66 /** OPCODE_NIC subcodes */
68 /* This subcode is sent by core PCI driver to indicate cores are ready. */
69 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01
70 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */
71 #define OPCODE_NIC_CMD 0x03
72 #define OPCODE_NIC_INFO 0x04
73 #define OPCODE_NIC_PORT_STATS 0x05
74 #define OPCODE_NIC_MDIO45 0x06
75 #define OPCODE_NIC_TIMESTAMP 0x07
76 #define OPCODE_NIC_INTRMOD_CFG 0x08
77 #define OPCODE_NIC_IF_CFG 0x09
79 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5
81 #define OPCODE_SLOW_PATH(rh) \
82 (OPCODE_SUBCODE(rh->r.opcode, rh->r.subcode) != \
83 OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA))
85 /* Application codes advertised by the core driver initialization packet. */
86 #define CVM_DRV_APP_START 0x0
87 #define CVM_DRV_NO_APP 0
88 #define CVM_DRV_APP_COUNT 0x2
89 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0)
90 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1)
91 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2)
92 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1)
94 /* Macro to increment index.
95 * Index is incremented by count; if the sum exceeds
96 * max, index is wrapped-around to the start.
98 #define INCR_INDEX(index, count, max) \
100 if (((index) + (count)) >= (max)) \
101 index = ((index) + (count)) - (max); \
106 #define INCR_INDEX_BY1(index, max) \
108 if ((++(index)) == (max)) \
112 #define DECR_INDEX(index, count, max) \
114 if ((count) > (index)) \
115 index = ((max) - ((count - index))); \
120 #define OCT_BOARD_NAME 32
121 #define OCT_SERIAL_LEN 64
123 /* Structure used by core driver to send indication that the Octeon
124 * application is ready.
126 struct octeon_core_setup {
129 char boardname[OCT_BOARD_NAME];
131 char board_serial_number[OCT_SERIAL_LEN];
139 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/
141 /* The Scatter-Gather List Entry. The scatter or gather component used with
142 * a Octeon input instruction has this format.
144 struct octeon_sg_entry {
145 /** The first 64 bit gives the size of data in each dptr.*/
151 /** The 4 dptr pointers for this entry. */
156 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry))
158 /* \brief Add size to gather list
159 * @param sg_entry scatter/gather entry
160 * @param size size to add
161 * @param pos position to add it.
163 static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
167 #ifdef __BIG_ENDIAN_BITFIELD
168 sg_entry->u.size[pos] = size;
170 sg_entry->u.size[3 - pos] = size;
174 /*------------------------- End Scatter/Gather ---------------------------*/
176 #define OCTNET_FRM_PTP_HEADER_SIZE 8
177 #define OCTNET_FRM_HEADER_SIZE 30 /* PTP timestamp + VLAN + Ethernet */
179 #define OCTNET_MIN_FRM_SIZE (64 + OCTNET_FRM_PTP_HEADER_SIZE)
180 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE)
182 #define OCTNET_DEFAULT_FRM_SIZE (1500 + OCTNET_FRM_HEADER_SIZE)
184 /** NIC Commands are sent using this Octeon Input Queue */
185 #define OCTNET_CMD_Q 0
187 /* NIC Command types */
188 #define OCTNET_CMD_CHANGE_MTU 0x1
189 #define OCTNET_CMD_CHANGE_MACADDR 0x2
190 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3
191 #define OCTNET_CMD_RX_CTL 0x4
193 #define OCTNET_CMD_SET_MULTI_LIST 0x5
194 #define OCTNET_CMD_CLEAR_STATS 0x6
196 /* command for setting the speed, duplex & autoneg */
197 #define OCTNET_CMD_SET_SETTINGS 0x7
198 #define OCTNET_CMD_SET_FLOW_CTL 0x8
200 #define OCTNET_CMD_MDIO_READ_WRITE 0x9
201 #define OCTNET_CMD_GPIO_ACCESS 0xA
202 #define OCTNET_CMD_LRO_ENABLE 0xB
203 #define OCTNET_CMD_LRO_DISABLE 0xC
204 #define OCTNET_CMD_SET_RSS 0xD
205 #define OCTNET_CMD_WRITE_SA 0xE
206 #define OCTNET_CMD_DELETE_SA 0xF
207 #define OCTNET_CMD_UPDATE_SA 0x12
209 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
210 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
211 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
212 #define OCTNET_CMD_VERBOSE_ENABLE 0x14
213 #define OCTNET_CMD_VERBOSE_DISABLE 0x15
215 /* RX(packets coming from wire) Checksum verification flags */
217 #define CNNIC_L4SUM_VERIFIED 0x1
218 #define CNNIC_IPSUM_VERIFIED 0x2
219 #define CNNIC_TUN_CSUM_VERIFIED 0x4
220 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
222 /*LROIPV4 and LROIPV6 Flags*/
223 #define OCTNIC_LROIPV4 0x1
224 #define OCTNIC_LROIPV6 0x2
226 /* Interface flags communicated between host driver and core app. */
227 enum octnet_ifflags {
228 OCTNET_IFFLAG_PROMISC = 0x01,
229 OCTNET_IFFLAG_ALLMULTI = 0x02,
230 OCTNET_IFFLAG_MULTICAST = 0x04,
231 OCTNET_IFFLAG_BROADCAST = 0x08,
232 OCTNET_IFFLAG_UNICAST = 0x10
256 #ifdef __BIG_ENDIAN_BITFIELD
259 u64 more:6; /* How many udd words follow the command */
284 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd))
286 /** Instruction Header */
287 struct octeon_instr_ih {
288 #ifdef __BIG_ENDIAN_BITFIELD
289 /** Raw mode indicator 1 = RAW */
292 /** Gather indicator 1=gather*/
295 /** Data length OR no. of entries in gather list */
298 /** Front Data size */
301 /** Packet Order / Work Unit selection (1 of 8)*/
304 /** Core group selection (1 of 16) */
307 /** Short Raw Packet Indicator 1=short raw pkt */
322 /** Short Raw Packet Indicator 1=short raw pkt */
325 /** Core group selection (1 of 16) */
328 /** Packet Order / Work Unit selection (1 of 8)*/
331 /** Front Data size */
334 /** Data length OR no. of entries in gather list */
337 /** Gather indicator 1=gather*/
340 /** Raw mode indicator 1 = RAW */
345 /** Input Request Header */
346 struct octeon_instr_irh {
347 #ifdef __BIG_ENDIAN_BITFIELD
354 u64 ossp:32; /* opcode/subcode specific parameters */
356 u64 ossp:32; /* opcode/subcode specific parameters */
366 /** Return Data Parameters */
367 struct octeon_instr_rdp {
368 #ifdef __BIG_ENDIAN_BITFIELD
379 /** Receive Header */
381 #ifdef __BIG_ENDIAN_BITFIELD
386 u64 len:3; /** additional 64-bit words */
387 u64 rid:13; /** request id in response to pkt sent by host */
389 u64 ossp:32; /** opcode/subcode specific parameters */
394 u64 len:3; /** additional 64-bit words */
395 u64 rid:13; /** request id in response to pkt sent by host */
398 u64 csum_verified:3; /** checksum verified. */
399 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */
404 u64 len:3; /** additional 64-bit words */
405 u64 rid:13; /** request id in response to pkt sent by host */
414 u64 len:3; /** additional 64-bit words */
423 u64 ossp:32; /** opcode/subcode specific parameters */
425 u64 rid:13; /** req id in response to pkt sent by host */
426 u64 len:3; /** additional 64-bit words */
431 u64 has_hwtstamp:1; /** 1 = has hwtstamp */
432 u64 csum_verified:3; /** checksum verified. */
435 u64 rid:13; /** req id in response to pkt sent by host */
436 u64 len:3; /** additional 64-bit words */
446 u64 len:3; /** additional 64-bit words */
455 u64 len:3; /** additional 64-bit words */
462 #define OCT_RH_SIZE (sizeof(union octeon_rh))
464 #define OCT_PKT_PARAM_IPV4OPTS 1
465 #define OCT_PKT_PARAM_IPV6EXTHDR 2
467 union octnic_packet_params {
470 #ifdef __BIG_ENDIAN_BITFIELD
474 u32 ipv4opts_ipv6exthdr:2;
484 u32 ipv4opts_ipv6exthdr:2;
492 /** Status of a RGMII Link on Octeon as seen by core driver. */
493 union oct_link_status {
497 #ifdef __BIG_ENDIAN_BITFIELD
519 /** Information for a OCTEON ethernet interface shared between core & host. */
520 struct oct_link_info {
521 union oct_link_status link;
524 #ifdef __BIG_ENDIAN_BITFIELD
538 u8 txpciq[MAX_IOQS_PER_NICIF];
539 u8 rxpciq[MAX_IOQS_PER_NICIF];
542 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info))
544 struct liquidio_if_cfg_info {
546 u64 iqmask; /** mask for IQs enabled for the port */
547 u64 oqmask; /** mask for OQs enabled for the port */
548 struct oct_link_info linfo; /** initial link information */
551 /** Stats for each NIC port in RX direction. */
552 struct nic_rx_stats {
553 /* link-level stats */
560 u64 fifo_err; /* Accounts for over/under-run of buffers */
573 u64 fw_lro_pkts; /* Number of packets that are LROed */
574 u64 fw_lro_octs; /* Number of octets that are LROed */
575 u64 fw_total_lro; /* Number of LRO packets formed */
576 u64 fw_lro_aborts; /* Number of times lRO of packet aborted */
577 /* intrmod: packet forward rate */
581 /** Stats for each NIC port in RX direction. */
582 struct nic_tx_stats {
583 /* link-level stats */
585 u64 total_bytes_sent;
589 u64 one_collision_sent; /* Packets sent after one collision*/
590 u64 multi_collision_sent; /* Packets sent after multiple collision*/
591 u64 max_collision_fail; /* Packets not sent due to max collisions */
592 u64 max_deferral_fail; /* Packets not sent due to max deferrals */
593 u64 fifo_err; /* Accounts for over/under-run of buffers */
595 u64 total_collisions; /* Total number of collisions detected */
605 struct oct_link_stats {
606 struct nic_rx_stats fromwire;
607 struct nic_tx_stats fromhost;
611 #define LIO68XX_LED_CTRL_ADDR 0x3501
612 #define LIO68XX_LED_CTRL_CFGON 0x1f
613 #define LIO68XX_LED_CTRL_CFGOFF 0x100
614 #define LIO68XX_LED_BEACON_ADDR 0x3508
615 #define LIO68XX_LED_BEACON_CFGON 0x47fd
616 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc
617 #define VITESSE_PHY_GPIO_DRIVEON 0x1
618 #define VITESSE_PHY_GPIO_CFG 0x8
619 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4
620 #define VITESSE_PHY_GPIO_HIGH 0x2
621 #define VITESSE_PHY_GPIO_LOW 0x3
623 struct oct_mdio_cmd {
631 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats))
633 #define LIO_INTRMOD_CHECK_INTERVAL 1
634 #define LIO_INTRMOD_MAXPKT_RATETHR 196608 /* max pkt rate threshold */
635 #define LIO_INTRMOD_MINPKT_RATETHR 9216 /* min pkt rate threshold */
636 #define LIO_INTRMOD_MAXCNT_TRIGGER 384 /* max pkts to trigger interrupt */
637 #define LIO_INTRMOD_MINCNT_TRIGGER 1 /* min pkts to trigger interrupt */
638 #define LIO_INTRMOD_MAXTMR_TRIGGER 128 /* max time to trigger interrupt */
639 #define LIO_INTRMOD_MINTMR_TRIGGER 32 /* min time to trigger interrupt */
641 struct oct_intrmod_cfg {
643 u64 intrmod_check_intrvl;
644 u64 intrmod_maxpkt_ratethr;
645 u64 intrmod_minpkt_ratethr;
646 u64 intrmod_maxcnt_trigger;
647 u64 intrmod_maxtmr_trigger;
648 u64 intrmod_mincnt_trigger;
649 u64 intrmod_mintmr_trigger;
652 #define BASE_QUEUE_NOT_REQUESTED 65535
654 union oct_nic_if_cfg {
657 #ifdef __BIG_ENDIAN_BITFIELD