Add the rt linux 4.1.3-rt3 as base
[kvmfornfv.git] / kernel / drivers / net / ethernet / brocade / bna / bna_types.h
1 /*
2  * Linux network driver for QLogic BR-series Converged Network Adapter.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms of the GNU General Public License (GPL) Version 2 as
6  * published by the Free Software Foundation
7  *
8  * This program is distributed in the hope that it will be useful, but
9  * WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
11  * General Public License for more details.
12  */
13 /*
14  * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
15  * Copyright (c) 2014-2015 QLogic Corporation
16  * All rights reserved
17  * www.qlogic.com
18  */
19 #ifndef __BNA_TYPES_H__
20 #define __BNA_TYPES_H__
21
22 #include "cna.h"
23 #include "bna_hw_defs.h"
24 #include "bfa_cee.h"
25 #include "bfa_msgq.h"
26
27 /* Forward declarations */
28
29 struct bna_mcam_handle;
30 struct bna_txq;
31 struct bna_tx;
32 struct bna_rxq;
33 struct bna_cq;
34 struct bna_rx;
35 struct bna_rxf;
36 struct bna_enet;
37 struct bna;
38 struct bnad;
39
40 /* Enums, primitive data types */
41
42 enum bna_status {
43         BNA_STATUS_T_DISABLED   = 0,
44         BNA_STATUS_T_ENABLED    = 1
45 };
46
47 enum bna_cleanup_type {
48         BNA_HARD_CLEANUP        = 0,
49         BNA_SOFT_CLEANUP        = 1
50 };
51
52 enum bna_cb_status {
53         BNA_CB_SUCCESS          = 0,
54         BNA_CB_FAIL             = 1,
55         BNA_CB_INTERRUPT        = 2,
56         BNA_CB_BUSY             = 3,
57         BNA_CB_INVALID_MAC      = 4,
58         BNA_CB_MCAST_LIST_FULL  = 5,
59         BNA_CB_UCAST_CAM_FULL   = 6,
60         BNA_CB_WAITING          = 7,
61         BNA_CB_NOT_EXEC         = 8
62 };
63
64 enum bna_res_type {
65         BNA_RES_T_MEM           = 1,
66         BNA_RES_T_INTR          = 2
67 };
68
69 enum bna_mem_type {
70         BNA_MEM_T_KVA           = 1,
71         BNA_MEM_T_DMA           = 2
72 };
73
74 enum bna_intr_type {
75         BNA_INTR_T_INTX         = 1,
76         BNA_INTR_T_MSIX         = 2
77 };
78
79 enum bna_res_req_type {
80         BNA_RES_MEM_T_COM               = 0,
81         BNA_RES_MEM_T_ATTR              = 1,
82         BNA_RES_MEM_T_FWTRC             = 2,
83         BNA_RES_MEM_T_STATS             = 3,
84         BNA_RES_T_MAX
85 };
86
87 enum bna_mod_res_req_type {
88         BNA_MOD_RES_MEM_T_TX_ARRAY      = 0,
89         BNA_MOD_RES_MEM_T_TXQ_ARRAY     = 1,
90         BNA_MOD_RES_MEM_T_RX_ARRAY      = 2,
91         BNA_MOD_RES_MEM_T_RXP_ARRAY     = 3,
92         BNA_MOD_RES_MEM_T_RXQ_ARRAY     = 4,
93         BNA_MOD_RES_MEM_T_UCMAC_ARRAY   = 5,
94         BNA_MOD_RES_MEM_T_MCMAC_ARRAY   = 6,
95         BNA_MOD_RES_MEM_T_MCHANDLE_ARRAY = 7,
96         BNA_MOD_RES_T_MAX
97 };
98
99 enum bna_tx_res_req_type {
100         BNA_TX_RES_MEM_T_TCB    = 0,
101         BNA_TX_RES_MEM_T_UNMAPQ = 1,
102         BNA_TX_RES_MEM_T_QPT    = 2,
103         BNA_TX_RES_MEM_T_SWQPT  = 3,
104         BNA_TX_RES_MEM_T_PAGE   = 4,
105         BNA_TX_RES_MEM_T_IBIDX  = 5,
106         BNA_TX_RES_INTR_T_TXCMPL = 6,
107         BNA_TX_RES_T_MAX,
108 };
109
110 enum bna_rx_mem_type {
111         BNA_RX_RES_MEM_T_CCB            = 0,    /* CQ context */
112         BNA_RX_RES_MEM_T_RCB            = 1,    /* CQ context */
113         BNA_RX_RES_MEM_T_UNMAPHQ        = 2,
114         BNA_RX_RES_MEM_T_UNMAPDQ        = 3,
115         BNA_RX_RES_MEM_T_CQPT           = 4,
116         BNA_RX_RES_MEM_T_CSWQPT         = 5,
117         BNA_RX_RES_MEM_T_CQPT_PAGE      = 6,
118         BNA_RX_RES_MEM_T_HQPT           = 7,
119         BNA_RX_RES_MEM_T_DQPT           = 8,
120         BNA_RX_RES_MEM_T_HSWQPT         = 9,
121         BNA_RX_RES_MEM_T_DSWQPT         = 10,
122         BNA_RX_RES_MEM_T_DPAGE          = 11,
123         BNA_RX_RES_MEM_T_HPAGE          = 12,
124         BNA_RX_RES_MEM_T_IBIDX          = 13,
125         BNA_RX_RES_MEM_T_RIT            = 14,
126         BNA_RX_RES_T_INTR               = 15,
127         BNA_RX_RES_T_MAX                = 16
128 };
129
130 enum bna_tx_type {
131         BNA_TX_T_REGULAR        = 0,
132         BNA_TX_T_LOOPBACK       = 1,
133 };
134
135 enum bna_tx_flags {
136         BNA_TX_F_ENET_STARTED   = 1,
137         BNA_TX_F_ENABLED        = 2,
138         BNA_TX_F_PRIO_CHANGED   = 4,
139         BNA_TX_F_BW_UPDATED     = 8,
140 };
141
142 enum bna_tx_mod_flags {
143         BNA_TX_MOD_F_ENET_STARTED       = 1,
144         BNA_TX_MOD_F_ENET_LOOPBACK      = 2,
145 };
146
147 enum bna_rx_type {
148         BNA_RX_T_REGULAR        = 0,
149         BNA_RX_T_LOOPBACK       = 1,
150 };
151
152 enum bna_rxp_type {
153         BNA_RXP_SINGLE          = 1,
154         BNA_RXP_SLR             = 2,
155         BNA_RXP_HDS             = 3
156 };
157
158 enum bna_rxmode {
159         BNA_RXMODE_PROMISC      = 1,
160         BNA_RXMODE_DEFAULT      = 2,
161         BNA_RXMODE_ALLMULTI     = 4
162 };
163
164 enum bna_rx_event {
165         RX_E_START                      = 1,
166         RX_E_STOP                       = 2,
167         RX_E_FAIL                       = 3,
168         RX_E_STARTED                    = 4,
169         RX_E_STOPPED                    = 5,
170         RX_E_RXF_STARTED                = 6,
171         RX_E_RXF_STOPPED                = 7,
172         RX_E_CLEANUP_DONE               = 8,
173 };
174
175 enum bna_rx_flags {
176         BNA_RX_F_ENET_STARTED   = 1,
177         BNA_RX_F_ENABLED        = 2,
178 };
179
180 enum bna_rx_mod_flags {
181         BNA_RX_MOD_F_ENET_STARTED       = 1,
182         BNA_RX_MOD_F_ENET_LOOPBACK      = 2,
183 };
184
185 enum bna_rxf_flags {
186         BNA_RXF_F_PAUSED                = 1,
187 };
188
189 enum bna_rxf_event {
190         RXF_E_START                     = 1,
191         RXF_E_STOP                      = 2,
192         RXF_E_FAIL                      = 3,
193         RXF_E_CONFIG                    = 4,
194         RXF_E_PAUSE                     = 5,
195         RXF_E_RESUME                    = 6,
196         RXF_E_FW_RESP                   = 7,
197 };
198
199 enum bna_enet_type {
200         BNA_ENET_T_REGULAR              = 0,
201         BNA_ENET_T_LOOPBACK_INTERNAL    = 1,
202         BNA_ENET_T_LOOPBACK_EXTERNAL    = 2,
203 };
204
205 enum bna_link_status {
206         BNA_LINK_DOWN           = 0,
207         BNA_LINK_UP             = 1,
208         BNA_CEE_UP              = 2
209 };
210
211 enum bna_ethport_flags {
212         BNA_ETHPORT_F_ADMIN_UP          = 1,
213         BNA_ETHPORT_F_PORT_ENABLED      = 2,
214         BNA_ETHPORT_F_RX_STARTED        = 4,
215 };
216
217 enum bna_enet_flags {
218         BNA_ENET_F_IOCETH_READY         = 1,
219         BNA_ENET_F_ENABLED              = 2,
220         BNA_ENET_F_PAUSE_CHANGED        = 4,
221         BNA_ENET_F_MTU_CHANGED          = 8
222 };
223
224 enum bna_rss_flags {
225         BNA_RSS_F_RIT_PENDING           = 1,
226         BNA_RSS_F_CFG_PENDING           = 2,
227         BNA_RSS_F_STATUS_PENDING        = 4,
228 };
229
230 enum bna_mod_flags {
231         BNA_MOD_F_INIT_DONE             = 1,
232 };
233
234 enum bna_pkt_rates {
235         BNA_PKT_RATE_10K                = 10000,
236         BNA_PKT_RATE_20K                = 20000,
237         BNA_PKT_RATE_30K                = 30000,
238         BNA_PKT_RATE_40K                = 40000,
239         BNA_PKT_RATE_50K                = 50000,
240         BNA_PKT_RATE_60K                = 60000,
241         BNA_PKT_RATE_70K                = 70000,
242         BNA_PKT_RATE_80K                = 80000,
243 };
244
245 enum bna_dim_load_types {
246         BNA_LOAD_T_HIGH_4               = 0, /* 80K <= r */
247         BNA_LOAD_T_HIGH_3               = 1, /* 60K <= r < 80K */
248         BNA_LOAD_T_HIGH_2               = 2, /* 50K <= r < 60K */
249         BNA_LOAD_T_HIGH_1               = 3, /* 40K <= r < 50K */
250         BNA_LOAD_T_LOW_1                = 4, /* 30K <= r < 40K */
251         BNA_LOAD_T_LOW_2                = 5, /* 20K <= r < 30K */
252         BNA_LOAD_T_LOW_3                = 6, /* 10K <= r < 20K */
253         BNA_LOAD_T_LOW_4                = 7, /* r < 10K */
254         BNA_LOAD_T_MAX                  = 8
255 };
256
257 enum bna_dim_bias_types {
258         BNA_BIAS_T_SMALL                = 0, /* small pkts > (large pkts * 2) */
259         BNA_BIAS_T_LARGE                = 1, /* Not BNA_BIAS_T_SMALL */
260         BNA_BIAS_T_MAX                  = 2
261 };
262
263 #define BNA_MAX_NAME_SIZE       64
264 struct bna_ident {
265         int                     id;
266         char                    name[BNA_MAX_NAME_SIZE];
267 };
268
269 struct bna_mac {
270         /* This should be the first one */
271         struct list_head                        qe;
272         u8                      addr[ETH_ALEN];
273         struct bna_mcam_handle *handle;
274 };
275
276 struct bna_mem_descr {
277         u32             len;
278         void            *kva;
279         struct bna_dma_addr dma;
280 };
281
282 struct bna_mem_info {
283         enum bna_mem_type mem_type;
284         u32             len;
285         u32             num;
286         u32             align_sz; /* 0/1 = no alignment */
287         struct bna_mem_descr *mdl;
288         void                    *cookie; /* For bnad to unmap dma later */
289 };
290
291 struct bna_intr_descr {
292         int                     vector;
293 };
294
295 struct bna_intr_info {
296         enum bna_intr_type intr_type;
297         int                     num;
298         struct bna_intr_descr *idl;
299 };
300
301 union bna_res_u {
302         struct bna_mem_info mem_info;
303         struct bna_intr_info intr_info;
304 };
305
306 struct bna_res_info {
307         enum bna_res_type res_type;
308         union bna_res_u         res_u;
309 };
310
311 /* HW QPT */
312 struct bna_qpt {
313         struct bna_dma_addr hw_qpt_ptr;
314         void            *kv_qpt_ptr;
315         u32             page_count;
316         u32             page_size;
317 };
318
319 struct bna_attr {
320         bool                    fw_query_complete;
321         int                     num_txq;
322         int                     num_rxp;
323         int                     num_ucmac;
324         int                     num_mcmac;
325         int                     max_rit_size;
326 };
327
328 /* IOCEth */
329
330 struct bna_ioceth {
331         bfa_fsm_t               fsm;
332         struct bfa_ioc ioc;
333
334         struct bna_attr attr;
335         struct bfa_msgq_cmd_entry msgq_cmd;
336         struct bfi_enet_attr_req attr_req;
337
338         void (*stop_cbfn)(struct bnad *bnad);
339         struct bnad *stop_cbarg;
340
341         struct bna *bna;
342 };
343
344 /* Enet */
345
346 /* Pause configuration */
347 struct bna_pause_config {
348         enum bna_status tx_pause;
349         enum bna_status rx_pause;
350 };
351
352 struct bna_enet {
353         bfa_fsm_t               fsm;
354         enum bna_enet_flags flags;
355
356         enum bna_enet_type type;
357
358         struct bna_pause_config pause_config;
359         int                     mtu;
360
361         /* Callback for bna_enet_disable(), enet_stop() */
362         void (*stop_cbfn)(void *);
363         void                    *stop_cbarg;
364
365         /* Callback for bna_enet_pause_config() */
366         void (*pause_cbfn)(struct bnad *);
367
368         /* Callback for bna_enet_mtu_set() */
369         void (*mtu_cbfn)(struct bnad *);
370
371         struct bfa_wc           chld_stop_wc;
372
373         struct bfa_msgq_cmd_entry msgq_cmd;
374         struct bfi_enet_set_pause_req pause_req;
375
376         struct bna *bna;
377 };
378
379 /* Ethport */
380
381 struct bna_ethport {
382         bfa_fsm_t               fsm;
383         enum bna_ethport_flags flags;
384
385         enum bna_link_status link_status;
386
387         int                     rx_started_count;
388
389         void (*stop_cbfn)(struct bna_enet *);
390
391         void (*adminup_cbfn)(struct bnad *, enum bna_cb_status);
392
393         void (*link_cbfn)(struct bnad *, enum bna_link_status);
394
395         struct bfa_msgq_cmd_entry msgq_cmd;
396         union {
397                 struct bfi_enet_enable_req admin_req;
398                 struct bfi_enet_diag_lb_req lpbk_req;
399         } bfi_enet_cmd;
400
401         struct bna *bna;
402 };
403
404 /* Interrupt Block */
405
406 /* Doorbell structure */
407 struct bna_ib_dbell {
408         void __iomem   *doorbell_addr;
409         u32             doorbell_ack;
410 };
411
412 /* IB structure */
413 struct bna_ib {
414         struct bna_dma_addr ib_seg_host_addr;
415         void            *ib_seg_host_addr_kva;
416
417         struct bna_ib_dbell door_bell;
418
419         enum bna_intr_type      intr_type;
420         int                     intr_vector;
421
422         u8                      coalescing_timeo;    /* Unit is 5usec. */
423
424         int                     interpkt_count;
425         int                     interpkt_timeo;
426 };
427
428 /* Tx object */
429
430 /* Tx datapath control structure */
431 #define BNA_Q_NAME_SIZE         16
432 struct bna_tcb {
433         /* Fast path */
434         void                    **sw_qpt;
435         void                    *sw_q;
436         void                    *unmap_q;
437         u32             producer_index;
438         u32             consumer_index;
439         volatile u32    *hw_consumer_index;
440         u32             q_depth;
441         void __iomem   *q_dbell;
442         struct bna_ib_dbell *i_dbell;
443         /* Control path */
444         struct bna_txq *txq;
445         struct bnad *bnad;
446         void                    *priv; /* BNAD's cookie */
447         enum bna_intr_type intr_type;
448         int                     intr_vector;
449         u8                      priority; /* Current priority */
450         unsigned long           flags; /* Used by bnad as required */
451         int                     id;
452         char                    name[BNA_Q_NAME_SIZE];
453 };
454
455 /* TxQ QPT and configuration */
456 struct bna_txq {
457         /* This should be the first one */
458         struct list_head                        qe;
459
460         u8                      priority;
461
462         struct bna_qpt qpt;
463         struct bna_tcb *tcb;
464         struct bna_ib ib;
465
466         struct bna_tx *tx;
467
468         int                     hw_id;
469
470         u64             tx_packets;
471         u64             tx_bytes;
472 };
473
474 /* Tx object */
475 struct bna_tx {
476         /* This should be the first one */
477         struct list_head                        qe;
478         int                     rid;
479         int                     hw_id;
480
481         bfa_fsm_t               fsm;
482         enum bna_tx_flags flags;
483
484         enum bna_tx_type type;
485         int                     num_txq;
486
487         struct list_head                        txq_q;
488         u16                     txf_vlan_id;
489
490         /* Tx event handlers */
491         void (*tcb_setup_cbfn)(struct bnad *, struct bna_tcb *);
492         void (*tcb_destroy_cbfn)(struct bnad *, struct bna_tcb *);
493         void (*tx_stall_cbfn)(struct bnad *, struct bna_tx *);
494         void (*tx_resume_cbfn)(struct bnad *, struct bna_tx *);
495         void (*tx_cleanup_cbfn)(struct bnad *, struct bna_tx *);
496
497         /* callback for bna_tx_disable(), bna_tx_stop() */
498         void (*stop_cbfn)(void *arg, struct bna_tx *tx);
499         void                    *stop_cbarg;
500
501         /* callback for bna_tx_prio_set() */
502         void (*prio_change_cbfn)(struct bnad *bnad, struct bna_tx *tx);
503
504         struct bfa_msgq_cmd_entry msgq_cmd;
505         union {
506                 struct bfi_enet_tx_cfg_req      cfg_req;
507                 struct bfi_enet_req             req;
508                 struct bfi_enet_tx_cfg_rsp      cfg_rsp;
509         } bfi_enet_cmd;
510
511         struct bna *bna;
512         void                    *priv;  /* bnad's cookie */
513 };
514
515 /* Tx object configuration used during creation */
516 struct bna_tx_config {
517         int                     num_txq;
518         int                     txq_depth;
519         int                     coalescing_timeo;
520         enum bna_tx_type tx_type;
521 };
522
523 struct bna_tx_event_cbfn {
524         /* Optional */
525         void (*tcb_setup_cbfn)(struct bnad *, struct bna_tcb *);
526         void (*tcb_destroy_cbfn)(struct bnad *, struct bna_tcb *);
527         /* Mandatory */
528         void (*tx_stall_cbfn)(struct bnad *, struct bna_tx *);
529         void (*tx_resume_cbfn)(struct bnad *, struct bna_tx *);
530         void (*tx_cleanup_cbfn)(struct bnad *, struct bna_tx *);
531 };
532
533 /* Tx module - keeps track of free, active tx objects */
534 struct bna_tx_mod {
535         struct bna_tx *tx;              /* BFI_MAX_TXQ entries */
536         struct bna_txq *txq;            /* BFI_MAX_TXQ entries */
537
538         struct list_head                        tx_free_q;
539         struct list_head                        tx_active_q;
540
541         struct list_head                        txq_free_q;
542
543         /* callback for bna_tx_mod_stop() */
544         void (*stop_cbfn)(struct bna_enet *enet);
545
546         struct bfa_wc           tx_stop_wc;
547
548         enum bna_tx_mod_flags flags;
549
550         u8                      prio_map;
551         int                     default_prio;
552         int                     iscsi_over_cee;
553         int                     iscsi_prio;
554         int                     prio_reconfigured;
555
556         u32                     rid_mask;
557
558         struct bna *bna;
559 };
560
561 /* Rx object */
562
563 /* Rx datapath control structure */
564 struct bna_rcb {
565         /* Fast path */
566         void                    **sw_qpt;
567         void                    *sw_q;
568         void                    *unmap_q;
569         u32             producer_index;
570         u32             consumer_index;
571         u32             q_depth;
572         void __iomem   *q_dbell;
573         /* Control path */
574         struct bna_rxq *rxq;
575         struct bna_ccb *ccb;
576         struct bnad *bnad;
577         void                    *priv; /* BNAD's cookie */
578         unsigned long           flags;
579         int                     id;
580 };
581
582 /* RxQ structure - QPT, configuration */
583 struct bna_rxq {
584         struct list_head                        qe;
585
586         int                     buffer_size;
587         int                     q_depth;
588         u32                     num_vecs;
589         enum bna_status         multi_buffer;
590
591         struct bna_qpt qpt;
592         struct bna_rcb *rcb;
593
594         struct bna_rxp *rxp;
595         struct bna_rx *rx;
596
597         int                     hw_id;
598
599         u64             rx_packets;
600         u64             rx_bytes;
601         u64             rx_packets_with_error;
602         u64             rxbuf_alloc_failed;
603 };
604
605 /* RxQ pair */
606 union bna_rxq_u {
607         struct {
608                 struct bna_rxq *hdr;
609                 struct bna_rxq *data;
610         } hds;
611         struct {
612                 struct bna_rxq *small;
613                 struct bna_rxq *large;
614         } slr;
615         struct {
616                 struct bna_rxq *only;
617                 struct bna_rxq *reserved;
618         } single;
619 };
620
621 /* Packet rate for Dynamic Interrupt Moderation */
622 struct bna_pkt_rate {
623         u32             small_pkt_cnt;
624         u32             large_pkt_cnt;
625 };
626
627 /* Completion control structure */
628 struct bna_ccb {
629         /* Fast path */
630         void                    **sw_qpt;
631         void                    *sw_q;
632         u32             producer_index;
633         volatile u32    *hw_producer_index;
634         u32             q_depth;
635         struct bna_ib_dbell *i_dbell;
636         struct bna_rcb *rcb[2];
637         void                    *ctrl; /* For bnad */
638         struct bna_pkt_rate pkt_rate;
639         u32                     pkts_una;
640         u32                     bytes_per_intr;
641
642         /* Control path */
643         struct bna_cq *cq;
644         struct bnad *bnad;
645         void                    *priv; /* BNAD's cookie */
646         enum bna_intr_type intr_type;
647         int                     intr_vector;
648         u8                      rx_coalescing_timeo; /* For NAPI */
649         int                     id;
650         char                    name[BNA_Q_NAME_SIZE];
651 };
652
653 /* CQ QPT, configuration  */
654 struct bna_cq {
655         struct bna_qpt qpt;
656         struct bna_ccb *ccb;
657
658         struct bna_ib ib;
659
660         struct bna_rx *rx;
661 };
662
663 struct bna_rss_config {
664         enum bfi_enet_rss_type  hash_type;
665         u8                      hash_mask;
666         u32             toeplitz_hash_key[BFI_ENET_RSS_KEY_LEN];
667 };
668
669 struct bna_hds_config {
670         enum bfi_enet_hds_type  hdr_type;
671         int                     forced_offset;
672 };
673
674 /* Rx object configuration used during creation */
675 struct bna_rx_config {
676         enum bna_rx_type rx_type;
677         int                     num_paths;
678         enum bna_rxp_type rxp_type;
679         int                     paused;
680         int                     coalescing_timeo;
681         /*
682          * Small/Large (or Header/Data) buffer size to be configured
683          * for SLR and HDS queue type.
684          */
685         u32                     frame_size;
686
687         /* header or small queue */
688         u32                     q1_depth;
689         u32                     q1_buf_size;
690
691         /* data or large queue */
692         u32                     q0_depth;
693         u32                     q0_buf_size;
694         u32                     q0_num_vecs;
695         enum bna_status         q0_multi_buf;
696
697         enum bna_status rss_status;
698         struct bna_rss_config rss_config;
699
700         struct bna_hds_config hds_config;
701
702         enum bna_status vlan_strip_status;
703 };
704
705 /* Rx Path structure - one per MSIX vector/CPU */
706 struct bna_rxp {
707         /* This should be the first one */
708         struct list_head                        qe;
709
710         enum bna_rxp_type type;
711         union   bna_rxq_u       rxq;
712         struct bna_cq cq;
713
714         struct bna_rx *rx;
715
716         /* MSI-x vector number for configuring RSS */
717         int                     vector;
718         int                     hw_id;
719 };
720
721 /* RxF structure (hardware Rx Function) */
722 struct bna_rxf {
723         bfa_fsm_t               fsm;
724         enum bna_rxf_flags flags;
725
726         struct bfa_msgq_cmd_entry msgq_cmd;
727         union {
728                 struct bfi_enet_enable_req req;
729                 struct bfi_enet_rss_cfg_req rss_req;
730                 struct bfi_enet_rit_req rit_req;
731                 struct bfi_enet_rx_vlan_req vlan_req;
732                 struct bfi_enet_mcast_add_req mcast_add_req;
733                 struct bfi_enet_mcast_del_req mcast_del_req;
734                 struct bfi_enet_ucast_req ucast_req;
735         } bfi_enet_cmd;
736
737         /* callback for bna_rxf_start() */
738         void (*start_cbfn) (struct bna_rx *rx);
739         struct bna_rx *start_cbarg;
740
741         /* callback for bna_rxf_stop() */
742         void (*stop_cbfn) (struct bna_rx *rx);
743         struct bna_rx *stop_cbarg;
744
745         /* callback for bna_rx_receive_pause() / bna_rx_receive_resume() */
746         void (*oper_state_cbfn) (struct bnad *bnad, struct bna_rx *rx);
747         struct bnad *oper_state_cbarg;
748
749         /**
750          * callback for:
751          *      bna_rxf_ucast_set()
752          *      bna_rxf_{ucast/mcast}_add(),
753          *      bna_rxf_{ucast/mcast}_del(),
754          *      bna_rxf_mode_set()
755          */
756         void (*cam_fltr_cbfn)(struct bnad *bnad, struct bna_rx *rx);
757         struct bnad *cam_fltr_cbarg;
758
759         /* List of unicast addresses yet to be applied to h/w */
760         struct list_head                        ucast_pending_add_q;
761         struct list_head                        ucast_pending_del_q;
762         struct bna_mac *ucast_pending_mac;
763         int                     ucast_pending_set;
764         /* ucast addresses applied to the h/w */
765         struct list_head                        ucast_active_q;
766         struct bna_mac ucast_active_mac;
767         int                     ucast_active_set;
768
769         /* List of multicast addresses yet to be applied to h/w */
770         struct list_head                        mcast_pending_add_q;
771         struct list_head                        mcast_pending_del_q;
772         /* multicast addresses applied to the h/w */
773         struct list_head                        mcast_active_q;
774         struct list_head                        mcast_handle_q;
775
776         /* Rx modes yet to be applied to h/w */
777         enum bna_rxmode rxmode_pending;
778         enum bna_rxmode rxmode_pending_bitmask;
779         /* Rx modes applied to h/w */
780         enum bna_rxmode rxmode_active;
781
782         u8                      vlan_pending_bitmask;
783         enum bna_status vlan_filter_status;
784         u32     vlan_filter_table[(BFI_ENET_VLAN_ID_MAX) / 32];
785         bool                    vlan_strip_pending;
786         enum bna_status         vlan_strip_status;
787
788         enum bna_rss_flags      rss_pending;
789         enum bna_status         rss_status;
790         struct bna_rss_config   rss_cfg;
791         u8                      *rit;
792         int                     rit_size;
793
794         struct bna_rx           *rx;
795 };
796
797 /* Rx object */
798 struct bna_rx {
799         /* This should be the first one */
800         struct list_head                        qe;
801         int                     rid;
802         int                     hw_id;
803
804         bfa_fsm_t               fsm;
805
806         enum bna_rx_type type;
807
808         int                     num_paths;
809         struct list_head                        rxp_q;
810
811         struct bna_hds_config   hds_cfg;
812
813         struct bna_rxf rxf;
814
815         enum bna_rx_flags rx_flags;
816
817         struct bfa_msgq_cmd_entry msgq_cmd;
818         union {
819                 struct bfi_enet_rx_cfg_req      cfg_req;
820                 struct bfi_enet_req             req;
821                 struct bfi_enet_rx_cfg_rsp      cfg_rsp;
822         } bfi_enet_cmd;
823
824         /* Rx event handlers */
825         void (*rcb_setup_cbfn)(struct bnad *, struct bna_rcb *);
826         void (*rcb_destroy_cbfn)(struct bnad *, struct bna_rcb *);
827         void (*ccb_setup_cbfn)(struct bnad *, struct bna_ccb *);
828         void (*ccb_destroy_cbfn)(struct bnad *, struct bna_ccb *);
829         void (*rx_stall_cbfn)(struct bnad *, struct bna_rx *);
830         void (*rx_cleanup_cbfn)(struct bnad *, struct bna_rx *);
831         void (*rx_post_cbfn)(struct bnad *, struct bna_rx *);
832
833         /* callback for bna_rx_disable(), bna_rx_stop() */
834         void (*stop_cbfn)(void *arg, struct bna_rx *rx);
835         void                    *stop_cbarg;
836
837         struct bna *bna;
838         void                    *priv; /* bnad's cookie */
839 };
840
841 struct bna_rx_event_cbfn {
842         /* Optional */
843         void (*rcb_setup_cbfn)(struct bnad *, struct bna_rcb *);
844         void (*rcb_destroy_cbfn)(struct bnad *, struct bna_rcb *);
845         void (*ccb_setup_cbfn)(struct bnad *, struct bna_ccb *);
846         void (*ccb_destroy_cbfn)(struct bnad *, struct bna_ccb *);
847         void (*rx_stall_cbfn)(struct bnad *, struct bna_rx *);
848         /* Mandatory */
849         void (*rx_cleanup_cbfn)(struct bnad *, struct bna_rx *);
850         void (*rx_post_cbfn)(struct bnad *, struct bna_rx *);
851 };
852
853 /* Rx module - keeps track of free, active rx objects */
854 struct bna_rx_mod {
855         struct bna *bna;                /* back pointer to parent */
856         struct bna_rx *rx;              /* BFI_MAX_RXQ entries */
857         struct bna_rxp *rxp;            /* BFI_MAX_RXQ entries */
858         struct bna_rxq *rxq;            /* BFI_MAX_RXQ entries */
859
860         struct list_head                        rx_free_q;
861         struct list_head                        rx_active_q;
862         int                     rx_free_count;
863
864         struct list_head                        rxp_free_q;
865         int                     rxp_free_count;
866
867         struct list_head                        rxq_free_q;
868         int                     rxq_free_count;
869
870         enum bna_rx_mod_flags flags;
871
872         /* callback for bna_rx_mod_stop() */
873         void (*stop_cbfn)(struct bna_enet *enet);
874
875         struct bfa_wc           rx_stop_wc;
876         u32             dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX];
877         u32             rid_mask;
878 };
879
880 /* CAM */
881
882 struct bna_ucam_mod {
883         struct bna_mac *ucmac;          /* num_ucmac * 2 entries */
884         struct list_head                        free_q;
885         struct list_head                        del_q;
886
887         struct bna *bna;
888 };
889
890 struct bna_mcam_handle {
891         /* This should be the first one */
892         struct list_head                        qe;
893         int                     handle;
894         int                     refcnt;
895 };
896
897 struct bna_mcam_mod {
898         struct bna_mac *mcmac;          /* num_mcmac * 2 entries */
899         struct bna_mcam_handle *mchandle;       /* num_mcmac entries */
900         struct list_head                        free_q;
901         struct list_head                        del_q;
902         struct list_head                        free_handle_q;
903
904         struct bna *bna;
905 };
906
907 /* Statistics */
908
909 struct bna_stats {
910         struct bna_dma_addr     hw_stats_dma;
911         struct bfi_enet_stats   *hw_stats_kva;
912         struct bfi_enet_stats   hw_stats;
913 };
914
915 struct bna_stats_mod {
916         bool            ioc_ready;
917         bool            stats_get_busy;
918         bool            stats_clr_busy;
919         struct bfa_msgq_cmd_entry stats_get_cmd;
920         struct bfa_msgq_cmd_entry stats_clr_cmd;
921         struct bfi_enet_stats_req stats_get;
922         struct bfi_enet_stats_req stats_clr;
923 };
924
925 /* BNA */
926
927 struct bna {
928         struct bna_ident ident;
929         struct bfa_pcidev pcidev;
930
931         struct bna_reg regs;
932         struct bna_bit_defn bits;
933
934         struct bna_stats stats;
935
936         struct bna_ioceth ioceth;
937         struct bfa_cee cee;
938         struct bfa_flash flash;
939         struct bfa_msgq msgq;
940
941         struct bna_ethport ethport;
942         struct bna_enet enet;
943         struct bna_stats_mod stats_mod;
944
945         struct bna_tx_mod tx_mod;
946         struct bna_rx_mod rx_mod;
947         struct bna_ucam_mod ucam_mod;
948         struct bna_mcam_mod mcam_mod;
949
950         enum bna_mod_flags mod_flags;
951
952         int                     default_mode_rid;
953         int                     promisc_rid;
954
955         struct bnad *bnad;
956 };
957 #endif  /* __BNA_TYPES_H__ */