kernel/drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 /*
   2  * Broadcom GENET (Gigabit Ethernet) controller driver
   3  *
   4  * Copyright (c) 2014 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/sched.h>
  16 #include <linux/types.h>
  17 #include <linux/fcntl.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/string.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_net.h>
  32 #include <linux/of_platform.h>
  33 #include <net/arp.h>
  34
  35 #include <linux/mii.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/inetdevice.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/in.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/phy.h>
  45 #include <linux/platform_data/bcmgenet.h>
  46
  47 #include <asm/unaligned.h>
  48
  49 #include "bcmgenet.h"
  50
  51 /* Maximum number of hardware queues, downsized if needed */
  52 #define GENET_MAX_MQ_CNT        4
  53
  54 /* Default highest priority queue for multi queue support */
  55 #define GENET_Q0_PRIORITY       0
  56
  57 #define GENET_Q16_RX_BD_CNT     \
  58         (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
  59 #define GENET_Q16_TX_BD_CNT     \
  60         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
  61
  62 #define RX_BUF_LENGTH           2048
  63 #define SKB_ALIGNMENT           32
  64
  65 /* Tx/Rx DMA register offset, skip 256 descriptors */
  66 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  67 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  68
  69 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  70                                 TOTAL_DESC * DMA_DESC_SIZE)
  71
  72 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  73                                 TOTAL_DESC * DMA_DESC_SIZE)
  74
  75 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  76                                              void __iomem *d, u32 value)
  77 {
  78         __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
  79 }
  80
  81 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
  82                                             void __iomem *d)
  83 {
  84         return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
  85 }
  86
  87 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
  88                                     void __iomem *d,
  89                                     dma_addr_t addr)
  90 {
  91         __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
  92
  93         /* Register writes to GISB bus can take couple hundred nanoseconds
  94          * and are done for each packet, save these expensive writes unless
  95          * the platform is explicitly configured for 64-bits/LPAE.
  96          */
  97 #ifdef CONFIG_PHYS_ADDR_T_64BIT
  98         if (priv->hw_params->flags & GENET_HAS_40BITS)
  99                 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
 100 #endif
 101 }
 102
 103 /* Combined address + length/status setter */
 104 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 105                                void __iomem *d, dma_addr_t addr, u32 val)
 106 {
 107         dmadesc_set_length_status(priv, d, val);
 108         dmadesc_set_addr(priv, d, addr);
 109 }
 110
 111 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 112                                           void __iomem *d)
 113 {
 114         dma_addr_t addr;
 115
 116         addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
 117
 118         /* Register writes to GISB bus can take couple hundred nanoseconds
 119          * and are done for each packet, save these expensive writes unless
 120          * the platform is explicitly configured for 64-bits/LPAE.
 121          */
 122 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 123         if (priv->hw_params->flags & GENET_HAS_40BITS)
 124                 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 125 #endif
 126         return addr;
 127 }
 128
 129 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 130
 131 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 132                                 NETIF_MSG_LINK)
 133
 134 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 135 {
 136         if (GENET_IS_V1(priv))
 137                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 138         else
 139                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 140 }
 141
 142 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 143 {
 144         if (GENET_IS_V1(priv))
 145                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 146         else
 147                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 148 }
 149
 150 /* These macros are defined to deal with register map change
 151  * between GENET1.1 and GENET2. Only those currently being used
 152  * by driver are defined.
 153  */
 154 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 155 {
 156         if (GENET_IS_V1(priv))
 157                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 158         else
 159                 return __raw_readl(priv->base +
 160                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 161 }
 162
 163 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 164 {
 165         if (GENET_IS_V1(priv))
 166                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 167         else
 168                 __raw_writel(val, priv->base +
 169                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 170 }
 171
 172 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 173 {
 174         if (GENET_IS_V1(priv))
 175                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 176         else
 177                 return __raw_readl(priv->base +
 178                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 179 }
 180
 181 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 182 {
 183         if (GENET_IS_V1(priv))
 184                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 185         else
 186                 __raw_writel(val, priv->base +
 187                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 188 }
 189
 190 /* RX/TX DMA register accessors */
 191 enum dma_reg {
 192         DMA_RING_CFG = 0,
 193         DMA_CTRL,
 194         DMA_STATUS,
 195         DMA_SCB_BURST_SIZE,
 196         DMA_ARB_CTRL,
 197         DMA_PRIORITY_0,
 198         DMA_PRIORITY_1,
 199         DMA_PRIORITY_2,
 200         DMA_INDEX2RING_0,
 201         DMA_INDEX2RING_1,
 202         DMA_INDEX2RING_2,
 203         DMA_INDEX2RING_3,
 204         DMA_INDEX2RING_4,
 205         DMA_INDEX2RING_5,
 206         DMA_INDEX2RING_6,
 207         DMA_INDEX2RING_7,
 208         DMA_RING0_TIMEOUT,
 209         DMA_RING1_TIMEOUT,
 210         DMA_RING2_TIMEOUT,
 211         DMA_RING3_TIMEOUT,
 212         DMA_RING4_TIMEOUT,
 213         DMA_RING5_TIMEOUT,
 214         DMA_RING6_TIMEOUT,
 215         DMA_RING7_TIMEOUT,
 216         DMA_RING8_TIMEOUT,
 217         DMA_RING9_TIMEOUT,
 218         DMA_RING10_TIMEOUT,
 219         DMA_RING11_TIMEOUT,
 220         DMA_RING12_TIMEOUT,
 221         DMA_RING13_TIMEOUT,
 222         DMA_RING14_TIMEOUT,
 223         DMA_RING15_TIMEOUT,
 224         DMA_RING16_TIMEOUT,
 225 };
 226
 227 static const u8 bcmgenet_dma_regs_v3plus[] = {
 228         [DMA_RING_CFG]          = 0x00,
 229         [DMA_CTRL]              = 0x04,
 230         [DMA_STATUS]            = 0x08,
 231         [DMA_SCB_BURST_SIZE]    = 0x0C,
 232         [DMA_ARB_CTRL]          = 0x2C,
 233         [DMA_PRIORITY_0]        = 0x30,
 234         [DMA_PRIORITY_1]        = 0x34,
 235         [DMA_PRIORITY_2]        = 0x38,
 236         [DMA_RING0_TIMEOUT]     = 0x2C,
 237         [DMA_RING1_TIMEOUT]     = 0x30,
 238         [DMA_RING2_TIMEOUT]     = 0x34,
 239         [DMA_RING3_TIMEOUT]     = 0x38,
 240         [DMA_RING4_TIMEOUT]     = 0x3c,
 241         [DMA_RING5_TIMEOUT]     = 0x40,
 242         [DMA_RING6_TIMEOUT]     = 0x44,
 243         [DMA_RING7_TIMEOUT]     = 0x48,
 244         [DMA_RING8_TIMEOUT]     = 0x4c,
 245         [DMA_RING9_TIMEOUT]     = 0x50,
 246         [DMA_RING10_TIMEOUT]    = 0x54,
 247         [DMA_RING11_TIMEOUT]    = 0x58,
 248         [DMA_RING12_TIMEOUT]    = 0x5c,
 249         [DMA_RING13_TIMEOUT]    = 0x60,
 250         [DMA_RING14_TIMEOUT]    = 0x64,
 251         [DMA_RING15_TIMEOUT]    = 0x68,
 252         [DMA_RING16_TIMEOUT]    = 0x6C,
 253         [DMA_INDEX2RING_0]      = 0x70,
 254         [DMA_INDEX2RING_1]      = 0x74,
 255         [DMA_INDEX2RING_2]      = 0x78,
 256         [DMA_INDEX2RING_3]      = 0x7C,
 257         [DMA_INDEX2RING_4]      = 0x80,
 258         [DMA_INDEX2RING_5]      = 0x84,
 259         [DMA_INDEX2RING_6]      = 0x88,
 260         [DMA_INDEX2RING_7]      = 0x8C,
 261 };
 262
 263 static const u8 bcmgenet_dma_regs_v2[] = {
 264         [DMA_RING_CFG]          = 0x00,
 265         [DMA_CTRL]              = 0x04,
 266         [DMA_STATUS]            = 0x08,
 267         [DMA_SCB_BURST_SIZE]    = 0x0C,
 268         [DMA_ARB_CTRL]          = 0x30,
 269         [DMA_PRIORITY_0]        = 0x34,
 270         [DMA_PRIORITY_1]        = 0x38,
 271         [DMA_PRIORITY_2]        = 0x3C,
 272         [DMA_RING0_TIMEOUT]     = 0x2C,
 273         [DMA_RING1_TIMEOUT]     = 0x30,
 274         [DMA_RING2_TIMEOUT]     = 0x34,
 275         [DMA_RING3_TIMEOUT]     = 0x38,
 276         [DMA_RING4_TIMEOUT]     = 0x3c,
 277         [DMA_RING5_TIMEOUT]     = 0x40,
 278         [DMA_RING6_TIMEOUT]     = 0x44,
 279         [DMA_RING7_TIMEOUT]     = 0x48,
 280         [DMA_RING8_TIMEOUT]     = 0x4c,
 281         [DMA_RING9_TIMEOUT]     = 0x50,
 282         [DMA_RING10_TIMEOUT]    = 0x54,
 283         [DMA_RING11_TIMEOUT]    = 0x58,
 284         [DMA_RING12_TIMEOUT]    = 0x5c,
 285         [DMA_RING13_TIMEOUT]    = 0x60,
 286         [DMA_RING14_TIMEOUT]    = 0x64,
 287         [DMA_RING15_TIMEOUT]    = 0x68,
 288         [DMA_RING16_TIMEOUT]    = 0x6C,
 289 };
 290
 291 static const u8 bcmgenet_dma_regs_v1[] = {
 292         [DMA_CTRL]              = 0x00,
 293         [DMA_STATUS]            = 0x04,
 294         [DMA_SCB_BURST_SIZE]    = 0x0C,
 295         [DMA_ARB_CTRL]          = 0x30,
 296         [DMA_PRIORITY_0]        = 0x34,
 297         [DMA_PRIORITY_1]        = 0x38,
 298         [DMA_PRIORITY_2]        = 0x3C,
 299         [DMA_RING0_TIMEOUT]     = 0x2C,
 300         [DMA_RING1_TIMEOUT]     = 0x30,
 301         [DMA_RING2_TIMEOUT]     = 0x34,
 302         [DMA_RING3_TIMEOUT]     = 0x38,
 303         [DMA_RING4_TIMEOUT]     = 0x3c,
 304         [DMA_RING5_TIMEOUT]     = 0x40,
 305         [DMA_RING6_TIMEOUT]     = 0x44,
 306         [DMA_RING7_TIMEOUT]     = 0x48,
 307         [DMA_RING8_TIMEOUT]     = 0x4c,
 308         [DMA_RING9_TIMEOUT]     = 0x50,
 309         [DMA_RING10_TIMEOUT]    = 0x54,
 310         [DMA_RING11_TIMEOUT]    = 0x58,
 311         [DMA_RING12_TIMEOUT]    = 0x5c,
 312         [DMA_RING13_TIMEOUT]    = 0x60,
 313         [DMA_RING14_TIMEOUT]    = 0x64,
 314         [DMA_RING15_TIMEOUT]    = 0x68,
 315         [DMA_RING16_TIMEOUT]    = 0x6C,
 316 };
 317
 318 /* Set at runtime once bcmgenet version is known */
 319 static const u8 *bcmgenet_dma_regs;
 320
 321 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 322 {
 323         return netdev_priv(dev_get_drvdata(dev));
 324 }
 325
 326 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 327                                       enum dma_reg r)
 328 {
 329         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 330                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 331 }
 332
 333 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 334                                         u32 val, enum dma_reg r)
 335 {
 336         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 337                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 338 }
 339
 340 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 341                                       enum dma_reg r)
 342 {
 343         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 344                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 345 }
 346
 347 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 348                                         u32 val, enum dma_reg r)
 349 {
 350         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 351                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 352 }
 353
 354 /* RDMA/TDMA ring registers and accessors
 355  * we merge the common fields and just prefix with T/D the registers
 356  * having different meaning depending on the direction
 357  */
 358 enum dma_ring_reg {
 359         TDMA_READ_PTR = 0,
 360         RDMA_WRITE_PTR = TDMA_READ_PTR,
 361         TDMA_READ_PTR_HI,
 362         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 363         TDMA_CONS_INDEX,
 364         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 365         TDMA_PROD_INDEX,
 366         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 367         DMA_RING_BUF_SIZE,
 368         DMA_START_ADDR,
 369         DMA_START_ADDR_HI,
 370         DMA_END_ADDR,
 371         DMA_END_ADDR_HI,
 372         DMA_MBUF_DONE_THRESH,
 373         TDMA_FLOW_PERIOD,
 374         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 375         TDMA_WRITE_PTR,
 376         RDMA_READ_PTR = TDMA_WRITE_PTR,
 377         TDMA_WRITE_PTR_HI,
 378         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 379 };
 380
 381 /* GENET v4 supports 40-bits pointer addressing
 382  * for obvious reasons the LO and HI word parts
 383  * are contiguous, but this offsets the other
 384  * registers.
 385  */
 386 static const u8 genet_dma_ring_regs_v4[] = {
 387         [TDMA_READ_PTR]                 = 0x00,
 388         [TDMA_READ_PTR_HI]              = 0x04,
 389         [TDMA_CONS_INDEX]               = 0x08,
 390         [TDMA_PROD_INDEX]               = 0x0C,
 391         [DMA_RING_BUF_SIZE]             = 0x10,
 392         [DMA_START_ADDR]                = 0x14,
 393         [DMA_START_ADDR_HI]             = 0x18,
 394         [DMA_END_ADDR]                  = 0x1C,
 395         [DMA_END_ADDR_HI]               = 0x20,
 396         [DMA_MBUF_DONE_THRESH]          = 0x24,
 397         [TDMA_FLOW_PERIOD]              = 0x28,
 398         [TDMA_WRITE_PTR]                = 0x2C,
 399         [TDMA_WRITE_PTR_HI]             = 0x30,
 400 };
 401
 402 static const u8 genet_dma_ring_regs_v123[] = {
 403         [TDMA_READ_PTR]                 = 0x00,
 404         [TDMA_CONS_INDEX]               = 0x04,
 405         [TDMA_PROD_INDEX]               = 0x08,
 406         [DMA_RING_BUF_SIZE]             = 0x0C,
 407         [DMA_START_ADDR]                = 0x10,
 408         [DMA_END_ADDR]                  = 0x14,
 409         [DMA_MBUF_DONE_THRESH]          = 0x18,
 410         [TDMA_FLOW_PERIOD]              = 0x1C,
 411         [TDMA_WRITE_PTR]                = 0x20,
 412 };
 413
 414 /* Set at runtime once GENET version is known */
 415 static const u8 *genet_dma_ring_regs;
 416
 417 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 418                                            unsigned int ring,
 419                                            enum dma_ring_reg r)
 420 {
 421         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 422                         (DMA_RING_SIZE * ring) +
 423                         genet_dma_ring_regs[r]);
 424 }
 425
 426 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 427                                              unsigned int ring, u32 val,
 428                                              enum dma_ring_reg r)
 429 {
 430         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 431                         (DMA_RING_SIZE * ring) +
 432                         genet_dma_ring_regs[r]);
 433 }
 434
 435 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 436                                            unsigned int ring,
 437                                            enum dma_ring_reg r)
 438 {
 439         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 440                         (DMA_RING_SIZE * ring) +
 441                         genet_dma_ring_regs[r]);
 442 }
 443
 444 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 445                                              unsigned int ring, u32 val,
 446                                              enum dma_ring_reg r)
 447 {
 448         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 449                         (DMA_RING_SIZE * ring) +
 450                         genet_dma_ring_regs[r]);
 451 }
 452
 453 static int bcmgenet_get_settings(struct net_device *dev,
 454                                  struct ethtool_cmd *cmd)
 455 {
 456         struct bcmgenet_priv *priv = netdev_priv(dev);
 457
 458         if (!netif_running(dev))
 459                 return -EINVAL;
 460
 461         if (!priv->phydev)
 462                 return -ENODEV;
 463
 464         return phy_ethtool_gset(priv->phydev, cmd);
 465 }
 466
 467 static int bcmgenet_set_settings(struct net_device *dev,
 468                                  struct ethtool_cmd *cmd)
 469 {
 470         struct bcmgenet_priv *priv = netdev_priv(dev);
 471
 472         if (!netif_running(dev))
 473                 return -EINVAL;
 474
 475         if (!priv->phydev)
 476                 return -ENODEV;
 477
 478         return phy_ethtool_sset(priv->phydev, cmd);
 479 }
 480
 481 static int bcmgenet_set_rx_csum(struct net_device *dev,
 482                                 netdev_features_t wanted)
 483 {
 484         struct bcmgenet_priv *priv = netdev_priv(dev);
 485         u32 rbuf_chk_ctrl;
 486         bool rx_csum_en;
 487
 488         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 489
 490         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 491
 492         /* enable rx checksumming */
 493         if (rx_csum_en)
 494                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 495         else
 496                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 497         priv->desc_rxchk_en = rx_csum_en;
 498
 499         /* If UniMAC forwards CRC, we need to skip over it to get
 500          * a valid CHK bit to be set in the per-packet status word
 501         */
 502         if (rx_csum_en && priv->crc_fwd_en)
 503                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 504         else
 505                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 506
 507         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 508
 509         return 0;
 510 }
 511
 512 static int bcmgenet_set_tx_csum(struct net_device *dev,
 513                                 netdev_features_t wanted)
 514 {
 515         struct bcmgenet_priv *priv = netdev_priv(dev);
 516         bool desc_64b_en;
 517         u32 tbuf_ctrl, rbuf_ctrl;
 518
 519         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 520         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 521
 522         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 523
 524         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 525         if (desc_64b_en) {
 526                 tbuf_ctrl |= RBUF_64B_EN;
 527                 rbuf_ctrl |= RBUF_64B_EN;
 528         } else {
 529                 tbuf_ctrl &= ~RBUF_64B_EN;
 530                 rbuf_ctrl &= ~RBUF_64B_EN;
 531         }
 532         priv->desc_64b_en = desc_64b_en;
 533
 534         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 535         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 536
 537         return 0;
 538 }
 539
 540 static int bcmgenet_set_features(struct net_device *dev,
 541                                  netdev_features_t features)
 542 {
 543         netdev_features_t changed = features ^ dev->features;
 544         netdev_features_t wanted = dev->wanted_features;
 545         int ret = 0;
 546
 547         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 548                 ret = bcmgenet_set_tx_csum(dev, wanted);
 549         if (changed & (NETIF_F_RXCSUM))
 550                 ret = bcmgenet_set_rx_csum(dev, wanted);
 551
 552         return ret;
 553 }
 554
 555 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 556 {
 557         struct bcmgenet_priv *priv = netdev_priv(dev);
 558
 559         return priv->msg_enable;
 560 }
 561
 562 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 563 {
 564         struct bcmgenet_priv *priv = netdev_priv(dev);
 565
 566         priv->msg_enable = level;
 567 }
 568
 569 static int bcmgenet_get_coalesce(struct net_device *dev,
 570                                  struct ethtool_coalesce *ec)
 571 {
 572         struct bcmgenet_priv *priv = netdev_priv(dev);
 573
 574         ec->tx_max_coalesced_frames =
 575                 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
 576                                          DMA_MBUF_DONE_THRESH);
 577         ec->rx_max_coalesced_frames =
 578                 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
 579                                          DMA_MBUF_DONE_THRESH);
 580         ec->rx_coalesce_usecs =
 581                 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
 582
 583         return 0;
 584 }
 585
 586 static int bcmgenet_set_coalesce(struct net_device *dev,
 587                                  struct ethtool_coalesce *ec)
 588 {
 589         struct bcmgenet_priv *priv = netdev_priv(dev);
 590         unsigned int i;
 591         u32 reg;
 592
 593         /* Base system clock is 125Mhz, DMA timeout is this reference clock
 594          * divided by 1024, which yields roughly 8.192us, our maximum value
 595          * has to fit in the DMA_TIMEOUT_MASK (16 bits)
 596          */
 597         if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 598             ec->tx_max_coalesced_frames == 0 ||
 599             ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 600             ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
 601                 return -EINVAL;
 602
 603         if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
 604                 return -EINVAL;
 605
 606         /* GENET TDMA hardware does not support a configurable timeout, but will
 607          * always generate an interrupt either after MBDONE packets have been
 608          * transmitted, or when the ring is emtpy.
 609          */
 610         if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
 611             ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
 612                 return -EOPNOTSUPP;
 613
 614         /* Program all TX queues with the same values, as there is no
 615          * ethtool knob to do coalescing on a per-queue basis
 616          */
 617         for (i = 0; i < priv->hw_params->tx_queues; i++)
 618                 bcmgenet_tdma_ring_writel(priv, i,
 619                                           ec->tx_max_coalesced_frames,
 620                                           DMA_MBUF_DONE_THRESH);
 621         bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
 622                                   ec->tx_max_coalesced_frames,
 623                                   DMA_MBUF_DONE_THRESH);
 624
 625         for (i = 0; i < priv->hw_params->rx_queues; i++) {
 626                 bcmgenet_rdma_ring_writel(priv, i,
 627                                           ec->rx_max_coalesced_frames,
 628                                           DMA_MBUF_DONE_THRESH);
 629
 630                 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
 631                 reg &= ~DMA_TIMEOUT_MASK;
 632                 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 633                 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
 634         }
 635
 636         bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
 637                                   ec->rx_max_coalesced_frames,
 638                                   DMA_MBUF_DONE_THRESH);
 639
 640         reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
 641         reg &= ~DMA_TIMEOUT_MASK;
 642         reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 643         bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
 644
 645         return 0;
 646 }
 647
 648 /* standard ethtool support functions. */
 649 enum bcmgenet_stat_type {
 650         BCMGENET_STAT_NETDEV = -1,
 651         BCMGENET_STAT_MIB_RX,
 652         BCMGENET_STAT_MIB_TX,
 653         BCMGENET_STAT_RUNT,
 654         BCMGENET_STAT_MISC,
 655         BCMGENET_STAT_SOFT,
 656 };
 657
 658 struct bcmgenet_stats {
 659         char stat_string[ETH_GSTRING_LEN];
 660         int stat_sizeof;
 661         int stat_offset;
 662         enum bcmgenet_stat_type type;
 663         /* reg offset from UMAC base for misc counters */
 664         u16 reg_offset;
 665 };
 666
 667 #define STAT_NETDEV(m) { \
 668         .stat_string = __stringify(m), \
 669         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 670         .stat_offset = offsetof(struct net_device_stats, m), \
 671         .type = BCMGENET_STAT_NETDEV, \
 672 }
 673
 674 #define STAT_GENET_MIB(str, m, _type) { \
 675         .stat_string = str, \
 676         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 677         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 678         .type = _type, \
 679 }
 680
 681 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 682 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 683 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 684 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
 685
 686 #define STAT_GENET_MISC(str, m, offset) { \
 687         .stat_string = str, \
 688         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 689         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 690         .type = BCMGENET_STAT_MISC, \
 691         .reg_offset = offset, \
 692 }
 693
 694
 695 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 696  * between the end of TX stats and the beginning of the RX RUNT
 697  */
 698 #define BCMGENET_STAT_OFFSET    0xc
 699
 700 /* Hardware counters must be kept in sync because the order/offset
 701  * is important here (order in structure declaration = order in hardware)
 702  */
 703 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 704         /* general stats */
 705         STAT_NETDEV(rx_packets),
 706         STAT_NETDEV(tx_packets),
 707         STAT_NETDEV(rx_bytes),
 708         STAT_NETDEV(tx_bytes),
 709         STAT_NETDEV(rx_errors),
 710         STAT_NETDEV(tx_errors),
 711         STAT_NETDEV(rx_dropped),
 712         STAT_NETDEV(tx_dropped),
 713         STAT_NETDEV(multicast),
 714         /* UniMAC RSV counters */
 715         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 716         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 717         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 718         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 719         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 720         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 721         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 722         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 723         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 724         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 725         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 726         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 727         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 728         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 729         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 730         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 731         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 732         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 733         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 734         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 735         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 736         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 737         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 738         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 739         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 740         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 741         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 742         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 743         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 744         /* UniMAC TSV counters */
 745         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 746         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 747         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 748         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 749         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 750         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 751         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 752         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 753         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 754         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 755         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 756         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 757         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 758         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 759         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 760         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 761         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 762         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 763         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 764         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 765         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 766         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 767         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 768         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 769         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 770         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 771         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 772         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 773         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 774         /* UniMAC RUNT counters */
 775         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 776         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 777         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 778         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 779         /* Misc UniMAC counters */
 780         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 781                         UMAC_RBUF_OVFL_CNT),
 782         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
 783         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 784         STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 785         STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
 786         STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
 787 };
 788
 789 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 790
 791 static void bcmgenet_get_drvinfo(struct net_device *dev,
 792                                  struct ethtool_drvinfo *info)
 793 {
 794         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 795         strlcpy(info->version, "v2.0", sizeof(info->version));
 796 }
 797
 798 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 799 {
 800         switch (string_set) {
 801         case ETH_SS_STATS:
 802                 return BCMGENET_STATS_LEN;
 803         default:
 804                 return -EOPNOTSUPP;
 805         }
 806 }
 807
 808 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 809                                  u8 *data)
 810 {
 811         int i;
 812
 813         switch (stringset) {
 814         case ETH_SS_STATS:
 815                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 816                         memcpy(data + i * ETH_GSTRING_LEN,
 817                                bcmgenet_gstrings_stats[i].stat_string,
 818                                ETH_GSTRING_LEN);
 819                 }
 820                 break;
 821         }
 822 }
 823
 824 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 825 {
 826         int i, j = 0;
 827
 828         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 829                 const struct bcmgenet_stats *s;
 830                 u8 offset = 0;
 831                 u32 val = 0;
 832                 char *p;
 833
 834                 s = &bcmgenet_gstrings_stats[i];
 835                 switch (s->type) {
 836                 case BCMGENET_STAT_NETDEV:
 837                 case BCMGENET_STAT_SOFT:
 838                         continue;
 839                 case BCMGENET_STAT_MIB_RX:
 840                 case BCMGENET_STAT_MIB_TX:
 841                 case BCMGENET_STAT_RUNT:
 842                         if (s->type != BCMGENET_STAT_MIB_RX)
 843                                 offset = BCMGENET_STAT_OFFSET;
 844                         val = bcmgenet_umac_readl(priv,
 845                                                   UMAC_MIB_START + j + offset);
 846                         break;
 847                 case BCMGENET_STAT_MISC:
 848                         val = bcmgenet_umac_readl(priv, s->reg_offset);
 849                         /* clear if overflowed */
 850                         if (val == ~0)
 851                                 bcmgenet_umac_writel(priv, 0, s->reg_offset);
 852                         break;
 853                 }
 854
 855                 j += s->stat_sizeof;
 856                 p = (char *)priv + s->stat_offset;
 857                 *(u32 *)p = val;
 858         }
 859 }
 860
 861 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 862                                        struct ethtool_stats *stats,
 863                                        u64 *data)
 864 {
 865         struct bcmgenet_priv *priv = netdev_priv(dev);
 866         int i;
 867
 868         if (netif_running(dev))
 869                 bcmgenet_update_mib_counters(priv);
 870
 871         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 872                 const struct bcmgenet_stats *s;
 873                 char *p;
 874
 875                 s = &bcmgenet_gstrings_stats[i];
 876                 if (s->type == BCMGENET_STAT_NETDEV)
 877                         p = (char *)&dev->stats;
 878                 else
 879                         p = (char *)priv;
 880                 p += s->stat_offset;
 881                 data[i] = *(u32 *)p;
 882         }
 883 }
 884
 885 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
 886 {
 887         struct bcmgenet_priv *priv = netdev_priv(dev);
 888         u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
 889         u32 reg;
 890
 891         if (enable && !priv->clk_eee_enabled) {
 892                 clk_prepare_enable(priv->clk_eee);
 893                 priv->clk_eee_enabled = true;
 894         }
 895
 896         reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
 897         if (enable)
 898                 reg |= EEE_EN;
 899         else
 900                 reg &= ~EEE_EN;
 901         bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
 902
 903         /* Enable EEE and switch to a 27Mhz clock automatically */
 904         reg = __raw_readl(priv->base + off);
 905         if (enable)
 906                 reg |= TBUF_EEE_EN | TBUF_PM_EN;
 907         else
 908                 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
 909         __raw_writel(reg, priv->base + off);
 910
 911         /* Do the same for thing for RBUF */
 912         reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
 913         if (enable)
 914                 reg |= RBUF_EEE_EN | RBUF_PM_EN;
 915         else
 916                 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
 917         bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
 918
 919         if (!enable && priv->clk_eee_enabled) {
 920                 clk_disable_unprepare(priv->clk_eee);
 921                 priv->clk_eee_enabled = false;
 922         }
 923
 924         priv->eee.eee_enabled = enable;
 925         priv->eee.eee_active = enable;
 926 }
 927
 928 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
 929 {
 930         struct bcmgenet_priv *priv = netdev_priv(dev);
 931         struct ethtool_eee *p = &priv->eee;
 932
 933         if (GENET_IS_V1(priv))
 934                 return -EOPNOTSUPP;
 935
 936         e->eee_enabled = p->eee_enabled;
 937         e->eee_active = p->eee_active;
 938         e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
 939
 940         return phy_ethtool_get_eee(priv->phydev, e);
 941 }
 942
 943 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
 944 {
 945         struct bcmgenet_priv *priv = netdev_priv(dev);
 946         struct ethtool_eee *p = &priv->eee;
 947         int ret = 0;
 948
 949         if (GENET_IS_V1(priv))
 950                 return -EOPNOTSUPP;
 951
 952         p->eee_enabled = e->eee_enabled;
 953
 954         if (!p->eee_enabled) {
 955                 bcmgenet_eee_enable_set(dev, false);
 956         } else {
 957                 ret = phy_init_eee(priv->phydev, 0);
 958                 if (ret) {
 959                         netif_err(priv, hw, dev, "EEE initialization failed\n");
 960                         return ret;
 961                 }
 962
 963                 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
 964                 bcmgenet_eee_enable_set(dev, true);
 965         }
 966
 967         return phy_ethtool_set_eee(priv->phydev, e);
 968 }
 969
 970 static int bcmgenet_nway_reset(struct net_device *dev)
 971 {
 972         struct bcmgenet_priv *priv = netdev_priv(dev);
 973
 974         return genphy_restart_aneg(priv->phydev);
 975 }
 976
 977 /* standard ethtool support functions. */
 978 static struct ethtool_ops bcmgenet_ethtool_ops = {
 979         .get_strings            = bcmgenet_get_strings,
 980         .get_sset_count         = bcmgenet_get_sset_count,
 981         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
 982         .get_settings           = bcmgenet_get_settings,
 983         .set_settings           = bcmgenet_set_settings,
 984         .get_drvinfo            = bcmgenet_get_drvinfo,
 985         .get_link               = ethtool_op_get_link,
 986         .get_msglevel           = bcmgenet_get_msglevel,
 987         .set_msglevel           = bcmgenet_set_msglevel,
 988         .get_wol                = bcmgenet_get_wol,
 989         .set_wol                = bcmgenet_set_wol,
 990         .get_eee                = bcmgenet_get_eee,
 991         .set_eee                = bcmgenet_set_eee,
 992         .nway_reset             = bcmgenet_nway_reset,
 993         .get_coalesce           = bcmgenet_get_coalesce,
 994         .set_coalesce           = bcmgenet_set_coalesce,
 995 };
 996
 997 /* Power down the unimac, based on mode. */
 998 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
 999                                 enum bcmgenet_power_mode mode)
1000 {
1001         int ret = 0;
1002         u32 reg;
1003
1004         switch (mode) {
1005         case GENET_POWER_CABLE_SENSE:
1006                 phy_detach(priv->phydev);
1007                 break;
1008
1009         case GENET_POWER_WOL_MAGIC:
1010                 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1011                 break;
1012
1013         case GENET_POWER_PASSIVE:
1014                 /* Power down LED */
1015                 if (priv->hw_params->flags & GENET_HAS_EXT) {
1016                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1017                         reg |= (EXT_PWR_DOWN_PHY |
1018                                 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1019                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1020
1021                         bcmgenet_phy_power_set(priv->dev, false);
1022                 }
1023                 break;
1024         default:
1025                 break;
1026         }
1027
1028         return 0;
1029 }
1030
1031 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1032                               enum bcmgenet_power_mode mode)
1033 {
1034         u32 reg;
1035
1036         if (!(priv->hw_params->flags & GENET_HAS_EXT))
1037                 return;
1038
1039         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1040
1041         switch (mode) {
1042         case GENET_POWER_PASSIVE:
1043                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
1044                                 EXT_PWR_DOWN_BIAS);
1045                 /* fallthrough */
1046         case GENET_POWER_CABLE_SENSE:
1047                 /* enable APD */
1048                 reg |= EXT_PWR_DN_EN_LD;
1049                 break;
1050         case GENET_POWER_WOL_MAGIC:
1051                 bcmgenet_wol_power_up_cfg(priv, mode);
1052                 return;
1053         default:
1054                 break;
1055         }
1056
1057         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1058         if (mode == GENET_POWER_PASSIVE) {
1059                 bcmgenet_phy_power_set(priv->dev, true);
1060                 bcmgenet_mii_reset(priv->dev);
1061         }
1062 }
1063
1064 /* ioctl handle special commands that are not present in ethtool. */
1065 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1066 {
1067         struct bcmgenet_priv *priv = netdev_priv(dev);
1068         int val = 0;
1069
1070         if (!netif_running(dev))
1071                 return -EINVAL;
1072
1073         switch (cmd) {
1074         case SIOCGMIIPHY:
1075         case SIOCGMIIREG:
1076         case SIOCSMIIREG:
1077                 if (!priv->phydev)
1078                         val = -ENODEV;
1079                 else
1080                         val = phy_mii_ioctl(priv->phydev, rq, cmd);
1081                 break;
1082
1083         default:
1084                 val = -EINVAL;
1085                 break;
1086         }
1087
1088         return val;
1089 }
1090
1091 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1092                                          struct bcmgenet_tx_ring *ring)
1093 {
1094         struct enet_cb *tx_cb_ptr;
1095
1096         tx_cb_ptr = ring->cbs;
1097         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1098
1099         /* Advancing local write pointer */
1100         if (ring->write_ptr == ring->end_ptr)
1101                 ring->write_ptr = ring->cb_ptr;
1102         else
1103                 ring->write_ptr++;
1104
1105         return tx_cb_ptr;
1106 }
1107
1108 /* Simple helper to free a control block's resources */
1109 static void bcmgenet_free_cb(struct enet_cb *cb)
1110 {
1111         dev_kfree_skb_any(cb->skb);
1112         cb->skb = NULL;
1113         dma_unmap_addr_set(cb, dma_addr, 0);
1114 }
1115
1116 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1117 {
1118         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1119                                  INTRL2_CPU_MASK_SET);
1120 }
1121
1122 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1123 {
1124         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1125                                  INTRL2_CPU_MASK_CLEAR);
1126 }
1127
1128 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1129 {
1130         bcmgenet_intrl2_1_writel(ring->priv,
1131                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1132                                  INTRL2_CPU_MASK_SET);
1133 }
1134
1135 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1136 {
1137         bcmgenet_intrl2_1_writel(ring->priv,
1138                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1139                                  INTRL2_CPU_MASK_CLEAR);
1140 }
1141
1142 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1143 {
1144         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1145                                  INTRL2_CPU_MASK_SET);
1146 }
1147
1148 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1149 {
1150         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1151                                  INTRL2_CPU_MASK_CLEAR);
1152 }
1153
1154 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1155 {
1156         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1157                                  INTRL2_CPU_MASK_CLEAR);
1158 }
1159
1160 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1161 {
1162         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1163                                  INTRL2_CPU_MASK_SET);
1164 }
1165
1166 /* Unlocked version of the reclaim routine */
1167 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1168                                           struct bcmgenet_tx_ring *ring)
1169 {
1170         struct bcmgenet_priv *priv = netdev_priv(dev);
1171         struct device *kdev = &priv->pdev->dev;
1172         struct enet_cb *tx_cb_ptr;
1173         struct netdev_queue *txq;
1174         unsigned int pkts_compl = 0;
1175         unsigned int c_index;
1176         unsigned int txbds_ready;
1177         unsigned int txbds_processed = 0;
1178
1179         /* Compute how many buffers are transmitted since last xmit call */
1180         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
1181         c_index &= DMA_C_INDEX_MASK;
1182
1183         if (likely(c_index >= ring->c_index))
1184                 txbds_ready = c_index - ring->c_index;
1185         else
1186                 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1187
1188         netif_dbg(priv, tx_done, dev,
1189                   "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1190                   __func__, ring->index, ring->c_index, c_index, txbds_ready);
1191
1192         /* Reclaim transmitted buffers */
1193         while (txbds_processed < txbds_ready) {
1194                 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1195                 if (tx_cb_ptr->skb) {
1196                         pkts_compl++;
1197                         dev->stats.tx_packets++;
1198                         dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1199                         dma_unmap_single(kdev,
1200                                          dma_unmap_addr(tx_cb_ptr, dma_addr),
1201                                          dma_unmap_len(tx_cb_ptr, dma_len),
1202                                          DMA_TO_DEVICE);
1203                         bcmgenet_free_cb(tx_cb_ptr);
1204                 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1205                         dev->stats.tx_bytes +=
1206                                 dma_unmap_len(tx_cb_ptr, dma_len);
1207                         dma_unmap_page(kdev,
1208                                        dma_unmap_addr(tx_cb_ptr, dma_addr),
1209                                        dma_unmap_len(tx_cb_ptr, dma_len),
1210                                        DMA_TO_DEVICE);
1211                         dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1212                 }
1213
1214                 txbds_processed++;
1215                 if (likely(ring->clean_ptr < ring->end_ptr))
1216                         ring->clean_ptr++;
1217                 else
1218                         ring->clean_ptr = ring->cb_ptr;
1219         }
1220
1221         ring->free_bds += txbds_processed;
1222         ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1223
1224         if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1225                 txq = netdev_get_tx_queue(dev, ring->queue);
1226                 if (netif_tx_queue_stopped(txq))
1227                         netif_tx_wake_queue(txq);
1228         }
1229
1230         return pkts_compl;
1231 }
1232
1233 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1234                                 struct bcmgenet_tx_ring *ring)
1235 {
1236         unsigned int released;
1237         unsigned long flags;
1238
1239         spin_lock_irqsave(&ring->lock, flags);
1240         released = __bcmgenet_tx_reclaim(dev, ring);
1241         spin_unlock_irqrestore(&ring->lock, flags);
1242
1243         return released;
1244 }
1245
1246 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1247 {
1248         struct bcmgenet_tx_ring *ring =
1249                 container_of(napi, struct bcmgenet_tx_ring, napi);
1250         unsigned int work_done = 0;
1251
1252         work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1253
1254         if (work_done == 0) {
1255                 napi_complete(napi);
1256                 ring->int_enable(ring);
1257
1258                 return 0;
1259         }
1260
1261         return budget;
1262 }
1263
1264 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1265 {
1266         struct bcmgenet_priv *priv = netdev_priv(dev);
1267         int i;
1268
1269         if (netif_is_multiqueue(dev)) {
1270                 for (i = 0; i < priv->hw_params->tx_queues; i++)
1271                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1272         }
1273
1274         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1275 }
1276
1277 /* Transmits a single SKB (either head of a fragment or a single SKB)
1278  * caller must hold priv->lock
1279  */
1280 static int bcmgenet_xmit_single(struct net_device *dev,
1281                                 struct sk_buff *skb,
1282                                 u16 dma_desc_flags,
1283                                 struct bcmgenet_tx_ring *ring)
1284 {
1285         struct bcmgenet_priv *priv = netdev_priv(dev);
1286         struct device *kdev = &priv->pdev->dev;
1287         struct enet_cb *tx_cb_ptr;
1288         unsigned int skb_len;
1289         dma_addr_t mapping;
1290         u32 length_status;
1291         int ret;
1292
1293         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1294
1295         if (unlikely(!tx_cb_ptr))
1296                 BUG();
1297
1298         tx_cb_ptr->skb = skb;
1299
1300         skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1301
1302         mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1303         ret = dma_mapping_error(kdev, mapping);
1304         if (ret) {
1305                 priv->mib.tx_dma_failed++;
1306                 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1307                 dev_kfree_skb(skb);
1308                 return ret;
1309         }
1310
1311         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1312         dma_unmap_len_set(tx_cb_ptr, dma_len, skb_len);
1313         length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1314                         (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1315                         DMA_TX_APPEND_CRC;
1316
1317         if (skb->ip_summed == CHECKSUM_PARTIAL)
1318                 length_status |= DMA_TX_DO_CSUM;
1319
1320         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1321
1322         return 0;
1323 }
1324
1325 /* Transmit a SKB fragment */
1326 static int bcmgenet_xmit_frag(struct net_device *dev,
1327                               skb_frag_t *frag,
1328                               u16 dma_desc_flags,
1329                               struct bcmgenet_tx_ring *ring)
1330 {
1331         struct bcmgenet_priv *priv = netdev_priv(dev);
1332         struct device *kdev = &priv->pdev->dev;
1333         struct enet_cb *tx_cb_ptr;
1334         dma_addr_t mapping;
1335         int ret;
1336
1337         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1338
1339         if (unlikely(!tx_cb_ptr))
1340                 BUG();
1341         tx_cb_ptr->skb = NULL;
1342
1343         mapping = skb_frag_dma_map(kdev, frag, 0,
1344                                    skb_frag_size(frag), DMA_TO_DEVICE);
1345         ret = dma_mapping_error(kdev, mapping);
1346         if (ret) {
1347                 priv->mib.tx_dma_failed++;
1348                 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1349                           __func__);
1350                 return ret;
1351         }
1352
1353         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1354         dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1355
1356         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1357                     (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1358                     (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1359
1360         return 0;
1361 }
1362
1363 /* Reallocate the SKB to put enough headroom in front of it and insert
1364  * the transmit checksum offsets in the descriptors
1365  */
1366 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1367                                             struct sk_buff *skb)
1368 {
1369         struct status_64 *status = NULL;
1370         struct sk_buff *new_skb;
1371         u16 offset;
1372         u8 ip_proto;
1373         u16 ip_ver;
1374         u32 tx_csum_info;
1375
1376         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1377                 /* If 64 byte status block enabled, must make sure skb has
1378                  * enough headroom for us to insert 64B status block.
1379                  */
1380                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1381                 dev_kfree_skb(skb);
1382                 if (!new_skb) {
1383                         dev->stats.tx_dropped++;
1384                         return NULL;
1385                 }
1386                 skb = new_skb;
1387         }
1388
1389         skb_push(skb, sizeof(*status));
1390         status = (struct status_64 *)skb->data;
1391
1392         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1393                 ip_ver = htons(skb->protocol);
1394                 switch (ip_ver) {
1395                 case ETH_P_IP:
1396                         ip_proto = ip_hdr(skb)->protocol;
1397                         break;
1398                 case ETH_P_IPV6:
1399                         ip_proto = ipv6_hdr(skb)->nexthdr;
1400                         break;
1401                 default:
1402                         return skb;
1403                 }
1404
1405                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1406                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1407                                 (offset + skb->csum_offset);
1408
1409                 /* Set the length valid bit for TCP and UDP and just set
1410                  * the special UDP flag for IPv4, else just set to 0.
1411                  */
1412                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1413                         tx_csum_info |= STATUS_TX_CSUM_LV;
1414                         if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1415                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1416                 } else {
1417                         tx_csum_info = 0;
1418                 }
1419
1420                 status->tx_csum_info = tx_csum_info;
1421         }
1422
1423         return skb;
1424 }
1425
1426 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1427 {
1428         struct bcmgenet_priv *priv = netdev_priv(dev);
1429         struct bcmgenet_tx_ring *ring = NULL;
1430         struct netdev_queue *txq;
1431         unsigned long flags = 0;
1432         int nr_frags, index;
1433         u16 dma_desc_flags;
1434         int ret;
1435         int i;
1436
1437         index = skb_get_queue_mapping(skb);
1438         /* Mapping strategy:
1439          * queue_mapping = 0, unclassified, packet xmited through ring16
1440          * queue_mapping = 1, goes to ring 0. (highest priority queue
1441          * queue_mapping = 2, goes to ring 1.
1442          * queue_mapping = 3, goes to ring 2.
1443          * queue_mapping = 4, goes to ring 3.
1444          */
1445         if (index == 0)
1446                 index = DESC_INDEX;
1447         else
1448                 index -= 1;
1449
1450         nr_frags = skb_shinfo(skb)->nr_frags;
1451         ring = &priv->tx_rings[index];
1452         txq = netdev_get_tx_queue(dev, ring->queue);
1453
1454         spin_lock_irqsave(&ring->lock, flags);
1455         if (ring->free_bds <= nr_frags + 1) {
1456                 netif_tx_stop_queue(txq);
1457                 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1458                            __func__, index, ring->queue);
1459                 ret = NETDEV_TX_BUSY;
1460                 goto out;
1461         }
1462
1463         if (skb_padto(skb, ETH_ZLEN)) {
1464                 ret = NETDEV_TX_OK;
1465                 goto out;
1466         }
1467
1468         /* set the SKB transmit checksum */
1469         if (priv->desc_64b_en) {
1470                 skb = bcmgenet_put_tx_csum(dev, skb);
1471                 if (!skb) {
1472                         ret = NETDEV_TX_OK;
1473                         goto out;
1474                 }
1475         }
1476
1477         dma_desc_flags = DMA_SOP;
1478         if (nr_frags == 0)
1479                 dma_desc_flags |= DMA_EOP;
1480
1481         /* Transmit single SKB or head of fragment list */
1482         ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1483         if (ret) {
1484                 ret = NETDEV_TX_OK;
1485                 goto out;
1486         }
1487
1488         /* xmit fragment */
1489         for (i = 0; i < nr_frags; i++) {
1490                 ret = bcmgenet_xmit_frag(dev,
1491                                          &skb_shinfo(skb)->frags[i],
1492                                          (i == nr_frags - 1) ? DMA_EOP : 0,
1493                                          ring);
1494                 if (ret) {
1495                         ret = NETDEV_TX_OK;
1496                         goto out;
1497                 }
1498         }
1499
1500         skb_tx_timestamp(skb);
1501
1502         /* Decrement total BD count and advance our write pointer */
1503         ring->free_bds -= nr_frags + 1;
1504         ring->prod_index += nr_frags + 1;
1505         ring->prod_index &= DMA_P_INDEX_MASK;
1506
1507         if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1508                 netif_tx_stop_queue(txq);
1509
1510         if (!skb->xmit_more || netif_xmit_stopped(txq))
1511                 /* Packets are ready, update producer index */
1512                 bcmgenet_tdma_ring_writel(priv, ring->index,
1513                                           ring->prod_index, TDMA_PROD_INDEX);
1514 out:
1515         spin_unlock_irqrestore(&ring->lock, flags);
1516
1517         return ret;
1518 }
1519
1520 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1521                                           struct enet_cb *cb)
1522 {
1523         struct device *kdev = &priv->pdev->dev;
1524         struct sk_buff *skb;
1525         struct sk_buff *rx_skb;
1526         dma_addr_t mapping;
1527
1528         /* Allocate a new Rx skb */
1529         skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1530         if (!skb) {
1531                 priv->mib.alloc_rx_buff_failed++;
1532                 netif_err(priv, rx_err, priv->dev,
1533                           "%s: Rx skb allocation failed\n", __func__);
1534                 return NULL;
1535         }
1536
1537         /* DMA-map the new Rx skb */
1538         mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1539                                  DMA_FROM_DEVICE);
1540         if (dma_mapping_error(kdev, mapping)) {
1541                 priv->mib.rx_dma_failed++;
1542                 dev_kfree_skb_any(skb);
1543                 netif_err(priv, rx_err, priv->dev,
1544                           "%s: Rx skb DMA mapping failed\n", __func__);
1545                 return NULL;
1546         }
1547
1548         /* Grab the current Rx skb from the ring and DMA-unmap it */
1549         rx_skb = cb->skb;
1550         if (likely(rx_skb))
1551                 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1552                                  priv->rx_buf_len, DMA_FROM_DEVICE);
1553
1554         /* Put the new Rx skb on the ring */
1555         cb->skb = skb;
1556         dma_unmap_addr_set(cb, dma_addr, mapping);
1557         dmadesc_set_addr(priv, cb->bd_addr, mapping);
1558
1559         /* Return the current Rx skb to caller */
1560         return rx_skb;
1561 }
1562
1563 /* bcmgenet_desc_rx - descriptor based rx process.
1564  * this could be called from bottom half, or from NAPI polling method.
1565  */
1566 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1567                                      unsigned int budget)
1568 {
1569         struct bcmgenet_priv *priv = ring->priv;
1570         struct net_device *dev = priv->dev;
1571         struct enet_cb *cb;
1572         struct sk_buff *skb;
1573         u32 dma_length_status;
1574         unsigned long dma_flag;
1575         int len;
1576         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1577         unsigned int p_index;
1578         unsigned int discards;
1579         unsigned int chksum_ok = 0;
1580
1581         p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1582
1583         discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1584                    DMA_P_INDEX_DISCARD_CNT_MASK;
1585         if (discards > ring->old_discards) {
1586                 discards = discards - ring->old_discards;
1587                 dev->stats.rx_missed_errors += discards;
1588                 dev->stats.rx_errors += discards;
1589                 ring->old_discards += discards;
1590
1591                 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1592                 if (ring->old_discards >= 0xC000) {
1593                         ring->old_discards = 0;
1594                         bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1595                                                   RDMA_PROD_INDEX);
1596                 }
1597         }
1598
1599         p_index &= DMA_P_INDEX_MASK;
1600
1601         if (likely(p_index >= ring->c_index))
1602                 rxpkttoprocess = p_index - ring->c_index;
1603         else
1604                 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1605                                  p_index;
1606
1607         netif_dbg(priv, rx_status, dev,
1608                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1609
1610         while ((rxpktprocessed < rxpkttoprocess) &&
1611                (rxpktprocessed < budget)) {
1612                 cb = &priv->rx_cbs[ring->read_ptr];
1613                 skb = bcmgenet_rx_refill(priv, cb);
1614
1615                 if (unlikely(!skb)) {
1616                         dev->stats.rx_dropped++;
1617                         goto next;
1618                 }
1619
1620                 if (!priv->desc_64b_en) {
1621                         dma_length_status =
1622                                 dmadesc_get_length_status(priv, cb->bd_addr);
1623                 } else {
1624                         struct status_64 *status;
1625
1626                         status = (struct status_64 *)skb->data;
1627                         dma_length_status = status->length_status;
1628                 }
1629
1630                 /* DMA flags and length are still valid no matter how
1631                  * we got the Receive Status Vector (64B RSB or register)
1632                  */
1633                 dma_flag = dma_length_status & 0xffff;
1634                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1635
1636                 netif_dbg(priv, rx_status, dev,
1637                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1638                           __func__, p_index, ring->c_index,
1639                           ring->read_ptr, dma_length_status);
1640
1641                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1642                         netif_err(priv, rx_status, dev,
1643                                   "dropping fragmented packet!\n");
1644                         dev->stats.rx_errors++;
1645                         dev_kfree_skb_any(skb);
1646                         goto next;
1647                 }
1648
1649                 /* report errors */
1650                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1651                                                 DMA_RX_OV |
1652                                                 DMA_RX_NO |
1653                                                 DMA_RX_LG |
1654                                                 DMA_RX_RXER))) {
1655                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1656                                   (unsigned int)dma_flag);
1657                         if (dma_flag & DMA_RX_CRC_ERROR)
1658                                 dev->stats.rx_crc_errors++;
1659                         if (dma_flag & DMA_RX_OV)
1660                                 dev->stats.rx_over_errors++;
1661                         if (dma_flag & DMA_RX_NO)
1662                                 dev->stats.rx_frame_errors++;
1663                         if (dma_flag & DMA_RX_LG)
1664                                 dev->stats.rx_length_errors++;
1665                         dev->stats.rx_errors++;
1666                         dev_kfree_skb_any(skb);
1667                         goto next;
1668                 } /* error packet */
1669
1670                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1671                              priv->desc_rxchk_en;
1672
1673                 skb_put(skb, len);
1674                 if (priv->desc_64b_en) {
1675                         skb_pull(skb, 64);
1676                         len -= 64;
1677                 }
1678
1679                 if (likely(chksum_ok))
1680                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1681
1682                 /* remove hardware 2bytes added for IP alignment */
1683                 skb_pull(skb, 2);
1684                 len -= 2;
1685
1686                 if (priv->crc_fwd_en) {
1687                         skb_trim(skb, len - ETH_FCS_LEN);
1688                         len -= ETH_FCS_LEN;
1689                 }
1690
1691                 /*Finish setting up the received SKB and send it to the kernel*/
1692                 skb->protocol = eth_type_trans(skb, priv->dev);
1693                 dev->stats.rx_packets++;
1694                 dev->stats.rx_bytes += len;
1695                 if (dma_flag & DMA_RX_MULT)
1696                         dev->stats.multicast++;
1697
1698                 /* Notify kernel */
1699                 napi_gro_receive(&ring->napi, skb);
1700                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1701
1702 next:
1703                 rxpktprocessed++;
1704                 if (likely(ring->read_ptr < ring->end_ptr))
1705                         ring->read_ptr++;
1706                 else
1707                         ring->read_ptr = ring->cb_ptr;
1708
1709                 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1710                 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1711         }
1712
1713         return rxpktprocessed;
1714 }
1715
1716 /* Rx NAPI polling method */
1717 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1718 {
1719         struct bcmgenet_rx_ring *ring = container_of(napi,
1720                         struct bcmgenet_rx_ring, napi);
1721         unsigned int work_done;
1722
1723         work_done = bcmgenet_desc_rx(ring, budget);
1724
1725         if (work_done < budget) {
1726                 napi_complete(napi);
1727                 ring->int_enable(ring);
1728         }
1729
1730         return work_done;
1731 }
1732
1733 /* Assign skb to RX DMA descriptor. */
1734 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1735                                      struct bcmgenet_rx_ring *ring)
1736 {
1737         struct enet_cb *cb;
1738         struct sk_buff *skb;
1739         int i;
1740
1741         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1742
1743         /* loop here for each buffer needing assign */
1744         for (i = 0; i < ring->size; i++) {
1745                 cb = ring->cbs + i;
1746                 skb = bcmgenet_rx_refill(priv, cb);
1747                 if (skb)
1748                         dev_kfree_skb_any(skb);
1749                 if (!cb->skb)
1750                         return -ENOMEM;
1751         }
1752
1753         return 0;
1754 }
1755
1756 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1757 {
1758         struct device *kdev = &priv->pdev->dev;
1759         struct enet_cb *cb;
1760         int i;
1761
1762         for (i = 0; i < priv->num_rx_bds; i++) {
1763                 cb = &priv->rx_cbs[i];
1764
1765                 if (dma_unmap_addr(cb, dma_addr)) {
1766                         dma_unmap_single(kdev,
1767                                          dma_unmap_addr(cb, dma_addr),
1768                                          priv->rx_buf_len, DMA_FROM_DEVICE);
1769                         dma_unmap_addr_set(cb, dma_addr, 0);
1770                 }
1771
1772                 if (cb->skb)
1773                         bcmgenet_free_cb(cb);
1774         }
1775 }
1776
1777 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1778 {
1779         u32 reg;
1780
1781         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1782         if (enable)
1783                 reg |= mask;
1784         else
1785                 reg &= ~mask;
1786         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1787
1788         /* UniMAC stops on a packet boundary, wait for a full-size packet
1789          * to be processed
1790          */
1791         if (enable == 0)
1792                 usleep_range(1000, 2000);
1793 }
1794
1795 static int reset_umac(struct bcmgenet_priv *priv)
1796 {
1797         struct device *kdev = &priv->pdev->dev;
1798         unsigned int timeout = 0;
1799         u32 reg;
1800
1801         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1802         bcmgenet_rbuf_ctrl_set(priv, 0);
1803         udelay(10);
1804
1805         /* disable MAC while updating its registers */
1806         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1807
1808         /* issue soft reset, wait for it to complete */
1809         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1810         while (timeout++ < 1000) {
1811                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1812                 if (!(reg & CMD_SW_RESET))
1813                         return 0;
1814
1815                 udelay(1);
1816         }
1817
1818         if (timeout == 1000) {
1819                 dev_err(kdev,
1820                         "timeout waiting for MAC to come out of reset\n");
1821                 return -ETIMEDOUT;
1822         }
1823
1824         return 0;
1825 }
1826
1827 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1828 {
1829         /* Mask all interrupts.*/
1830         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1831         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1832         bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1833         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1834         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1835         bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1836 }
1837
1838 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1839 {
1840         u32 int0_enable = 0;
1841
1842         /* Monitor cable plug/unplugged event for internal PHY, external PHY
1843          * and MoCA PHY
1844          */
1845         if (priv->internal_phy) {
1846                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1847         } else if (priv->ext_phy) {
1848                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1849         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1850                 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1851                         int0_enable |= UMAC_IRQ_LINK_EVENT;
1852         }
1853         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1854 }
1855
1856 static int init_umac(struct bcmgenet_priv *priv)
1857 {
1858         struct device *kdev = &priv->pdev->dev;
1859         int ret;
1860         u32 reg;
1861         u32 int0_enable = 0;
1862         u32 int1_enable = 0;
1863         int i;
1864
1865         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1866
1867         ret = reset_umac(priv);
1868         if (ret)
1869                 return ret;
1870
1871         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1872         /* clear tx/rx counter */
1873         bcmgenet_umac_writel(priv,
1874                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1875                              UMAC_MIB_CTRL);
1876         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1877
1878         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1879
1880         /* init rx registers, enable ip header optimization */
1881         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1882         reg |= RBUF_ALIGN_2B;
1883         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1884
1885         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1886                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1887
1888         bcmgenet_intr_disable(priv);
1889
1890         /* Enable Rx default queue 16 interrupts */
1891         int0_enable |= UMAC_IRQ_RXDMA_DONE;
1892
1893         /* Enable Tx default queue 16 interrupts */
1894         int0_enable |= UMAC_IRQ_TXDMA_DONE;
1895
1896         /* Configure backpressure vectors for MoCA */
1897         if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1898                 reg = bcmgenet_bp_mc_get(priv);
1899                 reg |= BIT(priv->hw_params->bp_in_en_shift);
1900
1901                 /* bp_mask: back pressure mask */
1902                 if (netif_is_multiqueue(priv->dev))
1903                         reg |= priv->hw_params->bp_in_mask;
1904                 else
1905                         reg &= ~priv->hw_params->bp_in_mask;
1906                 bcmgenet_bp_mc_set(priv, reg);
1907         }
1908
1909         /* Enable MDIO interrupts on GENET v3+ */
1910         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1911                 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1912
1913         /* Enable Rx priority queue interrupts */
1914         for (i = 0; i < priv->hw_params->rx_queues; ++i)
1915                 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1916
1917         /* Enable Tx priority queue interrupts */
1918         for (i = 0; i < priv->hw_params->tx_queues; ++i)
1919                 int1_enable |= (1 << i);
1920
1921         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1922         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
1923
1924         /* Enable rx/tx engine.*/
1925         dev_dbg(kdev, "done init umac\n");
1926
1927         return 0;
1928 }
1929
1930 /* Initialize a Tx ring along with corresponding hardware registers */
1931 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1932                                   unsigned int index, unsigned int size,
1933                                   unsigned int start_ptr, unsigned int end_ptr)
1934 {
1935         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1936         u32 words_per_bd = WORDS_PER_BD(priv);
1937         u32 flow_period_val = 0;
1938
1939         spin_lock_init(&ring->lock);
1940         ring->priv = priv;
1941         ring->index = index;
1942         if (index == DESC_INDEX) {
1943                 ring->queue = 0;
1944                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1945                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1946         } else {
1947                 ring->queue = index + 1;
1948                 ring->int_enable = bcmgenet_tx_ring_int_enable;
1949                 ring->int_disable = bcmgenet_tx_ring_int_disable;
1950         }
1951         ring->cbs = priv->tx_cbs + start_ptr;
1952         ring->size = size;
1953         ring->clean_ptr = start_ptr;
1954         ring->c_index = 0;
1955         ring->free_bds = size;
1956         ring->write_ptr = start_ptr;
1957         ring->cb_ptr = start_ptr;
1958         ring->end_ptr = end_ptr - 1;
1959         ring->prod_index = 0;
1960
1961         /* Set flow period for ring != 16 */
1962         if (index != DESC_INDEX)
1963                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1964
1965         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1966         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1967         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1968         /* Disable rate control for now */
1969         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1970                                   TDMA_FLOW_PERIOD);
1971         bcmgenet_tdma_ring_writel(priv, index,
1972                                   ((size << DMA_RING_SIZE_SHIFT) |
1973                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1974
1975         /* Set start and end address, read and write pointers */
1976         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1977                                   DMA_START_ADDR);
1978         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1979                                   TDMA_READ_PTR);
1980         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1981                                   TDMA_WRITE_PTR);
1982         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1983                                   DMA_END_ADDR);
1984 }
1985
1986 /* Initialize a RDMA ring */
1987 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1988                                  unsigned int index, unsigned int size,
1989                                  unsigned int start_ptr, unsigned int end_ptr)
1990 {
1991         struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1992         u32 words_per_bd = WORDS_PER_BD(priv);
1993         int ret;
1994
1995         ring->priv = priv;
1996         ring->index = index;
1997         if (index == DESC_INDEX) {
1998                 ring->int_enable = bcmgenet_rx_ring16_int_enable;
1999                 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2000         } else {
2001                 ring->int_enable = bcmgenet_rx_ring_int_enable;
2002                 ring->int_disable = bcmgenet_rx_ring_int_disable;
2003         }
2004         ring->cbs = priv->rx_cbs + start_ptr;
2005         ring->size = size;
2006         ring->c_index = 0;
2007         ring->read_ptr = start_ptr;
2008         ring->cb_ptr = start_ptr;
2009         ring->end_ptr = end_ptr - 1;
2010
2011         ret = bcmgenet_alloc_rx_buffers(priv, ring);
2012         if (ret)
2013                 return ret;
2014
2015         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2016         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2017         bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2018         bcmgenet_rdma_ring_writel(priv, index,
2019                                   ((size << DMA_RING_SIZE_SHIFT) |
2020                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2021         bcmgenet_rdma_ring_writel(priv, index,
2022                                   (DMA_FC_THRESH_LO <<
2023                                    DMA_XOFF_THRESHOLD_SHIFT) |
2024                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2025
2026         /* Set start and end address, read and write pointers */
2027         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2028                                   DMA_START_ADDR);
2029         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2030                                   RDMA_READ_PTR);
2031         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2032                                   RDMA_WRITE_PTR);
2033         bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2034                                   DMA_END_ADDR);
2035
2036         return ret;
2037 }
2038
2039 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2040 {
2041         unsigned int i;
2042         struct bcmgenet_tx_ring *ring;
2043
2044         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2045                 ring = &priv->tx_rings[i];
2046                 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2047         }
2048
2049         ring = &priv->tx_rings[DESC_INDEX];
2050         netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2051 }
2052
2053 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2054 {
2055         unsigned int i;
2056         struct bcmgenet_tx_ring *ring;
2057
2058         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2059                 ring = &priv->tx_rings[i];
2060                 napi_enable(&ring->napi);
2061         }
2062
2063         ring = &priv->tx_rings[DESC_INDEX];
2064         napi_enable(&ring->napi);
2065 }
2066
2067 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2068 {
2069         unsigned int i;
2070         struct bcmgenet_tx_ring *ring;
2071
2072         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2073                 ring = &priv->tx_rings[i];
2074                 napi_disable(&ring->napi);
2075         }
2076
2077         ring = &priv->tx_rings[DESC_INDEX];
2078         napi_disable(&ring->napi);
2079 }
2080
2081 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2082 {
2083         unsigned int i;
2084         struct bcmgenet_tx_ring *ring;
2085
2086         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2087                 ring = &priv->tx_rings[i];
2088                 netif_napi_del(&ring->napi);
2089         }
2090
2091         ring = &priv->tx_rings[DESC_INDEX];
2092         netif_napi_del(&ring->napi);
2093 }
2094
2095 /* Initialize Tx queues
2096  *
2097  * Queues 0-3 are priority-based, each one has 32 descriptors,
2098  * with queue 0 being the highest priority queue.
2099  *
2100  * Queue 16 is the default Tx queue with
2101  * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2102  *
2103  * The transmit control block pool is then partitioned as follows:
2104  * - Tx queue 0 uses tx_cbs[0..31]
2105  * - Tx queue 1 uses tx_cbs[32..63]
2106  * - Tx queue 2 uses tx_cbs[64..95]
2107  * - Tx queue 3 uses tx_cbs[96..127]
2108  * - Tx queue 16 uses tx_cbs[128..255]
2109  */
2110 static void bcmgenet_init_tx_queues(struct net_device *dev)
2111 {
2112         struct bcmgenet_priv *priv = netdev_priv(dev);
2113         u32 i, dma_enable;
2114         u32 dma_ctrl, ring_cfg;
2115         u32 dma_priority[3] = {0, 0, 0};
2116
2117         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2118         dma_enable = dma_ctrl & DMA_EN;
2119         dma_ctrl &= ~DMA_EN;
2120         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2121
2122         dma_ctrl = 0;
2123         ring_cfg = 0;
2124
2125         /* Enable strict priority arbiter mode */
2126         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2127
2128         /* Initialize Tx priority queues */
2129         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2130                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2131                                       i * priv->hw_params->tx_bds_per_q,
2132                                       (i + 1) * priv->hw_params->tx_bds_per_q);
2133                 ring_cfg |= (1 << i);
2134                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2135                 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2136                         ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2137         }
2138
2139         /* Initialize Tx default queue 16 */
2140         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2141                               priv->hw_params->tx_queues *
2142                               priv->hw_params->tx_bds_per_q,
2143                               TOTAL_DESC);
2144         ring_cfg |= (1 << DESC_INDEX);
2145         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2146         dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2147                 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2148                  DMA_PRIO_REG_SHIFT(DESC_INDEX));
2149
2150         /* Set Tx queue priorities */
2151         bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2152         bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2153         bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2154
2155         /* Initialize Tx NAPI */
2156         bcmgenet_init_tx_napi(priv);
2157
2158         /* Enable Tx queues */
2159         bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2160
2161         /* Enable Tx DMA */
2162         if (dma_enable)
2163                 dma_ctrl |= DMA_EN;
2164         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2165 }
2166
2167 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2168 {
2169         unsigned int i;
2170         struct bcmgenet_rx_ring *ring;
2171
2172         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2173                 ring = &priv->rx_rings[i];
2174                 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2175         }
2176
2177         ring = &priv->rx_rings[DESC_INDEX];
2178         netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2179 }
2180
2181 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2182 {
2183         unsigned int i;
2184         struct bcmgenet_rx_ring *ring;
2185
2186         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2187                 ring = &priv->rx_rings[i];
2188                 napi_enable(&ring->napi);
2189         }
2190
2191         ring = &priv->rx_rings[DESC_INDEX];
2192         napi_enable(&ring->napi);
2193 }
2194
2195 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2196 {
2197         unsigned int i;
2198         struct bcmgenet_rx_ring *ring;
2199
2200         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2201                 ring = &priv->rx_rings[i];
2202                 napi_disable(&ring->napi);
2203         }
2204
2205         ring = &priv->rx_rings[DESC_INDEX];
2206         napi_disable(&ring->napi);
2207 }
2208
2209 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2210 {
2211         unsigned int i;
2212         struct bcmgenet_rx_ring *ring;
2213
2214         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2215                 ring = &priv->rx_rings[i];
2216                 netif_napi_del(&ring->napi);
2217         }
2218
2219         ring = &priv->rx_rings[DESC_INDEX];
2220         netif_napi_del(&ring->napi);
2221 }
2222
2223 /* Initialize Rx queues
2224  *
2225  * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2226  * used to direct traffic to these queues.
2227  *
2228  * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2229  */
2230 static int bcmgenet_init_rx_queues(struct net_device *dev)
2231 {
2232         struct bcmgenet_priv *priv = netdev_priv(dev);
2233         u32 i;
2234         u32 dma_enable;
2235         u32 dma_ctrl;
2236         u32 ring_cfg;
2237         int ret;
2238
2239         dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2240         dma_enable = dma_ctrl & DMA_EN;
2241         dma_ctrl &= ~DMA_EN;
2242         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2243
2244         dma_ctrl = 0;
2245         ring_cfg = 0;
2246
2247         /* Initialize Rx priority queues */
2248         for (i = 0; i < priv->hw_params->rx_queues; i++) {
2249                 ret = bcmgenet_init_rx_ring(priv, i,
2250                                             priv->hw_params->rx_bds_per_q,
2251                                             i * priv->hw_params->rx_bds_per_q,
2252                                             (i + 1) *
2253                                             priv->hw_params->rx_bds_per_q);
2254                 if (ret)
2255                         return ret;
2256
2257                 ring_cfg |= (1 << i);
2258                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2259         }
2260
2261         /* Initialize Rx default queue 16 */
2262         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2263                                     priv->hw_params->rx_queues *
2264                                     priv->hw_params->rx_bds_per_q,
2265                                     TOTAL_DESC);
2266         if (ret)
2267                 return ret;
2268
2269         ring_cfg |= (1 << DESC_INDEX);
2270         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2271
2272         /* Initialize Rx NAPI */
2273         bcmgenet_init_rx_napi(priv);
2274
2275         /* Enable rings */
2276         bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2277
2278         /* Configure ring as descriptor ring and re-enable DMA if enabled */
2279         if (dma_enable)
2280                 dma_ctrl |= DMA_EN;
2281         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2282
2283         return 0;
2284 }
2285
2286 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2287 {
2288         int ret = 0;
2289         int timeout = 0;
2290         u32 reg;
2291         u32 dma_ctrl;
2292         int i;
2293
2294         /* Disable TDMA to stop add more frames in TX DMA */
2295         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2296         reg &= ~DMA_EN;
2297         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2298
2299         /* Check TDMA status register to confirm TDMA is disabled */
2300         while (timeout++ < DMA_TIMEOUT_VAL) {
2301                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2302                 if (reg & DMA_DISABLED)
2303                         break;
2304
2305                 udelay(1);
2306         }
2307
2308         if (timeout == DMA_TIMEOUT_VAL) {
2309                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2310                 ret = -ETIMEDOUT;
2311         }
2312
2313         /* Wait 10ms for packet drain in both tx and rx dma */
2314         usleep_range(10000, 20000);
2315
2316         /* Disable RDMA */
2317         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2318         reg &= ~DMA_EN;
2319         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2320
2321         timeout = 0;
2322         /* Check RDMA status register to confirm RDMA is disabled */
2323         while (timeout++ < DMA_TIMEOUT_VAL) {
2324                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2325                 if (reg & DMA_DISABLED)
2326                         break;
2327
2328                 udelay(1);
2329         }
2330
2331         if (timeout == DMA_TIMEOUT_VAL) {
2332                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2333                 ret = -ETIMEDOUT;
2334         }
2335
2336         dma_ctrl = 0;
2337         for (i = 0; i < priv->hw_params->rx_queues; i++)
2338                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2339         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2340         reg &= ~dma_ctrl;
2341         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2342
2343         dma_ctrl = 0;
2344         for (i = 0; i < priv->hw_params->tx_queues; i++)
2345                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2346         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2347         reg &= ~dma_ctrl;
2348         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2349
2350         return ret;
2351 }
2352
2353 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2354 {
2355         int i;
2356
2357         bcmgenet_fini_rx_napi(priv);
2358         bcmgenet_fini_tx_napi(priv);
2359
2360         /* disable DMA */
2361         bcmgenet_dma_teardown(priv);
2362
2363         for (i = 0; i < priv->num_tx_bds; i++) {
2364                 if (priv->tx_cbs[i].skb != NULL) {
2365                         dev_kfree_skb(priv->tx_cbs[i].skb);
2366                         priv->tx_cbs[i].skb = NULL;
2367                 }
2368         }
2369
2370         bcmgenet_free_rx_buffers(priv);
2371         kfree(priv->rx_cbs);
2372         kfree(priv->tx_cbs);
2373 }
2374
2375 /* init_edma: Initialize DMA control register */
2376 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2377 {
2378         int ret;
2379         unsigned int i;
2380         struct enet_cb *cb;
2381
2382         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2383
2384         /* Initialize common Rx ring structures */
2385         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2386         priv->num_rx_bds = TOTAL_DESC;
2387         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2388                                GFP_KERNEL);
2389         if (!priv->rx_cbs)
2390                 return -ENOMEM;
2391
2392         for (i = 0; i < priv->num_rx_bds; i++) {
2393                 cb = priv->rx_cbs + i;
2394                 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2395         }
2396
2397         /* Initialize common TX ring structures */
2398         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2399         priv->num_tx_bds = TOTAL_DESC;
2400         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2401                                GFP_KERNEL);
2402         if (!priv->tx_cbs) {
2403                 kfree(priv->rx_cbs);
2404                 return -ENOMEM;
2405         }
2406
2407         for (i = 0; i < priv->num_tx_bds; i++) {
2408                 cb = priv->tx_cbs + i;
2409                 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2410         }
2411
2412         /* Init rDma */
2413         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2414
2415         /* Initialize Rx queues */
2416         ret = bcmgenet_init_rx_queues(priv->dev);
2417         if (ret) {
2418                 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2419                 bcmgenet_free_rx_buffers(priv);
2420                 kfree(priv->rx_cbs);
2421                 kfree(priv->tx_cbs);
2422                 return ret;
2423         }
2424
2425         /* Init tDma */
2426         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2427
2428         /* Initialize Tx queues */
2429         bcmgenet_init_tx_queues(priv->dev);
2430
2431         return 0;
2432 }
2433
2434 /* Interrupt bottom half */
2435 static void bcmgenet_irq_task(struct work_struct *work)
2436 {
2437         struct bcmgenet_priv *priv = container_of(
2438                         work, struct bcmgenet_priv, bcmgenet_irq_work);
2439
2440         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2441
2442         if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2443                 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2444                 netif_dbg(priv, wol, priv->dev,
2445                           "magic packet detected, waking up\n");
2446                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2447         }
2448
2449         /* Link UP/DOWN event */
2450         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2451             (priv->irq0_stat & UMAC_IRQ_LINK_EVENT)) {
2452                 phy_mac_interrupt(priv->phydev,
2453                                   !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
2454                 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
2455         }
2456 }
2457
2458 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2459 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2460 {
2461         struct bcmgenet_priv *priv = dev_id;
2462         struct bcmgenet_rx_ring *rx_ring;
2463         struct bcmgenet_tx_ring *tx_ring;
2464         unsigned int index;
2465
2466         /* Save irq status for bottom-half processing. */
2467         priv->irq1_stat =
2468                 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2469                 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2470
2471         /* clear interrupts */
2472         bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2473
2474         netif_dbg(priv, intr, priv->dev,
2475                   "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
2476
2477         /* Check Rx priority queue interrupts */
2478         for (index = 0; index < priv->hw_params->rx_queues; index++) {
2479                 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2480                         continue;
2481
2482                 rx_ring = &priv->rx_rings[index];
2483
2484                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2485                         rx_ring->int_disable(rx_ring);
2486                         __napi_schedule(&rx_ring->napi);
2487                 }
2488         }
2489
2490         /* Check Tx priority queue interrupts */
2491         for (index = 0; index < priv->hw_params->tx_queues; index++) {
2492                 if (!(priv->irq1_stat & BIT(index)))
2493                         continue;
2494
2495                 tx_ring = &priv->tx_rings[index];
2496
2497                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2498                         tx_ring->int_disable(tx_ring);
2499                         __napi_schedule(&tx_ring->napi);
2500                 }
2501         }
2502
2503         return IRQ_HANDLED;
2504 }
2505
2506 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2507 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2508 {
2509         struct bcmgenet_priv *priv = dev_id;
2510         struct bcmgenet_rx_ring *rx_ring;
2511         struct bcmgenet_tx_ring *tx_ring;
2512
2513         /* Save irq status for bottom-half processing. */
2514         priv->irq0_stat =
2515                 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2516                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2517
2518         /* clear interrupts */
2519         bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2520
2521         netif_dbg(priv, intr, priv->dev,
2522                   "IRQ=0x%x\n", priv->irq0_stat);
2523
2524         if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
2525                 rx_ring = &priv->rx_rings[DESC_INDEX];
2526
2527                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2528                         rx_ring->int_disable(rx_ring);
2529                         __napi_schedule(&rx_ring->napi);
2530                 }
2531         }
2532
2533         if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
2534                 tx_ring = &priv->tx_rings[DESC_INDEX];
2535
2536                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2537                         tx_ring->int_disable(tx_ring);
2538                         __napi_schedule(&tx_ring->napi);
2539                 }
2540         }
2541
2542         if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2543                                 UMAC_IRQ_PHY_DET_F |
2544                                 UMAC_IRQ_LINK_EVENT |
2545                                 UMAC_IRQ_HFB_SM |
2546                                 UMAC_IRQ_HFB_MM |
2547                                 UMAC_IRQ_MPD_R)) {
2548                 /* all other interested interrupts handled in bottom half */
2549                 schedule_work(&priv->bcmgenet_irq_work);
2550         }
2551
2552         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2553             priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2554                 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2555                 wake_up(&priv->wq);
2556         }
2557
2558         return IRQ_HANDLED;
2559 }
2560
2561 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2562 {
2563         struct bcmgenet_priv *priv = dev_id;
2564
2565         pm_wakeup_event(&priv->pdev->dev, 0);
2566
2567         return IRQ_HANDLED;
2568 }
2569
2570 #ifdef CONFIG_NET_POLL_CONTROLLER
2571 static void bcmgenet_poll_controller(struct net_device *dev)
2572 {
2573         struct bcmgenet_priv *priv = netdev_priv(dev);
2574
2575         /* Invoke the main RX/TX interrupt handler */
2576         disable_irq(priv->irq0);
2577         bcmgenet_isr0(priv->irq0, priv);
2578         enable_irq(priv->irq0);
2579
2580         /* And the interrupt handler for RX/TX priority queues */
2581         disable_irq(priv->irq1);
2582         bcmgenet_isr1(priv->irq1, priv);
2583         enable_irq(priv->irq1);
2584 }
2585 #endif
2586
2587 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2588 {
2589         u32 reg;
2590
2591         reg = bcmgenet_rbuf_ctrl_get(priv);
2592         reg |= BIT(1);
2593         bcmgenet_rbuf_ctrl_set(priv, reg);
2594         udelay(10);
2595
2596         reg &= ~BIT(1);
2597         bcmgenet_rbuf_ctrl_set(priv, reg);
2598         udelay(10);
2599 }
2600
2601 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2602                                  unsigned char *addr)
2603 {
2604         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2605                         (addr[2] << 8) | addr[3], UMAC_MAC0);
2606         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2607 }
2608
2609 /* Returns a reusable dma control register value */
2610 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2611 {
2612         u32 reg;
2613         u32 dma_ctrl;
2614
2615         /* disable DMA */
2616         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2617         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2618         reg &= ~dma_ctrl;
2619         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2620
2621         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2622         reg &= ~dma_ctrl;
2623         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2624
2625         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2626         udelay(10);
2627         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2628
2629         return dma_ctrl;
2630 }
2631
2632 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2633 {
2634         u32 reg;
2635
2636         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2637         reg |= dma_ctrl;
2638         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2639
2640         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2641         reg |= dma_ctrl;
2642         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2643 }
2644
2645 static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2646                                            u32 f_index)
2647 {
2648         u32 offset;
2649         u32 reg;
2650
2651         offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2652         reg = bcmgenet_hfb_reg_readl(priv, offset);
2653         return !!(reg & (1 << (f_index % 32)));
2654 }
2655
2656 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2657 {
2658         u32 offset;
2659         u32 reg;
2660
2661         offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2662         reg = bcmgenet_hfb_reg_readl(priv, offset);
2663         reg |= (1 << (f_index % 32));
2664         bcmgenet_hfb_reg_writel(priv, reg, offset);
2665 }
2666
2667 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2668                                                      u32 f_index, u32 rx_queue)
2669 {
2670         u32 offset;
2671         u32 reg;
2672
2673         offset = f_index / 8;
2674         reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2675         reg &= ~(0xF << (4 * (f_index % 8)));
2676         reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2677         bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2678 }
2679
2680 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2681                                            u32 f_index, u32 f_length)
2682 {
2683         u32 offset;
2684         u32 reg;
2685
2686         offset = HFB_FLT_LEN_V3PLUS +
2687                  ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2688                  sizeof(u32);
2689         reg = bcmgenet_hfb_reg_readl(priv, offset);
2690         reg &= ~(0xFF << (8 * (f_index % 4)));
2691         reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2692         bcmgenet_hfb_reg_writel(priv, reg, offset);
2693 }
2694
2695 static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2696 {
2697         u32 f_index;
2698
2699         for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2700                 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2701                         return f_index;
2702
2703         return -ENOMEM;
2704 }
2705
2706 /* bcmgenet_hfb_add_filter
2707  *
2708  * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2709  * desired Rx queue.
2710  *
2711  * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2712  * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2713  *
2714  * bits 31:20 - unused
2715  * bit  19    - nibble 0 match enable
2716  * bit  18    - nibble 1 match enable
2717  * bit  17    - nibble 2 match enable
2718  * bit  16    - nibble 3 match enable
2719  * bits 15:12 - nibble 0 data
2720  * bits 11:8  - nibble 1 data
2721  * bits 7:4   - nibble 2 data
2722  * bits 3:0   - nibble 3 data
2723  *
2724  * Example:
2725  * In order to match:
2726  * - Ethernet frame type = 0x0800 (IP)
2727  * - IP version field = 4
2728  * - IP protocol field = 0x11 (UDP)
2729  *
2730  * The following filter is needed:
2731  * u32 hfb_filter_ipv4_udp[] = {
2732  *   Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2733  *   Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2734  *   Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2735  * };
2736  *
2737  * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2738  * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2739  *                         ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2740  */
2741 int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2742                             u32 f_length, u32 rx_queue)
2743 {
2744         int f_index;
2745         u32 i;
2746
2747         f_index = bcmgenet_hfb_find_unused_filter(priv);
2748         if (f_index < 0)
2749                 return -ENOMEM;
2750
2751         if (f_length > priv->hw_params->hfb_filter_size)
2752                 return -EINVAL;
2753
2754         for (i = 0; i < f_length; i++)
2755                 bcmgenet_hfb_writel(priv, f_data[i],
2756                         (f_index * priv->hw_params->hfb_filter_size + i) *
2757                         sizeof(u32));
2758
2759         bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2760         bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2761         bcmgenet_hfb_enable_filter(priv, f_index);
2762         bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2763
2764         return 0;
2765 }
2766
2767 /* bcmgenet_hfb_clear
2768  *
2769  * Clear Hardware Filter Block and disable all filtering.
2770  */
2771 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2772 {
2773         u32 i;
2774
2775         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2776         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2777         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2778
2779         for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2780                 bcmgenet_rdma_writel(priv, 0x0, i);
2781
2782         for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2783                 bcmgenet_hfb_reg_writel(priv, 0x0,
2784                                         HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2785
2786         for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2787                         priv->hw_params->hfb_filter_size; i++)
2788                 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2789 }
2790
2791 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2792 {
2793         if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2794                 return;
2795
2796         bcmgenet_hfb_clear(priv);
2797 }
2798
2799 static void bcmgenet_netif_start(struct net_device *dev)
2800 {
2801         struct bcmgenet_priv *priv = netdev_priv(dev);
2802
2803         /* Start the network engine */
2804         bcmgenet_enable_rx_napi(priv);
2805         bcmgenet_enable_tx_napi(priv);
2806
2807         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2808
2809         netif_tx_start_all_queues(dev);
2810
2811         /* Monitor link interrupts now */
2812         bcmgenet_link_intr_enable(priv);
2813
2814         phy_start(priv->phydev);
2815 }
2816
2817 static int bcmgenet_open(struct net_device *dev)
2818 {
2819         struct bcmgenet_priv *priv = netdev_priv(dev);
2820         unsigned long dma_ctrl;
2821         u32 reg;
2822         int ret;
2823
2824         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2825
2826         /* Turn on the clock */
2827         clk_prepare_enable(priv->clk);
2828
2829         /* If this is an internal GPHY, power it back on now, before UniMAC is
2830          * brought out of reset as absolutely no UniMAC activity is allowed
2831          */
2832         if (priv->internal_phy)
2833                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2834
2835         /* take MAC out of reset */
2836         bcmgenet_umac_reset(priv);
2837
2838         ret = init_umac(priv);
2839         if (ret)
2840                 goto err_clk_disable;
2841
2842         /* disable ethernet MAC while updating its registers */
2843         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2844
2845         /* Make sure we reflect the value of CRC_CMD_FWD */
2846         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2847         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2848
2849         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2850
2851         if (priv->internal_phy) {
2852                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2853                 reg |= EXT_ENERGY_DET_MASK;
2854                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2855         }
2856
2857         /* Disable RX/TX DMA and flush TX queues */
2858         dma_ctrl = bcmgenet_dma_disable(priv);
2859
2860         /* Reinitialize TDMA and RDMA and SW housekeeping */
2861         ret = bcmgenet_init_dma(priv);
2862         if (ret) {
2863                 netdev_err(dev, "failed to initialize DMA\n");
2864                 goto err_clk_disable;
2865         }
2866
2867         /* Always enable ring 16 - descriptor ring */
2868         bcmgenet_enable_dma(priv, dma_ctrl);
2869
2870         /* HFB init */
2871         bcmgenet_hfb_init(priv);
2872
2873         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2874                           dev->name, priv);
2875         if (ret < 0) {
2876                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2877                 goto err_fini_dma;
2878         }
2879
2880         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2881                           dev->name, priv);
2882         if (ret < 0) {
2883                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2884                 goto err_irq0;
2885         }
2886
2887         ret = bcmgenet_mii_probe(dev);
2888         if (ret) {
2889                 netdev_err(dev, "failed to connect to PHY\n");
2890                 goto err_irq1;
2891         }
2892
2893         bcmgenet_netif_start(dev);
2894
2895         return 0;
2896
2897 err_irq1:
2898         free_irq(priv->irq1, priv);
2899 err_irq0:
2900         free_irq(priv->irq0, priv);
2901 err_fini_dma:
2902         bcmgenet_fini_dma(priv);
2903 err_clk_disable:
2904         clk_disable_unprepare(priv->clk);
2905         return ret;
2906 }
2907
2908 static void bcmgenet_netif_stop(struct net_device *dev)
2909 {
2910         struct bcmgenet_priv *priv = netdev_priv(dev);
2911
2912         netif_tx_stop_all_queues(dev);
2913         phy_stop(priv->phydev);
2914         bcmgenet_intr_disable(priv);
2915         bcmgenet_disable_rx_napi(priv);
2916         bcmgenet_disable_tx_napi(priv);
2917
2918         /* Wait for pending work items to complete. Since interrupts are
2919          * disabled no new work will be scheduled.
2920          */
2921         cancel_work_sync(&priv->bcmgenet_irq_work);
2922
2923         priv->old_link = -1;
2924         priv->old_speed = -1;
2925         priv->old_duplex = -1;
2926         priv->old_pause = -1;
2927 }
2928
2929 static int bcmgenet_close(struct net_device *dev)
2930 {
2931         struct bcmgenet_priv *priv = netdev_priv(dev);
2932         int ret;
2933
2934         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2935
2936         bcmgenet_netif_stop(dev);
2937
2938         /* Really kill the PHY state machine and disconnect from it */
2939         phy_disconnect(priv->phydev);
2940
2941         /* Disable MAC receive */
2942         umac_enable_set(priv, CMD_RX_EN, false);
2943
2944         ret = bcmgenet_dma_teardown(priv);
2945         if (ret)
2946                 return ret;
2947
2948         /* Disable MAC transmit. TX DMA disabled have to done before this */
2949         umac_enable_set(priv, CMD_TX_EN, false);
2950
2951         /* tx reclaim */
2952         bcmgenet_tx_reclaim_all(dev);
2953         bcmgenet_fini_dma(priv);
2954
2955         free_irq(priv->irq0, priv);
2956         free_irq(priv->irq1, priv);
2957
2958         if (priv->internal_phy)
2959                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2960
2961         clk_disable_unprepare(priv->clk);
2962
2963         return ret;
2964 }
2965
2966 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2967 {
2968         struct bcmgenet_priv *priv = ring->priv;
2969         u32 p_index, c_index, intsts, intmsk;
2970         struct netdev_queue *txq;
2971         unsigned int free_bds;
2972         unsigned long flags;
2973         bool txq_stopped;
2974
2975         if (!netif_msg_tx_err(priv))
2976                 return;
2977
2978         txq = netdev_get_tx_queue(priv->dev, ring->queue);
2979
2980         spin_lock_irqsave(&ring->lock, flags);
2981         if (ring->index == DESC_INDEX) {
2982                 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2983                 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2984         } else {
2985                 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2986                 intmsk = 1 << ring->index;
2987         }
2988         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2989         p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2990         txq_stopped = netif_tx_queue_stopped(txq);
2991         free_bds = ring->free_bds;
2992         spin_unlock_irqrestore(&ring->lock, flags);
2993
2994         netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2995                   "TX queue status: %s, interrupts: %s\n"
2996                   "(sw)free_bds: %d (sw)size: %d\n"
2997                   "(sw)p_index: %d (hw)p_index: %d\n"
2998                   "(sw)c_index: %d (hw)c_index: %d\n"
2999                   "(sw)clean_p: %d (sw)write_p: %d\n"
3000                   "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3001                   ring->index, ring->queue,
3002                   txq_stopped ? "stopped" : "active",
3003                   intsts & intmsk ? "enabled" : "disabled",
3004                   free_bds, ring->size,
3005                   ring->prod_index, p_index & DMA_P_INDEX_MASK,
3006                   ring->c_index, c_index & DMA_C_INDEX_MASK,
3007                   ring->clean_ptr, ring->write_ptr,
3008                   ring->cb_ptr, ring->end_ptr);
3009 }
3010
3011 static void bcmgenet_timeout(struct net_device *dev)
3012 {
3013         struct bcmgenet_priv *priv = netdev_priv(dev);
3014         u32 int0_enable = 0;
3015         u32 int1_enable = 0;
3016         unsigned int q;
3017
3018         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3019
3020         for (q = 0; q < priv->hw_params->tx_queues; q++)
3021                 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3022         bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3023
3024         bcmgenet_tx_reclaim_all(dev);
3025
3026         for (q = 0; q < priv->hw_params->tx_queues; q++)
3027                 int1_enable |= (1 << q);
3028
3029         int0_enable = UMAC_IRQ_TXDMA_DONE;
3030
3031         /* Re-enable TX interrupts if disabled */
3032         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3033         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3034
3035         dev->trans_start = jiffies;
3036
3037         dev->stats.tx_errors++;
3038
3039         netif_tx_wake_all_queues(dev);
3040 }
3041
3042 #define MAX_MC_COUNT    16
3043
3044 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3045                                          unsigned char *addr,
3046                                          int *i,
3047                                          int *mc)
3048 {
3049         u32 reg;
3050
3051         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3052                              UMAC_MDF_ADDR + (*i * 4));
3053         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3054                              addr[4] << 8 | addr[5],
3055                              UMAC_MDF_ADDR + ((*i + 1) * 4));
3056         reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
3057         reg |= (1 << (MAX_MC_COUNT - *mc));
3058         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3059         *i += 2;
3060         (*mc)++;
3061 }
3062
3063 static void bcmgenet_set_rx_mode(struct net_device *dev)
3064 {
3065         struct bcmgenet_priv *priv = netdev_priv(dev);
3066         struct netdev_hw_addr *ha;
3067         int i, mc;
3068         u32 reg;
3069
3070         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3071
3072         /* Promiscuous mode */
3073         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3074         if (dev->flags & IFF_PROMISC) {
3075                 reg |= CMD_PROMISC;
3076                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3077                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3078                 return;
3079         } else {
3080                 reg &= ~CMD_PROMISC;
3081                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3082         }
3083
3084         /* UniMac doesn't support ALLMULTI */
3085         if (dev->flags & IFF_ALLMULTI) {
3086                 netdev_warn(dev, "ALLMULTI is not supported\n");
3087                 return;
3088         }
3089
3090         /* update MDF filter */
3091         i = 0;
3092         mc = 0;
3093         /* Broadcast */
3094         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
3095         /* my own address.*/
3096         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
3097         /* Unicast list*/
3098         if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
3099                 return;
3100
3101         if (!netdev_uc_empty(dev))
3102                 netdev_for_each_uc_addr(ha, dev)
3103                         bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3104         /* Multicast */
3105         if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3106                 return;
3107
3108         netdev_for_each_mc_addr(ha, dev)
3109                 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3110 }
3111
3112 /* Set the hardware MAC address. */
3113 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3114 {
3115         struct sockaddr *addr = p;
3116
3117         /* Setting the MAC address at the hardware level is not possible
3118          * without disabling the UniMAC RX/TX enable bits.
3119          */
3120         if (netif_running(dev))
3121                 return -EBUSY;
3122
3123         ether_addr_copy(dev->dev_addr, addr->sa_data);
3124
3125         return 0;
3126 }
3127
3128 static const struct net_device_ops bcmgenet_netdev_ops = {
3129         .ndo_open               = bcmgenet_open,
3130         .ndo_stop               = bcmgenet_close,
3131         .ndo_start_xmit         = bcmgenet_xmit,
3132         .ndo_tx_timeout         = bcmgenet_timeout,
3133         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
3134         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
3135         .ndo_do_ioctl           = bcmgenet_ioctl,
3136         .ndo_set_features       = bcmgenet_set_features,
3137 #ifdef CONFIG_NET_POLL_CONTROLLER
3138         .ndo_poll_controller    = bcmgenet_poll_controller,
3139 #endif
3140 };
3141
3142 /* Array of GENET hardware parameters/characteristics */
3143 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3144         [GENET_V1] = {
3145                 .tx_queues = 0,
3146                 .tx_bds_per_q = 0,
3147                 .rx_queues = 0,
3148                 .rx_bds_per_q = 0,
3149                 .bp_in_en_shift = 16,
3150                 .bp_in_mask = 0xffff,
3151                 .hfb_filter_cnt = 16,
3152                 .qtag_mask = 0x1F,
3153                 .hfb_offset = 0x1000,
3154                 .rdma_offset = 0x2000,
3155                 .tdma_offset = 0x3000,
3156                 .words_per_bd = 2,
3157         },
3158         [GENET_V2] = {
3159                 .tx_queues = 4,
3160                 .tx_bds_per_q = 32,
3161                 .rx_queues = 0,
3162                 .rx_bds_per_q = 0,
3163                 .bp_in_en_shift = 16,
3164                 .bp_in_mask = 0xffff,
3165                 .hfb_filter_cnt = 16,
3166                 .qtag_mask = 0x1F,
3167                 .tbuf_offset = 0x0600,
3168                 .hfb_offset = 0x1000,
3169                 .hfb_reg_offset = 0x2000,
3170                 .rdma_offset = 0x3000,
3171                 .tdma_offset = 0x4000,
3172                 .words_per_bd = 2,
3173                 .flags = GENET_HAS_EXT,
3174         },
3175         [GENET_V3] = {
3176                 .tx_queues = 4,
3177                 .tx_bds_per_q = 32,
3178                 .rx_queues = 0,
3179                 .rx_bds_per_q = 0,
3180                 .bp_in_en_shift = 17,
3181                 .bp_in_mask = 0x1ffff,
3182                 .hfb_filter_cnt = 48,
3183                 .hfb_filter_size = 128,
3184                 .qtag_mask = 0x3F,
3185                 .tbuf_offset = 0x0600,
3186                 .hfb_offset = 0x8000,
3187                 .hfb_reg_offset = 0xfc00,
3188                 .rdma_offset = 0x10000,
3189                 .tdma_offset = 0x11000,
3190                 .words_per_bd = 2,
3191                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3192                          GENET_HAS_MOCA_LINK_DET,
3193         },
3194         [GENET_V4] = {
3195                 .tx_queues = 4,
3196                 .tx_bds_per_q = 32,
3197                 .rx_queues = 0,
3198                 .rx_bds_per_q = 0,
3199                 .bp_in_en_shift = 17,
3200                 .bp_in_mask = 0x1ffff,
3201                 .hfb_filter_cnt = 48,
3202                 .hfb_filter_size = 128,
3203                 .qtag_mask = 0x3F,
3204                 .tbuf_offset = 0x0600,
3205                 .hfb_offset = 0x8000,
3206                 .hfb_reg_offset = 0xfc00,
3207                 .rdma_offset = 0x2000,
3208                 .tdma_offset = 0x4000,
3209                 .words_per_bd = 3,
3210                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3211                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3212         },
3213 };
3214
3215 /* Infer hardware parameters from the detected GENET version */
3216 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3217 {
3218         struct bcmgenet_hw_params *params;
3219         u32 reg;
3220         u8 major;
3221         u16 gphy_rev;
3222
3223         if (GENET_IS_V4(priv)) {
3224                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3225                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3226                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3227                 priv->version = GENET_V4;
3228         } else if (GENET_IS_V3(priv)) {
3229                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3230                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3231                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3232                 priv->version = GENET_V3;
3233         } else if (GENET_IS_V2(priv)) {
3234                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3235                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3236                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3237                 priv->version = GENET_V2;
3238         } else if (GENET_IS_V1(priv)) {
3239                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3240                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3241                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3242                 priv->version = GENET_V1;
3243         }
3244
3245         /* enum genet_version starts at 1 */
3246         priv->hw_params = &bcmgenet_hw_params[priv->version];
3247         params = priv->hw_params;
3248
3249         /* Read GENET HW version */
3250         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3251         major = (reg >> 24 & 0x0f);
3252         if (major == 5)
3253                 major = 4;
3254         else if (major == 0)
3255                 major = 1;
3256         if (major != priv->version) {
3257                 dev_err(&priv->pdev->dev,
3258                         "GENET version mismatch, got: %d, configured for: %d\n",
3259                         major, priv->version);
3260         }
3261
3262         /* Print the GENET core version */
3263         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3264                  major, (reg >> 16) & 0x0f, reg & 0xffff);
3265
3266         /* Store the integrated PHY revision for the MDIO probing function
3267          * to pass this information to the PHY driver. The PHY driver expects
3268          * to find the PHY major revision in bits 15:8 while the GENET register
3269          * stores that information in bits 7:0, account for that.
3270          *
3271          * On newer chips, starting with PHY revision G0, a new scheme is
3272          * deployed similar to the Starfighter 2 switch with GPHY major
3273          * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3274          * is reserved as well as special value 0x01ff, we have a small
3275          * heuristic to check for the new GPHY revision and re-arrange things
3276          * so the GPHY driver is happy.
3277          */
3278         gphy_rev = reg & 0xffff;
3279
3280         /* This is the good old scheme, just GPHY major, no minor nor patch */
3281         if ((gphy_rev & 0xf0) != 0)
3282                 priv->gphy_rev = gphy_rev << 8;
3283
3284         /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3285         else if ((gphy_rev & 0xff00) != 0)
3286                 priv->gphy_rev = gphy_rev;
3287
3288         /* This is reserved so should require special treatment */
3289         else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3290                 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3291                 return;
3292         }
3293
3294 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3295         if (!(params->flags & GENET_HAS_40BITS))
3296                 pr_warn("GENET does not support 40-bits PA\n");
3297 #endif
3298
3299         pr_debug("Configuration for version: %d\n"
3300                 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3301                 "BP << en: %2d, BP msk: 0x%05x\n"
3302                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3303                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3304                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3305                 "Words/BD: %d\n",
3306                 priv->version,
3307                 params->tx_queues, params->tx_bds_per_q,
3308                 params->rx_queues, params->rx_bds_per_q,
3309                 params->bp_in_en_shift, params->bp_in_mask,
3310                 params->hfb_filter_cnt, params->qtag_mask,
3311                 params->tbuf_offset, params->hfb_offset,
3312                 params->hfb_reg_offset,
3313                 params->rdma_offset, params->tdma_offset,
3314                 params->words_per_bd);
3315 }
3316
3317 static const struct of_device_id bcmgenet_match[] = {
3318         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3319         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3320         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3321         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3322         { },
3323 };
3324 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3325
3326 static int bcmgenet_probe(struct platform_device *pdev)
3327 {
3328         struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3329         struct device_node *dn = pdev->dev.of_node;
3330         const struct of_device_id *of_id = NULL;
3331         struct bcmgenet_priv *priv;
3332         struct net_device *dev;
3333         const void *macaddr;
3334         struct resource *r;
3335         int err = -EIO;
3336
3337         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3338         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3339                                  GENET_MAX_MQ_CNT + 1);
3340         if (!dev) {
3341                 dev_err(&pdev->dev, "can't allocate net device\n");
3342                 return -ENOMEM;
3343         }
3344
3345         if (dn) {
3346                 of_id = of_match_node(bcmgenet_match, dn);
3347                 if (!of_id)
3348                         return -EINVAL;
3349         }
3350
3351         priv = netdev_priv(dev);
3352         priv->irq0 = platform_get_irq(pdev, 0);
3353         priv->irq1 = platform_get_irq(pdev, 1);
3354         priv->wol_irq = platform_get_irq(pdev, 2);
3355         if (!priv->irq0 || !priv->irq1) {
3356                 dev_err(&pdev->dev, "can't find IRQs\n");
3357                 err = -EINVAL;
3358                 goto err;
3359         }
3360
3361         if (dn) {
3362                 macaddr = of_get_mac_address(dn);
3363                 if (!macaddr) {
3364                         dev_err(&pdev->dev, "can't find MAC address\n");
3365                         err = -EINVAL;
3366                         goto err;
3367                 }
3368         } else {
3369                 macaddr = pd->mac_address;
3370         }
3371
3372         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3373         priv->base = devm_ioremap_resource(&pdev->dev, r);
3374         if (IS_ERR(priv->base)) {
3375                 err = PTR_ERR(priv->base);
3376                 goto err;
3377         }
3378
3379         SET_NETDEV_DEV(dev, &pdev->dev);
3380         dev_set_drvdata(&pdev->dev, dev);
3381         ether_addr_copy(dev->dev_addr, macaddr);
3382         dev->watchdog_timeo = 2 * HZ;
3383         dev->ethtool_ops = &bcmgenet_ethtool_ops;
3384         dev->netdev_ops = &bcmgenet_netdev_ops;
3385
3386         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3387
3388         /* Set hardware features */
3389         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3390                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3391
3392         /* Request the WOL interrupt and advertise suspend if available */
3393         priv->wol_irq_disabled = true;
3394         err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3395                                dev->name, priv);
3396         if (!err)
3397                 device_set_wakeup_capable(&pdev->dev, 1);
3398
3399         /* Set the needed headroom to account for any possible
3400          * features enabling/disabling at runtime
3401          */
3402         dev->needed_headroom += 64;
3403
3404         netdev_boot_setup_check(dev);
3405
3406         priv->dev = dev;
3407         priv->pdev = pdev;
3408         if (of_id)
3409                 priv->version = (enum bcmgenet_version)of_id->data;
3410         else
3411                 priv->version = pd->genet_version;
3412
3413         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3414         if (IS_ERR(priv->clk)) {
3415                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3416                 priv->clk = NULL;
3417         }
3418
3419         clk_prepare_enable(priv->clk);
3420
3421         bcmgenet_set_hw_params(priv);
3422
3423         /* Mii wait queue */
3424         init_waitqueue_head(&priv->wq);
3425         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3426         priv->rx_buf_len = RX_BUF_LENGTH;
3427         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3428
3429         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3430         if (IS_ERR(priv->clk_wol)) {
3431                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3432                 priv->clk_wol = NULL;
3433         }
3434
3435         priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3436         if (IS_ERR(priv->clk_eee)) {
3437                 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3438                 priv->clk_eee = NULL;
3439         }
3440
3441         err = reset_umac(priv);
3442         if (err)
3443                 goto err_clk_disable;
3444
3445         err = bcmgenet_mii_init(dev);
3446         if (err)
3447                 goto err_clk_disable;
3448
3449         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
3450          * just the ring 16 descriptor based TX
3451          */
3452         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3453         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3454
3455         /* libphy will determine the link state */
3456         netif_carrier_off(dev);
3457
3458         /* Turn off the main clock, WOL clock is handled separately */
3459         clk_disable_unprepare(priv->clk);
3460
3461         err = register_netdev(dev);
3462         if (err)
3463                 goto err;
3464
3465         return err;
3466
3467 err_clk_disable:
3468         clk_disable_unprepare(priv->clk);
3469 err:
3470         free_netdev(dev);
3471         return err;
3472 }
3473
3474 static int bcmgenet_remove(struct platform_device *pdev)
3475 {
3476         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3477
3478         dev_set_drvdata(&pdev->dev, NULL);
3479         unregister_netdev(priv->dev);
3480         bcmgenet_mii_exit(priv->dev);
3481         free_netdev(priv->dev);
3482
3483         return 0;
3484 }
3485
3486 #ifdef CONFIG_PM_SLEEP
3487 static int bcmgenet_suspend(struct device *d)
3488 {
3489         struct net_device *dev = dev_get_drvdata(d);
3490         struct bcmgenet_priv *priv = netdev_priv(dev);
3491         int ret;
3492
3493         if (!netif_running(dev))
3494                 return 0;
3495
3496         bcmgenet_netif_stop(dev);
3497
3498         phy_suspend(priv->phydev);
3499
3500         netif_device_detach(dev);
3501
3502         /* Disable MAC receive */
3503         umac_enable_set(priv, CMD_RX_EN, false);
3504
3505         ret = bcmgenet_dma_teardown(priv);
3506         if (ret)
3507                 return ret;
3508
3509         /* Disable MAC transmit. TX DMA disabled have to done before this */
3510         umac_enable_set(priv, CMD_TX_EN, false);
3511
3512         /* tx reclaim */
3513         bcmgenet_tx_reclaim_all(dev);
3514         bcmgenet_fini_dma(priv);
3515
3516         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3517         if (device_may_wakeup(d) && priv->wolopts) {
3518                 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3519                 clk_prepare_enable(priv->clk_wol);
3520         } else if (priv->internal_phy) {
3521                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3522         }
3523
3524         /* Turn off the clocks */
3525         clk_disable_unprepare(priv->clk);
3526
3527         return ret;
3528 }
3529
3530 static int bcmgenet_resume(struct device *d)
3531 {
3532         struct net_device *dev = dev_get_drvdata(d);
3533         struct bcmgenet_priv *priv = netdev_priv(dev);
3534         unsigned long dma_ctrl;
3535         int ret;
3536         u32 reg;
3537
3538         if (!netif_running(dev))
3539                 return 0;
3540
3541         /* Turn on the clock */
3542         ret = clk_prepare_enable(priv->clk);
3543         if (ret)
3544                 return ret;
3545
3546         /* If this is an internal GPHY, power it back on now, before UniMAC is
3547          * brought out of reset as absolutely no UniMAC activity is allowed
3548          */
3549         if (priv->internal_phy)
3550                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3551
3552         bcmgenet_umac_reset(priv);
3553
3554         ret = init_umac(priv);
3555         if (ret)
3556                 goto out_clk_disable;
3557
3558         /* From WOL-enabled suspend, switch to regular clock */
3559         if (priv->wolopts)
3560                 clk_disable_unprepare(priv->clk_wol);
3561
3562         phy_init_hw(priv->phydev);
3563         /* Speed settings must be restored */
3564         bcmgenet_mii_config(priv->dev);
3565
3566         /* disable ethernet MAC while updating its registers */
3567         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3568
3569         bcmgenet_set_hw_addr(priv, dev->dev_addr);
3570
3571         if (priv->internal_phy) {
3572                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3573                 reg |= EXT_ENERGY_DET_MASK;
3574                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3575         }
3576
3577         if (priv->wolopts)
3578                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3579
3580         /* Disable RX/TX DMA and flush TX queues */
3581         dma_ctrl = bcmgenet_dma_disable(priv);
3582
3583         /* Reinitialize TDMA and RDMA and SW housekeeping */
3584         ret = bcmgenet_init_dma(priv);
3585         if (ret) {
3586                 netdev_err(dev, "failed to initialize DMA\n");
3587                 goto out_clk_disable;
3588         }
3589
3590         /* Always enable ring 16 - descriptor ring */
3591         bcmgenet_enable_dma(priv, dma_ctrl);
3592
3593         netif_device_attach(dev);
3594
3595         phy_resume(priv->phydev);
3596
3597         if (priv->eee.eee_enabled)
3598                 bcmgenet_eee_enable_set(dev, true);
3599
3600         bcmgenet_netif_start(dev);
3601
3602         return 0;
3603
3604 out_clk_disable:
3605         clk_disable_unprepare(priv->clk);
3606         return ret;
3607 }
3608 #endif /* CONFIG_PM_SLEEP */
3609
3610 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3611
3612 static struct platform_driver bcmgenet_driver = {
3613         .probe  = bcmgenet_probe,
3614         .remove = bcmgenet_remove,
3615         .driver = {
3616                 .name   = "bcmgenet",
3617                 .of_match_table = bcmgenet_match,
3618                 .pm     = &bcmgenet_pm_ops,
3619         },
3620 };
3621 module_platform_driver(bcmgenet_driver);
3622
3623 MODULE_AUTHOR("Broadcom Corporation");
3624 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3625 MODULE_ALIAS("platform:bcmgenet");
3626 MODULE_LICENSE("GPL");