kernel/drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 /*
   2  * Broadcom GENET (Gigabit Ethernet) controller driver
   3  *
   4  * Copyright (c) 2014 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/sched.h>
  16 #include <linux/types.h>
  17 #include <linux/fcntl.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/string.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_net.h>
  32 #include <linux/of_platform.h>
  33 #include <net/arp.h>
  34
  35 #include <linux/mii.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/inetdevice.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/in.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/phy.h>
  45 #include <linux/platform_data/bcmgenet.h>
  46
  47 #include <asm/unaligned.h>
  48
  49 #include "bcmgenet.h"
  50
  51 /* Maximum number of hardware queues, downsized if needed */
  52 #define GENET_MAX_MQ_CNT        4
  53
  54 /* Default highest priority queue for multi queue support */
  55 #define GENET_Q0_PRIORITY       0
  56
  57 #define GENET_Q16_RX_BD_CNT     \
  58         (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
  59 #define GENET_Q16_TX_BD_CNT     \
  60         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
  61
  62 #define RX_BUF_LENGTH           2048
  63 #define SKB_ALIGNMENT           32
  64
  65 /* Tx/Rx DMA register offset, skip 256 descriptors */
  66 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  67 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  68
  69 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  70                                 TOTAL_DESC * DMA_DESC_SIZE)
  71
  72 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  73                                 TOTAL_DESC * DMA_DESC_SIZE)
  74
  75 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  76                                              void __iomem *d, u32 value)
  77 {
  78         __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
  79 }
  80
  81 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
  82                                             void __iomem *d)
  83 {
  84         return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
  85 }
  86
  87 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
  88                                     void __iomem *d,
  89                                     dma_addr_t addr)
  90 {
  91         __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
  92
  93         /* Register writes to GISB bus can take couple hundred nanoseconds
  94          * and are done for each packet, save these expensive writes unless
  95          * the platform is explicitly configured for 64-bits/LPAE.
  96          */
  97 #ifdef CONFIG_PHYS_ADDR_T_64BIT
  98         if (priv->hw_params->flags & GENET_HAS_40BITS)
  99                 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
 100 #endif
 101 }
 102
 103 /* Combined address + length/status setter */
 104 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 105                                void __iomem *d, dma_addr_t addr, u32 val)
 106 {
 107         dmadesc_set_length_status(priv, d, val);
 108         dmadesc_set_addr(priv, d, addr);
 109 }
 110
 111 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 112                                           void __iomem *d)
 113 {
 114         dma_addr_t addr;
 115
 116         addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
 117
 118         /* Register writes to GISB bus can take couple hundred nanoseconds
 119          * and are done for each packet, save these expensive writes unless
 120          * the platform is explicitly configured for 64-bits/LPAE.
 121          */
 122 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 123         if (priv->hw_params->flags & GENET_HAS_40BITS)
 124                 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 125 #endif
 126         return addr;
 127 }
 128
 129 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 130
 131 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 132                                 NETIF_MSG_LINK)
 133
 134 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 135 {
 136         if (GENET_IS_V1(priv))
 137                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 138         else
 139                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 140 }
 141
 142 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 143 {
 144         if (GENET_IS_V1(priv))
 145                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 146         else
 147                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 148 }
 149
 150 /* These macros are defined to deal with register map change
 151  * between GENET1.1 and GENET2. Only those currently being used
 152  * by driver are defined.
 153  */
 154 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 155 {
 156         if (GENET_IS_V1(priv))
 157                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 158         else
 159                 return __raw_readl(priv->base +
 160                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 161 }
 162
 163 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 164 {
 165         if (GENET_IS_V1(priv))
 166                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 167         else
 168                 __raw_writel(val, priv->base +
 169                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 170 }
 171
 172 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 173 {
 174         if (GENET_IS_V1(priv))
 175                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 176         else
 177                 return __raw_readl(priv->base +
 178                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 179 }
 180
 181 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 182 {
 183         if (GENET_IS_V1(priv))
 184                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 185         else
 186                 __raw_writel(val, priv->base +
 187                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 188 }
 189
 190 /* RX/TX DMA register accessors */
 191 enum dma_reg {
 192         DMA_RING_CFG = 0,
 193         DMA_CTRL,
 194         DMA_STATUS,
 195         DMA_SCB_BURST_SIZE,
 196         DMA_ARB_CTRL,
 197         DMA_PRIORITY_0,
 198         DMA_PRIORITY_1,
 199         DMA_PRIORITY_2,
 200         DMA_INDEX2RING_0,
 201         DMA_INDEX2RING_1,
 202         DMA_INDEX2RING_2,
 203         DMA_INDEX2RING_3,
 204         DMA_INDEX2RING_4,
 205         DMA_INDEX2RING_5,
 206         DMA_INDEX2RING_6,
 207         DMA_INDEX2RING_7,
 208 };
 209
 210 static const u8 bcmgenet_dma_regs_v3plus[] = {
 211         [DMA_RING_CFG]          = 0x00,
 212         [DMA_CTRL]              = 0x04,
 213         [DMA_STATUS]            = 0x08,
 214         [DMA_SCB_BURST_SIZE]    = 0x0C,
 215         [DMA_ARB_CTRL]          = 0x2C,
 216         [DMA_PRIORITY_0]        = 0x30,
 217         [DMA_PRIORITY_1]        = 0x34,
 218         [DMA_PRIORITY_2]        = 0x38,
 219         [DMA_INDEX2RING_0]      = 0x70,
 220         [DMA_INDEX2RING_1]      = 0x74,
 221         [DMA_INDEX2RING_2]      = 0x78,
 222         [DMA_INDEX2RING_3]      = 0x7C,
 223         [DMA_INDEX2RING_4]      = 0x80,
 224         [DMA_INDEX2RING_5]      = 0x84,
 225         [DMA_INDEX2RING_6]      = 0x88,
 226         [DMA_INDEX2RING_7]      = 0x8C,
 227 };
 228
 229 static const u8 bcmgenet_dma_regs_v2[] = {
 230         [DMA_RING_CFG]          = 0x00,
 231         [DMA_CTRL]              = 0x04,
 232         [DMA_STATUS]            = 0x08,
 233         [DMA_SCB_BURST_SIZE]    = 0x0C,
 234         [DMA_ARB_CTRL]          = 0x30,
 235         [DMA_PRIORITY_0]        = 0x34,
 236         [DMA_PRIORITY_1]        = 0x38,
 237         [DMA_PRIORITY_2]        = 0x3C,
 238 };
 239
 240 static const u8 bcmgenet_dma_regs_v1[] = {
 241         [DMA_CTRL]              = 0x00,
 242         [DMA_STATUS]            = 0x04,
 243         [DMA_SCB_BURST_SIZE]    = 0x0C,
 244         [DMA_ARB_CTRL]          = 0x30,
 245         [DMA_PRIORITY_0]        = 0x34,
 246         [DMA_PRIORITY_1]        = 0x38,
 247         [DMA_PRIORITY_2]        = 0x3C,
 248 };
 249
 250 /* Set at runtime once bcmgenet version is known */
 251 static const u8 *bcmgenet_dma_regs;
 252
 253 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 254 {
 255         return netdev_priv(dev_get_drvdata(dev));
 256 }
 257
 258 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 259                                       enum dma_reg r)
 260 {
 261         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 262                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 263 }
 264
 265 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 266                                         u32 val, enum dma_reg r)
 267 {
 268         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 269                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 270 }
 271
 272 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 273                                       enum dma_reg r)
 274 {
 275         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 276                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 277 }
 278
 279 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 280                                         u32 val, enum dma_reg r)
 281 {
 282         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 283                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 284 }
 285
 286 /* RDMA/TDMA ring registers and accessors
 287  * we merge the common fields and just prefix with T/D the registers
 288  * having different meaning depending on the direction
 289  */
 290 enum dma_ring_reg {
 291         TDMA_READ_PTR = 0,
 292         RDMA_WRITE_PTR = TDMA_READ_PTR,
 293         TDMA_READ_PTR_HI,
 294         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 295         TDMA_CONS_INDEX,
 296         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 297         TDMA_PROD_INDEX,
 298         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 299         DMA_RING_BUF_SIZE,
 300         DMA_START_ADDR,
 301         DMA_START_ADDR_HI,
 302         DMA_END_ADDR,
 303         DMA_END_ADDR_HI,
 304         DMA_MBUF_DONE_THRESH,
 305         TDMA_FLOW_PERIOD,
 306         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 307         TDMA_WRITE_PTR,
 308         RDMA_READ_PTR = TDMA_WRITE_PTR,
 309         TDMA_WRITE_PTR_HI,
 310         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 311 };
 312
 313 /* GENET v4 supports 40-bits pointer addressing
 314  * for obvious reasons the LO and HI word parts
 315  * are contiguous, but this offsets the other
 316  * registers.
 317  */
 318 static const u8 genet_dma_ring_regs_v4[] = {
 319         [TDMA_READ_PTR]                 = 0x00,
 320         [TDMA_READ_PTR_HI]              = 0x04,
 321         [TDMA_CONS_INDEX]               = 0x08,
 322         [TDMA_PROD_INDEX]               = 0x0C,
 323         [DMA_RING_BUF_SIZE]             = 0x10,
 324         [DMA_START_ADDR]                = 0x14,
 325         [DMA_START_ADDR_HI]             = 0x18,
 326         [DMA_END_ADDR]                  = 0x1C,
 327         [DMA_END_ADDR_HI]               = 0x20,
 328         [DMA_MBUF_DONE_THRESH]          = 0x24,
 329         [TDMA_FLOW_PERIOD]              = 0x28,
 330         [TDMA_WRITE_PTR]                = 0x2C,
 331         [TDMA_WRITE_PTR_HI]             = 0x30,
 332 };
 333
 334 static const u8 genet_dma_ring_regs_v123[] = {
 335         [TDMA_READ_PTR]                 = 0x00,
 336         [TDMA_CONS_INDEX]               = 0x04,
 337         [TDMA_PROD_INDEX]               = 0x08,
 338         [DMA_RING_BUF_SIZE]             = 0x0C,
 339         [DMA_START_ADDR]                = 0x10,
 340         [DMA_END_ADDR]                  = 0x14,
 341         [DMA_MBUF_DONE_THRESH]          = 0x18,
 342         [TDMA_FLOW_PERIOD]              = 0x1C,
 343         [TDMA_WRITE_PTR]                = 0x20,
 344 };
 345
 346 /* Set at runtime once GENET version is known */
 347 static const u8 *genet_dma_ring_regs;
 348
 349 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 350                                            unsigned int ring,
 351                                            enum dma_ring_reg r)
 352 {
 353         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 354                         (DMA_RING_SIZE * ring) +
 355                         genet_dma_ring_regs[r]);
 356 }
 357
 358 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 359                                              unsigned int ring, u32 val,
 360                                              enum dma_ring_reg r)
 361 {
 362         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 363                         (DMA_RING_SIZE * ring) +
 364                         genet_dma_ring_regs[r]);
 365 }
 366
 367 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 368                                            unsigned int ring,
 369                                            enum dma_ring_reg r)
 370 {
 371         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 372                         (DMA_RING_SIZE * ring) +
 373                         genet_dma_ring_regs[r]);
 374 }
 375
 376 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 377                                              unsigned int ring, u32 val,
 378                                              enum dma_ring_reg r)
 379 {
 380         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 381                         (DMA_RING_SIZE * ring) +
 382                         genet_dma_ring_regs[r]);
 383 }
 384
 385 static int bcmgenet_get_settings(struct net_device *dev,
 386                                  struct ethtool_cmd *cmd)
 387 {
 388         struct bcmgenet_priv *priv = netdev_priv(dev);
 389
 390         if (!netif_running(dev))
 391                 return -EINVAL;
 392
 393         if (!priv->phydev)
 394                 return -ENODEV;
 395
 396         return phy_ethtool_gset(priv->phydev, cmd);
 397 }
 398
 399 static int bcmgenet_set_settings(struct net_device *dev,
 400                                  struct ethtool_cmd *cmd)
 401 {
 402         struct bcmgenet_priv *priv = netdev_priv(dev);
 403
 404         if (!netif_running(dev))
 405                 return -EINVAL;
 406
 407         if (!priv->phydev)
 408                 return -ENODEV;
 409
 410         return phy_ethtool_sset(priv->phydev, cmd);
 411 }
 412
 413 static int bcmgenet_set_rx_csum(struct net_device *dev,
 414                                 netdev_features_t wanted)
 415 {
 416         struct bcmgenet_priv *priv = netdev_priv(dev);
 417         u32 rbuf_chk_ctrl;
 418         bool rx_csum_en;
 419
 420         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 421
 422         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 423
 424         /* enable rx checksumming */
 425         if (rx_csum_en)
 426                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 427         else
 428                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 429         priv->desc_rxchk_en = rx_csum_en;
 430
 431         /* If UniMAC forwards CRC, we need to skip over it to get
 432          * a valid CHK bit to be set in the per-packet status word
 433         */
 434         if (rx_csum_en && priv->crc_fwd_en)
 435                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 436         else
 437                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 438
 439         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 440
 441         return 0;
 442 }
 443
 444 static int bcmgenet_set_tx_csum(struct net_device *dev,
 445                                 netdev_features_t wanted)
 446 {
 447         struct bcmgenet_priv *priv = netdev_priv(dev);
 448         bool desc_64b_en;
 449         u32 tbuf_ctrl, rbuf_ctrl;
 450
 451         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 452         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 453
 454         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 455
 456         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 457         if (desc_64b_en) {
 458                 tbuf_ctrl |= RBUF_64B_EN;
 459                 rbuf_ctrl |= RBUF_64B_EN;
 460         } else {
 461                 tbuf_ctrl &= ~RBUF_64B_EN;
 462                 rbuf_ctrl &= ~RBUF_64B_EN;
 463         }
 464         priv->desc_64b_en = desc_64b_en;
 465
 466         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 467         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 468
 469         return 0;
 470 }
 471
 472 static int bcmgenet_set_features(struct net_device *dev,
 473                                  netdev_features_t features)
 474 {
 475         netdev_features_t changed = features ^ dev->features;
 476         netdev_features_t wanted = dev->wanted_features;
 477         int ret = 0;
 478
 479         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 480                 ret = bcmgenet_set_tx_csum(dev, wanted);
 481         if (changed & (NETIF_F_RXCSUM))
 482                 ret = bcmgenet_set_rx_csum(dev, wanted);
 483
 484         return ret;
 485 }
 486
 487 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 488 {
 489         struct bcmgenet_priv *priv = netdev_priv(dev);
 490
 491         return priv->msg_enable;
 492 }
 493
 494 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 495 {
 496         struct bcmgenet_priv *priv = netdev_priv(dev);
 497
 498         priv->msg_enable = level;
 499 }
 500
 501 /* standard ethtool support functions. */
 502 enum bcmgenet_stat_type {
 503         BCMGENET_STAT_NETDEV = -1,
 504         BCMGENET_STAT_MIB_RX,
 505         BCMGENET_STAT_MIB_TX,
 506         BCMGENET_STAT_RUNT,
 507         BCMGENET_STAT_MISC,
 508         BCMGENET_STAT_SOFT,
 509 };
 510
 511 struct bcmgenet_stats {
 512         char stat_string[ETH_GSTRING_LEN];
 513         int stat_sizeof;
 514         int stat_offset;
 515         enum bcmgenet_stat_type type;
 516         /* reg offset from UMAC base for misc counters */
 517         u16 reg_offset;
 518 };
 519
 520 #define STAT_NETDEV(m) { \
 521         .stat_string = __stringify(m), \
 522         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 523         .stat_offset = offsetof(struct net_device_stats, m), \
 524         .type = BCMGENET_STAT_NETDEV, \
 525 }
 526
 527 #define STAT_GENET_MIB(str, m, _type) { \
 528         .stat_string = str, \
 529         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 530         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 531         .type = _type, \
 532 }
 533
 534 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 535 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 536 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 537 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
 538
 539 #define STAT_GENET_MISC(str, m, offset) { \
 540         .stat_string = str, \
 541         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 542         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 543         .type = BCMGENET_STAT_MISC, \
 544         .reg_offset = offset, \
 545 }
 546
 547
 548 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 549  * between the end of TX stats and the beginning of the RX RUNT
 550  */
 551 #define BCMGENET_STAT_OFFSET    0xc
 552
 553 /* Hardware counters must be kept in sync because the order/offset
 554  * is important here (order in structure declaration = order in hardware)
 555  */
 556 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 557         /* general stats */
 558         STAT_NETDEV(rx_packets),
 559         STAT_NETDEV(tx_packets),
 560         STAT_NETDEV(rx_bytes),
 561         STAT_NETDEV(tx_bytes),
 562         STAT_NETDEV(rx_errors),
 563         STAT_NETDEV(tx_errors),
 564         STAT_NETDEV(rx_dropped),
 565         STAT_NETDEV(tx_dropped),
 566         STAT_NETDEV(multicast),
 567         /* UniMAC RSV counters */
 568         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 569         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 570         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 571         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 572         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 573         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 574         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 575         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 576         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 577         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 578         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 579         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 580         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 581         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 582         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 583         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 584         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 585         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 586         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 587         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 588         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 589         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 590         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 591         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 592         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 593         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 594         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 595         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 596         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 597         /* UniMAC TSV counters */
 598         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 599         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 600         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 601         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 602         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 603         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 604         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 605         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 606         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 607         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 608         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 609         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 610         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 611         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 612         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 613         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 614         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 615         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 616         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 617         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 618         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 619         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 620         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 621         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 622         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 623         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 624         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 625         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 626         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 627         /* UniMAC RUNT counters */
 628         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 629         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 630         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 631         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 632         /* Misc UniMAC counters */
 633         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 634                         UMAC_RBUF_OVFL_CNT),
 635         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
 636         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 637         STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 638         STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
 639         STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
 640 };
 641
 642 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 643
 644 static void bcmgenet_get_drvinfo(struct net_device *dev,
 645                                  struct ethtool_drvinfo *info)
 646 {
 647         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 648         strlcpy(info->version, "v2.0", sizeof(info->version));
 649         info->n_stats = BCMGENET_STATS_LEN;
 650 }
 651
 652 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 653 {
 654         switch (string_set) {
 655         case ETH_SS_STATS:
 656                 return BCMGENET_STATS_LEN;
 657         default:
 658                 return -EOPNOTSUPP;
 659         }
 660 }
 661
 662 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 663                                  u8 *data)
 664 {
 665         int i;
 666
 667         switch (stringset) {
 668         case ETH_SS_STATS:
 669                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 670                         memcpy(data + i * ETH_GSTRING_LEN,
 671                                bcmgenet_gstrings_stats[i].stat_string,
 672                                ETH_GSTRING_LEN);
 673                 }
 674                 break;
 675         }
 676 }
 677
 678 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 679 {
 680         int i, j = 0;
 681
 682         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 683                 const struct bcmgenet_stats *s;
 684                 u8 offset = 0;
 685                 u32 val = 0;
 686                 char *p;
 687
 688                 s = &bcmgenet_gstrings_stats[i];
 689                 switch (s->type) {
 690                 case BCMGENET_STAT_NETDEV:
 691                 case BCMGENET_STAT_SOFT:
 692                         continue;
 693                 case BCMGENET_STAT_MIB_RX:
 694                 case BCMGENET_STAT_MIB_TX:
 695                 case BCMGENET_STAT_RUNT:
 696                         if (s->type != BCMGENET_STAT_MIB_RX)
 697                                 offset = BCMGENET_STAT_OFFSET;
 698                         val = bcmgenet_umac_readl(priv,
 699                                                   UMAC_MIB_START + j + offset);
 700                         break;
 701                 case BCMGENET_STAT_MISC:
 702                         val = bcmgenet_umac_readl(priv, s->reg_offset);
 703                         /* clear if overflowed */
 704                         if (val == ~0)
 705                                 bcmgenet_umac_writel(priv, 0, s->reg_offset);
 706                         break;
 707                 }
 708
 709                 j += s->stat_sizeof;
 710                 p = (char *)priv + s->stat_offset;
 711                 *(u32 *)p = val;
 712         }
 713 }
 714
 715 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 716                                        struct ethtool_stats *stats,
 717                                        u64 *data)
 718 {
 719         struct bcmgenet_priv *priv = netdev_priv(dev);
 720         int i;
 721
 722         if (netif_running(dev))
 723                 bcmgenet_update_mib_counters(priv);
 724
 725         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 726                 const struct bcmgenet_stats *s;
 727                 char *p;
 728
 729                 s = &bcmgenet_gstrings_stats[i];
 730                 if (s->type == BCMGENET_STAT_NETDEV)
 731                         p = (char *)&dev->stats;
 732                 else
 733                         p = (char *)priv;
 734                 p += s->stat_offset;
 735                 data[i] = *(u32 *)p;
 736         }
 737 }
 738
 739 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
 740 {
 741         struct bcmgenet_priv *priv = netdev_priv(dev);
 742         u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
 743         u32 reg;
 744
 745         if (enable && !priv->clk_eee_enabled) {
 746                 clk_prepare_enable(priv->clk_eee);
 747                 priv->clk_eee_enabled = true;
 748         }
 749
 750         reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
 751         if (enable)
 752                 reg |= EEE_EN;
 753         else
 754                 reg &= ~EEE_EN;
 755         bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
 756
 757         /* Enable EEE and switch to a 27Mhz clock automatically */
 758         reg = __raw_readl(priv->base + off);
 759         if (enable)
 760                 reg |= TBUF_EEE_EN | TBUF_PM_EN;
 761         else
 762                 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
 763         __raw_writel(reg, priv->base + off);
 764
 765         /* Do the same for thing for RBUF */
 766         reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
 767         if (enable)
 768                 reg |= RBUF_EEE_EN | RBUF_PM_EN;
 769         else
 770                 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
 771         bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
 772
 773         if (!enable && priv->clk_eee_enabled) {
 774                 clk_disable_unprepare(priv->clk_eee);
 775                 priv->clk_eee_enabled = false;
 776         }
 777
 778         priv->eee.eee_enabled = enable;
 779         priv->eee.eee_active = enable;
 780 }
 781
 782 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
 783 {
 784         struct bcmgenet_priv *priv = netdev_priv(dev);
 785         struct ethtool_eee *p = &priv->eee;
 786
 787         if (GENET_IS_V1(priv))
 788                 return -EOPNOTSUPP;
 789
 790         e->eee_enabled = p->eee_enabled;
 791         e->eee_active = p->eee_active;
 792         e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
 793
 794         return phy_ethtool_get_eee(priv->phydev, e);
 795 }
 796
 797 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
 798 {
 799         struct bcmgenet_priv *priv = netdev_priv(dev);
 800         struct ethtool_eee *p = &priv->eee;
 801         int ret = 0;
 802
 803         if (GENET_IS_V1(priv))
 804                 return -EOPNOTSUPP;
 805
 806         p->eee_enabled = e->eee_enabled;
 807
 808         if (!p->eee_enabled) {
 809                 bcmgenet_eee_enable_set(dev, false);
 810         } else {
 811                 ret = phy_init_eee(priv->phydev, 0);
 812                 if (ret) {
 813                         netif_err(priv, hw, dev, "EEE initialization failed\n");
 814                         return ret;
 815                 }
 816
 817                 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
 818                 bcmgenet_eee_enable_set(dev, true);
 819         }
 820
 821         return phy_ethtool_set_eee(priv->phydev, e);
 822 }
 823
 824 static int bcmgenet_nway_reset(struct net_device *dev)
 825 {
 826         struct bcmgenet_priv *priv = netdev_priv(dev);
 827
 828         return genphy_restart_aneg(priv->phydev);
 829 }
 830
 831 /* standard ethtool support functions. */
 832 static struct ethtool_ops bcmgenet_ethtool_ops = {
 833         .get_strings            = bcmgenet_get_strings,
 834         .get_sset_count         = bcmgenet_get_sset_count,
 835         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
 836         .get_settings           = bcmgenet_get_settings,
 837         .set_settings           = bcmgenet_set_settings,
 838         .get_drvinfo            = bcmgenet_get_drvinfo,
 839         .get_link               = ethtool_op_get_link,
 840         .get_msglevel           = bcmgenet_get_msglevel,
 841         .set_msglevel           = bcmgenet_set_msglevel,
 842         .get_wol                = bcmgenet_get_wol,
 843         .set_wol                = bcmgenet_set_wol,
 844         .get_eee                = bcmgenet_get_eee,
 845         .set_eee                = bcmgenet_set_eee,
 846         .nway_reset             = bcmgenet_nway_reset,
 847 };
 848
 849 /* Power down the unimac, based on mode. */
 850 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
 851                                 enum bcmgenet_power_mode mode)
 852 {
 853         int ret = 0;
 854         u32 reg;
 855
 856         switch (mode) {
 857         case GENET_POWER_CABLE_SENSE:
 858                 phy_detach(priv->phydev);
 859                 break;
 860
 861         case GENET_POWER_WOL_MAGIC:
 862                 ret = bcmgenet_wol_power_down_cfg(priv, mode);
 863                 break;
 864
 865         case GENET_POWER_PASSIVE:
 866                 /* Power down LED */
 867                 if (priv->hw_params->flags & GENET_HAS_EXT) {
 868                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 869                         reg |= (EXT_PWR_DOWN_PHY |
 870                                 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
 871                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 872
 873                         bcmgenet_phy_power_set(priv->dev, false);
 874                 }
 875                 break;
 876         default:
 877                 break;
 878         }
 879
 880         return 0;
 881 }
 882
 883 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
 884                               enum bcmgenet_power_mode mode)
 885 {
 886         u32 reg;
 887
 888         if (!(priv->hw_params->flags & GENET_HAS_EXT))
 889                 return;
 890
 891         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 892
 893         switch (mode) {
 894         case GENET_POWER_PASSIVE:
 895                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
 896                                 EXT_PWR_DOWN_BIAS);
 897                 /* fallthrough */
 898         case GENET_POWER_CABLE_SENSE:
 899                 /* enable APD */
 900                 reg |= EXT_PWR_DN_EN_LD;
 901                 break;
 902         case GENET_POWER_WOL_MAGIC:
 903                 bcmgenet_wol_power_up_cfg(priv, mode);
 904                 return;
 905         default:
 906                 break;
 907         }
 908
 909         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 910
 911         if (mode == GENET_POWER_PASSIVE)
 912                 bcmgenet_mii_reset(priv->dev);
 913 }
 914
 915 /* ioctl handle special commands that are not present in ethtool. */
 916 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 917 {
 918         struct bcmgenet_priv *priv = netdev_priv(dev);
 919         int val = 0;
 920
 921         if (!netif_running(dev))
 922                 return -EINVAL;
 923
 924         switch (cmd) {
 925         case SIOCGMIIPHY:
 926         case SIOCGMIIREG:
 927         case SIOCSMIIREG:
 928                 if (!priv->phydev)
 929                         val = -ENODEV;
 930                 else
 931                         val = phy_mii_ioctl(priv->phydev, rq, cmd);
 932                 break;
 933
 934         default:
 935                 val = -EINVAL;
 936                 break;
 937         }
 938
 939         return val;
 940 }
 941
 942 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
 943                                          struct bcmgenet_tx_ring *ring)
 944 {
 945         struct enet_cb *tx_cb_ptr;
 946
 947         tx_cb_ptr = ring->cbs;
 948         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
 949
 950         /* Advancing local write pointer */
 951         if (ring->write_ptr == ring->end_ptr)
 952                 ring->write_ptr = ring->cb_ptr;
 953         else
 954                 ring->write_ptr++;
 955
 956         return tx_cb_ptr;
 957 }
 958
 959 /* Simple helper to free a control block's resources */
 960 static void bcmgenet_free_cb(struct enet_cb *cb)
 961 {
 962         dev_kfree_skb_any(cb->skb);
 963         cb->skb = NULL;
 964         dma_unmap_addr_set(cb, dma_addr, 0);
 965 }
 966
 967 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
 968 {
 969         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
 970                                  INTRL2_CPU_MASK_SET);
 971 }
 972
 973 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
 974 {
 975         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
 976                                  INTRL2_CPU_MASK_CLEAR);
 977 }
 978
 979 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
 980 {
 981         bcmgenet_intrl2_1_writel(ring->priv,
 982                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
 983                                  INTRL2_CPU_MASK_SET);
 984 }
 985
 986 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
 987 {
 988         bcmgenet_intrl2_1_writel(ring->priv,
 989                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
 990                                  INTRL2_CPU_MASK_CLEAR);
 991 }
 992
 993 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
 994 {
 995         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
 996                                  INTRL2_CPU_MASK_SET);
 997 }
 998
 999 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1000 {
1001         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1002                                  INTRL2_CPU_MASK_CLEAR);
1003 }
1004
1005 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1006 {
1007         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1008                                  INTRL2_CPU_MASK_CLEAR);
1009 }
1010
1011 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1012 {
1013         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1014                                  INTRL2_CPU_MASK_SET);
1015 }
1016
1017 /* Unlocked version of the reclaim routine */
1018 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1019                                           struct bcmgenet_tx_ring *ring)
1020 {
1021         struct bcmgenet_priv *priv = netdev_priv(dev);
1022         struct enet_cb *tx_cb_ptr;
1023         struct netdev_queue *txq;
1024         unsigned int pkts_compl = 0;
1025         unsigned int c_index;
1026         unsigned int txbds_ready;
1027         unsigned int txbds_processed = 0;
1028
1029         /* Compute how many buffers are transmitted since last xmit call */
1030         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
1031         c_index &= DMA_C_INDEX_MASK;
1032
1033         if (likely(c_index >= ring->c_index))
1034                 txbds_ready = c_index - ring->c_index;
1035         else
1036                 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1037
1038         netif_dbg(priv, tx_done, dev,
1039                   "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1040                   __func__, ring->index, ring->c_index, c_index, txbds_ready);
1041
1042         /* Reclaim transmitted buffers */
1043         while (txbds_processed < txbds_ready) {
1044                 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1045                 if (tx_cb_ptr->skb) {
1046                         pkts_compl++;
1047                         dev->stats.tx_packets++;
1048                         dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1049                         dma_unmap_single(&dev->dev,
1050                                          dma_unmap_addr(tx_cb_ptr, dma_addr),
1051                                          tx_cb_ptr->skb->len,
1052                                          DMA_TO_DEVICE);
1053                         bcmgenet_free_cb(tx_cb_ptr);
1054                 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1055                         dev->stats.tx_bytes +=
1056                                 dma_unmap_len(tx_cb_ptr, dma_len);
1057                         dma_unmap_page(&dev->dev,
1058                                        dma_unmap_addr(tx_cb_ptr, dma_addr),
1059                                        dma_unmap_len(tx_cb_ptr, dma_len),
1060                                        DMA_TO_DEVICE);
1061                         dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1062                 }
1063
1064                 txbds_processed++;
1065                 if (likely(ring->clean_ptr < ring->end_ptr))
1066                         ring->clean_ptr++;
1067                 else
1068                         ring->clean_ptr = ring->cb_ptr;
1069         }
1070
1071         ring->free_bds += txbds_processed;
1072         ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1073
1074         if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1075                 txq = netdev_get_tx_queue(dev, ring->queue);
1076                 if (netif_tx_queue_stopped(txq))
1077                         netif_tx_wake_queue(txq);
1078         }
1079
1080         return pkts_compl;
1081 }
1082
1083 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1084                                 struct bcmgenet_tx_ring *ring)
1085 {
1086         unsigned int released;
1087         unsigned long flags;
1088
1089         spin_lock_irqsave(&ring->lock, flags);
1090         released = __bcmgenet_tx_reclaim(dev, ring);
1091         spin_unlock_irqrestore(&ring->lock, flags);
1092
1093         return released;
1094 }
1095
1096 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1097 {
1098         struct bcmgenet_tx_ring *ring =
1099                 container_of(napi, struct bcmgenet_tx_ring, napi);
1100         unsigned int work_done = 0;
1101
1102         work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1103
1104         if (work_done == 0) {
1105                 napi_complete(napi);
1106                 ring->int_enable(ring);
1107
1108                 return 0;
1109         }
1110
1111         return budget;
1112 }
1113
1114 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1115 {
1116         struct bcmgenet_priv *priv = netdev_priv(dev);
1117         int i;
1118
1119         if (netif_is_multiqueue(dev)) {
1120                 for (i = 0; i < priv->hw_params->tx_queues; i++)
1121                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1122         }
1123
1124         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1125 }
1126
1127 /* Transmits a single SKB (either head of a fragment or a single SKB)
1128  * caller must hold priv->lock
1129  */
1130 static int bcmgenet_xmit_single(struct net_device *dev,
1131                                 struct sk_buff *skb,
1132                                 u16 dma_desc_flags,
1133                                 struct bcmgenet_tx_ring *ring)
1134 {
1135         struct bcmgenet_priv *priv = netdev_priv(dev);
1136         struct device *kdev = &priv->pdev->dev;
1137         struct enet_cb *tx_cb_ptr;
1138         unsigned int skb_len;
1139         dma_addr_t mapping;
1140         u32 length_status;
1141         int ret;
1142
1143         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1144
1145         if (unlikely(!tx_cb_ptr))
1146                 BUG();
1147
1148         tx_cb_ptr->skb = skb;
1149
1150         skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1151
1152         mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1153         ret = dma_mapping_error(kdev, mapping);
1154         if (ret) {
1155                 priv->mib.tx_dma_failed++;
1156                 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1157                 dev_kfree_skb(skb);
1158                 return ret;
1159         }
1160
1161         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1162         dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1163         length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1164                         (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1165                         DMA_TX_APPEND_CRC;
1166
1167         if (skb->ip_summed == CHECKSUM_PARTIAL)
1168                 length_status |= DMA_TX_DO_CSUM;
1169
1170         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1171
1172         return 0;
1173 }
1174
1175 /* Transmit a SKB fragment */
1176 static int bcmgenet_xmit_frag(struct net_device *dev,
1177                               skb_frag_t *frag,
1178                               u16 dma_desc_flags,
1179                               struct bcmgenet_tx_ring *ring)
1180 {
1181         struct bcmgenet_priv *priv = netdev_priv(dev);
1182         struct device *kdev = &priv->pdev->dev;
1183         struct enet_cb *tx_cb_ptr;
1184         dma_addr_t mapping;
1185         int ret;
1186
1187         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1188
1189         if (unlikely(!tx_cb_ptr))
1190                 BUG();
1191         tx_cb_ptr->skb = NULL;
1192
1193         mapping = skb_frag_dma_map(kdev, frag, 0,
1194                                    skb_frag_size(frag), DMA_TO_DEVICE);
1195         ret = dma_mapping_error(kdev, mapping);
1196         if (ret) {
1197                 priv->mib.tx_dma_failed++;
1198                 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1199                           __func__);
1200                 return ret;
1201         }
1202
1203         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1204         dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1205
1206         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1207                     (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1208                     (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1209
1210         return 0;
1211 }
1212
1213 /* Reallocate the SKB to put enough headroom in front of it and insert
1214  * the transmit checksum offsets in the descriptors
1215  */
1216 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1217                                             struct sk_buff *skb)
1218 {
1219         struct status_64 *status = NULL;
1220         struct sk_buff *new_skb;
1221         u16 offset;
1222         u8 ip_proto;
1223         u16 ip_ver;
1224         u32 tx_csum_info;
1225
1226         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1227                 /* If 64 byte status block enabled, must make sure skb has
1228                  * enough headroom for us to insert 64B status block.
1229                  */
1230                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1231                 dev_kfree_skb(skb);
1232                 if (!new_skb) {
1233                         dev->stats.tx_errors++;
1234                         dev->stats.tx_dropped++;
1235                         return NULL;
1236                 }
1237                 skb = new_skb;
1238         }
1239
1240         skb_push(skb, sizeof(*status));
1241         status = (struct status_64 *)skb->data;
1242
1243         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1244                 ip_ver = htons(skb->protocol);
1245                 switch (ip_ver) {
1246                 case ETH_P_IP:
1247                         ip_proto = ip_hdr(skb)->protocol;
1248                         break;
1249                 case ETH_P_IPV6:
1250                         ip_proto = ipv6_hdr(skb)->nexthdr;
1251                         break;
1252                 default:
1253                         return skb;
1254                 }
1255
1256                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1257                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1258                                 (offset + skb->csum_offset);
1259
1260                 /* Set the length valid bit for TCP and UDP and just set
1261                  * the special UDP flag for IPv4, else just set to 0.
1262                  */
1263                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1264                         tx_csum_info |= STATUS_TX_CSUM_LV;
1265                         if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1266                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1267                 } else {
1268                         tx_csum_info = 0;
1269                 }
1270
1271                 status->tx_csum_info = tx_csum_info;
1272         }
1273
1274         return skb;
1275 }
1276
1277 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1278 {
1279         struct bcmgenet_priv *priv = netdev_priv(dev);
1280         struct bcmgenet_tx_ring *ring = NULL;
1281         struct netdev_queue *txq;
1282         unsigned long flags = 0;
1283         int nr_frags, index;
1284         u16 dma_desc_flags;
1285         int ret;
1286         int i;
1287
1288         index = skb_get_queue_mapping(skb);
1289         /* Mapping strategy:
1290          * queue_mapping = 0, unclassified, packet xmited through ring16
1291          * queue_mapping = 1, goes to ring 0. (highest priority queue
1292          * queue_mapping = 2, goes to ring 1.
1293          * queue_mapping = 3, goes to ring 2.
1294          * queue_mapping = 4, goes to ring 3.
1295          */
1296         if (index == 0)
1297                 index = DESC_INDEX;
1298         else
1299                 index -= 1;
1300
1301         nr_frags = skb_shinfo(skb)->nr_frags;
1302         ring = &priv->tx_rings[index];
1303         txq = netdev_get_tx_queue(dev, ring->queue);
1304
1305         spin_lock_irqsave(&ring->lock, flags);
1306         if (ring->free_bds <= nr_frags + 1) {
1307                 netif_tx_stop_queue(txq);
1308                 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1309                            __func__, index, ring->queue);
1310                 ret = NETDEV_TX_BUSY;
1311                 goto out;
1312         }
1313
1314         if (skb_padto(skb, ETH_ZLEN)) {
1315                 ret = NETDEV_TX_OK;
1316                 goto out;
1317         }
1318
1319         /* set the SKB transmit checksum */
1320         if (priv->desc_64b_en) {
1321                 skb = bcmgenet_put_tx_csum(dev, skb);
1322                 if (!skb) {
1323                         ret = NETDEV_TX_OK;
1324                         goto out;
1325                 }
1326         }
1327
1328         dma_desc_flags = DMA_SOP;
1329         if (nr_frags == 0)
1330                 dma_desc_flags |= DMA_EOP;
1331
1332         /* Transmit single SKB or head of fragment list */
1333         ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1334         if (ret) {
1335                 ret = NETDEV_TX_OK;
1336                 goto out;
1337         }
1338
1339         /* xmit fragment */
1340         for (i = 0; i < nr_frags; i++) {
1341                 ret = bcmgenet_xmit_frag(dev,
1342                                          &skb_shinfo(skb)->frags[i],
1343                                          (i == nr_frags - 1) ? DMA_EOP : 0,
1344                                          ring);
1345                 if (ret) {
1346                         ret = NETDEV_TX_OK;
1347                         goto out;
1348                 }
1349         }
1350
1351         skb_tx_timestamp(skb);
1352
1353         /* Decrement total BD count and advance our write pointer */
1354         ring->free_bds -= nr_frags + 1;
1355         ring->prod_index += nr_frags + 1;
1356         ring->prod_index &= DMA_P_INDEX_MASK;
1357
1358         if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1359                 netif_tx_stop_queue(txq);
1360
1361         if (!skb->xmit_more || netif_xmit_stopped(txq))
1362                 /* Packets are ready, update producer index */
1363                 bcmgenet_tdma_ring_writel(priv, ring->index,
1364                                           ring->prod_index, TDMA_PROD_INDEX);
1365 out:
1366         spin_unlock_irqrestore(&ring->lock, flags);
1367
1368         return ret;
1369 }
1370
1371 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1372                                           struct enet_cb *cb)
1373 {
1374         struct device *kdev = &priv->pdev->dev;
1375         struct sk_buff *skb;
1376         struct sk_buff *rx_skb;
1377         dma_addr_t mapping;
1378
1379         /* Allocate a new Rx skb */
1380         skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1381         if (!skb) {
1382                 priv->mib.alloc_rx_buff_failed++;
1383                 netif_err(priv, rx_err, priv->dev,
1384                           "%s: Rx skb allocation failed\n", __func__);
1385                 return NULL;
1386         }
1387
1388         /* DMA-map the new Rx skb */
1389         mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1390                                  DMA_FROM_DEVICE);
1391         if (dma_mapping_error(kdev, mapping)) {
1392                 priv->mib.rx_dma_failed++;
1393                 dev_kfree_skb_any(skb);
1394                 netif_err(priv, rx_err, priv->dev,
1395                           "%s: Rx skb DMA mapping failed\n", __func__);
1396                 return NULL;
1397         }
1398
1399         /* Grab the current Rx skb from the ring and DMA-unmap it */
1400         rx_skb = cb->skb;
1401         if (likely(rx_skb))
1402                 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1403                                  priv->rx_buf_len, DMA_FROM_DEVICE);
1404
1405         /* Put the new Rx skb on the ring */
1406         cb->skb = skb;
1407         dma_unmap_addr_set(cb, dma_addr, mapping);
1408         dmadesc_set_addr(priv, cb->bd_addr, mapping);
1409
1410         /* Return the current Rx skb to caller */
1411         return rx_skb;
1412 }
1413
1414 /* bcmgenet_desc_rx - descriptor based rx process.
1415  * this could be called from bottom half, or from NAPI polling method.
1416  */
1417 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1418                                      unsigned int budget)
1419 {
1420         struct bcmgenet_priv *priv = ring->priv;
1421         struct net_device *dev = priv->dev;
1422         struct enet_cb *cb;
1423         struct sk_buff *skb;
1424         u32 dma_length_status;
1425         unsigned long dma_flag;
1426         int len;
1427         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1428         unsigned int p_index;
1429         unsigned int discards;
1430         unsigned int chksum_ok = 0;
1431
1432         p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1433
1434         discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1435                    DMA_P_INDEX_DISCARD_CNT_MASK;
1436         if (discards > ring->old_discards) {
1437                 discards = discards - ring->old_discards;
1438                 dev->stats.rx_missed_errors += discards;
1439                 dev->stats.rx_errors += discards;
1440                 ring->old_discards += discards;
1441
1442                 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1443                 if (ring->old_discards >= 0xC000) {
1444                         ring->old_discards = 0;
1445                         bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1446                                                   RDMA_PROD_INDEX);
1447                 }
1448         }
1449
1450         p_index &= DMA_P_INDEX_MASK;
1451
1452         if (likely(p_index >= ring->c_index))
1453                 rxpkttoprocess = p_index - ring->c_index;
1454         else
1455                 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1456                                  p_index;
1457
1458         netif_dbg(priv, rx_status, dev,
1459                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1460
1461         while ((rxpktprocessed < rxpkttoprocess) &&
1462                (rxpktprocessed < budget)) {
1463                 cb = &priv->rx_cbs[ring->read_ptr];
1464                 skb = bcmgenet_rx_refill(priv, cb);
1465
1466                 if (unlikely(!skb)) {
1467                         dev->stats.rx_dropped++;
1468                         dev->stats.rx_errors++;
1469                         goto next;
1470                 }
1471
1472                 if (!priv->desc_64b_en) {
1473                         dma_length_status =
1474                                 dmadesc_get_length_status(priv, cb->bd_addr);
1475                 } else {
1476                         struct status_64 *status;
1477
1478                         status = (struct status_64 *)skb->data;
1479                         dma_length_status = status->length_status;
1480                 }
1481
1482                 /* DMA flags and length are still valid no matter how
1483                  * we got the Receive Status Vector (64B RSB or register)
1484                  */
1485                 dma_flag = dma_length_status & 0xffff;
1486                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1487
1488                 netif_dbg(priv, rx_status, dev,
1489                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1490                           __func__, p_index, ring->c_index,
1491                           ring->read_ptr, dma_length_status);
1492
1493                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1494                         netif_err(priv, rx_status, dev,
1495                                   "dropping fragmented packet!\n");
1496                         dev->stats.rx_dropped++;
1497                         dev->stats.rx_errors++;
1498                         dev_kfree_skb_any(skb);
1499                         goto next;
1500                 }
1501
1502                 /* report errors */
1503                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1504                                                 DMA_RX_OV |
1505                                                 DMA_RX_NO |
1506                                                 DMA_RX_LG |
1507                                                 DMA_RX_RXER))) {
1508                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1509                                   (unsigned int)dma_flag);
1510                         if (dma_flag & DMA_RX_CRC_ERROR)
1511                                 dev->stats.rx_crc_errors++;
1512                         if (dma_flag & DMA_RX_OV)
1513                                 dev->stats.rx_over_errors++;
1514                         if (dma_flag & DMA_RX_NO)
1515                                 dev->stats.rx_frame_errors++;
1516                         if (dma_flag & DMA_RX_LG)
1517                                 dev->stats.rx_length_errors++;
1518                         dev->stats.rx_dropped++;
1519                         dev->stats.rx_errors++;
1520                         dev_kfree_skb_any(skb);
1521                         goto next;
1522                 } /* error packet */
1523
1524                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1525                              priv->desc_rxchk_en;
1526
1527                 skb_put(skb, len);
1528                 if (priv->desc_64b_en) {
1529                         skb_pull(skb, 64);
1530                         len -= 64;
1531                 }
1532
1533                 if (likely(chksum_ok))
1534                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1535
1536                 /* remove hardware 2bytes added for IP alignment */
1537                 skb_pull(skb, 2);
1538                 len -= 2;
1539
1540                 if (priv->crc_fwd_en) {
1541                         skb_trim(skb, len - ETH_FCS_LEN);
1542                         len -= ETH_FCS_LEN;
1543                 }
1544
1545                 /*Finish setting up the received SKB and send it to the kernel*/
1546                 skb->protocol = eth_type_trans(skb, priv->dev);
1547                 dev->stats.rx_packets++;
1548                 dev->stats.rx_bytes += len;
1549                 if (dma_flag & DMA_RX_MULT)
1550                         dev->stats.multicast++;
1551
1552                 /* Notify kernel */
1553                 napi_gro_receive(&ring->napi, skb);
1554                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1555
1556 next:
1557                 rxpktprocessed++;
1558                 if (likely(ring->read_ptr < ring->end_ptr))
1559                         ring->read_ptr++;
1560                 else
1561                         ring->read_ptr = ring->cb_ptr;
1562
1563                 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1564                 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1565         }
1566
1567         return rxpktprocessed;
1568 }
1569
1570 /* Rx NAPI polling method */
1571 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1572 {
1573         struct bcmgenet_rx_ring *ring = container_of(napi,
1574                         struct bcmgenet_rx_ring, napi);
1575         unsigned int work_done;
1576
1577         work_done = bcmgenet_desc_rx(ring, budget);
1578
1579         if (work_done < budget) {
1580                 napi_complete(napi);
1581                 ring->int_enable(ring);
1582         }
1583
1584         return work_done;
1585 }
1586
1587 /* Assign skb to RX DMA descriptor. */
1588 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1589                                      struct bcmgenet_rx_ring *ring)
1590 {
1591         struct enet_cb *cb;
1592         struct sk_buff *skb;
1593         int i;
1594
1595         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1596
1597         /* loop here for each buffer needing assign */
1598         for (i = 0; i < ring->size; i++) {
1599                 cb = ring->cbs + i;
1600                 skb = bcmgenet_rx_refill(priv, cb);
1601                 if (skb)
1602                         dev_kfree_skb_any(skb);
1603                 if (!cb->skb)
1604                         return -ENOMEM;
1605         }
1606
1607         return 0;
1608 }
1609
1610 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1611 {
1612         struct enet_cb *cb;
1613         int i;
1614
1615         for (i = 0; i < priv->num_rx_bds; i++) {
1616                 cb = &priv->rx_cbs[i];
1617
1618                 if (dma_unmap_addr(cb, dma_addr)) {
1619                         dma_unmap_single(&priv->dev->dev,
1620                                          dma_unmap_addr(cb, dma_addr),
1621                                          priv->rx_buf_len, DMA_FROM_DEVICE);
1622                         dma_unmap_addr_set(cb, dma_addr, 0);
1623                 }
1624
1625                 if (cb->skb)
1626                         bcmgenet_free_cb(cb);
1627         }
1628 }
1629
1630 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1631 {
1632         u32 reg;
1633
1634         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1635         if (enable)
1636                 reg |= mask;
1637         else
1638                 reg &= ~mask;
1639         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1640
1641         /* UniMAC stops on a packet boundary, wait for a full-size packet
1642          * to be processed
1643          */
1644         if (enable == 0)
1645                 usleep_range(1000, 2000);
1646 }
1647
1648 static int reset_umac(struct bcmgenet_priv *priv)
1649 {
1650         struct device *kdev = &priv->pdev->dev;
1651         unsigned int timeout = 0;
1652         u32 reg;
1653
1654         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1655         bcmgenet_rbuf_ctrl_set(priv, 0);
1656         udelay(10);
1657
1658         /* disable MAC while updating its registers */
1659         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1660
1661         /* issue soft reset, wait for it to complete */
1662         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1663         while (timeout++ < 1000) {
1664                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1665                 if (!(reg & CMD_SW_RESET))
1666                         return 0;
1667
1668                 udelay(1);
1669         }
1670
1671         if (timeout == 1000) {
1672                 dev_err(kdev,
1673                         "timeout waiting for MAC to come out of reset\n");
1674                 return -ETIMEDOUT;
1675         }
1676
1677         return 0;
1678 }
1679
1680 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1681 {
1682         /* Mask all interrupts.*/
1683         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1684         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1685         bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1686         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1687         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1688         bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1689 }
1690
1691 static int init_umac(struct bcmgenet_priv *priv)
1692 {
1693         struct device *kdev = &priv->pdev->dev;
1694         int ret;
1695         u32 reg;
1696         u32 int0_enable = 0;
1697         u32 int1_enable = 0;
1698         int i;
1699
1700         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1701
1702         ret = reset_umac(priv);
1703         if (ret)
1704                 return ret;
1705
1706         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1707         /* clear tx/rx counter */
1708         bcmgenet_umac_writel(priv,
1709                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1710                              UMAC_MIB_CTRL);
1711         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1712
1713         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1714
1715         /* init rx registers, enable ip header optimization */
1716         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1717         reg |= RBUF_ALIGN_2B;
1718         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1719
1720         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1721                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1722
1723         bcmgenet_intr_disable(priv);
1724
1725         /* Enable Rx default queue 16 interrupts */
1726         int0_enable |= UMAC_IRQ_RXDMA_DONE;
1727
1728         /* Enable Tx default queue 16 interrupts */
1729         int0_enable |= UMAC_IRQ_TXDMA_DONE;
1730
1731         /* Monitor cable plug/unplugged event for internal PHY */
1732         if (phy_is_internal(priv->phydev)) {
1733                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1734         } else if (priv->ext_phy) {
1735                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1736         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1737                 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1738                         int0_enable |= UMAC_IRQ_LINK_EVENT;
1739
1740                 reg = bcmgenet_bp_mc_get(priv);
1741                 reg |= BIT(priv->hw_params->bp_in_en_shift);
1742
1743                 /* bp_mask: back pressure mask */
1744                 if (netif_is_multiqueue(priv->dev))
1745                         reg |= priv->hw_params->bp_in_mask;
1746                 else
1747                         reg &= ~priv->hw_params->bp_in_mask;
1748                 bcmgenet_bp_mc_set(priv, reg);
1749         }
1750
1751         /* Enable MDIO interrupts on GENET v3+ */
1752         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1753                 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1754
1755         /* Enable Rx priority queue interrupts */
1756         for (i = 0; i < priv->hw_params->rx_queues; ++i)
1757                 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1758
1759         /* Enable Tx priority queue interrupts */
1760         for (i = 0; i < priv->hw_params->tx_queues; ++i)
1761                 int1_enable |= (1 << i);
1762
1763         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1764         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
1765
1766         /* Enable rx/tx engine.*/
1767         dev_dbg(kdev, "done init umac\n");
1768
1769         return 0;
1770 }
1771
1772 /* Initialize a Tx ring along with corresponding hardware registers */
1773 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1774                                   unsigned int index, unsigned int size,
1775                                   unsigned int start_ptr, unsigned int end_ptr)
1776 {
1777         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1778         u32 words_per_bd = WORDS_PER_BD(priv);
1779         u32 flow_period_val = 0;
1780
1781         spin_lock_init(&ring->lock);
1782         ring->priv = priv;
1783         ring->index = index;
1784         if (index == DESC_INDEX) {
1785                 ring->queue = 0;
1786                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1787                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1788         } else {
1789                 ring->queue = index + 1;
1790                 ring->int_enable = bcmgenet_tx_ring_int_enable;
1791                 ring->int_disable = bcmgenet_tx_ring_int_disable;
1792         }
1793         ring->cbs = priv->tx_cbs + start_ptr;
1794         ring->size = size;
1795         ring->clean_ptr = start_ptr;
1796         ring->c_index = 0;
1797         ring->free_bds = size;
1798         ring->write_ptr = start_ptr;
1799         ring->cb_ptr = start_ptr;
1800         ring->end_ptr = end_ptr - 1;
1801         ring->prod_index = 0;
1802
1803         /* Set flow period for ring != 16 */
1804         if (index != DESC_INDEX)
1805                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1806
1807         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1808         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1809         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1810         /* Disable rate control for now */
1811         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1812                                   TDMA_FLOW_PERIOD);
1813         bcmgenet_tdma_ring_writel(priv, index,
1814                                   ((size << DMA_RING_SIZE_SHIFT) |
1815                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1816
1817         /* Set start and end address, read and write pointers */
1818         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1819                                   DMA_START_ADDR);
1820         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1821                                   TDMA_READ_PTR);
1822         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1823                                   TDMA_WRITE_PTR);
1824         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1825                                   DMA_END_ADDR);
1826 }
1827
1828 /* Initialize a RDMA ring */
1829 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1830                                  unsigned int index, unsigned int size,
1831                                  unsigned int start_ptr, unsigned int end_ptr)
1832 {
1833         struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1834         u32 words_per_bd = WORDS_PER_BD(priv);
1835         int ret;
1836
1837         ring->priv = priv;
1838         ring->index = index;
1839         if (index == DESC_INDEX) {
1840                 ring->int_enable = bcmgenet_rx_ring16_int_enable;
1841                 ring->int_disable = bcmgenet_rx_ring16_int_disable;
1842         } else {
1843                 ring->int_enable = bcmgenet_rx_ring_int_enable;
1844                 ring->int_disable = bcmgenet_rx_ring_int_disable;
1845         }
1846         ring->cbs = priv->rx_cbs + start_ptr;
1847         ring->size = size;
1848         ring->c_index = 0;
1849         ring->read_ptr = start_ptr;
1850         ring->cb_ptr = start_ptr;
1851         ring->end_ptr = end_ptr - 1;
1852
1853         ret = bcmgenet_alloc_rx_buffers(priv, ring);
1854         if (ret)
1855                 return ret;
1856
1857         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1858         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1859         bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1860         bcmgenet_rdma_ring_writel(priv, index,
1861                                   ((size << DMA_RING_SIZE_SHIFT) |
1862                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1863         bcmgenet_rdma_ring_writel(priv, index,
1864                                   (DMA_FC_THRESH_LO <<
1865                                    DMA_XOFF_THRESHOLD_SHIFT) |
1866                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1867
1868         /* Set start and end address, read and write pointers */
1869         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1870                                   DMA_START_ADDR);
1871         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1872                                   RDMA_READ_PTR);
1873         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1874                                   RDMA_WRITE_PTR);
1875         bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1876                                   DMA_END_ADDR);
1877
1878         return ret;
1879 }
1880
1881 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
1882 {
1883         unsigned int i;
1884         struct bcmgenet_tx_ring *ring;
1885
1886         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1887                 ring = &priv->tx_rings[i];
1888                 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1889         }
1890
1891         ring = &priv->tx_rings[DESC_INDEX];
1892         netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1893 }
1894
1895 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
1896 {
1897         unsigned int i;
1898         struct bcmgenet_tx_ring *ring;
1899
1900         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1901                 ring = &priv->tx_rings[i];
1902                 napi_enable(&ring->napi);
1903         }
1904
1905         ring = &priv->tx_rings[DESC_INDEX];
1906         napi_enable(&ring->napi);
1907 }
1908
1909 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
1910 {
1911         unsigned int i;
1912         struct bcmgenet_tx_ring *ring;
1913
1914         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1915                 ring = &priv->tx_rings[i];
1916                 napi_disable(&ring->napi);
1917         }
1918
1919         ring = &priv->tx_rings[DESC_INDEX];
1920         napi_disable(&ring->napi);
1921 }
1922
1923 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
1924 {
1925         unsigned int i;
1926         struct bcmgenet_tx_ring *ring;
1927
1928         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1929                 ring = &priv->tx_rings[i];
1930                 netif_napi_del(&ring->napi);
1931         }
1932
1933         ring = &priv->tx_rings[DESC_INDEX];
1934         netif_napi_del(&ring->napi);
1935 }
1936
1937 /* Initialize Tx queues
1938  *
1939  * Queues 0-3 are priority-based, each one has 32 descriptors,
1940  * with queue 0 being the highest priority queue.
1941  *
1942  * Queue 16 is the default Tx queue with
1943  * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1944  *
1945  * The transmit control block pool is then partitioned as follows:
1946  * - Tx queue 0 uses tx_cbs[0..31]
1947  * - Tx queue 1 uses tx_cbs[32..63]
1948  * - Tx queue 2 uses tx_cbs[64..95]
1949  * - Tx queue 3 uses tx_cbs[96..127]
1950  * - Tx queue 16 uses tx_cbs[128..255]
1951  */
1952 static void bcmgenet_init_tx_queues(struct net_device *dev)
1953 {
1954         struct bcmgenet_priv *priv = netdev_priv(dev);
1955         u32 i, dma_enable;
1956         u32 dma_ctrl, ring_cfg;
1957         u32 dma_priority[3] = {0, 0, 0};
1958
1959         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1960         dma_enable = dma_ctrl & DMA_EN;
1961         dma_ctrl &= ~DMA_EN;
1962         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1963
1964         dma_ctrl = 0;
1965         ring_cfg = 0;
1966
1967         /* Enable strict priority arbiter mode */
1968         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1969
1970         /* Initialize Tx priority queues */
1971         for (i = 0; i < priv->hw_params->tx_queues; i++) {
1972                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
1973                                       i * priv->hw_params->tx_bds_per_q,
1974                                       (i + 1) * priv->hw_params->tx_bds_per_q);
1975                 ring_cfg |= (1 << i);
1976                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
1977                 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1978                         ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1979         }
1980
1981         /* Initialize Tx default queue 16 */
1982         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
1983                               priv->hw_params->tx_queues *
1984                               priv->hw_params->tx_bds_per_q,
1985                               TOTAL_DESC);
1986         ring_cfg |= (1 << DESC_INDEX);
1987         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
1988         dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1989                 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1990                  DMA_PRIO_REG_SHIFT(DESC_INDEX));
1991
1992         /* Set Tx queue priorities */
1993         bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1994         bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1995         bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1996
1997         /* Initialize Tx NAPI */
1998         bcmgenet_init_tx_napi(priv);
1999
2000         /* Enable Tx queues */
2001         bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2002
2003         /* Enable Tx DMA */
2004         if (dma_enable)
2005                 dma_ctrl |= DMA_EN;
2006         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2007 }
2008
2009 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2010 {
2011         unsigned int i;
2012         struct bcmgenet_rx_ring *ring;
2013
2014         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2015                 ring = &priv->rx_rings[i];
2016                 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2017         }
2018
2019         ring = &priv->rx_rings[DESC_INDEX];
2020         netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2021 }
2022
2023 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2024 {
2025         unsigned int i;
2026         struct bcmgenet_rx_ring *ring;
2027
2028         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2029                 ring = &priv->rx_rings[i];
2030                 napi_enable(&ring->napi);
2031         }
2032
2033         ring = &priv->rx_rings[DESC_INDEX];
2034         napi_enable(&ring->napi);
2035 }
2036
2037 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2038 {
2039         unsigned int i;
2040         struct bcmgenet_rx_ring *ring;
2041
2042         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2043                 ring = &priv->rx_rings[i];
2044                 napi_disable(&ring->napi);
2045         }
2046
2047         ring = &priv->rx_rings[DESC_INDEX];
2048         napi_disable(&ring->napi);
2049 }
2050
2051 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2052 {
2053         unsigned int i;
2054         struct bcmgenet_rx_ring *ring;
2055
2056         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2057                 ring = &priv->rx_rings[i];
2058                 netif_napi_del(&ring->napi);
2059         }
2060
2061         ring = &priv->rx_rings[DESC_INDEX];
2062         netif_napi_del(&ring->napi);
2063 }
2064
2065 /* Initialize Rx queues
2066  *
2067  * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2068  * used to direct traffic to these queues.
2069  *
2070  * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2071  */
2072 static int bcmgenet_init_rx_queues(struct net_device *dev)
2073 {
2074         struct bcmgenet_priv *priv = netdev_priv(dev);
2075         u32 i;
2076         u32 dma_enable;
2077         u32 dma_ctrl;
2078         u32 ring_cfg;
2079         int ret;
2080
2081         dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2082         dma_enable = dma_ctrl & DMA_EN;
2083         dma_ctrl &= ~DMA_EN;
2084         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2085
2086         dma_ctrl = 0;
2087         ring_cfg = 0;
2088
2089         /* Initialize Rx priority queues */
2090         for (i = 0; i < priv->hw_params->rx_queues; i++) {
2091                 ret = bcmgenet_init_rx_ring(priv, i,
2092                                             priv->hw_params->rx_bds_per_q,
2093                                             i * priv->hw_params->rx_bds_per_q,
2094                                             (i + 1) *
2095                                             priv->hw_params->rx_bds_per_q);
2096                 if (ret)
2097                         return ret;
2098
2099                 ring_cfg |= (1 << i);
2100                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2101         }
2102
2103         /* Initialize Rx default queue 16 */
2104         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2105                                     priv->hw_params->rx_queues *
2106                                     priv->hw_params->rx_bds_per_q,
2107                                     TOTAL_DESC);
2108         if (ret)
2109                 return ret;
2110
2111         ring_cfg |= (1 << DESC_INDEX);
2112         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2113
2114         /* Initialize Rx NAPI */
2115         bcmgenet_init_rx_napi(priv);
2116
2117         /* Enable rings */
2118         bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2119
2120         /* Configure ring as descriptor ring and re-enable DMA if enabled */
2121         if (dma_enable)
2122                 dma_ctrl |= DMA_EN;
2123         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2124
2125         return 0;
2126 }
2127
2128 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2129 {
2130         int ret = 0;
2131         int timeout = 0;
2132         u32 reg;
2133
2134         /* Disable TDMA to stop add more frames in TX DMA */
2135         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2136         reg &= ~DMA_EN;
2137         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2138
2139         /* Check TDMA status register to confirm TDMA is disabled */
2140         while (timeout++ < DMA_TIMEOUT_VAL) {
2141                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2142                 if (reg & DMA_DISABLED)
2143                         break;
2144
2145                 udelay(1);
2146         }
2147
2148         if (timeout == DMA_TIMEOUT_VAL) {
2149                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2150                 ret = -ETIMEDOUT;
2151         }
2152
2153         /* Wait 10ms for packet drain in both tx and rx dma */
2154         usleep_range(10000, 20000);
2155
2156         /* Disable RDMA */
2157         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2158         reg &= ~DMA_EN;
2159         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2160
2161         timeout = 0;
2162         /* Check RDMA status register to confirm RDMA is disabled */
2163         while (timeout++ < DMA_TIMEOUT_VAL) {
2164                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2165                 if (reg & DMA_DISABLED)
2166                         break;
2167
2168                 udelay(1);
2169         }
2170
2171         if (timeout == DMA_TIMEOUT_VAL) {
2172                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2173                 ret = -ETIMEDOUT;
2174         }
2175
2176         return ret;
2177 }
2178
2179 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2180 {
2181         int i;
2182
2183         bcmgenet_fini_rx_napi(priv);
2184         bcmgenet_fini_tx_napi(priv);
2185
2186         /* disable DMA */
2187         bcmgenet_dma_teardown(priv);
2188
2189         for (i = 0; i < priv->num_tx_bds; i++) {
2190                 if (priv->tx_cbs[i].skb != NULL) {
2191                         dev_kfree_skb(priv->tx_cbs[i].skb);
2192                         priv->tx_cbs[i].skb = NULL;
2193                 }
2194         }
2195
2196         bcmgenet_free_rx_buffers(priv);
2197         kfree(priv->rx_cbs);
2198         kfree(priv->tx_cbs);
2199 }
2200
2201 /* init_edma: Initialize DMA control register */
2202 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2203 {
2204         int ret;
2205         unsigned int i;
2206         struct enet_cb *cb;
2207
2208         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2209
2210         /* Initialize common Rx ring structures */
2211         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2212         priv->num_rx_bds = TOTAL_DESC;
2213         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2214                                GFP_KERNEL);
2215         if (!priv->rx_cbs)
2216                 return -ENOMEM;
2217
2218         for (i = 0; i < priv->num_rx_bds; i++) {
2219                 cb = priv->rx_cbs + i;
2220                 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2221         }
2222
2223         /* Initialize common TX ring structures */
2224         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2225         priv->num_tx_bds = TOTAL_DESC;
2226         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2227                                GFP_KERNEL);
2228         if (!priv->tx_cbs) {
2229                 kfree(priv->rx_cbs);
2230                 return -ENOMEM;
2231         }
2232
2233         for (i = 0; i < priv->num_tx_bds; i++) {
2234                 cb = priv->tx_cbs + i;
2235                 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2236         }
2237
2238         /* Init rDma */
2239         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2240
2241         /* Initialize Rx queues */
2242         ret = bcmgenet_init_rx_queues(priv->dev);
2243         if (ret) {
2244                 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2245                 bcmgenet_free_rx_buffers(priv);
2246                 kfree(priv->rx_cbs);
2247                 kfree(priv->tx_cbs);
2248                 return ret;
2249         }
2250
2251         /* Init tDma */
2252         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2253
2254         /* Initialize Tx queues */
2255         bcmgenet_init_tx_queues(priv->dev);
2256
2257         return 0;
2258 }
2259
2260 /* Interrupt bottom half */
2261 static void bcmgenet_irq_task(struct work_struct *work)
2262 {
2263         struct bcmgenet_priv *priv = container_of(
2264                         work, struct bcmgenet_priv, bcmgenet_irq_work);
2265
2266         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2267
2268         if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2269                 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2270                 netif_dbg(priv, wol, priv->dev,
2271                           "magic packet detected, waking up\n");
2272                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2273         }
2274
2275         /* Link UP/DOWN event */
2276         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2277             (priv->irq0_stat & UMAC_IRQ_LINK_EVENT)) {
2278                 phy_mac_interrupt(priv->phydev,
2279                                   !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
2280                 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
2281         }
2282 }
2283
2284 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2285 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2286 {
2287         struct bcmgenet_priv *priv = dev_id;
2288         struct bcmgenet_rx_ring *rx_ring;
2289         struct bcmgenet_tx_ring *tx_ring;
2290         unsigned int index;
2291
2292         /* Save irq status for bottom-half processing. */
2293         priv->irq1_stat =
2294                 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2295                 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2296
2297         /* clear interrupts */
2298         bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2299
2300         netif_dbg(priv, intr, priv->dev,
2301                   "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
2302
2303         /* Check Rx priority queue interrupts */
2304         for (index = 0; index < priv->hw_params->rx_queues; index++) {
2305                 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2306                         continue;
2307
2308                 rx_ring = &priv->rx_rings[index];
2309
2310                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2311                         rx_ring->int_disable(rx_ring);
2312                         __napi_schedule(&rx_ring->napi);
2313                 }
2314         }
2315
2316         /* Check Tx priority queue interrupts */
2317         for (index = 0; index < priv->hw_params->tx_queues; index++) {
2318                 if (!(priv->irq1_stat & BIT(index)))
2319                         continue;
2320
2321                 tx_ring = &priv->tx_rings[index];
2322
2323                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2324                         tx_ring->int_disable(tx_ring);
2325                         __napi_schedule(&tx_ring->napi);
2326                 }
2327         }
2328
2329         return IRQ_HANDLED;
2330 }
2331
2332 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2333 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2334 {
2335         struct bcmgenet_priv *priv = dev_id;
2336         struct bcmgenet_rx_ring *rx_ring;
2337         struct bcmgenet_tx_ring *tx_ring;
2338
2339         /* Save irq status for bottom-half processing. */
2340         priv->irq0_stat =
2341                 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2342                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2343
2344         /* clear interrupts */
2345         bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2346
2347         netif_dbg(priv, intr, priv->dev,
2348                   "IRQ=0x%x\n", priv->irq0_stat);
2349
2350         if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
2351                 rx_ring = &priv->rx_rings[DESC_INDEX];
2352
2353                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2354                         rx_ring->int_disable(rx_ring);
2355                         __napi_schedule(&rx_ring->napi);
2356                 }
2357         }
2358
2359         if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
2360                 tx_ring = &priv->tx_rings[DESC_INDEX];
2361
2362                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2363                         tx_ring->int_disable(tx_ring);
2364                         __napi_schedule(&tx_ring->napi);
2365                 }
2366         }
2367
2368         if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2369                                 UMAC_IRQ_PHY_DET_F |
2370                                 UMAC_IRQ_LINK_EVENT |
2371                                 UMAC_IRQ_HFB_SM |
2372                                 UMAC_IRQ_HFB_MM |
2373                                 UMAC_IRQ_MPD_R)) {
2374                 /* all other interested interrupts handled in bottom half */
2375                 schedule_work(&priv->bcmgenet_irq_work);
2376         }
2377
2378         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2379             priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2380                 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2381                 wake_up(&priv->wq);
2382         }
2383
2384         return IRQ_HANDLED;
2385 }
2386
2387 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2388 {
2389         struct bcmgenet_priv *priv = dev_id;
2390
2391         pm_wakeup_event(&priv->pdev->dev, 0);
2392
2393         return IRQ_HANDLED;
2394 }
2395
2396 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2397 {
2398         u32 reg;
2399
2400         reg = bcmgenet_rbuf_ctrl_get(priv);
2401         reg |= BIT(1);
2402         bcmgenet_rbuf_ctrl_set(priv, reg);
2403         udelay(10);
2404
2405         reg &= ~BIT(1);
2406         bcmgenet_rbuf_ctrl_set(priv, reg);
2407         udelay(10);
2408 }
2409
2410 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2411                                  unsigned char *addr)
2412 {
2413         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2414                         (addr[2] << 8) | addr[3], UMAC_MAC0);
2415         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2416 }
2417
2418 /* Returns a reusable dma control register value */
2419 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2420 {
2421         u32 reg;
2422         u32 dma_ctrl;
2423
2424         /* disable DMA */
2425         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2426         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2427         reg &= ~dma_ctrl;
2428         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2429
2430         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2431         reg &= ~dma_ctrl;
2432         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2433
2434         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2435         udelay(10);
2436         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2437
2438         return dma_ctrl;
2439 }
2440
2441 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2442 {
2443         u32 reg;
2444
2445         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2446         reg |= dma_ctrl;
2447         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2448
2449         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2450         reg |= dma_ctrl;
2451         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2452 }
2453
2454 static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2455                                            u32 f_index)
2456 {
2457         u32 offset;
2458         u32 reg;
2459
2460         offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2461         reg = bcmgenet_hfb_reg_readl(priv, offset);
2462         return !!(reg & (1 << (f_index % 32)));
2463 }
2464
2465 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2466 {
2467         u32 offset;
2468         u32 reg;
2469
2470         offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2471         reg = bcmgenet_hfb_reg_readl(priv, offset);
2472         reg |= (1 << (f_index % 32));
2473         bcmgenet_hfb_reg_writel(priv, reg, offset);
2474 }
2475
2476 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2477                                                      u32 f_index, u32 rx_queue)
2478 {
2479         u32 offset;
2480         u32 reg;
2481
2482         offset = f_index / 8;
2483         reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2484         reg &= ~(0xF << (4 * (f_index % 8)));
2485         reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2486         bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2487 }
2488
2489 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2490                                            u32 f_index, u32 f_length)
2491 {
2492         u32 offset;
2493         u32 reg;
2494
2495         offset = HFB_FLT_LEN_V3PLUS +
2496                  ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2497                  sizeof(u32);
2498         reg = bcmgenet_hfb_reg_readl(priv, offset);
2499         reg &= ~(0xFF << (8 * (f_index % 4)));
2500         reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2501         bcmgenet_hfb_reg_writel(priv, reg, offset);
2502 }
2503
2504 static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2505 {
2506         u32 f_index;
2507
2508         for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2509                 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2510                         return f_index;
2511
2512         return -ENOMEM;
2513 }
2514
2515 /* bcmgenet_hfb_add_filter
2516  *
2517  * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2518  * desired Rx queue.
2519  *
2520  * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2521  * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2522  *
2523  * bits 31:20 - unused
2524  * bit  19    - nibble 0 match enable
2525  * bit  18    - nibble 1 match enable
2526  * bit  17    - nibble 2 match enable
2527  * bit  16    - nibble 3 match enable
2528  * bits 15:12 - nibble 0 data
2529  * bits 11:8  - nibble 1 data
2530  * bits 7:4   - nibble 2 data
2531  * bits 3:0   - nibble 3 data
2532  *
2533  * Example:
2534  * In order to match:
2535  * - Ethernet frame type = 0x0800 (IP)
2536  * - IP version field = 4
2537  * - IP protocol field = 0x11 (UDP)
2538  *
2539  * The following filter is needed:
2540  * u32 hfb_filter_ipv4_udp[] = {
2541  *   Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2542  *   Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2543  *   Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2544  * };
2545  *
2546  * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2547  * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2548  *                         ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2549  */
2550 int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2551                             u32 f_length, u32 rx_queue)
2552 {
2553         int f_index;
2554         u32 i;
2555
2556         f_index = bcmgenet_hfb_find_unused_filter(priv);
2557         if (f_index < 0)
2558                 return -ENOMEM;
2559
2560         if (f_length > priv->hw_params->hfb_filter_size)
2561                 return -EINVAL;
2562
2563         for (i = 0; i < f_length; i++)
2564                 bcmgenet_hfb_writel(priv, f_data[i],
2565                         (f_index * priv->hw_params->hfb_filter_size + i) *
2566                         sizeof(u32));
2567
2568         bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2569         bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2570         bcmgenet_hfb_enable_filter(priv, f_index);
2571         bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2572
2573         return 0;
2574 }
2575
2576 /* bcmgenet_hfb_clear
2577  *
2578  * Clear Hardware Filter Block and disable all filtering.
2579  */
2580 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2581 {
2582         u32 i;
2583
2584         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2585         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2586         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2587
2588         for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2589                 bcmgenet_rdma_writel(priv, 0x0, i);
2590
2591         for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2592                 bcmgenet_hfb_reg_writel(priv, 0x0,
2593                                         HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2594
2595         for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2596                         priv->hw_params->hfb_filter_size; i++)
2597                 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2598 }
2599
2600 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2601 {
2602         if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2603                 return;
2604
2605         bcmgenet_hfb_clear(priv);
2606 }
2607
2608 static void bcmgenet_netif_start(struct net_device *dev)
2609 {
2610         struct bcmgenet_priv *priv = netdev_priv(dev);
2611
2612         /* Start the network engine */
2613         bcmgenet_enable_rx_napi(priv);
2614         bcmgenet_enable_tx_napi(priv);
2615
2616         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2617
2618         netif_tx_start_all_queues(dev);
2619
2620         phy_start(priv->phydev);
2621 }
2622
2623 static int bcmgenet_open(struct net_device *dev)
2624 {
2625         struct bcmgenet_priv *priv = netdev_priv(dev);
2626         unsigned long dma_ctrl;
2627         u32 reg;
2628         int ret;
2629
2630         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2631
2632         /* Turn on the clock */
2633         if (!IS_ERR(priv->clk))
2634                 clk_prepare_enable(priv->clk);
2635
2636         /* If this is an internal GPHY, power it back on now, before UniMAC is
2637          * brought out of reset as absolutely no UniMAC activity is allowed
2638          */
2639         if (phy_is_internal(priv->phydev))
2640                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2641
2642         /* take MAC out of reset */
2643         bcmgenet_umac_reset(priv);
2644
2645         ret = init_umac(priv);
2646         if (ret)
2647                 goto err_clk_disable;
2648
2649         /* disable ethernet MAC while updating its registers */
2650         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2651
2652         /* Make sure we reflect the value of CRC_CMD_FWD */
2653         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2654         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2655
2656         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2657
2658         if (phy_is_internal(priv->phydev)) {
2659                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2660                 reg |= EXT_ENERGY_DET_MASK;
2661                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2662         }
2663
2664         /* Disable RX/TX DMA and flush TX queues */
2665         dma_ctrl = bcmgenet_dma_disable(priv);
2666
2667         /* Reinitialize TDMA and RDMA and SW housekeeping */
2668         ret = bcmgenet_init_dma(priv);
2669         if (ret) {
2670                 netdev_err(dev, "failed to initialize DMA\n");
2671                 goto err_clk_disable;
2672         }
2673
2674         /* Always enable ring 16 - descriptor ring */
2675         bcmgenet_enable_dma(priv, dma_ctrl);
2676
2677         /* HFB init */
2678         bcmgenet_hfb_init(priv);
2679
2680         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2681                           dev->name, priv);
2682         if (ret < 0) {
2683                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2684                 goto err_fini_dma;
2685         }
2686
2687         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2688                           dev->name, priv);
2689         if (ret < 0) {
2690                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2691                 goto err_irq0;
2692         }
2693
2694         /* Re-configure the port multiplexer towards the PHY device */
2695         bcmgenet_mii_config(priv->dev, false);
2696
2697         phy_connect_direct(dev, priv->phydev, bcmgenet_mii_setup,
2698                            priv->phy_interface);
2699
2700         bcmgenet_netif_start(dev);
2701
2702         return 0;
2703
2704 err_irq0:
2705         free_irq(priv->irq0, dev);
2706 err_fini_dma:
2707         bcmgenet_fini_dma(priv);
2708 err_clk_disable:
2709         if (!IS_ERR(priv->clk))
2710                 clk_disable_unprepare(priv->clk);
2711         return ret;
2712 }
2713
2714 static void bcmgenet_netif_stop(struct net_device *dev)
2715 {
2716         struct bcmgenet_priv *priv = netdev_priv(dev);
2717
2718         netif_tx_stop_all_queues(dev);
2719         phy_stop(priv->phydev);
2720         bcmgenet_intr_disable(priv);
2721         bcmgenet_disable_rx_napi(priv);
2722         bcmgenet_disable_tx_napi(priv);
2723
2724         /* Wait for pending work items to complete. Since interrupts are
2725          * disabled no new work will be scheduled.
2726          */
2727         cancel_work_sync(&priv->bcmgenet_irq_work);
2728
2729         priv->old_link = -1;
2730         priv->old_speed = -1;
2731         priv->old_duplex = -1;
2732         priv->old_pause = -1;
2733 }
2734
2735 static int bcmgenet_close(struct net_device *dev)
2736 {
2737         struct bcmgenet_priv *priv = netdev_priv(dev);
2738         int ret;
2739
2740         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2741
2742         bcmgenet_netif_stop(dev);
2743
2744         /* Really kill the PHY state machine and disconnect from it */
2745         phy_disconnect(priv->phydev);
2746
2747         /* Disable MAC receive */
2748         umac_enable_set(priv, CMD_RX_EN, false);
2749
2750         ret = bcmgenet_dma_teardown(priv);
2751         if (ret)
2752                 return ret;
2753
2754         /* Disable MAC transmit. TX DMA disabled have to done before this */
2755         umac_enable_set(priv, CMD_TX_EN, false);
2756
2757         /* tx reclaim */
2758         bcmgenet_tx_reclaim_all(dev);
2759         bcmgenet_fini_dma(priv);
2760
2761         free_irq(priv->irq0, priv);
2762         free_irq(priv->irq1, priv);
2763
2764         if (phy_is_internal(priv->phydev))
2765                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2766
2767         if (!IS_ERR(priv->clk))
2768                 clk_disable_unprepare(priv->clk);
2769
2770         return ret;
2771 }
2772
2773 static void bcmgenet_timeout(struct net_device *dev)
2774 {
2775         struct bcmgenet_priv *priv = netdev_priv(dev);
2776
2777         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2778
2779         dev->trans_start = jiffies;
2780
2781         dev->stats.tx_errors++;
2782
2783         netif_tx_wake_all_queues(dev);
2784 }
2785
2786 #define MAX_MC_COUNT    16
2787
2788 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2789                                          unsigned char *addr,
2790                                          int *i,
2791                                          int *mc)
2792 {
2793         u32 reg;
2794
2795         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2796                              UMAC_MDF_ADDR + (*i * 4));
2797         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2798                              addr[4] << 8 | addr[5],
2799                              UMAC_MDF_ADDR + ((*i + 1) * 4));
2800         reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2801         reg |= (1 << (MAX_MC_COUNT - *mc));
2802         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2803         *i += 2;
2804         (*mc)++;
2805 }
2806
2807 static void bcmgenet_set_rx_mode(struct net_device *dev)
2808 {
2809         struct bcmgenet_priv *priv = netdev_priv(dev);
2810         struct netdev_hw_addr *ha;
2811         int i, mc;
2812         u32 reg;
2813
2814         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2815
2816         /* Promiscuous mode */
2817         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2818         if (dev->flags & IFF_PROMISC) {
2819                 reg |= CMD_PROMISC;
2820                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2821                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2822                 return;
2823         } else {
2824                 reg &= ~CMD_PROMISC;
2825                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2826         }
2827
2828         /* UniMac doesn't support ALLMULTI */
2829         if (dev->flags & IFF_ALLMULTI) {
2830                 netdev_warn(dev, "ALLMULTI is not supported\n");
2831                 return;
2832         }
2833
2834         /* update MDF filter */
2835         i = 0;
2836         mc = 0;
2837         /* Broadcast */
2838         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2839         /* my own address.*/
2840         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2841         /* Unicast list*/
2842         if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2843                 return;
2844
2845         if (!netdev_uc_empty(dev))
2846                 netdev_for_each_uc_addr(ha, dev)
2847                         bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2848         /* Multicast */
2849         if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2850                 return;
2851
2852         netdev_for_each_mc_addr(ha, dev)
2853                 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2854 }
2855
2856 /* Set the hardware MAC address. */
2857 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2858 {
2859         struct sockaddr *addr = p;
2860
2861         /* Setting the MAC address at the hardware level is not possible
2862          * without disabling the UniMAC RX/TX enable bits.
2863          */
2864         if (netif_running(dev))
2865                 return -EBUSY;
2866
2867         ether_addr_copy(dev->dev_addr, addr->sa_data);
2868
2869         return 0;
2870 }
2871
2872 static const struct net_device_ops bcmgenet_netdev_ops = {
2873         .ndo_open               = bcmgenet_open,
2874         .ndo_stop               = bcmgenet_close,
2875         .ndo_start_xmit         = bcmgenet_xmit,
2876         .ndo_tx_timeout         = bcmgenet_timeout,
2877         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
2878         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
2879         .ndo_do_ioctl           = bcmgenet_ioctl,
2880         .ndo_set_features       = bcmgenet_set_features,
2881 };
2882
2883 /* Array of GENET hardware parameters/characteristics */
2884 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2885         [GENET_V1] = {
2886                 .tx_queues = 0,
2887                 .tx_bds_per_q = 0,
2888                 .rx_queues = 0,
2889                 .rx_bds_per_q = 0,
2890                 .bp_in_en_shift = 16,
2891                 .bp_in_mask = 0xffff,
2892                 .hfb_filter_cnt = 16,
2893                 .qtag_mask = 0x1F,
2894                 .hfb_offset = 0x1000,
2895                 .rdma_offset = 0x2000,
2896                 .tdma_offset = 0x3000,
2897                 .words_per_bd = 2,
2898         },
2899         [GENET_V2] = {
2900                 .tx_queues = 4,
2901                 .tx_bds_per_q = 32,
2902                 .rx_queues = 0,
2903                 .rx_bds_per_q = 0,
2904                 .bp_in_en_shift = 16,
2905                 .bp_in_mask = 0xffff,
2906                 .hfb_filter_cnt = 16,
2907                 .qtag_mask = 0x1F,
2908                 .tbuf_offset = 0x0600,
2909                 .hfb_offset = 0x1000,
2910                 .hfb_reg_offset = 0x2000,
2911                 .rdma_offset = 0x3000,
2912                 .tdma_offset = 0x4000,
2913                 .words_per_bd = 2,
2914                 .flags = GENET_HAS_EXT,
2915         },
2916         [GENET_V3] = {
2917                 .tx_queues = 4,
2918                 .tx_bds_per_q = 32,
2919                 .rx_queues = 0,
2920                 .rx_bds_per_q = 0,
2921                 .bp_in_en_shift = 17,
2922                 .bp_in_mask = 0x1ffff,
2923                 .hfb_filter_cnt = 48,
2924                 .hfb_filter_size = 128,
2925                 .qtag_mask = 0x3F,
2926                 .tbuf_offset = 0x0600,
2927                 .hfb_offset = 0x8000,
2928                 .hfb_reg_offset = 0xfc00,
2929                 .rdma_offset = 0x10000,
2930                 .tdma_offset = 0x11000,
2931                 .words_per_bd = 2,
2932                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
2933                          GENET_HAS_MOCA_LINK_DET,
2934         },
2935         [GENET_V4] = {
2936                 .tx_queues = 4,
2937                 .tx_bds_per_q = 32,
2938                 .rx_queues = 0,
2939                 .rx_bds_per_q = 0,
2940                 .bp_in_en_shift = 17,
2941                 .bp_in_mask = 0x1ffff,
2942                 .hfb_filter_cnt = 48,
2943                 .hfb_filter_size = 128,
2944                 .qtag_mask = 0x3F,
2945                 .tbuf_offset = 0x0600,
2946                 .hfb_offset = 0x8000,
2947                 .hfb_reg_offset = 0xfc00,
2948                 .rdma_offset = 0x2000,
2949                 .tdma_offset = 0x4000,
2950                 .words_per_bd = 3,
2951                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
2952                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
2953         },
2954 };
2955
2956 /* Infer hardware parameters from the detected GENET version */
2957 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2958 {
2959         struct bcmgenet_hw_params *params;
2960         u32 reg;
2961         u8 major;
2962         u16 gphy_rev;
2963
2964         if (GENET_IS_V4(priv)) {
2965                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2966                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2967                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2968                 priv->version = GENET_V4;
2969         } else if (GENET_IS_V3(priv)) {
2970                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2971                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2972                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2973                 priv->version = GENET_V3;
2974         } else if (GENET_IS_V2(priv)) {
2975                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2976                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2977                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2978                 priv->version = GENET_V2;
2979         } else if (GENET_IS_V1(priv)) {
2980                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2981                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2982                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2983                 priv->version = GENET_V1;
2984         }
2985
2986         /* enum genet_version starts at 1 */
2987         priv->hw_params = &bcmgenet_hw_params[priv->version];
2988         params = priv->hw_params;
2989
2990         /* Read GENET HW version */
2991         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2992         major = (reg >> 24 & 0x0f);
2993         if (major == 5)
2994                 major = 4;
2995         else if (major == 0)
2996                 major = 1;
2997         if (major != priv->version) {
2998                 dev_err(&priv->pdev->dev,
2999                         "GENET version mismatch, got: %d, configured for: %d\n",
3000                         major, priv->version);
3001         }
3002
3003         /* Print the GENET core version */
3004         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3005                  major, (reg >> 16) & 0x0f, reg & 0xffff);
3006
3007         /* Store the integrated PHY revision for the MDIO probing function
3008          * to pass this information to the PHY driver. The PHY driver expects
3009          * to find the PHY major revision in bits 15:8 while the GENET register
3010          * stores that information in bits 7:0, account for that.
3011          *
3012          * On newer chips, starting with PHY revision G0, a new scheme is
3013          * deployed similar to the Starfighter 2 switch with GPHY major
3014          * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3015          * is reserved as well as special value 0x01ff, we have a small
3016          * heuristic to check for the new GPHY revision and re-arrange things
3017          * so the GPHY driver is happy.
3018          */
3019         gphy_rev = reg & 0xffff;
3020
3021         /* This is the good old scheme, just GPHY major, no minor nor patch */
3022         if ((gphy_rev & 0xf0) != 0)
3023                 priv->gphy_rev = gphy_rev << 8;
3024
3025         /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3026         else if ((gphy_rev & 0xff00) != 0)
3027                 priv->gphy_rev = gphy_rev;
3028
3029         /* This is reserved so should require special treatment */
3030         else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3031                 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3032                 return;
3033         }
3034
3035 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3036         if (!(params->flags & GENET_HAS_40BITS))
3037                 pr_warn("GENET does not support 40-bits PA\n");
3038 #endif
3039
3040         pr_debug("Configuration for version: %d\n"
3041                 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3042                 "BP << en: %2d, BP msk: 0x%05x\n"
3043                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3044                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3045                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3046                 "Words/BD: %d\n",
3047                 priv->version,
3048                 params->tx_queues, params->tx_bds_per_q,
3049                 params->rx_queues, params->rx_bds_per_q,
3050                 params->bp_in_en_shift, params->bp_in_mask,
3051                 params->hfb_filter_cnt, params->qtag_mask,
3052                 params->tbuf_offset, params->hfb_offset,
3053                 params->hfb_reg_offset,
3054                 params->rdma_offset, params->tdma_offset,
3055                 params->words_per_bd);
3056 }
3057
3058 static const struct of_device_id bcmgenet_match[] = {
3059         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3060         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3061         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3062         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3063         { },
3064 };
3065
3066 static int bcmgenet_probe(struct platform_device *pdev)
3067 {
3068         struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3069         struct device_node *dn = pdev->dev.of_node;
3070         const struct of_device_id *of_id = NULL;
3071         struct bcmgenet_priv *priv;
3072         struct net_device *dev;
3073         const void *macaddr;
3074         struct resource *r;
3075         int err = -EIO;
3076
3077         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3078         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3079                                  GENET_MAX_MQ_CNT + 1);
3080         if (!dev) {
3081                 dev_err(&pdev->dev, "can't allocate net device\n");
3082                 return -ENOMEM;
3083         }
3084
3085         if (dn) {
3086                 of_id = of_match_node(bcmgenet_match, dn);
3087                 if (!of_id)
3088                         return -EINVAL;
3089         }
3090
3091         priv = netdev_priv(dev);
3092         priv->irq0 = platform_get_irq(pdev, 0);
3093         priv->irq1 = platform_get_irq(pdev, 1);
3094         priv->wol_irq = platform_get_irq(pdev, 2);
3095         if (!priv->irq0 || !priv->irq1) {
3096                 dev_err(&pdev->dev, "can't find IRQs\n");
3097                 err = -EINVAL;
3098                 goto err;
3099         }
3100
3101         if (dn) {
3102                 macaddr = of_get_mac_address(dn);
3103                 if (!macaddr) {
3104                         dev_err(&pdev->dev, "can't find MAC address\n");
3105                         err = -EINVAL;
3106                         goto err;
3107                 }
3108         } else {
3109                 macaddr = pd->mac_address;
3110         }
3111
3112         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3113         priv->base = devm_ioremap_resource(&pdev->dev, r);
3114         if (IS_ERR(priv->base)) {
3115                 err = PTR_ERR(priv->base);
3116                 goto err;
3117         }
3118
3119         SET_NETDEV_DEV(dev, &pdev->dev);
3120         dev_set_drvdata(&pdev->dev, dev);
3121         ether_addr_copy(dev->dev_addr, macaddr);
3122         dev->watchdog_timeo = 2 * HZ;
3123         dev->ethtool_ops = &bcmgenet_ethtool_ops;
3124         dev->netdev_ops = &bcmgenet_netdev_ops;
3125
3126         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3127
3128         /* Set hardware features */
3129         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3130                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3131
3132         /* Request the WOL interrupt and advertise suspend if available */
3133         priv->wol_irq_disabled = true;
3134         err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3135                                dev->name, priv);
3136         if (!err)
3137                 device_set_wakeup_capable(&pdev->dev, 1);
3138
3139         /* Set the needed headroom to account for any possible
3140          * features enabling/disabling at runtime
3141          */
3142         dev->needed_headroom += 64;
3143
3144         netdev_boot_setup_check(dev);
3145
3146         priv->dev = dev;
3147         priv->pdev = pdev;
3148         if (of_id)
3149                 priv->version = (enum bcmgenet_version)of_id->data;
3150         else
3151                 priv->version = pd->genet_version;
3152
3153         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3154         if (IS_ERR(priv->clk))
3155                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3156
3157         if (!IS_ERR(priv->clk))
3158                 clk_prepare_enable(priv->clk);
3159
3160         bcmgenet_set_hw_params(priv);
3161
3162         /* Mii wait queue */
3163         init_waitqueue_head(&priv->wq);
3164         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3165         priv->rx_buf_len = RX_BUF_LENGTH;
3166         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3167
3168         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3169         if (IS_ERR(priv->clk_wol))
3170                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3171
3172         priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3173         if (IS_ERR(priv->clk_eee)) {
3174                 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3175                 priv->clk_eee = NULL;
3176         }
3177
3178         err = reset_umac(priv);
3179         if (err)
3180                 goto err_clk_disable;
3181
3182         err = bcmgenet_mii_init(dev);
3183         if (err)
3184                 goto err_clk_disable;
3185
3186         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
3187          * just the ring 16 descriptor based TX
3188          */
3189         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3190         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3191
3192         /* libphy will determine the link state */
3193         netif_carrier_off(dev);
3194
3195         /* Turn off the main clock, WOL clock is handled separately */
3196         if (!IS_ERR(priv->clk))
3197                 clk_disable_unprepare(priv->clk);
3198
3199         err = register_netdev(dev);
3200         if (err)
3201                 goto err;
3202
3203         return err;
3204
3205 err_clk_disable:
3206         if (!IS_ERR(priv->clk))
3207                 clk_disable_unprepare(priv->clk);
3208 err:
3209         free_netdev(dev);
3210         return err;
3211 }
3212
3213 static int bcmgenet_remove(struct platform_device *pdev)
3214 {
3215         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3216
3217         dev_set_drvdata(&pdev->dev, NULL);
3218         unregister_netdev(priv->dev);
3219         bcmgenet_mii_exit(priv->dev);
3220         free_netdev(priv->dev);
3221
3222         return 0;
3223 }
3224
3225 #ifdef CONFIG_PM_SLEEP
3226 static int bcmgenet_suspend(struct device *d)
3227 {
3228         struct net_device *dev = dev_get_drvdata(d);
3229         struct bcmgenet_priv *priv = netdev_priv(dev);
3230         int ret;
3231
3232         if (!netif_running(dev))
3233                 return 0;
3234
3235         bcmgenet_netif_stop(dev);
3236
3237         phy_suspend(priv->phydev);
3238
3239         netif_device_detach(dev);
3240
3241         /* Disable MAC receive */
3242         umac_enable_set(priv, CMD_RX_EN, false);
3243
3244         ret = bcmgenet_dma_teardown(priv);
3245         if (ret)
3246                 return ret;
3247
3248         /* Disable MAC transmit. TX DMA disabled have to done before this */
3249         umac_enable_set(priv, CMD_TX_EN, false);
3250
3251         /* tx reclaim */
3252         bcmgenet_tx_reclaim_all(dev);
3253         bcmgenet_fini_dma(priv);
3254
3255         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3256         if (device_may_wakeup(d) && priv->wolopts) {
3257                 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3258                 clk_prepare_enable(priv->clk_wol);
3259         } else if (phy_is_internal(priv->phydev)) {
3260                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3261         }
3262
3263         /* Turn off the clocks */
3264         clk_disable_unprepare(priv->clk);
3265
3266         return ret;
3267 }
3268
3269 static int bcmgenet_resume(struct device *d)
3270 {
3271         struct net_device *dev = dev_get_drvdata(d);
3272         struct bcmgenet_priv *priv = netdev_priv(dev);
3273         unsigned long dma_ctrl;
3274         int ret;
3275         u32 reg;
3276
3277         if (!netif_running(dev))
3278                 return 0;
3279
3280         /* Turn on the clock */
3281         ret = clk_prepare_enable(priv->clk);
3282         if (ret)
3283                 return ret;
3284
3285         /* If this is an internal GPHY, power it back on now, before UniMAC is
3286          * brought out of reset as absolutely no UniMAC activity is allowed
3287          */
3288         if (phy_is_internal(priv->phydev))
3289                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3290
3291         bcmgenet_umac_reset(priv);
3292
3293         ret = init_umac(priv);
3294         if (ret)
3295                 goto out_clk_disable;
3296
3297         /* From WOL-enabled suspend, switch to regular clock */
3298         if (priv->wolopts)
3299                 clk_disable_unprepare(priv->clk_wol);
3300
3301         phy_init_hw(priv->phydev);
3302         /* Speed settings must be restored */
3303         bcmgenet_mii_config(priv->dev, false);
3304
3305         /* disable ethernet MAC while updating its registers */
3306         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3307
3308         bcmgenet_set_hw_addr(priv, dev->dev_addr);
3309
3310         if (phy_is_internal(priv->phydev)) {
3311                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3312                 reg |= EXT_ENERGY_DET_MASK;
3313                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3314         }
3315
3316         if (priv->wolopts)
3317                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3318
3319         /* Disable RX/TX DMA and flush TX queues */
3320         dma_ctrl = bcmgenet_dma_disable(priv);
3321
3322         /* Reinitialize TDMA and RDMA and SW housekeeping */
3323         ret = bcmgenet_init_dma(priv);
3324         if (ret) {
3325                 netdev_err(dev, "failed to initialize DMA\n");
3326                 goto out_clk_disable;
3327         }
3328
3329         /* Always enable ring 16 - descriptor ring */
3330         bcmgenet_enable_dma(priv, dma_ctrl);
3331
3332         netif_device_attach(dev);
3333
3334         phy_resume(priv->phydev);
3335
3336         if (priv->eee.eee_enabled)
3337                 bcmgenet_eee_enable_set(dev, true);
3338
3339         bcmgenet_netif_start(dev);
3340
3341         return 0;
3342
3343 out_clk_disable:
3344         clk_disable_unprepare(priv->clk);
3345         return ret;
3346 }
3347 #endif /* CONFIG_PM_SLEEP */
3348
3349 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3350
3351 static struct platform_driver bcmgenet_driver = {
3352         .probe  = bcmgenet_probe,
3353         .remove = bcmgenet_remove,
3354         .driver = {
3355                 .name   = "bcmgenet",
3356                 .of_match_table = bcmgenet_match,
3357                 .pm     = &bcmgenet_pm_ops,
3358         },
3359 };
3360 module_platform_driver(bcmgenet_driver);
3361
3362 MODULE_AUTHOR("Broadcom Corporation");
3363 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3364 MODULE_ALIAS("platform:bcmgenet");
3365 MODULE_LICENSE("GPL");