kernel/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c

   1 /* bnx2x_sp.c: Qlogic Everest network driver.
   2  *
   3  * Copyright 2011-2013 Broadcom Corporation
   4  * Copyright (c) 2014 QLogic Corporation
   5  * All rights reserved
   6  *
   7  * Unless you and Qlogic execute a separate written software license
   8  * agreement governing use of this software, this software is licensed to you
   9  * under the terms of the GNU General Public License version 2, available
  10  * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
  11  *
  12  * Notwithstanding the above, under no circumstances may you combine this
  13  * software in any way with any other Qlogic software provided under a
  14  * license other than the GPL, without Qlogic's express prior written
  15  * consent.
  16  *
  17  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  18  * Written by: Vladislav Zolotarov
  19  *
  20  */
  21
  22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  23
  24 #include <linux/module.h>
  25 #include <linux/crc32.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/crc32c.h>
  29 #include "bnx2x.h"
  30 #include "bnx2x_cmn.h"
  31 #include "bnx2x_sp.h"
  32
  33 #define BNX2X_MAX_EMUL_MULTI            16
  34
  35 /**** Exe Queue interfaces ****/
  36
  37 /**
  38  * bnx2x_exe_queue_init - init the Exe Queue object
  39  *
  40  * @o:          pointer to the object
  41  * @exe_len:    length
  42  * @owner:      pointer to the owner
  43  * @validate:   validate function pointer
  44  * @optimize:   optimize function pointer
  45  * @exec:       execute function pointer
  46  * @get:        get function pointer
  47  */
  48 static inline void bnx2x_exe_queue_init(struct bnx2x *bp,
  49                                         struct bnx2x_exe_queue_obj *o,
  50                                         int exe_len,
  51                                         union bnx2x_qable_obj *owner,
  52                                         exe_q_validate validate,
  53                                         exe_q_remove remove,
  54                                         exe_q_optimize optimize,
  55                                         exe_q_execute exec,
  56                                         exe_q_get get)
  57 {
  58         memset(o, 0, sizeof(*o));
  59
  60         INIT_LIST_HEAD(&o->exe_queue);
  61         INIT_LIST_HEAD(&o->pending_comp);
  62
  63         spin_lock_init(&o->lock);
  64
  65         o->exe_chunk_len = exe_len;
  66         o->owner         = owner;
  67
  68         /* Owner specific callbacks */
  69         o->validate      = validate;
  70         o->remove        = remove;
  71         o->optimize      = optimize;
  72         o->execute       = exec;
  73         o->get           = get;
  74
  75         DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n",
  76            exe_len);
  77 }
  78
  79 static inline void bnx2x_exe_queue_free_elem(struct bnx2x *bp,
  80                                              struct bnx2x_exeq_elem *elem)
  81 {
  82         DP(BNX2X_MSG_SP, "Deleting an exe_queue element\n");
  83         kfree(elem);
  84 }
  85
  86 static inline int bnx2x_exe_queue_length(struct bnx2x_exe_queue_obj *o)
  87 {
  88         struct bnx2x_exeq_elem *elem;
  89         int cnt = 0;
  90
  91         spin_lock_bh(&o->lock);
  92
  93         list_for_each_entry(elem, &o->exe_queue, link)
  94                 cnt++;
  95
  96         spin_unlock_bh(&o->lock);
  97
  98         return cnt;
  99 }
 100
 101 /**
 102  * bnx2x_exe_queue_add - add a new element to the execution queue
 103  *
 104  * @bp:         driver handle
 105  * @o:          queue
 106  * @cmd:        new command to add
 107  * @restore:    true - do not optimize the command
 108  *
 109  * If the element is optimized or is illegal, frees it.
 110  */
 111 static inline int bnx2x_exe_queue_add(struct bnx2x *bp,
 112                                       struct bnx2x_exe_queue_obj *o,
 113                                       struct bnx2x_exeq_elem *elem,
 114                                       bool restore)
 115 {
 116         int rc;
 117
 118         spin_lock_bh(&o->lock);
 119
 120         if (!restore) {
 121                 /* Try to cancel this element queue */
 122                 rc = o->optimize(bp, o->owner, elem);
 123                 if (rc)
 124                         goto free_and_exit;
 125
 126                 /* Check if this request is ok */
 127                 rc = o->validate(bp, o->owner, elem);
 128                 if (rc) {
 129                         DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc);
 130                         goto free_and_exit;
 131                 }
 132         }
 133
 134         /* If so, add it to the execution queue */
 135         list_add_tail(&elem->link, &o->exe_queue);
 136
 137         spin_unlock_bh(&o->lock);
 138
 139         return 0;
 140
 141 free_and_exit:
 142         bnx2x_exe_queue_free_elem(bp, elem);
 143
 144         spin_unlock_bh(&o->lock);
 145
 146         return rc;
 147 }
 148
 149 static inline void __bnx2x_exe_queue_reset_pending(
 150         struct bnx2x *bp,
 151         struct bnx2x_exe_queue_obj *o)
 152 {
 153         struct bnx2x_exeq_elem *elem;
 154
 155         while (!list_empty(&o->pending_comp)) {
 156                 elem = list_first_entry(&o->pending_comp,
 157                                         struct bnx2x_exeq_elem, link);
 158
 159                 list_del(&elem->link);
 160                 bnx2x_exe_queue_free_elem(bp, elem);
 161         }
 162 }
 163
 164 /**
 165  * bnx2x_exe_queue_step - execute one execution chunk atomically
 166  *
 167  * @bp:                 driver handle
 168  * @o:                  queue
 169  * @ramrod_flags:       flags
 170  *
 171  * (Should be called while holding the exe_queue->lock).
 172  */
 173 static inline int bnx2x_exe_queue_step(struct bnx2x *bp,
 174                                        struct bnx2x_exe_queue_obj *o,
 175                                        unsigned long *ramrod_flags)
 176 {
 177         struct bnx2x_exeq_elem *elem, spacer;
 178         int cur_len = 0, rc;
 179
 180         memset(&spacer, 0, sizeof(spacer));
 181
 182         /* Next step should not be performed until the current is finished,
 183          * unless a DRV_CLEAR_ONLY bit is set. In this case we just want to
 184          * properly clear object internals without sending any command to the FW
 185          * which also implies there won't be any completion to clear the
 186          * 'pending' list.
 187          */
 188         if (!list_empty(&o->pending_comp)) {
 189                 if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {
 190                         DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n");
 191                         __bnx2x_exe_queue_reset_pending(bp, o);
 192                 } else {
 193                         return 1;
 194                 }
 195         }
 196
 197         /* Run through the pending commands list and create a next
 198          * execution chunk.
 199          */
 200         while (!list_empty(&o->exe_queue)) {
 201                 elem = list_first_entry(&o->exe_queue, struct bnx2x_exeq_elem,
 202                                         link);
 203                 WARN_ON(!elem->cmd_len);
 204
 205                 if (cur_len + elem->cmd_len <= o->exe_chunk_len) {
 206                         cur_len += elem->cmd_len;
 207                         /* Prevent from both lists being empty when moving an
 208                          * element. This will allow the call of
 209                          * bnx2x_exe_queue_empty() without locking.
 210                          */
 211                         list_add_tail(&spacer.link, &o->pending_comp);
 212                         mb();
 213                         list_move_tail(&elem->link, &o->pending_comp);
 214                         list_del(&spacer.link);
 215                 } else
 216                         break;
 217         }
 218
 219         /* Sanity check */
 220         if (!cur_len)
 221                 return 0;
 222
 223         rc = o->execute(bp, o->owner, &o->pending_comp, ramrod_flags);
 224         if (rc < 0)
 225                 /* In case of an error return the commands back to the queue
 226                  * and reset the pending_comp.
 227                  */
 228                 list_splice_init(&o->pending_comp, &o->exe_queue);
 229         else if (!rc)
 230                 /* If zero is returned, means there are no outstanding pending
 231                  * completions and we may dismiss the pending list.
 232                  */
 233                 __bnx2x_exe_queue_reset_pending(bp, o);
 234
 235         return rc;
 236 }
 237
 238 static inline bool bnx2x_exe_queue_empty(struct bnx2x_exe_queue_obj *o)
 239 {
 240         bool empty = list_empty(&o->exe_queue);
 241
 242         /* Don't reorder!!! */
 243         mb();
 244
 245         return empty && list_empty(&o->pending_comp);
 246 }
 247
 248 static inline struct bnx2x_exeq_elem *bnx2x_exe_queue_alloc_elem(
 249         struct bnx2x *bp)
 250 {
 251         DP(BNX2X_MSG_SP, "Allocating a new exe_queue element\n");
 252         return kzalloc(sizeof(struct bnx2x_exeq_elem), GFP_ATOMIC);
 253 }
 254
 255 /************************ raw_obj functions ***********************************/
 256 static bool bnx2x_raw_check_pending(struct bnx2x_raw_obj *o)
 257 {
 258         return !!test_bit(o->state, o->pstate);
 259 }
 260
 261 static void bnx2x_raw_clear_pending(struct bnx2x_raw_obj *o)
 262 {
 263         smp_mb__before_atomic();
 264         clear_bit(o->state, o->pstate);
 265         smp_mb__after_atomic();
 266 }
 267
 268 static void bnx2x_raw_set_pending(struct bnx2x_raw_obj *o)
 269 {
 270         smp_mb__before_atomic();
 271         set_bit(o->state, o->pstate);
 272         smp_mb__after_atomic();
 273 }
 274
 275 /**
 276  * bnx2x_state_wait - wait until the given bit(state) is cleared
 277  *
 278  * @bp:         device handle
 279  * @state:      state which is to be cleared
 280  * @state_p:    state buffer
 281  *
 282  */
 283 static inline int bnx2x_state_wait(struct bnx2x *bp, int state,
 284                                    unsigned long *pstate)
 285 {
 286         /* can take a while if any port is running */
 287         int cnt = 5000;
 288
 289         if (CHIP_REV_IS_EMUL(bp))
 290                 cnt *= 20;
 291
 292         DP(BNX2X_MSG_SP, "waiting for state to become %d\n", state);
 293
 294         might_sleep();
 295         while (cnt--) {
 296                 if (!test_bit(state, pstate)) {
 297 #ifdef BNX2X_STOP_ON_ERROR
 298                         DP(BNX2X_MSG_SP, "exit  (cnt %d)\n", 5000 - cnt);
 299 #endif
 300                         return 0;
 301                 }
 302
 303                 usleep_range(1000, 2000);
 304
 305                 if (bp->panic)
 306                         return -EIO;
 307         }
 308
 309         /* timeout! */
 310         BNX2X_ERR("timeout waiting for state %d\n", state);
 311 #ifdef BNX2X_STOP_ON_ERROR
 312         bnx2x_panic();
 313 #endif
 314
 315         return -EBUSY;
 316 }
 317
 318 static int bnx2x_raw_wait(struct bnx2x *bp, struct bnx2x_raw_obj *raw)
 319 {
 320         return bnx2x_state_wait(bp, raw->state, raw->pstate);
 321 }
 322
 323 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
 324 /* credit handling callbacks */
 325 static bool bnx2x_get_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int *offset)
 326 {
 327         struct bnx2x_credit_pool_obj *mp = o->macs_pool;
 328
 329         WARN_ON(!mp);
 330
 331         return mp->get_entry(mp, offset);
 332 }
 333
 334 static bool bnx2x_get_credit_mac(struct bnx2x_vlan_mac_obj *o)
 335 {
 336         struct bnx2x_credit_pool_obj *mp = o->macs_pool;
 337
 338         WARN_ON(!mp);
 339
 340         return mp->get(mp, 1);
 341 }
 342
 343 static bool bnx2x_get_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int *offset)
 344 {
 345         struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
 346
 347         WARN_ON(!vp);
 348
 349         return vp->get_entry(vp, offset);
 350 }
 351
 352 static bool bnx2x_get_credit_vlan(struct bnx2x_vlan_mac_obj *o)
 353 {
 354         struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
 355
 356         WARN_ON(!vp);
 357
 358         return vp->get(vp, 1);
 359 }
 360
 361 static bool bnx2x_get_credit_vlan_mac(struct bnx2x_vlan_mac_obj *o)
 362 {
 363         struct bnx2x_credit_pool_obj *mp = o->macs_pool;
 364         struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
 365
 366         if (!mp->get(mp, 1))
 367                 return false;
 368
 369         if (!vp->get(vp, 1)) {
 370                 mp->put(mp, 1);
 371                 return false;
 372         }
 373
 374         return true;
 375 }
 376
 377 static bool bnx2x_put_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int offset)
 378 {
 379         struct bnx2x_credit_pool_obj *mp = o->macs_pool;
 380
 381         return mp->put_entry(mp, offset);
 382 }
 383
 384 static bool bnx2x_put_credit_mac(struct bnx2x_vlan_mac_obj *o)
 385 {
 386         struct bnx2x_credit_pool_obj *mp = o->macs_pool;
 387
 388         return mp->put(mp, 1);
 389 }
 390
 391 static bool bnx2x_put_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int offset)
 392 {
 393         struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
 394
 395         return vp->put_entry(vp, offset);
 396 }
 397
 398 static bool bnx2x_put_credit_vlan(struct bnx2x_vlan_mac_obj *o)
 399 {
 400         struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
 401
 402         return vp->put(vp, 1);
 403 }
 404
 405 static bool bnx2x_put_credit_vlan_mac(struct bnx2x_vlan_mac_obj *o)
 406 {
 407         struct bnx2x_credit_pool_obj *mp = o->macs_pool;
 408         struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
 409
 410         if (!mp->put(mp, 1))
 411                 return false;
 412
 413         if (!vp->put(vp, 1)) {
 414                 mp->get(mp, 1);
 415                 return false;
 416         }
 417
 418         return true;
 419 }
 420
 421 /**
 422  * __bnx2x_vlan_mac_h_write_trylock - try getting the vlan mac writer lock
 423  *
 424  * @bp:         device handle
 425  * @o:          vlan_mac object
 426  *
 427  * @details: Non-blocking implementation; should be called under execution
 428  *           queue lock.
 429  */
 430 static int __bnx2x_vlan_mac_h_write_trylock(struct bnx2x *bp,
 431                                             struct bnx2x_vlan_mac_obj *o)
 432 {
 433         if (o->head_reader) {
 434                 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - There are readers; Busy\n");
 435                 return -EBUSY;
 436         }
 437
 438         DP(BNX2X_MSG_SP, "vlan_mac_lock writer - Taken\n");
 439         return 0;
 440 }
 441
 442 /**
 443  * __bnx2x_vlan_mac_h_exec_pending - execute step instead of a previous step
 444  *
 445  * @bp:         device handle
 446  * @o:          vlan_mac object
 447  *
 448  * @details Should be called under execution queue lock; notice it might release
 449  *          and reclaim it during its run.
 450  */
 451 static void __bnx2x_vlan_mac_h_exec_pending(struct bnx2x *bp,
 452                                             struct bnx2x_vlan_mac_obj *o)
 453 {
 454         int rc;
 455         unsigned long ramrod_flags = o->saved_ramrod_flags;
 456
 457         DP(BNX2X_MSG_SP, "vlan_mac_lock execute pending command with ramrod flags %lu\n",
 458            ramrod_flags);
 459         o->head_exe_request = false;
 460         o->saved_ramrod_flags = 0;
 461         rc = bnx2x_exe_queue_step(bp, &o->exe_queue, &ramrod_flags);
 462         if ((rc != 0) && (rc != 1)) {
 463                 BNX2X_ERR("execution of pending commands failed with rc %d\n",
 464                           rc);
 465 #ifdef BNX2X_STOP_ON_ERROR
 466                 bnx2x_panic();
 467 #endif
 468         }
 469 }
 470
 471 /**
 472  * __bnx2x_vlan_mac_h_pend - Pend an execution step which couldn't run
 473  *
 474  * @bp:                 device handle
 475  * @o:                  vlan_mac object
 476  * @ramrod_flags:       ramrod flags of missed execution
 477  *
 478  * @details Should be called under execution queue lock.
 479  */
 480 static void __bnx2x_vlan_mac_h_pend(struct bnx2x *bp,
 481                                     struct bnx2x_vlan_mac_obj *o,
 482                                     unsigned long ramrod_flags)
 483 {
 484         o->head_exe_request = true;
 485         o->saved_ramrod_flags = ramrod_flags;
 486         DP(BNX2X_MSG_SP, "Placing pending execution with ramrod flags %lu\n",
 487            ramrod_flags);
 488 }
 489
 490 /**
 491  * __bnx2x_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock
 492  *
 493  * @bp:                 device handle
 494  * @o:                  vlan_mac object
 495  *
 496  * @details Should be called under execution queue lock. Notice if a pending
 497  *          execution exists, it would perform it - possibly releasing and
 498  *          reclaiming the execution queue lock.
 499  */
 500 static void __bnx2x_vlan_mac_h_write_unlock(struct bnx2x *bp,
 501                                             struct bnx2x_vlan_mac_obj *o)
 502 {
 503         /* It's possible a new pending execution was added since this writer
 504          * executed. If so, execute again. [Ad infinitum]
 505          */
 506         while (o->head_exe_request) {
 507                 DP(BNX2X_MSG_SP, "vlan_mac_lock - writer release encountered a pending request\n");
 508                 __bnx2x_vlan_mac_h_exec_pending(bp, o);
 509         }
 510 }
 511
 512
 513 /**
 514  * __bnx2x_vlan_mac_h_read_lock - lock the vlan mac head list reader lock
 515  *
 516  * @bp:                 device handle
 517  * @o:                  vlan_mac object
 518  *
 519  * @details Should be called under the execution queue lock. May sleep. May
 520  *          release and reclaim execution queue lock during its run.
 521  */
 522 static int __bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp,
 523                                         struct bnx2x_vlan_mac_obj *o)
 524 {
 525         /* If we got here, we're holding lock --> no WRITER exists */
 526         o->head_reader++;
 527         DP(BNX2X_MSG_SP, "vlan_mac_lock - locked reader - number %d\n",
 528            o->head_reader);
 529
 530         return 0;
 531 }
 532
 533 /**
 534  * bnx2x_vlan_mac_h_read_lock - lock the vlan mac head list reader lock
 535  *
 536  * @bp:                 device handle
 537  * @o:                  vlan_mac object
 538  *
 539  * @details May sleep. Claims and releases execution queue lock during its run.
 540  */
 541 int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp,
 542                                struct bnx2x_vlan_mac_obj *o)
 543 {
 544         int rc;
 545
 546         spin_lock_bh(&o->exe_queue.lock);
 547         rc = __bnx2x_vlan_mac_h_read_lock(bp, o);
 548         spin_unlock_bh(&o->exe_queue.lock);
 549
 550         return rc;
 551 }
 552
 553 /**
 554  * __bnx2x_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock
 555  *
 556  * @bp:                 device handle
 557  * @o:                  vlan_mac object
 558  *
 559  * @details Should be called under execution queue lock. Notice if a pending
 560  *          execution exists, it would be performed if this was the last
 561  *          reader. possibly releasing and reclaiming the execution queue lock.
 562  */
 563 static void __bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp,
 564                                           struct bnx2x_vlan_mac_obj *o)
 565 {
 566         if (!o->head_reader) {
 567                 BNX2X_ERR("Need to release vlan mac reader lock, but lock isn't taken\n");
 568 #ifdef BNX2X_STOP_ON_ERROR
 569                 bnx2x_panic();
 570 #endif
 571         } else {
 572                 o->head_reader--;
 573                 DP(BNX2X_MSG_SP, "vlan_mac_lock - decreased readers to %d\n",
 574                    o->head_reader);
 575         }
 576
 577         /* It's possible a new pending execution was added, and that this reader
 578          * was last - if so we need to execute the command.
 579          */
 580         if (!o->head_reader && o->head_exe_request) {
 581                 DP(BNX2X_MSG_SP, "vlan_mac_lock - reader release encountered a pending request\n");
 582
 583                 /* Writer release will do the trick */
 584                 __bnx2x_vlan_mac_h_write_unlock(bp, o);
 585         }
 586 }
 587
 588 /**
 589  * bnx2x_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock
 590  *
 591  * @bp:                 device handle
 592  * @o:                  vlan_mac object
 593  *
 594  * @details Notice if a pending execution exists, it would be performed if this
 595  *          was the last reader. Claims and releases the execution queue lock
 596  *          during its run.
 597  */
 598 void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp,
 599                                   struct bnx2x_vlan_mac_obj *o)
 600 {
 601         spin_lock_bh(&o->exe_queue.lock);
 602         __bnx2x_vlan_mac_h_read_unlock(bp, o);
 603         spin_unlock_bh(&o->exe_queue.lock);
 604 }
 605
 606 static int bnx2x_get_n_elements(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
 607                                 int n, u8 *base, u8 stride, u8 size)
 608 {
 609         struct bnx2x_vlan_mac_registry_elem *pos;
 610         u8 *next = base;
 611         int counter = 0;
 612         int read_lock;
 613
 614         DP(BNX2X_MSG_SP, "get_n_elements - taking vlan_mac_lock (reader)\n");
 615         read_lock = bnx2x_vlan_mac_h_read_lock(bp, o);
 616         if (read_lock != 0)
 617                 BNX2X_ERR("get_n_elements failed to get vlan mac reader lock; Access without lock\n");
 618
 619         /* traverse list */
 620         list_for_each_entry(pos, &o->head, link) {
 621                 if (counter < n) {
 622                         memcpy(next, &pos->u, size);
 623                         counter++;
 624                         DP(BNX2X_MSG_SP, "copied element number %d to address %p element was:\n",
 625                            counter, next);
 626                         next += stride + size;
 627                 }
 628         }
 629
 630         if (read_lock == 0) {
 631                 DP(BNX2X_MSG_SP, "get_n_elements - releasing vlan_mac_lock (reader)\n");
 632                 bnx2x_vlan_mac_h_read_unlock(bp, o);
 633         }
 634
 635         return counter * ETH_ALEN;
 636 }
 637
 638 /* check_add() callbacks */
 639 static int bnx2x_check_mac_add(struct bnx2x *bp,
 640                                struct bnx2x_vlan_mac_obj *o,
 641                                union bnx2x_classification_ramrod_data *data)
 642 {
 643         struct bnx2x_vlan_mac_registry_elem *pos;
 644
 645         DP(BNX2X_MSG_SP, "Checking MAC %pM for ADD command\n", data->mac.mac);
 646
 647         if (!is_valid_ether_addr(data->mac.mac))
 648                 return -EINVAL;
 649
 650         /* Check if a requested MAC already exists */
 651         list_for_each_entry(pos, &o->head, link)
 652                 if (ether_addr_equal(data->mac.mac, pos->u.mac.mac) &&
 653                     (data->mac.is_inner_mac == pos->u.mac.is_inner_mac))
 654                         return -EEXIST;
 655
 656         return 0;
 657 }
 658
 659 static int bnx2x_check_vlan_add(struct bnx2x *bp,
 660                                 struct bnx2x_vlan_mac_obj *o,
 661                                 union bnx2x_classification_ramrod_data *data)
 662 {
 663         struct bnx2x_vlan_mac_registry_elem *pos;
 664
 665         DP(BNX2X_MSG_SP, "Checking VLAN %d for ADD command\n", data->vlan.vlan);
 666
 667         list_for_each_entry(pos, &o->head, link)
 668                 if (data->vlan.vlan == pos->u.vlan.vlan)
 669                         return -EEXIST;
 670
 671         return 0;
 672 }
 673
 674 static int bnx2x_check_vlan_mac_add(struct bnx2x *bp,
 675                                     struct bnx2x_vlan_mac_obj *o,
 676                                    union bnx2x_classification_ramrod_data *data)
 677 {
 678         struct bnx2x_vlan_mac_registry_elem *pos;
 679
 680         DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for ADD command\n",
 681            data->vlan_mac.mac, data->vlan_mac.vlan);
 682
 683         list_for_each_entry(pos, &o->head, link)
 684                 if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) &&
 685                     (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac,
 686                                   ETH_ALEN)) &&
 687                     (data->vlan_mac.is_inner_mac ==
 688                      pos->u.vlan_mac.is_inner_mac))
 689                         return -EEXIST;
 690
 691         return 0;
 692 }
 693
 694 /* check_del() callbacks */
 695 static struct bnx2x_vlan_mac_registry_elem *
 696         bnx2x_check_mac_del(struct bnx2x *bp,
 697                             struct bnx2x_vlan_mac_obj *o,
 698                             union bnx2x_classification_ramrod_data *data)
 699 {
 700         struct bnx2x_vlan_mac_registry_elem *pos;
 701
 702         DP(BNX2X_MSG_SP, "Checking MAC %pM for DEL command\n", data->mac.mac);
 703
 704         list_for_each_entry(pos, &o->head, link)
 705                 if (ether_addr_equal(data->mac.mac, pos->u.mac.mac) &&
 706                     (data->mac.is_inner_mac == pos->u.mac.is_inner_mac))
 707                         return pos;
 708
 709         return NULL;
 710 }
 711
 712 static struct bnx2x_vlan_mac_registry_elem *
 713         bnx2x_check_vlan_del(struct bnx2x *bp,
 714                              struct bnx2x_vlan_mac_obj *o,
 715                              union bnx2x_classification_ramrod_data *data)
 716 {
 717         struct bnx2x_vlan_mac_registry_elem *pos;
 718
 719         DP(BNX2X_MSG_SP, "Checking VLAN %d for DEL command\n", data->vlan.vlan);
 720
 721         list_for_each_entry(pos, &o->head, link)
 722                 if (data->vlan.vlan == pos->u.vlan.vlan)
 723                         return pos;
 724
 725         return NULL;
 726 }
 727
 728 static struct bnx2x_vlan_mac_registry_elem *
 729         bnx2x_check_vlan_mac_del(struct bnx2x *bp,
 730                                  struct bnx2x_vlan_mac_obj *o,
 731                                  union bnx2x_classification_ramrod_data *data)
 732 {
 733         struct bnx2x_vlan_mac_registry_elem *pos;
 734
 735         DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for DEL command\n",
 736            data->vlan_mac.mac, data->vlan_mac.vlan);
 737
 738         list_for_each_entry(pos, &o->head, link)
 739                 if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) &&
 740                     (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac,
 741                              ETH_ALEN)) &&
 742                     (data->vlan_mac.is_inner_mac ==
 743                      pos->u.vlan_mac.is_inner_mac))
 744                         return pos;
 745
 746         return NULL;
 747 }
 748
 749 /* check_move() callback */
 750 static bool bnx2x_check_move(struct bnx2x *bp,
 751                              struct bnx2x_vlan_mac_obj *src_o,
 752                              struct bnx2x_vlan_mac_obj *dst_o,
 753                              union bnx2x_classification_ramrod_data *data)
 754 {
 755         struct bnx2x_vlan_mac_registry_elem *pos;
 756         int rc;
 757
 758         /* Check if we can delete the requested configuration from the first
 759          * object.
 760          */
 761         pos = src_o->check_del(bp, src_o, data);
 762
 763         /*  check if configuration can be added */
 764         rc = dst_o->check_add(bp, dst_o, data);
 765
 766         /* If this classification can not be added (is already set)
 767          * or can't be deleted - return an error.
 768          */
 769         if (rc || !pos)
 770                 return false;
 771
 772         return true;
 773 }
 774
 775 static bool bnx2x_check_move_always_err(
 776         struct bnx2x *bp,
 777         struct bnx2x_vlan_mac_obj *src_o,
 778         struct bnx2x_vlan_mac_obj *dst_o,
 779         union bnx2x_classification_ramrod_data *data)
 780 {
 781         return false;
 782 }
 783
 784 static inline u8 bnx2x_vlan_mac_get_rx_tx_flag(struct bnx2x_vlan_mac_obj *o)
 785 {
 786         struct bnx2x_raw_obj *raw = &o->raw;
 787         u8 rx_tx_flag = 0;
 788
 789         if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) ||
 790             (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
 791                 rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_TX_CMD;
 792
 793         if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) ||
 794             (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
 795                 rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_RX_CMD;
 796
 797         return rx_tx_flag;
 798 }
 799
 800 static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
 801                                  bool add, unsigned char *dev_addr, int index)
 802 {
 803         u32 wb_data[2];
 804         u32 reg_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
 805                          NIG_REG_LLH0_FUNC_MEM;
 806
 807         if (!IS_MF_SI(bp) && !IS_MF_AFEX(bp))
 808                 return;
 809
 810         if (index > BNX2X_LLH_CAM_MAX_PF_LINE)
 811                 return;
 812
 813         DP(BNX2X_MSG_SP, "Going to %s LLH configuration at entry %d\n",
 814                          (add ? "ADD" : "DELETE"), index);
 815
 816         if (add) {
 817                 /* LLH_FUNC_MEM is a u64 WB register */
 818                 reg_offset += 8*index;
 819
 820                 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
 821                               (dev_addr[4] <<  8) |  dev_addr[5]);
 822                 wb_data[1] = ((dev_addr[0] <<  8) |  dev_addr[1]);
 823
 824                 REG_WR_DMAE(bp, reg_offset, wb_data, 2);
 825         }
 826
 827         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
 828                                   NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4*index, add);
 829 }
 830
 831 /**
 832  * bnx2x_vlan_mac_set_cmd_hdr_e2 - set a header in a single classify ramrod
 833  *
 834  * @bp:         device handle
 835  * @o:          queue for which we want to configure this rule
 836  * @add:        if true the command is an ADD command, DEL otherwise
 837  * @opcode:     CLASSIFY_RULE_OPCODE_XXX
 838  * @hdr:        pointer to a header to setup
 839  *
 840  */
 841 static inline void bnx2x_vlan_mac_set_cmd_hdr_e2(struct bnx2x *bp,
 842         struct bnx2x_vlan_mac_obj *o, bool add, int opcode,
 843         struct eth_classify_cmd_header *hdr)
 844 {
 845         struct bnx2x_raw_obj *raw = &o->raw;
 846
 847         hdr->client_id = raw->cl_id;
 848         hdr->func_id = raw->func_id;
 849
 850         /* Rx or/and Tx (internal switching) configuration ? */
 851         hdr->cmd_general_data |=
 852                 bnx2x_vlan_mac_get_rx_tx_flag(o);
 853
 854         if (add)
 855                 hdr->cmd_general_data |= ETH_CLASSIFY_CMD_HEADER_IS_ADD;
 856
 857         hdr->cmd_general_data |=
 858                 (opcode << ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT);
 859 }
 860
 861 /**
 862  * bnx2x_vlan_mac_set_rdata_hdr_e2 - set the classify ramrod data header
 863  *
 864  * @cid:        connection id
 865  * @type:       BNX2X_FILTER_XXX_PENDING
 866  * @hdr:        pointer to header to setup
 867  * @rule_cnt:
 868  *
 869  * currently we always configure one rule and echo field to contain a CID and an
 870  * opcode type.
 871  */
 872 static inline void bnx2x_vlan_mac_set_rdata_hdr_e2(u32 cid, int type,
 873                                 struct eth_classify_header *hdr, int rule_cnt)
 874 {
 875         hdr->echo = cpu_to_le32((cid & BNX2X_SWCID_MASK) |
 876                                 (type << BNX2X_SWCID_SHIFT));
 877         hdr->rule_cnt = (u8)rule_cnt;
 878 }
 879
 880 /* hw_config() callbacks */
 881 static void bnx2x_set_one_mac_e2(struct bnx2x *bp,
 882                                  struct bnx2x_vlan_mac_obj *o,
 883                                  struct bnx2x_exeq_elem *elem, int rule_idx,
 884                                  int cam_offset)
 885 {
 886         struct bnx2x_raw_obj *raw = &o->raw;
 887         struct eth_classify_rules_ramrod_data *data =
 888                 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
 889         int rule_cnt = rule_idx + 1, cmd = elem->cmd_data.vlan_mac.cmd;
 890         union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
 891         bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false;
 892         unsigned long *vlan_mac_flags = &elem->cmd_data.vlan_mac.vlan_mac_flags;
 893         u8 *mac = elem->cmd_data.vlan_mac.u.mac.mac;
 894
 895         /* Set LLH CAM entry: currently only iSCSI and ETH macs are
 896          * relevant. In addition, current implementation is tuned for a
 897          * single ETH MAC.
 898          *
 899          * When multiple unicast ETH MACs PF configuration in switch
 900          * independent mode is required (NetQ, multiple netdev MACs,
 901          * etc.), consider better utilisation of 8 per function MAC
 902          * entries in the LLH register. There is also
 903          * NIG_REG_P[01]_LLH_FUNC_MEM2 registers that complete the
 904          * total number of CAM entries to 16.
 905          *
 906          * Currently we won't configure NIG for MACs other than a primary ETH
 907          * MAC and iSCSI L2 MAC.
 908          *
 909          * If this MAC is moving from one Queue to another, no need to change
 910          * NIG configuration.
 911          */
 912         if (cmd != BNX2X_VLAN_MAC_MOVE) {
 913                 if (test_bit(BNX2X_ISCSI_ETH_MAC, vlan_mac_flags))
 914                         bnx2x_set_mac_in_nig(bp, add, mac,
 915                                              BNX2X_LLH_CAM_ISCSI_ETH_LINE);
 916                 else if (test_bit(BNX2X_ETH_MAC, vlan_mac_flags))
 917                         bnx2x_set_mac_in_nig(bp, add, mac,
 918                                              BNX2X_LLH_CAM_ETH_LINE);
 919         }
 920
 921         /* Reset the ramrod data buffer for the first rule */
 922         if (rule_idx == 0)
 923                 memset(data, 0, sizeof(*data));
 924
 925         /* Setup a command header */
 926         bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_MAC,
 927                                       &rule_entry->mac.header);
 928
 929         DP(BNX2X_MSG_SP, "About to %s MAC %pM for Queue %d\n",
 930            (add ? "add" : "delete"), mac, raw->cl_id);
 931
 932         /* Set a MAC itself */
 933         bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb,
 934                               &rule_entry->mac.mac_mid,
 935                               &rule_entry->mac.mac_lsb, mac);
 936         rule_entry->mac.inner_mac =
 937                 cpu_to_le16(elem->cmd_data.vlan_mac.u.mac.is_inner_mac);
 938
 939         /* MOVE: Add a rule that will add this MAC to the target Queue */
 940         if (cmd == BNX2X_VLAN_MAC_MOVE) {
 941                 rule_entry++;
 942                 rule_cnt++;
 943
 944                 /* Setup ramrod data */
 945                 bnx2x_vlan_mac_set_cmd_hdr_e2(bp,
 946                                         elem->cmd_data.vlan_mac.target_obj,
 947                                               true, CLASSIFY_RULE_OPCODE_MAC,
 948                                               &rule_entry->mac.header);
 949
 950                 /* Set a MAC itself */
 951                 bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb,
 952                                       &rule_entry->mac.mac_mid,
 953                                       &rule_entry->mac.mac_lsb, mac);
 954                 rule_entry->mac.inner_mac =
 955                         cpu_to_le16(elem->cmd_data.vlan_mac.
 956                                                 u.mac.is_inner_mac);
 957         }
 958
 959         /* Set the ramrod data header */
 960         /* TODO: take this to the higher level in order to prevent multiple
 961                  writing */
 962         bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
 963                                         rule_cnt);
 964 }
 965
 966 /**
 967  * bnx2x_vlan_mac_set_rdata_hdr_e1x - set a header in a single classify ramrod
 968  *
 969  * @bp:         device handle
 970  * @o:          queue
 971  * @type:
 972  * @cam_offset: offset in cam memory
 973  * @hdr:        pointer to a header to setup
 974  *
 975  * E1/E1H
 976  */
 977 static inline void bnx2x_vlan_mac_set_rdata_hdr_e1x(struct bnx2x *bp,
 978         struct bnx2x_vlan_mac_obj *o, int type, int cam_offset,
 979         struct mac_configuration_hdr *hdr)
 980 {
 981         struct bnx2x_raw_obj *r = &o->raw;
 982
 983         hdr->length = 1;
 984         hdr->offset = (u8)cam_offset;
 985         hdr->client_id = cpu_to_le16(0xff);
 986         hdr->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
 987                                 (type << BNX2X_SWCID_SHIFT));
 988 }
 989
 990 static inline void bnx2x_vlan_mac_set_cfg_entry_e1x(struct bnx2x *bp,
 991         struct bnx2x_vlan_mac_obj *o, bool add, int opcode, u8 *mac,
 992         u16 vlan_id, struct mac_configuration_entry *cfg_entry)
 993 {
 994         struct bnx2x_raw_obj *r = &o->raw;
 995         u32 cl_bit_vec = (1 << r->cl_id);
 996
 997         cfg_entry->clients_bit_vector = cpu_to_le32(cl_bit_vec);
 998         cfg_entry->pf_id = r->func_id;
 999         cfg_entry->vlan_id = cpu_to_le16(vlan_id);
1000
1001         if (add) {
1002                 SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
1003                          T_ETH_MAC_COMMAND_SET);
1004                 SET_FLAG(cfg_entry->flags,
1005                          MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE, opcode);
1006
1007                 /* Set a MAC in a ramrod data */
1008                 bnx2x_set_fw_mac_addr(&cfg_entry->msb_mac_addr,
1009                                       &cfg_entry->middle_mac_addr,
1010                                       &cfg_entry->lsb_mac_addr, mac);
1011         } else
1012                 SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
1013                          T_ETH_MAC_COMMAND_INVALIDATE);
1014 }
1015
1016 static inline void bnx2x_vlan_mac_set_rdata_e1x(struct bnx2x *bp,
1017         struct bnx2x_vlan_mac_obj *o, int type, int cam_offset, bool add,
1018         u8 *mac, u16 vlan_id, int opcode, struct mac_configuration_cmd *config)
1019 {
1020         struct mac_configuration_entry *cfg_entry = &config->config_table[0];
1021         struct bnx2x_raw_obj *raw = &o->raw;
1022
1023         bnx2x_vlan_mac_set_rdata_hdr_e1x(bp, o, type, cam_offset,
1024                                          &config->hdr);
1025         bnx2x_vlan_mac_set_cfg_entry_e1x(bp, o, add, opcode, mac, vlan_id,
1026                                          cfg_entry);
1027
1028         DP(BNX2X_MSG_SP, "%s MAC %pM CLID %d CAM offset %d\n",
1029                          (add ? "setting" : "clearing"),
1030                          mac, raw->cl_id, cam_offset);
1031 }
1032
1033 /**
1034  * bnx2x_set_one_mac_e1x - fill a single MAC rule ramrod data
1035  *
1036  * @bp:         device handle
1037  * @o:          bnx2x_vlan_mac_obj
1038  * @elem:       bnx2x_exeq_elem
1039  * @rule_idx:   rule_idx
1040  * @cam_offset: cam_offset
1041  */
1042 static void bnx2x_set_one_mac_e1x(struct bnx2x *bp,
1043                                   struct bnx2x_vlan_mac_obj *o,
1044                                   struct bnx2x_exeq_elem *elem, int rule_idx,
1045                                   int cam_offset)
1046 {
1047         struct bnx2x_raw_obj *raw = &o->raw;
1048         struct mac_configuration_cmd *config =
1049                 (struct mac_configuration_cmd *)(raw->rdata);
1050         /* 57710 and 57711 do not support MOVE command,
1051          * so it's either ADD or DEL
1052          */
1053         bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ?
1054                 true : false;
1055
1056         /* Reset the ramrod data buffer */
1057         memset(config, 0, sizeof(*config));
1058
1059         bnx2x_vlan_mac_set_rdata_e1x(bp, o, raw->state,
1060                                      cam_offset, add,
1061                                      elem->cmd_data.vlan_mac.u.mac.mac, 0,
1062                                      ETH_VLAN_FILTER_ANY_VLAN, config);
1063 }
1064
1065 static void bnx2x_set_one_vlan_e2(struct bnx2x *bp,
1066                                   struct bnx2x_vlan_mac_obj *o,
1067                                   struct bnx2x_exeq_elem *elem, int rule_idx,
1068                                   int cam_offset)
1069 {
1070         struct bnx2x_raw_obj *raw = &o->raw;
1071         struct eth_classify_rules_ramrod_data *data =
1072                 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
1073         int rule_cnt = rule_idx + 1;
1074         union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
1075         enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
1076         bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false;
1077         u16 vlan = elem->cmd_data.vlan_mac.u.vlan.vlan;
1078
1079         /* Reset the ramrod data buffer for the first rule */
1080         if (rule_idx == 0)
1081                 memset(data, 0, sizeof(*data));
1082
1083         /* Set a rule header */
1084         bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_VLAN,
1085                                       &rule_entry->vlan.header);
1086
1087         DP(BNX2X_MSG_SP, "About to %s VLAN %d\n", (add ? "add" : "delete"),
1088                          vlan);
1089
1090         /* Set a VLAN itself */
1091         rule_entry->vlan.vlan = cpu_to_le16(vlan);
1092
1093         /* MOVE: Add a rule that will add this MAC to the target Queue */
1094         if (cmd == BNX2X_VLAN_MAC_MOVE) {
1095                 rule_entry++;
1096                 rule_cnt++;
1097
1098                 /* Setup ramrod data */
1099                 bnx2x_vlan_mac_set_cmd_hdr_e2(bp,
1100                                         elem->cmd_data.vlan_mac.target_obj,
1101                                               true, CLASSIFY_RULE_OPCODE_VLAN,
1102                                               &rule_entry->vlan.header);
1103
1104                 /* Set a VLAN itself */
1105                 rule_entry->vlan.vlan = cpu_to_le16(vlan);
1106         }
1107
1108         /* Set the ramrod data header */
1109         /* TODO: take this to the higher level in order to prevent multiple
1110                  writing */
1111         bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
1112                                         rule_cnt);
1113 }
1114
1115 static void bnx2x_set_one_vlan_mac_e2(struct bnx2x *bp,
1116                                       struct bnx2x_vlan_mac_obj *o,
1117                                       struct bnx2x_exeq_elem *elem,
1118                                       int rule_idx, int cam_offset)
1119 {
1120         struct bnx2x_raw_obj *raw = &o->raw;
1121         struct eth_classify_rules_ramrod_data *data =
1122                 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
1123         int rule_cnt = rule_idx + 1;
1124         union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
1125         enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
1126         bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false;
1127         u16 vlan = elem->cmd_data.vlan_mac.u.vlan_mac.vlan;
1128         u8 *mac = elem->cmd_data.vlan_mac.u.vlan_mac.mac;
1129         u16 inner_mac;
1130
1131         /* Reset the ramrod data buffer for the first rule */
1132         if (rule_idx == 0)
1133                 memset(data, 0, sizeof(*data));
1134
1135         /* Set a rule header */
1136         bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_PAIR,
1137                                       &rule_entry->pair.header);
1138
1139         /* Set VLAN and MAC themselves */
1140         rule_entry->pair.vlan = cpu_to_le16(vlan);
1141         bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb,
1142                               &rule_entry->pair.mac_mid,
1143                               &rule_entry->pair.mac_lsb, mac);
1144         inner_mac = elem->cmd_data.vlan_mac.u.vlan_mac.is_inner_mac;
1145         rule_entry->pair.inner_mac = cpu_to_le16(inner_mac);
1146         /* MOVE: Add a rule that will add this MAC/VLAN to the target Queue */
1147         if (cmd == BNX2X_VLAN_MAC_MOVE) {
1148                 struct bnx2x_vlan_mac_obj *target_obj;
1149
1150                 rule_entry++;
1151                 rule_cnt++;
1152
1153                 /* Setup ramrod data */
1154                 target_obj = elem->cmd_data.vlan_mac.target_obj;
1155                 bnx2x_vlan_mac_set_cmd_hdr_e2(bp, target_obj,
1156                                               true, CLASSIFY_RULE_OPCODE_PAIR,
1157                                               &rule_entry->pair.header);
1158
1159                 /* Set a VLAN itself */
1160                 rule_entry->pair.vlan = cpu_to_le16(vlan);
1161                 bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb,
1162                                       &rule_entry->pair.mac_mid,
1163                                       &rule_entry->pair.mac_lsb, mac);
1164                 rule_entry->pair.inner_mac = cpu_to_le16(inner_mac);
1165         }
1166
1167         /* Set the ramrod data header */
1168         bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
1169                                         rule_cnt);
1170 }
1171
1172 /**
1173  * bnx2x_set_one_vlan_mac_e1h -
1174  *
1175  * @bp:         device handle
1176  * @o:          bnx2x_vlan_mac_obj
1177  * @elem:       bnx2x_exeq_elem
1178  * @rule_idx:   rule_idx
1179  * @cam_offset: cam_offset
1180  */
1181 static void bnx2x_set_one_vlan_mac_e1h(struct bnx2x *bp,
1182                                        struct bnx2x_vlan_mac_obj *o,
1183                                        struct bnx2x_exeq_elem *elem,
1184                                        int rule_idx, int cam_offset)
1185 {
1186         struct bnx2x_raw_obj *raw = &o->raw;
1187         struct mac_configuration_cmd *config =
1188                 (struct mac_configuration_cmd *)(raw->rdata);
1189         /* 57710 and 57711 do not support MOVE command,
1190          * so it's either ADD or DEL
1191          */
1192         bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ?
1193                 true : false;
1194
1195         /* Reset the ramrod data buffer */
1196         memset(config, 0, sizeof(*config));
1197
1198         bnx2x_vlan_mac_set_rdata_e1x(bp, o, BNX2X_FILTER_VLAN_MAC_PENDING,
1199                                      cam_offset, add,
1200                                      elem->cmd_data.vlan_mac.u.vlan_mac.mac,
1201                                      elem->cmd_data.vlan_mac.u.vlan_mac.vlan,
1202                                      ETH_VLAN_FILTER_CLASSIFY, config);
1203 }
1204
1205 /**
1206  * bnx2x_vlan_mac_restore - reconfigure next MAC/VLAN/VLAN-MAC element
1207  *
1208  * @bp:         device handle
1209  * @p:          command parameters
1210  * @ppos:       pointer to the cookie
1211  *
1212  * reconfigure next MAC/VLAN/VLAN-MAC element from the
1213  * previously configured elements list.
1214  *
1215  * from command parameters only RAMROD_COMP_WAIT bit in ramrod_flags is taken
1216  * into an account
1217  *
1218  * pointer to the cookie  - that should be given back in the next call to make
1219  * function handle the next element. If *ppos is set to NULL it will restart the
1220  * iterator. If returned *ppos == NULL this means that the last element has been
1221  * handled.
1222  *
1223  */
1224 static int bnx2x_vlan_mac_restore(struct bnx2x *bp,
1225                            struct bnx2x_vlan_mac_ramrod_params *p,
1226                            struct bnx2x_vlan_mac_registry_elem **ppos)
1227 {
1228         struct bnx2x_vlan_mac_registry_elem *pos;
1229         struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj;
1230
1231         /* If list is empty - there is nothing to do here */
1232         if (list_empty(&o->head)) {
1233                 *ppos = NULL;
1234                 return 0;
1235         }
1236
1237         /* make a step... */
1238         if (*ppos == NULL)
1239                 *ppos = list_first_entry(&o->head,
1240                                          struct bnx2x_vlan_mac_registry_elem,
1241                                          link);
1242         else
1243                 *ppos = list_next_entry(*ppos, link);
1244
1245         pos = *ppos;
1246
1247         /* If it's the last step - return NULL */
1248         if (list_is_last(&pos->link, &o->head))
1249                 *ppos = NULL;
1250
1251         /* Prepare a 'user_req' */
1252         memcpy(&p->user_req.u, &pos->u, sizeof(pos->u));
1253
1254         /* Set the command */
1255         p->user_req.cmd = BNX2X_VLAN_MAC_ADD;
1256
1257         /* Set vlan_mac_flags */
1258         p->user_req.vlan_mac_flags = pos->vlan_mac_flags;
1259
1260         /* Set a restore bit */
1261         __set_bit(RAMROD_RESTORE, &p->ramrod_flags);
1262
1263         return bnx2x_config_vlan_mac(bp, p);
1264 }
1265
1266 /* bnx2x_exeq_get_mac/bnx2x_exeq_get_vlan/bnx2x_exeq_get_vlan_mac return a
1267  * pointer to an element with a specific criteria and NULL if such an element
1268  * hasn't been found.
1269  */
1270 static struct bnx2x_exeq_elem *bnx2x_exeq_get_mac(
1271         struct bnx2x_exe_queue_obj *o,
1272         struct bnx2x_exeq_elem *elem)
1273 {
1274         struct bnx2x_exeq_elem *pos;
1275         struct bnx2x_mac_ramrod_data *data = &elem->cmd_data.vlan_mac.u.mac;
1276
1277         /* Check pending for execution commands */
1278         list_for_each_entry(pos, &o->exe_queue, link)
1279                 if (!memcmp(&pos->cmd_data.vlan_mac.u.mac, data,
1280                               sizeof(*data)) &&
1281                     (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd))
1282                         return pos;
1283
1284         return NULL;
1285 }
1286
1287 static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan(
1288         struct bnx2x_exe_queue_obj *o,
1289         struct bnx2x_exeq_elem *elem)
1290 {
1291         struct bnx2x_exeq_elem *pos;
1292         struct bnx2x_vlan_ramrod_data *data = &elem->cmd_data.vlan_mac.u.vlan;
1293
1294         /* Check pending for execution commands */
1295         list_for_each_entry(pos, &o->exe_queue, link)
1296                 if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan, data,
1297                               sizeof(*data)) &&
1298                     (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd))
1299                         return pos;
1300
1301         return NULL;
1302 }
1303
1304 static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan_mac(
1305         struct bnx2x_exe_queue_obj *o,
1306         struct bnx2x_exeq_elem *elem)
1307 {
1308         struct bnx2x_exeq_elem *pos;
1309         struct bnx2x_vlan_mac_ramrod_data *data =
1310                 &elem->cmd_data.vlan_mac.u.vlan_mac;
1311
1312         /* Check pending for execution commands */
1313         list_for_each_entry(pos, &o->exe_queue, link)
1314                 if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan_mac, data,
1315                             sizeof(*data)) &&
1316                     (pos->cmd_data.vlan_mac.cmd ==
1317                      elem->cmd_data.vlan_mac.cmd))
1318                         return pos;
1319
1320         return NULL;
1321 }
1322
1323 /**
1324  * bnx2x_validate_vlan_mac_add - check if an ADD command can be executed
1325  *
1326  * @bp:         device handle
1327  * @qo:         bnx2x_qable_obj
1328  * @elem:       bnx2x_exeq_elem
1329  *
1330  * Checks that the requested configuration can be added. If yes and if
1331  * requested, consume CAM credit.
1332  *
1333  * The 'validate' is run after the 'optimize'.
1334  *
1335  */
1336 static inline int bnx2x_validate_vlan_mac_add(struct bnx2x *bp,
1337                                               union bnx2x_qable_obj *qo,
1338                                               struct bnx2x_exeq_elem *elem)
1339 {
1340         struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac;
1341         struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1342         int rc;
1343
1344         /* Check the registry */
1345         rc = o->check_add(bp, o, &elem->cmd_data.vlan_mac.u);
1346         if (rc) {
1347                 DP(BNX2X_MSG_SP, "ADD command is not allowed considering current registry state.\n");
1348                 return rc;
1349         }
1350
1351         /* Check if there is a pending ADD command for this
1352          * MAC/VLAN/VLAN-MAC. Return an error if there is.
1353          */
1354         if (exeq->get(exeq, elem)) {
1355                 DP(BNX2X_MSG_SP, "There is a pending ADD command already\n");
1356                 return -EEXIST;
1357         }
1358
1359         /* TODO: Check the pending MOVE from other objects where this
1360          * object is a destination object.
1361          */
1362
1363         /* Consume the credit if not requested not to */
1364         if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1365                        &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1366             o->get_credit(o)))
1367                 return -EINVAL;
1368
1369         return 0;
1370 }
1371
1372 /**
1373  * bnx2x_validate_vlan_mac_del - check if the DEL command can be executed
1374  *
1375  * @bp:         device handle
1376  * @qo:         quable object to check
1377  * @elem:       element that needs to be deleted
1378  *
1379  * Checks that the requested configuration can be deleted. If yes and if
1380  * requested, returns a CAM credit.
1381  *
1382  * The 'validate' is run after the 'optimize'.
1383  */
1384 static inline int bnx2x_validate_vlan_mac_del(struct bnx2x *bp,
1385                                               union bnx2x_qable_obj *qo,
1386                                               struct bnx2x_exeq_elem *elem)
1387 {
1388         struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac;
1389         struct bnx2x_vlan_mac_registry_elem *pos;
1390         struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1391         struct bnx2x_exeq_elem query_elem;
1392
1393         /* If this classification can not be deleted (doesn't exist)
1394          * - return a BNX2X_EXIST.
1395          */
1396         pos = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u);
1397         if (!pos) {
1398                 DP(BNX2X_MSG_SP, "DEL command is not allowed considering current registry state\n");
1399                 return -EEXIST;
1400         }
1401
1402         /* Check if there are pending DEL or MOVE commands for this
1403          * MAC/VLAN/VLAN-MAC. Return an error if so.
1404          */
1405         memcpy(&query_elem, elem, sizeof(query_elem));
1406
1407         /* Check for MOVE commands */
1408         query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_MOVE;
1409         if (exeq->get(exeq, &query_elem)) {
1410                 BNX2X_ERR("There is a pending MOVE command already\n");
1411                 return -EINVAL;
1412         }
1413
1414         /* Check for DEL commands */
1415         if (exeq->get(exeq, elem)) {
1416                 DP(BNX2X_MSG_SP, "There is a pending DEL command already\n");
1417                 return -EEXIST;
1418         }
1419
1420         /* Return the credit to the credit pool if not requested not to */
1421         if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1422                        &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1423             o->put_credit(o))) {
1424                 BNX2X_ERR("Failed to return a credit\n");
1425                 return -EINVAL;
1426         }
1427
1428         return 0;
1429 }
1430
1431 /**
1432  * bnx2x_validate_vlan_mac_move - check if the MOVE command can be executed
1433  *
1434  * @bp:         device handle
1435  * @qo:         quable object to check (source)
1436  * @elem:       element that needs to be moved
1437  *
1438  * Checks that the requested configuration can be moved. If yes and if
1439  * requested, returns a CAM credit.
1440  *
1441  * The 'validate' is run after the 'optimize'.
1442  */
1443 static inline int bnx2x_validate_vlan_mac_move(struct bnx2x *bp,
1444                                                union bnx2x_qable_obj *qo,
1445                                                struct bnx2x_exeq_elem *elem)
1446 {
1447         struct bnx2x_vlan_mac_obj *src_o = &qo->vlan_mac;
1448         struct bnx2x_vlan_mac_obj *dest_o = elem->cmd_data.vlan_mac.target_obj;
1449         struct bnx2x_exeq_elem query_elem;
1450         struct bnx2x_exe_queue_obj *src_exeq = &src_o->exe_queue;
1451         struct bnx2x_exe_queue_obj *dest_exeq = &dest_o->exe_queue;
1452
1453         /* Check if we can perform this operation based on the current registry
1454          * state.
1455          */
1456         if (!src_o->check_move(bp, src_o, dest_o,
1457                                &elem->cmd_data.vlan_mac.u)) {
1458                 DP(BNX2X_MSG_SP, "MOVE command is not allowed considering current registry state\n");
1459                 return -EINVAL;
1460         }
1461
1462         /* Check if there is an already pending DEL or MOVE command for the
1463          * source object or ADD command for a destination object. Return an
1464          * error if so.
1465          */
1466         memcpy(&query_elem, elem, sizeof(query_elem));
1467
1468         /* Check DEL on source */
1469         query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL;
1470         if (src_exeq->get(src_exeq, &query_elem)) {
1471                 BNX2X_ERR("There is a pending DEL command on the source queue already\n");
1472                 return -EINVAL;
1473         }
1474
1475         /* Check MOVE on source */
1476         if (src_exeq->get(src_exeq, elem)) {
1477                 DP(BNX2X_MSG_SP, "There is a pending MOVE command already\n");
1478                 return -EEXIST;
1479         }
1480
1481         /* Check ADD on destination */
1482         query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD;
1483         if (dest_exeq->get(dest_exeq, &query_elem)) {
1484                 BNX2X_ERR("There is a pending ADD command on the destination queue already\n");
1485                 return -EINVAL;
1486         }
1487
1488         /* Consume the credit if not requested not to */
1489         if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
1490                        &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1491             dest_o->get_credit(dest_o)))
1492                 return -EINVAL;
1493
1494         if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1495                        &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1496             src_o->put_credit(src_o))) {
1497                 /* return the credit taken from dest... */
1498                 dest_o->put_credit(dest_o);
1499                 return -EINVAL;
1500         }
1501
1502         return 0;
1503 }
1504
1505 static int bnx2x_validate_vlan_mac(struct bnx2x *bp,
1506                                    union bnx2x_qable_obj *qo,
1507                                    struct bnx2x_exeq_elem *elem)
1508 {
1509         switch (elem->cmd_data.vlan_mac.cmd) {
1510         case BNX2X_VLAN_MAC_ADD:
1511                 return bnx2x_validate_vlan_mac_add(bp, qo, elem);
1512         case BNX2X_VLAN_MAC_DEL:
1513                 return bnx2x_validate_vlan_mac_del(bp, qo, elem);
1514         case BNX2X_VLAN_MAC_MOVE:
1515                 return bnx2x_validate_vlan_mac_move(bp, qo, elem);
1516         default:
1517                 return -EINVAL;
1518         }
1519 }
1520
1521 static int bnx2x_remove_vlan_mac(struct bnx2x *bp,
1522                                   union bnx2x_qable_obj *qo,
1523                                   struct bnx2x_exeq_elem *elem)
1524 {
1525         int rc = 0;
1526
1527         /* If consumption wasn't required, nothing to do */
1528         if (test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1529                      &elem->cmd_data.vlan_mac.vlan_mac_flags))
1530                 return 0;
1531
1532         switch (elem->cmd_data.vlan_mac.cmd) {
1533         case BNX2X_VLAN_MAC_ADD:
1534         case BNX2X_VLAN_MAC_MOVE:
1535                 rc = qo->vlan_mac.put_credit(&qo->vlan_mac);
1536                 break;
1537         case BNX2X_VLAN_MAC_DEL:
1538                 rc = qo->vlan_mac.get_credit(&qo->vlan_mac);
1539                 break;
1540         default:
1541                 return -EINVAL;
1542         }
1543
1544         if (rc != true)
1545                 return -EINVAL;
1546
1547         return 0;
1548 }
1549
1550 /**
1551  * bnx2x_wait_vlan_mac - passively wait for 5 seconds until all work completes.
1552  *
1553  * @bp:         device handle
1554  * @o:          bnx2x_vlan_mac_obj
1555  *
1556  */
1557 static int bnx2x_wait_vlan_mac(struct bnx2x *bp,
1558                                struct bnx2x_vlan_mac_obj *o)
1559 {
1560         int cnt = 5000, rc;
1561         struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1562         struct bnx2x_raw_obj *raw = &o->raw;
1563
1564         while (cnt--) {
1565                 /* Wait for the current command to complete */
1566                 rc = raw->wait_comp(bp, raw);
1567                 if (rc)
1568                         return rc;
1569
1570                 /* Wait until there are no pending commands */
1571                 if (!bnx2x_exe_queue_empty(exeq))
1572                         usleep_range(1000, 2000);
1573                 else
1574                         return 0;
1575         }
1576
1577         return -EBUSY;
1578 }
1579
1580 static int __bnx2x_vlan_mac_execute_step(struct bnx2x *bp,
1581                                          struct bnx2x_vlan_mac_obj *o,
1582                                          unsigned long *ramrod_flags)
1583 {
1584         int rc = 0;
1585
1586         spin_lock_bh(&o->exe_queue.lock);
1587
1588         DP(BNX2X_MSG_SP, "vlan_mac_execute_step - trying to take writer lock\n");
1589         rc = __bnx2x_vlan_mac_h_write_trylock(bp, o);
1590
1591         if (rc != 0) {
1592                 __bnx2x_vlan_mac_h_pend(bp, o, *ramrod_flags);
1593
1594                 /* Calling function should not diffrentiate between this case
1595                  * and the case in which there is already a pending ramrod
1596                  */
1597                 rc = 1;
1598         } else {
1599                 rc = bnx2x_exe_queue_step(bp, &o->exe_queue, ramrod_flags);
1600         }
1601         spin_unlock_bh(&o->exe_queue.lock);
1602
1603         return rc;
1604 }
1605
1606 /**
1607  * bnx2x_complete_vlan_mac - complete one VLAN-MAC ramrod
1608  *
1609  * @bp:         device handle
1610  * @o:          bnx2x_vlan_mac_obj
1611  * @cqe:
1612  * @cont:       if true schedule next execution chunk
1613  *
1614  */
1615 static int bnx2x_complete_vlan_mac(struct bnx2x *bp,
1616                                    struct bnx2x_vlan_mac_obj *o,
1617                                    union event_ring_elem *cqe,
1618                                    unsigned long *ramrod_flags)
1619 {
1620         struct bnx2x_raw_obj *r = &o->raw;
1621         int rc;
1622
1623         /* Clearing the pending list & raw state should be made
1624          * atomically (as execution flow assumes they represent the same).
1625          */
1626         spin_lock_bh(&o->exe_queue.lock);
1627
1628         /* Reset pending list */
1629         __bnx2x_exe_queue_reset_pending(bp, &o->exe_queue);
1630
1631         /* Clear pending */
1632         r->clear_pending(r);
1633
1634         spin_unlock_bh(&o->exe_queue.lock);
1635
1636         /* If ramrod failed this is most likely a SW bug */
1637         if (cqe->message.error)
1638                 return -EINVAL;
1639
1640         /* Run the next bulk of pending commands if requested */
1641         if (test_bit(RAMROD_CONT, ramrod_flags)) {
1642                 rc = __bnx2x_vlan_mac_execute_step(bp, o, ramrod_flags);
1643
1644                 if (rc < 0)
1645                         return rc;
1646         }
1647
1648         /* If there is more work to do return PENDING */
1649         if (!bnx2x_exe_queue_empty(&o->exe_queue))
1650                 return 1;
1651
1652         return 0;
1653 }
1654
1655 /**
1656  * bnx2x_optimize_vlan_mac - optimize ADD and DEL commands.
1657  *
1658  * @bp:         device handle
1659  * @o:          bnx2x_qable_obj
1660  * @elem:       bnx2x_exeq_elem
1661  */
1662 static int bnx2x_optimize_vlan_mac(struct bnx2x *bp,
1663                                    union bnx2x_qable_obj *qo,
1664                                    struct bnx2x_exeq_elem *elem)
1665 {
1666         struct bnx2x_exeq_elem query, *pos;
1667         struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac;
1668         struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1669
1670         memcpy(&query, elem, sizeof(query));
1671
1672         switch (elem->cmd_data.vlan_mac.cmd) {
1673         case BNX2X_VLAN_MAC_ADD:
1674                 query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL;
1675                 break;
1676         case BNX2X_VLAN_MAC_DEL:
1677                 query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD;
1678                 break;
1679         default:
1680                 /* Don't handle anything other than ADD or DEL */
1681                 return 0;
1682         }
1683
1684         /* If we found the appropriate element - delete it */
1685         pos = exeq->get(exeq, &query);
1686         if (pos) {
1687
1688                 /* Return the credit of the optimized command */
1689                 if (!test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1690                               &pos->cmd_data.vlan_mac.vlan_mac_flags)) {
1691                         if ((query.cmd_data.vlan_mac.cmd ==
1692                              BNX2X_VLAN_MAC_ADD) && !o->put_credit(o)) {
1693                                 BNX2X_ERR("Failed to return the credit for the optimized ADD command\n");
1694                                 return -EINVAL;
1695                         } else if (!o->get_credit(o)) { /* VLAN_MAC_DEL */
1696                                 BNX2X_ERR("Failed to recover the credit from the optimized DEL command\n");
1697                                 return -EINVAL;
1698                         }
1699                 }
1700
1701                 DP(BNX2X_MSG_SP, "Optimizing %s command\n",
1702                            (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ?
1703                            "ADD" : "DEL");
1704
1705                 list_del(&pos->link);
1706                 bnx2x_exe_queue_free_elem(bp, pos);
1707                 return 1;
1708         }
1709
1710         return 0;
1711 }
1712
1713 /**
1714  * bnx2x_vlan_mac_get_registry_elem - prepare a registry element
1715  *
1716  * @bp:   device handle
1717  * @o:
1718  * @elem:
1719  * @restore:
1720  * @re:
1721  *
1722  * prepare a registry element according to the current command request.
1723  */
1724 static inline int bnx2x_vlan_mac_get_registry_elem(
1725         struct bnx2x *bp,
1726         struct bnx2x_vlan_mac_obj *o,
1727         struct bnx2x_exeq_elem *elem,
1728         bool restore,
1729         struct bnx2x_vlan_mac_registry_elem **re)
1730 {
1731         enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
1732         struct bnx2x_vlan_mac_registry_elem *reg_elem;
1733
1734         /* Allocate a new registry element if needed. */
1735         if (!restore &&
1736             ((cmd == BNX2X_VLAN_MAC_ADD) || (cmd == BNX2X_VLAN_MAC_MOVE))) {
1737                 reg_elem = kzalloc(sizeof(*reg_elem), GFP_ATOMIC);
1738                 if (!reg_elem)
1739                         return -ENOMEM;
1740
1741                 /* Get a new CAM offset */
1742                 if (!o->get_cam_offset(o, &reg_elem->cam_offset)) {
1743                         /* This shall never happen, because we have checked the
1744                          * CAM availability in the 'validate'.
1745                          */
1746                         WARN_ON(1);
1747                         kfree(reg_elem);
1748                         return -EINVAL;
1749                 }
1750
1751                 DP(BNX2X_MSG_SP, "Got cam offset %d\n", reg_elem->cam_offset);
1752
1753                 /* Set a VLAN-MAC data */
1754                 memcpy(&reg_elem->u, &elem->cmd_data.vlan_mac.u,
1755                           sizeof(reg_elem->u));
1756
1757                 /* Copy the flags (needed for DEL and RESTORE flows) */
1758                 reg_elem->vlan_mac_flags =
1759                         elem->cmd_data.vlan_mac.vlan_mac_flags;
1760         } else /* DEL, RESTORE */
1761                 reg_elem = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u);
1762
1763         *re = reg_elem;
1764         return 0;
1765 }
1766
1767 /**
1768  * bnx2x_execute_vlan_mac - execute vlan mac command
1769  *
1770  * @bp:                 device handle
1771  * @qo:
1772  * @exe_chunk:
1773  * @ramrod_flags:
1774  *
1775  * go and send a ramrod!
1776  */
1777 static int bnx2x_execute_vlan_mac(struct bnx2x *bp,
1778                                   union bnx2x_qable_obj *qo,
1779                                   struct list_head *exe_chunk,
1780                                   unsigned long *ramrod_flags)
1781 {
1782         struct bnx2x_exeq_elem *elem;
1783         struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac, *cam_obj;
1784         struct bnx2x_raw_obj *r = &o->raw;
1785         int rc, idx = 0;
1786         bool restore = test_bit(RAMROD_RESTORE, ramrod_flags);
1787         bool drv_only = test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags);
1788         struct bnx2x_vlan_mac_registry_elem *reg_elem;
1789         enum bnx2x_vlan_mac_cmd cmd;
1790
1791         /* If DRIVER_ONLY execution is requested, cleanup a registry
1792          * and exit. Otherwise send a ramrod to FW.
1793          */
1794         if (!drv_only) {
1795                 WARN_ON(r->check_pending(r));
1796
1797                 /* Set pending */
1798                 r->set_pending(r);
1799
1800                 /* Fill the ramrod data */
1801                 list_for_each_entry(elem, exe_chunk, link) {
1802                         cmd = elem->cmd_data.vlan_mac.cmd;
1803                         /* We will add to the target object in MOVE command, so
1804                          * change the object for a CAM search.
1805                          */
1806                         if (cmd == BNX2X_VLAN_MAC_MOVE)
1807                                 cam_obj = elem->cmd_data.vlan_mac.target_obj;
1808                         else
1809                                 cam_obj = o;
1810
1811                         rc = bnx2x_vlan_mac_get_registry_elem(bp, cam_obj,
1812                                                               elem, restore,
1813                                                               &reg_elem);
1814                         if (rc)
1815                                 goto error_exit;
1816
1817                         WARN_ON(!reg_elem);
1818
1819                         /* Push a new entry into the registry */
1820                         if (!restore &&
1821                             ((cmd == BNX2X_VLAN_MAC_ADD) ||
1822                             (cmd == BNX2X_VLAN_MAC_MOVE)))
1823                                 list_add(&reg_elem->link, &cam_obj->head);
1824
1825                         /* Configure a single command in a ramrod data buffer */
1826                         o->set_one_rule(bp, o, elem, idx,
1827                                         reg_elem->cam_offset);
1828
1829                         /* MOVE command consumes 2 entries in the ramrod data */
1830                         if (cmd == BNX2X_VLAN_MAC_MOVE)
1831                                 idx += 2;
1832                         else
1833                                 idx++;
1834                 }
1835
1836                 /* No need for an explicit memory barrier here as long we would
1837                  * need to ensure the ordering of writing to the SPQ element
1838                  * and updating of the SPQ producer which involves a memory
1839                  * read and we will have to put a full memory barrier there
1840                  * (inside bnx2x_sp_post()).
1841                  */
1842
1843                 rc = bnx2x_sp_post(bp, o->ramrod_cmd, r->cid,
1844                                    U64_HI(r->rdata_mapping),
1845                                    U64_LO(r->rdata_mapping),
1846                                    ETH_CONNECTION_TYPE);
1847                 if (rc)
1848                         goto error_exit;
1849         }
1850
1851         /* Now, when we are done with the ramrod - clean up the registry */
1852         list_for_each_entry(elem, exe_chunk, link) {
1853                 cmd = elem->cmd_data.vlan_mac.cmd;
1854                 if ((cmd == BNX2X_VLAN_MAC_DEL) ||
1855                     (cmd == BNX2X_VLAN_MAC_MOVE)) {
1856                         reg_elem = o->check_del(bp, o,
1857                                                 &elem->cmd_data.vlan_mac.u);
1858
1859                         WARN_ON(!reg_elem);
1860
1861                         o->put_cam_offset(o, reg_elem->cam_offset);
1862                         list_del(&reg_elem->link);
1863                         kfree(reg_elem);
1864                 }
1865         }
1866
1867         if (!drv_only)
1868                 return 1;
1869         else
1870                 return 0;
1871
1872 error_exit:
1873         r->clear_pending(r);
1874
1875         /* Cleanup a registry in case of a failure */
1876         list_for_each_entry(elem, exe_chunk, link) {
1877                 cmd = elem->cmd_data.vlan_mac.cmd;
1878
1879                 if (cmd == BNX2X_VLAN_MAC_MOVE)
1880                         cam_obj = elem->cmd_data.vlan_mac.target_obj;
1881                 else
1882                         cam_obj = o;
1883
1884                 /* Delete all newly added above entries */
1885                 if (!restore &&
1886                     ((cmd == BNX2X_VLAN_MAC_ADD) ||
1887                     (cmd == BNX2X_VLAN_MAC_MOVE))) {
1888                         reg_elem = o->check_del(bp, cam_obj,
1889                                                 &elem->cmd_data.vlan_mac.u);
1890                         if (reg_elem) {
1891                                 list_del(&reg_elem->link);
1892                                 kfree(reg_elem);
1893                         }
1894                 }
1895         }
1896
1897         return rc;
1898 }
1899
1900 static inline int bnx2x_vlan_mac_push_new_cmd(
1901         struct bnx2x *bp,
1902         struct bnx2x_vlan_mac_ramrod_params *p)
1903 {
1904         struct bnx2x_exeq_elem *elem;
1905         struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj;
1906         bool restore = test_bit(RAMROD_RESTORE, &p->ramrod_flags);
1907
1908         /* Allocate the execution queue element */
1909         elem = bnx2x_exe_queue_alloc_elem(bp);
1910         if (!elem)
1911                 return -ENOMEM;
1912
1913         /* Set the command 'length' */
1914         switch (p->user_req.cmd) {
1915         case BNX2X_VLAN_MAC_MOVE:
1916                 elem->cmd_len = 2;
1917                 break;
1918         default:
1919                 elem->cmd_len = 1;
1920         }
1921
1922         /* Fill the object specific info */
1923         memcpy(&elem->cmd_data.vlan_mac, &p->user_req, sizeof(p->user_req));
1924
1925         /* Try to add a new command to the pending list */
1926         return bnx2x_exe_queue_add(bp, &o->exe_queue, elem, restore);
1927 }
1928
1929 /**
1930  * bnx2x_config_vlan_mac - configure VLAN/MAC/VLAN_MAC filtering rules.
1931  *
1932  * @bp:   device handle
1933  * @p:
1934  *
1935  */
1936 int bnx2x_config_vlan_mac(struct bnx2x *bp,
1937                            struct bnx2x_vlan_mac_ramrod_params *p)
1938 {
1939         int rc = 0;
1940         struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj;
1941         unsigned long *ramrod_flags = &p->ramrod_flags;
1942         bool cont = test_bit(RAMROD_CONT, ramrod_flags);
1943         struct bnx2x_raw_obj *raw = &o->raw;
1944
1945         /*
1946          * Add new elements to the execution list for commands that require it.
1947          */
1948         if (!cont) {
1949                 rc = bnx2x_vlan_mac_push_new_cmd(bp, p);
1950                 if (rc)
1951                         return rc;
1952         }
1953
1954         /* If nothing will be executed further in this iteration we want to
1955          * return PENDING if there are pending commands
1956          */
1957         if (!bnx2x_exe_queue_empty(&o->exe_queue))
1958                 rc = 1;
1959
1960         if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags))  {
1961                 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.\n");
1962                 raw->clear_pending(raw);
1963         }
1964
1965         /* Execute commands if required */
1966         if (cont || test_bit(RAMROD_EXEC, ramrod_flags) ||
1967             test_bit(RAMROD_COMP_WAIT, ramrod_flags)) {
1968                 rc = __bnx2x_vlan_mac_execute_step(bp, p->vlan_mac_obj,
1969                                                    &p->ramrod_flags);
1970                 if (rc < 0)
1971                         return rc;
1972         }
1973
1974         /* RAMROD_COMP_WAIT is a superset of RAMROD_EXEC. If it was set
1975          * then user want to wait until the last command is done.
1976          */
1977         if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) {
1978                 /* Wait maximum for the current exe_queue length iterations plus
1979                  * one (for the current pending command).
1980                  */
1981                 int max_iterations = bnx2x_exe_queue_length(&o->exe_queue) + 1;
1982
1983                 while (!bnx2x_exe_queue_empty(&o->exe_queue) &&
1984                        max_iterations--) {
1985
1986                         /* Wait for the current command to complete */
1987                         rc = raw->wait_comp(bp, raw);
1988                         if (rc)
1989                                 return rc;
1990
1991                         /* Make a next step */
1992                         rc = __bnx2x_vlan_mac_execute_step(bp,
1993                                                            p->vlan_mac_obj,
1994                                                            &p->ramrod_flags);
1995                         if (rc < 0)
1996                                 return rc;
1997                 }
1998
1999                 return 0;
2000         }
2001
2002         return rc;
2003 }
2004
2005 /**
2006  * bnx2x_vlan_mac_del_all - delete elements with given vlan_mac_flags spec
2007  *
2008  * @bp:                 device handle
2009  * @o:
2010  * @vlan_mac_flags:
2011  * @ramrod_flags:       execution flags to be used for this deletion
2012  *
2013  * if the last operation has completed successfully and there are no
2014  * more elements left, positive value if the last operation has completed
2015  * successfully and there are more previously configured elements, negative
2016  * value is current operation has failed.
2017  */
2018 static int bnx2x_vlan_mac_del_all(struct bnx2x *bp,
2019                                   struct bnx2x_vlan_mac_obj *o,
2020                                   unsigned long *vlan_mac_flags,
2021                                   unsigned long *ramrod_flags)
2022 {
2023         struct bnx2x_vlan_mac_registry_elem *pos = NULL;
2024         struct bnx2x_vlan_mac_ramrod_params p;
2025         struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
2026         struct bnx2x_exeq_elem *exeq_pos, *exeq_pos_n;
2027         unsigned long flags;
2028         int read_lock;
2029         int rc = 0;
2030
2031         /* Clear pending commands first */
2032
2033         spin_lock_bh(&exeq->lock);
2034
2035         list_for_each_entry_safe(exeq_pos, exeq_pos_n, &exeq->exe_queue, link) {
2036                 flags = exeq_pos->cmd_data.vlan_mac.vlan_mac_flags;
2037                 if (BNX2X_VLAN_MAC_CMP_FLAGS(flags) ==
2038                     BNX2X_VLAN_MAC_CMP_FLAGS(*vlan_mac_flags)) {
2039                         rc = exeq->remove(bp, exeq->owner, exeq_pos);
2040                         if (rc) {
2041                                 BNX2X_ERR("Failed to remove command\n");
2042                                 spin_unlock_bh(&exeq->lock);
2043                                 return rc;
2044                         }
2045                         list_del(&exeq_pos->link);
2046                         bnx2x_exe_queue_free_elem(bp, exeq_pos);
2047                 }
2048         }
2049
2050         spin_unlock_bh(&exeq->lock);
2051
2052         /* Prepare a command request */
2053         memset(&p, 0, sizeof(p));
2054         p.vlan_mac_obj = o;
2055         p.ramrod_flags = *ramrod_flags;
2056         p.user_req.cmd = BNX2X_VLAN_MAC_DEL;
2057
2058         /* Add all but the last VLAN-MAC to the execution queue without actually
2059          * execution anything.
2060          */
2061         __clear_bit(RAMROD_COMP_WAIT, &p.ramrod_flags);
2062         __clear_bit(RAMROD_EXEC, &p.ramrod_flags);
2063         __clear_bit(RAMROD_CONT, &p.ramrod_flags);
2064
2065         DP(BNX2X_MSG_SP, "vlan_mac_del_all -- taking vlan_mac_lock (reader)\n");
2066         read_lock = bnx2x_vlan_mac_h_read_lock(bp, o);
2067         if (read_lock != 0)
2068                 return read_lock;
2069
2070         list_for_each_entry(pos, &o->head, link) {
2071                 flags = pos->vlan_mac_flags;
2072                 if (BNX2X_VLAN_MAC_CMP_FLAGS(flags) ==
2073                     BNX2X_VLAN_MAC_CMP_FLAGS(*vlan_mac_flags)) {
2074                         p.user_req.vlan_mac_flags = pos->vlan_mac_flags;
2075                         memcpy(&p.user_req.u, &pos->u, sizeof(pos->u));
2076                         rc = bnx2x_config_vlan_mac(bp, &p);
2077                         if (rc < 0) {
2078                                 BNX2X_ERR("Failed to add a new DEL command\n");
2079                                 bnx2x_vlan_mac_h_read_unlock(bp, o);
2080                                 return rc;
2081                         }
2082                 }
2083         }
2084
2085         DP(BNX2X_MSG_SP, "vlan_mac_del_all -- releasing vlan_mac_lock (reader)\n");
2086         bnx2x_vlan_mac_h_read_unlock(bp, o);
2087
2088         p.ramrod_flags = *ramrod_flags;
2089         __set_bit(RAMROD_CONT, &p.ramrod_flags);
2090
2091         return bnx2x_config_vlan_mac(bp, &p);
2092 }
2093
2094 static inline void bnx2x_init_raw_obj(struct bnx2x_raw_obj *raw, u8 cl_id,
2095         u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping, int state,
2096         unsigned long *pstate, bnx2x_obj_type type)
2097 {
2098         raw->func_id = func_id;
2099         raw->cid = cid;
2100         raw->cl_id = cl_id;
2101         raw->rdata = rdata;
2102         raw->rdata_mapping = rdata_mapping;
2103         raw->state = state;
2104         raw->pstate = pstate;
2105         raw->obj_type = type;
2106         raw->check_pending = bnx2x_raw_check_pending;
2107         raw->clear_pending = bnx2x_raw_clear_pending;
2108         raw->set_pending = bnx2x_raw_set_pending;
2109         raw->wait_comp = bnx2x_raw_wait;
2110 }
2111
2112 static inline void bnx2x_init_vlan_mac_common(struct bnx2x_vlan_mac_obj *o,
2113         u8 cl_id, u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping,
2114         int state, unsigned long *pstate, bnx2x_obj_type type,
2115         struct bnx2x_credit_pool_obj *macs_pool,
2116         struct bnx2x_credit_pool_obj *vlans_pool)
2117 {
2118         INIT_LIST_HEAD(&o->head);
2119         o->head_reader = 0;
2120         o->head_exe_request = false;
2121         o->saved_ramrod_flags = 0;
2122
2123         o->macs_pool = macs_pool;
2124         o->vlans_pool = vlans_pool;
2125
2126         o->delete_all = bnx2x_vlan_mac_del_all;
2127         o->restore = bnx2x_vlan_mac_restore;
2128         o->complete = bnx2x_complete_vlan_mac;
2129         o->wait = bnx2x_wait_vlan_mac;
2130
2131         bnx2x_init_raw_obj(&o->raw, cl_id, cid, func_id, rdata, rdata_mapping,
2132                            state, pstate, type);
2133 }
2134
2135 void bnx2x_init_mac_obj(struct bnx2x *bp,
2136                         struct bnx2x_vlan_mac_obj *mac_obj,
2137                         u8 cl_id, u32 cid, u8 func_id, void *rdata,
2138                         dma_addr_t rdata_mapping, int state,
2139                         unsigned long *pstate, bnx2x_obj_type type,
2140                         struct bnx2x_credit_pool_obj *macs_pool)
2141 {
2142         union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)mac_obj;
2143
2144         bnx2x_init_vlan_mac_common(mac_obj, cl_id, cid, func_id, rdata,
2145                                    rdata_mapping, state, pstate, type,
2146                                    macs_pool, NULL);
2147
2148         /* CAM credit pool handling */
2149         mac_obj->get_credit = bnx2x_get_credit_mac;
2150         mac_obj->put_credit = bnx2x_put_credit_mac;
2151         mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac;
2152         mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac;
2153
2154         if (CHIP_IS_E1x(bp)) {
2155                 mac_obj->set_one_rule      = bnx2x_set_one_mac_e1x;
2156                 mac_obj->check_del         = bnx2x_check_mac_del;
2157                 mac_obj->check_add         = bnx2x_check_mac_add;
2158                 mac_obj->check_move        = bnx2x_check_move_always_err;
2159                 mac_obj->ramrod_cmd        = RAMROD_CMD_ID_ETH_SET_MAC;
2160
2161                 /* Exe Queue */
2162                 bnx2x_exe_queue_init(bp,
2163                                      &mac_obj->exe_queue, 1, qable_obj,
2164                                      bnx2x_validate_vlan_mac,
2165                                      bnx2x_remove_vlan_mac,
2166                                      bnx2x_optimize_vlan_mac,
2167                                      bnx2x_execute_vlan_mac,
2168                                      bnx2x_exeq_get_mac);
2169         } else {
2170                 mac_obj->set_one_rule      = bnx2x_set_one_mac_e2;
2171                 mac_obj->check_del         = bnx2x_check_mac_del;
2172                 mac_obj->check_add         = bnx2x_check_mac_add;
2173                 mac_obj->check_move        = bnx2x_check_move;
2174                 mac_obj->ramrod_cmd        =
2175                         RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
2176                 mac_obj->get_n_elements    = bnx2x_get_n_elements;
2177
2178                 /* Exe Queue */
2179                 bnx2x_exe_queue_init(bp,
2180                                      &mac_obj->exe_queue, CLASSIFY_RULES_COUNT,
2181                                      qable_obj, bnx2x_validate_vlan_mac,
2182                                      bnx2x_remove_vlan_mac,
2183                                      bnx2x_optimize_vlan_mac,
2184                                      bnx2x_execute_vlan_mac,
2185                                      bnx2x_exeq_get_mac);
2186         }
2187 }
2188
2189 void bnx2x_init_vlan_obj(struct bnx2x *bp,
2190                          struct bnx2x_vlan_mac_obj *vlan_obj,
2191                          u8 cl_id, u32 cid, u8 func_id, void *rdata,
2192                          dma_addr_t rdata_mapping, int state,
2193                          unsigned long *pstate, bnx2x_obj_type type,
2194                          struct bnx2x_credit_pool_obj *vlans_pool)
2195 {
2196         union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)vlan_obj;
2197
2198         bnx2x_init_vlan_mac_common(vlan_obj, cl_id, cid, func_id, rdata,
2199                                    rdata_mapping, state, pstate, type, NULL,
2200                                    vlans_pool);
2201
2202         vlan_obj->get_credit = bnx2x_get_credit_vlan;
2203         vlan_obj->put_credit = bnx2x_put_credit_vlan;
2204         vlan_obj->get_cam_offset = bnx2x_get_cam_offset_vlan;
2205         vlan_obj->put_cam_offset = bnx2x_put_cam_offset_vlan;
2206
2207         if (CHIP_IS_E1x(bp)) {
2208                 BNX2X_ERR("Do not support chips others than E2 and newer\n");
2209                 BUG();
2210         } else {
2211                 vlan_obj->set_one_rule      = bnx2x_set_one_vlan_e2;
2212                 vlan_obj->check_del         = bnx2x_check_vlan_del;
2213                 vlan_obj->check_add         = bnx2x_check_vlan_add;
2214                 vlan_obj->check_move        = bnx2x_check_move;
2215                 vlan_obj->ramrod_cmd        =
2216                         RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
2217                 vlan_obj->get_n_elements    = bnx2x_get_n_elements;
2218
2219                 /* Exe Queue */
2220                 bnx2x_exe_queue_init(bp,
2221                                      &vlan_obj->exe_queue, CLASSIFY_RULES_COUNT,
2222                                      qable_obj, bnx2x_validate_vlan_mac,
2223                                      bnx2x_remove_vlan_mac,
2224                                      bnx2x_optimize_vlan_mac,
2225                                      bnx2x_execute_vlan_mac,
2226                                      bnx2x_exeq_get_vlan);
2227         }
2228 }
2229
2230 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp,
2231                              struct bnx2x_vlan_mac_obj *vlan_mac_obj,
2232                              u8 cl_id, u32 cid, u8 func_id, void *rdata,
2233                              dma_addr_t rdata_mapping, int state,
2234                              unsigned long *pstate, bnx2x_obj_type type,
2235                              struct bnx2x_credit_pool_obj *macs_pool,
2236                              struct bnx2x_credit_pool_obj *vlans_pool)
2237 {
2238         union bnx2x_qable_obj *qable_obj =
2239                 (union bnx2x_qable_obj *)vlan_mac_obj;
2240
2241         bnx2x_init_vlan_mac_common(vlan_mac_obj, cl_id, cid, func_id, rdata,
2242                                    rdata_mapping, state, pstate, type,
2243                                    macs_pool, vlans_pool);
2244
2245         /* CAM pool handling */
2246         vlan_mac_obj->get_credit = bnx2x_get_credit_vlan_mac;
2247         vlan_mac_obj->put_credit = bnx2x_put_credit_vlan_mac;
2248         /* CAM offset is relevant for 57710 and 57711 chips only which have a
2249          * single CAM for both MACs and VLAN-MAC pairs. So the offset
2250          * will be taken from MACs' pool object only.
2251          */
2252         vlan_mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac;
2253         vlan_mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac;
2254
2255         if (CHIP_IS_E1(bp)) {
2256                 BNX2X_ERR("Do not support chips others than E2\n");
2257                 BUG();
2258         } else if (CHIP_IS_E1H(bp)) {
2259                 vlan_mac_obj->set_one_rule      = bnx2x_set_one_vlan_mac_e1h;
2260                 vlan_mac_obj->check_del         = bnx2x_check_vlan_mac_del;
2261                 vlan_mac_obj->check_add         = bnx2x_check_vlan_mac_add;
2262                 vlan_mac_obj->check_move        = bnx2x_check_move_always_err;
2263                 vlan_mac_obj->ramrod_cmd        = RAMROD_CMD_ID_ETH_SET_MAC;
2264
2265                 /* Exe Queue */
2266                 bnx2x_exe_queue_init(bp,
2267                                      &vlan_mac_obj->exe_queue, 1, qable_obj,
2268                                      bnx2x_validate_vlan_mac,
2269                                      bnx2x_remove_vlan_mac,
2270                                      bnx2x_optimize_vlan_mac,
2271                                      bnx2x_execute_vlan_mac,
2272                                      bnx2x_exeq_get_vlan_mac);
2273         } else {
2274                 vlan_mac_obj->set_one_rule      = bnx2x_set_one_vlan_mac_e2;
2275                 vlan_mac_obj->check_del         = bnx2x_check_vlan_mac_del;
2276                 vlan_mac_obj->check_add         = bnx2x_check_vlan_mac_add;
2277                 vlan_mac_obj->check_move        = bnx2x_check_move;
2278                 vlan_mac_obj->ramrod_cmd        =
2279                         RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
2280
2281                 /* Exe Queue */
2282                 bnx2x_exe_queue_init(bp,
2283                                      &vlan_mac_obj->exe_queue,
2284                                      CLASSIFY_RULES_COUNT,
2285                                      qable_obj, bnx2x_validate_vlan_mac,
2286                                      bnx2x_remove_vlan_mac,
2287                                      bnx2x_optimize_vlan_mac,
2288                                      bnx2x_execute_vlan_mac,
2289                                      bnx2x_exeq_get_vlan_mac);
2290         }
2291 }
2292 /* RX_MODE verbs: DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
2293 static inline void __storm_memset_mac_filters(struct bnx2x *bp,
2294                         struct tstorm_eth_mac_filter_config *mac_filters,
2295                         u16 pf_id)
2296 {
2297         size_t size = sizeof(struct tstorm_eth_mac_filter_config);
2298
2299         u32 addr = BAR_TSTRORM_INTMEM +
2300                         TSTORM_MAC_FILTER_CONFIG_OFFSET(pf_id);
2301
2302         __storm_memset_struct(bp, addr, size, (u32 *)mac_filters);
2303 }
2304
2305 static int bnx2x_set_rx_mode_e1x(struct bnx2x *bp,
2306                                  struct bnx2x_rx_mode_ramrod_params *p)
2307 {
2308         /* update the bp MAC filter structure */
2309         u32 mask = (1 << p->cl_id);
2310
2311         struct tstorm_eth_mac_filter_config *mac_filters =
2312                 (struct tstorm_eth_mac_filter_config *)p->rdata;
2313
2314         /* initial setting is drop-all */
2315         u8 drop_all_ucast = 1, drop_all_mcast = 1;
2316         u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2317         u8 unmatched_unicast = 0;
2318
2319     /* In e1x there we only take into account rx accept flag since tx switching
2320      * isn't enabled. */
2321         if (test_bit(BNX2X_ACCEPT_UNICAST, &p->rx_accept_flags))
2322                 /* accept matched ucast */
2323                 drop_all_ucast = 0;
2324
2325         if (test_bit(BNX2X_ACCEPT_MULTICAST, &p->rx_accept_flags))
2326                 /* accept matched mcast */
2327                 drop_all_mcast = 0;
2328
2329         if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, &p->rx_accept_flags)) {
2330                 /* accept all mcast */
2331                 drop_all_ucast = 0;
2332                 accp_all_ucast = 1;
2333         }
2334         if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, &p->rx_accept_flags)) {
2335                 /* accept all mcast */
2336                 drop_all_mcast = 0;
2337                 accp_all_mcast = 1;
2338         }
2339         if (test_bit(BNX2X_ACCEPT_BROADCAST, &p->rx_accept_flags))
2340                 /* accept (all) bcast */
2341                 accp_all_bcast = 1;
2342         if (test_bit(BNX2X_ACCEPT_UNMATCHED, &p->rx_accept_flags))
2343                 /* accept unmatched unicasts */
2344                 unmatched_unicast = 1;
2345
2346         mac_filters->ucast_drop_all = drop_all_ucast ?
2347                 mac_filters->ucast_drop_all | mask :
2348                 mac_filters->ucast_drop_all & ~mask;
2349
2350         mac_filters->mcast_drop_all = drop_all_mcast ?
2351                 mac_filters->mcast_drop_all | mask :
2352                 mac_filters->mcast_drop_all & ~mask;
2353
2354         mac_filters->ucast_accept_all = accp_all_ucast ?
2355                 mac_filters->ucast_accept_all | mask :
2356                 mac_filters->ucast_accept_all & ~mask;
2357
2358         mac_filters->mcast_accept_all = accp_all_mcast ?
2359                 mac_filters->mcast_accept_all | mask :
2360                 mac_filters->mcast_accept_all & ~mask;
2361
2362         mac_filters->bcast_accept_all = accp_all_bcast ?
2363                 mac_filters->bcast_accept_all | mask :
2364                 mac_filters->bcast_accept_all & ~mask;
2365
2366         mac_filters->unmatched_unicast = unmatched_unicast ?
2367                 mac_filters->unmatched_unicast | mask :
2368                 mac_filters->unmatched_unicast & ~mask;
2369
2370         DP(BNX2X_MSG_SP, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n"
2371                          "accp_mcast 0x%x\naccp_bcast 0x%x\n",
2372            mac_filters->ucast_drop_all, mac_filters->mcast_drop_all,
2373            mac_filters->ucast_accept_all, mac_filters->mcast_accept_all,
2374            mac_filters->bcast_accept_all);
2375
2376         /* write the MAC filter structure*/
2377         __storm_memset_mac_filters(bp, mac_filters, p->func_id);
2378
2379         /* The operation is completed */
2380         clear_bit(p->state, p->pstate);
2381         smp_mb__after_atomic();
2382
2383         return 0;
2384 }
2385
2386 /* Setup ramrod data */
2387 static inline void bnx2x_rx_mode_set_rdata_hdr_e2(u32 cid,
2388                                 struct eth_classify_header *hdr,
2389                                 u8 rule_cnt)
2390 {
2391         hdr->echo = cpu_to_le32(cid);
2392         hdr->rule_cnt = rule_cnt;
2393 }
2394
2395 static inline void bnx2x_rx_mode_set_cmd_state_e2(struct bnx2x *bp,
2396                                 unsigned long *accept_flags,
2397                                 struct eth_filter_rules_cmd *cmd,
2398                                 bool clear_accept_all)
2399 {
2400         u16 state;
2401
2402         /* start with 'drop-all' */
2403         state = ETH_FILTER_RULES_CMD_UCAST_DROP_ALL |
2404                 ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2405
2406         if (test_bit(BNX2X_ACCEPT_UNICAST, accept_flags))
2407                 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2408
2409         if (test_bit(BNX2X_ACCEPT_MULTICAST, accept_flags))
2410                 state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2411
2412         if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, accept_flags)) {
2413                 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2414                 state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL;
2415         }
2416
2417         if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, accept_flags)) {
2418                 state |= ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL;
2419                 state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2420         }
2421
2422         if (test_bit(BNX2X_ACCEPT_BROADCAST, accept_flags))
2423                 state |= ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL;
2424
2425         if (test_bit(BNX2X_ACCEPT_UNMATCHED, accept_flags)) {
2426                 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2427                 state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED;
2428         }
2429
2430         if (test_bit(BNX2X_ACCEPT_ANY_VLAN, accept_flags))
2431                 state |= ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN;
2432
2433         /* Clear ACCEPT_ALL_XXX flags for FCoE L2 Queue */
2434         if (clear_accept_all) {
2435                 state &= ~ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL;
2436                 state &= ~ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL;
2437                 state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL;
2438                 state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED;
2439         }
2440
2441         cmd->state = cpu_to_le16(state);
2442 }
2443
2444 static int bnx2x_set_rx_mode_e2(struct bnx2x *bp,
2445                                 struct bnx2x_rx_mode_ramrod_params *p)
2446 {
2447         struct eth_filter_rules_ramrod_data *data = p->rdata;
2448         int rc;
2449         u8 rule_idx = 0;
2450
2451         /* Reset the ramrod data buffer */
2452         memset(data, 0, sizeof(*data));
2453
2454         /* Setup ramrod data */
2455
2456         /* Tx (internal switching) */
2457         if (test_bit(RAMROD_TX, &p->ramrod_flags)) {
2458                 data->rules[rule_idx].client_id = p->cl_id;
2459                 data->rules[rule_idx].func_id = p->func_id;
2460
2461                 data->rules[rule_idx].cmd_general_data =
2462                         ETH_FILTER_RULES_CMD_TX_CMD;
2463
2464                 bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags,
2465                                                &(data->rules[rule_idx++]),
2466                                                false);
2467         }
2468
2469         /* Rx */
2470         if (test_bit(RAMROD_RX, &p->ramrod_flags)) {
2471                 data->rules[rule_idx].client_id = p->cl_id;
2472                 data->rules[rule_idx].func_id = p->func_id;
2473
2474                 data->rules[rule_idx].cmd_general_data =
2475                         ETH_FILTER_RULES_CMD_RX_CMD;
2476
2477                 bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags,
2478                                                &(data->rules[rule_idx++]),
2479                                                false);
2480         }
2481
2482         /* If FCoE Queue configuration has been requested configure the Rx and
2483          * internal switching modes for this queue in separate rules.
2484          *
2485          * FCoE queue shell never be set to ACCEPT_ALL packets of any sort:
2486          * MCAST_ALL, UCAST_ALL, BCAST_ALL and UNMATCHED.
2487          */
2488         if (test_bit(BNX2X_RX_MODE_FCOE_ETH, &p->rx_mode_flags)) {
2489                 /*  Tx (internal switching) */
2490                 if (test_bit(RAMROD_TX, &p->ramrod_flags)) {
2491                         data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id);
2492                         data->rules[rule_idx].func_id = p->func_id;
2493
2494                         data->rules[rule_idx].cmd_general_data =
2495                                                 ETH_FILTER_RULES_CMD_TX_CMD;
2496
2497                         bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags,
2498                                                        &(data->rules[rule_idx]),
2499                                                        true);
2500                         rule_idx++;
2501                 }
2502
2503                 /* Rx */
2504                 if (test_bit(RAMROD_RX, &p->ramrod_flags)) {
2505                         data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id);
2506                         data->rules[rule_idx].func_id = p->func_id;
2507
2508                         data->rules[rule_idx].cmd_general_data =
2509                                                 ETH_FILTER_RULES_CMD_RX_CMD;
2510
2511                         bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags,
2512                                                        &(data->rules[rule_idx]),
2513                                                        true);
2514                         rule_idx++;
2515                 }
2516         }
2517
2518         /* Set the ramrod header (most importantly - number of rules to
2519          * configure).
2520          */
2521         bnx2x_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx);
2522
2523         DP(BNX2X_MSG_SP, "About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\n",
2524                          data->header.rule_cnt, p->rx_accept_flags,
2525                          p->tx_accept_flags);
2526
2527         /* No need for an explicit memory barrier here as long as we
2528          * ensure the ordering of writing to the SPQ element
2529          * and updating of the SPQ producer which involves a memory
2530          * read. If the memory read is removed we will have to put a
2531          * full memory barrier there (inside bnx2x_sp_post()).
2532          */
2533
2534         /* Send a ramrod */
2535         rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_FILTER_RULES, p->cid,
2536                            U64_HI(p->rdata_mapping),
2537                            U64_LO(p->rdata_mapping),
2538                            ETH_CONNECTION_TYPE);
2539         if (rc)
2540                 return rc;
2541
2542         /* Ramrod completion is pending */
2543         return 1;
2544 }
2545
2546 static int bnx2x_wait_rx_mode_comp_e2(struct bnx2x *bp,
2547                                       struct bnx2x_rx_mode_ramrod_params *p)
2548 {
2549         return bnx2x_state_wait(bp, p->state, p->pstate);
2550 }
2551
2552 static int bnx2x_empty_rx_mode_wait(struct bnx2x *bp,
2553                                     struct bnx2x_rx_mode_ramrod_params *p)
2554 {
2555         /* Do nothing */
2556         return 0;
2557 }
2558
2559 int bnx2x_config_rx_mode(struct bnx2x *bp,
2560                          struct bnx2x_rx_mode_ramrod_params *p)
2561 {
2562         int rc;
2563
2564         /* Configure the new classification in the chip */
2565         rc = p->rx_mode_obj->config_rx_mode(bp, p);
2566         if (rc < 0)
2567                 return rc;
2568
2569         /* Wait for a ramrod completion if was requested */
2570         if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) {
2571                 rc = p->rx_mode_obj->wait_comp(bp, p);
2572                 if (rc)
2573                         return rc;
2574         }
2575
2576         return rc;
2577 }
2578
2579 void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
2580                             struct bnx2x_rx_mode_obj *o)
2581 {
2582         if (CHIP_IS_E1x(bp)) {
2583                 o->wait_comp      = bnx2x_empty_rx_mode_wait;
2584                 o->config_rx_mode = bnx2x_set_rx_mode_e1x;
2585         } else {
2586                 o->wait_comp      = bnx2x_wait_rx_mode_comp_e2;
2587                 o->config_rx_mode = bnx2x_set_rx_mode_e2;
2588         }
2589 }
2590
2591 /********************* Multicast verbs: SET, CLEAR ****************************/
2592 static inline u8 bnx2x_mcast_bin_from_mac(u8 *mac)
2593 {
2594         return (crc32c_le(0, mac, ETH_ALEN) >> 24) & 0xff;
2595 }
2596
2597 struct bnx2x_mcast_mac_elem {
2598         struct list_head link;
2599         u8 mac[ETH_ALEN];
2600         u8 pad[2]; /* For a natural alignment of the following buffer */
2601 };
2602
2603 struct bnx2x_pending_mcast_cmd {
2604         struct list_head link;
2605         int type; /* BNX2X_MCAST_CMD_X */
2606         union {
2607                 struct list_head macs_head;
2608                 u32 macs_num; /* Needed for DEL command */
2609                 int next_bin; /* Needed for RESTORE flow with aprox match */
2610         } data;
2611
2612         bool done; /* set to true, when the command has been handled,
2613                     * practically used in 57712 handling only, where one pending
2614                     * command may be handled in a few operations. As long as for
2615                     * other chips every operation handling is completed in a
2616                     * single ramrod, there is no need to utilize this field.
2617                     */
2618 };
2619
2620 static int bnx2x_mcast_wait(struct bnx2x *bp,
2621                             struct bnx2x_mcast_obj *o)
2622 {
2623         if (bnx2x_state_wait(bp, o->sched_state, o->raw.pstate) ||
2624                         o->raw.wait_comp(bp, &o->raw))
2625                 return -EBUSY;
2626
2627         return 0;
2628 }
2629
2630 static int bnx2x_mcast_enqueue_cmd(struct bnx2x *bp,
2631                                    struct bnx2x_mcast_obj *o,
2632                                    struct bnx2x_mcast_ramrod_params *p,
2633                                    enum bnx2x_mcast_cmd cmd)
2634 {
2635         int total_sz;
2636         struct bnx2x_pending_mcast_cmd *new_cmd;
2637         struct bnx2x_mcast_mac_elem *cur_mac = NULL;
2638         struct bnx2x_mcast_list_elem *pos;
2639         int macs_list_len = ((cmd == BNX2X_MCAST_CMD_ADD) ?
2640                              p->mcast_list_len : 0);
2641
2642         /* If the command is empty ("handle pending commands only"), break */
2643         if (!p->mcast_list_len)
2644                 return 0;
2645
2646         total_sz = sizeof(*new_cmd) +
2647                 macs_list_len * sizeof(struct bnx2x_mcast_mac_elem);
2648
2649         /* Add mcast is called under spin_lock, thus calling with GFP_ATOMIC */
2650         new_cmd = kzalloc(total_sz, GFP_ATOMIC);
2651
2652         if (!new_cmd)
2653                 return -ENOMEM;
2654
2655         DP(BNX2X_MSG_SP, "About to enqueue a new %d command. macs_list_len=%d\n",
2656            cmd, macs_list_len);
2657
2658         INIT_LIST_HEAD(&new_cmd->data.macs_head);
2659
2660         new_cmd->type = cmd;
2661         new_cmd->done = false;
2662
2663         switch (cmd) {
2664         case BNX2X_MCAST_CMD_ADD:
2665                 cur_mac = (struct bnx2x_mcast_mac_elem *)
2666                           ((u8 *)new_cmd + sizeof(*new_cmd));
2667
2668                 /* Push the MACs of the current command into the pending command
2669                  * MACs list: FIFO
2670                  */
2671                 list_for_each_entry(pos, &p->mcast_list, link) {
2672                         memcpy(cur_mac->mac, pos->mac, ETH_ALEN);
2673                         list_add_tail(&cur_mac->link, &new_cmd->data.macs_head);
2674                         cur_mac++;
2675                 }
2676
2677                 break;
2678
2679         case BNX2X_MCAST_CMD_DEL:
2680                 new_cmd->data.macs_num = p->mcast_list_len;
2681                 break;
2682
2683         case BNX2X_MCAST_CMD_RESTORE:
2684                 new_cmd->data.next_bin = 0;
2685                 break;
2686
2687         default:
2688                 kfree(new_cmd);
2689                 BNX2X_ERR("Unknown command: %d\n", cmd);
2690                 return -EINVAL;
2691         }
2692
2693         /* Push the new pending command to the tail of the pending list: FIFO */
2694         list_add_tail(&new_cmd->link, &o->pending_cmds_head);
2695
2696         o->set_sched(o);
2697
2698         return 1;
2699 }
2700
2701 /**
2702  * bnx2x_mcast_get_next_bin - get the next set bin (index)
2703  *
2704  * @o:
2705  * @last:       index to start looking from (including)
2706  *
2707  * returns the next found (set) bin or a negative value if none is found.
2708  */
2709 static inline int bnx2x_mcast_get_next_bin(struct bnx2x_mcast_obj *o, int last)
2710 {
2711         int i, j, inner_start = last % BIT_VEC64_ELEM_SZ;
2712
2713         for (i = last / BIT_VEC64_ELEM_SZ; i < BNX2X_MCAST_VEC_SZ; i++) {
2714                 if (o->registry.aprox_match.vec[i])
2715                         for (j = inner_start; j < BIT_VEC64_ELEM_SZ; j++) {
2716                                 int cur_bit = j + BIT_VEC64_ELEM_SZ * i;
2717                                 if (BIT_VEC64_TEST_BIT(o->registry.aprox_match.
2718                                                        vec, cur_bit)) {
2719                                         return cur_bit;
2720                                 }
2721                         }
2722                 inner_start = 0;
2723         }
2724
2725         /* None found */
2726         return -1;
2727 }
2728
2729 /**
2730  * bnx2x_mcast_clear_first_bin - find the first set bin and clear it
2731  *
2732  * @o:
2733  *
2734  * returns the index of the found bin or -1 if none is found
2735  */
2736 static inline int bnx2x_mcast_clear_first_bin(struct bnx2x_mcast_obj *o)
2737 {
2738         int cur_bit = bnx2x_mcast_get_next_bin(o, 0);
2739
2740         if (cur_bit >= 0)
2741                 BIT_VEC64_CLEAR_BIT(o->registry.aprox_match.vec, cur_bit);
2742
2743         return cur_bit;
2744 }
2745
2746 static inline u8 bnx2x_mcast_get_rx_tx_flag(struct bnx2x_mcast_obj *o)
2747 {
2748         struct bnx2x_raw_obj *raw = &o->raw;
2749         u8 rx_tx_flag = 0;
2750
2751         if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) ||
2752             (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
2753                 rx_tx_flag |= ETH_MULTICAST_RULES_CMD_TX_CMD;
2754
2755         if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) ||
2756             (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
2757                 rx_tx_flag |= ETH_MULTICAST_RULES_CMD_RX_CMD;
2758
2759         return rx_tx_flag;
2760 }
2761
2762 static void bnx2x_mcast_set_one_rule_e2(struct bnx2x *bp,
2763                                         struct bnx2x_mcast_obj *o, int idx,
2764                                         union bnx2x_mcast_config_data *cfg_data,
2765                                         enum bnx2x_mcast_cmd cmd)
2766 {
2767         struct bnx2x_raw_obj *r = &o->raw;
2768         struct eth_multicast_rules_ramrod_data *data =
2769                 (struct eth_multicast_rules_ramrod_data *)(r->rdata);
2770         u8 func_id = r->func_id;
2771         u8 rx_tx_add_flag = bnx2x_mcast_get_rx_tx_flag(o);
2772         int bin;
2773
2774         if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE))
2775                 rx_tx_add_flag |= ETH_MULTICAST_RULES_CMD_IS_ADD;
2776
2777         data->rules[idx].cmd_general_data |= rx_tx_add_flag;
2778
2779         /* Get a bin and update a bins' vector */
2780         switch (cmd) {
2781         case BNX2X_MCAST_CMD_ADD:
2782                 bin = bnx2x_mcast_bin_from_mac(cfg_data->mac);
2783                 BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bin);
2784                 break;
2785
2786         case BNX2X_MCAST_CMD_DEL:
2787                 /* If there were no more bins to clear
2788                  * (bnx2x_mcast_clear_first_bin() returns -1) then we would
2789                  * clear any (0xff) bin.
2790                  * See bnx2x_mcast_validate_e2() for explanation when it may
2791                  * happen.
2792                  */
2793                 bin = bnx2x_mcast_clear_first_bin(o);
2794                 break;
2795
2796         case BNX2X_MCAST_CMD_RESTORE:
2797                 bin = cfg_data->bin;
2798                 break;
2799
2800         default:
2801                 BNX2X_ERR("Unknown command: %d\n", cmd);
2802                 return;
2803         }
2804
2805         DP(BNX2X_MSG_SP, "%s bin %d\n",
2806                          ((rx_tx_add_flag & ETH_MULTICAST_RULES_CMD_IS_ADD) ?
2807                          "Setting"  : "Clearing"), bin);
2808
2809         data->rules[idx].bin_id    = (u8)bin;
2810         data->rules[idx].func_id   = func_id;
2811         data->rules[idx].engine_id = o->engine_id;
2812 }
2813
2814 /**
2815  * bnx2x_mcast_handle_restore_cmd_e2 - restore configuration from the registry
2816  *
2817  * @bp:         device handle
2818  * @o:
2819  * @start_bin:  index in the registry to start from (including)
2820  * @rdata_idx:  index in the ramrod data to start from
2821  *
2822  * returns last handled bin index or -1 if all bins have been handled
2823  */
2824 static inline int bnx2x_mcast_handle_restore_cmd_e2(
2825         struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_bin,
2826         int *rdata_idx)
2827 {
2828         int cur_bin, cnt = *rdata_idx;
2829         union bnx2x_mcast_config_data cfg_data = {NULL};
2830
2831         /* go through the registry and configure the bins from it */
2832         for (cur_bin = bnx2x_mcast_get_next_bin(o, start_bin); cur_bin >= 0;
2833             cur_bin = bnx2x_mcast_get_next_bin(o, cur_bin + 1)) {
2834
2835                 cfg_data.bin = (u8)cur_bin;
2836                 o->set_one_rule(bp, o, cnt, &cfg_data,
2837                                 BNX2X_MCAST_CMD_RESTORE);
2838
2839                 cnt++;
2840
2841                 DP(BNX2X_MSG_SP, "About to configure a bin %d\n", cur_bin);
2842
2843                 /* Break if we reached the maximum number
2844                  * of rules.
2845                  */
2846                 if (cnt >= o->max_cmd_len)
2847                         break;
2848         }
2849
2850         *rdata_idx = cnt;
2851
2852         return cur_bin;
2853 }
2854
2855 static inline void bnx2x_mcast_hdl_pending_add_e2(struct bnx2x *bp,
2856         struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos,
2857         int *line_idx)
2858 {
2859         struct bnx2x_mcast_mac_elem *pmac_pos, *pmac_pos_n;
2860         int cnt = *line_idx;
2861         union bnx2x_mcast_config_data cfg_data = {NULL};
2862
2863         list_for_each_entry_safe(pmac_pos, pmac_pos_n, &cmd_pos->data.macs_head,
2864                                  link) {
2865
2866                 cfg_data.mac = &pmac_pos->mac[0];
2867                 o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type);
2868
2869                 cnt++;
2870
2871                 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
2872                    pmac_pos->mac);
2873
2874                 list_del(&pmac_pos->link);
2875
2876                 /* Break if we reached the maximum number
2877                  * of rules.
2878                  */
2879                 if (cnt >= o->max_cmd_len)
2880                         break;
2881         }
2882
2883         *line_idx = cnt;
2884
2885         /* if no more MACs to configure - we are done */
2886         if (list_empty(&cmd_pos->data.macs_head))
2887                 cmd_pos->done = true;
2888 }
2889
2890 static inline void bnx2x_mcast_hdl_pending_del_e2(struct bnx2x *bp,
2891         struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos,
2892         int *line_idx)
2893 {
2894         int cnt = *line_idx;
2895
2896         while (cmd_pos->data.macs_num) {
2897                 o->set_one_rule(bp, o, cnt, NULL, cmd_pos->type);
2898
2899                 cnt++;
2900
2901                 cmd_pos->data.macs_num--;
2902
2903                   DP(BNX2X_MSG_SP, "Deleting MAC. %d left,cnt is %d\n",
2904                                    cmd_pos->data.macs_num, cnt);
2905
2906                 /* Break if we reached the maximum
2907                  * number of rules.
2908                  */
2909                 if (cnt >= o->max_cmd_len)
2910                         break;
2911         }
2912
2913         *line_idx = cnt;
2914
2915         /* If we cleared all bins - we are done */
2916         if (!cmd_pos->data.macs_num)
2917                 cmd_pos->done = true;
2918 }
2919
2920 static inline void bnx2x_mcast_hdl_pending_restore_e2(struct bnx2x *bp,
2921         struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos,
2922         int *line_idx)
2923 {
2924         cmd_pos->data.next_bin = o->hdl_restore(bp, o, cmd_pos->data.next_bin,
2925                                                 line_idx);
2926
2927         if (cmd_pos->data.next_bin < 0)
2928                 /* If o->set_restore returned -1 we are done */
2929                 cmd_pos->done = true;
2930         else
2931                 /* Start from the next bin next time */
2932                 cmd_pos->data.next_bin++;
2933 }
2934
2935 static inline int bnx2x_mcast_handle_pending_cmds_e2(struct bnx2x *bp,
2936                                 struct bnx2x_mcast_ramrod_params *p)
2937 {
2938         struct bnx2x_pending_mcast_cmd *cmd_pos, *cmd_pos_n;
2939         int cnt = 0;
2940         struct bnx2x_mcast_obj *o = p->mcast_obj;
2941
2942         list_for_each_entry_safe(cmd_pos, cmd_pos_n, &o->pending_cmds_head,
2943                                  link) {
2944                 switch (cmd_pos->type) {
2945                 case BNX2X_MCAST_CMD_ADD:
2946                         bnx2x_mcast_hdl_pending_add_e2(bp, o, cmd_pos, &cnt);
2947                         break;
2948
2949                 case BNX2X_MCAST_CMD_DEL:
2950                         bnx2x_mcast_hdl_pending_del_e2(bp, o, cmd_pos, &cnt);
2951                         break;
2952
2953                 case BNX2X_MCAST_CMD_RESTORE:
2954                         bnx2x_mcast_hdl_pending_restore_e2(bp, o, cmd_pos,
2955                                                            &cnt);
2956                         break;
2957
2958                 default:
2959                         BNX2X_ERR("Unknown command: %d\n", cmd_pos->type);
2960                         return -EINVAL;
2961                 }
2962
2963                 /* If the command has been completed - remove it from the list
2964                  * and free the memory
2965                  */
2966                 if (cmd_pos->done) {
2967                         list_del(&cmd_pos->link);
2968                         kfree(cmd_pos);
2969                 }
2970
2971                 /* Break if we reached the maximum number of rules */
2972                 if (cnt >= o->max_cmd_len)
2973                         break;
2974         }
2975
2976         return cnt;
2977 }
2978
2979 static inline void bnx2x_mcast_hdl_add(struct bnx2x *bp,
2980         struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p,
2981         int *line_idx)
2982 {
2983         struct bnx2x_mcast_list_elem *mlist_pos;
2984         union bnx2x_mcast_config_data cfg_data = {NULL};
2985         int cnt = *line_idx;
2986
2987         list_for_each_entry(mlist_pos, &p->mcast_list, link) {
2988                 cfg_data.mac = mlist_pos->mac;
2989                 o->set_one_rule(bp, o, cnt, &cfg_data, BNX2X_MCAST_CMD_ADD);
2990
2991                 cnt++;
2992
2993                 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
2994                    mlist_pos->mac);
2995         }
2996
2997         *line_idx = cnt;
2998 }
2999
3000 static inline void bnx2x_mcast_hdl_del(struct bnx2x *bp,
3001         struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p,
3002         int *line_idx)
3003 {
3004         int cnt = *line_idx, i;
3005
3006         for (i = 0; i < p->mcast_list_len; i++) {
3007                 o->set_one_rule(bp, o, cnt, NULL, BNX2X_MCAST_CMD_DEL);
3008
3009                 cnt++;
3010
3011                 DP(BNX2X_MSG_SP, "Deleting MAC. %d left\n",
3012                                  p->mcast_list_len - i - 1);
3013         }
3014
3015         *line_idx = cnt;
3016 }
3017
3018 /**
3019  * bnx2x_mcast_handle_current_cmd -
3020  *
3021  * @bp:         device handle
3022  * @p:
3023  * @cmd:
3024  * @start_cnt:  first line in the ramrod data that may be used
3025  *
3026  * This function is called iff there is enough place for the current command in
3027  * the ramrod data.
3028  * Returns number of lines filled in the ramrod data in total.
3029  */
3030 static inline int bnx2x_mcast_handle_current_cmd(struct bnx2x *bp,
3031                         struct bnx2x_mcast_ramrod_params *p,
3032                         enum bnx2x_mcast_cmd cmd,
3033                         int start_cnt)
3034 {
3035         struct bnx2x_mcast_obj *o = p->mcast_obj;
3036         int cnt = start_cnt;
3037
3038         DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len);
3039
3040         switch (cmd) {
3041         case BNX2X_MCAST_CMD_ADD:
3042                 bnx2x_mcast_hdl_add(bp, o, p, &cnt);
3043                 break;
3044
3045         case BNX2X_MCAST_CMD_DEL:
3046                 bnx2x_mcast_hdl_del(bp, o, p, &cnt);
3047                 break;
3048
3049         case BNX2X_MCAST_CMD_RESTORE:
3050                 o->hdl_restore(bp, o, 0, &cnt);
3051                 break;
3052
3053         default:
3054                 BNX2X_ERR("Unknown command: %d\n", cmd);
3055                 return -EINVAL;
3056         }
3057
3058         /* The current command has been handled */
3059         p->mcast_list_len = 0;
3060
3061         return cnt;
3062 }
3063
3064 static int bnx2x_mcast_validate_e2(struct bnx2x *bp,
3065                                    struct bnx2x_mcast_ramrod_params *p,
3066                                    enum bnx2x_mcast_cmd cmd)
3067 {
3068         struct bnx2x_mcast_obj *o = p->mcast_obj;
3069         int reg_sz = o->get_registry_size(o);
3070
3071         switch (cmd) {
3072         /* DEL command deletes all currently configured MACs */
3073         case BNX2X_MCAST_CMD_DEL:
3074                 o->set_registry_size(o, 0);
3075                 /* Don't break */
3076
3077         /* RESTORE command will restore the entire multicast configuration */
3078         case BNX2X_MCAST_CMD_RESTORE:
3079                 /* Here we set the approximate amount of work to do, which in
3080                  * fact may be only less as some MACs in postponed ADD
3081                  * command(s) scheduled before this command may fall into
3082                  * the same bin and the actual number of bins set in the
3083                  * registry would be less than we estimated here. See
3084                  * bnx2x_mcast_set_one_rule_e2() for further details.
3085                  */
3086                 p->mcast_list_len = reg_sz;
3087                 break;
3088
3089         case BNX2X_MCAST_CMD_ADD:
3090         case BNX2X_MCAST_CMD_CONT:
3091                 /* Here we assume that all new MACs will fall into new bins.
3092                  * However we will correct the real registry size after we
3093                  * handle all pending commands.
3094                  */
3095                 o->set_registry_size(o, reg_sz + p->mcast_list_len);
3096                 break;
3097
3098         default:
3099                 BNX2X_ERR("Unknown command: %d\n", cmd);
3100                 return -EINVAL;
3101         }
3102
3103         /* Increase the total number of MACs pending to be configured */
3104         o->total_pending_num += p->mcast_list_len;
3105
3106         return 0;
3107 }
3108
3109 static void bnx2x_mcast_revert_e2(struct bnx2x *bp,
3110                                       struct bnx2x_mcast_ramrod_params *p,
3111                                       int old_num_bins)
3112 {
3113         struct bnx2x_mcast_obj *o = p->mcast_obj;
3114
3115         o->set_registry_size(o, old_num_bins);
3116         o->total_pending_num -= p->mcast_list_len;
3117 }
3118
3119 /**
3120  * bnx2x_mcast_set_rdata_hdr_e2 - sets a header values
3121  *
3122  * @bp:         device handle
3123  * @p:
3124  * @len:        number of rules to handle
3125  */
3126 static inline void bnx2x_mcast_set_rdata_hdr_e2(struct bnx2x *bp,
3127                                         struct bnx2x_mcast_ramrod_params *p,
3128                                         u8 len)
3129 {
3130         struct bnx2x_raw_obj *r = &p->mcast_obj->raw;
3131         struct eth_multicast_rules_ramrod_data *data =
3132                 (struct eth_multicast_rules_ramrod_data *)(r->rdata);
3133
3134         data->header.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
3135                                         (BNX2X_FILTER_MCAST_PENDING <<
3136                                          BNX2X_SWCID_SHIFT));
3137         data->header.rule_cnt = len;
3138 }
3139
3140 /**
3141  * bnx2x_mcast_refresh_registry_e2 - recalculate the actual number of set bins
3142  *
3143  * @bp:         device handle
3144  * @o:
3145  *
3146  * Recalculate the actual number of set bins in the registry using Brian
3147  * Kernighan's algorithm: it's execution complexity is as a number of set bins.
3148  *
3149  * returns 0 for the compliance with bnx2x_mcast_refresh_registry_e1().
3150  */
3151 static inline int bnx2x_mcast_refresh_registry_e2(struct bnx2x *bp,
3152                                                   struct bnx2x_mcast_obj *o)
3153 {
3154         int i, cnt = 0;
3155         u64 elem;
3156
3157         for (i = 0; i < BNX2X_MCAST_VEC_SZ; i++) {
3158                 elem = o->registry.aprox_match.vec[i];
3159                 for (; elem; cnt++)
3160                         elem &= elem - 1;
3161         }
3162
3163         o->set_registry_size(o, cnt);
3164
3165         return 0;
3166 }
3167
3168 static int bnx2x_mcast_setup_e2(struct bnx2x *bp,
3169                                 struct bnx2x_mcast_ramrod_params *p,
3170                                 enum bnx2x_mcast_cmd cmd)
3171 {
3172         struct bnx2x_raw_obj *raw = &p->mcast_obj->raw;
3173         struct bnx2x_mcast_obj *o = p->mcast_obj;
3174         struct eth_multicast_rules_ramrod_data *data =
3175                 (struct eth_multicast_rules_ramrod_data *)(raw->rdata);
3176         int cnt = 0, rc;
3177
3178         /* Reset the ramrod data buffer */
3179         memset(data, 0, sizeof(*data));
3180
3181         cnt = bnx2x_mcast_handle_pending_cmds_e2(bp, p);
3182
3183         /* If there are no more pending commands - clear SCHEDULED state */
3184         if (list_empty(&o->pending_cmds_head))
3185                 o->clear_sched(o);
3186
3187         /* The below may be true iff there was enough room in ramrod
3188          * data for all pending commands and for the current
3189          * command. Otherwise the current command would have been added
3190          * to the pending commands and p->mcast_list_len would have been
3191          * zeroed.
3192          */
3193         if (p->mcast_list_len > 0)
3194                 cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, cnt);
3195
3196         /* We've pulled out some MACs - update the total number of
3197          * outstanding.
3198          */
3199         o->total_pending_num -= cnt;
3200
3201         /* send a ramrod */
3202         WARN_ON(o->total_pending_num < 0);
3203         WARN_ON(cnt > o->max_cmd_len);
3204
3205         bnx2x_mcast_set_rdata_hdr_e2(bp, p, (u8)cnt);
3206
3207         /* Update a registry size if there are no more pending operations.
3208          *
3209          * We don't want to change the value of the registry size if there are
3210          * pending operations because we want it to always be equal to the
3211          * exact or the approximate number (see bnx2x_mcast_validate_e2()) of
3212          * set bins after the last requested operation in order to properly
3213          * evaluate the size of the next DEL/RESTORE operation.
3214          *
3215          * Note that we update the registry itself during command(s) handling
3216          * - see bnx2x_mcast_set_one_rule_e2(). That's because for 57712 we
3217          * aggregate multiple commands (ADD/DEL/RESTORE) into one ramrod but
3218          * with a limited amount of update commands (per MAC/bin) and we don't
3219          * know in this scope what the actual state of bins configuration is
3220          * going to be after this ramrod.
3221          */
3222         if (!o->total_pending_num)
3223                 bnx2x_mcast_refresh_registry_e2(bp, o);
3224
3225         /* If CLEAR_ONLY was requested - don't send a ramrod and clear
3226          * RAMROD_PENDING status immediately.
3227          */
3228         if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
3229                 raw->clear_pending(raw);
3230                 return 0;
3231         } else {
3232                 /* No need for an explicit memory barrier here as long as we
3233                  * ensure the ordering of writing to the SPQ element
3234                  * and updating of the SPQ producer which involves a memory
3235                  * read. If the memory read is removed we will have to put a
3236                  * full memory barrier there (inside bnx2x_sp_post()).
3237                  */
3238
3239                 /* Send a ramrod */
3240                 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_MULTICAST_RULES,
3241                                    raw->cid, U64_HI(raw->rdata_mapping),
3242                                    U64_LO(raw->rdata_mapping),
3243                                    ETH_CONNECTION_TYPE);
3244                 if (rc)
3245                         return rc;
3246
3247                 /* Ramrod completion is pending */
3248                 return 1;
3249         }
3250 }
3251
3252 static int bnx2x_mcast_validate_e1h(struct bnx2x *bp,
3253                                     struct bnx2x_mcast_ramrod_params *p,
3254                                     enum bnx2x_mcast_cmd cmd)
3255 {
3256         /* Mark, that there is a work to do */
3257         if ((cmd == BNX2X_MCAST_CMD_DEL) || (cmd == BNX2X_MCAST_CMD_RESTORE))
3258                 p->mcast_list_len = 1;
3259
3260         return 0;
3261 }
3262
3263 static void bnx2x_mcast_revert_e1h(struct bnx2x *bp,
3264                                        struct bnx2x_mcast_ramrod_params *p,
3265                                        int old_num_bins)
3266 {
3267         /* Do nothing */
3268 }
3269
3270 #define BNX2X_57711_SET_MC_FILTER(filter, bit) \
3271 do { \
3272         (filter)[(bit) >> 5] |= (1 << ((bit) & 0x1f)); \
3273 } while (0)
3274
3275 static inline void bnx2x_mcast_hdl_add_e1h(struct bnx2x *bp,
3276                                            struct bnx2x_mcast_obj *o,
3277                                            struct bnx2x_mcast_ramrod_params *p,
3278                                            u32 *mc_filter)
3279 {
3280         struct bnx2x_mcast_list_elem *mlist_pos;
3281         int bit;
3282
3283         list_for_each_entry(mlist_pos, &p->mcast_list, link) {
3284                 bit = bnx2x_mcast_bin_from_mac(mlist_pos->mac);
3285                 BNX2X_57711_SET_MC_FILTER(mc_filter, bit);
3286
3287                 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC, bin %d\n",
3288                    mlist_pos->mac, bit);
3289
3290                 /* bookkeeping... */
3291                 BIT_VEC64_SET_BIT(o->registry.aprox_match.vec,
3292                                   bit);
3293         }
3294 }
3295
3296 static inline void bnx2x_mcast_hdl_restore_e1h(struct bnx2x *bp,
3297         struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p,
3298         u32 *mc_filter)
3299 {
3300         int bit;
3301
3302         for (bit = bnx2x_mcast_get_next_bin(o, 0);
3303              bit >= 0;
3304              bit = bnx2x_mcast_get_next_bin(o, bit + 1)) {
3305                 BNX2X_57711_SET_MC_FILTER(mc_filter, bit);
3306                 DP(BNX2X_MSG_SP, "About to set bin %d\n", bit);
3307         }
3308 }
3309
3310 /* On 57711 we write the multicast MACs' approximate match
3311  * table by directly into the TSTORM's internal RAM. So we don't
3312  * really need to handle any tricks to make it work.
3313  */
3314 static int bnx2x_mcast_setup_e1h(struct bnx2x *bp,
3315                                  struct bnx2x_mcast_ramrod_params *p,
3316                                  enum bnx2x_mcast_cmd cmd)
3317 {
3318         int i;
3319         struct bnx2x_mcast_obj *o = p->mcast_obj;
3320         struct bnx2x_raw_obj *r = &o->raw;
3321
3322         /* If CLEAR_ONLY has been requested - clear the registry
3323          * and clear a pending bit.
3324          */
3325         if (!test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
3326                 u32 mc_filter[MC_HASH_SIZE] = {0};
3327
3328                 /* Set the multicast filter bits before writing it into
3329                  * the internal memory.
3330                  */
3331                 switch (cmd) {
3332                 case BNX2X_MCAST_CMD_ADD:
3333                         bnx2x_mcast_hdl_add_e1h(bp, o, p, mc_filter);
3334                         break;
3335
3336                 case BNX2X_MCAST_CMD_DEL:
3337                         DP(BNX2X_MSG_SP,
3338                            "Invalidating multicast MACs configuration\n");
3339
3340                         /* clear the registry */
3341                         memset(o->registry.aprox_match.vec, 0,
3342                                sizeof(o->registry.aprox_match.vec));
3343                         break;
3344
3345                 case BNX2X_MCAST_CMD_RESTORE:
3346                         bnx2x_mcast_hdl_restore_e1h(bp, o, p, mc_filter);
3347                         break;
3348
3349                 default:
3350                         BNX2X_ERR("Unknown command: %d\n", cmd);
3351                         return -EINVAL;
3352                 }
3353
3354                 /* Set the mcast filter in the internal memory */
3355                 for (i = 0; i < MC_HASH_SIZE; i++)
3356                         REG_WR(bp, MC_HASH_OFFSET(bp, i), mc_filter[i]);
3357         } else
3358                 /* clear the registry */
3359                 memset(o->registry.aprox_match.vec, 0,
3360                        sizeof(o->registry.aprox_match.vec));
3361
3362         /* We are done */
3363         r->clear_pending(r);
3364
3365         return 0;
3366 }
3367
3368 static int bnx2x_mcast_validate_e1(struct bnx2x *bp,
3369                                    struct bnx2x_mcast_ramrod_params *p,
3370                                    enum bnx2x_mcast_cmd cmd)
3371 {
3372         struct bnx2x_mcast_obj *o = p->mcast_obj;
3373         int reg_sz = o->get_registry_size(o);
3374
3375         switch (cmd) {
3376         /* DEL command deletes all currently configured MACs */
3377         case BNX2X_MCAST_CMD_DEL:
3378                 o->set_registry_size(o, 0);
3379                 /* Don't break */
3380
3381         /* RESTORE command will restore the entire multicast configuration */
3382         case BNX2X_MCAST_CMD_RESTORE:
3383                 p->mcast_list_len = reg_sz;
3384                   DP(BNX2X_MSG_SP, "Command %d, p->mcast_list_len=%d\n",
3385                                    cmd, p->mcast_list_len);
3386                 break;
3387
3388         case BNX2X_MCAST_CMD_ADD:
3389         case BNX2X_MCAST_CMD_CONT:
3390                 /* Multicast MACs on 57710 are configured as unicast MACs and
3391                  * there is only a limited number of CAM entries for that
3392                  * matter.
3393                  */
3394                 if (p->mcast_list_len > o->max_cmd_len) {
3395                         BNX2X_ERR("Can't configure more than %d multicast MACs on 57710\n",
3396                                   o->max_cmd_len);
3397                         return -EINVAL;
3398                 }
3399                 /* Every configured MAC should be cleared if DEL command is
3400                  * called. Only the last ADD command is relevant as long as
3401                  * every ADD commands overrides the previous configuration.
3402                  */
3403                 DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len);
3404                 if (p->mcast_list_len > 0)
3405                         o->set_registry_size(o, p->mcast_list_len);
3406
3407                 break;
3408
3409         default:
3410                 BNX2X_ERR("Unknown command: %d\n", cmd);
3411                 return -EINVAL;
3412         }
3413
3414         /* We want to ensure that commands are executed one by one for 57710.
3415          * Therefore each none-empty command will consume o->max_cmd_len.
3416          */
3417         if (p->mcast_list_len)
3418                 o->total_pending_num += o->max_cmd_len;
3419
3420         return 0;
3421 }
3422
3423 static void bnx2x_mcast_revert_e1(struct bnx2x *bp,
3424                                       struct bnx2x_mcast_ramrod_params *p,
3425                                       int old_num_macs)
3426 {
3427         struct bnx2x_mcast_obj *o = p->mcast_obj;
3428
3429         o->set_registry_size(o, old_num_macs);
3430
3431         /* If current command hasn't been handled yet and we are
3432          * here means that it's meant to be dropped and we have to
3433          * update the number of outstanding MACs accordingly.
3434          */
3435         if (p->mcast_list_len)
3436                 o->total_pending_num -= o->max_cmd_len;
3437 }
3438
3439 static void bnx2x_mcast_set_one_rule_e1(struct bnx2x *bp,
3440                                         struct bnx2x_mcast_obj *o, int idx,
3441                                         union bnx2x_mcast_config_data *cfg_data,
3442                                         enum bnx2x_mcast_cmd cmd)
3443 {
3444         struct bnx2x_raw_obj *r = &o->raw;
3445         struct mac_configuration_cmd *data =
3446                 (struct mac_configuration_cmd *)(r->rdata);
3447
3448         /* copy mac */
3449         if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE)) {
3450                 bnx2x_set_fw_mac_addr(&data->config_table[idx].msb_mac_addr,
3451                                       &data->config_table[idx].middle_mac_addr,
3452                                       &data->config_table[idx].lsb_mac_addr,
3453                                       cfg_data->mac);
3454
3455                 data->config_table[idx].vlan_id = 0;
3456                 data->config_table[idx].pf_id = r->func_id;
3457                 data->config_table[idx].clients_bit_vector =
3458                         cpu_to_le32(1 << r->cl_id);
3459
3460                 SET_FLAG(data->config_table[idx].flags,
3461                          MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
3462                          T_ETH_MAC_COMMAND_SET);
3463         }
3464 }
3465
3466 /**
3467  * bnx2x_mcast_set_rdata_hdr_e1  - set header values in mac_configuration_cmd
3468  *
3469  * @bp:         device handle
3470  * @p:
3471  * @len:        number of rules to handle
3472  */
3473 static inline void bnx2x_mcast_set_rdata_hdr_e1(struct bnx2x *bp,
3474                                         struct bnx2x_mcast_ramrod_params *p,
3475                                         u8 len)
3476 {
3477         struct bnx2x_raw_obj *r = &p->mcast_obj->raw;
3478         struct mac_configuration_cmd *data =
3479                 (struct mac_configuration_cmd *)(r->rdata);
3480
3481         u8 offset = (CHIP_REV_IS_SLOW(bp) ?
3482                      BNX2X_MAX_EMUL_MULTI*(1 + r->func_id) :
3483                      BNX2X_MAX_MULTICAST*(1 + r->func_id));
3484
3485         data->hdr.offset = offset;
3486         data->hdr.client_id = cpu_to_le16(0xff);
3487         data->hdr.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
3488                                      (BNX2X_FILTER_MCAST_PENDING <<
3489                                       BNX2X_SWCID_SHIFT));
3490         data->hdr.length = len;
3491 }
3492
3493 /**
3494  * bnx2x_mcast_handle_restore_cmd_e1 - restore command for 57710
3495  *
3496  * @bp:         device handle
3497  * @o:
3498  * @start_idx:  index in the registry to start from
3499  * @rdata_idx:  index in the ramrod data to start from
3500  *
3501  * restore command for 57710 is like all other commands - always a stand alone
3502  * command - start_idx and rdata_idx will always be 0. This function will always
3503  * succeed.
3504  * returns -1 to comply with 57712 variant.
3505  */
3506 static inline int bnx2x_mcast_handle_restore_cmd_e1(
3507         struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_idx,
3508         int *rdata_idx)
3509 {
3510         struct bnx2x_mcast_mac_elem *elem;
3511         int i = 0;
3512         union bnx2x_mcast_config_data cfg_data = {NULL};
3513
3514         /* go through the registry and configure the MACs from it. */
3515         list_for_each_entry(elem, &o->registry.exact_match.macs, link) {
3516                 cfg_data.mac = &elem->mac[0];
3517                 o->set_one_rule(bp, o, i, &cfg_data, BNX2X_MCAST_CMD_RESTORE);
3518
3519                 i++;
3520
3521                   DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
3522                      cfg_data.mac);
3523         }
3524
3525         *rdata_idx = i;
3526
3527         return -1;
3528 }
3529
3530 static inline int bnx2x_mcast_handle_pending_cmds_e1(
3531         struct bnx2x *bp, struct bnx2x_mcast_ramrod_params *p)
3532 {
3533         struct bnx2x_pending_mcast_cmd *cmd_pos;
3534         struct bnx2x_mcast_mac_elem *pmac_pos;
3535         struct bnx2x_mcast_obj *o = p->mcast_obj;
3536         union bnx2x_mcast_config_data cfg_data = {NULL};
3537         int cnt = 0;
3538
3539         /* If nothing to be done - return */
3540         if (list_empty(&o->pending_cmds_head))
3541                 return 0;
3542
3543         /* Handle the first command */
3544         cmd_pos = list_first_entry(&o->pending_cmds_head,
3545                                    struct bnx2x_pending_mcast_cmd, link);
3546
3547         switch (cmd_pos->type) {
3548         case BNX2X_MCAST_CMD_ADD:
3549                 list_for_each_entry(pmac_pos, &cmd_pos->data.macs_head, link) {
3550                         cfg_data.mac = &pmac_pos->mac[0];
3551                         o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type);
3552
3553                         cnt++;
3554
3555                         DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
3556                            pmac_pos->mac);
3557                 }
3558                 break;
3559
3560         case BNX2X_MCAST_CMD_DEL:
3561                 cnt = cmd_pos->data.macs_num;
3562                 DP(BNX2X_MSG_SP, "About to delete %d multicast MACs\n", cnt);
3563                 break;
3564
3565         case BNX2X_MCAST_CMD_RESTORE:
3566                 o->hdl_restore(bp, o, 0, &cnt);
3567                 break;
3568
3569         default:
3570                 BNX2X_ERR("Unknown command: %d\n", cmd_pos->type);
3571                 return -EINVAL;
3572         }
3573
3574         list_del(&cmd_pos->link);
3575         kfree(cmd_pos);
3576
3577         return cnt;
3578 }
3579
3580 /**
3581  * bnx2x_get_fw_mac_addr - revert the bnx2x_set_fw_mac_addr().
3582  *
3583  * @fw_hi:
3584  * @fw_mid:
3585  * @fw_lo:
3586  * @mac:
3587  */
3588 static inline void bnx2x_get_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid,
3589                                          __le16 *fw_lo, u8 *mac)
3590 {
3591         mac[1] = ((u8 *)fw_hi)[0];
3592         mac[0] = ((u8 *)fw_hi)[1];
3593         mac[3] = ((u8 *)fw_mid)[0];
3594         mac[2] = ((u8 *)fw_mid)[1];
3595         mac[5] = ((u8 *)fw_lo)[0];
3596         mac[4] = ((u8 *)fw_lo)[1];
3597 }
3598
3599 /**
3600  * bnx2x_mcast_refresh_registry_e1 -
3601  *
3602  * @bp:         device handle
3603  * @cnt:
3604  *
3605  * Check the ramrod data first entry flag to see if it's a DELETE or ADD command
3606  * and update the registry correspondingly: if ADD - allocate a memory and add
3607  * the entries to the registry (list), if DELETE - clear the registry and free
3608  * the memory.
3609  */
3610 static inline int bnx2x_mcast_refresh_registry_e1(struct bnx2x *bp,
3611                                                   struct bnx2x_mcast_obj *o)
3612 {
3613         struct bnx2x_raw_obj *raw = &o->raw;
3614         struct bnx2x_mcast_mac_elem *elem;
3615         struct mac_configuration_cmd *data =
3616                         (struct mac_configuration_cmd *)(raw->rdata);
3617
3618         /* If first entry contains a SET bit - the command was ADD,
3619          * otherwise - DEL_ALL
3620          */
3621         if (GET_FLAG(data->config_table[0].flags,
3622                         MAC_CONFIGURATION_ENTRY_ACTION_TYPE)) {
3623                 int i, len = data->hdr.length;
3624
3625                 /* Break if it was a RESTORE command */
3626                 if (!list_empty(&o->registry.exact_match.macs))
3627                         return 0;
3628
3629                 elem = kcalloc(len, sizeof(*elem), GFP_ATOMIC);
3630                 if (!elem) {
3631                         BNX2X_ERR("Failed to allocate registry memory\n");
3632                         return -ENOMEM;
3633                 }
3634
3635                 for (i = 0; i < len; i++, elem++) {
3636                         bnx2x_get_fw_mac_addr(
3637                                 &data->config_table[i].msb_mac_addr,
3638                                 &data->config_table[i].middle_mac_addr,
3639                                 &data->config_table[i].lsb_mac_addr,
3640                                 elem->mac);
3641                         DP(BNX2X_MSG_SP, "Adding registry entry for [%pM]\n",
3642                            elem->mac);
3643                         list_add_tail(&elem->link,
3644                                       &o->registry.exact_match.macs);
3645                 }
3646         } else {
3647                 elem = list_first_entry(&o->registry.exact_match.macs,
3648                                         struct bnx2x_mcast_mac_elem, link);
3649                 DP(BNX2X_MSG_SP, "Deleting a registry\n");
3650                 kfree(elem);
3651                 INIT_LIST_HEAD(&o->registry.exact_match.macs);
3652         }
3653
3654         return 0;
3655 }
3656
3657 static int bnx2x_mcast_setup_e1(struct bnx2x *bp,
3658                                 struct bnx2x_mcast_ramrod_params *p,
3659                                 enum bnx2x_mcast_cmd cmd)
3660 {
3661         struct bnx2x_mcast_obj *o = p->mcast_obj;
3662         struct bnx2x_raw_obj *raw = &o->raw;
3663         struct mac_configuration_cmd *data =
3664                 (struct mac_configuration_cmd *)(raw->rdata);
3665         int cnt = 0, i, rc;
3666
3667         /* Reset the ramrod data buffer */
3668         memset(data, 0, sizeof(*data));
3669
3670         /* First set all entries as invalid */
3671         for (i = 0; i < o->max_cmd_len ; i++)
3672                 SET_FLAG(data->config_table[i].flags,
3673                          MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
3674                          T_ETH_MAC_COMMAND_INVALIDATE);
3675
3676         /* Handle pending commands first */
3677         cnt = bnx2x_mcast_handle_pending_cmds_e1(bp, p);
3678
3679         /* If there are no more pending commands - clear SCHEDULED state */
3680         if (list_empty(&o->pending_cmds_head))
3681                 o->clear_sched(o);
3682
3683         /* The below may be true iff there were no pending commands */
3684         if (!cnt)
3685                 cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, 0);
3686
3687         /* For 57710 every command has o->max_cmd_len length to ensure that
3688          * commands are done one at a time.
3689          */
3690         o->total_pending_num -= o->max_cmd_len;
3691
3692         /* send a ramrod */
3693
3694         WARN_ON(cnt > o->max_cmd_len);
3695
3696         /* Set ramrod header (in particular, a number of entries to update) */
3697         bnx2x_mcast_set_rdata_hdr_e1(bp, p, (u8)cnt);
3698
3699         /* update a registry: we need the registry contents to be always up
3700          * to date in order to be able to execute a RESTORE opcode. Here
3701          * we use the fact that for 57710 we sent one command at a time
3702          * hence we may take the registry update out of the command handling
3703          * and do it in a simpler way here.
3704          */
3705         rc = bnx2x_mcast_refresh_registry_e1(bp, o);
3706         if (rc)
3707                 return rc;
3708
3709         /* If CLEAR_ONLY was requested - don't send a ramrod and clear
3710          * RAMROD_PENDING status immediately.
3711          */
3712         if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
3713                 raw->clear_pending(raw);
3714                 return 0;
3715         } else {
3716                 /* No need for an explicit memory barrier here as long as we
3717                  * ensure the ordering of writing to the SPQ element
3718                  * and updating of the SPQ producer which involves a memory
3719                  * read. If the memory read is removed we will have to put a
3720                  * full memory barrier there (inside bnx2x_sp_post()).
3721                  */
3722
3723                 /* Send a ramrod */
3724                 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, raw->cid,
3725                                    U64_HI(raw->rdata_mapping),
3726                                    U64_LO(raw->rdata_mapping),
3727                                    ETH_CONNECTION_TYPE);
3728                 if (rc)
3729                         return rc;
3730
3731                 /* Ramrod completion is pending */
3732                 return 1;
3733         }
3734 }
3735
3736 static int bnx2x_mcast_get_registry_size_exact(struct bnx2x_mcast_obj *o)
3737 {
3738         return o->registry.exact_match.num_macs_set;
3739 }
3740
3741 static int bnx2x_mcast_get_registry_size_aprox(struct bnx2x_mcast_obj *o)
3742 {
3743         return o->registry.aprox_match.num_bins_set;
3744 }
3745
3746 static void bnx2x_mcast_set_registry_size_exact(struct bnx2x_mcast_obj *o,
3747                                                 int n)
3748 {
3749         o->registry.exact_match.num_macs_set = n;
3750 }
3751
3752 static void bnx2x_mcast_set_registry_size_aprox(struct bnx2x_mcast_obj *o,
3753                                                 int n)
3754 {
3755         o->registry.aprox_match.num_bins_set = n;
3756 }
3757
3758 int bnx2x_config_mcast(struct bnx2x *bp,
3759                        struct bnx2x_mcast_ramrod_params *p,
3760                        enum bnx2x_mcast_cmd cmd)
3761 {
3762         struct bnx2x_mcast_obj *o = p->mcast_obj;
3763         struct bnx2x_raw_obj *r = &o->raw;
3764         int rc = 0, old_reg_size;
3765
3766         /* This is needed to recover number of currently configured mcast macs
3767          * in case of failure.
3768          */
3769         old_reg_size = o->get_registry_size(o);
3770
3771         /* Do some calculations and checks */
3772         rc = o->validate(bp, p, cmd);
3773         if (rc)
3774                 return rc;
3775
3776         /* Return if there is no work to do */
3777         if ((!p->mcast_list_len) && (!o->check_sched(o)))
3778                 return 0;
3779
3780         DP(BNX2X_MSG_SP, "o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d\n",
3781            o->total_pending_num, p->mcast_list_len, o->max_cmd_len);
3782
3783         /* Enqueue the current command to the pending list if we can't complete
3784          * it in the current iteration
3785          */
3786         if (r->check_pending(r) ||
3787             ((o->max_cmd_len > 0) && (o->total_pending_num > o->max_cmd_len))) {
3788                 rc = o->enqueue_cmd(bp, p->mcast_obj, p, cmd);
3789                 if (rc < 0)
3790                         goto error_exit1;
3791
3792                 /* As long as the current command is in a command list we
3793                  * don't need to handle it separately.
3794                  */
3795                 p->mcast_list_len = 0;
3796         }
3797
3798         if (!r->check_pending(r)) {
3799
3800                 /* Set 'pending' state */
3801                 r->set_pending(r);
3802
3803                 /* Configure the new classification in the chip */
3804                 rc = o->config_mcast(bp, p, cmd);
3805                 if (rc < 0)
3806                         goto error_exit2;
3807
3808                 /* Wait for a ramrod completion if was requested */
3809                 if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags))
3810                         rc = o->wait_comp(bp, o);
3811         }
3812
3813         return rc;
3814
3815 error_exit2:
3816         r->clear_pending(r);
3817
3818 error_exit1:
3819         o->revert(bp, p, old_reg_size);
3820
3821         return rc;
3822 }
3823
3824 static void bnx2x_mcast_clear_sched(struct bnx2x_mcast_obj *o)
3825 {
3826         smp_mb__before_atomic();
3827         clear_bit(o->sched_state, o->raw.pstate);
3828         smp_mb__after_atomic();
3829 }
3830
3831 static void bnx2x_mcast_set_sched(struct bnx2x_mcast_obj *o)
3832 {
3833         smp_mb__before_atomic();
3834         set_bit(o->sched_state, o->raw.pstate);
3835         smp_mb__after_atomic();
3836 }
3837
3838 static bool bnx2x_mcast_check_sched(struct bnx2x_mcast_obj *o)
3839 {
3840         return !!test_bit(o->sched_state, o->raw.pstate);
3841 }
3842
3843 static bool bnx2x_mcast_check_pending(struct bnx2x_mcast_obj *o)
3844 {
3845         return o->raw.check_pending(&o->raw) || o->check_sched(o);
3846 }
3847
3848 void bnx2x_init_mcast_obj(struct bnx2x *bp,
3849                           struct bnx2x_mcast_obj *mcast_obj,
3850                           u8 mcast_cl_id, u32 mcast_cid, u8 func_id,
3851                           u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
3852                           int state, unsigned long *pstate, bnx2x_obj_type type)
3853 {
3854         memset(mcast_obj, 0, sizeof(*mcast_obj));
3855
3856         bnx2x_init_raw_obj(&mcast_obj->raw, mcast_cl_id, mcast_cid, func_id,
3857                            rdata, rdata_mapping, state, pstate, type);
3858
3859         mcast_obj->engine_id = engine_id;
3860
3861         INIT_LIST_HEAD(&mcast_obj->pending_cmds_head);
3862
3863         mcast_obj->sched_state = BNX2X_FILTER_MCAST_SCHED;
3864         mcast_obj->check_sched = bnx2x_mcast_check_sched;
3865         mcast_obj->set_sched = bnx2x_mcast_set_sched;
3866         mcast_obj->clear_sched = bnx2x_mcast_clear_sched;
3867
3868         if (CHIP_IS_E1(bp)) {
3869                 mcast_obj->config_mcast      = bnx2x_mcast_setup_e1;
3870                 mcast_obj->enqueue_cmd       = bnx2x_mcast_enqueue_cmd;
3871                 mcast_obj->hdl_restore       =
3872                         bnx2x_mcast_handle_restore_cmd_e1;
3873                 mcast_obj->check_pending     = bnx2x_mcast_check_pending;
3874
3875                 if (CHIP_REV_IS_SLOW(bp))
3876                         mcast_obj->max_cmd_len = BNX2X_MAX_EMUL_MULTI;
3877                 else
3878                         mcast_obj->max_cmd_len = BNX2X_MAX_MULTICAST;
3879
3880                 mcast_obj->wait_comp         = bnx2x_mcast_wait;
3881                 mcast_obj->set_one_rule      = bnx2x_mcast_set_one_rule_e1;
3882                 mcast_obj->validate          = bnx2x_mcast_validate_e1;
3883                 mcast_obj->revert            = bnx2x_mcast_revert_e1;
3884                 mcast_obj->get_registry_size =
3885                         bnx2x_mcast_get_registry_size_exact;
3886                 mcast_obj->set_registry_size =
3887                         bnx2x_mcast_set_registry_size_exact;
3888
3889                 /* 57710 is the only chip that uses the exact match for mcast
3890                  * at the moment.
3891                  */
3892                 INIT_LIST_HEAD(&mcast_obj->registry.exact_match.macs);
3893
3894         } else if (CHIP_IS_E1H(bp)) {
3895                 mcast_obj->config_mcast  = bnx2x_mcast_setup_e1h;
3896                 mcast_obj->enqueue_cmd   = NULL;
3897                 mcast_obj->hdl_restore   = NULL;
3898                 mcast_obj->check_pending = bnx2x_mcast_check_pending;
3899
3900                 /* 57711 doesn't send a ramrod, so it has unlimited credit
3901                  * for one command.
3902                  */
3903                 mcast_obj->max_cmd_len       = -1;
3904                 mcast_obj->wait_comp         = bnx2x_mcast_wait;
3905                 mcast_obj->set_one_rule      = NULL;
3906                 mcast_obj->validate          = bnx2x_mcast_validate_e1h;
3907                 mcast_obj->revert            = bnx2x_mcast_revert_e1h;
3908                 mcast_obj->get_registry_size =
3909                         bnx2x_mcast_get_registry_size_aprox;
3910                 mcast_obj->set_registry_size =
3911                         bnx2x_mcast_set_registry_size_aprox;
3912         } else {
3913                 mcast_obj->config_mcast      = bnx2x_mcast_setup_e2;
3914                 mcast_obj->enqueue_cmd       = bnx2x_mcast_enqueue_cmd;
3915                 mcast_obj->hdl_restore       =
3916                         bnx2x_mcast_handle_restore_cmd_e2;
3917                 mcast_obj->check_pending     = bnx2x_mcast_check_pending;
3918                 /* TODO: There should be a proper HSI define for this number!!!
3919                  */
3920                 mcast_obj->max_cmd_len       = 16;
3921                 mcast_obj->wait_comp         = bnx2x_mcast_wait;
3922                 mcast_obj->set_one_rule      = bnx2x_mcast_set_one_rule_e2;
3923                 mcast_obj->validate          = bnx2x_mcast_validate_e2;
3924                 mcast_obj->revert            = bnx2x_mcast_revert_e2;
3925                 mcast_obj->get_registry_size =
3926                         bnx2x_mcast_get_registry_size_aprox;
3927                 mcast_obj->set_registry_size =
3928                         bnx2x_mcast_set_registry_size_aprox;
3929         }
3930 }
3931
3932 /*************************** Credit handling **********************************/
3933
3934 /**
3935  * atomic_add_ifless - add if the result is less than a given value.
3936  *
3937  * @v:  pointer of type atomic_t
3938  * @a:  the amount to add to v...
3939  * @u:  ...if (v + a) is less than u.
3940  *
3941  * returns true if (v + a) was less than u, and false otherwise.
3942  *
3943  */
3944 static inline bool __atomic_add_ifless(atomic_t *v, int a, int u)
3945 {
3946         int c, old;
3947
3948         c = atomic_read(v);
3949         for (;;) {
3950                 if (unlikely(c + a >= u))
3951                         return false;
3952
3953                 old = atomic_cmpxchg((v), c, c + a);
3954                 if (likely(old == c))
3955                         break;
3956                 c = old;
3957         }
3958
3959         return true;
3960 }
3961
3962 /**
3963  * atomic_dec_ifmoe - dec if the result is more or equal than a given value.
3964  *
3965  * @v:  pointer of type atomic_t
3966  * @a:  the amount to dec from v...
3967  * @u:  ...if (v - a) is more or equal than u.
3968  *
3969  * returns true if (v - a) was more or equal than u, and false
3970  * otherwise.
3971  */
3972 static inline bool __atomic_dec_ifmoe(atomic_t *v, int a, int u)
3973 {
3974         int c, old;
3975
3976         c = atomic_read(v);
3977         for (;;) {
3978                 if (unlikely(c - a < u))
3979                         return false;
3980
3981                 old = atomic_cmpxchg((v), c, c - a);
3982                 if (likely(old == c))
3983                         break;
3984                 c = old;
3985         }
3986
3987         return true;
3988 }
3989
3990 static bool bnx2x_credit_pool_get(struct bnx2x_credit_pool_obj *o, int cnt)
3991 {
3992         bool rc;
3993
3994         smp_mb();
3995         rc = __atomic_dec_ifmoe(&o->credit, cnt, 0);
3996         smp_mb();
3997
3998         return rc;
3999 }
4000
4001 static bool bnx2x_credit_pool_put(struct bnx2x_credit_pool_obj *o, int cnt)
4002 {
4003         bool rc;
4004
4005         smp_mb();
4006
4007         /* Don't let to refill if credit + cnt > pool_sz */
4008         rc = __atomic_add_ifless(&o->credit, cnt, o->pool_sz + 1);
4009
4010         smp_mb();
4011
4012         return rc;
4013 }
4014
4015 static int bnx2x_credit_pool_check(struct bnx2x_credit_pool_obj *o)
4016 {
4017         int cur_credit;
4018
4019         smp_mb();
4020         cur_credit = atomic_read(&o->credit);
4021
4022         return cur_credit;
4023 }
4024
4025 static bool bnx2x_credit_pool_always_true(struct bnx2x_credit_pool_obj *o,
4026                                           int cnt)
4027 {
4028         return true;
4029 }
4030
4031 static bool bnx2x_credit_pool_get_entry(
4032         struct bnx2x_credit_pool_obj *o,
4033         int *offset)
4034 {
4035         int idx, vec, i;
4036
4037         *offset = -1;
4038
4039         /* Find "internal cam-offset" then add to base for this object... */
4040         for (vec = 0; vec < BNX2X_POOL_VEC_SIZE; vec++) {
4041
4042                 /* Skip the current vector if there are no free entries in it */
4043                 if (!o->pool_mirror[vec])
4044                         continue;
4045
4046                 /* If we've got here we are going to find a free entry */
4047                 for (idx = vec * BIT_VEC64_ELEM_SZ, i = 0;
4048                       i < BIT_VEC64_ELEM_SZ; idx++, i++)
4049
4050                         if (BIT_VEC64_TEST_BIT(o->pool_mirror, idx)) {
4051                                 /* Got one!! */
4052                                 BIT_VEC64_CLEAR_BIT(o->pool_mirror, idx);
4053                                 *offset = o->base_pool_offset + idx;
4054                                 return true;
4055                         }
4056         }
4057
4058         return false;
4059 }
4060
4061 static bool bnx2x_credit_pool_put_entry(
4062         struct bnx2x_credit_pool_obj *o,
4063         int offset)
4064 {
4065         if (offset < o->base_pool_offset)
4066                 return false;
4067
4068         offset -= o->base_pool_offset;
4069
4070         if (offset >= o->pool_sz)
4071                 return false;
4072
4073         /* Return the entry to the pool */
4074         BIT_VEC64_SET_BIT(o->pool_mirror, offset);
4075
4076         return true;
4077 }
4078
4079 static bool bnx2x_credit_pool_put_entry_always_true(
4080         struct bnx2x_credit_pool_obj *o,
4081         int offset)
4082 {
4083         return true;
4084 }
4085
4086 static bool bnx2x_credit_pool_get_entry_always_true(
4087         struct bnx2x_credit_pool_obj *o,
4088         int *offset)
4089 {
4090         *offset = -1;
4091         return true;
4092 }
4093 /**
4094  * bnx2x_init_credit_pool - initialize credit pool internals.
4095  *
4096  * @p:
4097  * @base:       Base entry in the CAM to use.
4098  * @credit:     pool size.
4099  *
4100  * If base is negative no CAM entries handling will be performed.
4101  * If credit is negative pool operations will always succeed (unlimited pool).
4102  *
4103  */
4104 void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p,
4105                             int base, int credit)
4106 {
4107         /* Zero the object first */
4108         memset(p, 0, sizeof(*p));
4109
4110         /* Set the table to all 1s */
4111         memset(&p->pool_mirror, 0xff, sizeof(p->pool_mirror));
4112
4113         /* Init a pool as full */
4114         atomic_set(&p->credit, credit);
4115
4116         /* The total poll size */
4117         p->pool_sz = credit;
4118
4119         p->base_pool_offset = base;
4120
4121         /* Commit the change */
4122         smp_mb();
4123
4124         p->check = bnx2x_credit_pool_check;
4125
4126         /* if pool credit is negative - disable the checks */
4127         if (credit >= 0) {
4128                 p->put      = bnx2x_credit_pool_put;
4129                 p->get      = bnx2x_credit_pool_get;
4130                 p->put_entry = bnx2x_credit_pool_put_entry;
4131                 p->get_entry = bnx2x_credit_pool_get_entry;
4132         } else {
4133                 p->put      = bnx2x_credit_pool_always_true;
4134                 p->get      = bnx2x_credit_pool_always_true;
4135                 p->put_entry = bnx2x_credit_pool_put_entry_always_true;
4136                 p->get_entry = bnx2x_credit_pool_get_entry_always_true;
4137         }
4138
4139         /* If base is negative - disable entries handling */
4140         if (base < 0) {
4141                 p->put_entry = bnx2x_credit_pool_put_entry_always_true;
4142                 p->get_entry = bnx2x_credit_pool_get_entry_always_true;
4143         }
4144 }
4145
4146 void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
4147                                 struct bnx2x_credit_pool_obj *p, u8 func_id,
4148                                 u8 func_num)
4149 {
4150 /* TODO: this will be defined in consts as well... */
4151 #define BNX2X_CAM_SIZE_EMUL 5
4152
4153         int cam_sz;
4154
4155         if (CHIP_IS_E1(bp)) {
4156                 /* In E1, Multicast is saved in cam... */
4157                 if (!CHIP_REV_IS_SLOW(bp))
4158                         cam_sz = (MAX_MAC_CREDIT_E1 / 2) - BNX2X_MAX_MULTICAST;
4159                 else
4160                         cam_sz = BNX2X_CAM_SIZE_EMUL - BNX2X_MAX_EMUL_MULTI;
4161
4162                 bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz);
4163
4164         } else if (CHIP_IS_E1H(bp)) {
4165                 /* CAM credit is equaly divided between all active functions
4166                  * on the PORT!.
4167                  */
4168                 if ((func_num > 0)) {
4169                         if (!CHIP_REV_IS_SLOW(bp))
4170                                 cam_sz = (MAX_MAC_CREDIT_E1H / (2*func_num));
4171                         else
4172                                 cam_sz = BNX2X_CAM_SIZE_EMUL;
4173                         bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz);
4174                 } else {
4175                         /* this should never happen! Block MAC operations. */
4176                         bnx2x_init_credit_pool(p, 0, 0);
4177                 }
4178
4179         } else {
4180
4181                 /* CAM credit is equaly divided between all active functions
4182                  * on the PATH.
4183                  */
4184                 if (func_num > 0) {
4185                         if (!CHIP_REV_IS_SLOW(bp))
4186                                 cam_sz = PF_MAC_CREDIT_E2(bp, func_num);
4187                         else
4188                                 cam_sz = BNX2X_CAM_SIZE_EMUL;
4189
4190                         /* No need for CAM entries handling for 57712 and
4191                          * newer.
4192                          */
4193                         bnx2x_init_credit_pool(p, -1, cam_sz);
4194                 } else {
4195                         /* this should never happen! Block MAC operations. */
4196                         bnx2x_init_credit_pool(p, 0, 0);
4197                 }
4198         }
4199 }
4200
4201 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
4202                                  struct bnx2x_credit_pool_obj *p,
4203                                  u8 func_id,
4204                                  u8 func_num)
4205 {
4206         if (CHIP_IS_E1x(bp)) {
4207                 /* There is no VLAN credit in HW on 57710 and 57711 only
4208                  * MAC / MAC-VLAN can be set
4209                  */
4210                 bnx2x_init_credit_pool(p, 0, -1);
4211         } else {
4212                 /* CAM credit is equally divided between all active functions
4213                  * on the PATH.
4214                  */
4215                 if (func_num > 0) {
4216                         int credit = PF_VLAN_CREDIT_E2(bp, func_num);
4217
4218                         bnx2x_init_credit_pool(p, -1/*unused for E2*/, credit);
4219                 } else
4220                         /* this should never happen! Block VLAN operations. */
4221                         bnx2x_init_credit_pool(p, 0, 0);
4222         }
4223 }
4224
4225 /****************** RSS Configuration ******************/
4226 /**
4227  * bnx2x_debug_print_ind_table - prints the indirection table configuration.
4228  *
4229  * @bp:         driver handle
4230  * @p:          pointer to rss configuration
4231  *
4232  * Prints it when NETIF_MSG_IFUP debug level is configured.
4233  */
4234 static inline void bnx2x_debug_print_ind_table(struct bnx2x *bp,
4235                                         struct bnx2x_config_rss_params *p)
4236 {
4237         int i;
4238
4239         DP(BNX2X_MSG_SP, "Setting indirection table to:\n");
4240         DP(BNX2X_MSG_SP, "0x0000: ");
4241         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
4242                 DP_CONT(BNX2X_MSG_SP, "0x%02x ", p->ind_table[i]);
4243
4244                 /* Print 4 bytes in a line */
4245                 if ((i + 1 < T_ETH_INDIRECTION_TABLE_SIZE) &&
4246                     (((i + 1) & 0x3) == 0)) {
4247                         DP_CONT(BNX2X_MSG_SP, "\n");
4248                         DP(BNX2X_MSG_SP, "0x%04x: ", i + 1);
4249                 }
4250         }
4251
4252         DP_CONT(BNX2X_MSG_SP, "\n");
4253 }
4254
4255 /**
4256  * bnx2x_setup_rss - configure RSS
4257  *
4258  * @bp:         device handle
4259  * @p:          rss configuration
4260  *
4261  * sends on UPDATE ramrod for that matter.
4262  */
4263 static int bnx2x_setup_rss(struct bnx2x *bp,
4264                            struct bnx2x_config_rss_params *p)
4265 {
4266         struct bnx2x_rss_config_obj *o = p->rss_obj;
4267         struct bnx2x_raw_obj *r = &o->raw;
4268         struct eth_rss_update_ramrod_data *data =
4269                 (struct eth_rss_update_ramrod_data *)(r->rdata);
4270         u16 caps = 0;
4271         u8 rss_mode = 0;
4272         int rc;
4273
4274         memset(data, 0, sizeof(*data));
4275
4276         DP(BNX2X_MSG_SP, "Configuring RSS\n");
4277
4278         /* Set an echo field */
4279         data->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
4280                                  (r->state << BNX2X_SWCID_SHIFT));
4281
4282         /* RSS mode */
4283         if (test_bit(BNX2X_RSS_MODE_DISABLED, &p->rss_flags))
4284                 rss_mode = ETH_RSS_MODE_DISABLED;
4285         else if (test_bit(BNX2X_RSS_MODE_REGULAR, &p->rss_flags))
4286                 rss_mode = ETH_RSS_MODE_REGULAR;
4287
4288         data->rss_mode = rss_mode;
4289
4290         DP(BNX2X_MSG_SP, "rss_mode=%d\n", rss_mode);
4291
4292         /* RSS capabilities */
4293         if (test_bit(BNX2X_RSS_IPV4, &p->rss_flags))
4294                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY;
4295
4296         if (test_bit(BNX2X_RSS_IPV4_TCP, &p->rss_flags))
4297                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY;
4298
4299         if (test_bit(BNX2X_RSS_IPV4_UDP, &p->rss_flags))
4300                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY;
4301
4302         if (test_bit(BNX2X_RSS_IPV6, &p->rss_flags))
4303                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY;
4304
4305         if (test_bit(BNX2X_RSS_IPV6_TCP, &p->rss_flags))
4306                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY;
4307
4308         if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags))
4309                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
4310
4311         if (test_bit(BNX2X_RSS_IPV4_VXLAN, &p->rss_flags))
4312                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY;
4313
4314         if (test_bit(BNX2X_RSS_IPV6_VXLAN, &p->rss_flags))
4315                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY;
4316
4317         if (test_bit(BNX2X_RSS_TUNN_INNER_HDRS, &p->rss_flags))
4318                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY;
4319
4320         /* RSS keys */
4321         if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) {
4322                 u8 *dst = (u8 *)(data->rss_key) + sizeof(data->rss_key);
4323                 const u8 *src = (const u8 *)p->rss_key;
4324                 int i;
4325
4326                 /* Apparently, bnx2x reads this array in reverse order
4327                  * We need to byte swap rss_key to comply with Toeplitz specs.
4328                  */
4329                 for (i = 0; i < sizeof(data->rss_key); i++)
4330                         *--dst = *src++;
4331
4332                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY;
4333         }
4334
4335         data->capabilities = cpu_to_le16(caps);
4336
4337         /* Hashing mask */
4338         data->rss_result_mask = p->rss_result_mask;
4339
4340         /* RSS engine ID */
4341         data->rss_engine_id = o->engine_id;
4342
4343         DP(BNX2X_MSG_SP, "rss_engine_id=%d\n", data->rss_engine_id);
4344
4345         /* Indirection table */
4346         memcpy(data->indirection_table, p->ind_table,
4347                   T_ETH_INDIRECTION_TABLE_SIZE);
4348
4349         /* Remember the last configuration */
4350         memcpy(o->ind_table, p->ind_table, T_ETH_INDIRECTION_TABLE_SIZE);
4351
4352         /* Print the indirection table */
4353         if (netif_msg_ifup(bp))
4354                 bnx2x_debug_print_ind_table(bp, p);
4355
4356         /* No need for an explicit memory barrier here as long as we
4357          * ensure the ordering of writing to the SPQ element
4358          * and updating of the SPQ producer which involves a memory
4359          * read. If the memory read is removed we will have to put a
4360          * full memory barrier there (inside bnx2x_sp_post()).
4361          */
4362
4363         /* Send a ramrod */
4364         rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_RSS_UPDATE, r->cid,
4365                            U64_HI(r->rdata_mapping),
4366                            U64_LO(r->rdata_mapping),
4367                            ETH_CONNECTION_TYPE);
4368
4369         if (rc < 0)
4370                 return rc;
4371
4372         return 1;
4373 }
4374
4375 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
4376                              u8 *ind_table)
4377 {
4378         memcpy(ind_table, rss_obj->ind_table, sizeof(rss_obj->ind_table));
4379 }
4380
4381 int bnx2x_config_rss(struct bnx2x *bp,
4382                      struct bnx2x_config_rss_params *p)
4383 {
4384         int rc;
4385         struct bnx2x_rss_config_obj *o = p->rss_obj;
4386         struct bnx2x_raw_obj *r = &o->raw;
4387
4388         /* Do nothing if only driver cleanup was requested */
4389         if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
4390                 DP(BNX2X_MSG_SP, "Not configuring RSS ramrod_flags=%lx\n",
4391                    p->ramrod_flags);
4392                 return 0;
4393         }
4394
4395         r->set_pending(r);
4396
4397         rc = o->config_rss(bp, p);
4398         if (rc < 0) {
4399                 r->clear_pending(r);
4400                 return rc;
4401         }
4402
4403         if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags))
4404                 rc = r->wait_comp(bp, r);
4405
4406         return rc;
4407 }
4408
4409 void bnx2x_init_rss_config_obj(struct bnx2x *bp,
4410                                struct bnx2x_rss_config_obj *rss_obj,
4411                                u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
4412                                void *rdata, dma_addr_t rdata_mapping,
4413                                int state, unsigned long *pstate,
4414                                bnx2x_obj_type type)
4415 {
4416         bnx2x_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata,
4417                            rdata_mapping, state, pstate, type);
4418
4419         rss_obj->engine_id  = engine_id;
4420         rss_obj->config_rss = bnx2x_setup_rss;
4421 }
4422
4423 /********************** Queue state object ***********************************/
4424
4425 /**
4426  * bnx2x_queue_state_change - perform Queue state change transition
4427  *
4428  * @bp:         device handle
4429  * @params:     parameters to perform the transition
4430  *
4431  * returns 0 in case of successfully completed transition, negative error
4432  * code in case of failure, positive (EBUSY) value if there is a completion
4433  * to that is still pending (possible only if RAMROD_COMP_WAIT is
4434  * not set in params->ramrod_flags for asynchronous commands).
4435  *
4436  */
4437 int bnx2x_queue_state_change(struct bnx2x *bp,
4438                              struct bnx2x_queue_state_params *params)
4439 {
4440         struct bnx2x_queue_sp_obj *o = params->q_obj;
4441         int rc, pending_bit;
4442         unsigned long *pending = &o->pending;
4443
4444         /* Check that the requested transition is legal */
4445         rc = o->check_transition(bp, o, params);
4446         if (rc) {
4447                 BNX2X_ERR("check transition returned an error. rc %d\n", rc);
4448                 return -EINVAL;
4449         }
4450
4451         /* Set "pending" bit */
4452         DP(BNX2X_MSG_SP, "pending bit was=%lx\n", o->pending);
4453         pending_bit = o->set_pending(o, params);
4454         DP(BNX2X_MSG_SP, "pending bit now=%lx\n", o->pending);
4455
4456         /* Don't send a command if only driver cleanup was requested */
4457         if (test_bit(RAMROD_DRV_CLR_ONLY, &params->ramrod_flags))
4458                 o->complete_cmd(bp, o, pending_bit);
4459         else {
4460                 /* Send a ramrod */
4461                 rc = o->send_cmd(bp, params);
4462                 if (rc) {
4463                         o->next_state = BNX2X_Q_STATE_MAX;
4464                         clear_bit(pending_bit, pending);
4465                         smp_mb__after_atomic();
4466                         return rc;
4467                 }
4468
4469                 if (test_bit(RAMROD_COMP_WAIT, &params->ramrod_flags)) {
4470                         rc = o->wait_comp(bp, o, pending_bit);
4471                         if (rc)
4472                                 return rc;
4473
4474                         return 0;
4475                 }
4476         }
4477
4478         return !!test_bit(pending_bit, pending);
4479 }
4480
4481 static int bnx2x_queue_set_pending(struct bnx2x_queue_sp_obj *obj,
4482                                    struct bnx2x_queue_state_params *params)
4483 {
4484         enum bnx2x_queue_cmd cmd = params->cmd, bit;
4485
4486         /* ACTIVATE and DEACTIVATE commands are implemented on top of
4487          * UPDATE command.
4488          */
4489         if ((cmd == BNX2X_Q_CMD_ACTIVATE) ||
4490             (cmd == BNX2X_Q_CMD_DEACTIVATE))
4491                 bit = BNX2X_Q_CMD_UPDATE;
4492         else
4493                 bit = cmd;
4494
4495         set_bit(bit, &obj->pending);
4496         return bit;
4497 }
4498
4499 static int bnx2x_queue_wait_comp(struct bnx2x *bp,
4500                                  struct bnx2x_queue_sp_obj *o,
4501                                  enum bnx2x_queue_cmd cmd)
4502 {
4503         return bnx2x_state_wait(bp, cmd, &o->pending);
4504 }
4505
4506 /**
4507  * bnx2x_queue_comp_cmd - complete the state change command.
4508  *
4509  * @bp:         device handle
4510  * @o:
4511  * @cmd:
4512  *
4513  * Checks that the arrived completion is expected.
4514  */
4515 static int bnx2x_queue_comp_cmd(struct bnx2x *bp,
4516                                 struct bnx2x_queue_sp_obj *o,
4517                                 enum bnx2x_queue_cmd cmd)
4518 {
4519         unsigned long cur_pending = o->pending;
4520
4521         if (!test_and_clear_bit(cmd, &cur_pending)) {
4522                 BNX2X_ERR("Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d\n",
4523                           cmd, o->cids[BNX2X_PRIMARY_CID_INDEX],
4524                           o->state, cur_pending, o->next_state);
4525                 return -EINVAL;
4526         }
4527
4528         if (o->next_tx_only >= o->max_cos)
4529                 /* >= because tx only must always be smaller than cos since the
4530                  * primary connection supports COS 0
4531                  */
4532                 BNX2X_ERR("illegal value for next tx_only: %d. max cos was %d",
4533                            o->next_tx_only, o->max_cos);
4534
4535         DP(BNX2X_MSG_SP,
4536            "Completing command %d for queue %d, setting state to %d\n",
4537            cmd, o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_state);
4538
4539         if (o->next_tx_only)  /* print num tx-only if any exist */
4540                 DP(BNX2X_MSG_SP, "primary cid %d: num tx-only cons %d\n",
4541                    o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_tx_only);
4542
4543         o->state = o->next_state;
4544         o->num_tx_only = o->next_tx_only;
4545         o->next_state = BNX2X_Q_STATE_MAX;
4546
4547         /* It's important that o->state and o->next_state are
4548          * updated before o->pending.
4549          */
4550         wmb();
4551
4552         clear_bit(cmd, &o->pending);
4553         smp_mb__after_atomic();
4554
4555         return 0;
4556 }
4557
4558 static void bnx2x_q_fill_setup_data_e2(struct bnx2x *bp,
4559                                 struct bnx2x_queue_state_params *cmd_params,
4560                                 struct client_init_ramrod_data *data)
4561 {
4562         struct bnx2x_queue_setup_params *params = &cmd_params->params.setup;
4563
4564         /* Rx data */
4565
4566         /* IPv6 TPA supported for E2 and above only */
4567         data->rx.tpa_en |= test_bit(BNX2X_Q_FLG_TPA_IPV6, &params->flags) *
4568                                 CLIENT_INIT_RX_DATA_TPA_EN_IPV6;
4569 }
4570
4571 static void bnx2x_q_fill_init_general_data(struct bnx2x *bp,
4572                                 struct bnx2x_queue_sp_obj *o,
4573                                 struct bnx2x_general_setup_params *params,
4574                                 struct client_init_general_data *gen_data,
4575                                 unsigned long *flags)
4576 {
4577         gen_data->client_id = o->cl_id;
4578
4579         if (test_bit(BNX2X_Q_FLG_STATS, flags)) {
4580                 gen_data->statistics_counter_id =
4581                                         params->stat_id;
4582                 gen_data->statistics_en_flg = 1;
4583                 gen_data->statistics_zero_flg =
4584                         test_bit(BNX2X_Q_FLG_ZERO_STATS, flags);
4585         } else
4586                 gen_data->statistics_counter_id =
4587                                         DISABLE_STATISTIC_COUNTER_ID_VALUE;
4588
4589         gen_data->is_fcoe_flg = test_bit(BNX2X_Q_FLG_FCOE, flags);
4590         gen_data->activate_flg = test_bit(BNX2X_Q_FLG_ACTIVE, flags);
4591         gen_data->sp_client_id = params->spcl_id;
4592         gen_data->mtu = cpu_to_le16(params->mtu);
4593         gen_data->func_id = o->func_id;
4594
4595         gen_data->cos = params->cos;
4596
4597         gen_data->traffic_type =
4598                 test_bit(BNX2X_Q_FLG_FCOE, flags) ?
4599                 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
4600
4601         gen_data->fp_hsi_ver = params->fp_hsi;
4602
4603         DP(BNX2X_MSG_SP, "flags: active %d, cos %d, stats en %d\n",
4604            gen_data->activate_flg, gen_data->cos, gen_data->statistics_en_flg);
4605 }
4606
4607 static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj *o,
4608                                 struct bnx2x_txq_setup_params *params,
4609                                 struct client_init_tx_data *tx_data,
4610                                 unsigned long *flags)
4611 {
4612         tx_data->enforce_security_flg =
4613                 test_bit(BNX2X_Q_FLG_TX_SEC, flags);
4614         tx_data->default_vlan =
4615                 cpu_to_le16(params->default_vlan);
4616         tx_data->default_vlan_flg =
4617                 test_bit(BNX2X_Q_FLG_DEF_VLAN, flags);
4618         tx_data->tx_switching_flg =
4619                 test_bit(BNX2X_Q_FLG_TX_SWITCH, flags);
4620         tx_data->anti_spoofing_flg =
4621                 test_bit(BNX2X_Q_FLG_ANTI_SPOOF, flags);
4622         tx_data->force_default_pri_flg =
4623                 test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags);
4624         tx_data->refuse_outband_vlan_flg =
4625                 test_bit(BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN, flags);
4626         tx_data->tunnel_lso_inc_ip_id =
4627                 test_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, flags);
4628         tx_data->tunnel_non_lso_pcsum_location =
4629                 test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, flags) ? CSUM_ON_PKT :
4630                                                             CSUM_ON_BD;
4631
4632         tx_data->tx_status_block_id = params->fw_sb_id;
4633         tx_data->tx_sb_index_number = params->sb_cq_index;
4634         tx_data->tss_leading_client_id = params->tss_leading_cl_id;
4635
4636         tx_data->tx_bd_page_base.lo =
4637                 cpu_to_le32(U64_LO(params->dscr_map));
4638         tx_data->tx_bd_page_base.hi =
4639                 cpu_to_le32(U64_HI(params->dscr_map));
4640
4641         /* Don't configure any Tx switching mode during queue SETUP */
4642         tx_data->state = 0;
4643 }
4644
4645 static void bnx2x_q_fill_init_pause_data(struct bnx2x_queue_sp_obj *o,
4646                                 struct rxq_pause_params *params,
4647                                 struct client_init_rx_data *rx_data)
4648 {
4649         /* flow control data */
4650         rx_data->cqe_pause_thr_low = cpu_to_le16(params->rcq_th_lo);
4651         rx_data->cqe_pause_thr_high = cpu_to_le16(params->rcq_th_hi);
4652         rx_data->bd_pause_thr_low = cpu_to_le16(params->bd_th_lo);
4653         rx_data->bd_pause_thr_high = cpu_to_le16(params->bd_th_hi);
4654         rx_data->sge_pause_thr_low = cpu_to_le16(params->sge_th_lo);
4655         rx_data->sge_pause_thr_high = cpu_to_le16(params->sge_th_hi);
4656         rx_data->rx_cos_mask = cpu_to_le16(params->pri_map);
4657 }
4658
4659 static void bnx2x_q_fill_init_rx_data(struct bnx2x_queue_sp_obj *o,
4660                                 struct bnx2x_rxq_setup_params *params,
4661                                 struct client_init_rx_data *rx_data,
4662                                 unsigned long *flags)
4663 {
4664         rx_data->tpa_en = test_bit(BNX2X_Q_FLG_TPA, flags) *
4665                                 CLIENT_INIT_RX_DATA_TPA_EN_IPV4;
4666         rx_data->tpa_en |= test_bit(BNX2X_Q_FLG_TPA_GRO, flags) *
4667                                 CLIENT_INIT_RX_DATA_TPA_MODE;
4668         rx_data->vmqueue_mode_en_flg = 0;
4669
4670         rx_data->cache_line_alignment_log_size =
4671                 params->cache_line_log;
4672         rx_data->enable_dynamic_hc =
4673                 test_bit(BNX2X_Q_FLG_DHC, flags);
4674         rx_data->max_sges_for_packet = params->max_sges_pkt;
4675         rx_data->client_qzone_id = params->cl_qzone_id;
4676         rx_data->max_agg_size = cpu_to_le16(params->tpa_agg_sz);
4677
4678         /* Always start in DROP_ALL mode */
4679         rx_data->state = cpu_to_le16(CLIENT_INIT_RX_DATA_UCAST_DROP_ALL |
4680                                      CLIENT_INIT_RX_DATA_MCAST_DROP_ALL);
4681
4682         /* We don't set drop flags */
4683         rx_data->drop_ip_cs_err_flg = 0;
4684         rx_data->drop_tcp_cs_err_flg = 0;
4685         rx_data->drop_ttl0_flg = 0;
4686         rx_data->drop_udp_cs_err_flg = 0;
4687         rx_data->inner_vlan_removal_enable_flg =
4688                 test_bit(BNX2X_Q_FLG_VLAN, flags);
4689         rx_data->outer_vlan_removal_enable_flg =
4690                 test_bit(BNX2X_Q_FLG_OV, flags);
4691         rx_data->status_block_id = params->fw_sb_id;
4692         rx_data->rx_sb_index_number = params->sb_cq_index;
4693         rx_data->max_tpa_queues = params->max_tpa_queues;
4694         rx_data->max_bytes_on_bd = cpu_to_le16(params->buf_sz);
4695         rx_data->sge_buff_size = cpu_to_le16(params->sge_buf_sz);
4696         rx_data->bd_page_base.lo =
4697                 cpu_to_le32(U64_LO(params->dscr_map));
4698         rx_data->bd_page_base.hi =
4699                 cpu_to_le32(U64_HI(params->dscr_map));
4700         rx_data->sge_page_base.lo =
4701                 cpu_to_le32(U64_LO(params->sge_map));
4702         rx_data->sge_page_base.hi =
4703                 cpu_to_le32(U64_HI(params->sge_map));
4704         rx_data->cqe_page_base.lo =
4705                 cpu_to_le32(U64_LO(params->rcq_map));
4706         rx_data->cqe_page_base.hi =
4707                 cpu_to_le32(U64_HI(params->rcq_map));
4708         rx_data->is_leading_rss = test_bit(BNX2X_Q_FLG_LEADING_RSS, flags);
4709
4710         if (test_bit(BNX2X_Q_FLG_MCAST, flags)) {
4711                 rx_data->approx_mcast_engine_id = params->mcast_engine_id;
4712                 rx_data->is_approx_mcast = 1;
4713         }
4714
4715         rx_data->rss_engine_id = params->rss_engine_id;
4716
4717         /* silent vlan removal */
4718         rx_data->silent_vlan_removal_flg =
4719                 test_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, flags);
4720         rx_data->silent_vlan_value =
4721                 cpu_to_le16(params->silent_removal_value);
4722         rx_data->silent_vlan_mask =
4723                 cpu_to_le16(params->silent_removal_mask);
4724 }
4725
4726 /* initialize the general, tx and rx parts of a queue object */
4727 static void bnx2x_q_fill_setup_data_cmn(struct bnx2x *bp,
4728                                 struct bnx2x_queue_state_params *cmd_params,
4729                                 struct client_init_ramrod_data *data)
4730 {
4731         bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj,
4732                                        &cmd_params->params.setup.gen_params,
4733                                        &data->general,
4734                                        &cmd_params->params.setup.flags);
4735
4736         bnx2x_q_fill_init_tx_data(cmd_params->q_obj,
4737                                   &cmd_params->params.setup.txq_params,
4738                                   &data->tx,
4739                                   &cmd_params->params.setup.flags);
4740
4741         bnx2x_q_fill_init_rx_data(cmd_params->q_obj,
4742                                   &cmd_params->params.setup.rxq_params,
4743                                   &data->rx,
4744                                   &cmd_params->params.setup.flags);
4745
4746         bnx2x_q_fill_init_pause_data(cmd_params->q_obj,
4747                                      &cmd_params->params.setup.pause_params,
4748                                      &data->rx);
4749 }
4750
4751 /* initialize the general and tx parts of a tx-only queue object */
4752 static void bnx2x_q_fill_setup_tx_only(struct bnx2x *bp,
4753                                 struct bnx2x_queue_state_params *cmd_params,
4754                                 struct tx_queue_init_ramrod_data *data)
4755 {
4756         bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj,
4757                                        &cmd_params->params.tx_only.gen_params,
4758                                        &data->general,
4759                                        &cmd_params->params.tx_only.flags);
4760
4761         bnx2x_q_fill_init_tx_data(cmd_params->q_obj,
4762                                   &cmd_params->params.tx_only.txq_params,
4763                                   &data->tx,
4764                                   &cmd_params->params.tx_only.flags);
4765
4766         DP(BNX2X_MSG_SP, "cid %d, tx bd page lo %x hi %x",
4767                          cmd_params->q_obj->cids[0],
4768                          data->tx.tx_bd_page_base.lo,
4769                          data->tx.tx_bd_page_base.hi);
4770 }
4771
4772 /**
4773  * bnx2x_q_init - init HW/FW queue
4774  *
4775  * @bp:         device handle
4776  * @params:
4777  *
4778  * HW/FW initial Queue configuration:
4779  *      - HC: Rx and Tx
4780  *      - CDU context validation
4781  *
4782  */
4783 static inline int bnx2x_q_init(struct bnx2x *bp,
4784                                struct bnx2x_queue_state_params *params)
4785 {
4786         struct bnx2x_queue_sp_obj *o = params->q_obj;
4787         struct bnx2x_queue_init_params *init = &params->params.init;
4788         u16 hc_usec;
4789         u8 cos;
4790
4791         /* Tx HC configuration */
4792         if (test_bit(BNX2X_Q_TYPE_HAS_TX, &o->type) &&
4793             test_bit(BNX2X_Q_FLG_HC, &init->tx.flags)) {
4794                 hc_usec = init->tx.hc_rate ? 1000000 / init->tx.hc_rate : 0;
4795
4796                 bnx2x_update_coalesce_sb_index(bp, init->tx.fw_sb_id,
4797                         init->tx.sb_cq_index,
4798                         !test_bit(BNX2X_Q_FLG_HC_EN, &init->tx.flags),
4799                         hc_usec);
4800         }
4801
4802         /* Rx HC configuration */
4803         if (test_bit(BNX2X_Q_TYPE_HAS_RX, &o->type) &&
4804             test_bit(BNX2X_Q_FLG_HC, &init->rx.flags)) {
4805                 hc_usec = init->rx.hc_rate ? 1000000 / init->rx.hc_rate : 0;
4806
4807                 bnx2x_update_coalesce_sb_index(bp, init->rx.fw_sb_id,
4808                         init->rx.sb_cq_index,
4809                         !test_bit(BNX2X_Q_FLG_HC_EN, &init->rx.flags),
4810                         hc_usec);
4811         }
4812
4813         /* Set CDU context validation values */
4814         for (cos = 0; cos < o->max_cos; cos++) {
4815                 DP(BNX2X_MSG_SP, "setting context validation. cid %d, cos %d\n",
4816                                  o->cids[cos], cos);
4817                 DP(BNX2X_MSG_SP, "context pointer %p\n", init->cxts[cos]);
4818                 bnx2x_set_ctx_validation(bp, init->cxts[cos], o->cids[cos]);
4819         }
4820
4821         /* As no ramrod is sent, complete the command immediately  */
4822         o->complete_cmd(bp, o, BNX2X_Q_CMD_INIT);
4823
4824         mmiowb();
4825         smp_mb();
4826
4827         return 0;
4828 }
4829
4830 static inline int bnx2x_q_send_setup_e1x(struct bnx2x *bp,
4831                                         struct bnx2x_queue_state_params *params)
4832 {
4833         struct bnx2x_queue_sp_obj *o = params->q_obj;
4834         struct client_init_ramrod_data *rdata =
4835                 (struct client_init_ramrod_data *)o->rdata;
4836         dma_addr_t data_mapping = o->rdata_mapping;
4837         int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
4838
4839         /* Clear the ramrod data */
4840         memset(rdata, 0, sizeof(*rdata));
4841
4842         /* Fill the ramrod data */
4843         bnx2x_q_fill_setup_data_cmn(bp, params, rdata);
4844
4845         /* No need for an explicit memory barrier here as long as we
4846          * ensure the ordering of writing to the SPQ element
4847          * and updating of the SPQ producer which involves a memory
4848          * read. If the memory read is removed we will have to put a
4849          * full memory barrier there (inside bnx2x_sp_post()).
4850          */
4851         return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX],
4852                              U64_HI(data_mapping),
4853                              U64_LO(data_mapping), ETH_CONNECTION_TYPE);
4854 }
4855
4856 static inline int bnx2x_q_send_setup_e2(struct bnx2x *bp,
4857                                         struct bnx2x_queue_state_params *params)
4858 {
4859         struct bnx2x_queue_sp_obj *o = params->q_obj;
4860         struct client_init_ramrod_data *rdata =
4861                 (struct client_init_ramrod_data *)o->rdata;
4862         dma_addr_t data_mapping = o->rdata_mapping;
4863         int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
4864
4865         /* Clear the ramrod data */
4866         memset(rdata, 0, sizeof(*rdata));
4867
4868         /* Fill the ramrod data */
4869         bnx2x_q_fill_setup_data_cmn(bp, params, rdata);
4870         bnx2x_q_fill_setup_data_e2(bp, params, rdata);
4871
4872         /* No need for an explicit memory barrier here as long as we
4873          * ensure the ordering of writing to the SPQ element
4874          * and updating of the SPQ producer which involves a memory
4875          * read. If the memory read is removed we will have to put a
4876          * full memory barrier there (inside bnx2x_sp_post()).
4877          */
4878         return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX],
4879                              U64_HI(data_mapping),
4880                              U64_LO(data_mapping), ETH_CONNECTION_TYPE);
4881 }
4882
4883 static inline int bnx2x_q_send_setup_tx_only(struct bnx2x *bp,
4884                                   struct bnx2x_queue_state_params *params)
4885 {
4886         struct bnx2x_queue_sp_obj *o = params->q_obj;
4887         struct tx_queue_init_ramrod_data *rdata =
4888                 (struct tx_queue_init_ramrod_data *)o->rdata;
4889         dma_addr_t data_mapping = o->rdata_mapping;
4890         int ramrod = RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP;
4891         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
4892                 &params->params.tx_only;
4893         u8 cid_index = tx_only_params->cid_index;
4894
4895         if (cid_index >= o->max_cos) {
4896                 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
4897                           o->cl_id, cid_index);
4898                 return -EINVAL;
4899         }
4900
4901         DP(BNX2X_MSG_SP, "parameters received: cos: %d sp-id: %d\n",
4902                          tx_only_params->gen_params.cos,
4903                          tx_only_params->gen_params.spcl_id);
4904
4905         /* Clear the ramrod data */
4906         memset(rdata, 0, sizeof(*rdata));
4907
4908         /* Fill the ramrod data */
4909         bnx2x_q_fill_setup_tx_only(bp, params, rdata);
4910
4911         DP(BNX2X_MSG_SP, "sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d\n",
4912                          o->cids[cid_index], rdata->general.client_id,
4913                          rdata->general.sp_client_id, rdata->general.cos);
4914
4915         /* No need for an explicit memory barrier here as long as we
4916          * ensure the ordering of writing to the SPQ element
4917          * and updating of the SPQ producer which involves a memory
4918          * read. If the memory read is removed we will have to put a
4919          * full memory barrier there (inside bnx2x_sp_post()).
4920          */
4921         return bnx2x_sp_post(bp, ramrod, o->cids[cid_index],
4922                              U64_HI(data_mapping),
4923                              U64_LO(data_mapping), ETH_CONNECTION_TYPE);
4924 }
4925
4926 static void bnx2x_q_fill_update_data(struct bnx2x *bp,
4927                                      struct bnx2x_queue_sp_obj *obj,
4928                                      struct bnx2x_queue_update_params *params,
4929                                      struct client_update_ramrod_data *data)
4930 {
4931         /* Client ID of the client to update */
4932         data->client_id = obj->cl_id;
4933
4934         /* Function ID of the client to update */
4935         data->func_id = obj->func_id;
4936
4937         /* Default VLAN value */
4938         data->default_vlan = cpu_to_le16(params->def_vlan);
4939
4940         /* Inner VLAN stripping */
4941         data->inner_vlan_removal_enable_flg =
4942                 test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM, &params->update_flags);
4943         data->inner_vlan_removal_change_flg =
4944                 test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
4945                          &params->update_flags);
4946
4947         /* Outer VLAN stripping */
4948         data->outer_vlan_removal_enable_flg =
4949                 test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM, &params->update_flags);
4950         data->outer_vlan_removal_change_flg =
4951                 test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
4952                          &params->update_flags);
4953
4954         /* Drop packets that have source MAC that doesn't belong to this
4955          * Queue.
4956          */
4957         data->anti_spoofing_enable_flg =
4958                 test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF, &params->update_flags);
4959         data->anti_spoofing_change_flg =
4960                 test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, &params->update_flags);
4961
4962         /* Activate/Deactivate */
4963         data->activate_flg =
4964                 test_bit(BNX2X_Q_UPDATE_ACTIVATE, &params->update_flags);
4965         data->activate_change_flg =
4966                 test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &params->update_flags);
4967
4968         /* Enable default VLAN */
4969         data->default_vlan_enable_flg =
4970                 test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, &params->update_flags);
4971         data->default_vlan_change_flg =
4972                 test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
4973                          &params->update_flags);
4974
4975         /* silent vlan removal */
4976         data->silent_vlan_change_flg =
4977                 test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4978                          &params->update_flags);
4979         data->silent_vlan_removal_flg =
4980                 test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, &params->update_flags);
4981         data->silent_vlan_value = cpu_to_le16(params->silent_removal_value);
4982         data->silent_vlan_mask = cpu_to_le16(params->silent_removal_mask);
4983
4984         /* tx switching */
4985         data->tx_switching_flg =
4986                 test_bit(BNX2X_Q_UPDATE_TX_SWITCHING, &params->update_flags);
4987         data->tx_switching_change_flg =
4988                 test_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
4989                          &params->update_flags);
4990
4991         /* PTP */
4992         data->handle_ptp_pkts_flg =
4993                 test_bit(BNX2X_Q_UPDATE_PTP_PKTS, &params->update_flags);
4994         data->handle_ptp_pkts_change_flg =
4995                 test_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG, &params->update_flags);
4996 }
4997
4998 static inline int bnx2x_q_send_update(struct bnx2x *bp,
4999                                       struct bnx2x_queue_state_params *params)
5000 {
5001         struct bnx2x_queue_sp_obj *o = params->q_obj;
5002         struct client_update_ramrod_data *rdata =
5003                 (struct client_update_ramrod_data *)o->rdata;
5004         dma_addr_t data_mapping = o->rdata_mapping;
5005         struct bnx2x_queue_update_params *update_params =
5006                 &params->params.update;
5007         u8 cid_index = update_params->cid_index;
5008
5009         if (cid_index >= o->max_cos) {
5010                 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
5011                           o->cl_id, cid_index);
5012                 return -EINVAL;
5013         }
5014
5015         /* Clear the ramrod data */
5016         memset(rdata, 0, sizeof(*rdata));
5017
5018         /* Fill the ramrod data */
5019         bnx2x_q_fill_update_data(bp, o, update_params, rdata);
5020
5021         /* No need for an explicit memory barrier here as long as we
5022          * ensure the ordering of writing to the SPQ element
5023          * and updating of the SPQ producer which involves a memory
5024          * read. If the memory read is removed we will have to put a
5025          * full memory barrier there (inside bnx2x_sp_post()).
5026          */
5027         return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
5028                              o->cids[cid_index], U64_HI(data_mapping),
5029                              U64_LO(data_mapping), ETH_CONNECTION_TYPE);
5030 }
5031
5032 /**
5033  * bnx2x_q_send_deactivate - send DEACTIVATE command
5034  *
5035  * @bp:         device handle
5036  * @params:
5037  *
5038  * implemented using the UPDATE command.
5039  */
5040 static inline int bnx2x_q_send_deactivate(struct bnx2x *bp,
5041                                         struct bnx2x_queue_state_params *params)
5042 {
5043         struct bnx2x_queue_update_params *update = &params->params.update;
5044
5045         memset(update, 0, sizeof(*update));
5046
5047         __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags);
5048
5049         return bnx2x_q_send_update(bp, params);
5050 }
5051
5052 /**
5053  * bnx2x_q_send_activate - send ACTIVATE command
5054  *
5055  * @bp:         device handle
5056  * @params:
5057  *
5058  * implemented using the UPDATE command.
5059  */
5060 static inline int bnx2x_q_send_activate(struct bnx2x *bp,
5061                                         struct bnx2x_queue_state_params *params)
5062 {
5063         struct bnx2x_queue_update_params *update = &params->params.update;
5064
5065         memset(update, 0, sizeof(*update));
5066
5067         __set_bit(BNX2X_Q_UPDATE_ACTIVATE, &update->update_flags);
5068         __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags);
5069
5070         return bnx2x_q_send_update(bp, params);
5071 }
5072
5073 static void bnx2x_q_fill_update_tpa_data(struct bnx2x *bp,
5074                                 struct bnx2x_queue_sp_obj *obj,
5075                                 struct bnx2x_queue_update_tpa_params *params,
5076                                 struct tpa_update_ramrod_data *data)
5077 {
5078         data->client_id = obj->cl_id;
5079         data->complete_on_both_clients = params->complete_on_both_clients;
5080         data->dont_verify_rings_pause_thr_flg =
5081                 params->dont_verify_thr;
5082         data->max_agg_size = cpu_to_le16(params->max_agg_sz);
5083         data->max_sges_for_packet = params->max_sges_pkt;
5084         data->max_tpa_queues = params->max_tpa_queues;
5085         data->sge_buff_size = cpu_to_le16(params->sge_buff_sz);
5086         data->sge_page_base_hi = cpu_to_le32(U64_HI(params->sge_map));
5087         data->sge_page_base_lo = cpu_to_le32(U64_LO(params->sge_map));
5088         data->sge_pause_thr_high = cpu_to_le16(params->sge_pause_thr_high);
5089         data->sge_pause_thr_low = cpu_to_le16(params->sge_pause_thr_low);
5090         data->tpa_mode = params->tpa_mode;
5091         data->update_ipv4 = params->update_ipv4;
5092         data->update_ipv6 = params->update_ipv6;
5093 }
5094
5095 static inline int bnx2x_q_send_update_tpa(struct bnx2x *bp,
5096                                         struct bnx2x_queue_state_params *params)
5097 {
5098         struct bnx2x_queue_sp_obj *o = params->q_obj;
5099         struct tpa_update_ramrod_data *rdata =
5100                 (struct tpa_update_ramrod_data *)o->rdata;
5101         dma_addr_t data_mapping = o->rdata_mapping;
5102         struct bnx2x_queue_update_tpa_params *update_tpa_params =
5103                 &params->params.update_tpa;
5104         u16 type;
5105
5106         /* Clear the ramrod data */
5107         memset(rdata, 0, sizeof(*rdata));
5108
5109         /* Fill the ramrod data */
5110         bnx2x_q_fill_update_tpa_data(bp, o, update_tpa_params, rdata);
5111
5112         /* Add the function id inside the type, so that sp post function
5113          * doesn't automatically add the PF func-id, this is required
5114          * for operations done by PFs on behalf of their VFs
5115          */
5116         type = ETH_CONNECTION_TYPE |
5117                 ((o->func_id) << SPE_HDR_FUNCTION_ID_SHIFT);
5118
5119         /* No need for an explicit memory barrier here as long as we
5120          * ensure the ordering of writing to the SPQ element
5121          * and updating of the SPQ producer which involves a memory
5122          * read. If the memory read is removed we will have to put a
5123          * full memory barrier there (inside bnx2x_sp_post()).
5124          */
5125         return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TPA_UPDATE,
5126                              o->cids[BNX2X_PRIMARY_CID_INDEX],
5127                              U64_HI(data_mapping),
5128                              U64_LO(data_mapping), type);
5129 }
5130
5131 static inline int bnx2x_q_send_halt(struct bnx2x *bp,
5132                                     struct bnx2x_queue_state_params *params)
5133 {
5134         struct bnx2x_queue_sp_obj *o = params->q_obj;
5135
5136         return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT,
5137                              o->cids[BNX2X_PRIMARY_CID_INDEX], 0, o->cl_id,
5138                              ETH_CONNECTION_TYPE);
5139 }
5140
5141 static inline int bnx2x_q_send_cfc_del(struct bnx2x *bp,
5142                                        struct bnx2x_queue_state_params *params)
5143 {
5144         struct bnx2x_queue_sp_obj *o = params->q_obj;
5145         u8 cid_idx = params->params.cfc_del.cid_index;
5146
5147         if (cid_idx >= o->max_cos) {
5148                 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
5149                           o->cl_id, cid_idx);
5150                 return -EINVAL;
5151         }
5152
5153         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL,
5154                              o->cids[cid_idx], 0, 0, NONE_CONNECTION_TYPE);
5155 }
5156
5157 static inline int bnx2x_q_send_terminate(struct bnx2x *bp,
5158                                         struct bnx2x_queue_state_params *params)
5159 {
5160         struct bnx2x_queue_sp_obj *o = params->q_obj;
5161         u8 cid_index = params->params.terminate.cid_index;
5162
5163         if (cid_index >= o->max_cos) {
5164                 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
5165                           o->cl_id, cid_index);
5166                 return -EINVAL;
5167         }
5168
5169         return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE,
5170                              o->cids[cid_index], 0, 0, ETH_CONNECTION_TYPE);
5171 }
5172
5173 static inline int bnx2x_q_send_empty(struct bnx2x *bp,
5174                                      struct bnx2x_queue_state_params *params)
5175 {
5176         struct bnx2x_queue_sp_obj *o = params->q_obj;
5177
5178         return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_EMPTY,
5179                              o->cids[BNX2X_PRIMARY_CID_INDEX], 0, 0,
5180                              ETH_CONNECTION_TYPE);
5181 }
5182
5183 static inline int bnx2x_queue_send_cmd_cmn(struct bnx2x *bp,
5184                                         struct bnx2x_queue_state_params *params)
5185 {
5186         switch (params->cmd) {
5187         case BNX2X_Q_CMD_INIT:
5188                 return bnx2x_q_init(bp, params);
5189         case BNX2X_Q_CMD_SETUP_TX_ONLY:
5190                 return bnx2x_q_send_setup_tx_only(bp, params);
5191         case BNX2X_Q_CMD_DEACTIVATE:
5192                 return bnx2x_q_send_deactivate(bp, params);
5193         case BNX2X_Q_CMD_ACTIVATE:
5194                 return bnx2x_q_send_activate(bp, params);
5195         case BNX2X_Q_CMD_UPDATE:
5196                 return bnx2x_q_send_update(bp, params);
5197         case BNX2X_Q_CMD_UPDATE_TPA:
5198                 return bnx2x_q_send_update_tpa(bp, params);
5199         case BNX2X_Q_CMD_HALT:
5200                 return bnx2x_q_send_halt(bp, params);
5201         case BNX2X_Q_CMD_CFC_DEL:
5202                 return bnx2x_q_send_cfc_del(bp, params);
5203         case BNX2X_Q_CMD_TERMINATE:
5204                 return bnx2x_q_send_terminate(bp, params);
5205         case BNX2X_Q_CMD_EMPTY:
5206                 return bnx2x_q_send_empty(bp, params);
5207         default:
5208                 BNX2X_ERR("Unknown command: %d\n", params->cmd);
5209                 return -EINVAL;
5210         }
5211 }
5212
5213 static int bnx2x_queue_send_cmd_e1x(struct bnx2x *bp,
5214                                     struct bnx2x_queue_state_params *params)
5215 {
5216         switch (params->cmd) {
5217         case BNX2X_Q_CMD_SETUP:
5218                 return bnx2x_q_send_setup_e1x(bp, params);
5219         case BNX2X_Q_CMD_INIT:
5220         case BNX2X_Q_CMD_SETUP_TX_ONLY:
5221         case BNX2X_Q_CMD_DEACTIVATE:
5222         case BNX2X_Q_CMD_ACTIVATE:
5223         case BNX2X_Q_CMD_UPDATE:
5224         case BNX2X_Q_CMD_UPDATE_TPA:
5225         case BNX2X_Q_CMD_HALT:
5226         case BNX2X_Q_CMD_CFC_DEL:
5227         case BNX2X_Q_CMD_TERMINATE:
5228         case BNX2X_Q_CMD_EMPTY:
5229                 return bnx2x_queue_send_cmd_cmn(bp, params);
5230         default:
5231                 BNX2X_ERR("Unknown command: %d\n", params->cmd);
5232                 return -EINVAL;
5233         }
5234 }
5235
5236 static int bnx2x_queue_send_cmd_e2(struct bnx2x *bp,
5237                                    struct bnx2x_queue_state_params *params)
5238 {
5239         switch (params->cmd) {
5240         case BNX2X_Q_CMD_SETUP:
5241                 return bnx2x_q_send_setup_e2(bp, params);
5242         case BNX2X_Q_CMD_INIT:
5243         case BNX2X_Q_CMD_SETUP_TX_ONLY:
5244         case BNX2X_Q_CMD_DEACTIVATE:
5245         case BNX2X_Q_CMD_ACTIVATE:
5246         case BNX2X_Q_CMD_UPDATE:
5247         case BNX2X_Q_CMD_UPDATE_TPA:
5248         case BNX2X_Q_CMD_HALT:
5249         case BNX2X_Q_CMD_CFC_DEL:
5250         case BNX2X_Q_CMD_TERMINATE:
5251         case BNX2X_Q_CMD_EMPTY:
5252                 return bnx2x_queue_send_cmd_cmn(bp, params);
5253         default:
5254                 BNX2X_ERR("Unknown command: %d\n", params->cmd);
5255                 return -EINVAL;
5256         }
5257 }
5258
5259 /**
5260  * bnx2x_queue_chk_transition - check state machine of a regular Queue
5261  *
5262  * @bp:         device handle
5263  * @o:
5264  * @params:
5265  *
5266  * (not Forwarding)
5267  * It both checks if the requested command is legal in a current
5268  * state and, if it's legal, sets a `next_state' in the object
5269  * that will be used in the completion flow to set the `state'
5270  * of the object.
5271  *
5272  * returns 0 if a requested command is a legal transition,
5273  *         -EINVAL otherwise.
5274  */
5275 static int bnx2x_queue_chk_transition(struct bnx2x *bp,
5276                                       struct bnx2x_queue_sp_obj *o,
5277                                       struct bnx2x_queue_state_params *params)
5278 {
5279         enum bnx2x_q_state state = o->state, next_state = BNX2X_Q_STATE_MAX;
5280         enum bnx2x_queue_cmd cmd = params->cmd;
5281         struct bnx2x_queue_update_params *update_params =
5282                  &params->params.update;
5283         u8 next_tx_only = o->num_tx_only;
5284
5285         /* Forget all pending for completion commands if a driver only state
5286          * transition has been requested.
5287          */
5288         if (test_bit(RAMROD_DRV_CLR_ONLY, &params->ramrod_flags)) {
5289                 o->pending = 0;
5290                 o->next_state = BNX2X_Q_STATE_MAX;
5291         }
5292
5293         /* Don't allow a next state transition if we are in the middle of
5294          * the previous one.
5295          */
5296         if (o->pending) {
5297                 BNX2X_ERR("Blocking transition since pending was %lx\n",
5298                           o->pending);
5299                 return -EBUSY;
5300         }
5301
5302         switch (state) {
5303         case BNX2X_Q_STATE_RESET:
5304                 if (cmd == BNX2X_Q_CMD_INIT)
5305                         next_state = BNX2X_Q_STATE_INITIALIZED;
5306
5307                 break;
5308         case BNX2X_Q_STATE_INITIALIZED:
5309                 if (cmd == BNX2X_Q_CMD_SETUP) {
5310                         if (test_bit(BNX2X_Q_FLG_ACTIVE,
5311                                      &params->params.setup.flags))
5312                                 next_state = BNX2X_Q_STATE_ACTIVE;
5313                         else
5314                                 next_state = BNX2X_Q_STATE_INACTIVE;
5315                 }
5316
5317                 break;
5318         case BNX2X_Q_STATE_ACTIVE:
5319                 if (cmd == BNX2X_Q_CMD_DEACTIVATE)
5320                         next_state = BNX2X_Q_STATE_INACTIVE;
5321
5322                 else if ((cmd == BNX2X_Q_CMD_EMPTY) ||
5323                          (cmd == BNX2X_Q_CMD_UPDATE_TPA))
5324                         next_state = BNX2X_Q_STATE_ACTIVE;
5325
5326                 else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) {
5327                         next_state = BNX2X_Q_STATE_MULTI_COS;
5328                         next_tx_only = 1;
5329                 }
5330
5331                 else if (cmd == BNX2X_Q_CMD_HALT)
5332                         next_state = BNX2X_Q_STATE_STOPPED;
5333
5334                 else if (cmd == BNX2X_Q_CMD_UPDATE) {
5335                         /* If "active" state change is requested, update the
5336                          *  state accordingly.
5337                          */
5338                         if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG,
5339                                      &update_params->update_flags) &&
5340                             !test_bit(BNX2X_Q_UPDATE_ACTIVATE,
5341                                       &update_params->update_flags))
5342                                 next_state = BNX2X_Q_STATE_INACTIVE;
5343                         else
5344                                 next_state = BNX2X_Q_STATE_ACTIVE;
5345                 }
5346
5347                 break;
5348         case BNX2X_Q_STATE_MULTI_COS:
5349                 if (cmd == BNX2X_Q_CMD_TERMINATE)
5350                         next_state = BNX2X_Q_STATE_MCOS_TERMINATED;
5351
5352                 else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) {
5353                         next_state = BNX2X_Q_STATE_MULTI_COS;
5354                         next_tx_only = o->num_tx_only + 1;
5355                 }
5356
5357                 else if ((cmd == BNX2X_Q_CMD_EMPTY) ||
5358                          (cmd == BNX2X_Q_CMD_UPDATE_TPA))
5359                         next_state = BNX2X_Q_STATE_MULTI_COS;
5360
5361                 else if (cmd == BNX2X_Q_CMD_UPDATE) {
5362                         /* If "active" state change is requested, update the
5363                          *  state accordingly.
5364                          */
5365                         if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG,
5366                                      &update_params->update_flags) &&
5367                             !test_bit(BNX2X_Q_UPDATE_ACTIVATE,
5368                                       &update_params->update_flags))
5369                                 next_state = BNX2X_Q_STATE_INACTIVE;
5370                         else
5371                                 next_state = BNX2X_Q_STATE_MULTI_COS;
5372                 }
5373
5374                 break;
5375         case BNX2X_Q_STATE_MCOS_TERMINATED:
5376                 if (cmd == BNX2X_Q_CMD_CFC_DEL) {
5377                         next_tx_only = o->num_tx_only - 1;
5378                         if (next_tx_only == 0)
5379                                 next_state = BNX2X_Q_STATE_ACTIVE;
5380                         else
5381                                 next_state = BNX2X_Q_STATE_MULTI_COS;
5382                 }
5383
5384                 break;
5385         case BNX2X_Q_STATE_INACTIVE:
5386                 if (cmd == BNX2X_Q_CMD_ACTIVATE)
5387                         next_state = BNX2X_Q_STATE_ACTIVE;
5388
5389                 else if ((cmd == BNX2X_Q_CMD_EMPTY) ||
5390                          (cmd == BNX2X_Q_CMD_UPDATE_TPA))
5391                         next_state = BNX2X_Q_STATE_INACTIVE;
5392
5393                 else if (cmd == BNX2X_Q_CMD_HALT)
5394                         next_state = BNX2X_Q_STATE_STOPPED;
5395
5396                 else if (cmd == BNX2X_Q_CMD_UPDATE) {
5397                         /* If "active" state change is requested, update the
5398                          * state accordingly.
5399                          */
5400                         if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG,
5401                                      &update_params->update_flags) &&
5402                             test_bit(BNX2X_Q_UPDATE_ACTIVATE,
5403                                      &update_params->update_flags)){
5404                                 if (o->num_tx_only == 0)
5405                                         next_state = BNX2X_Q_STATE_ACTIVE;
5406                                 else /* tx only queues exist for this queue */
5407                                         next_state = BNX2X_Q_STATE_MULTI_COS;
5408                         } else
5409                                 next_state = BNX2X_Q_STATE_INACTIVE;
5410                 }
5411
5412                 break;
5413         case BNX2X_Q_STATE_STOPPED:
5414                 if (cmd == BNX2X_Q_CMD_TERMINATE)
5415                         next_state = BNX2X_Q_STATE_TERMINATED;
5416
5417                 break;
5418         case BNX2X_Q_STATE_TERMINATED:
5419                 if (cmd == BNX2X_Q_CMD_CFC_DEL)
5420                         next_state = BNX2X_Q_STATE_RESET;
5421
5422                 break;
5423         default:
5424                 BNX2X_ERR("Illegal state: %d\n", state);
5425         }
5426
5427         /* Transition is assured */
5428         if (next_state != BNX2X_Q_STATE_MAX) {
5429                 DP(BNX2X_MSG_SP, "Good state transition: %d(%d)->%d\n",
5430                                  state, cmd, next_state);
5431                 o->next_state = next_state;
5432                 o->next_tx_only = next_tx_only;
5433                 return 0;
5434         }
5435
5436         DP(BNX2X_MSG_SP, "Bad state transition request: %d %d\n", state, cmd);
5437
5438         return -EINVAL;
5439 }
5440
5441 void bnx2x_init_queue_obj(struct bnx2x *bp,
5442                           struct bnx2x_queue_sp_obj *obj,
5443                           u8 cl_id, u32 *cids, u8 cid_cnt, u8 func_id,
5444                           void *rdata,
5445                           dma_addr_t rdata_mapping, unsigned long type)
5446 {
5447         memset(obj, 0, sizeof(*obj));
5448
5449         /* We support only BNX2X_MULTI_TX_COS Tx CoS at the moment */
5450         BUG_ON(BNX2X_MULTI_TX_COS < cid_cnt);
5451
5452         memcpy(obj->cids, cids, sizeof(obj->cids[0]) * cid_cnt);
5453         obj->max_cos = cid_cnt;
5454         obj->cl_id = cl_id;
5455         obj->func_id = func_id;
5456         obj->rdata = rdata;
5457         obj->rdata_mapping = rdata_mapping;
5458         obj->type = type;
5459         obj->next_state = BNX2X_Q_STATE_MAX;
5460
5461         if (CHIP_IS_E1x(bp))
5462                 obj->send_cmd = bnx2x_queue_send_cmd_e1x;
5463         else
5464                 obj->send_cmd = bnx2x_queue_send_cmd_e2;
5465
5466         obj->check_transition = bnx2x_queue_chk_transition;
5467
5468         obj->complete_cmd = bnx2x_queue_comp_cmd;
5469         obj->wait_comp = bnx2x_queue_wait_comp;
5470         obj->set_pending = bnx2x_queue_set_pending;
5471 }
5472
5473 /* return a queue object's logical state*/
5474 int bnx2x_get_q_logical_state(struct bnx2x *bp,
5475                                struct bnx2x_queue_sp_obj *obj)
5476 {
5477         switch (obj->state) {
5478         case BNX2X_Q_STATE_ACTIVE:
5479         case BNX2X_Q_STATE_MULTI_COS:
5480                 return BNX2X_Q_LOGICAL_STATE_ACTIVE;
5481         case BNX2X_Q_STATE_RESET:
5482         case BNX2X_Q_STATE_INITIALIZED:
5483         case BNX2X_Q_STATE_MCOS_TERMINATED:
5484         case BNX2X_Q_STATE_INACTIVE:
5485         case BNX2X_Q_STATE_STOPPED:
5486         case BNX2X_Q_STATE_TERMINATED:
5487         case BNX2X_Q_STATE_FLRED:
5488                 return BNX2X_Q_LOGICAL_STATE_STOPPED;
5489         default:
5490                 return -EINVAL;
5491         }
5492 }
5493
5494 /********************** Function state object *********************************/
5495 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
5496                                            struct bnx2x_func_sp_obj *o)
5497 {
5498         /* in the middle of transaction - return INVALID state */
5499         if (o->pending)
5500                 return BNX2X_F_STATE_MAX;
5501
5502         /* unsure the order of reading of o->pending and o->state
5503          * o->pending should be read first
5504          */
5505         rmb();
5506
5507         return o->state;
5508 }
5509
5510 static int bnx2x_func_wait_comp(struct bnx2x *bp,
5511                                 struct bnx2x_func_sp_obj *o,
5512                                 enum bnx2x_func_cmd cmd)
5513 {
5514         return bnx2x_state_wait(bp, cmd, &o->pending);
5515 }
5516
5517 /**
5518  * bnx2x_func_state_change_comp - complete the state machine transition
5519  *
5520  * @bp:         device handle
5521  * @o:
5522  * @cmd:
5523  *
5524  * Called on state change transition. Completes the state
5525  * machine transition only - no HW interaction.
5526  */
5527 static inline int bnx2x_func_state_change_comp(struct bnx2x *bp,
5528                                                struct bnx2x_func_sp_obj *o,
5529                                                enum bnx2x_func_cmd cmd)
5530 {
5531         unsigned long cur_pending = o->pending;
5532
5533         if (!test_and_clear_bit(cmd, &cur_pending)) {
5534                 BNX2X_ERR("Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d\n",
5535                           cmd, BP_FUNC(bp), o->state,
5536                           cur_pending, o->next_state);
5537                 return -EINVAL;
5538         }
5539
5540         DP(BNX2X_MSG_SP,
5541            "Completing command %d for func %d, setting state to %d\n",
5542            cmd, BP_FUNC(bp), o->next_state);
5543
5544         o->state = o->next_state;
5545         o->next_state = BNX2X_F_STATE_MAX;
5546
5547         /* It's important that o->state and o->next_state are
5548          * updated before o->pending.
5549          */
5550         wmb();
5551
5552         clear_bit(cmd, &o->pending);
5553         smp_mb__after_atomic();
5554
5555         return 0;
5556 }
5557
5558 /**
5559  * bnx2x_func_comp_cmd - complete the state change command
5560  *
5561  * @bp:         device handle
5562  * @o:
5563  * @cmd:
5564  *
5565  * Checks that the arrived completion is expected.
5566  */
5567 static int bnx2x_func_comp_cmd(struct bnx2x *bp,
5568                                struct bnx2x_func_sp_obj *o,
5569                                enum bnx2x_func_cmd cmd)
5570 {
5571         /* Complete the state machine part first, check if it's a
5572          * legal completion.
5573          */
5574         int rc = bnx2x_func_state_change_comp(bp, o, cmd);
5575         return rc;
5576 }
5577
5578 /**
5579  * bnx2x_func_chk_transition - perform function state machine transition
5580  *
5581  * @bp:         device handle
5582  * @o:
5583  * @params:
5584  *
5585  * It both checks if the requested command is legal in a current
5586  * state and, if it's legal, sets a `next_state' in the object
5587  * that will be used in the completion flow to set the `state'
5588  * of the object.
5589  *
5590  * returns 0 if a requested command is a legal transition,
5591  *         -EINVAL otherwise.
5592  */
5593 static int bnx2x_func_chk_transition(struct bnx2x *bp,
5594                                      struct bnx2x_func_sp_obj *o,
5595                                      struct bnx2x_func_state_params *params)
5596 {
5597         enum bnx2x_func_state state = o->state, next_state = BNX2X_F_STATE_MAX;
5598         enum bnx2x_func_cmd cmd = params->cmd;
5599
5600         /* Forget all pending for completion commands if a driver only state
5601          * transition has been requested.
5602          */
5603         if (test_bit(RAMROD_DRV_CLR_ONLY, &params->ramrod_flags)) {
5604                 o->pending = 0;
5605                 o->next_state = BNX2X_F_STATE_MAX;
5606         }
5607
5608         /* Don't allow a next state transition if we are in the middle of
5609          * the previous one.
5610          */
5611         if (o->pending)
5612                 return -EBUSY;
5613
5614         switch (state) {
5615         case BNX2X_F_STATE_RESET:
5616                 if (cmd == BNX2X_F_CMD_HW_INIT)
5617                         next_state = BNX2X_F_STATE_INITIALIZED;
5618
5619                 break;
5620         case BNX2X_F_STATE_INITIALIZED:
5621                 if (cmd == BNX2X_F_CMD_START)
5622                         next_state = BNX2X_F_STATE_STARTED;
5623
5624                 else if (cmd == BNX2X_F_CMD_HW_RESET)
5625                         next_state = BNX2X_F_STATE_RESET;
5626
5627                 break;
5628         case BNX2X_F_STATE_STARTED:
5629                 if (cmd == BNX2X_F_CMD_STOP)
5630                         next_state = BNX2X_F_STATE_INITIALIZED;
5631                 /* afex ramrods can be sent only in started mode, and only
5632                  * if not pending for function_stop ramrod completion
5633                  * for these events - next state remained STARTED.
5634                  */
5635                 else if ((cmd == BNX2X_F_CMD_AFEX_UPDATE) &&
5636                          (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5637                         next_state = BNX2X_F_STATE_STARTED;
5638
5639                 else if ((cmd == BNX2X_F_CMD_AFEX_VIFLISTS) &&
5640                          (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5641                         next_state = BNX2X_F_STATE_STARTED;
5642
5643                 /* Switch_update ramrod can be sent in either started or
5644                  * tx_stopped state, and it doesn't change the state.
5645                  */
5646                 else if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) &&
5647                          (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5648                         next_state = BNX2X_F_STATE_STARTED;
5649
5650                 else if ((cmd == BNX2X_F_CMD_SET_TIMESYNC) &&
5651                          (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5652                         next_state = BNX2X_F_STATE_STARTED;
5653
5654                 else if (cmd == BNX2X_F_CMD_TX_STOP)
5655                         next_state = BNX2X_F_STATE_TX_STOPPED;
5656
5657                 break;
5658         case BNX2X_F_STATE_TX_STOPPED:
5659                 if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) &&
5660                     (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5661                         next_state = BNX2X_F_STATE_TX_STOPPED;
5662
5663                 else if ((cmd == BNX2X_F_CMD_SET_TIMESYNC) &&
5664                          (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5665                         next_state = BNX2X_F_STATE_TX_STOPPED;
5666
5667                 else if (cmd == BNX2X_F_CMD_TX_START)
5668                         next_state = BNX2X_F_STATE_STARTED;
5669
5670                 break;
5671         default:
5672                 BNX2X_ERR("Unknown state: %d\n", state);
5673         }
5674
5675         /* Transition is assured */
5676         if (next_state != BNX2X_F_STATE_MAX) {
5677                 DP(BNX2X_MSG_SP, "Good function state transition: %d(%d)->%d\n",
5678                                  state, cmd, next_state);
5679                 o->next_state = next_state;
5680                 return 0;
5681         }
5682
5683         DP(BNX2X_MSG_SP, "Bad function state transition request: %d %d\n",
5684                          state, cmd);
5685
5686         return -EINVAL;
5687 }
5688
5689 /**
5690  * bnx2x_func_init_func - performs HW init at function stage
5691  *
5692  * @bp:         device handle
5693  * @drv:
5694  *
5695  * Init HW when the current phase is
5696  * FW_MSG_CODE_DRV_LOAD_FUNCTION: initialize only FUNCTION-only
5697  * HW blocks.
5698  */
5699 static inline int bnx2x_func_init_func(struct bnx2x *bp,
5700                                        const struct bnx2x_func_sp_drv_ops *drv)
5701 {
5702         return drv->init_hw_func(bp);
5703 }
5704
5705 /**
5706  * bnx2x_func_init_port - performs HW init at port stage
5707  *
5708  * @bp:         device handle
5709  * @drv:
5710  *
5711  * Init HW when the current phase is
5712  * FW_MSG_CODE_DRV_LOAD_PORT: initialize PORT-only and
5713  * FUNCTION-only HW blocks.
5714  *
5715  */
5716 static inline int bnx2x_func_init_port(struct bnx2x *bp,
5717                                        const struct bnx2x_func_sp_drv_ops *drv)
5718 {
5719         int rc = drv->init_hw_port(bp);
5720         if (rc)
5721                 return rc;
5722
5723         return bnx2x_func_init_func(bp, drv);
5724 }
5725
5726 /**
5727  * bnx2x_func_init_cmn_chip - performs HW init at chip-common stage
5728  *
5729  * @bp:         device handle
5730  * @drv:
5731  *
5732  * Init HW when the current phase is
5733  * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON_CHIP,
5734  * PORT-only and FUNCTION-only HW blocks.
5735  */
5736 static inline int bnx2x_func_init_cmn_chip(struct bnx2x *bp,
5737                                         const struct bnx2x_func_sp_drv_ops *drv)
5738 {
5739         int rc = drv->init_hw_cmn_chip(bp);
5740         if (rc)
5741                 return rc;
5742
5743         return bnx2x_func_init_port(bp, drv);
5744 }
5745
5746 /**
5747  * bnx2x_func_init_cmn - performs HW init at common stage
5748  *
5749  * @bp:         device handle
5750  * @drv:
5751  *
5752  * Init HW when the current phase is
5753  * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON,
5754  * PORT-only and FUNCTION-only HW blocks.
5755  */
5756 static inline int bnx2x_func_init_cmn(struct bnx2x *bp,
5757                                       const struct bnx2x_func_sp_drv_ops *drv)
5758 {
5759         int rc = drv->init_hw_cmn(bp);
5760         if (rc)
5761                 return rc;
5762
5763         return bnx2x_func_init_port(bp, drv);
5764 }
5765
5766 static int bnx2x_func_hw_init(struct bnx2x *bp,
5767                               struct bnx2x_func_state_params *params)
5768 {
5769         u32 load_code = params->params.hw_init.load_phase;
5770         struct bnx2x_func_sp_obj *o = params->f_obj;
5771         const struct bnx2x_func_sp_drv_ops *drv = o->drv;
5772         int rc = 0;
5773
5774         DP(BNX2X_MSG_SP, "function %d  load_code %x\n",
5775                          BP_ABS_FUNC(bp), load_code);
5776
5777         /* Prepare buffers for unzipping the FW */
5778         rc = drv->gunzip_init(bp);
5779         if (rc)
5780                 return rc;
5781
5782         /* Prepare FW */
5783         rc = drv->init_fw(bp);
5784         if (rc) {
5785                 BNX2X_ERR("Error loading firmware\n");
5786                 goto init_err;
5787         }
5788
5789         /* Handle the beginning of COMMON_XXX pases separately... */
5790         switch (load_code) {
5791         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5792                 rc = bnx2x_func_init_cmn_chip(bp, drv);
5793                 if (rc)
5794                         goto init_err;
5795
5796                 break;
5797         case FW_MSG_CODE_DRV_LOAD_COMMON:
5798                 rc = bnx2x_func_init_cmn(bp, drv);
5799                 if (rc)
5800                         goto init_err;
5801
5802                 break;
5803         case FW_MSG_CODE_DRV_LOAD_PORT:
5804                 rc = bnx2x_func_init_port(bp, drv);
5805                 if (rc)
5806                         goto init_err;
5807
5808                 break;
5809         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5810                 rc = bnx2x_func_init_func(bp, drv);
5811                 if (rc)
5812                         goto init_err;
5813
5814                 break;
5815         default:
5816                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5817                 rc = -EINVAL;
5818         }
5819
5820 init_err:
5821         drv->gunzip_end(bp);
5822
5823         /* In case of success, complete the command immediately: no ramrods
5824          * have been sent.
5825          */
5826         if (!rc)
5827                 o->complete_cmd(bp, o, BNX2X_F_CMD_HW_INIT);
5828
5829         return rc;
5830 }
5831
5832 /**
5833  * bnx2x_func_reset_func - reset HW at function stage
5834  *
5835  * @bp:         device handle
5836  * @drv:
5837  *
5838  * Reset HW at FW_MSG_CODE_DRV_UNLOAD_FUNCTION stage: reset only
5839  * FUNCTION-only HW blocks.
5840  */
5841 static inline void bnx2x_func_reset_func(struct bnx2x *bp,
5842                                         const struct bnx2x_func_sp_drv_ops *drv)
5843 {
5844         drv->reset_hw_func(bp);
5845 }
5846
5847 /**
5848  * bnx2x_func_reset_port - reset HW at port stage
5849  *
5850  * @bp:         device handle
5851  * @drv:
5852  *
5853  * Reset HW at FW_MSG_CODE_DRV_UNLOAD_PORT stage: reset
5854  * FUNCTION-only and PORT-only HW blocks.
5855  *
5856  *                 !!!IMPORTANT!!!
5857  *
5858  * It's important to call reset_port before reset_func() as the last thing
5859  * reset_func does is pf_disable() thus disabling PGLUE_B, which
5860  * makes impossible any DMAE transactions.
5861  */
5862 static inline void bnx2x_func_reset_port(struct bnx2x *bp,
5863                                         const struct bnx2x_func_sp_drv_ops *drv)
5864 {
5865         drv->reset_hw_port(bp);
5866         bnx2x_func_reset_func(bp, drv);
5867 }
5868
5869 /**
5870  * bnx2x_func_reset_cmn - reset HW at common stage
5871  *
5872  * @bp:         device handle
5873  * @drv:
5874  *
5875  * Reset HW at FW_MSG_CODE_DRV_UNLOAD_COMMON and
5876  * FW_MSG_CODE_DRV_UNLOAD_COMMON_CHIP stages: reset COMMON,
5877  * COMMON_CHIP, FUNCTION-only and PORT-only HW blocks.
5878  */
5879 static inline void bnx2x_func_reset_cmn(struct bnx2x *bp,
5880                                         const struct bnx2x_func_sp_drv_ops *drv)
5881 {
5882         bnx2x_func_reset_port(bp, drv);
5883         drv->reset_hw_cmn(bp);
5884 }
5885
5886 static inline int bnx2x_func_hw_reset(struct bnx2x *bp,
5887                                       struct bnx2x_func_state_params *params)
5888 {
5889         u32 reset_phase = params->params.hw_reset.reset_phase;
5890         struct bnx2x_func_sp_obj *o = params->f_obj;
5891         const struct bnx2x_func_sp_drv_ops *drv = o->drv;
5892
5893         DP(BNX2X_MSG_SP, "function %d  reset_phase %x\n", BP_ABS_FUNC(bp),
5894                          reset_phase);
5895
5896         switch (reset_phase) {
5897         case FW_MSG_CODE_DRV_UNLOAD_COMMON:
5898                 bnx2x_func_reset_cmn(bp, drv);
5899                 break;
5900         case FW_MSG_CODE_DRV_UNLOAD_PORT:
5901                 bnx2x_func_reset_port(bp, drv);
5902                 break;
5903         case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
5904                 bnx2x_func_reset_func(bp, drv);
5905                 break;
5906         default:
5907                 BNX2X_ERR("Unknown reset_phase (0x%x) from MCP\n",
5908                            reset_phase);
5909                 break;
5910         }
5911
5912         /* Complete the command immediately: no ramrods have been sent. */
5913         o->complete_cmd(bp, o, BNX2X_F_CMD_HW_RESET);
5914
5915         return 0;
5916 }
5917
5918 static inline int bnx2x_func_send_start(struct bnx2x *bp,
5919                                         struct bnx2x_func_state_params *params)
5920 {
5921         struct bnx2x_func_sp_obj *o = params->f_obj;
5922         struct function_start_data *rdata =
5923                 (struct function_start_data *)o->rdata;
5924         dma_addr_t data_mapping = o->rdata_mapping;
5925         struct bnx2x_func_start_params *start_params = &params->params.start;
5926
5927         memset(rdata, 0, sizeof(*rdata));
5928
5929         /* Fill the ramrod data with provided parameters */
5930         rdata->function_mode    = (u8)start_params->mf_mode;
5931         rdata->sd_vlan_tag      = cpu_to_le16(start_params->sd_vlan_tag);
5932         rdata->path_id          = BP_PATH(bp);
5933         rdata->network_cos_mode = start_params->network_cos_mode;
5934
5935         rdata->vxlan_dst_port   = cpu_to_le16(start_params->vxlan_dst_port);
5936         rdata->geneve_dst_port  = cpu_to_le16(start_params->geneve_dst_port);
5937         rdata->inner_clss_l2gre = start_params->inner_clss_l2gre;
5938         rdata->inner_clss_l2geneve = start_params->inner_clss_l2geneve;
5939         rdata->inner_clss_vxlan = start_params->inner_clss_vxlan;
5940         rdata->inner_rss        = start_params->inner_rss;
5941
5942         rdata->sd_accept_mf_clss_fail = start_params->class_fail;
5943         if (start_params->class_fail_ethtype) {
5944                 rdata->sd_accept_mf_clss_fail_match_ethtype = 1;
5945                 rdata->sd_accept_mf_clss_fail_ethtype =
5946                         cpu_to_le16(start_params->class_fail_ethtype);
5947         }
5948
5949         rdata->sd_vlan_force_pri_flg = start_params->sd_vlan_force_pri;
5950         rdata->sd_vlan_force_pri_val = start_params->sd_vlan_force_pri_val;
5951         if (start_params->sd_vlan_eth_type)
5952                 rdata->sd_vlan_eth_type =
5953                         cpu_to_le16(start_params->sd_vlan_eth_type);
5954         else
5955                 rdata->sd_vlan_eth_type =
5956                         cpu_to_le16(0x8100);
5957
5958         rdata->no_added_tags = start_params->no_added_tags;
5959
5960         rdata->c2s_pri_tt_valid = start_params->c2s_pri_valid;
5961         if (rdata->c2s_pri_tt_valid) {
5962                 memcpy(rdata->c2s_pri_trans_table.val,
5963                        start_params->c2s_pri,
5964                        MAX_VLAN_PRIORITIES);
5965                 rdata->c2s_pri_default = start_params->c2s_pri_default;
5966         }
5967         /* No need for an explicit memory barrier here as long we would
5968          * need to ensure the ordering of writing to the SPQ element
5969          * and updating of the SPQ producer which involves a memory
5970          * read and we will have to put a full memory barrier there
5971          * (inside bnx2x_sp_post()).
5972          */
5973
5974         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0,
5975                              U64_HI(data_mapping),
5976                              U64_LO(data_mapping), NONE_CONNECTION_TYPE);
5977 }
5978
5979 static inline int bnx2x_func_send_switch_update(struct bnx2x *bp,
5980                                         struct bnx2x_func_state_params *params)
5981 {
5982         struct bnx2x_func_sp_obj *o = params->f_obj;
5983         struct function_update_data *rdata =
5984                 (struct function_update_data *)o->rdata;
5985         dma_addr_t data_mapping = o->rdata_mapping;
5986         struct bnx2x_func_switch_update_params *switch_update_params =
5987                 &params->params.switch_update;
5988
5989         memset(rdata, 0, sizeof(*rdata));
5990
5991         /* Fill the ramrod data with provided parameters */
5992         if (test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
5993                      &switch_update_params->changes)) {
5994                 rdata->tx_switch_suspend_change_flg = 1;
5995                 rdata->tx_switch_suspend =
5996                         test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
5997                                  &switch_update_params->changes);
5998         }
5999
6000         if (test_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
6001                      &switch_update_params->changes)) {
6002                 rdata->sd_vlan_tag_change_flg = 1;
6003                 rdata->sd_vlan_tag =
6004                         cpu_to_le16(switch_update_params->vlan);
6005         }
6006
6007         if (test_bit(BNX2X_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG,
6008                      &switch_update_params->changes)) {
6009                 rdata->sd_vlan_eth_type_change_flg = 1;
6010                 rdata->sd_vlan_eth_type =
6011                         cpu_to_le16(switch_update_params->vlan_eth_type);
6012         }
6013
6014         if (test_bit(BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
6015                      &switch_update_params->changes)) {
6016                 rdata->sd_vlan_force_pri_change_flg = 1;
6017                 if (test_bit(BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
6018                              &switch_update_params->changes))
6019                         rdata->sd_vlan_force_pri_flg = 1;
6020                 rdata->sd_vlan_force_pri_flg =
6021                         switch_update_params->vlan_force_prio;
6022         }
6023
6024         if (test_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
6025                      &switch_update_params->changes)) {
6026                 rdata->update_tunn_cfg_flg = 1;
6027                 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
6028                              &switch_update_params->changes))
6029                         rdata->inner_clss_l2gre = 1;
6030                 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
6031                              &switch_update_params->changes))
6032                         rdata->inner_clss_vxlan = 1;
6033                 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
6034                              &switch_update_params->changes))
6035                         rdata->inner_clss_l2geneve = 1;
6036                 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
6037                              &switch_update_params->changes))
6038                         rdata->inner_rss = 1;
6039                 rdata->vxlan_dst_port =
6040                         cpu_to_le16(switch_update_params->vxlan_dst_port);
6041                 rdata->geneve_dst_port =
6042                         cpu_to_le16(switch_update_params->geneve_dst_port);
6043         }
6044
6045         rdata->echo = SWITCH_UPDATE;
6046
6047         /* No need for an explicit memory barrier here as long as we
6048          * ensure the ordering of writing to the SPQ element
6049          * and updating of the SPQ producer which involves a memory
6050          * read. If the memory read is removed we will have to put a
6051          * full memory barrier there (inside bnx2x_sp_post()).
6052          */
6053         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,
6054                              U64_HI(data_mapping),
6055                              U64_LO(data_mapping), NONE_CONNECTION_TYPE);
6056 }
6057
6058 static inline int bnx2x_func_send_afex_update(struct bnx2x *bp,
6059                                          struct bnx2x_func_state_params *params)
6060 {
6061         struct bnx2x_func_sp_obj *o = params->f_obj;
6062         struct function_update_data *rdata =
6063                 (struct function_update_data *)o->afex_rdata;
6064         dma_addr_t data_mapping = o->afex_rdata_mapping;
6065         struct bnx2x_func_afex_update_params *afex_update_params =
6066                 &params->params.afex_update;
6067
6068         memset(rdata, 0, sizeof(*rdata));
6069
6070         /* Fill the ramrod data with provided parameters */
6071         rdata->vif_id_change_flg = 1;
6072         rdata->vif_id = cpu_to_le16(afex_update_params->vif_id);
6073         rdata->afex_default_vlan_change_flg = 1;
6074         rdata->afex_default_vlan =
6075                 cpu_to_le16(afex_update_params->afex_default_vlan);
6076         rdata->allowed_priorities_change_flg = 1;
6077         rdata->allowed_priorities = afex_update_params->allowed_priorities;
6078         rdata->echo = AFEX_UPDATE;
6079
6080         /* No need for an explicit memory barrier here as long as we
6081          * ensure the ordering of writing to the SPQ element
6082          * and updating of the SPQ producer which involves a memory
6083          * read. If the memory read is removed we will have to put a
6084          * full memory barrier there (inside bnx2x_sp_post()).
6085          */
6086         DP(BNX2X_MSG_SP,
6087            "afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x\n",
6088            rdata->vif_id,
6089            rdata->afex_default_vlan, rdata->allowed_priorities);
6090
6091         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,
6092                              U64_HI(data_mapping),
6093                              U64_LO(data_mapping), NONE_CONNECTION_TYPE);
6094 }
6095
6096 static
6097 inline int bnx2x_func_send_afex_viflists(struct bnx2x *bp,
6098                                          struct bnx2x_func_state_params *params)
6099 {
6100         struct bnx2x_func_sp_obj *o = params->f_obj;
6101         struct afex_vif_list_ramrod_data *rdata =
6102                 (struct afex_vif_list_ramrod_data *)o->afex_rdata;
6103         struct bnx2x_func_afex_viflists_params *afex_vif_params =
6104                 &params->params.afex_viflists;
6105         u64 *p_rdata = (u64 *)rdata;
6106
6107         memset(rdata, 0, sizeof(*rdata));
6108
6109         /* Fill the ramrod data with provided parameters */
6110         rdata->vif_list_index = cpu_to_le16(afex_vif_params->vif_list_index);
6111         rdata->func_bit_map          = afex_vif_params->func_bit_map;
6112         rdata->afex_vif_list_command = afex_vif_params->afex_vif_list_command;
6113         rdata->func_to_clear         = afex_vif_params->func_to_clear;
6114
6115         /* send in echo type of sub command */
6116         rdata->echo = afex_vif_params->afex_vif_list_command;
6117
6118         /*  No need for an explicit memory barrier here as long we would
6119          *  need to ensure the ordering of writing to the SPQ element
6120          *  and updating of the SPQ producer which involves a memory
6121          *  read and we will have to put a full memory barrier there
6122          *  (inside bnx2x_sp_post()).
6123          */
6124
6125         DP(BNX2X_MSG_SP, "afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x\n",
6126            rdata->afex_vif_list_command, rdata->vif_list_index,
6127            rdata->func_bit_map, rdata->func_to_clear);
6128
6129         /* this ramrod sends data directly and not through DMA mapping */
6130         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 0,
6131                              U64_HI(*p_rdata), U64_LO(*p_rdata),
6132                              NONE_CONNECTION_TYPE);
6133 }
6134
6135 static inline int bnx2x_func_send_stop(struct bnx2x *bp,
6136                                        struct bnx2x_func_state_params *params)
6137 {
6138         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0,
6139                              NONE_CONNECTION_TYPE);
6140 }
6141
6142 static inline int bnx2x_func_send_tx_stop(struct bnx2x *bp,
6143                                        struct bnx2x_func_state_params *params)
6144 {
6145         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 0, 0, 0,
6146                              NONE_CONNECTION_TYPE);
6147 }
6148 static inline int bnx2x_func_send_tx_start(struct bnx2x *bp,
6149                                        struct bnx2x_func_state_params *params)
6150 {
6151         struct bnx2x_func_sp_obj *o = params->f_obj;
6152         struct flow_control_configuration *rdata =
6153                 (struct flow_control_configuration *)o->rdata;
6154         dma_addr_t data_mapping = o->rdata_mapping;
6155         struct bnx2x_func_tx_start_params *tx_start_params =
6156                 &params->params.tx_start;
6157         int i;
6158
6159         memset(rdata, 0, sizeof(*rdata));
6160
6161         rdata->dcb_enabled = tx_start_params->dcb_enabled;
6162         rdata->dcb_version = tx_start_params->dcb_version;
6163         rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0_en;
6164
6165         for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)
6166                 rdata->traffic_type_to_priority_cos[i] =
6167                         tx_start_params->traffic_type_to_priority_cos[i];
6168
6169         for (i = 0; i < MAX_TRAFFIC_TYPES; i++)
6170                 rdata->dcb_outer_pri[i] = tx_start_params->dcb_outer_pri[i];
6171         /* No need for an explicit memory barrier here as long as we
6172          * ensure the ordering of writing to the SPQ element
6173          * and updating of the SPQ producer which involves a memory
6174          * read. If the memory read is removed we will have to put a
6175          * full memory barrier there (inside bnx2x_sp_post()).
6176          */
6177         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_START_TRAFFIC, 0,
6178                              U64_HI(data_mapping),
6179                              U64_LO(data_mapping), NONE_CONNECTION_TYPE);
6180 }
6181
6182 static inline
6183 int bnx2x_func_send_set_timesync(struct bnx2x *bp,
6184                                  struct bnx2x_func_state_params *params)
6185 {
6186         struct bnx2x_func_sp_obj *o = params->f_obj;
6187         struct set_timesync_ramrod_data *rdata =
6188                 (struct set_timesync_ramrod_data *)o->rdata;
6189         dma_addr_t data_mapping = o->rdata_mapping;
6190         struct bnx2x_func_set_timesync_params *set_timesync_params =
6191                 &params->params.set_timesync;
6192
6193         memset(rdata, 0, sizeof(*rdata));
6194
6195         /* Fill the ramrod data with provided parameters */
6196         rdata->drift_adjust_cmd = set_timesync_params->drift_adjust_cmd;
6197         rdata->offset_cmd = set_timesync_params->offset_cmd;
6198         rdata->add_sub_drift_adjust_value =
6199                 set_timesync_params->add_sub_drift_adjust_value;
6200         rdata->drift_adjust_value = set_timesync_params->drift_adjust_value;
6201         rdata->drift_adjust_period = set_timesync_params->drift_adjust_period;
6202         rdata->offset_delta.lo =
6203                 cpu_to_le32(U64_LO(set_timesync_params->offset_delta));
6204         rdata->offset_delta.hi =
6205                 cpu_to_le32(U64_HI(set_timesync_params->offset_delta));
6206
6207         DP(BNX2X_MSG_SP, "Set timesync command params: drift_cmd = %d, offset_cmd = %d, add_sub_drift = %d, drift_val = %d, drift_period = %d, offset_lo = %d, offset_hi = %d\n",
6208            rdata->drift_adjust_cmd, rdata->offset_cmd,
6209            rdata->add_sub_drift_adjust_value, rdata->drift_adjust_value,
6210            rdata->drift_adjust_period, rdata->offset_delta.lo,
6211            rdata->offset_delta.hi);
6212
6213         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_TIMESYNC, 0,
6214                              U64_HI(data_mapping),
6215                              U64_LO(data_mapping), NONE_CONNECTION_TYPE);
6216 }
6217
6218 static int bnx2x_func_send_cmd(struct bnx2x *bp,
6219                                struct bnx2x_func_state_params *params)
6220 {
6221         switch (params->cmd) {
6222         case BNX2X_F_CMD_HW_INIT:
6223                 return bnx2x_func_hw_init(bp, params);
6224         case BNX2X_F_CMD_START:
6225                 return bnx2x_func_send_start(bp, params);
6226         case BNX2X_F_CMD_STOP:
6227                 return bnx2x_func_send_stop(bp, params);
6228         case BNX2X_F_CMD_HW_RESET:
6229                 return bnx2x_func_hw_reset(bp, params);
6230         case BNX2X_F_CMD_AFEX_UPDATE:
6231                 return bnx2x_func_send_afex_update(bp, params);
6232         case BNX2X_F_CMD_AFEX_VIFLISTS:
6233                 return bnx2x_func_send_afex_viflists(bp, params);
6234         case BNX2X_F_CMD_TX_STOP:
6235                 return bnx2x_func_send_tx_stop(bp, params);
6236         case BNX2X_F_CMD_TX_START:
6237                 return bnx2x_func_send_tx_start(bp, params);
6238         case BNX2X_F_CMD_SWITCH_UPDATE:
6239                 return bnx2x_func_send_switch_update(bp, params);
6240         case BNX2X_F_CMD_SET_TIMESYNC:
6241                 return bnx2x_func_send_set_timesync(bp, params);
6242         default:
6243                 BNX2X_ERR("Unknown command: %d\n", params->cmd);
6244                 return -EINVAL;
6245         }
6246 }
6247
6248 void bnx2x_init_func_obj(struct bnx2x *bp,
6249                          struct bnx2x_func_sp_obj *obj,
6250                          void *rdata, dma_addr_t rdata_mapping,
6251                          void *afex_rdata, dma_addr_t afex_rdata_mapping,
6252                          struct bnx2x_func_sp_drv_ops *drv_iface)
6253 {
6254         memset(obj, 0, sizeof(*obj));
6255
6256         mutex_init(&obj->one_pending_mutex);
6257
6258         obj->rdata = rdata;
6259         obj->rdata_mapping = rdata_mapping;
6260         obj->afex_rdata = afex_rdata;
6261         obj->afex_rdata_mapping = afex_rdata_mapping;
6262         obj->send_cmd = bnx2x_func_send_cmd;
6263         obj->check_transition = bnx2x_func_chk_transition;
6264         obj->complete_cmd = bnx2x_func_comp_cmd;
6265         obj->wait_comp = bnx2x_func_wait_comp;
6266
6267         obj->drv = drv_iface;
6268 }
6269
6270 /**
6271  * bnx2x_func_state_change - perform Function state change transition
6272  *
6273  * @bp:         device handle
6274  * @params:     parameters to perform the transaction
6275  *
6276  * returns 0 in case of successfully completed transition,
6277  *         negative error code in case of failure, positive
6278  *         (EBUSY) value if there is a completion to that is
6279  *         still pending (possible only if RAMROD_COMP_WAIT is
6280  *         not set in params->ramrod_flags for asynchronous
6281  *         commands).
6282  */
6283 int bnx2x_func_state_change(struct bnx2x *bp,
6284                             struct bnx2x_func_state_params *params)
6285 {
6286         struct bnx2x_func_sp_obj *o = params->f_obj;
6287         int rc, cnt = 300;
6288         enum bnx2x_func_cmd cmd = params->cmd;
6289         unsigned long *pending = &o->pending;
6290
6291         mutex_lock(&o->one_pending_mutex);
6292
6293         /* Check that the requested transition is legal */
6294         rc = o->check_transition(bp, o, params);
6295         if ((rc == -EBUSY) &&
6296             (test_bit(RAMROD_RETRY, &params->ramrod_flags))) {
6297                 while ((rc == -EBUSY) && (--cnt > 0)) {
6298                         mutex_unlock(&o->one_pending_mutex);
6299                         msleep(10);
6300                         mutex_lock(&o->one_pending_mutex);
6301                         rc = o->check_transition(bp, o, params);
6302                 }
6303                 if (rc == -EBUSY) {
6304                         mutex_unlock(&o->one_pending_mutex);
6305                         BNX2X_ERR("timeout waiting for previous ramrod completion\n");
6306                         return rc;
6307                 }
6308         } else if (rc) {
6309                 mutex_unlock(&o->one_pending_mutex);
6310                 return rc;
6311         }
6312
6313         /* Set "pending" bit */
6314         set_bit(cmd, pending);
6315
6316         /* Don't send a command if only driver cleanup was requested */
6317         if (test_bit(RAMROD_DRV_CLR_ONLY, &params->ramrod_flags)) {
6318                 bnx2x_func_state_change_comp(bp, o, cmd);
6319                 mutex_unlock(&o->one_pending_mutex);
6320         } else {
6321                 /* Send a ramrod */
6322                 rc = o->send_cmd(bp, params);
6323
6324                 mutex_unlock(&o->one_pending_mutex);
6325
6326                 if (rc) {
6327                         o->next_state = BNX2X_F_STATE_MAX;
6328                         clear_bit(cmd, pending);
6329                         smp_mb__after_atomic();
6330                         return rc;
6331                 }
6332
6333                 if (test_bit(RAMROD_COMP_WAIT, &params->ramrod_flags)) {
6334                         rc = o->wait_comp(bp, o, cmd);
6335                         if (rc)
6336                                 return rc;
6337
6338                         return 0;
6339                 }
6340         }
6341
6342         return !!test_bit(cmd, pending);
6343 }