kernel/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2013 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
  31                                              struct link_params *params,
  32                                              u8 dev_addr, u16 addr, u8 byte_cnt,
  33                                              u8 *o_buf, u8);
  34 /********************************************************/
  35 #define ETH_HLEN                        14
  36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  37 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  38 #define ETH_MIN_PACKET_SIZE             60
  39 #define ETH_MAX_PACKET_SIZE             1500
  40 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  41 #define MDIO_ACCESS_TIMEOUT             1000
  42 #define WC_LANE_MAX                     4
  43 #define I2C_SWITCH_WIDTH                2
  44 #define I2C_BSC0                        0
  45 #define I2C_BSC1                        1
  46 #define I2C_WA_RETRY_CNT                3
  47 #define I2C_WA_PWR_ITER                 (I2C_WA_RETRY_CNT - 1)
  48 #define MCPR_IMC_COMMAND_READ_OP        1
  49 #define MCPR_IMC_COMMAND_WRITE_OP       2
  50
  51 /* LED Blink rate that will achieve ~15.9Hz */
  52 #define LED_BLINK_RATE_VAL_E3           354
  53 #define LED_BLINK_RATE_VAL_E1X_E2       480
  54 /***********************************************************/
  55 /*                      Shortcut definitions               */
  56 /***********************************************************/
  57
  58 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  59
  60 #define NIG_STATUS_EMAC0_MI_INT \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  62 #define NIG_STATUS_XGXS0_LINK10G \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  64 #define NIG_STATUS_XGXS0_LINK_STATUS \
  65                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  67                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  68 #define NIG_STATUS_SERDES0_LINK_STATUS \
  69                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  70 #define NIG_MASK_MI_INT \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  72 #define NIG_MASK_XGXS0_LINK10G \
  73                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  74 #define NIG_MASK_XGXS0_LINK_STATUS \
  75                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  76 #define NIG_MASK_SERDES0_LINK_STATUS \
  77                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  78
  79 #define MDIO_AN_CL73_OR_37_COMPLETE \
  80                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  81                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  82
  83 #define XGXS_RESET_BITS \
  84         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  85          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  86          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  89
  90 #define SERDES_RESET_BITS \
  91         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  92          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  93          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  94          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  95
  96 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  97 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  98 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  99 #define AUTONEG_PARALLEL \
 100                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
 101 #define AUTONEG_SGMII_FIBER_AUTODET \
 102                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
 103 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 104
 105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 106                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 108                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 109 #define GP_STATUS_SPEED_MASK \
 110                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 111 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 112 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 113 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 114 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 115 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 116 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 117 #define GP_STATUS_10G_HIG \
 118                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 119 #define GP_STATUS_10G_CX4 \
 120                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 122 #define GP_STATUS_10G_KX4 \
 123                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 125 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 127 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
 129 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 130 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 131 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 132 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 133 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 134 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 135 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 136 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 137 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 138 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 139 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 140 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 141 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 142 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 143 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 144
 145 #define LINK_UPDATE_MASK \
 146                         (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
 147                          LINK_STATUS_LINK_UP | \
 148                          LINK_STATUS_PHYSICAL_LINK_FLAG | \
 149                          LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
 150                          LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
 151                          LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
 152                          LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
 153                          LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
 154                          LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 155
 156 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 157         #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0
 158         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 159         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 160         #define SFP_EEPROM_CON_TYPE_VAL_RJ45    0x22
 161
 162
 163 #define SFP_EEPROM_10G_COMP_CODE_ADDR           0x3
 164         #define SFP_EEPROM_10G_COMP_CODE_SR_MASK        (1<<4)
 165         #define SFP_EEPROM_10G_COMP_CODE_LR_MASK        (1<<5)
 166         #define SFP_EEPROM_10G_COMP_CODE_LRM_MASK       (1<<6)
 167
 168 #define SFP_EEPROM_1G_COMP_CODE_ADDR            0x6
 169         #define SFP_EEPROM_1G_COMP_CODE_SX      (1<<0)
 170         #define SFP_EEPROM_1G_COMP_CODE_LX      (1<<1)
 171         #define SFP_EEPROM_1G_COMP_CODE_CX      (1<<2)
 172         #define SFP_EEPROM_1G_COMP_CODE_BASE_T  (1<<3)
 173
 174 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 175         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 176         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 177
 178 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 179         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 180 #define SFP_EEPROM_OPTIONS_SIZE                 2
 181
 182 #define EDC_MODE_LINEAR                         0x0022
 183 #define EDC_MODE_LIMITING                               0x0044
 184 #define EDC_MODE_PASSIVE_DAC                    0x0055
 185 #define EDC_MODE_ACTIVE_DAC                     0x0066
 186
 187 /* ETS defines*/
 188 #define DCBX_INVALID_COS                                        (0xFF)
 189
 190 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 191 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 192 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 193 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 194 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 195
 196 #define MAX_PACKET_SIZE                                 (9700)
 197 #define MAX_KR_LINK_RETRY                               4
 198 #define DEFAULT_TX_DRV_BRDCT            2
 199 #define DEFAULT_TX_DRV_IFIR             0
 200 #define DEFAULT_TX_DRV_POST2            3
 201 #define DEFAULT_TX_DRV_IPRE_DRIVER      6
 202
 203 /**********************************************************/
 204 /*                     INTERFACE                          */
 205 /**********************************************************/
 206
 207 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 208         bnx2x_cl45_write(_bp, _phy, \
 209                 (_phy)->def_md_devad, \
 210                 (_bank + (_addr & 0xf)), \
 211                 _val)
 212
 213 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 214         bnx2x_cl45_read(_bp, _phy, \
 215                 (_phy)->def_md_devad, \
 216                 (_bank + (_addr & 0xf)), \
 217                 _val)
 218
 219 static int bnx2x_check_half_open_conn(struct link_params *params,
 220                                       struct link_vars *vars, u8 notify);
 221 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
 222                                       struct link_params *params);
 223
 224 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 225 {
 226         u32 val = REG_RD(bp, reg);
 227
 228         val |= bits;
 229         REG_WR(bp, reg, val);
 230         return val;
 231 }
 232
 233 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 234 {
 235         u32 val = REG_RD(bp, reg);
 236
 237         val &= ~bits;
 238         REG_WR(bp, reg, val);
 239         return val;
 240 }
 241
 242 /*
 243  * bnx2x_check_lfa - This function checks if link reinitialization is required,
 244  *                   or link flap can be avoided.
 245  *
 246  * @params:     link parameters
 247  * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
 248  *         condition code.
 249  */
 250 static int bnx2x_check_lfa(struct link_params *params)
 251 {
 252         u32 link_status, cfg_idx, lfa_mask, cfg_size;
 253         u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
 254         u32 saved_val, req_val, eee_status;
 255         struct bnx2x *bp = params->bp;
 256
 257         additional_config =
 258                 REG_RD(bp, params->lfa_base +
 259                            offsetof(struct shmem_lfa, additional_config));
 260
 261         /* NOTE: must be first condition checked -
 262         * to verify DCC bit is cleared in any case!
 263         */
 264         if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
 265                 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
 266                 REG_WR(bp, params->lfa_base +
 267                            offsetof(struct shmem_lfa, additional_config),
 268                        additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
 269                 return LFA_DCC_LFA_DISABLED;
 270         }
 271
 272         /* Verify that link is up */
 273         link_status = REG_RD(bp, params->shmem_base +
 274                              offsetof(struct shmem_region,
 275                                       port_mb[params->port].link_status));
 276         if (!(link_status & LINK_STATUS_LINK_UP))
 277                 return LFA_LINK_DOWN;
 278
 279         /* if loaded after BOOT from SAN, don't flap the link in any case and
 280          * rely on link set by preboot driver
 281          */
 282         if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
 283                 return 0;
 284
 285         /* Verify that loopback mode is not set */
 286         if (params->loopback_mode)
 287                 return LFA_LOOPBACK_ENABLED;
 288
 289         /* Verify that MFW supports LFA */
 290         if (!params->lfa_base)
 291                 return LFA_MFW_IS_TOO_OLD;
 292
 293         if (params->num_phys == 3) {
 294                 cfg_size = 2;
 295                 lfa_mask = 0xffffffff;
 296         } else {
 297                 cfg_size = 1;
 298                 lfa_mask = 0xffff;
 299         }
 300
 301         /* Compare Duplex */
 302         saved_val = REG_RD(bp, params->lfa_base +
 303                            offsetof(struct shmem_lfa, req_duplex));
 304         req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
 305         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 306                 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
 307                                (saved_val & lfa_mask), (req_val & lfa_mask));
 308                 return LFA_DUPLEX_MISMATCH;
 309         }
 310         /* Compare Flow Control */
 311         saved_val = REG_RD(bp, params->lfa_base +
 312                            offsetof(struct shmem_lfa, req_flow_ctrl));
 313         req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
 314         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 315                 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
 316                                (saved_val & lfa_mask), (req_val & lfa_mask));
 317                 return LFA_FLOW_CTRL_MISMATCH;
 318         }
 319         /* Compare Link Speed */
 320         saved_val = REG_RD(bp, params->lfa_base +
 321                            offsetof(struct shmem_lfa, req_line_speed));
 322         req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
 323         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 324                 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
 325                                (saved_val & lfa_mask), (req_val & lfa_mask));
 326                 return LFA_LINK_SPEED_MISMATCH;
 327         }
 328
 329         for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
 330                 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
 331                                             offsetof(struct shmem_lfa,
 332                                                      speed_cap_mask[cfg_idx]));
 333
 334                 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
 335                         DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
 336                                        cur_speed_cap_mask,
 337                                        params->speed_cap_mask[cfg_idx]);
 338                         return LFA_SPEED_CAP_MISMATCH;
 339                 }
 340         }
 341
 342         cur_req_fc_auto_adv =
 343                 REG_RD(bp, params->lfa_base +
 344                        offsetof(struct shmem_lfa, additional_config)) &
 345                 REQ_FC_AUTO_ADV_MASK;
 346
 347         if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
 348                 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
 349                                cur_req_fc_auto_adv, params->req_fc_auto_adv);
 350                 return LFA_FLOW_CTRL_MISMATCH;
 351         }
 352
 353         eee_status = REG_RD(bp, params->shmem2_base +
 354                             offsetof(struct shmem2_region,
 355                                      eee_status[params->port]));
 356
 357         if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
 358              (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
 359             ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
 360              (params->eee_mode & EEE_MODE_ADV_LPI))) {
 361                 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
 362                                eee_status);
 363                 return LFA_EEE_MISMATCH;
 364         }
 365
 366         /* LFA conditions are met */
 367         return 0;
 368 }
 369 /******************************************************************/
 370 /*                      EPIO/GPIO section                         */
 371 /******************************************************************/
 372 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 373 {
 374         u32 epio_mask, gp_oenable;
 375         *en = 0;
 376         /* Sanity check */
 377         if (epio_pin > 31) {
 378                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 379                 return;
 380         }
 381
 382         epio_mask = 1 << epio_pin;
 383         /* Set this EPIO to output */
 384         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 385         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 386
 387         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 388 }
 389 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 390 {
 391         u32 epio_mask, gp_output, gp_oenable;
 392
 393         /* Sanity check */
 394         if (epio_pin > 31) {
 395                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 396                 return;
 397         }
 398         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 399         epio_mask = 1 << epio_pin;
 400         /* Set this EPIO to output */
 401         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 402         if (en)
 403                 gp_output |= epio_mask;
 404         else
 405                 gp_output &= ~epio_mask;
 406
 407         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 408
 409         /* Set the value for this EPIO */
 410         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 411         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 412 }
 413
 414 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 415 {
 416         if (pin_cfg == PIN_CFG_NA)
 417                 return;
 418         if (pin_cfg >= PIN_CFG_EPIO0) {
 419                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 420         } else {
 421                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 422                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 423                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 424         }
 425 }
 426
 427 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 428 {
 429         if (pin_cfg == PIN_CFG_NA)
 430                 return -EINVAL;
 431         if (pin_cfg >= PIN_CFG_EPIO0) {
 432                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 433         } else {
 434                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 435                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 436                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 437         }
 438         return 0;
 439
 440 }
 441 /******************************************************************/
 442 /*                              ETS section                       */
 443 /******************************************************************/
 444 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 445 {
 446         /* ETS disabled configuration*/
 447         struct bnx2x *bp = params->bp;
 448
 449         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 450
 451         /* mapping between entry  priority to client number (0,1,2 -debug and
 452          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 453          * 3bits client num.
 454          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 455          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 456          */
 457
 458         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 459         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 460          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 461          * COS0 entry, 4 - COS1 entry.
 462          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 463          * bit4   bit3    bit2   bit1     bit0
 464          * MCP and debug are strict
 465          */
 466
 467         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 468         /* defines which entries (clients) are subjected to WFQ arbitration */
 469         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 470         /* For strict priority entries defines the number of consecutive
 471          * slots for the highest priority.
 472          */
 473         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 474         /* mapping between the CREDIT_WEIGHT registers and actual client
 475          * numbers
 476          */
 477         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 478         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 479         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 480
 481         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 482         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 483         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 484         /* ETS mode disable */
 485         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 486         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 487          * weight for COS0/COS1.
 488          */
 489         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 490         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 491         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 492         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 493         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 494         /* Defines the number of consecutive slots for the strict priority */
 495         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 496 }
 497 /******************************************************************************
 498 * Description:
 499 *       Getting min_w_val will be set according to line speed .
 500 *.
 501 ******************************************************************************/
 502 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 503 {
 504         u32 min_w_val = 0;
 505         /* Calculate min_w_val.*/
 506         if (vars->link_up) {
 507                 if (vars->line_speed == SPEED_20000)
 508                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 509                 else
 510                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 511         } else
 512                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 513         /* If the link isn't up (static configuration for example ) The
 514          * link will be according to 20GBPS.
 515          */
 516         return min_w_val;
 517 }
 518 /******************************************************************************
 519 * Description:
 520 *       Getting credit upper bound form min_w_val.
 521 *.
 522 ******************************************************************************/
 523 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 524 {
 525         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 526                                                 MAX_PACKET_SIZE);
 527         return credit_upper_bound;
 528 }
 529 /******************************************************************************
 530 * Description:
 531 *       Set credit upper bound for NIG.
 532 *.
 533 ******************************************************************************/
 534 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 535         const struct link_params *params,
 536         const u32 min_w_val)
 537 {
 538         struct bnx2x *bp = params->bp;
 539         const u8 port = params->port;
 540         const u32 credit_upper_bound =
 541             bnx2x_ets_get_credit_upper_bound(min_w_val);
 542
 543         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 544                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 545         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 546                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 547         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 548                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 549         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 550                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 551         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 552                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 553         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 554                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 555
 556         if (!port) {
 557                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 558                         credit_upper_bound);
 559                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 560                         credit_upper_bound);
 561                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 562                         credit_upper_bound);
 563         }
 564 }
 565 /******************************************************************************
 566 * Description:
 567 *       Will return the NIG ETS registers to init values.Except
 568 *       credit_upper_bound.
 569 *       That isn't used in this configuration (No WFQ is enabled) and will be
 570 *       configured according to spec
 571 *.
 572 ******************************************************************************/
 573 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 574                                         const struct link_vars *vars)
 575 {
 576         struct bnx2x *bp = params->bp;
 577         const u8 port = params->port;
 578         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 579         /* Mapping between entry  priority to client number (0,1,2 -debug and
 580          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 581          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 582          * reset value or init tool
 583          */
 584         if (port) {
 585                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 586                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 587         } else {
 588                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 589                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 590         }
 591         /* For strict priority entries defines the number of consecutive
 592          * slots for the highest priority.
 593          */
 594         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 595                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 596         /* Mapping between the CREDIT_WEIGHT registers and actual client
 597          * numbers
 598          */
 599         if (port) {
 600                 /*Port 1 has 6 COS*/
 601                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 602                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 603         } else {
 604                 /*Port 0 has 9 COS*/
 605                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 606                        0x43210876);
 607                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 608         }
 609
 610         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 611          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 612          * COS0 entry, 4 - COS1 entry.
 613          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 614          * bit4   bit3    bit2   bit1     bit0
 615          * MCP and debug are strict
 616          */
 617         if (port)
 618                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 619         else
 620                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 621         /* defines which entries (clients) are subjected to WFQ arbitration */
 622         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 623                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 624
 625         /* Please notice the register address are note continuous and a
 626          * for here is note appropriate.In 2 port mode port0 only COS0-5
 627          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 628          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 629          * are never used for WFQ
 630          */
 631         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 632                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 633         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 634                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 635         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 636                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 637         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 638                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 639         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 640                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 641         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 642                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 643         if (!port) {
 644                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 645                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 646                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 647         }
 648
 649         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 650 }
 651 /******************************************************************************
 652 * Description:
 653 *       Set credit upper bound for PBF.
 654 *.
 655 ******************************************************************************/
 656 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 657         const struct link_params *params,
 658         const u32 min_w_val)
 659 {
 660         struct bnx2x *bp = params->bp;
 661         const u32 credit_upper_bound =
 662             bnx2x_ets_get_credit_upper_bound(min_w_val);
 663         const u8 port = params->port;
 664         u32 base_upper_bound = 0;
 665         u8 max_cos = 0;
 666         u8 i = 0;
 667         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 668          * port mode port1 has COS0-2 that can be used for WFQ.
 669          */
 670         if (!port) {
 671                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 672                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 673         } else {
 674                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 675                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 676         }
 677
 678         for (i = 0; i < max_cos; i++)
 679                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 680 }
 681
 682 /******************************************************************************
 683 * Description:
 684 *       Will return the PBF ETS registers to init values.Except
 685 *       credit_upper_bound.
 686 *       That isn't used in this configuration (No WFQ is enabled) and will be
 687 *       configured according to spec
 688 *.
 689 ******************************************************************************/
 690 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 691 {
 692         struct bnx2x *bp = params->bp;
 693         const u8 port = params->port;
 694         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 695         u8 i = 0;
 696         u32 base_weight = 0;
 697         u8 max_cos = 0;
 698
 699         /* Mapping between entry  priority to client number 0 - COS0
 700          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 701          * TODO_ETS - Should be done by reset value or init tool
 702          */
 703         if (port)
 704                 /*  0x688 (|011|0 10|00 1|000) */
 705                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 706         else
 707                 /*  (10 1|100 |011|0 10|00 1|000) */
 708                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 709
 710         /* TODO_ETS - Should be done by reset value or init tool */
 711         if (port)
 712                 /* 0x688 (|011|0 10|00 1|000)*/
 713                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 714         else
 715         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 716         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 717
 718         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 719                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 720
 721
 722         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 723                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 724
 725         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 726                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 727         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 728          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 729          */
 730         if (!port) {
 731                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 732                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 733         } else {
 734                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 735                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 736         }
 737
 738         for (i = 0; i < max_cos; i++)
 739                 REG_WR(bp, base_weight + (0x4 * i), 0);
 740
 741         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 742 }
 743 /******************************************************************************
 744 * Description:
 745 *       E3B0 disable will return basically the values to init values.
 746 *.
 747 ******************************************************************************/
 748 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 749                                    const struct link_vars *vars)
 750 {
 751         struct bnx2x *bp = params->bp;
 752
 753         if (!CHIP_IS_E3B0(bp)) {
 754                 DP(NETIF_MSG_LINK,
 755                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 756                 return -EINVAL;
 757         }
 758
 759         bnx2x_ets_e3b0_nig_disabled(params, vars);
 760
 761         bnx2x_ets_e3b0_pbf_disabled(params);
 762
 763         return 0;
 764 }
 765
 766 /******************************************************************************
 767 * Description:
 768 *       Disable will return basically the values to init values.
 769 *
 770 ******************************************************************************/
 771 int bnx2x_ets_disabled(struct link_params *params,
 772                       struct link_vars *vars)
 773 {
 774         struct bnx2x *bp = params->bp;
 775         int bnx2x_status = 0;
 776
 777         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 778                 bnx2x_ets_e2e3a0_disabled(params);
 779         else if (CHIP_IS_E3B0(bp))
 780                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 781         else {
 782                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 783                 return -EINVAL;
 784         }
 785
 786         return bnx2x_status;
 787 }
 788
 789 /******************************************************************************
 790 * Description
 791 *       Set the COS mappimg to SP and BW until this point all the COS are not
 792 *       set as SP or BW.
 793 ******************************************************************************/
 794 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 795                                   const struct bnx2x_ets_params *ets_params,
 796                                   const u8 cos_sp_bitmap,
 797                                   const u8 cos_bw_bitmap)
 798 {
 799         struct bnx2x *bp = params->bp;
 800         const u8 port = params->port;
 801         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 802         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 803         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 804         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 805
 806         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 807                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 808
 809         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 810                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 811
 812         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 813                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 814                nig_cli_subject2wfq_bitmap);
 815
 816         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 817                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 818                pbf_cli_subject2wfq_bitmap);
 819
 820         return 0;
 821 }
 822
 823 /******************************************************************************
 824 * Description:
 825 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 826 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 827 ******************************************************************************/
 828 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 829                                      const u8 cos_entry,
 830                                      const u32 min_w_val_nig,
 831                                      const u32 min_w_val_pbf,
 832                                      const u16 total_bw,
 833                                      const u8 bw,
 834                                      const u8 port)
 835 {
 836         u32 nig_reg_adress_crd_weight = 0;
 837         u32 pbf_reg_adress_crd_weight = 0;
 838         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 839         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 840         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 841
 842         switch (cos_entry) {
 843         case 0:
 844             nig_reg_adress_crd_weight =
 845                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 846                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 847              pbf_reg_adress_crd_weight = (port) ?
 848                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 849              break;
 850         case 1:
 851              nig_reg_adress_crd_weight = (port) ?
 852                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 853                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 854              pbf_reg_adress_crd_weight = (port) ?
 855                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 856              break;
 857         case 2:
 858              nig_reg_adress_crd_weight = (port) ?
 859                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 860                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 861
 862                  pbf_reg_adress_crd_weight = (port) ?
 863                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 864              break;
 865         case 3:
 866             if (port)
 867                         return -EINVAL;
 868              nig_reg_adress_crd_weight =
 869                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 870              pbf_reg_adress_crd_weight =
 871                  PBF_REG_COS3_WEIGHT_P0;
 872              break;
 873         case 4:
 874             if (port)
 875                 return -EINVAL;
 876              nig_reg_adress_crd_weight =
 877                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 878              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 879              break;
 880         case 5:
 881             if (port)
 882                 return -EINVAL;
 883              nig_reg_adress_crd_weight =
 884                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 885              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 886              break;
 887         }
 888
 889         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 890
 891         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 892
 893         return 0;
 894 }
 895 /******************************************************************************
 896 * Description:
 897 *       Calculate the total BW.A value of 0 isn't legal.
 898 *
 899 ******************************************************************************/
 900 static int bnx2x_ets_e3b0_get_total_bw(
 901         const struct link_params *params,
 902         struct bnx2x_ets_params *ets_params,
 903         u16 *total_bw)
 904 {
 905         struct bnx2x *bp = params->bp;
 906         u8 cos_idx = 0;
 907         u8 is_bw_cos_exist = 0;
 908
 909         *total_bw = 0 ;
 910         /* Calculate total BW requested */
 911         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 912                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 913                         is_bw_cos_exist = 1;
 914                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 915                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 916                                                    "was set to 0\n");
 917                                 /* This is to prevent a state when ramrods
 918                                  * can't be sent
 919                                  */
 920                                 ets_params->cos[cos_idx].params.bw_params.bw
 921                                          = 1;
 922                         }
 923                         *total_bw +=
 924                                 ets_params->cos[cos_idx].params.bw_params.bw;
 925                 }
 926         }
 927
 928         /* Check total BW is valid */
 929         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 930                 if (*total_bw == 0) {
 931                         DP(NETIF_MSG_LINK,
 932                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 933                         return -EINVAL;
 934                 }
 935                 DP(NETIF_MSG_LINK,
 936                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 937                 /* We can handle a case whre the BW isn't 100 this can happen
 938                  * if the TC are joined.
 939                  */
 940         }
 941         return 0;
 942 }
 943
 944 /******************************************************************************
 945 * Description:
 946 *       Invalidate all the sp_pri_to_cos.
 947 *
 948 ******************************************************************************/
 949 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 950 {
 951         u8 pri = 0;
 952         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 953                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 954 }
 955 /******************************************************************************
 956 * Description:
 957 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 958 *       according to sp_pri_to_cos.
 959 *
 960 ******************************************************************************/
 961 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 962                                             u8 *sp_pri_to_cos, const u8 pri,
 963                                             const u8 cos_entry)
 964 {
 965         struct bnx2x *bp = params->bp;
 966         const u8 port = params->port;
 967         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 968                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 969
 970         if (pri >= max_num_of_cos) {
 971                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 972                    "parameter Illegal strict priority\n");
 973             return -EINVAL;
 974         }
 975
 976         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 977                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 978                                    "parameter There can't be two COS's with "
 979                                    "the same strict pri\n");
 980                 return -EINVAL;
 981         }
 982
 983         sp_pri_to_cos[pri] = cos_entry;
 984         return 0;
 985
 986 }
 987
 988 /******************************************************************************
 989 * Description:
 990 *       Returns the correct value according to COS and priority in
 991 *       the sp_pri_cli register.
 992 *
 993 ******************************************************************************/
 994 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 995                                          const u8 pri_set,
 996                                          const u8 pri_offset,
 997                                          const u8 entry_size)
 998 {
 999         u64 pri_cli_nig = 0;
1000         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
1001                                                     (pri_set + pri_offset));
1002
1003         return pri_cli_nig;
1004 }
1005 /******************************************************************************
1006 * Description:
1007 *       Returns the correct value according to COS and priority in the
1008 *       sp_pri_cli register for NIG.
1009 *
1010 ******************************************************************************/
1011 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
1012 {
1013         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1014         const u8 nig_cos_offset = 3;
1015         const u8 nig_pri_offset = 3;
1016
1017         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1018                 nig_pri_offset, 4);
1019
1020 }
1021 /******************************************************************************
1022 * Description:
1023 *       Returns the correct value according to COS and priority in the
1024 *       sp_pri_cli register for PBF.
1025 *
1026 ******************************************************************************/
1027 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1028 {
1029         const u8 pbf_cos_offset = 0;
1030         const u8 pbf_pri_offset = 0;
1031
1032         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1033                 pbf_pri_offset, 3);
1034
1035 }
1036
1037 /******************************************************************************
1038 * Description:
1039 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1040 *       according to sp_pri_to_cos.(which COS has higher priority)
1041 *
1042 ******************************************************************************/
1043 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1044                                              u8 *sp_pri_to_cos)
1045 {
1046         struct bnx2x *bp = params->bp;
1047         u8 i = 0;
1048         const u8 port = params->port;
1049         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1050         u64 pri_cli_nig = 0x210;
1051         u32 pri_cli_pbf = 0x0;
1052         u8 pri_set = 0;
1053         u8 pri_bitmask = 0;
1054         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1055                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1056
1057         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1058
1059         /* Set all the strict priority first */
1060         for (i = 0; i < max_num_of_cos; i++) {
1061                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1062                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1063                                 DP(NETIF_MSG_LINK,
1064                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1065                                            "invalid cos entry\n");
1066                                 return -EINVAL;
1067                         }
1068
1069                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1070                             sp_pri_to_cos[i], pri_set);
1071
1072                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1073                             sp_pri_to_cos[i], pri_set);
1074                         pri_bitmask = 1 << sp_pri_to_cos[i];
1075                         /* COS is used remove it from bitmap.*/
1076                         if (!(pri_bitmask & cos_bit_to_set)) {
1077                                 DP(NETIF_MSG_LINK,
1078                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1079                                         "invalid There can't be two COS's with"
1080                                         " the same strict pri\n");
1081                                 return -EINVAL;
1082                         }
1083                         cos_bit_to_set &= ~pri_bitmask;
1084                         pri_set++;
1085                 }
1086         }
1087
1088         /* Set all the Non strict priority i= COS*/
1089         for (i = 0; i < max_num_of_cos; i++) {
1090                 pri_bitmask = 1 << i;
1091                 /* Check if COS was already used for SP */
1092                 if (pri_bitmask & cos_bit_to_set) {
1093                         /* COS wasn't used for SP */
1094                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1095                             i, pri_set);
1096
1097                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1098                             i, pri_set);
1099                         /* COS is used remove it from bitmap.*/
1100                         cos_bit_to_set &= ~pri_bitmask;
1101                         pri_set++;
1102                 }
1103         }
1104
1105         if (pri_set != max_num_of_cos) {
1106                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1107                                    "entries were set\n");
1108                 return -EINVAL;
1109         }
1110
1111         if (port) {
1112                 /* Only 6 usable clients*/
1113                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1114                        (u32)pri_cli_nig);
1115
1116                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1117         } else {
1118                 /* Only 9 usable clients*/
1119                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1120                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1121
1122                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1123                        pri_cli_nig_lsb);
1124                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1125                        pri_cli_nig_msb);
1126
1127                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1128         }
1129         return 0;
1130 }
1131
1132 /******************************************************************************
1133 * Description:
1134 *       Configure the COS to ETS according to BW and SP settings.
1135 ******************************************************************************/
1136 int bnx2x_ets_e3b0_config(const struct link_params *params,
1137                          const struct link_vars *vars,
1138                          struct bnx2x_ets_params *ets_params)
1139 {
1140         struct bnx2x *bp = params->bp;
1141         int bnx2x_status = 0;
1142         const u8 port = params->port;
1143         u16 total_bw = 0;
1144         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1145         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1146         u8 cos_bw_bitmap = 0;
1147         u8 cos_sp_bitmap = 0;
1148         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1149         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1150                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1151         u8 cos_entry = 0;
1152
1153         if (!CHIP_IS_E3B0(bp)) {
1154                 DP(NETIF_MSG_LINK,
1155                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1156                 return -EINVAL;
1157         }
1158
1159         if ((ets_params->num_of_cos > max_num_of_cos)) {
1160                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1161                                    "isn't supported\n");
1162                 return -EINVAL;
1163         }
1164
1165         /* Prepare sp strict priority parameters*/
1166         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1167
1168         /* Prepare BW parameters*/
1169         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1170                                                    &total_bw);
1171         if (bnx2x_status) {
1172                 DP(NETIF_MSG_LINK,
1173                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1174                 return -EINVAL;
1175         }
1176
1177         /* Upper bound is set according to current link speed (min_w_val
1178          * should be the same for upper bound and COS credit val).
1179          */
1180         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1181         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1182
1183
1184         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1185                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1186                         cos_bw_bitmap |= (1 << cos_entry);
1187                         /* The function also sets the BW in HW(not the mappin
1188                          * yet)
1189                          */
1190                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1191                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1192                                 total_bw,
1193                                 ets_params->cos[cos_entry].params.bw_params.bw,
1194                                  port);
1195                 } else if (bnx2x_cos_state_strict ==
1196                         ets_params->cos[cos_entry].state){
1197                         cos_sp_bitmap |= (1 << cos_entry);
1198
1199                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1200                                 params,
1201                                 sp_pri_to_cos,
1202                                 ets_params->cos[cos_entry].params.sp_params.pri,
1203                                 cos_entry);
1204
1205                 } else {
1206                         DP(NETIF_MSG_LINK,
1207                            "bnx2x_ets_e3b0_config cos state not valid\n");
1208                         return -EINVAL;
1209                 }
1210                 if (bnx2x_status) {
1211                         DP(NETIF_MSG_LINK,
1212                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1213                         return bnx2x_status;
1214                 }
1215         }
1216
1217         /* Set SP register (which COS has higher priority) */
1218         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1219                                                          sp_pri_to_cos);
1220
1221         if (bnx2x_status) {
1222                 DP(NETIF_MSG_LINK,
1223                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1224                 return bnx2x_status;
1225         }
1226
1227         /* Set client mapping of BW and strict */
1228         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1229                                               cos_sp_bitmap,
1230                                               cos_bw_bitmap);
1231
1232         if (bnx2x_status) {
1233                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1234                 return bnx2x_status;
1235         }
1236         return 0;
1237 }
1238 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1239 {
1240         /* ETS disabled configuration */
1241         struct bnx2x *bp = params->bp;
1242         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1243         /* Defines which entries (clients) are subjected to WFQ arbitration
1244          * COS0 0x8
1245          * COS1 0x10
1246          */
1247         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1248         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1249          * client numbers (WEIGHT_0 does not actually have to represent
1250          * client 0)
1251          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1252          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1253          */
1254         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1255
1256         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1257                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1258         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1259                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1260
1261         /* ETS mode enabled*/
1262         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1263
1264         /* Defines the number of consecutive slots for the strict priority */
1265         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1266         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1267          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1268          * entry, 4 - COS1 entry.
1269          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1270          * bit4   bit3    bit2     bit1    bit0
1271          * MCP and debug are strict
1272          */
1273         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1274
1275         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1276         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1277                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1278         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1279                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1280 }
1281
1282 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1283                         const u32 cos1_bw)
1284 {
1285         /* ETS disabled configuration*/
1286         struct bnx2x *bp = params->bp;
1287         const u32 total_bw = cos0_bw + cos1_bw;
1288         u32 cos0_credit_weight = 0;
1289         u32 cos1_credit_weight = 0;
1290
1291         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1292
1293         if ((!total_bw) ||
1294             (!cos0_bw) ||
1295             (!cos1_bw)) {
1296                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1297                 return;
1298         }
1299
1300         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1301                 total_bw;
1302         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1303                 total_bw;
1304
1305         bnx2x_ets_bw_limit_common(params);
1306
1307         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1308         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1309
1310         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1311         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1312 }
1313
1314 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1315 {
1316         /* ETS disabled configuration*/
1317         struct bnx2x *bp = params->bp;
1318         u32 val = 0;
1319
1320         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1321         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1322          * as strict.  Bits 0,1,2 - debug and management entries,
1323          * 3 - COS0 entry, 4 - COS1 entry.
1324          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1325          *  bit4   bit3   bit2      bit1     bit0
1326          * MCP and debug are strict
1327          */
1328         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1329         /* For strict priority entries defines the number of consecutive slots
1330          * for the highest priority.
1331          */
1332         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1333         /* ETS mode disable */
1334         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1335         /* Defines the number of consecutive slots for the strict priority */
1336         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1337
1338         /* Defines the number of consecutive slots for the strict priority */
1339         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1340
1341         /* Mapping between entry  priority to client number (0,1,2 -debug and
1342          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1343          * 3bits client num.
1344          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1345          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1346          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1347          */
1348         val = (!strict_cos) ? 0x2318 : 0x22E0;
1349         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1350
1351         return 0;
1352 }
1353
1354 /******************************************************************/
1355 /*                      PFC section                               */
1356 /******************************************************************/
1357 static void bnx2x_update_pfc_xmac(struct link_params *params,
1358                                   struct link_vars *vars,
1359                                   u8 is_lb)
1360 {
1361         struct bnx2x *bp = params->bp;
1362         u32 xmac_base;
1363         u32 pause_val, pfc0_val, pfc1_val;
1364
1365         /* XMAC base adrr */
1366         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1367
1368         /* Initialize pause and pfc registers */
1369         pause_val = 0x18000;
1370         pfc0_val = 0xFFFF8000;
1371         pfc1_val = 0x2;
1372
1373         /* No PFC support */
1374         if (!(params->feature_config_flags &
1375               FEATURE_CONFIG_PFC_ENABLED)) {
1376
1377                 /* RX flow control - Process pause frame in receive direction
1378                  */
1379                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1380                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1381
1382                 /* TX flow control - Send pause packet when buffer is full */
1383                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1384                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1385         } else {/* PFC support */
1386                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1387                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1388                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1389                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1390                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1391                 /* Write pause and PFC registers */
1392                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1393                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1394                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1395                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1396
1397         }
1398
1399         /* Write pause and PFC registers */
1400         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1401         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1402         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1403
1404
1405         /* Set MAC address for source TX Pause/PFC frames */
1406         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1407                ((params->mac_addr[2] << 24) |
1408                 (params->mac_addr[3] << 16) |
1409                 (params->mac_addr[4] << 8) |
1410                 (params->mac_addr[5])));
1411         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1412                ((params->mac_addr[0] << 8) |
1413                 (params->mac_addr[1])));
1414
1415         udelay(30);
1416 }
1417
1418 /******************************************************************/
1419 /*                      MAC/PBF section                           */
1420 /******************************************************************/
1421 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1422                                u32 emac_base)
1423 {
1424         u32 new_mode, cur_mode;
1425         u32 clc_cnt;
1426         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1427          * (a value of 49==0x31) and make sure that the AUTO poll is off
1428          */
1429         cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1430
1431         if (USES_WARPCORE(bp))
1432                 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1433         else
1434                 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1435
1436         if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1437             (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1438                 return;
1439
1440         new_mode = cur_mode &
1441                 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1442         new_mode |= clc_cnt;
1443         new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1444
1445         DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1446            cur_mode, new_mode);
1447         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1448         udelay(40);
1449 }
1450
1451 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1452                                         struct link_params *params)
1453 {
1454         u8 phy_index;
1455         /* Set mdio clock per phy */
1456         for (phy_index = INT_PHY; phy_index < params->num_phys;
1457               phy_index++)
1458                 bnx2x_set_mdio_clk(bp, params->chip_id,
1459                                    params->phy[phy_index].mdio_ctrl);
1460 }
1461
1462 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1463 {
1464         u32 port4mode_ovwr_val;
1465         /* Check 4-port override enabled */
1466         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1467         if (port4mode_ovwr_val & (1<<0)) {
1468                 /* Return 4-port mode override value */
1469                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1470         }
1471         /* Return 4-port mode from input pin */
1472         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1473 }
1474
1475 static void bnx2x_emac_init(struct link_params *params,
1476                             struct link_vars *vars)
1477 {
1478         /* reset and unreset the emac core */
1479         struct bnx2x *bp = params->bp;
1480         u8 port = params->port;
1481         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1482         u32 val;
1483         u16 timeout;
1484
1485         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1486                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1487         udelay(5);
1488         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1489                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1490
1491         /* init emac - use read-modify-write */
1492         /* self clear reset */
1493         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1494         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1495
1496         timeout = 200;
1497         do {
1498                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1499                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1500                 if (!timeout) {
1501                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1502                         return;
1503                 }
1504                 timeout--;
1505         } while (val & EMAC_MODE_RESET);
1506
1507         bnx2x_set_mdio_emac_per_phy(bp, params);
1508         /* Set mac address */
1509         val = ((params->mac_addr[0] << 8) |
1510                 params->mac_addr[1]);
1511         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1512
1513         val = ((params->mac_addr[2] << 24) |
1514                (params->mac_addr[3] << 16) |
1515                (params->mac_addr[4] << 8) |
1516                 params->mac_addr[5]);
1517         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1518 }
1519
1520 static void bnx2x_set_xumac_nig(struct link_params *params,
1521                                 u16 tx_pause_en,
1522                                 u8 enable)
1523 {
1524         struct bnx2x *bp = params->bp;
1525
1526         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1527                enable);
1528         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1529                enable);
1530         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1531                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1532 }
1533
1534 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1535 {
1536         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1537         u32 val;
1538         struct bnx2x *bp = params->bp;
1539         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1540                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1541                 return;
1542         val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1543         if (en)
1544                 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1545                         UMAC_COMMAND_CONFIG_REG_RX_ENA);
1546         else
1547                 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1548                          UMAC_COMMAND_CONFIG_REG_RX_ENA);
1549         /* Disable RX and TX */
1550         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1551 }
1552
1553 static void bnx2x_umac_enable(struct link_params *params,
1554                             struct link_vars *vars, u8 lb)
1555 {
1556         u32 val;
1557         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1558         struct bnx2x *bp = params->bp;
1559         /* Reset UMAC */
1560         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1561                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1562         usleep_range(1000, 2000);
1563
1564         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1565                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1566
1567         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1568
1569         /* This register opens the gate for the UMAC despite its name */
1570         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1571
1572         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1573                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1574                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1575                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1576         switch (vars->line_speed) {
1577         case SPEED_10:
1578                 val |= (0<<2);
1579                 break;
1580         case SPEED_100:
1581                 val |= (1<<2);
1582                 break;
1583         case SPEED_1000:
1584                 val |= (2<<2);
1585                 break;
1586         case SPEED_2500:
1587                 val |= (3<<2);
1588                 break;
1589         default:
1590                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1591                                vars->line_speed);
1592                 break;
1593         }
1594         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1595                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1596
1597         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1598                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1599
1600         if (vars->duplex == DUPLEX_HALF)
1601                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1602
1603         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1604         udelay(50);
1605
1606         /* Configure UMAC for EEE */
1607         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1608                 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1609                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1610                        UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1611                 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1612         } else {
1613                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1614         }
1615
1616         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1617         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1618                ((params->mac_addr[2] << 24) |
1619                 (params->mac_addr[3] << 16) |
1620                 (params->mac_addr[4] << 8) |
1621                 (params->mac_addr[5])));
1622         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1623                ((params->mac_addr[0] << 8) |
1624                 (params->mac_addr[1])));
1625
1626         /* Enable RX and TX */
1627         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1628         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1629                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1630         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1631         udelay(50);
1632
1633         /* Remove SW Reset */
1634         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1635
1636         /* Check loopback mode */
1637         if (lb)
1638                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1639         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1640
1641         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1642          * length used by the MAC receive logic to check frames.
1643          */
1644         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1645         bnx2x_set_xumac_nig(params,
1646                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1647         vars->mac_type = MAC_TYPE_UMAC;
1648
1649 }
1650
1651 /* Define the XMAC mode */
1652 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1653 {
1654         struct bnx2x *bp = params->bp;
1655         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1656
1657         /* In 4-port mode, need to set the mode only once, so if XMAC is
1658          * already out of reset, it means the mode has already been set,
1659          * and it must not* reset the XMAC again, since it controls both
1660          * ports of the path
1661          */
1662
1663         if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1664              (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1665              (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1666             is_port4mode &&
1667             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1668              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1669                 DP(NETIF_MSG_LINK,
1670                    "XMAC already out of reset in 4-port mode\n");
1671                 return;
1672         }
1673
1674         /* Hard reset */
1675         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1676                MISC_REGISTERS_RESET_REG_2_XMAC);
1677         usleep_range(1000, 2000);
1678
1679         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1680                MISC_REGISTERS_RESET_REG_2_XMAC);
1681         if (is_port4mode) {
1682                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1683
1684                 /* Set the number of ports on the system side to up to 2 */
1685                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1686
1687                 /* Set the number of ports on the Warp Core to 10G */
1688                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1689         } else {
1690                 /* Set the number of ports on the system side to 1 */
1691                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1692                 if (max_speed == SPEED_10000) {
1693                         DP(NETIF_MSG_LINK,
1694                            "Init XMAC to 10G x 1 port per path\n");
1695                         /* Set the number of ports on the Warp Core to 10G */
1696                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1697                 } else {
1698                         DP(NETIF_MSG_LINK,
1699                            "Init XMAC to 20G x 2 ports per path\n");
1700                         /* Set the number of ports on the Warp Core to 20G */
1701                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1702                 }
1703         }
1704         /* Soft reset */
1705         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1706                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1707         usleep_range(1000, 2000);
1708
1709         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1710                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1711
1712 }
1713
1714 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1715 {
1716         u8 port = params->port;
1717         struct bnx2x *bp = params->bp;
1718         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1719         u32 val;
1720
1721         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1722             MISC_REGISTERS_RESET_REG_2_XMAC) {
1723                 /* Send an indication to change the state in the NIG back to XON
1724                  * Clearing this bit enables the next set of this bit to get
1725                  * rising edge
1726                  */
1727                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1728                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1729                        (pfc_ctrl & ~(1<<1)));
1730                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1731                        (pfc_ctrl | (1<<1)));
1732                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1733                 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1734                 if (en)
1735                         val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1736                 else
1737                         val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1738                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1739         }
1740 }
1741
1742 static int bnx2x_xmac_enable(struct link_params *params,
1743                              struct link_vars *vars, u8 lb)
1744 {
1745         u32 val, xmac_base;
1746         struct bnx2x *bp = params->bp;
1747         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1748
1749         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1750
1751         bnx2x_xmac_init(params, vars->line_speed);
1752
1753         /* This register determines on which events the MAC will assert
1754          * error on the i/f to the NIG along w/ EOP.
1755          */
1756
1757         /* This register tells the NIG whether to send traffic to UMAC
1758          * or XMAC
1759          */
1760         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1761
1762         /* When XMAC is in XLGMII mode, disable sending idles for fault
1763          * detection.
1764          */
1765         if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1766                 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1767                        (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1768                         XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1769                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1770                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1771                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1772                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1773         }
1774         /* Set Max packet size */
1775         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1776
1777         /* CRC append for Tx packets */
1778         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1779
1780         /* update PFC */
1781         bnx2x_update_pfc_xmac(params, vars, 0);
1782
1783         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1784                 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1785                 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1786                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1787         } else {
1788                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1789         }
1790
1791         /* Enable TX and RX */
1792         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1793
1794         /* Set MAC in XLGMII mode for dual-mode */
1795         if ((vars->line_speed == SPEED_20000) &&
1796             (params->phy[INT_PHY].supported &
1797              SUPPORTED_20000baseKR2_Full))
1798                 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1799
1800         /* Check loopback mode */
1801         if (lb)
1802                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1803         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1804         bnx2x_set_xumac_nig(params,
1805                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1806
1807         vars->mac_type = MAC_TYPE_XMAC;
1808
1809         return 0;
1810 }
1811
1812 static int bnx2x_emac_enable(struct link_params *params,
1813                              struct link_vars *vars, u8 lb)
1814 {
1815         struct bnx2x *bp = params->bp;
1816         u8 port = params->port;
1817         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1818         u32 val;
1819
1820         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1821
1822         /* Disable BMAC */
1823         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1824                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1825
1826         /* enable emac and not bmac */
1827         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1828
1829         /* ASIC */
1830         if (vars->phy_flags & PHY_XGXS_FLAG) {
1831                 u32 ser_lane = ((params->lane_config &
1832                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1833                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1834
1835                 DP(NETIF_MSG_LINK, "XGXS\n");
1836                 /* select the master lanes (out of 0-3) */
1837                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1838                 /* select XGXS */
1839                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1840
1841         } else { /* SerDes */
1842                 DP(NETIF_MSG_LINK, "SerDes\n");
1843                 /* select SerDes */
1844                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1845         }
1846
1847         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1848                       EMAC_RX_MODE_RESET);
1849         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1850                       EMAC_TX_MODE_RESET);
1851
1852                 /* pause enable/disable */
1853                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1854                                EMAC_RX_MODE_FLOW_EN);
1855
1856                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1857                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1858                                 EMAC_TX_MODE_FLOW_EN));
1859                 if (!(params->feature_config_flags &
1860                       FEATURE_CONFIG_PFC_ENABLED)) {
1861                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1862                                 bnx2x_bits_en(bp, emac_base +
1863                                               EMAC_REG_EMAC_RX_MODE,
1864                                               EMAC_RX_MODE_FLOW_EN);
1865
1866                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1867                                 bnx2x_bits_en(bp, emac_base +
1868                                               EMAC_REG_EMAC_TX_MODE,
1869                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1870                                                EMAC_TX_MODE_FLOW_EN));
1871                 } else
1872                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1873                                       EMAC_TX_MODE_FLOW_EN);
1874
1875         /* KEEP_VLAN_TAG, promiscuous */
1876         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1877         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1878
1879         /* Setting this bit causes MAC control frames (except for pause
1880          * frames) to be passed on for processing. This setting has no
1881          * affect on the operation of the pause frames. This bit effects
1882          * all packets regardless of RX Parser packet sorting logic.
1883          * Turn the PFC off to make sure we are in Xon state before
1884          * enabling it.
1885          */
1886         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1887         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1888                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1889                 /* Enable PFC again */
1890                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1891                         EMAC_REG_RX_PFC_MODE_RX_EN |
1892                         EMAC_REG_RX_PFC_MODE_TX_EN |
1893                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1894
1895                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1896                         ((0x0101 <<
1897                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1898                          (0x00ff <<
1899                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1900                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1901         }
1902         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1903
1904         /* Set Loopback */
1905         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1906         if (lb)
1907                 val |= 0x810;
1908         else
1909                 val &= ~0x810;
1910         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1911
1912         /* Enable emac */
1913         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1914
1915         /* Enable emac for jumbo packets */
1916         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1917                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1918                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1919
1920         /* Strip CRC */
1921         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1922
1923         /* Disable the NIG in/out to the bmac */
1924         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1925         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1926         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1927
1928         /* Enable the NIG in/out to the emac */
1929         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1930         val = 0;
1931         if ((params->feature_config_flags &
1932               FEATURE_CONFIG_PFC_ENABLED) ||
1933             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1934                 val = 1;
1935
1936         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1937         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1938
1939         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1940
1941         vars->mac_type = MAC_TYPE_EMAC;
1942         return 0;
1943 }
1944
1945 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1946                                    struct link_vars *vars)
1947 {
1948         u32 wb_data[2];
1949         struct bnx2x *bp = params->bp;
1950         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1951                 NIG_REG_INGRESS_BMAC0_MEM;
1952
1953         u32 val = 0x14;
1954         if ((!(params->feature_config_flags &
1955               FEATURE_CONFIG_PFC_ENABLED)) &&
1956                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1957                 /* Enable BigMAC to react on received Pause packets */
1958                 val |= (1<<5);
1959         wb_data[0] = val;
1960         wb_data[1] = 0;
1961         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1962
1963         /* TX control */
1964         val = 0xc0;
1965         if (!(params->feature_config_flags &
1966               FEATURE_CONFIG_PFC_ENABLED) &&
1967                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1968                 val |= 0x800000;
1969         wb_data[0] = val;
1970         wb_data[1] = 0;
1971         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1972 }
1973
1974 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1975                                    struct link_vars *vars,
1976                                    u8 is_lb)
1977 {
1978         /* Set rx control: Strip CRC and enable BigMAC to relay
1979          * control packets to the system as well
1980          */
1981         u32 wb_data[2];
1982         struct bnx2x *bp = params->bp;
1983         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1984                 NIG_REG_INGRESS_BMAC0_MEM;
1985         u32 val = 0x14;
1986
1987         if ((!(params->feature_config_flags &
1988               FEATURE_CONFIG_PFC_ENABLED)) &&
1989                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1990                 /* Enable BigMAC to react on received Pause packets */
1991                 val |= (1<<5);
1992         wb_data[0] = val;
1993         wb_data[1] = 0;
1994         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1995         udelay(30);
1996
1997         /* Tx control */
1998         val = 0xc0;
1999         if (!(params->feature_config_flags &
2000                                 FEATURE_CONFIG_PFC_ENABLED) &&
2001             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2002                 val |= 0x800000;
2003         wb_data[0] = val;
2004         wb_data[1] = 0;
2005         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2006
2007         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2008                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2009                 /* Enable PFC RX & TX & STATS and set 8 COS  */
2010                 wb_data[0] = 0x0;
2011                 wb_data[0] |= (1<<0);  /* RX */
2012                 wb_data[0] |= (1<<1);  /* TX */
2013                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2014                 wb_data[0] |= (1<<3);  /* 8 cos */
2015                 wb_data[0] |= (1<<5);  /* STATS */
2016                 wb_data[1] = 0;
2017                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2018                             wb_data, 2);
2019                 /* Clear the force Xon */
2020                 wb_data[0] &= ~(1<<2);
2021         } else {
2022                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2023                 /* Disable PFC RX & TX & STATS and set 8 COS */
2024                 wb_data[0] = 0x8;
2025                 wb_data[1] = 0;
2026         }
2027
2028         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2029
2030         /* Set Time (based unit is 512 bit time) between automatic
2031          * re-sending of PP packets amd enable automatic re-send of
2032          * Per-Priroity Packet as long as pp_gen is asserted and
2033          * pp_disable is low.
2034          */
2035         val = 0x8000;
2036         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2037                 val |= (1<<16); /* enable automatic re-send */
2038
2039         wb_data[0] = val;
2040         wb_data[1] = 0;
2041         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2042                     wb_data, 2);
2043
2044         /* mac control */
2045         val = 0x3; /* Enable RX and TX */
2046         if (is_lb) {
2047                 val |= 0x4; /* Local loopback */
2048                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2049         }
2050         /* When PFC enabled, Pass pause frames towards the NIG. */
2051         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2052                 val |= ((1<<6)|(1<<5));
2053
2054         wb_data[0] = val;
2055         wb_data[1] = 0;
2056         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2057 }
2058
2059 /******************************************************************************
2060 * Description:
2061 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2062 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2063 ******************************************************************************/
2064 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2065                                            u8 cos_entry,
2066                                            u32 priority_mask, u8 port)
2067 {
2068         u32 nig_reg_rx_priority_mask_add = 0;
2069
2070         switch (cos_entry) {
2071         case 0:
2072              nig_reg_rx_priority_mask_add = (port) ?
2073                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2074                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2075              break;
2076         case 1:
2077             nig_reg_rx_priority_mask_add = (port) ?
2078                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2079                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2080             break;
2081         case 2:
2082             nig_reg_rx_priority_mask_add = (port) ?
2083                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2084                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2085             break;
2086         case 3:
2087             if (port)
2088                 return -EINVAL;
2089             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2090             break;
2091         case 4:
2092             if (port)
2093                 return -EINVAL;
2094             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2095             break;
2096         case 5:
2097             if (port)
2098                 return -EINVAL;
2099             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2100             break;
2101         }
2102
2103         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2104
2105         return 0;
2106 }
2107 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2108 {
2109         struct bnx2x *bp = params->bp;
2110
2111         REG_WR(bp, params->shmem_base +
2112                offsetof(struct shmem_region,
2113                         port_mb[params->port].link_status), link_status);
2114 }
2115
2116 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2117 {
2118         struct bnx2x *bp = params->bp;
2119
2120         if (SHMEM2_HAS(bp, link_attr_sync))
2121                 REG_WR(bp, params->shmem2_base +
2122                        offsetof(struct shmem2_region,
2123                                 link_attr_sync[params->port]), link_attr);
2124 }
2125
2126 static void bnx2x_update_pfc_nig(struct link_params *params,
2127                 struct link_vars *vars,
2128                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2129 {
2130         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2131         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2132         u32 pkt_priority_to_cos = 0;
2133         struct bnx2x *bp = params->bp;
2134         u8 port = params->port;
2135
2136         int set_pfc = params->feature_config_flags &
2137                 FEATURE_CONFIG_PFC_ENABLED;
2138         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2139
2140         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2141          * MAC control frames (that are not pause packets)
2142          * will be forwarded to the XCM.
2143          */
2144         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2145                           NIG_REG_LLH0_XCM_MASK);
2146         /* NIG params will override non PFC params, since it's possible to
2147          * do transition from PFC to SAFC
2148          */
2149         if (set_pfc) {
2150                 pause_enable = 0;
2151                 llfc_out_en = 0;
2152                 llfc_enable = 0;
2153                 if (CHIP_IS_E3(bp))
2154                         ppp_enable = 0;
2155                 else
2156                         ppp_enable = 1;
2157                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2158                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2159                 xcm_out_en = 0;
2160                 hwpfc_enable = 1;
2161         } else  {
2162                 if (nig_params) {
2163                         llfc_out_en = nig_params->llfc_out_en;
2164                         llfc_enable = nig_params->llfc_enable;
2165                         pause_enable = nig_params->pause_enable;
2166                 } else  /* Default non PFC mode - PAUSE */
2167                         pause_enable = 1;
2168
2169                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2170                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2171                 xcm_out_en = 1;
2172         }
2173
2174         if (CHIP_IS_E3(bp))
2175                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2176                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2177         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2178                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2179         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2180                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2181         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2182                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2183
2184         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2185                NIG_REG_PPP_ENABLE_0, ppp_enable);
2186
2187         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2188                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2189
2190         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2191                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2192
2193         /* Output enable for RX_XCM # IF */
2194         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2195                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2196
2197         /* HW PFC TX enable */
2198         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2199                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2200
2201         if (nig_params) {
2202                 u8 i = 0;
2203                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2204
2205                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2206                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2207                 nig_params->rx_cos_priority_mask[i], port);
2208
2209                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2210                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2211                        nig_params->llfc_high_priority_classes);
2212
2213                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2214                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2215                        nig_params->llfc_low_priority_classes);
2216         }
2217         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2218                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2219                pkt_priority_to_cos);
2220 }
2221
2222 int bnx2x_update_pfc(struct link_params *params,
2223                       struct link_vars *vars,
2224                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2225 {
2226         /* The PFC and pause are orthogonal to one another, meaning when
2227          * PFC is enabled, the pause are disabled, and when PFC is
2228          * disabled, pause are set according to the pause result.
2229          */
2230         u32 val;
2231         struct bnx2x *bp = params->bp;
2232         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2233
2234         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2235                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2236         else
2237                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2238
2239         bnx2x_update_mng(params, vars->link_status);
2240
2241         /* Update NIG params */
2242         bnx2x_update_pfc_nig(params, vars, pfc_params);
2243
2244         if (!vars->link_up)
2245                 return 0;
2246
2247         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2248
2249         if (CHIP_IS_E3(bp)) {
2250                 if (vars->mac_type == MAC_TYPE_XMAC)
2251                         bnx2x_update_pfc_xmac(params, vars, 0);
2252         } else {
2253                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2254                 if ((val &
2255                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2256                     == 0) {
2257                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2258                         bnx2x_emac_enable(params, vars, 0);
2259                         return 0;
2260                 }
2261                 if (CHIP_IS_E2(bp))
2262                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2263                 else
2264                         bnx2x_update_pfc_bmac1(params, vars);
2265
2266                 val = 0;
2267                 if ((params->feature_config_flags &
2268                      FEATURE_CONFIG_PFC_ENABLED) ||
2269                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2270                         val = 1;
2271                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2272         }
2273         return 0;
2274 }
2275
2276 static int bnx2x_bmac1_enable(struct link_params *params,
2277                               struct link_vars *vars,
2278                               u8 is_lb)
2279 {
2280         struct bnx2x *bp = params->bp;
2281         u8 port = params->port;
2282         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2283                                NIG_REG_INGRESS_BMAC0_MEM;
2284         u32 wb_data[2];
2285         u32 val;
2286
2287         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2288
2289         /* XGXS control */
2290         wb_data[0] = 0x3c;
2291         wb_data[1] = 0;
2292         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2293                     wb_data, 2);
2294
2295         /* TX MAC SA */
2296         wb_data[0] = ((params->mac_addr[2] << 24) |
2297                        (params->mac_addr[3] << 16) |
2298                        (params->mac_addr[4] << 8) |
2299                         params->mac_addr[5]);
2300         wb_data[1] = ((params->mac_addr[0] << 8) |
2301                         params->mac_addr[1]);
2302         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2303
2304         /* MAC control */
2305         val = 0x3;
2306         if (is_lb) {
2307                 val |= 0x4;
2308                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2309         }
2310         wb_data[0] = val;
2311         wb_data[1] = 0;
2312         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2313
2314         /* Set rx mtu */
2315         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2316         wb_data[1] = 0;
2317         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2318
2319         bnx2x_update_pfc_bmac1(params, vars);
2320
2321         /* Set tx mtu */
2322         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2323         wb_data[1] = 0;
2324         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2325
2326         /* Set cnt max size */
2327         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2328         wb_data[1] = 0;
2329         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2330
2331         /* Configure SAFC */
2332         wb_data[0] = 0x1000200;
2333         wb_data[1] = 0;
2334         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2335                     wb_data, 2);
2336
2337         return 0;
2338 }
2339
2340 static int bnx2x_bmac2_enable(struct link_params *params,
2341                               struct link_vars *vars,
2342                               u8 is_lb)
2343 {
2344         struct bnx2x *bp = params->bp;
2345         u8 port = params->port;
2346         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2347                                NIG_REG_INGRESS_BMAC0_MEM;
2348         u32 wb_data[2];
2349
2350         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2351
2352         wb_data[0] = 0;
2353         wb_data[1] = 0;
2354         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2355         udelay(30);
2356
2357         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2358         wb_data[0] = 0x3c;
2359         wb_data[1] = 0;
2360         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2361                     wb_data, 2);
2362
2363         udelay(30);
2364
2365         /* TX MAC SA */
2366         wb_data[0] = ((params->mac_addr[2] << 24) |
2367                        (params->mac_addr[3] << 16) |
2368                        (params->mac_addr[4] << 8) |
2369                         params->mac_addr[5]);
2370         wb_data[1] = ((params->mac_addr[0] << 8) |
2371                         params->mac_addr[1]);
2372         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2373                     wb_data, 2);
2374
2375         udelay(30);
2376
2377         /* Configure SAFC */
2378         wb_data[0] = 0x1000200;
2379         wb_data[1] = 0;
2380         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2381                     wb_data, 2);
2382         udelay(30);
2383
2384         /* Set RX MTU */
2385         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2386         wb_data[1] = 0;
2387         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2388         udelay(30);
2389
2390         /* Set TX MTU */
2391         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2392         wb_data[1] = 0;
2393         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2394         udelay(30);
2395         /* Set cnt max size */
2396         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2397         wb_data[1] = 0;
2398         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2399         udelay(30);
2400         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2401
2402         return 0;
2403 }
2404
2405 static int bnx2x_bmac_enable(struct link_params *params,
2406                              struct link_vars *vars,
2407                              u8 is_lb, u8 reset_bmac)
2408 {
2409         int rc = 0;
2410         u8 port = params->port;
2411         struct bnx2x *bp = params->bp;
2412         u32 val;
2413         /* Reset and unreset the BigMac */
2414         if (reset_bmac) {
2415                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2416                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2417                 usleep_range(1000, 2000);
2418         }
2419
2420         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2421                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2422
2423         /* Enable access for bmac registers */
2424         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2425
2426         /* Enable BMAC according to BMAC type*/
2427         if (CHIP_IS_E2(bp))
2428                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2429         else
2430                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2431         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2432         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2433         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2434         val = 0;
2435         if ((params->feature_config_flags &
2436               FEATURE_CONFIG_PFC_ENABLED) ||
2437             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2438                 val = 1;
2439         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2440         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2441         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2442         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2443         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2444         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2445
2446         vars->mac_type = MAC_TYPE_BMAC;
2447         return rc;
2448 }
2449
2450 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2451 {
2452         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2453                         NIG_REG_INGRESS_BMAC0_MEM;
2454         u32 wb_data[2];
2455         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2456
2457         if (CHIP_IS_E2(bp))
2458                 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2459         else
2460                 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2461         /* Only if the bmac is out of reset */
2462         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2463                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2464             nig_bmac_enable) {
2465                 /* Clear Rx Enable bit in BMAC_CONTROL register */
2466                 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2467                 if (en)
2468                         wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2469                 else
2470                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2471                 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2472                 usleep_range(1000, 2000);
2473         }
2474 }
2475
2476 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2477                             u32 line_speed)
2478 {
2479         struct bnx2x *bp = params->bp;
2480         u8 port = params->port;
2481         u32 init_crd, crd;
2482         u32 count = 1000;
2483
2484         /* Disable port */
2485         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2486
2487         /* Wait for init credit */
2488         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2489         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2490         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2491
2492         while ((init_crd != crd) && count) {
2493                 usleep_range(5000, 10000);
2494                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2495                 count--;
2496         }
2497         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2498         if (init_crd != crd) {
2499                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2500                           init_crd, crd);
2501                 return -EINVAL;
2502         }
2503
2504         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2505             line_speed == SPEED_10 ||
2506             line_speed == SPEED_100 ||
2507             line_speed == SPEED_1000 ||
2508             line_speed == SPEED_2500) {
2509                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2510                 /* Update threshold */
2511                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2512                 /* Update init credit */
2513                 init_crd = 778;         /* (800-18-4) */
2514
2515         } else {
2516                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2517                               ETH_OVREHEAD)/16;
2518                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2519                 /* Update threshold */
2520                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2521                 /* Update init credit */
2522                 switch (line_speed) {
2523                 case SPEED_10000:
2524                         init_crd = thresh + 553 - 22;
2525                         break;
2526                 default:
2527                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2528                                   line_speed);
2529                         return -EINVAL;
2530                 }
2531         }
2532         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2533         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2534                  line_speed, init_crd);
2535
2536         /* Probe the credit changes */
2537         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2538         usleep_range(5000, 10000);
2539         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2540
2541         /* Enable port */
2542         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2543         return 0;
2544 }
2545
2546 /**
2547  * bnx2x_get_emac_base - retrive emac base address
2548  *
2549  * @bp:                 driver handle
2550  * @mdc_mdio_access:    access type
2551  * @port:               port id
2552  *
2553  * This function selects the MDC/MDIO access (through emac0 or
2554  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2555  * phy has a default access mode, which could also be overridden
2556  * by nvram configuration. This parameter, whether this is the
2557  * default phy configuration, or the nvram overrun
2558  * configuration, is passed here as mdc_mdio_access and selects
2559  * the emac_base for the CL45 read/writes operations
2560  */
2561 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2562                                u32 mdc_mdio_access, u8 port)
2563 {
2564         u32 emac_base = 0;
2565         switch (mdc_mdio_access) {
2566         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2567                 break;
2568         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2569                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2570                         emac_base = GRCBASE_EMAC1;
2571                 else
2572                         emac_base = GRCBASE_EMAC0;
2573                 break;
2574         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2575                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2576                         emac_base = GRCBASE_EMAC0;
2577                 else
2578                         emac_base = GRCBASE_EMAC1;
2579                 break;
2580         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2581                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2582                 break;
2583         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2584                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2585                 break;
2586         default:
2587                 break;
2588         }
2589         return emac_base;
2590
2591 }
2592
2593 /******************************************************************/
2594 /*                      CL22 access functions                     */
2595 /******************************************************************/
2596 static int bnx2x_cl22_write(struct bnx2x *bp,
2597                                        struct bnx2x_phy *phy,
2598                                        u16 reg, u16 val)
2599 {
2600         u32 tmp, mode;
2601         u8 i;
2602         int rc = 0;
2603         /* Switch to CL22 */
2604         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2605         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2606                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2607
2608         /* Address */
2609         tmp = ((phy->addr << 21) | (reg << 16) | val |
2610                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2611                EMAC_MDIO_COMM_START_BUSY);
2612         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2613
2614         for (i = 0; i < 50; i++) {
2615                 udelay(10);
2616
2617                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2618                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2619                         udelay(5);
2620                         break;
2621                 }
2622         }
2623         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2624                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2625                 rc = -EFAULT;
2626         }
2627         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2628         return rc;
2629 }
2630
2631 static int bnx2x_cl22_read(struct bnx2x *bp,
2632                                       struct bnx2x_phy *phy,
2633                                       u16 reg, u16 *ret_val)
2634 {
2635         u32 val, mode;
2636         u16 i;
2637         int rc = 0;
2638
2639         /* Switch to CL22 */
2640         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2641         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2642                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2643
2644         /* Address */
2645         val = ((phy->addr << 21) | (reg << 16) |
2646                EMAC_MDIO_COMM_COMMAND_READ_22 |
2647                EMAC_MDIO_COMM_START_BUSY);
2648         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2649
2650         for (i = 0; i < 50; i++) {
2651                 udelay(10);
2652
2653                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2654                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2655                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2656                         udelay(5);
2657                         break;
2658                 }
2659         }
2660         if (val & EMAC_MDIO_COMM_START_BUSY) {
2661                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2662
2663                 *ret_val = 0;
2664                 rc = -EFAULT;
2665         }
2666         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2667         return rc;
2668 }
2669
2670 /******************************************************************/
2671 /*                      CL45 access functions                     */
2672 /******************************************************************/
2673 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2674                            u8 devad, u16 reg, u16 *ret_val)
2675 {
2676         u32 val;
2677         u16 i;
2678         int rc = 0;
2679         u32 chip_id;
2680         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2681                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2682                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2683                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2684         }
2685
2686         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2687                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2688                               EMAC_MDIO_STATUS_10MB);
2689         /* Address */
2690         val = ((phy->addr << 21) | (devad << 16) | reg |
2691                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2692                EMAC_MDIO_COMM_START_BUSY);
2693         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2694
2695         for (i = 0; i < 50; i++) {
2696                 udelay(10);
2697
2698                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2699                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2700                         udelay(5);
2701                         break;
2702                 }
2703         }
2704         if (val & EMAC_MDIO_COMM_START_BUSY) {
2705                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2706                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2707                 *ret_val = 0;
2708                 rc = -EFAULT;
2709         } else {
2710                 /* Data */
2711                 val = ((phy->addr << 21) | (devad << 16) |
2712                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2713                        EMAC_MDIO_COMM_START_BUSY);
2714                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2715
2716                 for (i = 0; i < 50; i++) {
2717                         udelay(10);
2718
2719                         val = REG_RD(bp, phy->mdio_ctrl +
2720                                      EMAC_REG_EMAC_MDIO_COMM);
2721                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2722                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2723                                 break;
2724                         }
2725                 }
2726                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2727                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2728                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2729                         *ret_val = 0;
2730                         rc = -EFAULT;
2731                 }
2732         }
2733         /* Work around for E3 A0 */
2734         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2735                 phy->flags ^= FLAGS_DUMMY_READ;
2736                 if (phy->flags & FLAGS_DUMMY_READ) {
2737                         u16 temp_val;
2738                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2739                 }
2740         }
2741
2742         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2743                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2744                                EMAC_MDIO_STATUS_10MB);
2745         return rc;
2746 }
2747
2748 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2749                             u8 devad, u16 reg, u16 val)
2750 {
2751         u32 tmp;
2752         u8 i;
2753         int rc = 0;
2754         u32 chip_id;
2755         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2756                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2757                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2758                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2759         }
2760
2761         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2762                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2763                               EMAC_MDIO_STATUS_10MB);
2764
2765         /* Address */
2766         tmp = ((phy->addr << 21) | (devad << 16) | reg |
2767                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2768                EMAC_MDIO_COMM_START_BUSY);
2769         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2770
2771         for (i = 0; i < 50; i++) {
2772                 udelay(10);
2773
2774                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2775                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2776                         udelay(5);
2777                         break;
2778                 }
2779         }
2780         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2781                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2782                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2783                 rc = -EFAULT;
2784         } else {
2785                 /* Data */
2786                 tmp = ((phy->addr << 21) | (devad << 16) | val |
2787                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2788                        EMAC_MDIO_COMM_START_BUSY);
2789                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2790
2791                 for (i = 0; i < 50; i++) {
2792                         udelay(10);
2793
2794                         tmp = REG_RD(bp, phy->mdio_ctrl +
2795                                      EMAC_REG_EMAC_MDIO_COMM);
2796                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2797                                 udelay(5);
2798                                 break;
2799                         }
2800                 }
2801                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2802                         DP(NETIF_MSG_LINK, "write phy register failed\n");
2803                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2804                         rc = -EFAULT;
2805                 }
2806         }
2807         /* Work around for E3 A0 */
2808         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2809                 phy->flags ^= FLAGS_DUMMY_READ;
2810                 if (phy->flags & FLAGS_DUMMY_READ) {
2811                         u16 temp_val;
2812                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2813                 }
2814         }
2815         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2816                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2817                                EMAC_MDIO_STATUS_10MB);
2818         return rc;
2819 }
2820
2821 /******************************************************************/
2822 /*                      EEE section                                */
2823 /******************************************************************/
2824 static u8 bnx2x_eee_has_cap(struct link_params *params)
2825 {
2826         struct bnx2x *bp = params->bp;
2827
2828         if (REG_RD(bp, params->shmem2_base) <=
2829                    offsetof(struct shmem2_region, eee_status[params->port]))
2830                 return 0;
2831
2832         return 1;
2833 }
2834
2835 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2836 {
2837         switch (nvram_mode) {
2838         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2839                 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2840                 break;
2841         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2842                 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2843                 break;
2844         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2845                 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2846                 break;
2847         default:
2848                 *idle_timer = 0;
2849                 break;
2850         }
2851
2852         return 0;
2853 }
2854
2855 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2856 {
2857         switch (idle_timer) {
2858         case EEE_MODE_NVRAM_BALANCED_TIME:
2859                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2860                 break;
2861         case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2862                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2863                 break;
2864         case EEE_MODE_NVRAM_LATENCY_TIME:
2865                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2866                 break;
2867         default:
2868                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2869                 break;
2870         }
2871
2872         return 0;
2873 }
2874
2875 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2876 {
2877         u32 eee_mode, eee_idle;
2878         struct bnx2x *bp = params->bp;
2879
2880         if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2881                 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2882                         /* time value in eee_mode --> used directly*/
2883                         eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2884                 } else {
2885                         /* hsi value in eee_mode --> time */
2886                         if (bnx2x_eee_nvram_to_time(params->eee_mode &
2887                                                     EEE_MODE_NVRAM_MASK,
2888                                                     &eee_idle))
2889                                 return 0;
2890                 }
2891         } else {
2892                 /* hsi values in nvram --> time*/
2893                 eee_mode = ((REG_RD(bp, params->shmem_base +
2894                                     offsetof(struct shmem_region, dev_info.
2895                                     port_feature_config[params->port].
2896                                     eee_power_mode)) &
2897                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2898                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2899
2900                 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2901                         return 0;
2902         }
2903
2904         return eee_idle;
2905 }
2906
2907 static int bnx2x_eee_set_timers(struct link_params *params,
2908                                    struct link_vars *vars)
2909 {
2910         u32 eee_idle = 0, eee_mode;
2911         struct bnx2x *bp = params->bp;
2912
2913         eee_idle = bnx2x_eee_calc_timer(params);
2914
2915         if (eee_idle) {
2916                 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2917                        eee_idle);
2918         } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2919                    (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2920                    (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2921                 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2922                 return -EINVAL;
2923         }
2924
2925         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2926         if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2927                 /* eee_idle in 1u --> eee_status in 16u */
2928                 eee_idle >>= 4;
2929                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2930                                     SHMEM_EEE_TIME_OUTPUT_BIT;
2931         } else {
2932                 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2933                         return -EINVAL;
2934                 vars->eee_status |= eee_mode;
2935         }
2936
2937         return 0;
2938 }
2939
2940 static int bnx2x_eee_initial_config(struct link_params *params,
2941                                      struct link_vars *vars, u8 mode)
2942 {
2943         vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2944
2945         /* Propagate params' bits --> vars (for migration exposure) */
2946         if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2947                 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2948         else
2949                 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2950
2951         if (params->eee_mode & EEE_MODE_ADV_LPI)
2952                 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2953         else
2954                 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2955
2956         return bnx2x_eee_set_timers(params, vars);
2957 }
2958
2959 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2960                                 struct link_params *params,
2961                                 struct link_vars *vars)
2962 {
2963         struct bnx2x *bp = params->bp;
2964
2965         /* Make Certain LPI is disabled */
2966         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2967
2968         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2969
2970         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2971
2972         return 0;
2973 }
2974
2975 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
2976                                   struct link_params *params,
2977                                   struct link_vars *vars, u8 modes)
2978 {
2979         struct bnx2x *bp = params->bp;
2980         u16 val = 0;
2981
2982         /* Mask events preventing LPI generation */
2983         REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2984
2985         if (modes & SHMEM_EEE_10G_ADV) {
2986                 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
2987                 val |= 0x8;
2988         }
2989         if (modes & SHMEM_EEE_1G_ADV) {
2990                 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
2991                 val |= 0x4;
2992         }
2993
2994         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
2995
2996         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2997         vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
2998
2999         return 0;
3000 }
3001
3002 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3003 {
3004         struct bnx2x *bp = params->bp;
3005
3006         if (bnx2x_eee_has_cap(params))
3007                 REG_WR(bp, params->shmem2_base +
3008                        offsetof(struct shmem2_region,
3009                                 eee_status[params->port]), eee_status);
3010 }
3011
3012 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3013                                   struct link_params *params,
3014                                   struct link_vars *vars)
3015 {
3016         struct bnx2x *bp = params->bp;
3017         u16 adv = 0, lp = 0;
3018         u32 lp_adv = 0;
3019         u8 neg = 0;
3020
3021         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3022         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3023
3024         if (lp & 0x2) {
3025                 lp_adv |= SHMEM_EEE_100M_ADV;
3026                 if (adv & 0x2) {
3027                         if (vars->line_speed == SPEED_100)
3028                                 neg = 1;
3029                         DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3030                 }
3031         }
3032         if (lp & 0x14) {
3033                 lp_adv |= SHMEM_EEE_1G_ADV;
3034                 if (adv & 0x14) {
3035                         if (vars->line_speed == SPEED_1000)
3036                                 neg = 1;
3037                         DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3038                 }
3039         }
3040         if (lp & 0x68) {
3041                 lp_adv |= SHMEM_EEE_10G_ADV;
3042                 if (adv & 0x68) {
3043                         if (vars->line_speed == SPEED_10000)
3044                                 neg = 1;
3045                         DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3046                 }
3047         }
3048
3049         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3050         vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3051
3052         if (neg) {
3053                 DP(NETIF_MSG_LINK, "EEE is active\n");
3054                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3055         }
3056
3057 }
3058
3059 /******************************************************************/
3060 /*                      BSC access functions from E3              */
3061 /******************************************************************/
3062 static void bnx2x_bsc_module_sel(struct link_params *params)
3063 {
3064         int idx;
3065         u32 board_cfg, sfp_ctrl;
3066         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3067         struct bnx2x *bp = params->bp;
3068         u8 port = params->port;
3069         /* Read I2C output PINs */
3070         board_cfg = REG_RD(bp, params->shmem_base +
3071                            offsetof(struct shmem_region,
3072                                     dev_info.shared_hw_config.board));
3073         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3074         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3075                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3076
3077         /* Read I2C output value */
3078         sfp_ctrl = REG_RD(bp, params->shmem_base +
3079                           offsetof(struct shmem_region,
3080                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3081         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3082         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3083         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3084         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3085                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3086 }
3087
3088 static int bnx2x_bsc_read(struct link_params *params,
3089                           struct bnx2x *bp,
3090                           u8 sl_devid,
3091                           u16 sl_addr,
3092                           u8 lc_addr,
3093                           u8 xfer_cnt,
3094                           u32 *data_array)
3095 {
3096         u32 val, i;
3097         int rc = 0;
3098
3099         if (xfer_cnt > 16) {
3100                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3101                                         xfer_cnt);
3102                 return -EINVAL;
3103         }
3104         bnx2x_bsc_module_sel(params);
3105
3106         xfer_cnt = 16 - lc_addr;
3107
3108         /* Enable the engine */
3109         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3110         val |= MCPR_IMC_COMMAND_ENABLE;
3111         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3112
3113         /* Program slave device ID */
3114         val = (sl_devid << 16) | sl_addr;
3115         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3116
3117         /* Start xfer with 0 byte to update the address pointer ???*/
3118         val = (MCPR_IMC_COMMAND_ENABLE) |
3119               (MCPR_IMC_COMMAND_WRITE_OP <<
3120                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3121                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3122         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3123
3124         /* Poll for completion */
3125         i = 0;
3126         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3127         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3128                 udelay(10);
3129                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3130                 if (i++ > 1000) {
3131                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3132                                                                 i);
3133                         rc = -EFAULT;
3134                         break;
3135                 }
3136         }
3137         if (rc == -EFAULT)
3138                 return rc;
3139
3140         /* Start xfer with read op */
3141         val = (MCPR_IMC_COMMAND_ENABLE) |
3142                 (MCPR_IMC_COMMAND_READ_OP <<
3143                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3144                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3145                   (xfer_cnt);
3146         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3147
3148         /* Poll for completion */
3149         i = 0;
3150         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3151         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3152                 udelay(10);
3153                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3154                 if (i++ > 1000) {
3155                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3156                         rc = -EFAULT;
3157                         break;
3158                 }
3159         }
3160         if (rc == -EFAULT)
3161                 return rc;
3162
3163         for (i = (lc_addr >> 2); i < 4; i++) {
3164                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3165 #ifdef __BIG_ENDIAN
3166                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3167                                 ((data_array[i] & 0x0000ff00) << 8) |
3168                                 ((data_array[i] & 0x00ff0000) >> 8) |
3169                                 ((data_array[i] & 0xff000000) >> 24);
3170 #endif
3171         }
3172         return rc;
3173 }
3174
3175 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3176                                      u8 devad, u16 reg, u16 or_val)
3177 {
3178         u16 val;
3179         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3180         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3181 }
3182
3183 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3184                                       struct bnx2x_phy *phy,
3185                                       u8 devad, u16 reg, u16 and_val)
3186 {
3187         u16 val;
3188         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3189         bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3190 }
3191
3192 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3193                    u8 devad, u16 reg, u16 *ret_val)
3194 {
3195         u8 phy_index;
3196         /* Probe for the phy according to the given phy_addr, and execute
3197          * the read request on it
3198          */
3199         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3200                 if (params->phy[phy_index].addr == phy_addr) {
3201                         return bnx2x_cl45_read(params->bp,
3202                                                &params->phy[phy_index], devad,
3203                                                reg, ret_val);
3204                 }
3205         }
3206         return -EINVAL;
3207 }
3208
3209 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3210                     u8 devad, u16 reg, u16 val)
3211 {
3212         u8 phy_index;
3213         /* Probe for the phy according to the given phy_addr, and execute
3214          * the write request on it
3215          */
3216         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3217                 if (params->phy[phy_index].addr == phy_addr) {
3218                         return bnx2x_cl45_write(params->bp,
3219                                                 &params->phy[phy_index], devad,
3220                                                 reg, val);
3221                 }
3222         }
3223         return -EINVAL;
3224 }
3225 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3226                                   struct link_params *params)
3227 {
3228         u8 lane = 0;
3229         struct bnx2x *bp = params->bp;
3230         u32 path_swap, path_swap_ovr;
3231         u8 path, port;
3232
3233         path = BP_PATH(bp);
3234         port = params->port;
3235
3236         if (bnx2x_is_4_port_mode(bp)) {
3237                 u32 port_swap, port_swap_ovr;
3238
3239                 /* Figure out path swap value */
3240                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3241                 if (path_swap_ovr & 0x1)
3242                         path_swap = (path_swap_ovr & 0x2);
3243                 else
3244                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3245
3246                 if (path_swap)
3247                         path = path ^ 1;
3248
3249                 /* Figure out port swap value */
3250                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3251                 if (port_swap_ovr & 0x1)
3252                         port_swap = (port_swap_ovr & 0x2);
3253                 else
3254                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3255
3256                 if (port_swap)
3257                         port = port ^ 1;
3258
3259                 lane = (port<<1) + path;
3260         } else { /* Two port mode - no port swap */
3261
3262                 /* Figure out path swap value */
3263                 path_swap_ovr =
3264                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3265                 if (path_swap_ovr & 0x1) {
3266                         path_swap = (path_swap_ovr & 0x2);
3267                 } else {
3268                         path_swap =
3269                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3270                 }
3271                 if (path_swap)
3272                         path = path ^ 1;
3273
3274                 lane = path << 1 ;
3275         }
3276         return lane;
3277 }
3278
3279 static void bnx2x_set_aer_mmd(struct link_params *params,
3280                               struct bnx2x_phy *phy)
3281 {
3282         u32 ser_lane;
3283         u16 offset, aer_val;
3284         struct bnx2x *bp = params->bp;
3285         ser_lane = ((params->lane_config &
3286                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3287                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3288
3289         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3290                 (phy->addr + ser_lane) : 0;
3291
3292         if (USES_WARPCORE(bp)) {
3293                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3294                 /* In Dual-lane mode, two lanes are joined together,
3295                  * so in order to configure them, the AER broadcast method is
3296                  * used here.
3297                  * 0x200 is the broadcast address for lanes 0,1
3298                  * 0x201 is the broadcast address for lanes 2,3
3299                  */
3300                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3301                         aer_val = (aer_val >> 1) | 0x200;
3302         } else if (CHIP_IS_E2(bp))
3303                 aer_val = 0x3800 + offset - 1;
3304         else
3305                 aer_val = 0x3800 + offset;
3306
3307         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3308                           MDIO_AER_BLOCK_AER_REG, aer_val);
3309
3310 }
3311
3312 /******************************************************************/
3313 /*                      Internal phy section                      */
3314 /******************************************************************/
3315
3316 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3317 {
3318         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3319
3320         /* Set Clause 22 */
3321         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3322         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3323         udelay(500);
3324         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3325         udelay(500);
3326          /* Set Clause 45 */
3327         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3328 }
3329
3330 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3331 {
3332         u32 val;
3333
3334         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3335
3336         val = SERDES_RESET_BITS << (port*16);
3337
3338         /* Reset and unreset the SerDes/XGXS */
3339         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3340         udelay(500);
3341         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3342
3343         bnx2x_set_serdes_access(bp, port);
3344
3345         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3346                DEFAULT_PHY_DEV_ADDR);
3347 }
3348
3349 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3350                                      struct link_params *params,
3351                                      u32 action)
3352 {
3353         struct bnx2x *bp = params->bp;
3354         switch (action) {
3355         case PHY_INIT:
3356                 /* Set correct devad */
3357                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3358                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3359                        phy->def_md_devad);
3360                 break;
3361         }
3362 }
3363
3364 static void bnx2x_xgxs_deassert(struct link_params *params)
3365 {
3366         struct bnx2x *bp = params->bp;
3367         u8 port;
3368         u32 val;
3369         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3370         port = params->port;
3371
3372         val = XGXS_RESET_BITS << (port*16);
3373
3374         /* Reset and unreset the SerDes/XGXS */
3375         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3376         udelay(500);
3377         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3378         bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,
3379                                  PHY_INIT);
3380 }
3381
3382 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3383                                      struct link_params *params, u16 *ieee_fc)
3384 {
3385         struct bnx2x *bp = params->bp;
3386         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3387         /* Resolve pause mode and advertisement Please refer to Table
3388          * 28B-3 of the 802.3ab-1999 spec
3389          */
3390
3391         switch (phy->req_flow_ctrl) {
3392         case BNX2X_FLOW_CTRL_AUTO:
3393                 switch (params->req_fc_auto_adv) {
3394                 case BNX2X_FLOW_CTRL_BOTH:
3395                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3396                         break;
3397                 case BNX2X_FLOW_CTRL_RX:
3398                 case BNX2X_FLOW_CTRL_TX:
3399                         *ieee_fc |=
3400                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3401                         break;
3402                 default:
3403                         break;
3404                 }
3405                 break;
3406         case BNX2X_FLOW_CTRL_TX:
3407                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3408                 break;
3409
3410         case BNX2X_FLOW_CTRL_RX:
3411         case BNX2X_FLOW_CTRL_BOTH:
3412                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3413                 break;
3414
3415         case BNX2X_FLOW_CTRL_NONE:
3416         default:
3417                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3418                 break;
3419         }
3420         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3421 }
3422
3423 static void set_phy_vars(struct link_params *params,
3424                          struct link_vars *vars)
3425 {
3426         struct bnx2x *bp = params->bp;
3427         u8 actual_phy_idx, phy_index, link_cfg_idx;
3428         u8 phy_config_swapped = params->multi_phy_config &
3429                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3430         for (phy_index = INT_PHY; phy_index < params->num_phys;
3431               phy_index++) {
3432                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3433                 actual_phy_idx = phy_index;
3434                 if (phy_config_swapped) {
3435                         if (phy_index == EXT_PHY1)
3436                                 actual_phy_idx = EXT_PHY2;
3437                         else if (phy_index == EXT_PHY2)
3438                                 actual_phy_idx = EXT_PHY1;
3439                 }
3440                 params->phy[actual_phy_idx].req_flow_ctrl =
3441                         params->req_flow_ctrl[link_cfg_idx];
3442
3443                 params->phy[actual_phy_idx].req_line_speed =
3444                         params->req_line_speed[link_cfg_idx];
3445
3446                 params->phy[actual_phy_idx].speed_cap_mask =
3447                         params->speed_cap_mask[link_cfg_idx];
3448
3449                 params->phy[actual_phy_idx].req_duplex =
3450                         params->req_duplex[link_cfg_idx];
3451
3452                 if (params->req_line_speed[link_cfg_idx] ==
3453                     SPEED_AUTO_NEG)
3454                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3455
3456                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3457                            " speed_cap_mask %x\n",
3458                            params->phy[actual_phy_idx].req_flow_ctrl,
3459                            params->phy[actual_phy_idx].req_line_speed,
3460                            params->phy[actual_phy_idx].speed_cap_mask);
3461         }
3462 }
3463
3464 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3465                                     struct bnx2x_phy *phy,
3466                                     struct link_vars *vars)
3467 {
3468         u16 val;
3469         struct bnx2x *bp = params->bp;
3470         /* Read modify write pause advertizing */
3471         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3472
3473         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3474
3475         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3476         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3477         if ((vars->ieee_fc &
3478             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3479             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3480                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3481         }
3482         if ((vars->ieee_fc &
3483             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3484             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3485                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3486         }
3487         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3488         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3489 }
3490
3491 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3492 {                                               /*  LD      LP   */
3493         switch (pause_result) {                 /* ASYM P ASYM P */
3494         case 0xb:                               /*   1  0   1  1 */
3495                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3496                 break;
3497
3498         case 0xe:                               /*   1  1   1  0 */
3499                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3500                 break;
3501
3502         case 0x5:                               /*   0  1   0  1 */
3503         case 0x7:                               /*   0  1   1  1 */
3504         case 0xd:                               /*   1  1   0  1 */
3505         case 0xf:                               /*   1  1   1  1 */
3506                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3507                 break;
3508
3509         default:
3510                 break;
3511         }
3512         if (pause_result & (1<<0))
3513                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3514         if (pause_result & (1<<1))
3515                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3516
3517 }
3518
3519 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3520                                         struct link_params *params,
3521                                         struct link_vars *vars)
3522 {
3523         u16 ld_pause;           /* local */
3524         u16 lp_pause;           /* link partner */
3525         u16 pause_result;
3526         struct bnx2x *bp = params->bp;
3527         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3528                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3529                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3530         } else if (CHIP_IS_E3(bp) &&
3531                 SINGLE_MEDIA_DIRECT(params)) {
3532                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3533                 u16 gp_status, gp_mask;
3534                 bnx2x_cl45_read(bp, phy,
3535                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3536                                 &gp_status);
3537                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3538                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3539                         lane;
3540                 if ((gp_status & gp_mask) == gp_mask) {
3541                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3542                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3543                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3544                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3545                 } else {
3546                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3547                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3548                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3549                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3550                         ld_pause = ((ld_pause &
3551                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3552                                     << 3);
3553                         lp_pause = ((lp_pause &
3554                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3555                                     << 3);
3556                 }
3557         } else {
3558                 bnx2x_cl45_read(bp, phy,
3559                                 MDIO_AN_DEVAD,
3560                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3561                 bnx2x_cl45_read(bp, phy,
3562                                 MDIO_AN_DEVAD,
3563                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3564         }
3565         pause_result = (ld_pause &
3566                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3567         pause_result |= (lp_pause &
3568                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3569         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3570         bnx2x_pause_resolve(vars, pause_result);
3571
3572 }
3573
3574 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3575                                    struct link_params *params,
3576                                    struct link_vars *vars)
3577 {
3578         u8 ret = 0;
3579         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3580         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3581                 /* Update the advertised flow-controled of LD/LP in AN */
3582                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3583                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3584                 /* But set the flow-control result as the requested one */
3585                 vars->flow_ctrl = phy->req_flow_ctrl;
3586         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3587                 vars->flow_ctrl = params->req_fc_auto_adv;
3588         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3589                 ret = 1;
3590                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3591         }
3592         return ret;
3593 }
3594 /******************************************************************/
3595 /*                      Warpcore section                          */
3596 /******************************************************************/
3597 /* The init_internal_warpcore should mirror the xgxs,
3598  * i.e. reset the lane (if needed), set aer for the
3599  * init configuration, and set/clear SGMII flag. Internal
3600  * phy init is done purely in phy_init stage.
3601  */
3602 #define WC_TX_DRIVER(post2, idriver, ipre, ifir) \
3603         ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3604          (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3605          (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \
3606          (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET))
3607
3608 #define WC_TX_FIR(post, main, pre) \
3609         ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3610          (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3611          (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3612
3613 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3614                                          struct link_params *params,
3615                                          struct link_vars *vars)
3616 {
3617         struct bnx2x *bp = params->bp;
3618         u16 i;
3619         static struct bnx2x_reg_set reg_set[] = {
3620                 /* Step 1 - Program the TX/RX alignment markers */
3621                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3622                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3623                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3624                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3625                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3626                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3627                 /* Step 2 - Configure the NP registers */
3628                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3629                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3630                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3631                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3632                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3633                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3634                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3635                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3636                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3637         };
3638         DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3639
3640         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3641                                  MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3642
3643         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3644                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3645                                  reg_set[i].val);
3646
3647         /* Start KR2 work-around timer which handles BCM8073 link-parner */
3648         params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3649         bnx2x_update_link_attr(params, params->link_attr_sync);
3650 }
3651
3652 static void bnx2x_disable_kr2(struct link_params *params,
3653                               struct link_vars *vars,
3654                               struct bnx2x_phy *phy)
3655 {
3656         struct bnx2x *bp = params->bp;
3657         int i;
3658         static struct bnx2x_reg_set reg_set[] = {
3659                 /* Step 1 - Program the TX/RX alignment markers */
3660                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3661                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3662                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3663                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3664                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3665                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3666                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3667                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3668                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3669                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3670                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3671                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3672                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3673                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3674                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3675         };
3676         DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
3677
3678         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3679                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3680                                  reg_set[i].val);
3681         params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3682         bnx2x_update_link_attr(params, params->link_attr_sync);
3683
3684         vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
3685 }
3686
3687 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3688                                                struct link_params *params)
3689 {
3690         struct bnx2x *bp = params->bp;
3691
3692         DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3693         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3694                          MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3695         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3696                                  MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3697 }
3698
3699 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3700                                          struct link_params *params)
3701 {
3702         /* Restart autoneg on the leading lane only */
3703         struct bnx2x *bp = params->bp;
3704         u16 lane = bnx2x_get_warpcore_lane(phy, params);
3705         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3706                           MDIO_AER_BLOCK_AER_REG, lane);
3707         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3708                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3709
3710         /* Restore AER */
3711         bnx2x_set_aer_mmd(params, phy);
3712 }
3713
3714 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3715                                         struct link_params *params,
3716                                         struct link_vars *vars) {
3717         u16 lane, i, cl72_ctrl, an_adv = 0, val;
3718         u32 wc_lane_config;
3719         struct bnx2x *bp = params->bp;
3720         static struct bnx2x_reg_set reg_set[] = {
3721                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3722                 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3723                 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3724                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3725                 /* Disable Autoneg: re-enable it after adv is done. */
3726                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3727                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3728                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3729         };
3730         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3731         /* Set to default registers that may be overriden by 10G force */
3732         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3733                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3734                                  reg_set[i].val);
3735
3736         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3737                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3738         cl72_ctrl &= 0x08ff;
3739         cl72_ctrl |= 0x3800;
3740         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3741                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3742
3743         /* Check adding advertisement for 1G KX */
3744         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3745              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3746             (vars->line_speed == SPEED_1000)) {
3747                 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3748                 an_adv |= (1<<5);
3749
3750                 /* Enable CL37 1G Parallel Detect */
3751                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3752                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3753         }
3754         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3755              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3756             (vars->line_speed ==  SPEED_10000)) {
3757                 /* Check adding advertisement for 10G KR */
3758                 an_adv |= (1<<7);
3759                 /* Enable 10G Parallel Detect */
3760                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3761                                   MDIO_AER_BLOCK_AER_REG, 0);
3762
3763                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3764                                  MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3765                 bnx2x_set_aer_mmd(params, phy);
3766                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3767         }
3768
3769         /* Set Transmit PMD settings */
3770         lane = bnx2x_get_warpcore_lane(phy, params);
3771         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3772                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3773                          WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
3774         /* Configure the next lane if dual mode */
3775         if (phy->flags & FLAGS_WC_DUAL_MODE)
3776                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3777                                  MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3778                                  WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
3779         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3780                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3781                          0x03f0);
3782         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3783                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3784                          0x03f0);
3785
3786         /* Advertised speeds */
3787         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3788                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3789
3790         /* Advertised and set FEC (Forward Error Correction) */
3791         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3792                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3793                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3794                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3795
3796         /* Enable CL37 BAM */
3797         if (REG_RD(bp, params->shmem_base +
3798                    offsetof(struct shmem_region, dev_info.
3799                             port_hw_config[params->port].default_cfg)) &
3800             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3801                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3802                                          MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3803                                          1);
3804                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3805         }
3806
3807         /* Advertise pause */
3808         bnx2x_ext_phy_set_pause(params, phy, vars);
3809         vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3810         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3811                                  MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3812
3813         /* Over 1G - AN local device user page 1 */
3814         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3815                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3816
3817         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3818              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3819             (phy->req_line_speed == SPEED_20000)) {
3820
3821                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3822                                   MDIO_AER_BLOCK_AER_REG, lane);
3823
3824                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3825                                          MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3826                                          (1<<11));
3827
3828                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3829                                  MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3830                 bnx2x_set_aer_mmd(params, phy);
3831
3832                 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3833         } else {
3834                 /* Enable Auto-Detect to support 1G over CL37 as well */
3835                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3836                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
3837                 wc_lane_config = REG_RD(bp, params->shmem_base +
3838                                         offsetof(struct shmem_region, dev_info.
3839                                         shared_hw_config.wc_lane_config));
3840                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3841                                 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
3842                 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
3843                  * parallel-detect loop when CL73 and CL37 are enabled.
3844                  */
3845                 val |= 1 << 11;
3846
3847                 /* Restore Polarity settings in case it was run over by
3848                  * previous link owner
3849                  */
3850                 if (wc_lane_config &
3851                     (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
3852                         val |= 3 << 2;
3853                 else
3854                         val &= ~(3 << 2);
3855                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3856                                  MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
3857                                  val);
3858
3859                 bnx2x_disable_kr2(params, vars, phy);
3860         }
3861
3862         /* Enable Autoneg: only on the main lane */
3863         bnx2x_warpcore_restart_AN_KR(phy, params);
3864 }
3865
3866 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3867                                       struct link_params *params,
3868                                       struct link_vars *vars)
3869 {
3870         struct bnx2x *bp = params->bp;
3871         u16 val16, i, lane;
3872         static struct bnx2x_reg_set reg_set[] = {
3873                 /* Disable Autoneg */
3874                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3875                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3876                         0x3f00},
3877                 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3878                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3879                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3880                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3881                 /* Leave cl72 training enable, needed for KR */
3882                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3883         };
3884
3885         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3886                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3887                                  reg_set[i].val);
3888
3889         lane = bnx2x_get_warpcore_lane(phy, params);
3890         /* Global registers */
3891         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3892                           MDIO_AER_BLOCK_AER_REG, 0);
3893         /* Disable CL36 PCS Tx */
3894         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3895                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3896         val16 &= ~(0x0011 << lane);
3897         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3898                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3899
3900         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3901                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3902         val16 |= (0x0303 << (lane << 1));
3903         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3904                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3905         /* Restore AER */
3906         bnx2x_set_aer_mmd(params, phy);
3907         /* Set speed via PMA/PMD register */
3908         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3909                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3910
3911         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3912                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3913
3914         /* Enable encoded forced speed */
3915         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3916                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3917
3918         /* Turn TX scramble payload only the 64/66 scrambler */
3919         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3920                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3921
3922         /* Turn RX scramble payload only the 64/66 scrambler */
3923         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3924                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3925
3926         /* Set and clear loopback to cause a reset to 64/66 decoder */
3927         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3928                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3929         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3930                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3931
3932 }
3933
3934 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3935                                        struct link_params *params,
3936                                        u8 is_xfi)
3937 {
3938         struct bnx2x *bp = params->bp;
3939         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3940         u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3941         u32 ifir_val, ipost2_val, ipre_driver_val;
3942
3943         /* Hold rxSeqStart */
3944         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3945                                  MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3946
3947         /* Hold tx_fifo_reset */
3948         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3949                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3950
3951         /* Disable CL73 AN */
3952         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3953
3954         /* Disable 100FX Enable and Auto-Detect */
3955         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3956                                   MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3957
3958         /* Disable 100FX Idle detect */
3959         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3960                                  MDIO_WC_REG_FX100_CTRL3, 0x0080);
3961
3962         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3963         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3964                                   MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3965
3966         /* Turn off auto-detect & fiber mode */
3967         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3968                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3969                                   0xFFEE);
3970
3971         /* Set filter_force_link, disable_false_link and parallel_detect */
3972         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3973                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3974         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3975                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3976                          ((val | 0x0006) & 0xFFFE));
3977
3978         /* Set XFI / SFI */
3979         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3980                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3981
3982         misc1_val &= ~(0x1f);
3983
3984         if (is_xfi) {
3985                 misc1_val |= 0x5;
3986                 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3987                 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0);
3988         } else {
3989                 cfg_tap_val = REG_RD(bp, params->shmem_base +
3990                                      offsetof(struct shmem_region, dev_info.
3991                                               port_hw_config[params->port].
3992                                               sfi_tap_values));
3993
3994                 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
3995
3996                 misc1_val |= 0x9;
3997
3998                 /* TAP values are controlled by nvram, if value there isn't 0 */
3999                 if (tx_equal)
4000                         tap_val = (u16)tx_equal;
4001                 else
4002                         tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4003
4004                 ifir_val = DEFAULT_TX_DRV_IFIR;
4005                 ipost2_val = DEFAULT_TX_DRV_POST2;
4006                 ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER;
4007                 tx_drv_brdct = DEFAULT_TX_DRV_BRDCT;
4008
4009                 /* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all
4010                  * configuration.
4011                  */
4012                 if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK |
4013                                    PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK |
4014                                    PORT_HW_CFG_TX_DRV_POST2_MASK)) {
4015                         ifir_val = (cfg_tap_val &
4016                                     PORT_HW_CFG_TX_DRV_IFIR_MASK) >>
4017                                 PORT_HW_CFG_TX_DRV_IFIR_SHIFT;
4018                         ipre_driver_val = (cfg_tap_val &
4019                                            PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK)
4020                         >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT;
4021                         ipost2_val = (cfg_tap_val &
4022                                       PORT_HW_CFG_TX_DRV_POST2_MASK) >>
4023                                 PORT_HW_CFG_TX_DRV_POST2_SHIFT;
4024                 }
4025
4026                 if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) {
4027                         tx_drv_brdct = (cfg_tap_val &
4028                                         PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4029                                 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4030                 }
4031
4032                 tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct,
4033                                              ipre_driver_val, ifir_val);
4034         }
4035         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4036                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4037
4038         /* Set Transmit PMD settings */
4039         lane = bnx2x_get_warpcore_lane(phy, params);
4040         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4041                          MDIO_WC_REG_TX_FIR_TAP,
4042                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4043         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4044                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4045                          tx_driver_val);
4046
4047         /* Enable fiber mode, enable and invert sig_det */
4048         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4049                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4050
4051         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4052         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4053                                  MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4054
4055         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4056
4057         /* 10G XFI Full Duplex */
4058         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4059                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4060
4061         /* Release tx_fifo_reset */
4062         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4063                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4064                                   0xFFFE);
4065         /* Release rxSeqStart */
4066         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4067                                   MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4068 }
4069
4070 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4071                                              struct link_params *params)
4072 {
4073         u16 val;
4074         struct bnx2x *bp = params->bp;
4075         /* Set global registers, so set AER lane to 0 */
4076         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4077                           MDIO_AER_BLOCK_AER_REG, 0);
4078
4079         /* Disable sequencer */
4080         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4081                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4082
4083         bnx2x_set_aer_mmd(params, phy);
4084
4085         bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4086                                   MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4087         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4088                          MDIO_AN_REG_CTRL, 0);
4089         /* Turn off CL73 */
4090         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4091                         MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4092         val &= ~(1<<5);
4093         val |= (1<<6);
4094         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4095                          MDIO_WC_REG_CL73_USERB0_CTRL, val);
4096
4097         /* Set 20G KR2 force speed */
4098         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4099                                  MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4100
4101         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4102                                  MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4103
4104         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4105                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4106         val &= ~(3<<14);
4107         val |= (1<<15);
4108         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4109                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4110         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4111                          MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4112
4113         /* Enable sequencer (over lane 0) */
4114         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4115                           MDIO_AER_BLOCK_AER_REG, 0);
4116
4117         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4118                                  MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4119
4120         bnx2x_set_aer_mmd(params, phy);
4121 }
4122
4123 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4124                                          struct bnx2x_phy *phy,
4125                                          u16 lane)
4126 {
4127         /* Rx0 anaRxControl1G */
4128         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4129                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4130
4131         /* Rx2 anaRxControl1G */
4132         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4133                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4134
4135         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4136                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4137
4138         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4139                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4140
4141         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4142                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4143
4144         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4145                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4146
4147         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4148                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4149
4150         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4151                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4152
4153         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4154                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4155
4156         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4157                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4158
4159         /* Serdes Digital Misc1 */
4160         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4161                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4162
4163         /* Serdes Digital4 Misc3 */
4164         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4165                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4166
4167         /* Set Transmit PMD settings */
4168         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4169                          MDIO_WC_REG_TX_FIR_TAP,
4170                          (WC_TX_FIR(0x12, 0x2d, 0x00) |
4171                           MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4172         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4173                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4174                          WC_TX_DRIVER(0x02, 0x02, 0x02, 0));
4175 }
4176
4177 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4178                                            struct link_params *params,
4179                                            u8 fiber_mode,
4180                                            u8 always_autoneg)
4181 {
4182         struct bnx2x *bp = params->bp;
4183         u16 val16, digctrl_kx1, digctrl_kx2;
4184
4185         /* Clear XFI clock comp in non-10G single lane mode. */
4186         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4187                                   MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4188
4189         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4190
4191         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4192                 /* SGMII Autoneg */
4193                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4194                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4195                                          0x1000);
4196                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4197         } else {
4198                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4199                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4200                 val16 &= 0xcebf;
4201                 switch (phy->req_line_speed) {
4202                 case SPEED_10:
4203                         break;
4204                 case SPEED_100:
4205                         val16 |= 0x2000;
4206                         break;
4207                 case SPEED_1000:
4208                         val16 |= 0x0040;
4209                         break;
4210                 default:
4211                         DP(NETIF_MSG_LINK,
4212                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4213                         return;
4214                 }
4215
4216                 if (phy->req_duplex == DUPLEX_FULL)
4217                         val16 |= 0x0100;
4218
4219                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4220                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4221
4222                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4223                                phy->req_line_speed);
4224                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4225                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4226                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4227         }
4228
4229         /* SGMII Slave mode and disable signal detect */
4230         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4231                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4232         if (fiber_mode)
4233                 digctrl_kx1 = 1;
4234         else
4235                 digctrl_kx1 &= 0xff4a;
4236
4237         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4238                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4239                         digctrl_kx1);
4240
4241         /* Turn off parallel detect */
4242         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4243                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4244         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4245                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4246                         (digctrl_kx2 & ~(1<<2)));
4247
4248         /* Re-enable parallel detect */
4249         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4250                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4251                         (digctrl_kx2 | (1<<2)));
4252
4253         /* Enable autodet */
4254         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4255                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4256                         (digctrl_kx1 | 0x10));
4257 }
4258
4259 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4260                                       struct bnx2x_phy *phy,
4261                                       u8 reset)
4262 {
4263         u16 val;
4264         /* Take lane out of reset after configuration is finished */
4265         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4266                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4267         if (reset)
4268                 val |= 0xC000;
4269         else
4270                 val &= 0x3FFF;
4271         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4272                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4273         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4274                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4275 }
4276 /* Clear SFI/XFI link settings registers */
4277 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4278                                       struct link_params *params,
4279                                       u16 lane)
4280 {
4281         struct bnx2x *bp = params->bp;
4282         u16 i;
4283         static struct bnx2x_reg_set wc_regs[] = {
4284                 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4285                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4286                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4287                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4288                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4289                         0x0195},
4290                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4291                         0x0007},
4292                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4293                         0x0002},
4294                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4295                 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4296                 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4297                 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4298         };
4299         /* Set XFI clock comp as default. */
4300         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4301                                  MDIO_WC_REG_RX66_CONTROL, (3<<13));
4302
4303         for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4304                 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4305                                  wc_regs[i].val);
4306
4307         lane = bnx2x_get_warpcore_lane(phy, params);
4308         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4309                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4310
4311 }
4312
4313 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4314                                                 u32 chip_id,
4315                                                 u32 shmem_base, u8 port,
4316                                                 u8 *gpio_num, u8 *gpio_port)
4317 {
4318         u32 cfg_pin;
4319         *gpio_num = 0;
4320         *gpio_port = 0;
4321         if (CHIP_IS_E3(bp)) {
4322                 cfg_pin = (REG_RD(bp, shmem_base +
4323                                 offsetof(struct shmem_region,
4324                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4325                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4326                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4327
4328                 /* Should not happen. This function called upon interrupt
4329                  * triggered by GPIO ( since EPIO can only generate interrupts
4330                  * to MCP).
4331                  * So if this function was called and none of the GPIOs was set,
4332                  * it means the shit hit the fan.
4333                  */
4334                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4335                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4336                         DP(NETIF_MSG_LINK,
4337                            "No cfg pin %x for module detect indication\n",
4338                            cfg_pin);
4339                         return -EINVAL;
4340                 }
4341
4342                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4343                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4344         } else {
4345                 *gpio_num = MISC_REGISTERS_GPIO_3;
4346                 *gpio_port = port;
4347         }
4348
4349         return 0;
4350 }
4351
4352 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4353                                        struct link_params *params)
4354 {
4355         struct bnx2x *bp = params->bp;
4356         u8 gpio_num, gpio_port;
4357         u32 gpio_val;
4358         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4359                                       params->shmem_base, params->port,
4360                                       &gpio_num, &gpio_port) != 0)
4361                 return 0;
4362         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4363
4364         /* Call the handling function in case module is detected */
4365         if (gpio_val == 0)
4366                 return 1;
4367         else
4368                 return 0;
4369 }
4370 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4371                                      struct link_params *params)
4372 {
4373         u16 gp2_status_reg0, lane;
4374         struct bnx2x *bp = params->bp;
4375
4376         lane = bnx2x_get_warpcore_lane(phy, params);
4377
4378         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4379                                  &gp2_status_reg0);
4380
4381         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4382 }
4383
4384 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4385                                           struct link_params *params,
4386                                           struct link_vars *vars)
4387 {
4388         struct bnx2x *bp = params->bp;
4389         u32 serdes_net_if;
4390         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4391
4392         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4393
4394         if (!vars->turn_to_run_wc_rt)
4395                 return;
4396
4397         if (vars->rx_tx_asic_rst) {
4398                 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4399                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4400                                 offsetof(struct shmem_region, dev_info.
4401                                 port_hw_config[params->port].default_cfg)) &
4402                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4403
4404                 switch (serdes_net_if) {
4405                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4406                         /* Do we get link yet? */
4407                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4408                                         &gp_status1);
4409                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4410                                 /*10G KR*/
4411                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4412
4413                         if (lnkup_kr || lnkup) {
4414                                 vars->rx_tx_asic_rst = 0;
4415                         } else {
4416                                 /* Reset the lane to see if link comes up.*/
4417                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4418                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4419
4420                                 /* Restart Autoneg */
4421                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4422                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4423
4424                                 vars->rx_tx_asic_rst--;
4425                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4426                                 vars->rx_tx_asic_rst);
4427                         }
4428                         break;
4429
4430                 default:
4431                         break;
4432                 }
4433
4434         } /*params->rx_tx_asic_rst*/
4435
4436 }
4437 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4438                                       struct link_params *params)
4439 {
4440         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4441         struct bnx2x *bp = params->bp;
4442         bnx2x_warpcore_clear_regs(phy, params, lane);
4443         if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4444              SPEED_10000) &&
4445             (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4446                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4447                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4448         } else {
4449                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4450                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4451         }
4452 }
4453
4454 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4455                                          struct bnx2x_phy *phy,
4456                                          u8 tx_en)
4457 {
4458         struct bnx2x *bp = params->bp;
4459         u32 cfg_pin;
4460         u8 port = params->port;
4461
4462         cfg_pin = REG_RD(bp, params->shmem_base +
4463                          offsetof(struct shmem_region,
4464                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4465                 PORT_HW_CFG_E3_TX_LASER_MASK;
4466         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4467         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4468
4469         /* For 20G, the expected pin to be used is 3 pins after the current */
4470         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4471         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4472                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4473 }
4474
4475 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4476                                        struct link_params *params,
4477                                        struct link_vars *vars)
4478 {
4479         struct bnx2x *bp = params->bp;
4480         u32 serdes_net_if;
4481         u8 fiber_mode;
4482         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4483         serdes_net_if = (REG_RD(bp, params->shmem_base +
4484                          offsetof(struct shmem_region, dev_info.
4485                                   port_hw_config[params->port].default_cfg)) &
4486                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4487         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4488                            "serdes_net_if = 0x%x\n",
4489                        vars->line_speed, serdes_net_if);
4490         bnx2x_set_aer_mmd(params, phy);
4491         bnx2x_warpcore_reset_lane(bp, phy, 1);
4492         vars->phy_flags |= PHY_XGXS_FLAG;
4493         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4494             (phy->req_line_speed &&
4495              ((phy->req_line_speed == SPEED_100) ||
4496               (phy->req_line_speed == SPEED_10)))) {
4497                 vars->phy_flags |= PHY_SGMII_FLAG;
4498                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4499                 bnx2x_warpcore_clear_regs(phy, params, lane);
4500                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4501         } else {
4502                 switch (serdes_net_if) {
4503                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4504                         /* Enable KR Auto Neg */
4505                         if (params->loopback_mode != LOOPBACK_EXT)
4506                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4507                         else {
4508                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4509                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4510                         }
4511                         break;
4512
4513                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4514                         bnx2x_warpcore_clear_regs(phy, params, lane);
4515                         if (vars->line_speed == SPEED_10000) {
4516                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4517                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4518                         } else {
4519                                 if (SINGLE_MEDIA_DIRECT(params)) {
4520                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4521                                         fiber_mode = 1;
4522                                 } else {
4523                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4524                                         fiber_mode = 0;
4525                                 }
4526                                 bnx2x_warpcore_set_sgmii_speed(phy,
4527                                                                 params,
4528                                                                 fiber_mode,
4529                                                                 0);
4530                         }
4531
4532                         break;
4533
4534                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4535                         /* Issue Module detection if module is plugged, or
4536                          * enabled transmitter to avoid current leakage in case
4537                          * no module is connected
4538                          */
4539                         if ((params->loopback_mode == LOOPBACK_NONE) ||
4540                             (params->loopback_mode == LOOPBACK_EXT)) {
4541                                 if (bnx2x_is_sfp_module_plugged(phy, params))
4542                                         bnx2x_sfp_module_detection(phy, params);
4543                                 else
4544                                         bnx2x_sfp_e3_set_transmitter(params,
4545                                                                      phy, 1);
4546                         }
4547
4548                         bnx2x_warpcore_config_sfi(phy, params);
4549                         break;
4550
4551                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4552                         if (vars->line_speed != SPEED_20000) {
4553                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4554                                 return;
4555                         }
4556                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4557                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4558                         /* Issue Module detection */
4559
4560                         bnx2x_sfp_module_detection(phy, params);
4561                         break;
4562                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4563                         if (!params->loopback_mode) {
4564                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4565                         } else {
4566                                 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4567                                 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4568                         }
4569                         break;
4570                 default:
4571                         DP(NETIF_MSG_LINK,
4572                            "Unsupported Serdes Net Interface 0x%x\n",
4573                            serdes_net_if);
4574                         return;
4575                 }
4576         }
4577
4578         /* Take lane out of reset after configuration is finished */
4579         bnx2x_warpcore_reset_lane(bp, phy, 0);
4580         DP(NETIF_MSG_LINK, "Exit config init\n");
4581 }
4582
4583 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4584                                       struct link_params *params)
4585 {
4586         struct bnx2x *bp = params->bp;
4587         u16 val16, lane;
4588         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4589         bnx2x_set_mdio_emac_per_phy(bp, params);
4590         bnx2x_set_aer_mmd(params, phy);
4591         /* Global register */
4592         bnx2x_warpcore_reset_lane(bp, phy, 1);
4593
4594         /* Clear loopback settings (if any) */
4595         /* 10G & 20G */
4596         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4597                                   MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4598
4599         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4600                                   MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4601
4602         /* Update those 1-copy registers */
4603         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4604                           MDIO_AER_BLOCK_AER_REG, 0);
4605         /* Enable 1G MDIO (1-copy) */
4606         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4607                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4608                                   ~0x10);
4609
4610         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4611                                   MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4612         lane = bnx2x_get_warpcore_lane(phy, params);
4613         /* Disable CL36 PCS Tx */
4614         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4615                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4616         val16 |= (0x11 << lane);
4617         if (phy->flags & FLAGS_WC_DUAL_MODE)
4618                 val16 |= (0x22 << lane);
4619         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4620                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4621
4622         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4623                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4624         val16 &= ~(0x0303 << (lane << 1));
4625         val16 |= (0x0101 << (lane << 1));
4626         if (phy->flags & FLAGS_WC_DUAL_MODE) {
4627                 val16 &= ~(0x0c0c << (lane << 1));
4628                 val16 |= (0x0404 << (lane << 1));
4629         }
4630
4631         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4632                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4633         /* Restore AER */
4634         bnx2x_set_aer_mmd(params, phy);
4635
4636 }
4637
4638 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4639                                         struct link_params *params)
4640 {
4641         struct bnx2x *bp = params->bp;
4642         u16 val16;
4643         u32 lane;
4644         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4645                        params->loopback_mode, phy->req_line_speed);
4646
4647         if (phy->req_line_speed < SPEED_10000 ||
4648             phy->supported & SUPPORTED_20000baseKR2_Full) {
4649                 /* 10/100/1000/20G-KR2 */
4650
4651                 /* Update those 1-copy registers */
4652                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4653                                   MDIO_AER_BLOCK_AER_REG, 0);
4654                 /* Enable 1G MDIO (1-copy) */
4655                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4656                                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4657                                          0x10);
4658                 /* Set 1G loopback based on lane (1-copy) */
4659                 lane = bnx2x_get_warpcore_lane(phy, params);
4660                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4661                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4662                 val16 |= (1<<lane);
4663                 if (phy->flags & FLAGS_WC_DUAL_MODE)
4664                         val16 |= (2<<lane);
4665                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4666                                  MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4667                                  val16);
4668
4669                 /* Switch back to 4-copy registers */
4670                 bnx2x_set_aer_mmd(params, phy);
4671         } else {
4672                 /* 10G / 20G-DXGXS */
4673                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4674                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4675                                          0x4000);
4676                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4677                                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4678         }
4679 }
4680
4681
4682
4683 static void bnx2x_sync_link(struct link_params *params,
4684                              struct link_vars *vars)
4685 {
4686         struct bnx2x *bp = params->bp;
4687         u8 link_10g_plus;
4688         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4689                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4690         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4691         if (vars->link_up) {
4692                 DP(NETIF_MSG_LINK, "phy link up\n");
4693
4694                 vars->phy_link_up = 1;
4695                 vars->duplex = DUPLEX_FULL;
4696                 switch (vars->link_status &
4697                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4698                 case LINK_10THD:
4699                         vars->duplex = DUPLEX_HALF;
4700                         /* Fall thru */
4701                 case LINK_10TFD:
4702                         vars->line_speed = SPEED_10;
4703                         break;
4704
4705                 case LINK_100TXHD:
4706                         vars->duplex = DUPLEX_HALF;
4707                         /* Fall thru */
4708                 case LINK_100T4:
4709                 case LINK_100TXFD:
4710                         vars->line_speed = SPEED_100;
4711                         break;
4712
4713                 case LINK_1000THD:
4714                         vars->duplex = DUPLEX_HALF;
4715                         /* Fall thru */
4716                 case LINK_1000TFD:
4717                         vars->line_speed = SPEED_1000;
4718                         break;
4719
4720                 case LINK_2500THD:
4721                         vars->duplex = DUPLEX_HALF;
4722                         /* Fall thru */
4723                 case LINK_2500TFD:
4724                         vars->line_speed = SPEED_2500;
4725                         break;
4726
4727                 case LINK_10GTFD:
4728                         vars->line_speed = SPEED_10000;
4729                         break;
4730                 case LINK_20GTFD:
4731                         vars->line_speed = SPEED_20000;
4732                         break;
4733                 default:
4734                         break;
4735                 }
4736                 vars->flow_ctrl = 0;
4737                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4738                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4739
4740                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4741                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4742
4743                 if (!vars->flow_ctrl)
4744                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4745
4746                 if (vars->line_speed &&
4747                     ((vars->line_speed == SPEED_10) ||
4748                      (vars->line_speed == SPEED_100))) {
4749                         vars->phy_flags |= PHY_SGMII_FLAG;
4750                 } else {
4751                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4752                 }
4753                 if (vars->line_speed &&
4754                     USES_WARPCORE(bp) &&
4755                     (vars->line_speed == SPEED_1000))
4756                         vars->phy_flags |= PHY_SGMII_FLAG;
4757                 /* Anything 10 and over uses the bmac */
4758                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4759
4760                 if (link_10g_plus) {
4761                         if (USES_WARPCORE(bp))
4762                                 vars->mac_type = MAC_TYPE_XMAC;
4763                         else
4764                                 vars->mac_type = MAC_TYPE_BMAC;
4765                 } else {
4766                         if (USES_WARPCORE(bp))
4767                                 vars->mac_type = MAC_TYPE_UMAC;
4768                         else
4769                                 vars->mac_type = MAC_TYPE_EMAC;
4770                 }
4771         } else { /* Link down */
4772                 DP(NETIF_MSG_LINK, "phy link down\n");
4773
4774                 vars->phy_link_up = 0;
4775
4776                 vars->line_speed = 0;
4777                 vars->duplex = DUPLEX_FULL;
4778                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4779
4780                 /* Indicate no mac active */
4781                 vars->mac_type = MAC_TYPE_NONE;
4782                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4783                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4784                 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4785                         vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4786         }
4787 }
4788
4789 void bnx2x_link_status_update(struct link_params *params,
4790                               struct link_vars *vars)
4791 {
4792         struct bnx2x *bp = params->bp;
4793         u8 port = params->port;
4794         u32 sync_offset, media_types;
4795         /* Update PHY configuration */
4796         set_phy_vars(params, vars);
4797
4798         vars->link_status = REG_RD(bp, params->shmem_base +
4799                                    offsetof(struct shmem_region,
4800                                             port_mb[port].link_status));
4801
4802         /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4803         if (params->loopback_mode != LOOPBACK_NONE &&
4804             params->loopback_mode != LOOPBACK_EXT)
4805                 vars->link_status |= LINK_STATUS_LINK_UP;
4806
4807         if (bnx2x_eee_has_cap(params))
4808                 vars->eee_status = REG_RD(bp, params->shmem2_base +
4809                                           offsetof(struct shmem2_region,
4810                                                    eee_status[params->port]));
4811
4812         vars->phy_flags = PHY_XGXS_FLAG;
4813         bnx2x_sync_link(params, vars);
4814         /* Sync media type */
4815         sync_offset = params->shmem_base +
4816                         offsetof(struct shmem_region,
4817                                  dev_info.port_hw_config[port].media_type);
4818         media_types = REG_RD(bp, sync_offset);
4819
4820         params->phy[INT_PHY].media_type =
4821                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4822                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4823         params->phy[EXT_PHY1].media_type =
4824                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4825                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4826         params->phy[EXT_PHY2].media_type =
4827                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4828                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4829         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4830
4831         /* Sync AEU offset */
4832         sync_offset = params->shmem_base +
4833                         offsetof(struct shmem_region,
4834                                  dev_info.port_hw_config[port].aeu_int_mask);
4835
4836         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4837
4838         /* Sync PFC status */
4839         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4840                 params->feature_config_flags |=
4841                                         FEATURE_CONFIG_PFC_ENABLED;
4842         else
4843                 params->feature_config_flags &=
4844                                         ~FEATURE_CONFIG_PFC_ENABLED;
4845
4846         if (SHMEM2_HAS(bp, link_attr_sync))
4847                 params->link_attr_sync = SHMEM2_RD(bp,
4848                                                  link_attr_sync[params->port]);
4849
4850         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4851                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4852         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4853                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4854 }
4855
4856 static void bnx2x_set_master_ln(struct link_params *params,
4857                                 struct bnx2x_phy *phy)
4858 {
4859         struct bnx2x *bp = params->bp;
4860         u16 new_master_ln, ser_lane;
4861         ser_lane = ((params->lane_config &
4862                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4863                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4864
4865         /* Set the master_ln for AN */
4866         CL22_RD_OVER_CL45(bp, phy,
4867                           MDIO_REG_BANK_XGXS_BLOCK2,
4868                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4869                           &new_master_ln);
4870
4871         CL22_WR_OVER_CL45(bp, phy,
4872                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4873                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4874                           (new_master_ln | ser_lane));
4875 }
4876
4877 static int bnx2x_reset_unicore(struct link_params *params,
4878                                struct bnx2x_phy *phy,
4879                                u8 set_serdes)
4880 {
4881         struct bnx2x *bp = params->bp;
4882         u16 mii_control;
4883         u16 i;
4884         CL22_RD_OVER_CL45(bp, phy,
4885                           MDIO_REG_BANK_COMBO_IEEE0,
4886                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4887
4888         /* Reset the unicore */
4889         CL22_WR_OVER_CL45(bp, phy,
4890                           MDIO_REG_BANK_COMBO_IEEE0,
4891                           MDIO_COMBO_IEEE0_MII_CONTROL,
4892                           (mii_control |
4893                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4894         if (set_serdes)
4895                 bnx2x_set_serdes_access(bp, params->port);
4896
4897         /* Wait for the reset to self clear */
4898         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4899                 udelay(5);
4900
4901                 /* The reset erased the previous bank value */
4902                 CL22_RD_OVER_CL45(bp, phy,
4903                                   MDIO_REG_BANK_COMBO_IEEE0,
4904                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4905                                   &mii_control);
4906
4907                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4908                         udelay(5);
4909                         return 0;
4910                 }
4911         }
4912
4913         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4914                               " Port %d\n",
4915                          params->port);
4916         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4917         return -EINVAL;
4918
4919 }
4920
4921 static void bnx2x_set_swap_lanes(struct link_params *params,
4922                                  struct bnx2x_phy *phy)
4923 {
4924         struct bnx2x *bp = params->bp;
4925         /* Each two bits represents a lane number:
4926          * No swap is 0123 => 0x1b no need to enable the swap
4927          */
4928         u16 rx_lane_swap, tx_lane_swap;
4929
4930         rx_lane_swap = ((params->lane_config &
4931                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4932                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4933         tx_lane_swap = ((params->lane_config &
4934                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4935                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4936
4937         if (rx_lane_swap != 0x1b) {
4938                 CL22_WR_OVER_CL45(bp, phy,
4939                                   MDIO_REG_BANK_XGXS_BLOCK2,
4940                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4941                                   (rx_lane_swap |
4942                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4943                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4944         } else {
4945                 CL22_WR_OVER_CL45(bp, phy,
4946                                   MDIO_REG_BANK_XGXS_BLOCK2,
4947                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4948         }
4949
4950         if (tx_lane_swap != 0x1b) {
4951                 CL22_WR_OVER_CL45(bp, phy,
4952                                   MDIO_REG_BANK_XGXS_BLOCK2,
4953                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4954                                   (tx_lane_swap |
4955                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4956         } else {
4957                 CL22_WR_OVER_CL45(bp, phy,
4958                                   MDIO_REG_BANK_XGXS_BLOCK2,
4959                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4960         }
4961 }
4962
4963 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4964                                          struct link_params *params)
4965 {
4966         struct bnx2x *bp = params->bp;
4967         u16 control2;
4968         CL22_RD_OVER_CL45(bp, phy,
4969                           MDIO_REG_BANK_SERDES_DIGITAL,
4970                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4971                           &control2);
4972         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4973                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4974         else
4975                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4976         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4977                 phy->speed_cap_mask, control2);
4978         CL22_WR_OVER_CL45(bp, phy,
4979                           MDIO_REG_BANK_SERDES_DIGITAL,
4980                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4981                           control2);
4982
4983         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4984              (phy->speed_cap_mask &
4985                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4986                 DP(NETIF_MSG_LINK, "XGXS\n");
4987
4988                 CL22_WR_OVER_CL45(bp, phy,
4989                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4990                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4991                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4992
4993                 CL22_RD_OVER_CL45(bp, phy,
4994                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4995                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4996                                   &control2);
4997
4998
4999                 control2 |=
5000                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
5001
5002                 CL22_WR_OVER_CL45(bp, phy,
5003                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
5004                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5005                                   control2);
5006
5007                 /* Disable parallel detection of HiG */
5008                 CL22_WR_OVER_CL45(bp, phy,
5009                                   MDIO_REG_BANK_XGXS_BLOCK2,
5010                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
5011                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5012                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5013         }
5014 }
5015
5016 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
5017                               struct link_params *params,
5018                               struct link_vars *vars,
5019                               u8 enable_cl73)
5020 {
5021         struct bnx2x *bp = params->bp;
5022         u16 reg_val;
5023
5024         /* CL37 Autoneg */
5025         CL22_RD_OVER_CL45(bp, phy,
5026                           MDIO_REG_BANK_COMBO_IEEE0,
5027                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5028
5029         /* CL37 Autoneg Enabled */
5030         if (vars->line_speed == SPEED_AUTO_NEG)
5031                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5032         else /* CL37 Autoneg Disabled */
5033                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5034                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5035
5036         CL22_WR_OVER_CL45(bp, phy,
5037                           MDIO_REG_BANK_COMBO_IEEE0,
5038                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5039
5040         /* Enable/Disable Autodetection */
5041
5042         CL22_RD_OVER_CL45(bp, phy,
5043                           MDIO_REG_BANK_SERDES_DIGITAL,
5044                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
5045         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5046                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5047         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5048         if (vars->line_speed == SPEED_AUTO_NEG)
5049                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5050         else
5051                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5052
5053         CL22_WR_OVER_CL45(bp, phy,
5054                           MDIO_REG_BANK_SERDES_DIGITAL,
5055                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5056
5057         /* Enable TetonII and BAM autoneg */
5058         CL22_RD_OVER_CL45(bp, phy,
5059                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5060                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5061                           &reg_val);
5062         if (vars->line_speed == SPEED_AUTO_NEG) {
5063                 /* Enable BAM aneg Mode and TetonII aneg Mode */
5064                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5065                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5066         } else {
5067                 /* TetonII and BAM Autoneg Disabled */
5068                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5069                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5070         }
5071         CL22_WR_OVER_CL45(bp, phy,
5072                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5073                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5074                           reg_val);
5075
5076         if (enable_cl73) {
5077                 /* Enable Cl73 FSM status bits */
5078                 CL22_WR_OVER_CL45(bp, phy,
5079                                   MDIO_REG_BANK_CL73_USERB0,
5080                                   MDIO_CL73_USERB0_CL73_UCTRL,
5081                                   0xe);
5082
5083                 /* Enable BAM Station Manager*/
5084                 CL22_WR_OVER_CL45(bp, phy,
5085                         MDIO_REG_BANK_CL73_USERB0,
5086                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5087                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5088                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5089                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5090
5091                 /* Advertise CL73 link speeds */
5092                 CL22_RD_OVER_CL45(bp, phy,
5093                                   MDIO_REG_BANK_CL73_IEEEB1,
5094                                   MDIO_CL73_IEEEB1_AN_ADV2,
5095                                   &reg_val);
5096                 if (phy->speed_cap_mask &
5097                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5098                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5099                 if (phy->speed_cap_mask &
5100                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5101                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5102
5103                 CL22_WR_OVER_CL45(bp, phy,
5104                                   MDIO_REG_BANK_CL73_IEEEB1,
5105                                   MDIO_CL73_IEEEB1_AN_ADV2,
5106                                   reg_val);
5107
5108                 /* CL73 Autoneg Enabled */
5109                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5110
5111         } else /* CL73 Autoneg Disabled */
5112                 reg_val = 0;
5113
5114         CL22_WR_OVER_CL45(bp, phy,
5115                           MDIO_REG_BANK_CL73_IEEEB0,
5116                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5117 }
5118
5119 /* Program SerDes, forced speed */
5120 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5121                                  struct link_params *params,
5122                                  struct link_vars *vars)
5123 {
5124         struct bnx2x *bp = params->bp;
5125         u16 reg_val;
5126
5127         /* Program duplex, disable autoneg and sgmii*/
5128         CL22_RD_OVER_CL45(bp, phy,
5129                           MDIO_REG_BANK_COMBO_IEEE0,
5130                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5131         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5132                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5133                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5134         if (phy->req_duplex == DUPLEX_FULL)
5135                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5136         CL22_WR_OVER_CL45(bp, phy,
5137                           MDIO_REG_BANK_COMBO_IEEE0,
5138                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5139
5140         /* Program speed
5141          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5142          */
5143         CL22_RD_OVER_CL45(bp, phy,
5144                           MDIO_REG_BANK_SERDES_DIGITAL,
5145                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5146         /* Clearing the speed value before setting the right speed */
5147         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5148
5149         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5150                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5151
5152         if (!((vars->line_speed == SPEED_1000) ||
5153               (vars->line_speed == SPEED_100) ||
5154               (vars->line_speed == SPEED_10))) {
5155
5156                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5157                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5158                 if (vars->line_speed == SPEED_10000)
5159                         reg_val |=
5160                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5161         }
5162
5163         CL22_WR_OVER_CL45(bp, phy,
5164                           MDIO_REG_BANK_SERDES_DIGITAL,
5165                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5166
5167 }
5168
5169 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5170                                               struct link_params *params)
5171 {
5172         struct bnx2x *bp = params->bp;
5173         u16 val = 0;
5174
5175         /* Set extended capabilities */
5176         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5177                 val |= MDIO_OVER_1G_UP1_2_5G;
5178         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5179                 val |= MDIO_OVER_1G_UP1_10G;
5180         CL22_WR_OVER_CL45(bp, phy,
5181                           MDIO_REG_BANK_OVER_1G,
5182                           MDIO_OVER_1G_UP1, val);
5183
5184         CL22_WR_OVER_CL45(bp, phy,
5185                           MDIO_REG_BANK_OVER_1G,
5186                           MDIO_OVER_1G_UP3, 0x400);
5187 }
5188
5189 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5190                                               struct link_params *params,
5191                                               u16 ieee_fc)
5192 {
5193         struct bnx2x *bp = params->bp;
5194         u16 val;
5195         /* For AN, we are always publishing full duplex */
5196
5197         CL22_WR_OVER_CL45(bp, phy,
5198                           MDIO_REG_BANK_COMBO_IEEE0,
5199                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5200         CL22_RD_OVER_CL45(bp, phy,
5201                           MDIO_REG_BANK_CL73_IEEEB1,
5202                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5203         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5204         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5205         CL22_WR_OVER_CL45(bp, phy,
5206                           MDIO_REG_BANK_CL73_IEEEB1,
5207                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5208 }
5209
5210 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5211                                   struct link_params *params,
5212                                   u8 enable_cl73)
5213 {
5214         struct bnx2x *bp = params->bp;
5215         u16 mii_control;
5216
5217         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5218         /* Enable and restart BAM/CL37 aneg */
5219
5220         if (enable_cl73) {
5221                 CL22_RD_OVER_CL45(bp, phy,
5222                                   MDIO_REG_BANK_CL73_IEEEB0,
5223                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5224                                   &mii_control);
5225
5226                 CL22_WR_OVER_CL45(bp, phy,
5227                                   MDIO_REG_BANK_CL73_IEEEB0,
5228                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5229                                   (mii_control |
5230                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5231                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5232         } else {
5233
5234                 CL22_RD_OVER_CL45(bp, phy,
5235                                   MDIO_REG_BANK_COMBO_IEEE0,
5236                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5237                                   &mii_control);
5238                 DP(NETIF_MSG_LINK,
5239                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5240                          mii_control);
5241                 CL22_WR_OVER_CL45(bp, phy,
5242                                   MDIO_REG_BANK_COMBO_IEEE0,
5243                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5244                                   (mii_control |
5245                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5246                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5247         }
5248 }
5249
5250 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5251                                            struct link_params *params,
5252                                            struct link_vars *vars)
5253 {
5254         struct bnx2x *bp = params->bp;
5255         u16 control1;
5256
5257         /* In SGMII mode, the unicore is always slave */
5258
5259         CL22_RD_OVER_CL45(bp, phy,
5260                           MDIO_REG_BANK_SERDES_DIGITAL,
5261                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5262                           &control1);
5263         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5264         /* Set sgmii mode (and not fiber) */
5265         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5266                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5267                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5268         CL22_WR_OVER_CL45(bp, phy,
5269                           MDIO_REG_BANK_SERDES_DIGITAL,
5270                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5271                           control1);
5272
5273         /* If forced speed */
5274         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5275                 /* Set speed, disable autoneg */
5276                 u16 mii_control;
5277
5278                 CL22_RD_OVER_CL45(bp, phy,
5279                                   MDIO_REG_BANK_COMBO_IEEE0,
5280                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5281                                   &mii_control);
5282                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5283                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5284                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5285
5286                 switch (vars->line_speed) {
5287                 case SPEED_100:
5288                         mii_control |=
5289                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5290                         break;
5291                 case SPEED_1000:
5292                         mii_control |=
5293                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5294                         break;
5295                 case SPEED_10:
5296                         /* There is nothing to set for 10M */
5297                         break;
5298                 default:
5299                         /* Invalid speed for SGMII */
5300                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5301                                   vars->line_speed);
5302                         break;
5303                 }
5304
5305                 /* Setting the full duplex */
5306                 if (phy->req_duplex == DUPLEX_FULL)
5307                         mii_control |=
5308                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5309                 CL22_WR_OVER_CL45(bp, phy,
5310                                   MDIO_REG_BANK_COMBO_IEEE0,
5311                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5312                                   mii_control);
5313
5314         } else { /* AN mode */
5315                 /* Enable and restart AN */
5316                 bnx2x_restart_autoneg(phy, params, 0);
5317         }
5318 }
5319
5320 /* Link management
5321  */
5322 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5323                                              struct link_params *params)
5324 {
5325         struct bnx2x *bp = params->bp;
5326         u16 pd_10g, status2_1000x;
5327         if (phy->req_line_speed != SPEED_AUTO_NEG)
5328                 return 0;
5329         CL22_RD_OVER_CL45(bp, phy,
5330                           MDIO_REG_BANK_SERDES_DIGITAL,
5331                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5332                           &status2_1000x);
5333         CL22_RD_OVER_CL45(bp, phy,
5334                           MDIO_REG_BANK_SERDES_DIGITAL,
5335                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5336                           &status2_1000x);
5337         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5338                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5339                          params->port);
5340                 return 1;
5341         }
5342
5343         CL22_RD_OVER_CL45(bp, phy,
5344                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5345                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5346                           &pd_10g);
5347
5348         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5349                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5350                          params->port);
5351                 return 1;
5352         }
5353         return 0;
5354 }
5355
5356 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5357                                 struct link_params *params,
5358                                 struct link_vars *vars,
5359                                 u32 gp_status)
5360 {
5361         u16 ld_pause;   /* local driver */
5362         u16 lp_pause;   /* link partner */
5363         u16 pause_result;
5364         struct bnx2x *bp = params->bp;
5365         if ((gp_status &
5366              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5367               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5368             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5369              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5370
5371                 CL22_RD_OVER_CL45(bp, phy,
5372                                   MDIO_REG_BANK_CL73_IEEEB1,
5373                                   MDIO_CL73_IEEEB1_AN_ADV1,
5374                                   &ld_pause);
5375                 CL22_RD_OVER_CL45(bp, phy,
5376                                   MDIO_REG_BANK_CL73_IEEEB1,
5377                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5378                                   &lp_pause);
5379                 pause_result = (ld_pause &
5380                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5381                 pause_result |= (lp_pause &
5382                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5383                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5384         } else {
5385                 CL22_RD_OVER_CL45(bp, phy,
5386                                   MDIO_REG_BANK_COMBO_IEEE0,
5387                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5388                                   &ld_pause);
5389                 CL22_RD_OVER_CL45(bp, phy,
5390                         MDIO_REG_BANK_COMBO_IEEE0,
5391                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5392                         &lp_pause);
5393                 pause_result = (ld_pause &
5394                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5395                 pause_result |= (lp_pause &
5396                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5397                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5398         }
5399         bnx2x_pause_resolve(vars, pause_result);
5400
5401 }
5402
5403 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5404                                     struct link_params *params,
5405                                     struct link_vars *vars,
5406                                     u32 gp_status)
5407 {
5408         struct bnx2x *bp = params->bp;
5409         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5410
5411         /* Resolve from gp_status in case of AN complete and not sgmii */
5412         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5413                 /* Update the advertised flow-controled of LD/LP in AN */
5414                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5415                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5416                 /* But set the flow-control result as the requested one */
5417                 vars->flow_ctrl = phy->req_flow_ctrl;
5418         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5419                 vars->flow_ctrl = params->req_fc_auto_adv;
5420         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5421                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5422                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5423                         vars->flow_ctrl = params->req_fc_auto_adv;
5424                         return;
5425                 }
5426                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5427         }
5428         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5429 }
5430
5431 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5432                                          struct link_params *params)
5433 {
5434         struct bnx2x *bp = params->bp;
5435         u16 rx_status, ustat_val, cl37_fsm_received;
5436         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5437         /* Step 1: Make sure signal is detected */
5438         CL22_RD_OVER_CL45(bp, phy,
5439                           MDIO_REG_BANK_RX0,
5440                           MDIO_RX0_RX_STATUS,
5441                           &rx_status);
5442         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5443             (MDIO_RX0_RX_STATUS_SIGDET)) {
5444                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5445                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5446                 CL22_WR_OVER_CL45(bp, phy,
5447                                   MDIO_REG_BANK_CL73_IEEEB0,
5448                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5449                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5450                 return;
5451         }
5452         /* Step 2: Check CL73 state machine */
5453         CL22_RD_OVER_CL45(bp, phy,
5454                           MDIO_REG_BANK_CL73_USERB0,
5455                           MDIO_CL73_USERB0_CL73_USTAT1,
5456                           &ustat_val);
5457         if ((ustat_val &
5458              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5459               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5460             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5461               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5462                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5463                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5464                 return;
5465         }
5466         /* Step 3: Check CL37 Message Pages received to indicate LP
5467          * supports only CL37
5468          */
5469         CL22_RD_OVER_CL45(bp, phy,
5470                           MDIO_REG_BANK_REMOTE_PHY,
5471                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5472                           &cl37_fsm_received);
5473         if ((cl37_fsm_received &
5474              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5475              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5476             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5477               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5478                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5479                              "misc_rx_status(0x8330) = 0x%x\n",
5480                          cl37_fsm_received);
5481                 return;
5482         }
5483         /* The combined cl37/cl73 fsm state information indicating that
5484          * we are connected to a device which does not support cl73, but
5485          * does support cl37 BAM. In this case we disable cl73 and
5486          * restart cl37 auto-neg
5487          */
5488
5489         /* Disable CL73 */
5490         CL22_WR_OVER_CL45(bp, phy,
5491                           MDIO_REG_BANK_CL73_IEEEB0,
5492                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5493                           0);
5494         /* Restart CL37 autoneg */
5495         bnx2x_restart_autoneg(phy, params, 0);
5496         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5497 }
5498
5499 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5500                                   struct link_params *params,
5501                                   struct link_vars *vars,
5502                                   u32 gp_status)
5503 {
5504         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5505                 vars->link_status |=
5506                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5507
5508         if (bnx2x_direct_parallel_detect_used(phy, params))
5509                 vars->link_status |=
5510                         LINK_STATUS_PARALLEL_DETECTION_USED;
5511 }
5512 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5513                                      struct link_params *params,
5514                                       struct link_vars *vars,
5515                                       u16 is_link_up,
5516                                       u16 speed_mask,
5517                                       u16 is_duplex)
5518 {
5519         struct bnx2x *bp = params->bp;
5520         if (phy->req_line_speed == SPEED_AUTO_NEG)
5521                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5522         if (is_link_up) {
5523                 DP(NETIF_MSG_LINK, "phy link up\n");
5524
5525                 vars->phy_link_up = 1;
5526                 vars->link_status |= LINK_STATUS_LINK_UP;
5527
5528                 switch (speed_mask) {
5529                 case GP_STATUS_10M:
5530                         vars->line_speed = SPEED_10;
5531                         if (is_duplex == DUPLEX_FULL)
5532                                 vars->link_status |= LINK_10TFD;
5533                         else
5534                                 vars->link_status |= LINK_10THD;
5535                         break;
5536
5537                 case GP_STATUS_100M:
5538                         vars->line_speed = SPEED_100;
5539                         if (is_duplex == DUPLEX_FULL)
5540                                 vars->link_status |= LINK_100TXFD;
5541                         else
5542                                 vars->link_status |= LINK_100TXHD;
5543                         break;
5544
5545                 case GP_STATUS_1G:
5546                 case GP_STATUS_1G_KX:
5547                         vars->line_speed = SPEED_1000;
5548                         if (is_duplex == DUPLEX_FULL)
5549                                 vars->link_status |= LINK_1000TFD;
5550                         else
5551                                 vars->link_status |= LINK_1000THD;
5552                         break;
5553
5554                 case GP_STATUS_2_5G:
5555                         vars->line_speed = SPEED_2500;
5556                         if (is_duplex == DUPLEX_FULL)
5557                                 vars->link_status |= LINK_2500TFD;
5558                         else
5559                                 vars->link_status |= LINK_2500THD;
5560                         break;
5561
5562                 case GP_STATUS_5G:
5563                 case GP_STATUS_6G:
5564                         DP(NETIF_MSG_LINK,
5565                                  "link speed unsupported  gp_status 0x%x\n",
5566                                   speed_mask);
5567                         return -EINVAL;
5568
5569                 case GP_STATUS_10G_KX4:
5570                 case GP_STATUS_10G_HIG:
5571                 case GP_STATUS_10G_CX4:
5572                 case GP_STATUS_10G_KR:
5573                 case GP_STATUS_10G_SFI:
5574                 case GP_STATUS_10G_XFI:
5575                         vars->line_speed = SPEED_10000;
5576                         vars->link_status |= LINK_10GTFD;
5577                         break;
5578                 case GP_STATUS_20G_DXGXS:
5579                 case GP_STATUS_20G_KR2:
5580                         vars->line_speed = SPEED_20000;
5581                         vars->link_status |= LINK_20GTFD;
5582                         break;
5583                 default:
5584                         DP(NETIF_MSG_LINK,
5585                                   "link speed unsupported gp_status 0x%x\n",
5586                                   speed_mask);
5587                         return -EINVAL;
5588                 }
5589         } else { /* link_down */
5590                 DP(NETIF_MSG_LINK, "phy link down\n");
5591
5592                 vars->phy_link_up = 0;
5593
5594                 vars->duplex = DUPLEX_FULL;
5595                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5596                 vars->mac_type = MAC_TYPE_NONE;
5597         }
5598         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5599                     vars->phy_link_up, vars->line_speed);
5600         return 0;
5601 }
5602
5603 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5604                                       struct link_params *params,
5605                                       struct link_vars *vars)
5606 {
5607         struct bnx2x *bp = params->bp;
5608
5609         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5610         int rc = 0;
5611
5612         /* Read gp_status */
5613         CL22_RD_OVER_CL45(bp, phy,
5614                           MDIO_REG_BANK_GP_STATUS,
5615                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5616                           &gp_status);
5617         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5618                 duplex = DUPLEX_FULL;
5619         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5620                 link_up = 1;
5621         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5622         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5623                        gp_status, link_up, speed_mask);
5624         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5625                                          duplex);
5626         if (rc == -EINVAL)
5627                 return rc;
5628
5629         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5630                 if (SINGLE_MEDIA_DIRECT(params)) {
5631                         vars->duplex = duplex;
5632                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5633                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5634                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5635                                                       gp_status);
5636                 }
5637         } else { /* Link_down */
5638                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5639                     SINGLE_MEDIA_DIRECT(params)) {
5640                         /* Check signal is detected */
5641                         bnx2x_check_fallback_to_cl37(phy, params);
5642                 }
5643         }
5644
5645         /* Read LP advertised speeds*/
5646         if (SINGLE_MEDIA_DIRECT(params) &&
5647             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5648                 u16 val;
5649
5650                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5651                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5652
5653                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5654                         vars->link_status |=
5655                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5656                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5657                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5658                         vars->link_status |=
5659                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5660
5661                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5662                                   MDIO_OVER_1G_LP_UP1, &val);
5663
5664                 if (val & MDIO_OVER_1G_UP1_2_5G)
5665                         vars->link_status |=
5666                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5667                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5668                         vars->link_status |=
5669                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5670         }
5671
5672         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5673                    vars->duplex, vars->flow_ctrl, vars->link_status);
5674         return rc;
5675 }
5676
5677 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5678                                      struct link_params *params,
5679                                      struct link_vars *vars)
5680 {
5681         struct bnx2x *bp = params->bp;
5682         u8 lane;
5683         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5684         int rc = 0;
5685         lane = bnx2x_get_warpcore_lane(phy, params);
5686         /* Read gp_status */
5687         if ((params->loopback_mode) &&
5688             (phy->flags & FLAGS_WC_DUAL_MODE)) {
5689                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5690                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5691                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5692                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5693                 link_up &= 0x1;
5694         } else if ((phy->req_line_speed > SPEED_10000) &&
5695                 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5696                 u16 temp_link_up;
5697                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5698                                 1, &temp_link_up);
5699                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5700                                 1, &link_up);
5701                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5702                                temp_link_up, link_up);
5703                 link_up &= (1<<2);
5704                 if (link_up)
5705                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5706         } else {
5707                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5708                                 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5709                                 &gp_status1);
5710                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5711                 /* Check for either KR, 1G, or AN up. */
5712                 link_up = ((gp_status1 >> 8) |
5713                            (gp_status1 >> 12) |
5714                            (gp_status1)) &
5715                         (1 << lane);
5716                 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5717                         u16 an_link;
5718                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5719                                         MDIO_AN_REG_STATUS, &an_link);
5720                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5721                                         MDIO_AN_REG_STATUS, &an_link);
5722                         link_up |= (an_link & (1<<2));
5723                 }
5724                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5725                         u16 pd, gp_status4;
5726                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5727                                 /* Check Autoneg complete */
5728                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5729                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5730                                                 &gp_status4);
5731                                 if (gp_status4 & ((1<<12)<<lane))
5732                                         vars->link_status |=
5733                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5734
5735                                 /* Check parallel detect used */
5736                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5737                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5738                                                 &pd);
5739                                 if (pd & (1<<15))
5740                                         vars->link_status |=
5741                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5742                         }
5743                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5744                         vars->duplex = duplex;
5745                 }
5746         }
5747
5748         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5749             SINGLE_MEDIA_DIRECT(params)) {
5750                 u16 val;
5751
5752                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5753                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5754
5755                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5756                         vars->link_status |=
5757                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5758                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5759                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5760                         vars->link_status |=
5761                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5762
5763                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5764                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5765
5766                 if (val & MDIO_OVER_1G_UP1_2_5G)
5767                         vars->link_status |=
5768                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5769                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5770                         vars->link_status |=
5771                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5772
5773         }
5774
5775
5776         if (lane < 2) {
5777                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5778                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5779         } else {
5780                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5781                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5782         }
5783         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5784
5785         if ((lane & 1) == 0)
5786                 gp_speed <<= 8;
5787         gp_speed &= 0x3f00;
5788         link_up = !!link_up;
5789
5790         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5791                                          duplex);
5792
5793         /* In case of KR link down, start up the recovering procedure */
5794         if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
5795             (!(phy->flags & FLAGS_WC_DUAL_MODE)))
5796                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5797
5798         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5799                    vars->duplex, vars->flow_ctrl, vars->link_status);
5800         return rc;
5801 }
5802 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5803 {
5804         struct bnx2x *bp = params->bp;
5805         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5806         u16 lp_up2;
5807         u16 tx_driver;
5808         u16 bank;
5809
5810         /* Read precomp */
5811         CL22_RD_OVER_CL45(bp, phy,
5812                           MDIO_REG_BANK_OVER_1G,
5813                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5814
5815         /* Bits [10:7] at lp_up2, positioned at [15:12] */
5816         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5817                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5818                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5819
5820         if (lp_up2 == 0)
5821                 return;
5822
5823         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5824               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5825                 CL22_RD_OVER_CL45(bp, phy,
5826                                   bank,
5827                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5828
5829                 /* Replace tx_driver bits [15:12] */
5830                 if (lp_up2 !=
5831                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5832                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5833                         tx_driver |= lp_up2;
5834                         CL22_WR_OVER_CL45(bp, phy,
5835                                           bank,
5836                                           MDIO_TX0_TX_DRIVER, tx_driver);
5837                 }
5838         }
5839 }
5840
5841 static int bnx2x_emac_program(struct link_params *params,
5842                               struct link_vars *vars)
5843 {
5844         struct bnx2x *bp = params->bp;
5845         u8 port = params->port;
5846         u16 mode = 0;
5847
5848         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5849         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5850                        EMAC_REG_EMAC_MODE,
5851                        (EMAC_MODE_25G_MODE |
5852                         EMAC_MODE_PORT_MII_10M |
5853                         EMAC_MODE_HALF_DUPLEX));
5854         switch (vars->line_speed) {
5855         case SPEED_10:
5856                 mode |= EMAC_MODE_PORT_MII_10M;
5857                 break;
5858
5859         case SPEED_100:
5860                 mode |= EMAC_MODE_PORT_MII;
5861                 break;
5862
5863         case SPEED_1000:
5864                 mode |= EMAC_MODE_PORT_GMII;
5865                 break;
5866
5867         case SPEED_2500:
5868                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5869                 break;
5870
5871         default:
5872                 /* 10G not valid for EMAC */
5873                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5874                            vars->line_speed);
5875                 return -EINVAL;
5876         }
5877
5878         if (vars->duplex == DUPLEX_HALF)
5879                 mode |= EMAC_MODE_HALF_DUPLEX;
5880         bnx2x_bits_en(bp,
5881                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5882                       mode);
5883
5884         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5885         return 0;
5886 }
5887
5888 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5889                                   struct link_params *params)
5890 {
5891
5892         u16 bank, i = 0;
5893         struct bnx2x *bp = params->bp;
5894
5895         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5896               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5897                         CL22_WR_OVER_CL45(bp, phy,
5898                                           bank,
5899                                           MDIO_RX0_RX_EQ_BOOST,
5900                                           phy->rx_preemphasis[i]);
5901         }
5902
5903         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5904                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5905                         CL22_WR_OVER_CL45(bp, phy,
5906                                           bank,
5907                                           MDIO_TX0_TX_DRIVER,
5908                                           phy->tx_preemphasis[i]);
5909         }
5910 }
5911
5912 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5913                                    struct link_params *params,
5914                                    struct link_vars *vars)
5915 {
5916         struct bnx2x *bp = params->bp;
5917         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5918                           (params->loopback_mode == LOOPBACK_XGXS));
5919         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5920                 if (SINGLE_MEDIA_DIRECT(params) &&
5921                     (params->feature_config_flags &
5922                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5923                         bnx2x_set_preemphasis(phy, params);
5924
5925                 /* Forced speed requested? */
5926                 if (vars->line_speed != SPEED_AUTO_NEG ||
5927                     (SINGLE_MEDIA_DIRECT(params) &&
5928                      params->loopback_mode == LOOPBACK_EXT)) {
5929                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5930
5931                         /* Disable autoneg */
5932                         bnx2x_set_autoneg(phy, params, vars, 0);
5933
5934                         /* Program speed and duplex */
5935                         bnx2x_program_serdes(phy, params, vars);
5936
5937                 } else { /* AN_mode */
5938                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5939
5940                         /* AN enabled */
5941                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5942
5943                         /* Program duplex & pause advertisement (for aneg) */
5944                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5945                                                           vars->ieee_fc);
5946
5947                         /* Enable autoneg */
5948                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5949
5950                         /* Enable and restart AN */
5951                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5952                 }
5953
5954         } else { /* SGMII mode */
5955                 DP(NETIF_MSG_LINK, "SGMII\n");
5956
5957                 bnx2x_initialize_sgmii_process(phy, params, vars);
5958         }
5959 }
5960
5961 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5962                           struct link_params *params,
5963                           struct link_vars *vars)
5964 {
5965         int rc;
5966         vars->phy_flags |= PHY_XGXS_FLAG;
5967         if ((phy->req_line_speed &&
5968              ((phy->req_line_speed == SPEED_100) ||
5969               (phy->req_line_speed == SPEED_10))) ||
5970             (!phy->req_line_speed &&
5971              (phy->speed_cap_mask >=
5972               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5973              (phy->speed_cap_mask <
5974               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5975             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5976                 vars->phy_flags |= PHY_SGMII_FLAG;
5977         else
5978                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5979
5980         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5981         bnx2x_set_aer_mmd(params, phy);
5982         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5983                 bnx2x_set_master_ln(params, phy);
5984
5985         rc = bnx2x_reset_unicore(params, phy, 0);
5986         /* Reset the SerDes and wait for reset bit return low */
5987         if (rc)
5988                 return rc;
5989
5990         bnx2x_set_aer_mmd(params, phy);
5991         /* Setting the masterLn_def again after the reset */
5992         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5993                 bnx2x_set_master_ln(params, phy);
5994                 bnx2x_set_swap_lanes(params, phy);
5995         }
5996
5997         return rc;
5998 }
5999
6000 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
6001                                      struct bnx2x_phy *phy,
6002                                      struct link_params *params)
6003 {
6004         u16 cnt, ctrl;
6005         /* Wait for soft reset to get cleared up to 1 sec */
6006         for (cnt = 0; cnt < 1000; cnt++) {
6007                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6008                         bnx2x_cl22_read(bp, phy,
6009                                 MDIO_PMA_REG_CTRL, &ctrl);
6010                 else
6011                         bnx2x_cl45_read(bp, phy,
6012                                 MDIO_PMA_DEVAD,
6013                                 MDIO_PMA_REG_CTRL, &ctrl);
6014                 if (!(ctrl & (1<<15)))
6015                         break;
6016                 usleep_range(1000, 2000);
6017         }
6018
6019         if (cnt == 1000)
6020                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
6021                                       " Port %d\n",
6022                          params->port);
6023         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6024         return cnt;
6025 }
6026
6027 static void bnx2x_link_int_enable(struct link_params *params)
6028 {
6029         u8 port = params->port;
6030         u32 mask;
6031         struct bnx2x *bp = params->bp;
6032
6033         /* Setting the status to report on link up for either XGXS or SerDes */
6034         if (CHIP_IS_E3(bp)) {
6035                 mask = NIG_MASK_XGXS0_LINK_STATUS;
6036                 if (!(SINGLE_MEDIA_DIRECT(params)))
6037                         mask |= NIG_MASK_MI_INT;
6038         } else if (params->switch_cfg == SWITCH_CFG_10G) {
6039                 mask = (NIG_MASK_XGXS0_LINK10G |
6040                         NIG_MASK_XGXS0_LINK_STATUS);
6041                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
6042                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6043                         params->phy[INT_PHY].type !=
6044                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6045                         mask |= NIG_MASK_MI_INT;
6046                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6047                 }
6048
6049         } else { /* SerDes */
6050                 mask = NIG_MASK_SERDES0_LINK_STATUS;
6051                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6052                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6053                         params->phy[INT_PHY].type !=
6054                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6055                         mask |= NIG_MASK_MI_INT;
6056                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6057                 }
6058         }
6059         bnx2x_bits_en(bp,
6060                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6061                       mask);
6062
6063         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6064                  (params->switch_cfg == SWITCH_CFG_10G),
6065                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6066         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6067                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6068                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6069                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6070         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6071            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6072            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6073 }
6074
6075 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6076                                      u8 exp_mi_int)
6077 {
6078         u32 latch_status = 0;
6079
6080         /* Disable the MI INT ( external phy int ) by writing 1 to the
6081          * status register. Link down indication is high-active-signal,
6082          * so in this case we need to write the status to clear the XOR
6083          */
6084         /* Read Latched signals */
6085         latch_status = REG_RD(bp,
6086                                     NIG_REG_LATCH_STATUS_0 + port*8);
6087         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6088         /* Handle only those with latched-signal=up.*/
6089         if (exp_mi_int)
6090                 bnx2x_bits_en(bp,
6091                               NIG_REG_STATUS_INTERRUPT_PORT0
6092                               + port*4,
6093                               NIG_STATUS_EMAC0_MI_INT);
6094         else
6095                 bnx2x_bits_dis(bp,
6096                                NIG_REG_STATUS_INTERRUPT_PORT0
6097                                + port*4,
6098                                NIG_STATUS_EMAC0_MI_INT);
6099
6100         if (latch_status & 1) {
6101
6102                 /* For all latched-signal=up : Re-Arm Latch signals */
6103                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6104                        (latch_status & 0xfffe) | (latch_status & 1));
6105         }
6106         /* For all latched-signal=up,Write original_signal to status */
6107 }
6108
6109 static void bnx2x_link_int_ack(struct link_params *params,
6110                                struct link_vars *vars, u8 is_10g_plus)
6111 {
6112         struct bnx2x *bp = params->bp;
6113         u8 port = params->port;
6114         u32 mask;
6115         /* First reset all status we assume only one line will be
6116          * change at a time
6117          */
6118         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6119                        (NIG_STATUS_XGXS0_LINK10G |
6120                         NIG_STATUS_XGXS0_LINK_STATUS |
6121                         NIG_STATUS_SERDES0_LINK_STATUS));
6122         if (vars->phy_link_up) {
6123                 if (USES_WARPCORE(bp))
6124                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
6125                 else {
6126                         if (is_10g_plus)
6127                                 mask = NIG_STATUS_XGXS0_LINK10G;
6128                         else if (params->switch_cfg == SWITCH_CFG_10G) {
6129                                 /* Disable the link interrupt by writing 1 to
6130                                  * the relevant lane in the status register
6131                                  */
6132                                 u32 ser_lane =
6133                                         ((params->lane_config &
6134                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6135                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6136                                 mask = ((1 << ser_lane) <<
6137                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6138                         } else
6139                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6140                 }
6141                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6142                                mask);
6143                 bnx2x_bits_en(bp,
6144                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6145                               mask);
6146         }
6147 }
6148
6149 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6150 {
6151         u8 *str_ptr = str;
6152         u32 mask = 0xf0000000;
6153         u8 shift = 8*4;
6154         u8 digit;
6155         u8 remove_leading_zeros = 1;
6156         if (*len < 10) {
6157                 /* Need more than 10chars for this format */
6158                 *str_ptr = '\0';
6159                 (*len)--;
6160                 return -EINVAL;
6161         }
6162         while (shift > 0) {
6163
6164                 shift -= 4;
6165                 digit = ((num & mask) >> shift);
6166                 if (digit == 0 && remove_leading_zeros) {
6167                         mask = mask >> 4;
6168                         continue;
6169                 } else if (digit < 0xa)
6170                         *str_ptr = digit + '0';
6171                 else
6172                         *str_ptr = digit - 0xa + 'a';
6173                 remove_leading_zeros = 0;
6174                 str_ptr++;
6175                 (*len)--;
6176                 mask = mask >> 4;
6177                 if (shift == 4*4) {
6178                         *str_ptr = '.';
6179                         str_ptr++;
6180                         (*len)--;
6181                         remove_leading_zeros = 1;
6182                 }
6183         }
6184         return 0;
6185 }
6186
6187
6188 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6189 {
6190         str[0] = '\0';
6191         (*len)--;
6192         return 0;
6193 }
6194
6195 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6196                                  u16 len)
6197 {
6198         struct bnx2x *bp;
6199         u32 spirom_ver = 0;
6200         int status = 0;
6201         u8 *ver_p = version;
6202         u16 remain_len = len;
6203         if (version == NULL || params == NULL)
6204                 return -EINVAL;
6205         bp = params->bp;
6206
6207         /* Extract first external phy*/
6208         version[0] = '\0';
6209         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6210
6211         if (params->phy[EXT_PHY1].format_fw_ver) {
6212                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6213                                                               ver_p,
6214                                                               &remain_len);
6215                 ver_p += (len - remain_len);
6216         }
6217         if ((params->num_phys == MAX_PHYS) &&
6218             (params->phy[EXT_PHY2].ver_addr != 0)) {
6219                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6220                 if (params->phy[EXT_PHY2].format_fw_ver) {
6221                         *ver_p = '/';
6222                         ver_p++;
6223                         remain_len--;
6224                         status |= params->phy[EXT_PHY2].format_fw_ver(
6225                                 spirom_ver,
6226                                 ver_p,
6227                                 &remain_len);
6228                         ver_p = version + (len - remain_len);
6229                 }
6230         }
6231         *ver_p = '\0';
6232         return status;
6233 }
6234
6235 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6236                                     struct link_params *params)
6237 {
6238         u8 port = params->port;
6239         struct bnx2x *bp = params->bp;
6240
6241         if (phy->req_line_speed != SPEED_1000) {
6242                 u32 md_devad = 0;
6243
6244                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6245
6246                 if (!CHIP_IS_E3(bp)) {
6247                         /* Change the uni_phy_addr in the nig */
6248                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6249                                                port*0x18));
6250
6251                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6252                                0x5);
6253                 }
6254
6255                 bnx2x_cl45_write(bp, phy,
6256                                  5,
6257                                  (MDIO_REG_BANK_AER_BLOCK +
6258                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6259                                  0x2800);
6260
6261                 bnx2x_cl45_write(bp, phy,
6262                                  5,
6263                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6264                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6265                                  0x6041);
6266                 msleep(200);
6267                 /* Set aer mmd back */
6268                 bnx2x_set_aer_mmd(params, phy);
6269
6270                 if (!CHIP_IS_E3(bp)) {
6271                         /* And md_devad */
6272                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6273                                md_devad);
6274                 }
6275         } else {
6276                 u16 mii_ctrl;
6277                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6278                 bnx2x_cl45_read(bp, phy, 5,
6279                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6280                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6281                                 &mii_ctrl);
6282                 bnx2x_cl45_write(bp, phy, 5,
6283                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6284                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6285                                  mii_ctrl |
6286                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6287         }
6288 }
6289
6290 int bnx2x_set_led(struct link_params *params,
6291                   struct link_vars *vars, u8 mode, u32 speed)
6292 {
6293         u8 port = params->port;
6294         u16 hw_led_mode = params->hw_led_mode;
6295         int rc = 0;
6296         u8 phy_idx;
6297         u32 tmp;
6298         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6299         struct bnx2x *bp = params->bp;
6300         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6301         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6302                  speed, hw_led_mode);
6303         /* In case */
6304         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6305                 if (params->phy[phy_idx].set_link_led) {
6306                         params->phy[phy_idx].set_link_led(
6307                                 &params->phy[phy_idx], params, mode);
6308                 }
6309         }
6310
6311         switch (mode) {
6312         case LED_MODE_FRONT_PANEL_OFF:
6313         case LED_MODE_OFF:
6314                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6315                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6316                        SHARED_HW_CFG_LED_MAC1);
6317
6318                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6319                 if (params->phy[EXT_PHY1].type ==
6320                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6321                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6322                                 EMAC_LED_100MB_OVERRIDE |
6323                                 EMAC_LED_10MB_OVERRIDE);
6324                 else
6325                         tmp |= EMAC_LED_OVERRIDE;
6326
6327                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6328                 break;
6329
6330         case LED_MODE_OPER:
6331                 /* For all other phys, OPER mode is same as ON, so in case
6332                  * link is down, do nothing
6333                  */
6334                 if (!vars->link_up)
6335                         break;
6336         case LED_MODE_ON:
6337                 if (((params->phy[EXT_PHY1].type ==
6338                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6339                          (params->phy[EXT_PHY1].type ==
6340                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6341                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6342                         /* This is a work-around for E2+8727 Configurations */
6343                         if (mode == LED_MODE_ON ||
6344                                 speed == SPEED_10000){
6345                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6346                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6347
6348                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6349                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6350                                         (tmp | EMAC_LED_OVERRIDE));
6351                                 /* Return here without enabling traffic
6352                                  * LED blink and setting rate in ON mode.
6353                                  * In oper mode, enabling LED blink
6354                                  * and setting rate is needed.
6355                                  */
6356                                 if (mode == LED_MODE_ON)
6357                                         return rc;
6358                         }
6359                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6360                         /* This is a work-around for HW issue found when link
6361                          * is up in CL73
6362                          */
6363                         if ((!CHIP_IS_E3(bp)) ||
6364                             (CHIP_IS_E3(bp) &&
6365                              mode == LED_MODE_ON))
6366                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6367
6368                         if (CHIP_IS_E1x(bp) ||
6369                             CHIP_IS_E2(bp) ||
6370                             (mode == LED_MODE_ON))
6371                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6372                         else
6373                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6374                                        hw_led_mode);
6375                 } else if ((params->phy[EXT_PHY1].type ==
6376                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6377                            (mode == LED_MODE_ON)) {
6378                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6379                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6380                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6381                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6382                         /* Break here; otherwise, it'll disable the
6383                          * intended override.
6384                          */
6385                         break;
6386                 } else {
6387                         u32 nig_led_mode = ((params->hw_led_mode <<
6388                                              SHARED_HW_CFG_LED_MODE_SHIFT) ==
6389                                             SHARED_HW_CFG_LED_EXTPHY2) ?
6390                                 (SHARED_HW_CFG_LED_PHY1 >>
6391                                  SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
6392                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6393                                nig_led_mode);
6394                 }
6395
6396                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6397                 /* Set blinking rate to ~15.9Hz */
6398                 if (CHIP_IS_E3(bp))
6399                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6400                                LED_BLINK_RATE_VAL_E3);
6401                 else
6402                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6403                                LED_BLINK_RATE_VAL_E1X_E2);
6404                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6405                        port*4, 1);
6406                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6407                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6408                         (tmp & (~EMAC_LED_OVERRIDE)));
6409
6410                 if (CHIP_IS_E1(bp) &&
6411                     ((speed == SPEED_2500) ||
6412                      (speed == SPEED_1000) ||
6413                      (speed == SPEED_100) ||
6414                      (speed == SPEED_10))) {
6415                         /* For speeds less than 10G LED scheme is different */
6416                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6417                                + port*4, 1);
6418                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6419                                port*4, 0);
6420                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6421                                port*4, 1);
6422                 }
6423                 break;
6424
6425         default:
6426                 rc = -EINVAL;
6427                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6428                          mode);
6429                 break;
6430         }
6431         return rc;
6432
6433 }
6434
6435 /* This function comes to reflect the actual link state read DIRECTLY from the
6436  * HW
6437  */
6438 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6439                     u8 is_serdes)
6440 {
6441         struct bnx2x *bp = params->bp;
6442         u16 gp_status = 0, phy_index = 0;
6443         u8 ext_phy_link_up = 0, serdes_phy_type;
6444         struct link_vars temp_vars;
6445         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6446
6447         if (CHIP_IS_E3(bp)) {
6448                 u16 link_up;
6449                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6450                     > SPEED_10000) {
6451                         /* Check 20G link */
6452                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6453                                         1, &link_up);
6454                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6455                                         1, &link_up);
6456                         link_up &= (1<<2);
6457                 } else {
6458                         /* Check 10G link and below*/
6459                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6460                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6461                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6462                                         &gp_status);
6463                         gp_status = ((gp_status >> 8) & 0xf) |
6464                                 ((gp_status >> 12) & 0xf);
6465                         link_up = gp_status & (1 << lane);
6466                 }
6467                 if (!link_up)
6468                         return -ESRCH;
6469         } else {
6470                 CL22_RD_OVER_CL45(bp, int_phy,
6471                           MDIO_REG_BANK_GP_STATUS,
6472                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6473                           &gp_status);
6474         /* Link is up only if both local phy and external phy are up */
6475         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6476                 return -ESRCH;
6477         }
6478         /* In XGXS loopback mode, do not check external PHY */
6479         if (params->loopback_mode == LOOPBACK_XGXS)
6480                 return 0;
6481
6482         switch (params->num_phys) {
6483         case 1:
6484                 /* No external PHY */
6485                 return 0;
6486         case 2:
6487                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6488                         &params->phy[EXT_PHY1],
6489                         params, &temp_vars);
6490                 break;
6491         case 3: /* Dual Media */
6492                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6493                       phy_index++) {
6494                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6495                                             ETH_PHY_SFPP_10G_FIBER) ||
6496                                            (params->phy[phy_index].media_type ==
6497                                             ETH_PHY_SFP_1G_FIBER) ||
6498                                            (params->phy[phy_index].media_type ==
6499                                             ETH_PHY_XFP_FIBER) ||
6500                                            (params->phy[phy_index].media_type ==
6501                                             ETH_PHY_DA_TWINAX));
6502
6503                         if (is_serdes != serdes_phy_type)
6504                                 continue;
6505                         if (params->phy[phy_index].read_status) {
6506                                 ext_phy_link_up |=
6507                                         params->phy[phy_index].read_status(
6508                                                 &params->phy[phy_index],
6509                                                 params, &temp_vars);
6510                         }
6511                 }
6512                 break;
6513         }
6514         if (ext_phy_link_up)
6515                 return 0;
6516         return -ESRCH;
6517 }
6518
6519 static int bnx2x_link_initialize(struct link_params *params,
6520                                  struct link_vars *vars)
6521 {
6522         u8 phy_index, non_ext_phy;
6523         struct bnx2x *bp = params->bp;
6524         /* In case of external phy existence, the line speed would be the
6525          * line speed linked up by the external phy. In case it is direct
6526          * only, then the line_speed during initialization will be
6527          * equal to the req_line_speed
6528          */
6529         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6530
6531         /* Initialize the internal phy in case this is a direct board
6532          * (no external phys), or this board has external phy which requires
6533          * to first.
6534          */
6535         if (!USES_WARPCORE(bp))
6536                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6537         /* init ext phy and enable link state int */
6538         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6539                        (params->loopback_mode == LOOPBACK_XGXS));
6540
6541         if (non_ext_phy ||
6542             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6543             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6544                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6545                 if (vars->line_speed == SPEED_AUTO_NEG &&
6546                     (CHIP_IS_E1x(bp) ||
6547                      CHIP_IS_E2(bp)))
6548                         bnx2x_set_parallel_detection(phy, params);
6549                 if (params->phy[INT_PHY].config_init)
6550                         params->phy[INT_PHY].config_init(phy, params, vars);
6551         }
6552
6553         /* Re-read this value in case it was changed inside config_init due to
6554          * limitations of optic module
6555          */
6556         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6557
6558         /* Init external phy*/
6559         if (non_ext_phy) {
6560                 if (params->phy[INT_PHY].supported &
6561                     SUPPORTED_FIBRE)
6562                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6563         } else {
6564                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6565                       phy_index++) {
6566                         /* No need to initialize second phy in case of first
6567                          * phy only selection. In case of second phy, we do
6568                          * need to initialize the first phy, since they are
6569                          * connected.
6570                          */
6571                         if (params->phy[phy_index].supported &
6572                             SUPPORTED_FIBRE)
6573                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6574
6575                         if (phy_index == EXT_PHY2 &&
6576                             (bnx2x_phy_selection(params) ==
6577                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6578                                 DP(NETIF_MSG_LINK,
6579                                    "Not initializing second phy\n");
6580                                 continue;
6581                         }
6582                         params->phy[phy_index].config_init(
6583                                 &params->phy[phy_index],
6584                                 params, vars);
6585                 }
6586         }
6587         /* Reset the interrupt indication after phy was initialized */
6588         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6589                        params->port*4,
6590                        (NIG_STATUS_XGXS0_LINK10G |
6591                         NIG_STATUS_XGXS0_LINK_STATUS |
6592                         NIG_STATUS_SERDES0_LINK_STATUS |
6593                         NIG_MASK_MI_INT));
6594         return 0;
6595 }
6596
6597 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6598                                  struct link_params *params)
6599 {
6600         /* Reset the SerDes/XGXS */
6601         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6602                (0x1ff << (params->port*16)));
6603 }
6604
6605 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6606                                         struct link_params *params)
6607 {
6608         struct bnx2x *bp = params->bp;
6609         u8 gpio_port;
6610         /* HW reset */
6611         if (CHIP_IS_E2(bp))
6612                 gpio_port = BP_PATH(bp);
6613         else
6614                 gpio_port = params->port;
6615         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6616                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6617                        gpio_port);
6618         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6619                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6620                        gpio_port);
6621         DP(NETIF_MSG_LINK, "reset external PHY\n");
6622 }
6623
6624 static int bnx2x_update_link_down(struct link_params *params,
6625                                   struct link_vars *vars)
6626 {
6627         struct bnx2x *bp = params->bp;
6628         u8 port = params->port;
6629
6630         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6631         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6632         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6633         /* Indicate no mac active */
6634         vars->mac_type = MAC_TYPE_NONE;
6635
6636         /* Update shared memory */
6637         vars->link_status &= ~LINK_UPDATE_MASK;
6638         vars->line_speed = 0;
6639         bnx2x_update_mng(params, vars->link_status);
6640
6641         /* Activate nig drain */
6642         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6643
6644         /* Disable emac */
6645         if (!CHIP_IS_E3(bp))
6646                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6647
6648         usleep_range(10000, 20000);
6649         /* Reset BigMac/Xmac */
6650         if (CHIP_IS_E1x(bp) ||
6651             CHIP_IS_E2(bp))
6652                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6653
6654         if (CHIP_IS_E3(bp)) {
6655                 /* Prevent LPI Generation by chip */
6656                 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6657                        0);
6658                 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6659                        0);
6660                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6661                                       SHMEM_EEE_ACTIVE_BIT);
6662
6663                 bnx2x_update_mng_eee(params, vars->eee_status);
6664                 bnx2x_set_xmac_rxtx(params, 0);
6665                 bnx2x_set_umac_rxtx(params, 0);
6666         }
6667
6668         return 0;
6669 }
6670
6671 static int bnx2x_update_link_up(struct link_params *params,
6672                                 struct link_vars *vars,
6673                                 u8 link_10g)
6674 {
6675         struct bnx2x *bp = params->bp;
6676         u8 phy_idx, port = params->port;
6677         int rc = 0;
6678
6679         vars->link_status |= (LINK_STATUS_LINK_UP |
6680                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6681         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6682
6683         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6684                 vars->link_status |=
6685                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6686
6687         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6688                 vars->link_status |=
6689                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6690         if (USES_WARPCORE(bp)) {
6691                 if (link_10g) {
6692                         if (bnx2x_xmac_enable(params, vars, 0) ==
6693                             -ESRCH) {
6694                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6695                                 vars->link_up = 0;
6696                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6697                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6698                         }
6699                 } else
6700                         bnx2x_umac_enable(params, vars, 0);
6701                 bnx2x_set_led(params, vars,
6702                               LED_MODE_OPER, vars->line_speed);
6703
6704                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6705                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6706                         DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6707                         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6708                                (params->port << 2), 1);
6709                         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6710                         REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6711                                (params->port << 2), 0xfc20);
6712                 }
6713         }
6714         if ((CHIP_IS_E1x(bp) ||
6715              CHIP_IS_E2(bp))) {
6716                 if (link_10g) {
6717                         if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6718                             -ESRCH) {
6719                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6720                                 vars->link_up = 0;
6721                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6722                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6723                         }
6724
6725                         bnx2x_set_led(params, vars,
6726                                       LED_MODE_OPER, SPEED_10000);
6727                 } else {
6728                         rc = bnx2x_emac_program(params, vars);
6729                         bnx2x_emac_enable(params, vars, 0);
6730
6731                         /* AN complete? */
6732                         if ((vars->link_status &
6733                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6734                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6735                             SINGLE_MEDIA_DIRECT(params))
6736                                 bnx2x_set_gmii_tx_driver(params);
6737                 }
6738         }
6739
6740         /* PBF - link up */
6741         if (CHIP_IS_E1x(bp))
6742                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6743                                        vars->line_speed);
6744
6745         /* Disable drain */
6746         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6747
6748         /* Update shared memory */
6749         bnx2x_update_mng(params, vars->link_status);
6750         bnx2x_update_mng_eee(params, vars->eee_status);
6751         /* Check remote fault */
6752         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6753                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6754                         bnx2x_check_half_open_conn(params, vars, 0);
6755                         break;
6756                 }
6757         }
6758         msleep(20);
6759         return rc;
6760 }
6761
6762 static void bnx2x_chng_link_count(struct link_params *params, bool clear)
6763 {
6764         struct bnx2x *bp = params->bp;
6765         u32 addr, val;
6766
6767         /* Verify the link_change_count is supported by the MFW */
6768         if (!(SHMEM2_HAS(bp, link_change_count)))
6769                 return;
6770
6771         addr = params->shmem2_base +
6772                 offsetof(struct shmem2_region, link_change_count[params->port]);
6773         if (clear)
6774                 val = 0;
6775         else
6776                 val = REG_RD(bp, addr) + 1;
6777         REG_WR(bp, addr, val);
6778 }
6779
6780 /* The bnx2x_link_update function should be called upon link
6781  * interrupt.
6782  * Link is considered up as follows:
6783  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6784  *   to be up
6785  * - SINGLE_MEDIA - The link between the 577xx and the external
6786  *   phy (XGXS) need to up as well as the external link of the
6787  *   phy (PHY_EXT1)
6788  * - DUAL_MEDIA - The link between the 577xx and the first
6789  *   external phy needs to be up, and at least one of the 2
6790  *   external phy link must be up.
6791  */
6792 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6793 {
6794         struct bnx2x *bp = params->bp;
6795         struct link_vars phy_vars[MAX_PHYS];
6796         u8 port = params->port;
6797         u8 link_10g_plus, phy_index;
6798         u32 prev_link_status = vars->link_status;
6799         u8 ext_phy_link_up = 0, cur_link_up;
6800         int rc = 0;
6801         u8 is_mi_int = 0;
6802         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6803         u8 active_external_phy = INT_PHY;
6804         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6805         vars->link_status &= ~LINK_UPDATE_MASK;
6806         for (phy_index = INT_PHY; phy_index < params->num_phys;
6807               phy_index++) {
6808                 phy_vars[phy_index].flow_ctrl = 0;
6809                 phy_vars[phy_index].link_status = 0;
6810                 phy_vars[phy_index].line_speed = 0;
6811                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6812                 phy_vars[phy_index].phy_link_up = 0;
6813                 phy_vars[phy_index].link_up = 0;
6814                 phy_vars[phy_index].fault_detected = 0;
6815                 /* different consideration, since vars holds inner state */
6816                 phy_vars[phy_index].eee_status = vars->eee_status;
6817         }
6818
6819         if (USES_WARPCORE(bp))
6820                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6821
6822         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6823                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6824                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6825
6826         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6827                                 port*0x18) > 0);
6828         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6829                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6830                  is_mi_int,
6831                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6832
6833         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6834           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6835           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6836
6837         /* Disable emac */
6838         if (!CHIP_IS_E3(bp))
6839                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6840
6841         /* Step 1:
6842          * Check external link change only for external phys, and apply
6843          * priority selection between them in case the link on both phys
6844          * is up. Note that instead of the common vars, a temporary
6845          * vars argument is used since each phy may have different link/
6846          * speed/duplex result
6847          */
6848         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6849               phy_index++) {
6850                 struct bnx2x_phy *phy = &params->phy[phy_index];
6851                 if (!phy->read_status)
6852                         continue;
6853                 /* Read link status and params of this ext phy */
6854                 cur_link_up = phy->read_status(phy, params,
6855                                                &phy_vars[phy_index]);
6856                 if (cur_link_up) {
6857                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6858                                    phy_index);
6859                 } else {
6860                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6861                                    phy_index);
6862                         continue;
6863                 }
6864
6865                 if (!ext_phy_link_up) {
6866                         ext_phy_link_up = 1;
6867                         active_external_phy = phy_index;
6868                 } else {
6869                         switch (bnx2x_phy_selection(params)) {
6870                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6871                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6872                         /* In this option, the first PHY makes sure to pass the
6873                          * traffic through itself only.
6874                          * Its not clear how to reset the link on the second phy
6875                          */
6876                                 active_external_phy = EXT_PHY1;
6877                                 break;
6878                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6879                         /* In this option, the first PHY makes sure to pass the
6880                          * traffic through the second PHY.
6881                          */
6882                                 active_external_phy = EXT_PHY2;
6883                                 break;
6884                         default:
6885                         /* Link indication on both PHYs with the following cases
6886                          * is invalid:
6887                          * - FIRST_PHY means that second phy wasn't initialized,
6888                          * hence its link is expected to be down
6889                          * - SECOND_PHY means that first phy should not be able
6890                          * to link up by itself (using configuration)
6891                          * - DEFAULT should be overriden during initialiazation
6892                          */
6893                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6894                                            "mpc=0x%x. DISABLING LINK !!!\n",
6895                                            params->multi_phy_config);
6896                                 ext_phy_link_up = 0;
6897                                 break;
6898                         }
6899                 }
6900         }
6901         prev_line_speed = vars->line_speed;
6902         /* Step 2:
6903          * Read the status of the internal phy. In case of
6904          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6905          * otherwise this is the link between the 577xx and the first
6906          * external phy
6907          */
6908         if (params->phy[INT_PHY].read_status)
6909                 params->phy[INT_PHY].read_status(
6910                         &params->phy[INT_PHY],
6911                         params, vars);
6912         /* The INT_PHY flow control reside in the vars. This include the
6913          * case where the speed or flow control are not set to AUTO.
6914          * Otherwise, the active external phy flow control result is set
6915          * to the vars. The ext_phy_line_speed is needed to check if the
6916          * speed is different between the internal phy and external phy.
6917          * This case may be result of intermediate link speed change.
6918          */
6919         if (active_external_phy > INT_PHY) {
6920                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6921                 /* Link speed is taken from the XGXS. AN and FC result from
6922                  * the external phy.
6923                  */
6924                 vars->link_status |= phy_vars[active_external_phy].link_status;
6925
6926                 /* if active_external_phy is first PHY and link is up - disable
6927                  * disable TX on second external PHY
6928                  */
6929                 if (active_external_phy == EXT_PHY1) {
6930                         if (params->phy[EXT_PHY2].phy_specific_func) {
6931                                 DP(NETIF_MSG_LINK,
6932                                    "Disabling TX on EXT_PHY2\n");
6933                                 params->phy[EXT_PHY2].phy_specific_func(
6934                                         &params->phy[EXT_PHY2],
6935                                         params, DISABLE_TX);
6936                         }
6937                 }
6938
6939                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6940                 vars->duplex = phy_vars[active_external_phy].duplex;
6941                 if (params->phy[active_external_phy].supported &
6942                     SUPPORTED_FIBRE)
6943                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6944                 else
6945                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6946
6947                 vars->eee_status = phy_vars[active_external_phy].eee_status;
6948
6949                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6950                            active_external_phy);
6951         }
6952
6953         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6954               phy_index++) {
6955                 if (params->phy[phy_index].flags &
6956                     FLAGS_REARM_LATCH_SIGNAL) {
6957                         bnx2x_rearm_latch_signal(bp, port,
6958                                                  phy_index ==
6959                                                  active_external_phy);
6960                         break;
6961                 }
6962         }
6963         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6964                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6965                    vars->link_status, ext_phy_line_speed);
6966         /* Upon link speed change set the NIG into drain mode. Comes to
6967          * deals with possible FIFO glitch due to clk change when speed
6968          * is decreased without link down indicator
6969          */
6970
6971         if (vars->phy_link_up) {
6972                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6973                     (ext_phy_line_speed != vars->line_speed)) {
6974                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6975                                    " different than the external"
6976                                    " link speed %d\n", vars->line_speed,
6977                                    ext_phy_line_speed);
6978                         vars->phy_link_up = 0;
6979                 } else if (prev_line_speed != vars->line_speed) {
6980                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6981                                0);
6982                         usleep_range(1000, 2000);
6983                 }
6984         }
6985
6986         /* Anything 10 and over uses the bmac */
6987         link_10g_plus = (vars->line_speed >= SPEED_10000);
6988
6989         bnx2x_link_int_ack(params, vars, link_10g_plus);
6990
6991         /* In case external phy link is up, and internal link is down
6992          * (not initialized yet probably after link initialization, it
6993          * needs to be initialized.
6994          * Note that after link down-up as result of cable plug, the xgxs
6995          * link would probably become up again without the need
6996          * initialize it
6997          */
6998         if (!(SINGLE_MEDIA_DIRECT(params))) {
6999                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
7000                            " init_preceding = %d\n", ext_phy_link_up,
7001                            vars->phy_link_up,
7002                            params->phy[EXT_PHY1].flags &
7003                            FLAGS_INIT_XGXS_FIRST);
7004                 if (!(params->phy[EXT_PHY1].flags &
7005                       FLAGS_INIT_XGXS_FIRST)
7006                     && ext_phy_link_up && !vars->phy_link_up) {
7007                         vars->line_speed = ext_phy_line_speed;
7008                         if (vars->line_speed < SPEED_1000)
7009                                 vars->phy_flags |= PHY_SGMII_FLAG;
7010                         else
7011                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
7012
7013                         if (params->phy[INT_PHY].config_init)
7014                                 params->phy[INT_PHY].config_init(
7015                                         &params->phy[INT_PHY], params,
7016                                                 vars);
7017                 }
7018         }
7019         /* Link is up only if both local phy and external phy (in case of
7020          * non-direct board) are up and no fault detected on active PHY.
7021          */
7022         vars->link_up = (vars->phy_link_up &&
7023                          (ext_phy_link_up ||
7024                           SINGLE_MEDIA_DIRECT(params)) &&
7025                          (phy_vars[active_external_phy].fault_detected == 0));
7026
7027         /* Update the PFC configuration in case it was changed */
7028         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
7029                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
7030         else
7031                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7032
7033         if (vars->link_up)
7034                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
7035         else
7036                 rc = bnx2x_update_link_down(params, vars);
7037
7038         if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP)
7039                 bnx2x_chng_link_count(params, false);
7040
7041         /* Update MCP link status was changed */
7042         if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7043                 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7044
7045         return rc;
7046 }
7047
7048 /*****************************************************************************/
7049 /*                          External Phy section                             */
7050 /*****************************************************************************/
7051 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
7052 {
7053         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7054                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7055         usleep_range(1000, 2000);
7056         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7057                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7058 }
7059
7060 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
7061                                       u32 spirom_ver, u32 ver_addr)
7062 {
7063         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
7064                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
7065
7066         if (ver_addr)
7067                 REG_WR(bp, ver_addr, spirom_ver);
7068 }
7069
7070 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7071                                       struct bnx2x_phy *phy,
7072                                       u8 port)
7073 {
7074         u16 fw_ver1, fw_ver2;
7075
7076         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7077                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7078         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7079                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7080         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7081                                   phy->ver_addr);
7082 }
7083
7084 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7085                                        struct bnx2x_phy *phy,
7086                                        struct link_vars *vars)
7087 {
7088         u16 val;
7089         bnx2x_cl45_read(bp, phy,
7090                         MDIO_AN_DEVAD,
7091                         MDIO_AN_REG_STATUS, &val);
7092         bnx2x_cl45_read(bp, phy,
7093                         MDIO_AN_DEVAD,
7094                         MDIO_AN_REG_STATUS, &val);
7095         if (val & (1<<5))
7096                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7097         if ((val & (1<<0)) == 0)
7098                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7099 }
7100
7101 /******************************************************************/
7102 /*              common BCM8073/BCM8727 PHY SECTION                */
7103 /******************************************************************/
7104 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7105                                   struct link_params *params,
7106                                   struct link_vars *vars)
7107 {
7108         struct bnx2x *bp = params->bp;
7109         if (phy->req_line_speed == SPEED_10 ||
7110             phy->req_line_speed == SPEED_100) {
7111                 vars->flow_ctrl = phy->req_flow_ctrl;
7112                 return;
7113         }
7114
7115         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7116             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7117                 u16 pause_result;
7118                 u16 ld_pause;           /* local */
7119                 u16 lp_pause;           /* link partner */
7120                 bnx2x_cl45_read(bp, phy,
7121                                 MDIO_AN_DEVAD,
7122                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7123
7124                 bnx2x_cl45_read(bp, phy,
7125                                 MDIO_AN_DEVAD,
7126                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7127                 pause_result = (ld_pause &
7128                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7129                 pause_result |= (lp_pause &
7130                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7131
7132                 bnx2x_pause_resolve(vars, pause_result);
7133                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7134                            pause_result);
7135         }
7136 }
7137 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7138                                              struct bnx2x_phy *phy,
7139                                              u8 port)
7140 {
7141         u32 count = 0;
7142         u16 fw_ver1, fw_msgout;
7143         int rc = 0;
7144
7145         /* Boot port from external ROM  */
7146         /* EDC grst */
7147         bnx2x_cl45_write(bp, phy,
7148                          MDIO_PMA_DEVAD,
7149                          MDIO_PMA_REG_GEN_CTRL,
7150                          0x0001);
7151
7152         /* Ucode reboot and rst */
7153         bnx2x_cl45_write(bp, phy,
7154                          MDIO_PMA_DEVAD,
7155                          MDIO_PMA_REG_GEN_CTRL,
7156                          0x008c);
7157
7158         bnx2x_cl45_write(bp, phy,
7159                          MDIO_PMA_DEVAD,
7160                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7161
7162         /* Reset internal microprocessor */
7163         bnx2x_cl45_write(bp, phy,
7164                          MDIO_PMA_DEVAD,
7165                          MDIO_PMA_REG_GEN_CTRL,
7166                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7167
7168         /* Release srst bit */
7169         bnx2x_cl45_write(bp, phy,
7170                          MDIO_PMA_DEVAD,
7171                          MDIO_PMA_REG_GEN_CTRL,
7172                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7173
7174         /* Delay 100ms per the PHY specifications */
7175         msleep(100);
7176
7177         /* 8073 sometimes taking longer to download */
7178         do {
7179                 count++;
7180                 if (count > 300) {
7181                         DP(NETIF_MSG_LINK,
7182                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7183                                  "Download failed. fw version = 0x%x\n",
7184                                  port, fw_ver1);
7185                         rc = -EINVAL;
7186                         break;
7187                 }
7188
7189                 bnx2x_cl45_read(bp, phy,
7190                                 MDIO_PMA_DEVAD,
7191                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7192                 bnx2x_cl45_read(bp, phy,
7193                                 MDIO_PMA_DEVAD,
7194                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7195
7196                 usleep_range(1000, 2000);
7197         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7198                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7199                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7200
7201         /* Clear ser_boot_ctl bit */
7202         bnx2x_cl45_write(bp, phy,
7203                          MDIO_PMA_DEVAD,
7204                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7205         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7206
7207         DP(NETIF_MSG_LINK,
7208                  "bnx2x_8073_8727_external_rom_boot port %x:"
7209                  "Download complete. fw version = 0x%x\n",
7210                  port, fw_ver1);
7211
7212         return rc;
7213 }
7214
7215 /******************************************************************/
7216 /*                      BCM8073 PHY SECTION                       */
7217 /******************************************************************/
7218 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7219 {
7220         /* This is only required for 8073A1, version 102 only */
7221         u16 val;
7222
7223         /* Read 8073 HW revision*/
7224         bnx2x_cl45_read(bp, phy,
7225                         MDIO_PMA_DEVAD,
7226                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7227
7228         if (val != 1) {
7229                 /* No need to workaround in 8073 A1 */
7230                 return 0;
7231         }
7232
7233         bnx2x_cl45_read(bp, phy,
7234                         MDIO_PMA_DEVAD,
7235                         MDIO_PMA_REG_ROM_VER2, &val);
7236
7237         /* SNR should be applied only for version 0x102 */
7238         if (val != 0x102)
7239                 return 0;
7240
7241         return 1;
7242 }
7243
7244 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7245 {
7246         u16 val, cnt, cnt1 ;
7247
7248         bnx2x_cl45_read(bp, phy,
7249                         MDIO_PMA_DEVAD,
7250                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7251
7252         if (val > 0) {
7253                 /* No need to workaround in 8073 A1 */
7254                 return 0;
7255         }
7256         /* XAUI workaround in 8073 A0: */
7257
7258         /* After loading the boot ROM and restarting Autoneg, poll
7259          * Dev1, Reg $C820:
7260          */
7261
7262         for (cnt = 0; cnt < 1000; cnt++) {
7263                 bnx2x_cl45_read(bp, phy,
7264                                 MDIO_PMA_DEVAD,
7265                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7266                                 &val);
7267                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7268                    * system initialization (XAUI work-around not required, as
7269                    * these bits indicate 2.5G or 1G link up).
7270                    */
7271                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7272                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7273                         return 0;
7274                 } else if (!(val & (1<<15))) {
7275                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7276                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7277                          * MSB (bit15) goes to 1 (indicating that the XAUI
7278                          * workaround has completed), then continue on with
7279                          * system initialization.
7280                          */
7281                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7282                                 bnx2x_cl45_read(bp, phy,
7283                                         MDIO_PMA_DEVAD,
7284                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7285                                 if (val & (1<<15)) {
7286                                         DP(NETIF_MSG_LINK,
7287                                           "XAUI workaround has completed\n");
7288                                         return 0;
7289                                  }
7290                                  usleep_range(3000, 6000);
7291                         }
7292                         break;
7293                 }
7294                 usleep_range(3000, 6000);
7295         }
7296         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7297         return -EINVAL;
7298 }
7299
7300 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7301 {
7302         /* Force KR or KX */
7303         bnx2x_cl45_write(bp, phy,
7304                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7305         bnx2x_cl45_write(bp, phy,
7306                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7307         bnx2x_cl45_write(bp, phy,
7308                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7309         bnx2x_cl45_write(bp, phy,
7310                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7311 }
7312
7313 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7314                                       struct bnx2x_phy *phy,
7315                                       struct link_vars *vars)
7316 {
7317         u16 cl37_val;
7318         struct bnx2x *bp = params->bp;
7319         bnx2x_cl45_read(bp, phy,
7320                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7321
7322         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7323         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7324         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7325         if ((vars->ieee_fc &
7326             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7327             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7328                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7329         }
7330         if ((vars->ieee_fc &
7331             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7332             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7333                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7334         }
7335         if ((vars->ieee_fc &
7336             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7337             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7338                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7339         }
7340         DP(NETIF_MSG_LINK,
7341                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7342
7343         bnx2x_cl45_write(bp, phy,
7344                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7345         msleep(500);
7346 }
7347
7348 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7349                                      struct link_params *params,
7350                                      u32 action)
7351 {
7352         struct bnx2x *bp = params->bp;
7353         switch (action) {
7354         case PHY_INIT:
7355                 /* Enable LASI */
7356                 bnx2x_cl45_write(bp, phy,
7357                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7358                 bnx2x_cl45_write(bp, phy,
7359                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7360                 break;
7361         }
7362 }
7363
7364 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7365                                   struct link_params *params,
7366                                   struct link_vars *vars)
7367 {
7368         struct bnx2x *bp = params->bp;
7369         u16 val = 0, tmp1;
7370         u8 gpio_port;
7371         DP(NETIF_MSG_LINK, "Init 8073\n");
7372
7373         if (CHIP_IS_E2(bp))
7374                 gpio_port = BP_PATH(bp);
7375         else
7376                 gpio_port = params->port;
7377         /* Restore normal power mode*/
7378         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7379                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7380
7381         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7382                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7383
7384         bnx2x_8073_specific_func(phy, params, PHY_INIT);
7385         bnx2x_8073_set_pause_cl37(params, phy, vars);
7386
7387         bnx2x_cl45_read(bp, phy,
7388                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7389
7390         bnx2x_cl45_read(bp, phy,
7391                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7392
7393         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7394
7395         /* Swap polarity if required - Must be done only in non-1G mode */
7396         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7397                 /* Configure the 8073 to swap _P and _N of the KR lines */
7398                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7399                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7400                 bnx2x_cl45_read(bp, phy,
7401                                 MDIO_PMA_DEVAD,
7402                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7403                 bnx2x_cl45_write(bp, phy,
7404                                  MDIO_PMA_DEVAD,
7405                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7406                                  (val | (3<<9)));
7407         }
7408
7409
7410         /* Enable CL37 BAM */
7411         if (REG_RD(bp, params->shmem_base +
7412                          offsetof(struct shmem_region, dev_info.
7413                                   port_hw_config[params->port].default_cfg)) &
7414             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7415
7416                 bnx2x_cl45_read(bp, phy,
7417                                 MDIO_AN_DEVAD,
7418                                 MDIO_AN_REG_8073_BAM, &val);
7419                 bnx2x_cl45_write(bp, phy,
7420                                  MDIO_AN_DEVAD,
7421                                  MDIO_AN_REG_8073_BAM, val | 1);
7422                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7423         }
7424         if (params->loopback_mode == LOOPBACK_EXT) {
7425                 bnx2x_807x_force_10G(bp, phy);
7426                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7427                 return 0;
7428         } else {
7429                 bnx2x_cl45_write(bp, phy,
7430                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7431         }
7432         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7433                 if (phy->req_line_speed == SPEED_10000) {
7434                         val = (1<<7);
7435                 } else if (phy->req_line_speed ==  SPEED_2500) {
7436                         val = (1<<5);
7437                         /* Note that 2.5G works only when used with 1G
7438                          * advertisement
7439                          */
7440                 } else
7441                         val = (1<<5);
7442         } else {
7443                 val = 0;
7444                 if (phy->speed_cap_mask &
7445                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7446                         val |= (1<<7);
7447
7448                 /* Note that 2.5G works only when used with 1G advertisement */
7449                 if (phy->speed_cap_mask &
7450                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7451                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7452                         val |= (1<<5);
7453                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7454         }
7455
7456         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7457         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7458
7459         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7460              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7461             (phy->req_line_speed == SPEED_2500)) {
7462                 u16 phy_ver;
7463                 /* Allow 2.5G for A1 and above */
7464                 bnx2x_cl45_read(bp, phy,
7465                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7466                                 &phy_ver);
7467                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7468                 if (phy_ver > 0)
7469                         tmp1 |= 1;
7470                 else
7471                         tmp1 &= 0xfffe;
7472         } else {
7473                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7474                 tmp1 &= 0xfffe;
7475         }
7476
7477         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7478         /* Add support for CL37 (passive mode) II */
7479
7480         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7481         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7482                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7483                                   0x20 : 0x40)));
7484
7485         /* Add support for CL37 (passive mode) III */
7486         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7487
7488         /* The SNR will improve about 2db by changing BW and FEE main
7489          * tap. Rest commands are executed after link is up
7490          * Change FFE main cursor to 5 in EDC register
7491          */
7492         if (bnx2x_8073_is_snr_needed(bp, phy))
7493                 bnx2x_cl45_write(bp, phy,
7494                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7495                                  0xFB0C);
7496
7497         /* Enable FEC (Forware Error Correction) Request in the AN */
7498         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7499         tmp1 |= (1<<15);
7500         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7501
7502         bnx2x_ext_phy_set_pause(params, phy, vars);
7503
7504         /* Restart autoneg */
7505         msleep(500);
7506         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7507         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7508                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7509         return 0;
7510 }
7511
7512 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7513                                  struct link_params *params,
7514                                  struct link_vars *vars)
7515 {
7516         struct bnx2x *bp = params->bp;
7517         u8 link_up = 0;
7518         u16 val1, val2;
7519         u16 link_status = 0;
7520         u16 an1000_status = 0;
7521
7522         bnx2x_cl45_read(bp, phy,
7523                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7524
7525         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7526
7527         /* Clear the interrupt LASI status register */
7528         bnx2x_cl45_read(bp, phy,
7529                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7530         bnx2x_cl45_read(bp, phy,
7531                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7532         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7533         /* Clear MSG-OUT */
7534         bnx2x_cl45_read(bp, phy,
7535                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7536
7537         /* Check the LASI */
7538         bnx2x_cl45_read(bp, phy,
7539                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7540
7541         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7542
7543         /* Check the link status */
7544         bnx2x_cl45_read(bp, phy,
7545                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7546         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7547
7548         bnx2x_cl45_read(bp, phy,
7549                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7550         bnx2x_cl45_read(bp, phy,
7551                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7552         link_up = ((val1 & 4) == 4);
7553         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7554
7555         if (link_up &&
7556              ((phy->req_line_speed != SPEED_10000))) {
7557                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7558                         return 0;
7559         }
7560         bnx2x_cl45_read(bp, phy,
7561                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7562         bnx2x_cl45_read(bp, phy,
7563                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7564
7565         /* Check the link status on 1.1.2 */
7566         bnx2x_cl45_read(bp, phy,
7567                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7568         bnx2x_cl45_read(bp, phy,
7569                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7570         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7571                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7572
7573         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7574         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7575                 /* The SNR will improve about 2dbby changing the BW and FEE main
7576                  * tap. The 1st write to change FFE main tap is set before
7577                  * restart AN. Change PLL Bandwidth in EDC register
7578                  */
7579                 bnx2x_cl45_write(bp, phy,
7580                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7581                                  0x26BC);
7582
7583                 /* Change CDR Bandwidth in EDC register */
7584                 bnx2x_cl45_write(bp, phy,
7585                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7586                                  0x0333);
7587         }
7588         bnx2x_cl45_read(bp, phy,
7589                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7590                         &link_status);
7591
7592         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7593         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7594                 link_up = 1;
7595                 vars->line_speed = SPEED_10000;
7596                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7597                            params->port);
7598         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7599                 link_up = 1;
7600                 vars->line_speed = SPEED_2500;
7601                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7602                            params->port);
7603         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7604                 link_up = 1;
7605                 vars->line_speed = SPEED_1000;
7606                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7607                            params->port);
7608         } else {
7609                 link_up = 0;
7610                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7611                            params->port);
7612         }
7613
7614         if (link_up) {
7615                 /* Swap polarity if required */
7616                 if (params->lane_config &
7617                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7618                         /* Configure the 8073 to swap P and N of the KR lines */
7619                         bnx2x_cl45_read(bp, phy,
7620                                         MDIO_XS_DEVAD,
7621                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7622                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7623                          * when it`s in 10G mode.
7624                          */
7625                         if (vars->line_speed == SPEED_1000) {
7626                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7627                                               "the 8073\n");
7628                                 val1 |= (1<<3);
7629                         } else
7630                                 val1 &= ~(1<<3);
7631
7632                         bnx2x_cl45_write(bp, phy,
7633                                          MDIO_XS_DEVAD,
7634                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7635                                          val1);
7636                 }
7637                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7638                 bnx2x_8073_resolve_fc(phy, params, vars);
7639                 vars->duplex = DUPLEX_FULL;
7640         }
7641
7642         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7643                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7644                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7645
7646                 if (val1 & (1<<5))
7647                         vars->link_status |=
7648                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7649                 if (val1 & (1<<7))
7650                         vars->link_status |=
7651                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7652         }
7653
7654         return link_up;
7655 }
7656
7657 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7658                                   struct link_params *params)
7659 {
7660         struct bnx2x *bp = params->bp;
7661         u8 gpio_port;
7662         if (CHIP_IS_E2(bp))
7663                 gpio_port = BP_PATH(bp);
7664         else
7665                 gpio_port = params->port;
7666         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7667            gpio_port);
7668         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7669                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7670                        gpio_port);
7671 }
7672
7673 /******************************************************************/
7674 /*                      BCM8705 PHY SECTION                       */
7675 /******************************************************************/
7676 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7677                                   struct link_params *params,
7678                                   struct link_vars *vars)
7679 {
7680         struct bnx2x *bp = params->bp;
7681         DP(NETIF_MSG_LINK, "init 8705\n");
7682         /* Restore normal power mode*/
7683         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7684                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7685         /* HW reset */
7686         bnx2x_ext_phy_hw_reset(bp, params->port);
7687         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7688         bnx2x_wait_reset_complete(bp, phy, params);
7689
7690         bnx2x_cl45_write(bp, phy,
7691                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7692         bnx2x_cl45_write(bp, phy,
7693                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7694         bnx2x_cl45_write(bp, phy,
7695                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7696         bnx2x_cl45_write(bp, phy,
7697                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7698         /* BCM8705 doesn't have microcode, hence the 0 */
7699         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7700         return 0;
7701 }
7702
7703 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7704                                  struct link_params *params,
7705                                  struct link_vars *vars)
7706 {
7707         u8 link_up = 0;
7708         u16 val1, rx_sd;
7709         struct bnx2x *bp = params->bp;
7710         DP(NETIF_MSG_LINK, "read status 8705\n");
7711         bnx2x_cl45_read(bp, phy,
7712                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7713         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7714
7715         bnx2x_cl45_read(bp, phy,
7716                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7717         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7718
7719         bnx2x_cl45_read(bp, phy,
7720                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7721
7722         bnx2x_cl45_read(bp, phy,
7723                       MDIO_PMA_DEVAD, 0xc809, &val1);
7724         bnx2x_cl45_read(bp, phy,
7725                       MDIO_PMA_DEVAD, 0xc809, &val1);
7726
7727         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7728         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7729         if (link_up) {
7730                 vars->line_speed = SPEED_10000;
7731                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7732         }
7733         return link_up;
7734 }
7735
7736 /******************************************************************/
7737 /*                      SFP+ module Section                       */
7738 /******************************************************************/
7739 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7740                                            struct bnx2x_phy *phy,
7741                                            u8 pmd_dis)
7742 {
7743         struct bnx2x *bp = params->bp;
7744         /* Disable transmitter only for bootcodes which can enable it afterwards
7745          * (for D3 link)
7746          */
7747         if (pmd_dis) {
7748                 if (params->feature_config_flags &
7749                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7750                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7751                 else {
7752                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7753                         return;
7754                 }
7755         } else
7756                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7757         bnx2x_cl45_write(bp, phy,
7758                          MDIO_PMA_DEVAD,
7759                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7760 }
7761
7762 static u8 bnx2x_get_gpio_port(struct link_params *params)
7763 {
7764         u8 gpio_port;
7765         u32 swap_val, swap_override;
7766         struct bnx2x *bp = params->bp;
7767         if (CHIP_IS_E2(bp))
7768                 gpio_port = BP_PATH(bp);
7769         else
7770                 gpio_port = params->port;
7771         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7772         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7773         return gpio_port ^ (swap_val && swap_override);
7774 }
7775
7776 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7777                                            struct bnx2x_phy *phy,
7778                                            u8 tx_en)
7779 {
7780         u16 val;
7781         u8 port = params->port;
7782         struct bnx2x *bp = params->bp;
7783         u32 tx_en_mode;
7784
7785         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7786         tx_en_mode = REG_RD(bp, params->shmem_base +
7787                             offsetof(struct shmem_region,
7788                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7789                 PORT_HW_CFG_TX_LASER_MASK;
7790         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7791                            "mode = %x\n", tx_en, port, tx_en_mode);
7792         switch (tx_en_mode) {
7793         case PORT_HW_CFG_TX_LASER_MDIO:
7794
7795                 bnx2x_cl45_read(bp, phy,
7796                                 MDIO_PMA_DEVAD,
7797                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7798                                 &val);
7799
7800                 if (tx_en)
7801                         val &= ~(1<<15);
7802                 else
7803                         val |= (1<<15);
7804
7805                 bnx2x_cl45_write(bp, phy,
7806                                  MDIO_PMA_DEVAD,
7807                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7808                                  val);
7809         break;
7810         case PORT_HW_CFG_TX_LASER_GPIO0:
7811         case PORT_HW_CFG_TX_LASER_GPIO1:
7812         case PORT_HW_CFG_TX_LASER_GPIO2:
7813         case PORT_HW_CFG_TX_LASER_GPIO3:
7814         {
7815                 u16 gpio_pin;
7816                 u8 gpio_port, gpio_mode;
7817                 if (tx_en)
7818                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7819                 else
7820                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7821
7822                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7823                 gpio_port = bnx2x_get_gpio_port(params);
7824                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7825                 break;
7826         }
7827         default:
7828                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7829                 break;
7830         }
7831 }
7832
7833 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7834                                       struct bnx2x_phy *phy,
7835                                       u8 tx_en)
7836 {
7837         struct bnx2x *bp = params->bp;
7838         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7839         if (CHIP_IS_E3(bp))
7840                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7841         else
7842                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7843 }
7844
7845 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7846                                              struct link_params *params,
7847                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7848                                              u8 *o_buf, u8 is_init)
7849 {
7850         struct bnx2x *bp = params->bp;
7851         u16 val = 0;
7852         u16 i;
7853         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7854                 DP(NETIF_MSG_LINK,
7855                    "Reading from eeprom is limited to 0xf\n");
7856                 return -EINVAL;
7857         }
7858         /* Set the read command byte count */
7859         bnx2x_cl45_write(bp, phy,
7860                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7861                          (byte_cnt | (dev_addr << 8)));
7862
7863         /* Set the read command address */
7864         bnx2x_cl45_write(bp, phy,
7865                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7866                          addr);
7867
7868         /* Activate read command */
7869         bnx2x_cl45_write(bp, phy,
7870                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7871                          0x2c0f);
7872
7873         /* Wait up to 500us for command complete status */
7874         for (i = 0; i < 100; i++) {
7875                 bnx2x_cl45_read(bp, phy,
7876                                 MDIO_PMA_DEVAD,
7877                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7878                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7879                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7880                         break;
7881                 udelay(5);
7882         }
7883
7884         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7885                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7886                 DP(NETIF_MSG_LINK,
7887                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7888                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7889                 return -EINVAL;
7890         }
7891
7892         /* Read the buffer */
7893         for (i = 0; i < byte_cnt; i++) {
7894                 bnx2x_cl45_read(bp, phy,
7895                                 MDIO_PMA_DEVAD,
7896                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7897                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7898         }
7899
7900         for (i = 0; i < 100; i++) {
7901                 bnx2x_cl45_read(bp, phy,
7902                                 MDIO_PMA_DEVAD,
7903                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7904                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7905                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7906                         return 0;
7907                 usleep_range(1000, 2000);
7908         }
7909         return -EINVAL;
7910 }
7911
7912 static void bnx2x_warpcore_power_module(struct link_params *params,
7913                                         u8 power)
7914 {
7915         u32 pin_cfg;
7916         struct bnx2x *bp = params->bp;
7917
7918         pin_cfg = (REG_RD(bp, params->shmem_base +
7919                           offsetof(struct shmem_region,
7920                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7921                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7922                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7923
7924         if (pin_cfg == PIN_CFG_NA)
7925                 return;
7926         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7927                        power, pin_cfg);
7928         /* Low ==> corresponding SFP+ module is powered
7929          * high ==> the SFP+ module is powered down
7930          */
7931         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7932 }
7933 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7934                                                  struct link_params *params,
7935                                                  u8 dev_addr,
7936                                                  u16 addr, u8 byte_cnt,
7937                                                  u8 *o_buf, u8 is_init)
7938 {
7939         int rc = 0;
7940         u8 i, j = 0, cnt = 0;
7941         u32 data_array[4];
7942         u16 addr32;
7943         struct bnx2x *bp = params->bp;
7944
7945         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7946                 DP(NETIF_MSG_LINK,
7947                    "Reading from eeprom is limited to 16 bytes\n");
7948                 return -EINVAL;
7949         }
7950
7951         /* 4 byte aligned address */
7952         addr32 = addr & (~0x3);
7953         do {
7954                 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7955                         bnx2x_warpcore_power_module(params, 0);
7956                         /* Note that 100us are not enough here */
7957                         usleep_range(1000, 2000);
7958                         bnx2x_warpcore_power_module(params, 1);
7959                 }
7960                 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt,
7961                                     data_array);
7962         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7963
7964         if (rc == 0) {
7965                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7966                         o_buf[j] = *((u8 *)data_array + i);
7967                         j++;
7968                 }
7969         }
7970
7971         return rc;
7972 }
7973
7974 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7975                                              struct link_params *params,
7976                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7977                                              u8 *o_buf, u8 is_init)
7978 {
7979         struct bnx2x *bp = params->bp;
7980         u16 val, i;
7981
7982         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7983                 DP(NETIF_MSG_LINK,
7984                    "Reading from eeprom is limited to 0xf\n");
7985                 return -EINVAL;
7986         }
7987
7988         /* Set 2-wire transfer rate of SFP+ module EEPROM
7989          * to 100Khz since some DACs(direct attached cables) do
7990          * not work at 400Khz.
7991          */
7992         bnx2x_cl45_write(bp, phy,
7993                          MDIO_PMA_DEVAD,
7994                          MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7995                          ((dev_addr << 8) | 1));
7996
7997         /* Need to read from 1.8000 to clear it */
7998         bnx2x_cl45_read(bp, phy,
7999                         MDIO_PMA_DEVAD,
8000                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8001                         &val);
8002
8003         /* Set the read command byte count */
8004         bnx2x_cl45_write(bp, phy,
8005                          MDIO_PMA_DEVAD,
8006                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8007                          ((byte_cnt < 2) ? 2 : byte_cnt));
8008
8009         /* Set the read command address */
8010         bnx2x_cl45_write(bp, phy,
8011                          MDIO_PMA_DEVAD,
8012                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8013                          addr);
8014         /* Set the destination address */
8015         bnx2x_cl45_write(bp, phy,
8016                          MDIO_PMA_DEVAD,
8017                          0x8004,
8018                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
8019
8020         /* Activate read command */
8021         bnx2x_cl45_write(bp, phy,
8022                          MDIO_PMA_DEVAD,
8023                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8024                          0x8002);
8025         /* Wait appropriate time for two-wire command to finish before
8026          * polling the status register
8027          */
8028         usleep_range(1000, 2000);
8029
8030         /* Wait up to 500us for command complete status */
8031         for (i = 0; i < 100; i++) {
8032                 bnx2x_cl45_read(bp, phy,
8033                                 MDIO_PMA_DEVAD,
8034                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8035                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8036                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8037                         break;
8038                 udelay(5);
8039         }
8040
8041         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8042                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8043                 DP(NETIF_MSG_LINK,
8044                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8045                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8046                 return -EFAULT;
8047         }
8048
8049         /* Read the buffer */
8050         for (i = 0; i < byte_cnt; i++) {
8051                 bnx2x_cl45_read(bp, phy,
8052                                 MDIO_PMA_DEVAD,
8053                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8054                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8055         }
8056
8057         for (i = 0; i < 100; i++) {
8058                 bnx2x_cl45_read(bp, phy,
8059                                 MDIO_PMA_DEVAD,
8060                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8061                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8062                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8063                         return 0;
8064                 usleep_range(1000, 2000);
8065         }
8066
8067         return -EINVAL;
8068 }
8069 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8070                                  struct link_params *params, u8 dev_addr,
8071                                  u16 addr, u16 byte_cnt, u8 *o_buf)
8072 {
8073         int rc = 0;
8074         struct bnx2x *bp = params->bp;
8075         u8 xfer_size;
8076         u8 *user_data = o_buf;
8077         read_sfp_module_eeprom_func_p read_func;
8078
8079         if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8080                 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8081                 return -EINVAL;
8082         }
8083
8084         switch (phy->type) {
8085         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8086                 read_func = bnx2x_8726_read_sfp_module_eeprom;
8087                 break;
8088         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8089         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8090                 read_func = bnx2x_8727_read_sfp_module_eeprom;
8091                 break;
8092         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8093                 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8094                 break;
8095         default:
8096                 return -EOPNOTSUPP;
8097         }
8098
8099         while (!rc && (byte_cnt > 0)) {
8100                 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8101                         SFP_EEPROM_PAGE_SIZE : byte_cnt;
8102                 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8103                                user_data, 0);
8104                 byte_cnt -= xfer_size;
8105                 user_data += xfer_size;
8106                 addr += xfer_size;
8107         }
8108         return rc;
8109 }
8110
8111 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8112                               struct link_params *params,
8113                               u16 *edc_mode)
8114 {
8115         struct bnx2x *bp = params->bp;
8116         u32 sync_offset = 0, phy_idx, media_types;
8117         u8 val[SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0;
8118         *edc_mode = EDC_MODE_LIMITING;
8119         phy->media_type = ETH_PHY_UNSPECIFIED;
8120         /* First check for copper cable */
8121         if (bnx2x_read_sfp_module_eeprom(phy,
8122                                          params,
8123                                          I2C_DEV_ADDR_A0,
8124                                          0,
8125                                          SFP_EEPROM_FC_TX_TECH_ADDR + 1,
8126                                          (u8 *)val) != 0) {
8127                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8128                 return -EINVAL;
8129         }
8130         params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;
8131         params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] <<
8132                 LINK_SFP_EEPROM_COMP_CODE_SHIFT;
8133         bnx2x_update_link_attr(params, params->link_attr_sync);
8134         switch (val[SFP_EEPROM_CON_TYPE_ADDR]) {
8135         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8136         {
8137                 u8 copper_module_type;
8138                 phy->media_type = ETH_PHY_DA_TWINAX;
8139                 /* Check if its active cable (includes SFP+ module)
8140                  * of passive cable
8141                  */
8142                 copper_module_type = val[SFP_EEPROM_FC_TX_TECH_ADDR];
8143
8144                 if (copper_module_type &
8145                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8146                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8147                         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8148                                 *edc_mode = EDC_MODE_ACTIVE_DAC;
8149                         else
8150                                 check_limiting_mode = 1;
8151                 } else {
8152                         *edc_mode = EDC_MODE_PASSIVE_DAC;
8153                         /* Even in case PASSIVE_DAC indication is not set,
8154                          * treat it as a passive DAC cable, since some cables
8155                          * don't have this indication.
8156                          */
8157                         if (copper_module_type &
8158                             SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8159                                 DP(NETIF_MSG_LINK,
8160                                    "Passive Copper cable detected\n");
8161                         } else {
8162                                 DP(NETIF_MSG_LINK,
8163                                    "Unknown copper-cable-type\n");
8164                         }
8165                 }
8166                 break;
8167         }
8168         case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
8169         case SFP_EEPROM_CON_TYPE_VAL_LC:
8170         case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8171                 check_limiting_mode = 1;
8172                 if (((val[SFP_EEPROM_10G_COMP_CODE_ADDR] &
8173                      (SFP_EEPROM_10G_COMP_CODE_SR_MASK |
8174                       SFP_EEPROM_10G_COMP_CODE_LR_MASK |
8175                        SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) &&
8176                     (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {
8177                         DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8178                         phy->media_type = ETH_PHY_SFP_1G_FIBER;
8179                         if (phy->req_line_speed != SPEED_1000) {
8180                                 u8 gport = params->port;
8181                                 phy->req_line_speed = SPEED_1000;
8182                                 if (!CHIP_IS_E1x(bp)) {
8183                                         gport = BP_PATH(bp) +
8184                                         (params->port << 1);
8185                                 }
8186                                 netdev_err(bp->dev,
8187                                            "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8188                                            gport);
8189                         }
8190                         if (val[SFP_EEPROM_1G_COMP_CODE_ADDR] &
8191                             SFP_EEPROM_1G_COMP_CODE_BASE_T) {
8192                                 bnx2x_sfp_set_transmitter(params, phy, 0);
8193                                 msleep(40);
8194                                 bnx2x_sfp_set_transmitter(params, phy, 1);
8195                         }
8196                 } else {
8197                         int idx, cfg_idx = 0;
8198                         DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8199                         for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8200                                 if (params->phy[idx].type == phy->type) {
8201                                         cfg_idx = LINK_CONFIG_IDX(idx);
8202                                         break;
8203                                 }
8204                         }
8205                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8206                         phy->req_line_speed = params->req_line_speed[cfg_idx];
8207                 }
8208                 break;
8209         default:
8210                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8211                          val[SFP_EEPROM_CON_TYPE_ADDR]);
8212                 return -EINVAL;
8213         }
8214         sync_offset = params->shmem_base +
8215                 offsetof(struct shmem_region,
8216                          dev_info.port_hw_config[params->port].media_type);
8217         media_types = REG_RD(bp, sync_offset);
8218         /* Update media type for non-PMF sync */
8219         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8220                 if (&(params->phy[phy_idx]) == phy) {
8221                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8222                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8223                         media_types |= ((phy->media_type &
8224                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8225                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8226                         break;
8227                 }
8228         }
8229         REG_WR(bp, sync_offset, media_types);
8230         if (check_limiting_mode) {
8231                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8232                 if (bnx2x_read_sfp_module_eeprom(phy,
8233                                                  params,
8234                                                  I2C_DEV_ADDR_A0,
8235                                                  SFP_EEPROM_OPTIONS_ADDR,
8236                                                  SFP_EEPROM_OPTIONS_SIZE,
8237                                                  options) != 0) {
8238                         DP(NETIF_MSG_LINK,
8239                            "Failed to read Option field from module EEPROM\n");
8240                         return -EINVAL;
8241                 }
8242                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8243                         *edc_mode = EDC_MODE_LINEAR;
8244                 else
8245                         *edc_mode = EDC_MODE_LIMITING;
8246         }
8247         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8248         return 0;
8249 }
8250 /* This function read the relevant field from the module (SFP+), and verify it
8251  * is compliant with this board
8252  */
8253 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8254                                    struct link_params *params)
8255 {
8256         struct bnx2x *bp = params->bp;
8257         u32 val, cmd;
8258         u32 fw_resp, fw_cmd_param;
8259         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8260         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8261         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8262         val = REG_RD(bp, params->shmem_base +
8263                          offsetof(struct shmem_region, dev_info.
8264                                   port_feature_config[params->port].config));
8265         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8266             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8267                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8268                 return 0;
8269         }
8270
8271         if (params->feature_config_flags &
8272             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8273                 /* Use specific phy request */
8274                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8275         } else if (params->feature_config_flags &
8276                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8277                 /* Use first phy request only in case of non-dual media*/
8278                 if (DUAL_MEDIA(params)) {
8279                         DP(NETIF_MSG_LINK,
8280                            "FW does not support OPT MDL verification\n");
8281                         return -EINVAL;
8282                 }
8283                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8284         } else {
8285                 /* No support in OPT MDL detection */
8286                 DP(NETIF_MSG_LINK,
8287                    "FW does not support OPT MDL verification\n");
8288                 return -EINVAL;
8289         }
8290
8291         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8292         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8293         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8294                 DP(NETIF_MSG_LINK, "Approved module\n");
8295                 return 0;
8296         }
8297
8298         /* Format the warning message */
8299         if (bnx2x_read_sfp_module_eeprom(phy,
8300                                          params,
8301                                          I2C_DEV_ADDR_A0,
8302                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8303                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8304                                          (u8 *)vendor_name))
8305                 vendor_name[0] = '\0';
8306         else
8307                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8308         if (bnx2x_read_sfp_module_eeprom(phy,
8309                                          params,
8310                                          I2C_DEV_ADDR_A0,
8311                                          SFP_EEPROM_PART_NO_ADDR,
8312                                          SFP_EEPROM_PART_NO_SIZE,
8313                                          (u8 *)vendor_pn))
8314                 vendor_pn[0] = '\0';
8315         else
8316                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8317
8318         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8319                               " Port %d from %s part number %s\n",
8320                          params->port, vendor_name, vendor_pn);
8321         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8322             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8323                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8324         return -EINVAL;
8325 }
8326
8327 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8328                                                  struct link_params *params)
8329
8330 {
8331         u8 val;
8332         int rc;
8333         struct bnx2x *bp = params->bp;
8334         u16 timeout;
8335         /* Initialization time after hot-plug may take up to 300ms for
8336          * some phys type ( e.g. JDSU )
8337          */
8338
8339         for (timeout = 0; timeout < 60; timeout++) {
8340                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8341                         rc = bnx2x_warpcore_read_sfp_module_eeprom(
8342                                 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8343                                 1);
8344                 else
8345                         rc = bnx2x_read_sfp_module_eeprom(phy, params,
8346                                                           I2C_DEV_ADDR_A0,
8347                                                           1, 1, &val);
8348                 if (rc == 0) {
8349                         DP(NETIF_MSG_LINK,
8350                            "SFP+ module initialization took %d ms\n",
8351                            timeout * 5);
8352                         return 0;
8353                 }
8354                 usleep_range(5000, 10000);
8355         }
8356         rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8357                                           1, 1, &val);
8358         return rc;
8359 }
8360
8361 static void bnx2x_8727_power_module(struct bnx2x *bp,
8362                                     struct bnx2x_phy *phy,
8363                                     u8 is_power_up) {
8364         /* Make sure GPIOs are not using for LED mode */
8365         u16 val;
8366         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8367          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8368          * output
8369          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8370          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8371          * where the 1st bit is the over-current(only input), and 2nd bit is
8372          * for power( only output )
8373          *
8374          * In case of NOC feature is disabled and power is up, set GPIO control
8375          *  as input to enable listening of over-current indication
8376          */
8377         if (phy->flags & FLAGS_NOC)
8378                 return;
8379         if (is_power_up)
8380                 val = (1<<4);
8381         else
8382                 /* Set GPIO control to OUTPUT, and set the power bit
8383                  * to according to the is_power_up
8384                  */
8385                 val = (1<<1);
8386
8387         bnx2x_cl45_write(bp, phy,
8388                          MDIO_PMA_DEVAD,
8389                          MDIO_PMA_REG_8727_GPIO_CTRL,
8390                          val);
8391 }
8392
8393 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8394                                         struct bnx2x_phy *phy,
8395                                         u16 edc_mode)
8396 {
8397         u16 cur_limiting_mode;
8398
8399         bnx2x_cl45_read(bp, phy,
8400                         MDIO_PMA_DEVAD,
8401                         MDIO_PMA_REG_ROM_VER2,
8402                         &cur_limiting_mode);
8403         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8404                  cur_limiting_mode);
8405
8406         if (edc_mode == EDC_MODE_LIMITING) {
8407                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8408                 bnx2x_cl45_write(bp, phy,
8409                                  MDIO_PMA_DEVAD,
8410                                  MDIO_PMA_REG_ROM_VER2,
8411                                  EDC_MODE_LIMITING);
8412         } else { /* LRM mode ( default )*/
8413
8414                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8415
8416                 /* Changing to LRM mode takes quite few seconds. So do it only
8417                  * if current mode is limiting (default is LRM)
8418                  */
8419                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8420                         return 0;
8421
8422                 bnx2x_cl45_write(bp, phy,
8423                                  MDIO_PMA_DEVAD,
8424                                  MDIO_PMA_REG_LRM_MODE,
8425                                  0);
8426                 bnx2x_cl45_write(bp, phy,
8427                                  MDIO_PMA_DEVAD,
8428                                  MDIO_PMA_REG_ROM_VER2,
8429                                  0x128);
8430                 bnx2x_cl45_write(bp, phy,
8431                                  MDIO_PMA_DEVAD,
8432                                  MDIO_PMA_REG_MISC_CTRL0,
8433                                  0x4008);
8434                 bnx2x_cl45_write(bp, phy,
8435                                  MDIO_PMA_DEVAD,
8436                                  MDIO_PMA_REG_LRM_MODE,
8437                                  0xaaaa);
8438         }
8439         return 0;
8440 }
8441
8442 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8443                                         struct bnx2x_phy *phy,
8444                                         u16 edc_mode)
8445 {
8446         u16 phy_identifier;
8447         u16 rom_ver2_val;
8448         bnx2x_cl45_read(bp, phy,
8449                         MDIO_PMA_DEVAD,
8450                         MDIO_PMA_REG_PHY_IDENTIFIER,
8451                         &phy_identifier);
8452
8453         bnx2x_cl45_write(bp, phy,
8454                          MDIO_PMA_DEVAD,
8455                          MDIO_PMA_REG_PHY_IDENTIFIER,
8456                          (phy_identifier & ~(1<<9)));
8457
8458         bnx2x_cl45_read(bp, phy,
8459                         MDIO_PMA_DEVAD,
8460                         MDIO_PMA_REG_ROM_VER2,
8461                         &rom_ver2_val);
8462         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8463         bnx2x_cl45_write(bp, phy,
8464                          MDIO_PMA_DEVAD,
8465                          MDIO_PMA_REG_ROM_VER2,
8466                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8467
8468         bnx2x_cl45_write(bp, phy,
8469                          MDIO_PMA_DEVAD,
8470                          MDIO_PMA_REG_PHY_IDENTIFIER,
8471                          (phy_identifier | (1<<9)));
8472
8473         return 0;
8474 }
8475
8476 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8477                                      struct link_params *params,
8478                                      u32 action)
8479 {
8480         struct bnx2x *bp = params->bp;
8481         u16 val;
8482         switch (action) {
8483         case DISABLE_TX:
8484                 bnx2x_sfp_set_transmitter(params, phy, 0);
8485                 break;
8486         case ENABLE_TX:
8487                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8488                         bnx2x_sfp_set_transmitter(params, phy, 1);
8489                 break;
8490         case PHY_INIT:
8491                 bnx2x_cl45_write(bp, phy,
8492                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8493                                  (1<<2) | (1<<5));
8494                 bnx2x_cl45_write(bp, phy,
8495                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8496                                  0);
8497                 bnx2x_cl45_write(bp, phy,
8498                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8499                 /* Make MOD_ABS give interrupt on change */
8500                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8501                                 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8502                                 &val);
8503                 val |= (1<<12);
8504                 if (phy->flags & FLAGS_NOC)
8505                         val |= (3<<5);
8506                 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8507                  * status which reflect SFP+ module over-current
8508                  */
8509                 if (!(phy->flags & FLAGS_NOC))
8510                         val &= 0xff8f; /* Reset bits 4-6 */
8511                 bnx2x_cl45_write(bp, phy,
8512                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8513                                  val);
8514                 break;
8515         default:
8516                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8517                    action);
8518                 return;
8519         }
8520 }
8521
8522 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8523                                            u8 gpio_mode)
8524 {
8525         struct bnx2x *bp = params->bp;
8526
8527         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8528                             offsetof(struct shmem_region,
8529                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8530                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8531         switch (fault_led_gpio) {
8532         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8533                 return;
8534         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8535         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8536         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8537         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8538         {
8539                 u8 gpio_port = bnx2x_get_gpio_port(params);
8540                 u16 gpio_pin = fault_led_gpio -
8541                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8542                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8543                                    "pin %x port %x mode %x\n",
8544                                gpio_pin, gpio_port, gpio_mode);
8545                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8546         }
8547         break;
8548         default:
8549                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8550                                fault_led_gpio);
8551         }
8552 }
8553
8554 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8555                                           u8 gpio_mode)
8556 {
8557         u32 pin_cfg;
8558         u8 port = params->port;
8559         struct bnx2x *bp = params->bp;
8560         pin_cfg = (REG_RD(bp, params->shmem_base +
8561                          offsetof(struct shmem_region,
8562                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8563                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8564                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8565         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8566                        gpio_mode, pin_cfg);
8567         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8568 }
8569
8570 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8571                                            u8 gpio_mode)
8572 {
8573         struct bnx2x *bp = params->bp;
8574         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8575         if (CHIP_IS_E3(bp)) {
8576                 /* Low ==> if SFP+ module is supported otherwise
8577                  * High ==> if SFP+ module is not on the approved vendor list
8578                  */
8579                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8580         } else
8581                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8582 }
8583
8584 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8585                                     struct link_params *params)
8586 {
8587         struct bnx2x *bp = params->bp;
8588         bnx2x_warpcore_power_module(params, 0);
8589         /* Put Warpcore in low power mode */
8590         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8591
8592         /* Put LCPLL in low power mode */
8593         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8594         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8595         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8596 }
8597
8598 static void bnx2x_power_sfp_module(struct link_params *params,
8599                                    struct bnx2x_phy *phy,
8600                                    u8 power)
8601 {
8602         struct bnx2x *bp = params->bp;
8603         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8604
8605         switch (phy->type) {
8606         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8607         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8608                 bnx2x_8727_power_module(params->bp, phy, power);
8609                 break;
8610         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8611                 bnx2x_warpcore_power_module(params, power);
8612                 break;
8613         default:
8614                 break;
8615         }
8616 }
8617 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8618                                              struct bnx2x_phy *phy,
8619                                              u16 edc_mode)
8620 {
8621         u16 val = 0;
8622         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8623         struct bnx2x *bp = params->bp;
8624
8625         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8626         /* This is a global register which controls all lanes */
8627         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8628                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8629         val &= ~(0xf << (lane << 2));
8630
8631         switch (edc_mode) {
8632         case EDC_MODE_LINEAR:
8633         case EDC_MODE_LIMITING:
8634                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8635                 break;
8636         case EDC_MODE_PASSIVE_DAC:
8637         case EDC_MODE_ACTIVE_DAC:
8638                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8639                 break;
8640         default:
8641                 break;
8642         }
8643
8644         val |= (mode << (lane << 2));
8645         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8646                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8647         /* A must read */
8648         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8649                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8650
8651         /* Restart microcode to re-read the new mode */
8652         bnx2x_warpcore_reset_lane(bp, phy, 1);
8653         bnx2x_warpcore_reset_lane(bp, phy, 0);
8654
8655 }
8656
8657 static void bnx2x_set_limiting_mode(struct link_params *params,
8658                                     struct bnx2x_phy *phy,
8659                                     u16 edc_mode)
8660 {
8661         switch (phy->type) {
8662         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8663                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8664                 break;
8665         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8666         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8667                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8668                 break;
8669         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8670                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8671                 break;
8672         }
8673 }
8674
8675 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8676                                       struct link_params *params)
8677 {
8678         struct bnx2x *bp = params->bp;
8679         u16 edc_mode;
8680         int rc = 0;
8681
8682         u32 val = REG_RD(bp, params->shmem_base +
8683                              offsetof(struct shmem_region, dev_info.
8684                                      port_feature_config[params->port].config));
8685         /* Enabled transmitter by default */
8686         bnx2x_sfp_set_transmitter(params, phy, 1);
8687         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8688                  params->port);
8689         /* Power up module */
8690         bnx2x_power_sfp_module(params, phy, 1);
8691         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8692                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8693                 return -EINVAL;
8694         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8695                 /* Check SFP+ module compatibility */
8696                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8697                 rc = -EINVAL;
8698                 /* Turn on fault module-detected led */
8699                 bnx2x_set_sfp_module_fault_led(params,
8700                                                MISC_REGISTERS_GPIO_HIGH);
8701
8702                 /* Check if need to power down the SFP+ module */
8703                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8704                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8705                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8706                         bnx2x_power_sfp_module(params, phy, 0);
8707                         return rc;
8708                 }
8709         } else {
8710                 /* Turn off fault module-detected led */
8711                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8712         }
8713
8714         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8715          * is done automatically
8716          */
8717         bnx2x_set_limiting_mode(params, phy, edc_mode);
8718
8719         /* Disable transmit for this module if the module is not approved, and
8720          * laser needs to be disabled.
8721          */
8722         if ((rc) &&
8723             ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8724              PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8725                 bnx2x_sfp_set_transmitter(params, phy, 0);
8726
8727         return rc;
8728 }
8729
8730 void bnx2x_handle_module_detect_int(struct link_params *params)
8731 {
8732         struct bnx2x *bp = params->bp;
8733         struct bnx2x_phy *phy;
8734         u32 gpio_val;
8735         u8 gpio_num, gpio_port;
8736         if (CHIP_IS_E3(bp)) {
8737                 phy = &params->phy[INT_PHY];
8738                 /* Always enable TX laser,will be disabled in case of fault */
8739                 bnx2x_sfp_set_transmitter(params, phy, 1);
8740         } else {
8741                 phy = &params->phy[EXT_PHY1];
8742         }
8743         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8744                                       params->port, &gpio_num, &gpio_port) ==
8745             -EINVAL) {
8746                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8747                 return;
8748         }
8749
8750         /* Set valid module led off */
8751         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8752
8753         /* Get current gpio val reflecting module plugged in / out*/
8754         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8755
8756         /* Call the handling function in case module is detected */
8757         if (gpio_val == 0) {
8758                 bnx2x_set_mdio_emac_per_phy(bp, params);
8759                 bnx2x_set_aer_mmd(params, phy);
8760
8761                 bnx2x_power_sfp_module(params, phy, 1);
8762                 bnx2x_set_gpio_int(bp, gpio_num,
8763                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8764                                    gpio_port);
8765                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8766                         bnx2x_sfp_module_detection(phy, params);
8767                         if (CHIP_IS_E3(bp)) {
8768                                 u16 rx_tx_in_reset;
8769                                 /* In case WC is out of reset, reconfigure the
8770                                  * link speed while taking into account 1G
8771                                  * module limitation.
8772                                  */
8773                                 bnx2x_cl45_read(bp, phy,
8774                                                 MDIO_WC_DEVAD,
8775                                                 MDIO_WC_REG_DIGITAL5_MISC6,
8776                                                 &rx_tx_in_reset);
8777                                 if ((!rx_tx_in_reset) &&
8778                                     (params->link_flags &
8779                                      PHY_INITIALIZED)) {
8780                                         bnx2x_warpcore_reset_lane(bp, phy, 1);
8781                                         bnx2x_warpcore_config_sfi(phy, params);
8782                                         bnx2x_warpcore_reset_lane(bp, phy, 0);
8783                                 }
8784                         }
8785                 } else {
8786                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8787                 }
8788         } else {
8789                 bnx2x_set_gpio_int(bp, gpio_num,
8790                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8791                                    gpio_port);
8792                 /* Module was plugged out.
8793                  * Disable transmit for this module
8794                  */
8795                 phy->media_type = ETH_PHY_NOT_PRESENT;
8796         }
8797 }
8798
8799 /******************************************************************/
8800 /*              Used by 8706 and 8727                             */
8801 /******************************************************************/
8802 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8803                                  struct bnx2x_phy *phy,
8804                                  u16 alarm_status_offset,
8805                                  u16 alarm_ctrl_offset)
8806 {
8807         u16 alarm_status, val;
8808         bnx2x_cl45_read(bp, phy,
8809                         MDIO_PMA_DEVAD, alarm_status_offset,
8810                         &alarm_status);
8811         bnx2x_cl45_read(bp, phy,
8812                         MDIO_PMA_DEVAD, alarm_status_offset,
8813                         &alarm_status);
8814         /* Mask or enable the fault event. */
8815         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8816         if (alarm_status & (1<<0))
8817                 val &= ~(1<<0);
8818         else
8819                 val |= (1<<0);
8820         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8821 }
8822 /******************************************************************/
8823 /*              common BCM8706/BCM8726 PHY SECTION                */
8824 /******************************************************************/
8825 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8826                                       struct link_params *params,
8827                                       struct link_vars *vars)
8828 {
8829         u8 link_up = 0;
8830         u16 val1, val2, rx_sd, pcs_status;
8831         struct bnx2x *bp = params->bp;
8832         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8833         /* Clear RX Alarm*/
8834         bnx2x_cl45_read(bp, phy,
8835                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8836
8837         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8838                              MDIO_PMA_LASI_TXCTRL);
8839
8840         /* Clear LASI indication*/
8841         bnx2x_cl45_read(bp, phy,
8842                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8843         bnx2x_cl45_read(bp, phy,
8844                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8845         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8846
8847         bnx2x_cl45_read(bp, phy,
8848                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8849         bnx2x_cl45_read(bp, phy,
8850                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8851         bnx2x_cl45_read(bp, phy,
8852                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8853         bnx2x_cl45_read(bp, phy,
8854                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8855
8856         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8857                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8858         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8859          * are set, or if the autoneg bit 1 is set
8860          */
8861         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8862         if (link_up) {
8863                 if (val2 & (1<<1))
8864                         vars->line_speed = SPEED_1000;
8865                 else
8866                         vars->line_speed = SPEED_10000;
8867                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8868                 vars->duplex = DUPLEX_FULL;
8869         }
8870
8871         /* Capture 10G link fault. Read twice to clear stale value. */
8872         if (vars->line_speed == SPEED_10000) {
8873                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8874                             MDIO_PMA_LASI_TXSTAT, &val1);
8875                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8876                             MDIO_PMA_LASI_TXSTAT, &val1);
8877                 if (val1 & (1<<0))
8878                         vars->fault_detected = 1;
8879         }
8880
8881         return link_up;
8882 }
8883
8884 /******************************************************************/
8885 /*                      BCM8706 PHY SECTION                       */
8886 /******************************************************************/
8887 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8888                                  struct link_params *params,
8889                                  struct link_vars *vars)
8890 {
8891         u32 tx_en_mode;
8892         u16 cnt, val, tmp1;
8893         struct bnx2x *bp = params->bp;
8894
8895         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8896                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8897         /* HW reset */
8898         bnx2x_ext_phy_hw_reset(bp, params->port);
8899         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8900         bnx2x_wait_reset_complete(bp, phy, params);
8901
8902         /* Wait until fw is loaded */
8903         for (cnt = 0; cnt < 100; cnt++) {
8904                 bnx2x_cl45_read(bp, phy,
8905                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8906                 if (val)
8907                         break;
8908                 usleep_range(10000, 20000);
8909         }
8910         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8911         if ((params->feature_config_flags &
8912              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8913                 u8 i;
8914                 u16 reg;
8915                 for (i = 0; i < 4; i++) {
8916                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8917                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8918                                    MDIO_XS_8706_REG_BANK_RX0);
8919                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8920                         /* Clear first 3 bits of the control */
8921                         val &= ~0x7;
8922                         /* Set control bits according to configuration */
8923                         val |= (phy->rx_preemphasis[i] & 0x7);
8924                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8925                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8926                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8927                 }
8928         }
8929         /* Force speed */
8930         if (phy->req_line_speed == SPEED_10000) {
8931                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8932
8933                 bnx2x_cl45_write(bp, phy,
8934                                  MDIO_PMA_DEVAD,
8935                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8936                 bnx2x_cl45_write(bp, phy,
8937                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8938                                  0);
8939                 /* Arm LASI for link and Tx fault. */
8940                 bnx2x_cl45_write(bp, phy,
8941                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8942         } else {
8943                 /* Force 1Gbps using autoneg with 1G advertisement */
8944
8945                 /* Allow CL37 through CL73 */
8946                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8947                 bnx2x_cl45_write(bp, phy,
8948                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8949
8950                 /* Enable Full-Duplex advertisement on CL37 */
8951                 bnx2x_cl45_write(bp, phy,
8952                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8953                 /* Enable CL37 AN */
8954                 bnx2x_cl45_write(bp, phy,
8955                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8956                 /* 1G support */
8957                 bnx2x_cl45_write(bp, phy,
8958                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8959
8960                 /* Enable clause 73 AN */
8961                 bnx2x_cl45_write(bp, phy,
8962                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8963                 bnx2x_cl45_write(bp, phy,
8964                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8965                                  0x0400);
8966                 bnx2x_cl45_write(bp, phy,
8967                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8968                                  0x0004);
8969         }
8970         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8971
8972         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8973          * power mode, if TX Laser is disabled
8974          */
8975
8976         tx_en_mode = REG_RD(bp, params->shmem_base +
8977                             offsetof(struct shmem_region,
8978                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8979                         & PORT_HW_CFG_TX_LASER_MASK;
8980
8981         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8982                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8983                 bnx2x_cl45_read(bp, phy,
8984                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8985                 tmp1 |= 0x1;
8986                 bnx2x_cl45_write(bp, phy,
8987                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8988         }
8989
8990         return 0;
8991 }
8992
8993 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8994                                   struct link_params *params,
8995                                   struct link_vars *vars)
8996 {
8997         return bnx2x_8706_8726_read_status(phy, params, vars);
8998 }
8999
9000 /******************************************************************/
9001 /*                      BCM8726 PHY SECTION                       */
9002 /******************************************************************/
9003 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
9004                                        struct link_params *params)
9005 {
9006         struct bnx2x *bp = params->bp;
9007         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
9008         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
9009 }
9010
9011 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
9012                                          struct link_params *params)
9013 {
9014         struct bnx2x *bp = params->bp;
9015         /* Need to wait 100ms after reset */
9016         msleep(100);
9017
9018         /* Micro controller re-boot */
9019         bnx2x_cl45_write(bp, phy,
9020                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
9021
9022         /* Set soft reset */
9023         bnx2x_cl45_write(bp, phy,
9024                          MDIO_PMA_DEVAD,
9025                          MDIO_PMA_REG_GEN_CTRL,
9026                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
9027
9028         bnx2x_cl45_write(bp, phy,
9029                          MDIO_PMA_DEVAD,
9030                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
9031
9032         bnx2x_cl45_write(bp, phy,
9033                          MDIO_PMA_DEVAD,
9034                          MDIO_PMA_REG_GEN_CTRL,
9035                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
9036
9037         /* Wait for 150ms for microcode load */
9038         msleep(150);
9039
9040         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
9041         bnx2x_cl45_write(bp, phy,
9042                          MDIO_PMA_DEVAD,
9043                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
9044
9045         msleep(200);
9046         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
9047 }
9048
9049 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
9050                                  struct link_params *params,
9051                                  struct link_vars *vars)
9052 {
9053         struct bnx2x *bp = params->bp;
9054         u16 val1;
9055         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
9056         if (link_up) {
9057                 bnx2x_cl45_read(bp, phy,
9058                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9059                                 &val1);
9060                 if (val1 & (1<<15)) {
9061                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
9062                         link_up = 0;
9063                         vars->line_speed = 0;
9064                 }
9065         }
9066         return link_up;
9067 }
9068
9069
9070 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
9071                                   struct link_params *params,
9072                                   struct link_vars *vars)
9073 {
9074         struct bnx2x *bp = params->bp;
9075         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
9076
9077         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9078         bnx2x_wait_reset_complete(bp, phy, params);
9079
9080         bnx2x_8726_external_rom_boot(phy, params);
9081
9082         /* Need to call module detected on initialization since the module
9083          * detection triggered by actual module insertion might occur before
9084          * driver is loaded, and when driver is loaded, it reset all
9085          * registers, including the transmitter
9086          */
9087         bnx2x_sfp_module_detection(phy, params);
9088
9089         if (phy->req_line_speed == SPEED_1000) {
9090                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9091                 bnx2x_cl45_write(bp, phy,
9092                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9093                 bnx2x_cl45_write(bp, phy,
9094                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9095                 bnx2x_cl45_write(bp, phy,
9096                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9097                 bnx2x_cl45_write(bp, phy,
9098                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9099                                  0x400);
9100         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9101                    (phy->speed_cap_mask &
9102                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9103                    ((phy->speed_cap_mask &
9104                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9105                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9106                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9107                 /* Set Flow control */
9108                 bnx2x_ext_phy_set_pause(params, phy, vars);
9109                 bnx2x_cl45_write(bp, phy,
9110                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9111                 bnx2x_cl45_write(bp, phy,
9112                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9113                 bnx2x_cl45_write(bp, phy,
9114                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9115                 bnx2x_cl45_write(bp, phy,
9116                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9117                 bnx2x_cl45_write(bp, phy,
9118                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9119                 /* Enable RX-ALARM control to receive interrupt for 1G speed
9120                  * change
9121                  */
9122                 bnx2x_cl45_write(bp, phy,
9123                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9124                 bnx2x_cl45_write(bp, phy,
9125                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9126                                  0x400);
9127
9128         } else { /* Default 10G. Set only LASI control */
9129                 bnx2x_cl45_write(bp, phy,
9130                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9131         }
9132
9133         /* Set TX PreEmphasis if needed */
9134         if ((params->feature_config_flags &
9135              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9136                 DP(NETIF_MSG_LINK,
9137                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9138                          phy->tx_preemphasis[0],
9139                          phy->tx_preemphasis[1]);
9140                 bnx2x_cl45_write(bp, phy,
9141                                  MDIO_PMA_DEVAD,
9142                                  MDIO_PMA_REG_8726_TX_CTRL1,
9143                                  phy->tx_preemphasis[0]);
9144
9145                 bnx2x_cl45_write(bp, phy,
9146                                  MDIO_PMA_DEVAD,
9147                                  MDIO_PMA_REG_8726_TX_CTRL2,
9148                                  phy->tx_preemphasis[1]);
9149         }
9150
9151         return 0;
9152
9153 }
9154
9155 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9156                                   struct link_params *params)
9157 {
9158         struct bnx2x *bp = params->bp;
9159         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9160         /* Set serial boot control for external load */
9161         bnx2x_cl45_write(bp, phy,
9162                          MDIO_PMA_DEVAD,
9163                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
9164 }
9165
9166 /******************************************************************/
9167 /*                      BCM8727 PHY SECTION                       */
9168 /******************************************************************/
9169
9170 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9171                                     struct link_params *params, u8 mode)
9172 {
9173         struct bnx2x *bp = params->bp;
9174         u16 led_mode_bitmask = 0;
9175         u16 gpio_pins_bitmask = 0;
9176         u16 val;
9177         /* Only NOC flavor requires to set the LED specifically */
9178         if (!(phy->flags & FLAGS_NOC))
9179                 return;
9180         switch (mode) {
9181         case LED_MODE_FRONT_PANEL_OFF:
9182         case LED_MODE_OFF:
9183                 led_mode_bitmask = 0;
9184                 gpio_pins_bitmask = 0x03;
9185                 break;
9186         case LED_MODE_ON:
9187                 led_mode_bitmask = 0;
9188                 gpio_pins_bitmask = 0x02;
9189                 break;
9190         case LED_MODE_OPER:
9191                 led_mode_bitmask = 0x60;
9192                 gpio_pins_bitmask = 0x11;
9193                 break;
9194         }
9195         bnx2x_cl45_read(bp, phy,
9196                         MDIO_PMA_DEVAD,
9197                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9198                         &val);
9199         val &= 0xff8f;
9200         val |= led_mode_bitmask;
9201         bnx2x_cl45_write(bp, phy,
9202                          MDIO_PMA_DEVAD,
9203                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9204                          val);
9205         bnx2x_cl45_read(bp, phy,
9206                         MDIO_PMA_DEVAD,
9207                         MDIO_PMA_REG_8727_GPIO_CTRL,
9208                         &val);
9209         val &= 0xffe0;
9210         val |= gpio_pins_bitmask;
9211         bnx2x_cl45_write(bp, phy,
9212                          MDIO_PMA_DEVAD,
9213                          MDIO_PMA_REG_8727_GPIO_CTRL,
9214                          val);
9215 }
9216 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9217                                 struct link_params *params) {
9218         u32 swap_val, swap_override;
9219         u8 port;
9220         /* The PHY reset is controlled by GPIO 1. Fake the port number
9221          * to cancel the swap done in set_gpio()
9222          */
9223         struct bnx2x *bp = params->bp;
9224         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9225         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9226         port = (swap_val && swap_override) ^ 1;
9227         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9228                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9229 }
9230
9231 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9232                                     struct link_params *params)
9233 {
9234         struct bnx2x *bp = params->bp;
9235         u16 tmp1, val;
9236         /* Set option 1G speed */
9237         if ((phy->req_line_speed == SPEED_1000) ||
9238             (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9239                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9240                 bnx2x_cl45_write(bp, phy,
9241                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9242                 bnx2x_cl45_write(bp, phy,
9243                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9244                 bnx2x_cl45_read(bp, phy,
9245                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9246                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9247                 /* Power down the XAUI until link is up in case of dual-media
9248                  * and 1G
9249                  */
9250                 if (DUAL_MEDIA(params)) {
9251                         bnx2x_cl45_read(bp, phy,
9252                                         MDIO_PMA_DEVAD,
9253                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9254                         val |= (3<<10);
9255                         bnx2x_cl45_write(bp, phy,
9256                                          MDIO_PMA_DEVAD,
9257                                          MDIO_PMA_REG_8727_PCS_GP, val);
9258                 }
9259         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9260                    ((phy->speed_cap_mask &
9261                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9262                    ((phy->speed_cap_mask &
9263                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9264                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9265
9266                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9267                 bnx2x_cl45_write(bp, phy,
9268                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9269                 bnx2x_cl45_write(bp, phy,
9270                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9271         } else {
9272                 /* Since the 8727 has only single reset pin, need to set the 10G
9273                  * registers although it is default
9274                  */
9275                 bnx2x_cl45_write(bp, phy,
9276                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9277                                  0x0020);
9278                 bnx2x_cl45_write(bp, phy,
9279                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9280                 bnx2x_cl45_write(bp, phy,
9281                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9282                 bnx2x_cl45_write(bp, phy,
9283                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9284                                  0x0008);
9285         }
9286 }
9287
9288 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9289                                   struct link_params *params,
9290                                   struct link_vars *vars)
9291 {
9292         u32 tx_en_mode;
9293         u16 tmp1, mod_abs, tmp2;
9294         struct bnx2x *bp = params->bp;
9295         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9296
9297         bnx2x_wait_reset_complete(bp, phy, params);
9298
9299         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9300
9301         bnx2x_8727_specific_func(phy, params, PHY_INIT);
9302         /* Initially configure MOD_ABS to interrupt when module is
9303          * presence( bit 8)
9304          */
9305         bnx2x_cl45_read(bp, phy,
9306                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9307         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9308          * When the EDC is off it locks onto a reference clock and avoids
9309          * becoming 'lost'
9310          */
9311         mod_abs &= ~(1<<8);
9312         if (!(phy->flags & FLAGS_NOC))
9313                 mod_abs &= ~(1<<9);
9314         bnx2x_cl45_write(bp, phy,
9315                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9316
9317         /* Enable/Disable PHY transmitter output */
9318         bnx2x_set_disable_pmd_transmit(params, phy, 0);
9319
9320         bnx2x_8727_power_module(bp, phy, 1);
9321
9322         bnx2x_cl45_read(bp, phy,
9323                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9324
9325         bnx2x_cl45_read(bp, phy,
9326                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9327
9328         bnx2x_8727_config_speed(phy, params);
9329
9330
9331         /* Set TX PreEmphasis if needed */
9332         if ((params->feature_config_flags &
9333              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9334                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9335                            phy->tx_preemphasis[0],
9336                            phy->tx_preemphasis[1]);
9337                 bnx2x_cl45_write(bp, phy,
9338                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9339                                  phy->tx_preemphasis[0]);
9340
9341                 bnx2x_cl45_write(bp, phy,
9342                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9343                                  phy->tx_preemphasis[1]);
9344         }
9345
9346         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9347          * power mode, if TX Laser is disabled
9348          */
9349         tx_en_mode = REG_RD(bp, params->shmem_base +
9350                             offsetof(struct shmem_region,
9351                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9352                         & PORT_HW_CFG_TX_LASER_MASK;
9353
9354         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9355
9356                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9357                 bnx2x_cl45_read(bp, phy,
9358                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9359                 tmp2 |= 0x1000;
9360                 tmp2 &= 0xFFEF;
9361                 bnx2x_cl45_write(bp, phy,
9362                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9363                 bnx2x_cl45_read(bp, phy,
9364                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9365                                 &tmp2);
9366                 bnx2x_cl45_write(bp, phy,
9367                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9368                                  (tmp2 & 0x7fff));
9369         }
9370
9371         return 0;
9372 }
9373
9374 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9375                                       struct link_params *params)
9376 {
9377         struct bnx2x *bp = params->bp;
9378         u16 mod_abs, rx_alarm_status;
9379         u32 val = REG_RD(bp, params->shmem_base +
9380                              offsetof(struct shmem_region, dev_info.
9381                                       port_feature_config[params->port].
9382                                       config));
9383         bnx2x_cl45_read(bp, phy,
9384                         MDIO_PMA_DEVAD,
9385                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9386         if (mod_abs & (1<<8)) {
9387
9388                 /* Module is absent */
9389                 DP(NETIF_MSG_LINK,
9390                    "MOD_ABS indication show module is absent\n");
9391                 phy->media_type = ETH_PHY_NOT_PRESENT;
9392                 /* 1. Set mod_abs to detect next module
9393                  *    presence event
9394                  * 2. Set EDC off by setting OPTXLOS signal input to low
9395                  *    (bit 9).
9396                  *    When the EDC is off it locks onto a reference clock and
9397                  *    avoids becoming 'lost'.
9398                  */
9399                 mod_abs &= ~(1<<8);
9400                 if (!(phy->flags & FLAGS_NOC))
9401                         mod_abs &= ~(1<<9);
9402                 bnx2x_cl45_write(bp, phy,
9403                                  MDIO_PMA_DEVAD,
9404                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9405
9406                 /* Clear RX alarm since it stays up as long as
9407                  * the mod_abs wasn't changed
9408                  */
9409                 bnx2x_cl45_read(bp, phy,
9410                                 MDIO_PMA_DEVAD,
9411                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9412
9413         } else {
9414                 /* Module is present */
9415                 DP(NETIF_MSG_LINK,
9416                    "MOD_ABS indication show module is present\n");
9417                 /* First disable transmitter, and if the module is ok, the
9418                  * module_detection will enable it
9419                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9420                  * 2. Restore the default polarity of the OPRXLOS signal and
9421                  * this signal will then correctly indicate the presence or
9422                  * absence of the Rx signal. (bit 9)
9423                  */
9424                 mod_abs |= (1<<8);
9425                 if (!(phy->flags & FLAGS_NOC))
9426                         mod_abs |= (1<<9);
9427                 bnx2x_cl45_write(bp, phy,
9428                                  MDIO_PMA_DEVAD,
9429                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9430
9431                 /* Clear RX alarm since it stays up as long as the mod_abs
9432                  * wasn't changed. This is need to be done before calling the
9433                  * module detection, otherwise it will clear* the link update
9434                  * alarm
9435                  */
9436                 bnx2x_cl45_read(bp, phy,
9437                                 MDIO_PMA_DEVAD,
9438                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9439
9440
9441                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9442                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9443                         bnx2x_sfp_set_transmitter(params, phy, 0);
9444
9445                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9446                         bnx2x_sfp_module_detection(phy, params);
9447                 else
9448                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9449
9450                 /* Reconfigure link speed based on module type limitations */
9451                 bnx2x_8727_config_speed(phy, params);
9452         }
9453
9454         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9455                    rx_alarm_status);
9456         /* No need to check link status in case of module plugged in/out */
9457 }
9458
9459 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9460                                  struct link_params *params,
9461                                  struct link_vars *vars)
9462
9463 {
9464         struct bnx2x *bp = params->bp;
9465         u8 link_up = 0, oc_port = params->port;
9466         u16 link_status = 0;
9467         u16 rx_alarm_status, lasi_ctrl, val1;
9468
9469         /* If PHY is not initialized, do not check link status */
9470         bnx2x_cl45_read(bp, phy,
9471                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9472                         &lasi_ctrl);
9473         if (!lasi_ctrl)
9474                 return 0;
9475
9476         /* Check the LASI on Rx */
9477         bnx2x_cl45_read(bp, phy,
9478                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9479                         &rx_alarm_status);
9480         vars->line_speed = 0;
9481         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9482
9483         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9484                              MDIO_PMA_LASI_TXCTRL);
9485
9486         bnx2x_cl45_read(bp, phy,
9487                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9488
9489         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9490
9491         /* Clear MSG-OUT */
9492         bnx2x_cl45_read(bp, phy,
9493                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9494
9495         /* If a module is present and there is need to check
9496          * for over current
9497          */
9498         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9499                 /* Check over-current using 8727 GPIO0 input*/
9500                 bnx2x_cl45_read(bp, phy,
9501                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9502                                 &val1);
9503
9504                 if ((val1 & (1<<8)) == 0) {
9505                         if (!CHIP_IS_E1x(bp))
9506                                 oc_port = BP_PATH(bp) + (params->port << 1);
9507                         DP(NETIF_MSG_LINK,
9508                            "8727 Power fault has been detected on port %d\n",
9509                            oc_port);
9510                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9511                                             "been detected and the power to "
9512                                             "that SFP+ module has been removed "
9513                                             "to prevent failure of the card. "
9514                                             "Please remove the SFP+ module and "
9515                                             "restart the system to clear this "
9516                                             "error.\n",
9517                          oc_port);
9518                         /* Disable all RX_ALARMs except for mod_abs */
9519                         bnx2x_cl45_write(bp, phy,
9520                                          MDIO_PMA_DEVAD,
9521                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9522
9523                         bnx2x_cl45_read(bp, phy,
9524                                         MDIO_PMA_DEVAD,
9525                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9526                         /* Wait for module_absent_event */
9527                         val1 |= (1<<8);
9528                         bnx2x_cl45_write(bp, phy,
9529                                          MDIO_PMA_DEVAD,
9530                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9531                         /* Clear RX alarm */
9532                         bnx2x_cl45_read(bp, phy,
9533                                 MDIO_PMA_DEVAD,
9534                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9535                         bnx2x_8727_power_module(params->bp, phy, 0);
9536                         return 0;
9537                 }
9538         } /* Over current check */
9539
9540         /* When module absent bit is set, check module */
9541         if (rx_alarm_status & (1<<5)) {
9542                 bnx2x_8727_handle_mod_abs(phy, params);
9543                 /* Enable all mod_abs and link detection bits */
9544                 bnx2x_cl45_write(bp, phy,
9545                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9546                                  ((1<<5) | (1<<2)));
9547         }
9548
9549         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9550                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9551                 bnx2x_sfp_set_transmitter(params, phy, 1);
9552         } else {
9553                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9554                 return 0;
9555         }
9556
9557         bnx2x_cl45_read(bp, phy,
9558                         MDIO_PMA_DEVAD,
9559                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9560
9561         /* Bits 0..2 --> speed detected,
9562          * Bits 13..15--> link is down
9563          */
9564         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9565                 link_up = 1;
9566                 vars->line_speed = SPEED_10000;
9567                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9568                            params->port);
9569         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9570                 link_up = 1;
9571                 vars->line_speed = SPEED_1000;
9572                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9573                            params->port);
9574         } else {
9575                 link_up = 0;
9576                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9577                            params->port);
9578         }
9579
9580         /* Capture 10G link fault. */
9581         if (vars->line_speed == SPEED_10000) {
9582                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9583                             MDIO_PMA_LASI_TXSTAT, &val1);
9584
9585                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9586                             MDIO_PMA_LASI_TXSTAT, &val1);
9587
9588                 if (val1 & (1<<0)) {
9589                         vars->fault_detected = 1;
9590                 }
9591         }
9592
9593         if (link_up) {
9594                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9595                 vars->duplex = DUPLEX_FULL;
9596                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9597         }
9598
9599         if ((DUAL_MEDIA(params)) &&
9600             (phy->req_line_speed == SPEED_1000)) {
9601                 bnx2x_cl45_read(bp, phy,
9602                                 MDIO_PMA_DEVAD,
9603                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9604                 /* In case of dual-media board and 1G, power up the XAUI side,
9605                  * otherwise power it down. For 10G it is done automatically
9606                  */
9607                 if (link_up)
9608                         val1 &= ~(3<<10);
9609                 else
9610                         val1 |= (3<<10);
9611                 bnx2x_cl45_write(bp, phy,
9612                                  MDIO_PMA_DEVAD,
9613                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9614         }
9615         return link_up;
9616 }
9617
9618 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9619                                   struct link_params *params)
9620 {
9621         struct bnx2x *bp = params->bp;
9622
9623         /* Enable/Disable PHY transmitter output */
9624         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9625
9626         /* Disable Transmitter */
9627         bnx2x_sfp_set_transmitter(params, phy, 0);
9628         /* Clear LASI */
9629         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9630
9631 }
9632
9633 /******************************************************************/
9634 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9635 /******************************************************************/
9636 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9637                                             struct bnx2x *bp,
9638                                             u8 port)
9639 {
9640         u16 val, fw_ver2, cnt, i;
9641         static struct bnx2x_reg_set reg_set[] = {
9642                 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9643                 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9644                 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9645                 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9646                 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9647         };
9648         u16 fw_ver1;
9649
9650         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9651             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9652                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9653                 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9654                                 phy->ver_addr);
9655         } else {
9656                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9657                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9658                 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9659                         bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9660                                          reg_set[i].reg, reg_set[i].val);
9661
9662                 for (cnt = 0; cnt < 100; cnt++) {
9663                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9664                         if (val & 1)
9665                                 break;
9666                         udelay(5);
9667                 }
9668                 if (cnt == 100) {
9669                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9670                                         "phy fw version(1)\n");
9671                         bnx2x_save_spirom_version(bp, port, 0,
9672                                                   phy->ver_addr);
9673                         return;
9674                 }
9675
9676
9677                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9678                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9679                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9680                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9681                 for (cnt = 0; cnt < 100; cnt++) {
9682                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9683                         if (val & 1)
9684                                 break;
9685                         udelay(5);
9686                 }
9687                 if (cnt == 100) {
9688                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9689                                         "version(2)\n");
9690                         bnx2x_save_spirom_version(bp, port, 0,
9691                                                   phy->ver_addr);
9692                         return;
9693                 }
9694
9695                 /* lower 16 bits of the register SPI_FW_STATUS */
9696                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9697                 /* upper 16 bits of register SPI_FW_STATUS */
9698                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9699
9700                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9701                                           phy->ver_addr);
9702         }
9703
9704 }
9705 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9706                                 struct bnx2x_phy *phy)
9707 {
9708         u16 val, offset, i;
9709         static struct bnx2x_reg_set reg_set[] = {
9710                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9711                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9712                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9713                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9714                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9715                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9716                 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9717         };
9718         /* PHYC_CTL_LED_CTL */
9719         bnx2x_cl45_read(bp, phy,
9720                         MDIO_PMA_DEVAD,
9721                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9722         val &= 0xFE00;
9723         val |= 0x0092;
9724
9725         bnx2x_cl45_write(bp, phy,
9726                          MDIO_PMA_DEVAD,
9727                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9728
9729         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9730                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9731                                  reg_set[i].val);
9732
9733         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9734             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
9735                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9736         else
9737                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9738
9739         /* stretch_en for LED3*/
9740         bnx2x_cl45_read_or_write(bp, phy,
9741                                  MDIO_PMA_DEVAD, offset,
9742                                  MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9743 }
9744
9745 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9746                                       struct link_params *params,
9747                                       u32 action)
9748 {
9749         struct bnx2x *bp = params->bp;
9750         switch (action) {
9751         case PHY_INIT:
9752                 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9753                     (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9754                         /* Save spirom version */
9755                         bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9756                 }
9757                 /* This phy uses the NIG latch mechanism since link indication
9758                  * arrives through its LED4 and not via its LASI signal, so we
9759                  * get steady signal instead of clear on read
9760                  */
9761                 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9762                               1 << NIG_LATCH_BC_ENABLE_MI_INT);
9763
9764                 bnx2x_848xx_set_led(bp, phy);
9765                 break;
9766         }
9767 }
9768
9769 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9770                                        struct link_params *params,
9771                                        struct link_vars *vars)
9772 {
9773         struct bnx2x *bp = params->bp;
9774         u16 autoneg_val, an_1000_val, an_10_100_val;
9775
9776         bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9777         bnx2x_cl45_write(bp, phy,
9778                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9779
9780         /* set 1000 speed advertisement */
9781         bnx2x_cl45_read(bp, phy,
9782                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9783                         &an_1000_val);
9784
9785         bnx2x_ext_phy_set_pause(params, phy, vars);
9786         bnx2x_cl45_read(bp, phy,
9787                         MDIO_AN_DEVAD,
9788                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9789                         &an_10_100_val);
9790         bnx2x_cl45_read(bp, phy,
9791                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9792                         &autoneg_val);
9793         /* Disable forced speed */
9794         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9795         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9796
9797         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9798              (phy->speed_cap_mask &
9799              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9800             (phy->req_line_speed == SPEED_1000)) {
9801                 an_1000_val |= (1<<8);
9802                 autoneg_val |= (1<<9 | 1<<12);
9803                 if (phy->req_duplex == DUPLEX_FULL)
9804                         an_1000_val |= (1<<9);
9805                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9806         } else
9807                 an_1000_val &= ~((1<<8) | (1<<9));
9808
9809         bnx2x_cl45_write(bp, phy,
9810                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9811                          an_1000_val);
9812
9813         /* Set 10/100 speed advertisement */
9814         if (phy->req_line_speed == SPEED_AUTO_NEG) {
9815                 if (phy->speed_cap_mask &
9816                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9817                         /* Enable autoneg and restart autoneg for legacy speeds
9818                          */
9819                         autoneg_val |= (1<<9 | 1<<12);
9820                         an_10_100_val |= (1<<8);
9821                         DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
9822                 }
9823
9824                 if (phy->speed_cap_mask &
9825                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9826                         /* Enable autoneg and restart autoneg for legacy speeds
9827                          */
9828                         autoneg_val |= (1<<9 | 1<<12);
9829                         an_10_100_val |= (1<<7);
9830                         DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
9831                 }
9832
9833                 if ((phy->speed_cap_mask &
9834                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9835                     (phy->supported & SUPPORTED_10baseT_Full)) {
9836                         an_10_100_val |= (1<<6);
9837                         autoneg_val |= (1<<9 | 1<<12);
9838                         DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
9839                 }
9840
9841                 if ((phy->speed_cap_mask &
9842                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9843                     (phy->supported & SUPPORTED_10baseT_Half)) {
9844                         an_10_100_val |= (1<<5);
9845                         autoneg_val |= (1<<9 | 1<<12);
9846                         DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
9847                 }
9848         }
9849
9850         /* Only 10/100 are allowed to work in FORCE mode */
9851         if ((phy->req_line_speed == SPEED_100) &&
9852             (phy->supported &
9853              (SUPPORTED_100baseT_Half |
9854               SUPPORTED_100baseT_Full))) {
9855                 autoneg_val |= (1<<13);
9856                 /* Enabled AUTO-MDIX when autoneg is disabled */
9857                 bnx2x_cl45_write(bp, phy,
9858                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9859                                  (1<<15 | 1<<9 | 7<<0));
9860                 /* The PHY needs this set even for forced link. */
9861                 an_10_100_val |= (1<<8) | (1<<7);
9862                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9863         }
9864         if ((phy->req_line_speed == SPEED_10) &&
9865             (phy->supported &
9866              (SUPPORTED_10baseT_Half |
9867               SUPPORTED_10baseT_Full))) {
9868                 /* Enabled AUTO-MDIX when autoneg is disabled */
9869                 bnx2x_cl45_write(bp, phy,
9870                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9871                                  (1<<15 | 1<<9 | 7<<0));
9872                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9873         }
9874
9875         bnx2x_cl45_write(bp, phy,
9876                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9877                          an_10_100_val);
9878
9879         if (phy->req_duplex == DUPLEX_FULL)
9880                 autoneg_val |= (1<<8);
9881
9882         /* Always write this if this is not 84833/4.
9883          * For 84833/4, write it only when it's a forced speed.
9884          */
9885         if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9886              (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
9887             ((autoneg_val & (1<<12)) == 0))
9888                 bnx2x_cl45_write(bp, phy,
9889                          MDIO_AN_DEVAD,
9890                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9891
9892         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9893             (phy->speed_cap_mask &
9894              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9895                 (phy->req_line_speed == SPEED_10000)) {
9896                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9897                         /* Restart autoneg for 10G*/
9898
9899                         bnx2x_cl45_read_or_write(
9900                                 bp, phy,
9901                                 MDIO_AN_DEVAD,
9902                                 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9903                                 0x1000);
9904                         bnx2x_cl45_write(bp, phy,
9905                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9906                                          0x3200);
9907         } else
9908                 bnx2x_cl45_write(bp, phy,
9909                                  MDIO_AN_DEVAD,
9910                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9911                                  1);
9912
9913         return 0;
9914 }
9915
9916 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9917                                   struct link_params *params,
9918                                   struct link_vars *vars)
9919 {
9920         struct bnx2x *bp = params->bp;
9921         /* Restore normal power mode*/
9922         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9923                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9924
9925         /* HW reset */
9926         bnx2x_ext_phy_hw_reset(bp, params->port);
9927         bnx2x_wait_reset_complete(bp, phy, params);
9928
9929         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9930         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9931 }
9932
9933 #define PHY84833_CMDHDLR_WAIT 300
9934 #define PHY84833_CMDHDLR_MAX_ARGS 5
9935 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9936                                 struct link_params *params, u16 fw_cmd,
9937                                 u16 cmd_args[], int argc)
9938 {
9939         int idx;
9940         u16 val;
9941         struct bnx2x *bp = params->bp;
9942         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9943         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9944                         MDIO_84833_CMD_HDLR_STATUS,
9945                         PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9946         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9947                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9948                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9949                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9950                         break;
9951                 usleep_range(1000, 2000);
9952         }
9953         if (idx >= PHY84833_CMDHDLR_WAIT) {
9954                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9955                 return -EINVAL;
9956         }
9957
9958         /* Prepare argument(s) and issue command */
9959         for (idx = 0; idx < argc; idx++) {
9960                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9961                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9962                                 cmd_args[idx]);
9963         }
9964         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9965                         MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9966         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9967                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9968                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9969                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9970                         (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9971                         break;
9972                 usleep_range(1000, 2000);
9973         }
9974         if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9975                 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9976                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9977                 return -EINVAL;
9978         }
9979         /* Gather returning data */
9980         for (idx = 0; idx < argc; idx++) {
9981                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9982                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9983                                 &cmd_args[idx]);
9984         }
9985         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9986                         MDIO_84833_CMD_HDLR_STATUS,
9987                         PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9988         return 0;
9989 }
9990
9991 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9992                                    struct link_params *params,
9993                                    struct link_vars *vars)
9994 {
9995         u32 pair_swap;
9996         u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9997         int status;
9998         struct bnx2x *bp = params->bp;
9999
10000         /* Check for configuration. */
10001         pair_swap = REG_RD(bp, params->shmem_base +
10002                            offsetof(struct shmem_region,
10003                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
10004                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
10005
10006         if (pair_swap == 0)
10007                 return 0;
10008
10009         /* Only the second argument is used for this command */
10010         data[1] = (u16)pair_swap;
10011
10012         status = bnx2x_84833_cmd_hdlr(phy, params,
10013                 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
10014         if (status == 0)
10015                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
10016
10017         return status;
10018 }
10019
10020 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
10021                                       u32 shmem_base_path[],
10022                                       u32 chip_id)
10023 {
10024         u32 reset_pin[2];
10025         u32 idx;
10026         u8 reset_gpios;
10027         if (CHIP_IS_E3(bp)) {
10028                 /* Assume that these will be GPIOs, not EPIOs. */
10029                 for (idx = 0; idx < 2; idx++) {
10030                         /* Map config param to register bit. */
10031                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10032                                 offsetof(struct shmem_region,
10033                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
10034                         reset_pin[idx] = (reset_pin[idx] &
10035                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10036                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10037                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
10038                         reset_pin[idx] = (1 << reset_pin[idx]);
10039                 }
10040                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10041         } else {
10042                 /* E2, look from diff place of shmem. */
10043                 for (idx = 0; idx < 2; idx++) {
10044                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10045                                 offsetof(struct shmem_region,
10046                                 dev_info.port_hw_config[0].default_cfg));
10047                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
10048                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
10049                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
10050                         reset_pin[idx] = (1 << reset_pin[idx]);
10051                 }
10052                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10053         }
10054
10055         return reset_gpios;
10056 }
10057
10058 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
10059                                 struct link_params *params)
10060 {
10061         struct bnx2x *bp = params->bp;
10062         u8 reset_gpios;
10063         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
10064                                 offsetof(struct shmem2_region,
10065                                 other_shmem_base_addr));
10066
10067         u32 shmem_base_path[2];
10068
10069         /* Work around for 84833 LED failure inside RESET status */
10070         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10071                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10072                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10073         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10074                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10075                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10076
10077         shmem_base_path[0] = params->shmem_base;
10078         shmem_base_path[1] = other_shmem_base_addr;
10079
10080         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
10081                                                   params->chip_id);
10082
10083         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10084         udelay(10);
10085         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10086                 reset_gpios);
10087
10088         return 0;
10089 }
10090
10091 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10092                                    struct link_params *params,
10093                                    struct link_vars *vars)
10094 {
10095         int rc;
10096         struct bnx2x *bp = params->bp;
10097         u16 cmd_args = 0;
10098
10099         DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10100
10101         /* Prevent Phy from working in EEE and advertising it */
10102         rc = bnx2x_84833_cmd_hdlr(phy, params,
10103                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10104         if (rc) {
10105                 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10106                 return rc;
10107         }
10108
10109         return bnx2x_eee_disable(phy, params, vars);
10110 }
10111
10112 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10113                                    struct link_params *params,
10114                                    struct link_vars *vars)
10115 {
10116         int rc;
10117         struct bnx2x *bp = params->bp;
10118         u16 cmd_args = 1;
10119
10120         rc = bnx2x_84833_cmd_hdlr(phy, params,
10121                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10122         if (rc) {
10123                 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10124                 return rc;
10125         }
10126
10127         return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10128 }
10129
10130 #define PHY84833_CONSTANT_LATENCY 1193
10131 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10132                                    struct link_params *params,
10133                                    struct link_vars *vars)
10134 {
10135         struct bnx2x *bp = params->bp;
10136         u8 port, initialize = 1;
10137         u16 val;
10138         u32 actual_phy_selection;
10139         u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10140         int rc = 0;
10141
10142         usleep_range(1000, 2000);
10143
10144         if (!(CHIP_IS_E1x(bp)))
10145                 port = BP_PATH(bp);
10146         else
10147                 port = params->port;
10148
10149         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10150                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10151                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10152                                port);
10153         } else {
10154                 /* MDIO reset */
10155                 bnx2x_cl45_write(bp, phy,
10156                                 MDIO_PMA_DEVAD,
10157                                 MDIO_PMA_REG_CTRL, 0x8000);
10158         }
10159
10160         bnx2x_wait_reset_complete(bp, phy, params);
10161
10162         /* Wait for GPHY to come out of reset */
10163         msleep(50);
10164         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10165             (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10166                 /* BCM84823 requires that XGXS links up first @ 10G for normal
10167                  * behavior.
10168                  */
10169                 u16 temp;
10170                 temp = vars->line_speed;
10171                 vars->line_speed = SPEED_10000;
10172                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10173                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10174                 vars->line_speed = temp;
10175         }
10176
10177         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10178                         MDIO_CTL_REG_84823_MEDIA, &val);
10179         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10180                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10181                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10182                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10183                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10184
10185         if (CHIP_IS_E3(bp)) {
10186                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10187                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10188         } else {
10189                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10190                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10191         }
10192
10193         actual_phy_selection = bnx2x_phy_selection(params);
10194
10195         switch (actual_phy_selection) {
10196         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10197                 /* Do nothing. Essentially this is like the priority copper */
10198                 break;
10199         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10200                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10201                 break;
10202         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10203                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10204                 break;
10205         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10206                 /* Do nothing here. The first PHY won't be initialized at all */
10207                 break;
10208         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10209                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10210                 initialize = 0;
10211                 break;
10212         }
10213         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10214                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10215
10216         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10217                          MDIO_CTL_REG_84823_MEDIA, val);
10218         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10219                    params->multi_phy_config, val);
10220
10221         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10222             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10223                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10224
10225                 /* Keep AutogrEEEn disabled. */
10226                 cmd_args[0] = 0x0;
10227                 cmd_args[1] = 0x0;
10228                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10229                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10230                 rc = bnx2x_84833_cmd_hdlr(phy, params,
10231                         PHY84833_CMD_SET_EEE_MODE, cmd_args,
10232                         PHY84833_CMDHDLR_MAX_ARGS);
10233                 if (rc)
10234                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10235         }
10236         if (initialize)
10237                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10238         else
10239                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10240         /* 84833 PHY has a better feature and doesn't need to support this. */
10241         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10242                 u32 cms_enable = REG_RD(bp, params->shmem_base +
10243                         offsetof(struct shmem_region,
10244                         dev_info.port_hw_config[params->port].default_cfg)) &
10245                         PORT_HW_CFG_ENABLE_CMS_MASK;
10246
10247                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10248                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10249                 if (cms_enable)
10250                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10251                 else
10252                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10253                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10254                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10255         }
10256
10257         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10258                         MDIO_84833_TOP_CFG_FW_REV, &val);
10259
10260         /* Configure EEE support */
10261         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10262             (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10263             bnx2x_eee_has_cap(params)) {
10264                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10265                 if (rc) {
10266                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10267                         bnx2x_8483x_disable_eee(phy, params, vars);
10268                         return rc;
10269                 }
10270
10271                 if ((phy->req_duplex == DUPLEX_FULL) &&
10272                     (params->eee_mode & EEE_MODE_ADV_LPI) &&
10273                     (bnx2x_eee_calc_timer(params) ||
10274                      !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10275                         rc = bnx2x_8483x_enable_eee(phy, params, vars);
10276                 else
10277                         rc = bnx2x_8483x_disable_eee(phy, params, vars);
10278                 if (rc) {
10279                         DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10280                         return rc;
10281                 }
10282         } else {
10283                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10284         }
10285
10286         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10287             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10288                 /* Bring PHY out of super isolate mode as the final step. */
10289                 bnx2x_cl45_read_and_write(bp, phy,
10290                                           MDIO_CTL_DEVAD,
10291                                           MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10292                                           (u16)~MDIO_84833_SUPER_ISOLATE);
10293         }
10294         return rc;
10295 }
10296
10297 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10298                                   struct link_params *params,
10299                                   struct link_vars *vars)
10300 {
10301         struct bnx2x *bp = params->bp;
10302         u16 val, val1, val2;
10303         u8 link_up = 0;
10304
10305
10306         /* Check 10G-BaseT link status */
10307         /* Check PMD signal ok */
10308         bnx2x_cl45_read(bp, phy,
10309                         MDIO_AN_DEVAD, 0xFFFA, &val1);
10310         bnx2x_cl45_read(bp, phy,
10311                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10312                         &val2);
10313         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10314
10315         /* Check link 10G */
10316         if (val2 & (1<<11)) {
10317                 vars->line_speed = SPEED_10000;
10318                 vars->duplex = DUPLEX_FULL;
10319                 link_up = 1;
10320                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10321         } else { /* Check Legacy speed link */
10322                 u16 legacy_status, legacy_speed;
10323
10324                 /* Enable expansion register 0x42 (Operation mode status) */
10325                 bnx2x_cl45_write(bp, phy,
10326                                  MDIO_AN_DEVAD,
10327                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10328
10329                 /* Get legacy speed operation status */
10330                 bnx2x_cl45_read(bp, phy,
10331                                 MDIO_AN_DEVAD,
10332                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10333                                 &legacy_status);
10334
10335                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10336                    legacy_status);
10337                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10338                 legacy_speed = (legacy_status & (3<<9));
10339                 if (legacy_speed == (0<<9))
10340                         vars->line_speed = SPEED_10;
10341                 else if (legacy_speed == (1<<9))
10342                         vars->line_speed = SPEED_100;
10343                 else if (legacy_speed == (2<<9))
10344                         vars->line_speed = SPEED_1000;
10345                 else { /* Should not happen: Treat as link down */
10346                         vars->line_speed = 0;
10347                         link_up = 0;
10348                 }
10349
10350                 if (link_up) {
10351                         if (legacy_status & (1<<8))
10352                                 vars->duplex = DUPLEX_FULL;
10353                         else
10354                                 vars->duplex = DUPLEX_HALF;
10355
10356                         DP(NETIF_MSG_LINK,
10357                            "Link is up in %dMbps, is_duplex_full= %d\n",
10358                            vars->line_speed,
10359                            (vars->duplex == DUPLEX_FULL));
10360                         /* Check legacy speed AN resolution */
10361                         bnx2x_cl45_read(bp, phy,
10362                                         MDIO_AN_DEVAD,
10363                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10364                                         &val);
10365                         if (val & (1<<5))
10366                                 vars->link_status |=
10367                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10368                         bnx2x_cl45_read(bp, phy,
10369                                         MDIO_AN_DEVAD,
10370                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10371                                         &val);
10372                         if ((val & (1<<0)) == 0)
10373                                 vars->link_status |=
10374                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10375                 }
10376         }
10377         if (link_up) {
10378                 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10379                            vars->line_speed);
10380                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10381
10382                 /* Read LP advertised speeds */
10383                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10384                                 MDIO_AN_REG_CL37_FC_LP, &val);
10385                 if (val & (1<<5))
10386                         vars->link_status |=
10387                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10388                 if (val & (1<<6))
10389                         vars->link_status |=
10390                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10391                 if (val & (1<<7))
10392                         vars->link_status |=
10393                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10394                 if (val & (1<<8))
10395                         vars->link_status |=
10396                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10397                 if (val & (1<<9))
10398                         vars->link_status |=
10399                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10400
10401                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10402                                 MDIO_AN_REG_1000T_STATUS, &val);
10403
10404                 if (val & (1<<10))
10405                         vars->link_status |=
10406                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10407                 if (val & (1<<11))
10408                         vars->link_status |=
10409                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10410
10411                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10412                                 MDIO_AN_REG_MASTER_STATUS, &val);
10413
10414                 if (val & (1<<11))
10415                         vars->link_status |=
10416                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10417
10418                 /* Determine if EEE was negotiated */
10419                 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10420                     (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
10421                         bnx2x_eee_an_resolve(phy, params, vars);
10422         }
10423
10424         return link_up;
10425 }
10426
10427 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10428 {
10429         int status = 0;
10430         u32 spirom_ver;
10431         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10432         status = bnx2x_format_ver(spirom_ver, str, len);
10433         return status;
10434 }
10435
10436 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10437                                 struct link_params *params)
10438 {
10439         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10440                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10441         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10442                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10443 }
10444
10445 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10446                                         struct link_params *params)
10447 {
10448         bnx2x_cl45_write(params->bp, phy,
10449                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10450         bnx2x_cl45_write(params->bp, phy,
10451                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10452 }
10453
10454 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10455                                    struct link_params *params)
10456 {
10457         struct bnx2x *bp = params->bp;
10458         u8 port;
10459         u16 val16;
10460
10461         if (!(CHIP_IS_E1x(bp)))
10462                 port = BP_PATH(bp);
10463         else
10464                 port = params->port;
10465
10466         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10467                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10468                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10469                                port);
10470         } else {
10471                 bnx2x_cl45_read(bp, phy,
10472                                 MDIO_CTL_DEVAD,
10473                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10474                 val16 |= MDIO_84833_SUPER_ISOLATE;
10475                 bnx2x_cl45_write(bp, phy,
10476                                  MDIO_CTL_DEVAD,
10477                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10478         }
10479 }
10480
10481 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10482                                      struct link_params *params, u8 mode)
10483 {
10484         struct bnx2x *bp = params->bp;
10485         u16 val;
10486         u8 port;
10487
10488         if (!(CHIP_IS_E1x(bp)))
10489                 port = BP_PATH(bp);
10490         else
10491                 port = params->port;
10492
10493         switch (mode) {
10494         case LED_MODE_OFF:
10495
10496                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10497
10498                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10499                     SHARED_HW_CFG_LED_EXTPHY1) {
10500
10501                         /* Set LED masks */
10502                         bnx2x_cl45_write(bp, phy,
10503                                         MDIO_PMA_DEVAD,
10504                                         MDIO_PMA_REG_8481_LED1_MASK,
10505                                         0x0);
10506
10507                         bnx2x_cl45_write(bp, phy,
10508                                         MDIO_PMA_DEVAD,
10509                                         MDIO_PMA_REG_8481_LED2_MASK,
10510                                         0x0);
10511
10512                         bnx2x_cl45_write(bp, phy,
10513                                         MDIO_PMA_DEVAD,
10514                                         MDIO_PMA_REG_8481_LED3_MASK,
10515                                         0x0);
10516
10517                         bnx2x_cl45_write(bp, phy,
10518                                         MDIO_PMA_DEVAD,
10519                                         MDIO_PMA_REG_8481_LED5_MASK,
10520                                         0x0);
10521
10522                 } else {
10523                         bnx2x_cl45_write(bp, phy,
10524                                          MDIO_PMA_DEVAD,
10525                                          MDIO_PMA_REG_8481_LED1_MASK,
10526                                          0x0);
10527                 }
10528                 break;
10529         case LED_MODE_FRONT_PANEL_OFF:
10530
10531                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10532                    port);
10533
10534                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10535                     SHARED_HW_CFG_LED_EXTPHY1) {
10536
10537                         /* Set LED masks */
10538                         bnx2x_cl45_write(bp, phy,
10539                                          MDIO_PMA_DEVAD,
10540                                          MDIO_PMA_REG_8481_LED1_MASK,
10541                                          0x0);
10542
10543                         bnx2x_cl45_write(bp, phy,
10544                                          MDIO_PMA_DEVAD,
10545                                          MDIO_PMA_REG_8481_LED2_MASK,
10546                                          0x0);
10547
10548                         bnx2x_cl45_write(bp, phy,
10549                                          MDIO_PMA_DEVAD,
10550                                          MDIO_PMA_REG_8481_LED3_MASK,
10551                                          0x0);
10552
10553                         bnx2x_cl45_write(bp, phy,
10554                                          MDIO_PMA_DEVAD,
10555                                          MDIO_PMA_REG_8481_LED5_MASK,
10556                                          0x20);
10557
10558                 } else {
10559                         bnx2x_cl45_write(bp, phy,
10560                                          MDIO_PMA_DEVAD,
10561                                          MDIO_PMA_REG_8481_LED1_MASK,
10562                                          0x0);
10563                         if (phy->type ==
10564                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10565                                 /* Disable MI_INT interrupt before setting LED4
10566                                  * source to constant off.
10567                                  */
10568                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10569                                            params->port*4) &
10570                                     NIG_MASK_MI_INT) {
10571                                         params->link_flags |=
10572                                         LINK_FLAGS_INT_DISABLED;
10573
10574                                         bnx2x_bits_dis(
10575                                                 bp,
10576                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10577                                                 params->port*4,
10578                                                 NIG_MASK_MI_INT);
10579                                 }
10580                                 bnx2x_cl45_write(bp, phy,
10581                                                  MDIO_PMA_DEVAD,
10582                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10583                                                  0x0);
10584                         }
10585                 }
10586                 break;
10587         case LED_MODE_ON:
10588
10589                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10590
10591                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10592                     SHARED_HW_CFG_LED_EXTPHY1) {
10593                         /* Set control reg */
10594                         bnx2x_cl45_read(bp, phy,
10595                                         MDIO_PMA_DEVAD,
10596                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10597                                         &val);
10598                         val &= 0x8000;
10599                         val |= 0x2492;
10600
10601                         bnx2x_cl45_write(bp, phy,
10602                                          MDIO_PMA_DEVAD,
10603                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10604                                          val);
10605
10606                         /* Set LED masks */
10607                         bnx2x_cl45_write(bp, phy,
10608                                          MDIO_PMA_DEVAD,
10609                                          MDIO_PMA_REG_8481_LED1_MASK,
10610                                          0x0);
10611
10612                         bnx2x_cl45_write(bp, phy,
10613                                          MDIO_PMA_DEVAD,
10614                                          MDIO_PMA_REG_8481_LED2_MASK,
10615                                          0x20);
10616
10617                         bnx2x_cl45_write(bp, phy,
10618                                          MDIO_PMA_DEVAD,
10619                                          MDIO_PMA_REG_8481_LED3_MASK,
10620                                          0x20);
10621
10622                         bnx2x_cl45_write(bp, phy,
10623                                          MDIO_PMA_DEVAD,
10624                                          MDIO_PMA_REG_8481_LED5_MASK,
10625                                          0x0);
10626                 } else {
10627                         bnx2x_cl45_write(bp, phy,
10628                                          MDIO_PMA_DEVAD,
10629                                          MDIO_PMA_REG_8481_LED1_MASK,
10630                                          0x20);
10631                         if (phy->type ==
10632                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10633                                 /* Disable MI_INT interrupt before setting LED4
10634                                  * source to constant on.
10635                                  */
10636                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10637                                            params->port*4) &
10638                                     NIG_MASK_MI_INT) {
10639                                         params->link_flags |=
10640                                         LINK_FLAGS_INT_DISABLED;
10641
10642                                         bnx2x_bits_dis(
10643                                                 bp,
10644                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10645                                                 params->port*4,
10646                                                 NIG_MASK_MI_INT);
10647                                 }
10648                                 bnx2x_cl45_write(bp, phy,
10649                                                  MDIO_PMA_DEVAD,
10650                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10651                                                  0x20);
10652                         }
10653                 }
10654                 break;
10655
10656         case LED_MODE_OPER:
10657
10658                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10659
10660                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10661                     SHARED_HW_CFG_LED_EXTPHY1) {
10662
10663                         /* Set control reg */
10664                         bnx2x_cl45_read(bp, phy,
10665                                         MDIO_PMA_DEVAD,
10666                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10667                                         &val);
10668
10669                         if (!((val &
10670                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10671                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10672                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10673                                 bnx2x_cl45_write(bp, phy,
10674                                                  MDIO_PMA_DEVAD,
10675                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10676                                                  0xa492);
10677                         }
10678
10679                         /* Set LED masks */
10680                         bnx2x_cl45_write(bp, phy,
10681                                          MDIO_PMA_DEVAD,
10682                                          MDIO_PMA_REG_8481_LED1_MASK,
10683                                          0x10);
10684
10685                         bnx2x_cl45_write(bp, phy,
10686                                          MDIO_PMA_DEVAD,
10687                                          MDIO_PMA_REG_8481_LED2_MASK,
10688                                          0x80);
10689
10690                         bnx2x_cl45_write(bp, phy,
10691                                          MDIO_PMA_DEVAD,
10692                                          MDIO_PMA_REG_8481_LED3_MASK,
10693                                          0x98);
10694
10695                         bnx2x_cl45_write(bp, phy,
10696                                          MDIO_PMA_DEVAD,
10697                                          MDIO_PMA_REG_8481_LED5_MASK,
10698                                          0x40);
10699
10700                 } else {
10701                         /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10702                          * sources are all wired through LED1, rather than only
10703                          * 10G in other modes.
10704                          */
10705                         val = ((params->hw_led_mode <<
10706                                 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10707                                SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10708
10709                         bnx2x_cl45_write(bp, phy,
10710                                          MDIO_PMA_DEVAD,
10711                                          MDIO_PMA_REG_8481_LED1_MASK,
10712                                          val);
10713
10714                         /* Tell LED3 to blink on source */
10715                         bnx2x_cl45_read(bp, phy,
10716                                         MDIO_PMA_DEVAD,
10717                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10718                                         &val);
10719                         val &= ~(7<<6);
10720                         val |= (1<<6); /* A83B[8:6]= 1 */
10721                         bnx2x_cl45_write(bp, phy,
10722                                          MDIO_PMA_DEVAD,
10723                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10724                                          val);
10725                         if (phy->type ==
10726                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10727                                 /* Restore LED4 source to external link,
10728                                  * and re-enable interrupts.
10729                                  */
10730                                 bnx2x_cl45_write(bp, phy,
10731                                                  MDIO_PMA_DEVAD,
10732                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10733                                                  0x40);
10734                                 if (params->link_flags &
10735                                     LINK_FLAGS_INT_DISABLED) {
10736                                         bnx2x_link_int_enable(params);
10737                                         params->link_flags &=
10738                                                 ~LINK_FLAGS_INT_DISABLED;
10739                                 }
10740                         }
10741                 }
10742                 break;
10743         }
10744
10745         /* This is a workaround for E3+84833 until autoneg
10746          * restart is fixed in f/w
10747          */
10748         if (CHIP_IS_E3(bp)) {
10749                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10750                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10751         }
10752 }
10753
10754 /******************************************************************/
10755 /*                      54618SE PHY SECTION                       */
10756 /******************************************************************/
10757 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10758                                         struct link_params *params,
10759                                         u32 action)
10760 {
10761         struct bnx2x *bp = params->bp;
10762         u16 temp;
10763         switch (action) {
10764         case PHY_INIT:
10765                 /* Configure LED4: set to INTR (0x6). */
10766                 /* Accessing shadow register 0xe. */
10767                 bnx2x_cl22_write(bp, phy,
10768                                  MDIO_REG_GPHY_SHADOW,
10769                                  MDIO_REG_GPHY_SHADOW_LED_SEL2);
10770                 bnx2x_cl22_read(bp, phy,
10771                                 MDIO_REG_GPHY_SHADOW,
10772                                 &temp);
10773                 temp &= ~(0xf << 4);
10774                 temp |= (0x6 << 4);
10775                 bnx2x_cl22_write(bp, phy,
10776                                  MDIO_REG_GPHY_SHADOW,
10777                                  MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10778                 /* Configure INTR based on link status change. */
10779                 bnx2x_cl22_write(bp, phy,
10780                                  MDIO_REG_INTR_MASK,
10781                                  ~MDIO_REG_INTR_MASK_LINK_STATUS);
10782                 break;
10783         }
10784 }
10785
10786 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10787                                                struct link_params *params,
10788                                                struct link_vars *vars)
10789 {
10790         struct bnx2x *bp = params->bp;
10791         u8 port;
10792         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10793         u32 cfg_pin;
10794
10795         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10796         usleep_range(1000, 2000);
10797
10798         /* This works with E3 only, no need to check the chip
10799          * before determining the port.
10800          */
10801         port = params->port;
10802
10803         cfg_pin = (REG_RD(bp, params->shmem_base +
10804                         offsetof(struct shmem_region,
10805                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10806                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10807                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10808
10809         /* Drive pin high to bring the GPHY out of reset. */
10810         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10811
10812         /* wait for GPHY to reset */
10813         msleep(50);
10814
10815         /* reset phy */
10816         bnx2x_cl22_write(bp, phy,
10817                          MDIO_PMA_REG_CTRL, 0x8000);
10818         bnx2x_wait_reset_complete(bp, phy, params);
10819
10820         /* Wait for GPHY to reset */
10821         msleep(50);
10822
10823
10824         bnx2x_54618se_specific_func(phy, params, PHY_INIT);
10825         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10826         bnx2x_cl22_write(bp, phy,
10827                         MDIO_REG_GPHY_SHADOW,
10828                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10829         bnx2x_cl22_read(bp, phy,
10830                         MDIO_REG_GPHY_SHADOW,
10831                         &temp);
10832         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10833         bnx2x_cl22_write(bp, phy,
10834                         MDIO_REG_GPHY_SHADOW,
10835                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10836
10837         /* Set up fc */
10838         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10839         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10840         fc_val = 0;
10841         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10842                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10843                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10844
10845         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10846                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10847                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10848
10849         /* Read all advertisement */
10850         bnx2x_cl22_read(bp, phy,
10851                         0x09,
10852                         &an_1000_val);
10853
10854         bnx2x_cl22_read(bp, phy,
10855                         0x04,
10856                         &an_10_100_val);
10857
10858         bnx2x_cl22_read(bp, phy,
10859                         MDIO_PMA_REG_CTRL,
10860                         &autoneg_val);
10861
10862         /* Disable forced speed */
10863         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10864         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10865                            (1<<11));
10866
10867         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10868              (phy->speed_cap_mask &
10869               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10870             (phy->req_line_speed == SPEED_1000)) {
10871                 an_1000_val |= (1<<8);
10872                 autoneg_val |= (1<<9 | 1<<12);
10873                 if (phy->req_duplex == DUPLEX_FULL)
10874                         an_1000_val |= (1<<9);
10875                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10876         } else
10877                 an_1000_val &= ~((1<<8) | (1<<9));
10878
10879         bnx2x_cl22_write(bp, phy,
10880                         0x09,
10881                         an_1000_val);
10882         bnx2x_cl22_read(bp, phy,
10883                         0x09,
10884                         &an_1000_val);
10885
10886         /* Advertise 10/100 link speed */
10887         if (phy->req_line_speed == SPEED_AUTO_NEG) {
10888                 if (phy->speed_cap_mask &
10889                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
10890                         an_10_100_val |= (1<<5);
10891                         autoneg_val |= (1<<9 | 1<<12);
10892                         DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
10893                 }
10894                 if (phy->speed_cap_mask &
10895                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
10896                         an_10_100_val |= (1<<6);
10897                         autoneg_val |= (1<<9 | 1<<12);
10898                         DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
10899                 }
10900                 if (phy->speed_cap_mask &
10901                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
10902                         an_10_100_val |= (1<<7);
10903                         autoneg_val |= (1<<9 | 1<<12);
10904                         DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
10905                 }
10906                 if (phy->speed_cap_mask &
10907                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
10908                         an_10_100_val |= (1<<8);
10909                         autoneg_val |= (1<<9 | 1<<12);
10910                         DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
10911                 }
10912         }
10913
10914         /* Only 10/100 are allowed to work in FORCE mode */
10915         if (phy->req_line_speed == SPEED_100) {
10916                 autoneg_val |= (1<<13);
10917                 /* Enabled AUTO-MDIX when autoneg is disabled */
10918                 bnx2x_cl22_write(bp, phy,
10919                                 0x18,
10920                                 (1<<15 | 1<<9 | 7<<0));
10921                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10922         }
10923         if (phy->req_line_speed == SPEED_10) {
10924                 /* Enabled AUTO-MDIX when autoneg is disabled */
10925                 bnx2x_cl22_write(bp, phy,
10926                                 0x18,
10927                                 (1<<15 | 1<<9 | 7<<0));
10928                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10929         }
10930
10931         if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
10932                 int rc;
10933
10934                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
10935                                  MDIO_REG_GPHY_EXP_ACCESS_TOP |
10936                                  MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10937                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10938                 temp &= 0xfffe;
10939                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10940
10941                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10942                 if (rc) {
10943                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10944                         bnx2x_eee_disable(phy, params, vars);
10945                 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
10946                            (phy->req_duplex == DUPLEX_FULL) &&
10947                            (bnx2x_eee_calc_timer(params) ||
10948                             !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
10949                         /* Need to advertise EEE only when requested,
10950                          * and either no LPI assertion was requested,
10951                          * or it was requested and a valid timer was set.
10952                          * Also notice full duplex is required for EEE.
10953                          */
10954                         bnx2x_eee_advertise(phy, params, vars,
10955                                             SHMEM_EEE_1G_ADV);
10956                 } else {
10957                         DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
10958                         bnx2x_eee_disable(phy, params, vars);
10959                 }
10960         } else {
10961                 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10962                                     SHMEM_EEE_SUPPORTED_SHIFT;
10963
10964                 if (phy->flags & FLAGS_EEE) {
10965                         /* Handle legacy auto-grEEEn */
10966                         if (params->feature_config_flags &
10967                             FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10968                                 temp = 6;
10969                                 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10970                         } else {
10971                                 temp = 0;
10972                                 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
10973                         }
10974                         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10975                                          MDIO_AN_REG_EEE_ADV, temp);
10976                 }
10977         }
10978
10979         bnx2x_cl22_write(bp, phy,
10980                         0x04,
10981                         an_10_100_val | fc_val);
10982
10983         if (phy->req_duplex == DUPLEX_FULL)
10984                 autoneg_val |= (1<<8);
10985
10986         bnx2x_cl22_write(bp, phy,
10987                         MDIO_PMA_REG_CTRL, autoneg_val);
10988
10989         return 0;
10990 }
10991
10992
10993 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10994                                        struct link_params *params, u8 mode)
10995 {
10996         struct bnx2x *bp = params->bp;
10997         u16 temp;
10998
10999         bnx2x_cl22_write(bp, phy,
11000                 MDIO_REG_GPHY_SHADOW,
11001                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
11002         bnx2x_cl22_read(bp, phy,
11003                 MDIO_REG_GPHY_SHADOW,
11004                 &temp);
11005         temp &= 0xff00;
11006
11007         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
11008         switch (mode) {
11009         case LED_MODE_FRONT_PANEL_OFF:
11010         case LED_MODE_OFF:
11011                 temp |= 0x00ee;
11012                 break;
11013         case LED_MODE_OPER:
11014                 temp |= 0x0001;
11015                 break;
11016         case LED_MODE_ON:
11017                 temp |= 0x00ff;
11018                 break;
11019         default:
11020                 break;
11021         }
11022         bnx2x_cl22_write(bp, phy,
11023                 MDIO_REG_GPHY_SHADOW,
11024                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11025         return;
11026 }
11027
11028
11029 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
11030                                      struct link_params *params)
11031 {
11032         struct bnx2x *bp = params->bp;
11033         u32 cfg_pin;
11034         u8 port;
11035
11036         /* In case of no EPIO routed to reset the GPHY, put it
11037          * in low power mode.
11038          */
11039         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
11040         /* This works with E3 only, no need to check the chip
11041          * before determining the port.
11042          */
11043         port = params->port;
11044         cfg_pin = (REG_RD(bp, params->shmem_base +
11045                         offsetof(struct shmem_region,
11046                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11047                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11048                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11049
11050         /* Drive pin low to put GPHY in reset. */
11051         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
11052 }
11053
11054 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
11055                                     struct link_params *params,
11056                                     struct link_vars *vars)
11057 {
11058         struct bnx2x *bp = params->bp;
11059         u16 val;
11060         u8 link_up = 0;
11061         u16 legacy_status, legacy_speed;
11062
11063         /* Get speed operation status */
11064         bnx2x_cl22_read(bp, phy,
11065                         MDIO_REG_GPHY_AUX_STATUS,
11066                         &legacy_status);
11067         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
11068
11069         /* Read status to clear the PHY interrupt. */
11070         bnx2x_cl22_read(bp, phy,
11071                         MDIO_REG_INTR_STATUS,
11072                         &val);
11073
11074         link_up = ((legacy_status & (1<<2)) == (1<<2));
11075
11076         if (link_up) {
11077                 legacy_speed = (legacy_status & (7<<8));
11078                 if (legacy_speed == (7<<8)) {
11079                         vars->line_speed = SPEED_1000;
11080                         vars->duplex = DUPLEX_FULL;
11081                 } else if (legacy_speed == (6<<8)) {
11082                         vars->line_speed = SPEED_1000;
11083                         vars->duplex = DUPLEX_HALF;
11084                 } else if (legacy_speed == (5<<8)) {
11085                         vars->line_speed = SPEED_100;
11086                         vars->duplex = DUPLEX_FULL;
11087                 }
11088                 /* Omitting 100Base-T4 for now */
11089                 else if (legacy_speed == (3<<8)) {
11090                         vars->line_speed = SPEED_100;
11091                         vars->duplex = DUPLEX_HALF;
11092                 } else if (legacy_speed == (2<<8)) {
11093                         vars->line_speed = SPEED_10;
11094                         vars->duplex = DUPLEX_FULL;
11095                 } else if (legacy_speed == (1<<8)) {
11096                         vars->line_speed = SPEED_10;
11097                         vars->duplex = DUPLEX_HALF;
11098                 } else /* Should not happen */
11099                         vars->line_speed = 0;
11100
11101                 DP(NETIF_MSG_LINK,
11102                    "Link is up in %dMbps, is_duplex_full= %d\n",
11103                    vars->line_speed,
11104                    (vars->duplex == DUPLEX_FULL));
11105
11106                 /* Check legacy speed AN resolution */
11107                 bnx2x_cl22_read(bp, phy,
11108                                 0x01,
11109                                 &val);
11110                 if (val & (1<<5))
11111                         vars->link_status |=
11112                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11113                 bnx2x_cl22_read(bp, phy,
11114                                 0x06,
11115                                 &val);
11116                 if ((val & (1<<0)) == 0)
11117                         vars->link_status |=
11118                                 LINK_STATUS_PARALLEL_DETECTION_USED;
11119
11120                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11121                            vars->line_speed);
11122
11123                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11124
11125                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11126                         /* Report LP advertised speeds */
11127                         bnx2x_cl22_read(bp, phy, 0x5, &val);
11128
11129                         if (val & (1<<5))
11130                                 vars->link_status |=
11131                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11132                         if (val & (1<<6))
11133                                 vars->link_status |=
11134                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11135                         if (val & (1<<7))
11136                                 vars->link_status |=
11137                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11138                         if (val & (1<<8))
11139                                 vars->link_status |=
11140                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11141                         if (val & (1<<9))
11142                                 vars->link_status |=
11143                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11144
11145                         bnx2x_cl22_read(bp, phy, 0xa, &val);
11146                         if (val & (1<<10))
11147                                 vars->link_status |=
11148                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11149                         if (val & (1<<11))
11150                                 vars->link_status |=
11151                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11152
11153                         if ((phy->flags & FLAGS_EEE) &&
11154                             bnx2x_eee_has_cap(params))
11155                                 bnx2x_eee_an_resolve(phy, params, vars);
11156                 }
11157         }
11158         return link_up;
11159 }
11160
11161 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11162                                           struct link_params *params)
11163 {
11164         struct bnx2x *bp = params->bp;
11165         u16 val;
11166         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11167
11168         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11169
11170         /* Enable master/slave manual mmode and set to master */
11171         /* mii write 9 [bits set 11 12] */
11172         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11173
11174         /* forced 1G and disable autoneg */
11175         /* set val [mii read 0] */
11176         /* set val [expr $val & [bits clear 6 12 13]] */
11177         /* set val [expr $val | [bits set 6 8]] */
11178         /* mii write 0 $val */
11179         bnx2x_cl22_read(bp, phy, 0x00, &val);
11180         val &= ~((1<<6) | (1<<12) | (1<<13));
11181         val |= (1<<6) | (1<<8);
11182         bnx2x_cl22_write(bp, phy, 0x00, val);
11183
11184         /* Set external loopback and Tx using 6dB coding */
11185         /* mii write 0x18 7 */
11186         /* set val [mii read 0x18] */
11187         /* mii write 0x18 [expr $val | [bits set 10 15]] */
11188         bnx2x_cl22_write(bp, phy, 0x18, 7);
11189         bnx2x_cl22_read(bp, phy, 0x18, &val);
11190         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11191
11192         /* This register opens the gate for the UMAC despite its name */
11193         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11194
11195         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11196          * length used by the MAC receive logic to check frames.
11197          */
11198         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11199 }
11200
11201 /******************************************************************/
11202 /*                      SFX7101 PHY SECTION                       */
11203 /******************************************************************/
11204 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11205                                        struct link_params *params)
11206 {
11207         struct bnx2x *bp = params->bp;
11208         /* SFX7101_XGXS_TEST1 */
11209         bnx2x_cl45_write(bp, phy,
11210                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11211 }
11212
11213 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11214                                   struct link_params *params,
11215                                   struct link_vars *vars)
11216 {
11217         u16 fw_ver1, fw_ver2, val;
11218         struct bnx2x *bp = params->bp;
11219         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11220
11221         /* Restore normal power mode*/
11222         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11223                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11224         /* HW reset */
11225         bnx2x_ext_phy_hw_reset(bp, params->port);
11226         bnx2x_wait_reset_complete(bp, phy, params);
11227
11228         bnx2x_cl45_write(bp, phy,
11229                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11230         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11231         bnx2x_cl45_write(bp, phy,
11232                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11233
11234         bnx2x_ext_phy_set_pause(params, phy, vars);
11235         /* Restart autoneg */
11236         bnx2x_cl45_read(bp, phy,
11237                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11238         val |= 0x200;
11239         bnx2x_cl45_write(bp, phy,
11240                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11241
11242         /* Save spirom version */
11243         bnx2x_cl45_read(bp, phy,
11244                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11245
11246         bnx2x_cl45_read(bp, phy,
11247                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11248         bnx2x_save_spirom_version(bp, params->port,
11249                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11250         return 0;
11251 }
11252
11253 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11254                                  struct link_params *params,
11255                                  struct link_vars *vars)
11256 {
11257         struct bnx2x *bp = params->bp;
11258         u8 link_up;
11259         u16 val1, val2;
11260         bnx2x_cl45_read(bp, phy,
11261                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11262         bnx2x_cl45_read(bp, phy,
11263                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11264         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11265                    val2, val1);
11266         bnx2x_cl45_read(bp, phy,
11267                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11268         bnx2x_cl45_read(bp, phy,
11269                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11270         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11271                    val2, val1);
11272         link_up = ((val1 & 4) == 4);
11273         /* If link is up print the AN outcome of the SFX7101 PHY */
11274         if (link_up) {
11275                 bnx2x_cl45_read(bp, phy,
11276                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11277                                 &val2);
11278                 vars->line_speed = SPEED_10000;
11279                 vars->duplex = DUPLEX_FULL;
11280                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11281                            val2, (val2 & (1<<14)));
11282                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11283                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11284
11285                 /* Read LP advertised speeds */
11286                 if (val2 & (1<<11))
11287                         vars->link_status |=
11288                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11289         }
11290         return link_up;
11291 }
11292
11293 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11294 {
11295         if (*len < 5)
11296                 return -EINVAL;
11297         str[0] = (spirom_ver & 0xFF);
11298         str[1] = (spirom_ver & 0xFF00) >> 8;
11299         str[2] = (spirom_ver & 0xFF0000) >> 16;
11300         str[3] = (spirom_ver & 0xFF000000) >> 24;
11301         str[4] = '\0';
11302         *len -= 5;
11303         return 0;
11304 }
11305
11306 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11307 {
11308         u16 val, cnt;
11309
11310         bnx2x_cl45_read(bp, phy,
11311                         MDIO_PMA_DEVAD,
11312                         MDIO_PMA_REG_7101_RESET, &val);
11313
11314         for (cnt = 0; cnt < 10; cnt++) {
11315                 msleep(50);
11316                 /* Writes a self-clearing reset */
11317                 bnx2x_cl45_write(bp, phy,
11318                                  MDIO_PMA_DEVAD,
11319                                  MDIO_PMA_REG_7101_RESET,
11320                                  (val | (1<<15)));
11321                 /* Wait for clear */
11322                 bnx2x_cl45_read(bp, phy,
11323                                 MDIO_PMA_DEVAD,
11324                                 MDIO_PMA_REG_7101_RESET, &val);
11325
11326                 if ((val & (1<<15)) == 0)
11327                         break;
11328         }
11329 }
11330
11331 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11332                                 struct link_params *params) {
11333         /* Low power mode is controlled by GPIO 2 */
11334         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11335                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11336         /* The PHY reset is controlled by GPIO 1 */
11337         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11338                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11339 }
11340
11341 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11342                                     struct link_params *params, u8 mode)
11343 {
11344         u16 val = 0;
11345         struct bnx2x *bp = params->bp;
11346         switch (mode) {
11347         case LED_MODE_FRONT_PANEL_OFF:
11348         case LED_MODE_OFF:
11349                 val = 2;
11350                 break;
11351         case LED_MODE_ON:
11352                 val = 1;
11353                 break;
11354         case LED_MODE_OPER:
11355                 val = 0;
11356                 break;
11357         }
11358         bnx2x_cl45_write(bp, phy,
11359                          MDIO_PMA_DEVAD,
11360                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
11361                          val);
11362 }
11363
11364 /******************************************************************/
11365 /*                      STATIC PHY DECLARATION                    */
11366 /******************************************************************/
11367
11368 static const struct bnx2x_phy phy_null = {
11369         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11370         .addr           = 0,
11371         .def_md_devad   = 0,
11372         .flags          = FLAGS_INIT_XGXS_FIRST,
11373         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11374         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11375         .mdio_ctrl      = 0,
11376         .supported      = 0,
11377         .media_type     = ETH_PHY_NOT_PRESENT,
11378         .ver_addr       = 0,
11379         .req_flow_ctrl  = 0,
11380         .req_line_speed = 0,
11381         .speed_cap_mask = 0,
11382         .req_duplex     = 0,
11383         .rsrv           = 0,
11384         .config_init    = (config_init_t)NULL,
11385         .read_status    = (read_status_t)NULL,
11386         .link_reset     = (link_reset_t)NULL,
11387         .config_loopback = (config_loopback_t)NULL,
11388         .format_fw_ver  = (format_fw_ver_t)NULL,
11389         .hw_reset       = (hw_reset_t)NULL,
11390         .set_link_led   = (set_link_led_t)NULL,
11391         .phy_specific_func = (phy_specific_func_t)NULL
11392 };
11393
11394 static const struct bnx2x_phy phy_serdes = {
11395         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11396         .addr           = 0xff,
11397         .def_md_devad   = 0,
11398         .flags          = 0,
11399         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11400         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11401         .mdio_ctrl      = 0,
11402         .supported      = (SUPPORTED_10baseT_Half |
11403                            SUPPORTED_10baseT_Full |
11404                            SUPPORTED_100baseT_Half |
11405                            SUPPORTED_100baseT_Full |
11406                            SUPPORTED_1000baseT_Full |
11407                            SUPPORTED_2500baseX_Full |
11408                            SUPPORTED_TP |
11409                            SUPPORTED_Autoneg |
11410                            SUPPORTED_Pause |
11411                            SUPPORTED_Asym_Pause),
11412         .media_type     = ETH_PHY_BASE_T,
11413         .ver_addr       = 0,
11414         .req_flow_ctrl  = 0,
11415         .req_line_speed = 0,
11416         .speed_cap_mask = 0,
11417         .req_duplex     = 0,
11418         .rsrv           = 0,
11419         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11420         .read_status    = (read_status_t)bnx2x_link_settings_status,
11421         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11422         .config_loopback = (config_loopback_t)NULL,
11423         .format_fw_ver  = (format_fw_ver_t)NULL,
11424         .hw_reset       = (hw_reset_t)NULL,
11425         .set_link_led   = (set_link_led_t)NULL,
11426         .phy_specific_func = (phy_specific_func_t)NULL
11427 };
11428
11429 static const struct bnx2x_phy phy_xgxs = {
11430         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11431         .addr           = 0xff,
11432         .def_md_devad   = 0,
11433         .flags          = 0,
11434         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11435         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11436         .mdio_ctrl      = 0,
11437         .supported      = (SUPPORTED_10baseT_Half |
11438                            SUPPORTED_10baseT_Full |
11439                            SUPPORTED_100baseT_Half |
11440                            SUPPORTED_100baseT_Full |
11441                            SUPPORTED_1000baseT_Full |
11442                            SUPPORTED_2500baseX_Full |
11443                            SUPPORTED_10000baseT_Full |
11444                            SUPPORTED_FIBRE |
11445                            SUPPORTED_Autoneg |
11446                            SUPPORTED_Pause |
11447                            SUPPORTED_Asym_Pause),
11448         .media_type     = ETH_PHY_CX4,
11449         .ver_addr       = 0,
11450         .req_flow_ctrl  = 0,
11451         .req_line_speed = 0,
11452         .speed_cap_mask = 0,
11453         .req_duplex     = 0,
11454         .rsrv           = 0,
11455         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11456         .read_status    = (read_status_t)bnx2x_link_settings_status,
11457         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11458         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11459         .format_fw_ver  = (format_fw_ver_t)NULL,
11460         .hw_reset       = (hw_reset_t)NULL,
11461         .set_link_led   = (set_link_led_t)NULL,
11462         .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11463 };
11464 static const struct bnx2x_phy phy_warpcore = {
11465         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11466         .addr           = 0xff,
11467         .def_md_devad   = 0,
11468         .flags          = FLAGS_TX_ERROR_CHECK,
11469         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11470         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11471         .mdio_ctrl      = 0,
11472         .supported      = (SUPPORTED_10baseT_Half |
11473                            SUPPORTED_10baseT_Full |
11474                            SUPPORTED_100baseT_Half |
11475                            SUPPORTED_100baseT_Full |
11476                            SUPPORTED_1000baseT_Full |
11477                            SUPPORTED_10000baseT_Full |
11478                            SUPPORTED_20000baseKR2_Full |
11479                            SUPPORTED_20000baseMLD2_Full |
11480                            SUPPORTED_FIBRE |
11481                            SUPPORTED_Autoneg |
11482                            SUPPORTED_Pause |
11483                            SUPPORTED_Asym_Pause),
11484         .media_type     = ETH_PHY_UNSPECIFIED,
11485         .ver_addr       = 0,
11486         .req_flow_ctrl  = 0,
11487         .req_line_speed = 0,
11488         .speed_cap_mask = 0,
11489         /* req_duplex = */0,
11490         /* rsrv = */0,
11491         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
11492         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
11493         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
11494         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11495         .format_fw_ver  = (format_fw_ver_t)NULL,
11496         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
11497         .set_link_led   = (set_link_led_t)NULL,
11498         .phy_specific_func = (phy_specific_func_t)NULL
11499 };
11500
11501
11502 static const struct bnx2x_phy phy_7101 = {
11503         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11504         .addr           = 0xff,
11505         .def_md_devad   = 0,
11506         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11507         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11508         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11509         .mdio_ctrl      = 0,
11510         .supported      = (SUPPORTED_10000baseT_Full |
11511                            SUPPORTED_TP |
11512                            SUPPORTED_Autoneg |
11513                            SUPPORTED_Pause |
11514                            SUPPORTED_Asym_Pause),
11515         .media_type     = ETH_PHY_BASE_T,
11516         .ver_addr       = 0,
11517         .req_flow_ctrl  = 0,
11518         .req_line_speed = 0,
11519         .speed_cap_mask = 0,
11520         .req_duplex     = 0,
11521         .rsrv           = 0,
11522         .config_init    = (config_init_t)bnx2x_7101_config_init,
11523         .read_status    = (read_status_t)bnx2x_7101_read_status,
11524         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11525         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11526         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11527         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11528         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11529         .phy_specific_func = (phy_specific_func_t)NULL
11530 };
11531 static const struct bnx2x_phy phy_8073 = {
11532         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11533         .addr           = 0xff,
11534         .def_md_devad   = 0,
11535         .flags          = 0,
11536         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11537         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11538         .mdio_ctrl      = 0,
11539         .supported      = (SUPPORTED_10000baseT_Full |
11540                            SUPPORTED_2500baseX_Full |
11541                            SUPPORTED_1000baseT_Full |
11542                            SUPPORTED_FIBRE |
11543                            SUPPORTED_Autoneg |
11544                            SUPPORTED_Pause |
11545                            SUPPORTED_Asym_Pause),
11546         .media_type     = ETH_PHY_KR,
11547         .ver_addr       = 0,
11548         .req_flow_ctrl  = 0,
11549         .req_line_speed = 0,
11550         .speed_cap_mask = 0,
11551         .req_duplex     = 0,
11552         .rsrv           = 0,
11553         .config_init    = (config_init_t)bnx2x_8073_config_init,
11554         .read_status    = (read_status_t)bnx2x_8073_read_status,
11555         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11556         .config_loopback = (config_loopback_t)NULL,
11557         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11558         .hw_reset       = (hw_reset_t)NULL,
11559         .set_link_led   = (set_link_led_t)NULL,
11560         .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11561 };
11562 static const struct bnx2x_phy phy_8705 = {
11563         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11564         .addr           = 0xff,
11565         .def_md_devad   = 0,
11566         .flags          = FLAGS_INIT_XGXS_FIRST,
11567         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11568         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11569         .mdio_ctrl      = 0,
11570         .supported      = (SUPPORTED_10000baseT_Full |
11571                            SUPPORTED_FIBRE |
11572                            SUPPORTED_Pause |
11573                            SUPPORTED_Asym_Pause),
11574         .media_type     = ETH_PHY_XFP_FIBER,
11575         .ver_addr       = 0,
11576         .req_flow_ctrl  = 0,
11577         .req_line_speed = 0,
11578         .speed_cap_mask = 0,
11579         .req_duplex     = 0,
11580         .rsrv           = 0,
11581         .config_init    = (config_init_t)bnx2x_8705_config_init,
11582         .read_status    = (read_status_t)bnx2x_8705_read_status,
11583         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11584         .config_loopback = (config_loopback_t)NULL,
11585         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11586         .hw_reset       = (hw_reset_t)NULL,
11587         .set_link_led   = (set_link_led_t)NULL,
11588         .phy_specific_func = (phy_specific_func_t)NULL
11589 };
11590 static const struct bnx2x_phy phy_8706 = {
11591         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11592         .addr           = 0xff,
11593         .def_md_devad   = 0,
11594         .flags          = FLAGS_INIT_XGXS_FIRST,
11595         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11596         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11597         .mdio_ctrl      = 0,
11598         .supported      = (SUPPORTED_10000baseT_Full |
11599                            SUPPORTED_1000baseT_Full |
11600                            SUPPORTED_FIBRE |
11601                            SUPPORTED_Pause |
11602                            SUPPORTED_Asym_Pause),
11603         .media_type     = ETH_PHY_SFPP_10G_FIBER,
11604         .ver_addr       = 0,
11605         .req_flow_ctrl  = 0,
11606         .req_line_speed = 0,
11607         .speed_cap_mask = 0,
11608         .req_duplex     = 0,
11609         .rsrv           = 0,
11610         .config_init    = (config_init_t)bnx2x_8706_config_init,
11611         .read_status    = (read_status_t)bnx2x_8706_read_status,
11612         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11613         .config_loopback = (config_loopback_t)NULL,
11614         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11615         .hw_reset       = (hw_reset_t)NULL,
11616         .set_link_led   = (set_link_led_t)NULL,
11617         .phy_specific_func = (phy_specific_func_t)NULL
11618 };
11619
11620 static const struct bnx2x_phy phy_8726 = {
11621         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11622         .addr           = 0xff,
11623         .def_md_devad   = 0,
11624         .flags          = (FLAGS_INIT_XGXS_FIRST |
11625                            FLAGS_TX_ERROR_CHECK),
11626         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11627         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11628         .mdio_ctrl      = 0,
11629         .supported      = (SUPPORTED_10000baseT_Full |
11630                            SUPPORTED_1000baseT_Full |
11631                            SUPPORTED_Autoneg |
11632                            SUPPORTED_FIBRE |
11633                            SUPPORTED_Pause |
11634                            SUPPORTED_Asym_Pause),
11635         .media_type     = ETH_PHY_NOT_PRESENT,
11636         .ver_addr       = 0,
11637         .req_flow_ctrl  = 0,
11638         .req_line_speed = 0,
11639         .speed_cap_mask = 0,
11640         .req_duplex     = 0,
11641         .rsrv           = 0,
11642         .config_init    = (config_init_t)bnx2x_8726_config_init,
11643         .read_status    = (read_status_t)bnx2x_8726_read_status,
11644         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11645         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11646         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11647         .hw_reset       = (hw_reset_t)NULL,
11648         .set_link_led   = (set_link_led_t)NULL,
11649         .phy_specific_func = (phy_specific_func_t)NULL
11650 };
11651
11652 static const struct bnx2x_phy phy_8727 = {
11653         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11654         .addr           = 0xff,
11655         .def_md_devad   = 0,
11656         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11657                            FLAGS_TX_ERROR_CHECK),
11658         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11659         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11660         .mdio_ctrl      = 0,
11661         .supported      = (SUPPORTED_10000baseT_Full |
11662                            SUPPORTED_1000baseT_Full |
11663                            SUPPORTED_FIBRE |
11664                            SUPPORTED_Pause |
11665                            SUPPORTED_Asym_Pause),
11666         .media_type     = ETH_PHY_NOT_PRESENT,
11667         .ver_addr       = 0,
11668         .req_flow_ctrl  = 0,
11669         .req_line_speed = 0,
11670         .speed_cap_mask = 0,
11671         .req_duplex     = 0,
11672         .rsrv           = 0,
11673         .config_init    = (config_init_t)bnx2x_8727_config_init,
11674         .read_status    = (read_status_t)bnx2x_8727_read_status,
11675         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
11676         .config_loopback = (config_loopback_t)NULL,
11677         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11678         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
11679         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
11680         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11681 };
11682 static const struct bnx2x_phy phy_8481 = {
11683         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11684         .addr           = 0xff,
11685         .def_md_devad   = 0,
11686         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11687                           FLAGS_REARM_LATCH_SIGNAL,
11688         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11689         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11690         .mdio_ctrl      = 0,
11691         .supported      = (SUPPORTED_10baseT_Half |
11692                            SUPPORTED_10baseT_Full |
11693                            SUPPORTED_100baseT_Half |
11694                            SUPPORTED_100baseT_Full |
11695                            SUPPORTED_1000baseT_Full |
11696                            SUPPORTED_10000baseT_Full |
11697                            SUPPORTED_TP |
11698                            SUPPORTED_Autoneg |
11699                            SUPPORTED_Pause |
11700                            SUPPORTED_Asym_Pause),
11701         .media_type     = ETH_PHY_BASE_T,
11702         .ver_addr       = 0,
11703         .req_flow_ctrl  = 0,
11704         .req_line_speed = 0,
11705         .speed_cap_mask = 0,
11706         .req_duplex     = 0,
11707         .rsrv           = 0,
11708         .config_init    = (config_init_t)bnx2x_8481_config_init,
11709         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11710         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
11711         .config_loopback = (config_loopback_t)NULL,
11712         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11713         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11714         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11715         .phy_specific_func = (phy_specific_func_t)NULL
11716 };
11717
11718 static const struct bnx2x_phy phy_84823 = {
11719         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11720         .addr           = 0xff,
11721         .def_md_devad   = 0,
11722         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11723                            FLAGS_REARM_LATCH_SIGNAL |
11724                            FLAGS_TX_ERROR_CHECK),
11725         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11726         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11727         .mdio_ctrl      = 0,
11728         .supported      = (SUPPORTED_10baseT_Half |
11729                            SUPPORTED_10baseT_Full |
11730                            SUPPORTED_100baseT_Half |
11731                            SUPPORTED_100baseT_Full |
11732                            SUPPORTED_1000baseT_Full |
11733                            SUPPORTED_10000baseT_Full |
11734                            SUPPORTED_TP |
11735                            SUPPORTED_Autoneg |
11736                            SUPPORTED_Pause |
11737                            SUPPORTED_Asym_Pause),
11738         .media_type     = ETH_PHY_BASE_T,
11739         .ver_addr       = 0,
11740         .req_flow_ctrl  = 0,
11741         .req_line_speed = 0,
11742         .speed_cap_mask = 0,
11743         .req_duplex     = 0,
11744         .rsrv           = 0,
11745         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11746         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11747         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11748         .config_loopback = (config_loopback_t)NULL,
11749         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11750         .hw_reset       = (hw_reset_t)NULL,
11751         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11752         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11753 };
11754
11755 static const struct bnx2x_phy phy_84833 = {
11756         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11757         .addr           = 0xff,
11758         .def_md_devad   = 0,
11759         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11760                            FLAGS_REARM_LATCH_SIGNAL |
11761                            FLAGS_TX_ERROR_CHECK),
11762         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11763         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11764         .mdio_ctrl      = 0,
11765         .supported      = (SUPPORTED_100baseT_Half |
11766                            SUPPORTED_100baseT_Full |
11767                            SUPPORTED_1000baseT_Full |
11768                            SUPPORTED_10000baseT_Full |
11769                            SUPPORTED_TP |
11770                            SUPPORTED_Autoneg |
11771                            SUPPORTED_Pause |
11772                            SUPPORTED_Asym_Pause),
11773         .media_type     = ETH_PHY_BASE_T,
11774         .ver_addr       = 0,
11775         .req_flow_ctrl  = 0,
11776         .req_line_speed = 0,
11777         .speed_cap_mask = 0,
11778         .req_duplex     = 0,
11779         .rsrv           = 0,
11780         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11781         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11782         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11783         .config_loopback = (config_loopback_t)NULL,
11784         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11785         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11786         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11787         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11788 };
11789
11790 static const struct bnx2x_phy phy_84834 = {
11791         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11792         .addr           = 0xff,
11793         .def_md_devad   = 0,
11794         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11795                             FLAGS_REARM_LATCH_SIGNAL,
11796         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11797         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11798         .mdio_ctrl      = 0,
11799         .supported      = (SUPPORTED_100baseT_Half |
11800                            SUPPORTED_100baseT_Full |
11801                            SUPPORTED_1000baseT_Full |
11802                            SUPPORTED_10000baseT_Full |
11803                            SUPPORTED_TP |
11804                            SUPPORTED_Autoneg |
11805                            SUPPORTED_Pause |
11806                            SUPPORTED_Asym_Pause),
11807         .media_type     = ETH_PHY_BASE_T,
11808         .ver_addr       = 0,
11809         .req_flow_ctrl  = 0,
11810         .req_line_speed = 0,
11811         .speed_cap_mask = 0,
11812         .req_duplex     = 0,
11813         .rsrv           = 0,
11814         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11815         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11816         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11817         .config_loopback = (config_loopback_t)NULL,
11818         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11819         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11820         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11821         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11822 };
11823
11824 static const struct bnx2x_phy phy_54618se = {
11825         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11826         .addr           = 0xff,
11827         .def_md_devad   = 0,
11828         .flags          = FLAGS_INIT_XGXS_FIRST,
11829         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11830         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11831         .mdio_ctrl      = 0,
11832         .supported      = (SUPPORTED_10baseT_Half |
11833                            SUPPORTED_10baseT_Full |
11834                            SUPPORTED_100baseT_Half |
11835                            SUPPORTED_100baseT_Full |
11836                            SUPPORTED_1000baseT_Full |
11837                            SUPPORTED_TP |
11838                            SUPPORTED_Autoneg |
11839                            SUPPORTED_Pause |
11840                            SUPPORTED_Asym_Pause),
11841         .media_type     = ETH_PHY_BASE_T,
11842         .ver_addr       = 0,
11843         .req_flow_ctrl  = 0,
11844         .req_line_speed = 0,
11845         .speed_cap_mask = 0,
11846         /* req_duplex = */0,
11847         /* rsrv = */0,
11848         .config_init    = (config_init_t)bnx2x_54618se_config_init,
11849         .read_status    = (read_status_t)bnx2x_54618se_read_status,
11850         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
11851         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11852         .format_fw_ver  = (format_fw_ver_t)NULL,
11853         .hw_reset       = (hw_reset_t)NULL,
11854         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
11855         .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
11856 };
11857 /*****************************************************************/
11858 /*                                                               */
11859 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11860 /*                                                               */
11861 /*****************************************************************/
11862
11863 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11864                                      struct bnx2x_phy *phy, u8 port,
11865                                      u8 phy_index)
11866 {
11867         /* Get the 4 lanes xgxs config rx and tx */
11868         u32 rx = 0, tx = 0, i;
11869         for (i = 0; i < 2; i++) {
11870                 /* INT_PHY and EXT_PHY1 share the same value location in
11871                  * the shmem. When num_phys is greater than 1, than this value
11872                  * applies only to EXT_PHY1
11873                  */
11874                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11875                         rx = REG_RD(bp, shmem_base +
11876                                     offsetof(struct shmem_region,
11877                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11878
11879                         tx = REG_RD(bp, shmem_base +
11880                                     offsetof(struct shmem_region,
11881                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11882                 } else {
11883                         rx = REG_RD(bp, shmem_base +
11884                                     offsetof(struct shmem_region,
11885                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11886
11887                         tx = REG_RD(bp, shmem_base +
11888                                     offsetof(struct shmem_region,
11889                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11890                 }
11891
11892                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11893                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11894
11895                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11896                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11897         }
11898 }
11899
11900 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11901                                     u8 phy_index, u8 port)
11902 {
11903         u32 ext_phy_config = 0;
11904         switch (phy_index) {
11905         case EXT_PHY1:
11906                 ext_phy_config = REG_RD(bp, shmem_base +
11907                                               offsetof(struct shmem_region,
11908                         dev_info.port_hw_config[port].external_phy_config));
11909                 break;
11910         case EXT_PHY2:
11911                 ext_phy_config = REG_RD(bp, shmem_base +
11912                                               offsetof(struct shmem_region,
11913                         dev_info.port_hw_config[port].external_phy_config2));
11914                 break;
11915         default:
11916                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11917                 return -EINVAL;
11918         }
11919
11920         return ext_phy_config;
11921 }
11922 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11923                                   struct bnx2x_phy *phy)
11924 {
11925         u32 phy_addr;
11926         u32 chip_id;
11927         u32 switch_cfg = (REG_RD(bp, shmem_base +
11928                                        offsetof(struct shmem_region,
11929                         dev_info.port_feature_config[port].link_config)) &
11930                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11931         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11932                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11933
11934         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11935         if (USES_WARPCORE(bp)) {
11936                 u32 serdes_net_if;
11937                 phy_addr = REG_RD(bp,
11938                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11939                 *phy = phy_warpcore;
11940                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11941                         phy->flags |= FLAGS_4_PORT_MODE;
11942                 else
11943                         phy->flags &= ~FLAGS_4_PORT_MODE;
11944                         /* Check Dual mode */
11945                 serdes_net_if = (REG_RD(bp, shmem_base +
11946                                         offsetof(struct shmem_region, dev_info.
11947                                         port_hw_config[port].default_cfg)) &
11948                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11949                 /* Set the appropriate supported and flags indications per
11950                  * interface type of the chip
11951                  */
11952                 switch (serdes_net_if) {
11953                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11954                         phy->supported &= (SUPPORTED_10baseT_Half |
11955                                            SUPPORTED_10baseT_Full |
11956                                            SUPPORTED_100baseT_Half |
11957                                            SUPPORTED_100baseT_Full |
11958                                            SUPPORTED_1000baseT_Full |
11959                                            SUPPORTED_FIBRE |
11960                                            SUPPORTED_Autoneg |
11961                                            SUPPORTED_Pause |
11962                                            SUPPORTED_Asym_Pause);
11963                         phy->media_type = ETH_PHY_BASE_T;
11964                         break;
11965                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11966                         phy->supported &= (SUPPORTED_1000baseT_Full |
11967                                            SUPPORTED_10000baseT_Full |
11968                                            SUPPORTED_FIBRE |
11969                                            SUPPORTED_Pause |
11970                                            SUPPORTED_Asym_Pause);
11971                         phy->media_type = ETH_PHY_XFP_FIBER;
11972                         break;
11973                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11974                         phy->supported &= (SUPPORTED_1000baseT_Full |
11975                                            SUPPORTED_10000baseT_Full |
11976                                            SUPPORTED_FIBRE |
11977                                            SUPPORTED_Pause |
11978                                            SUPPORTED_Asym_Pause);
11979                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
11980                         break;
11981                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11982                         phy->media_type = ETH_PHY_KR;
11983                         phy->supported &= (SUPPORTED_1000baseT_Full |
11984                                            SUPPORTED_10000baseT_Full |
11985                                            SUPPORTED_FIBRE |
11986                                            SUPPORTED_Autoneg |
11987                                            SUPPORTED_Pause |
11988                                            SUPPORTED_Asym_Pause);
11989                         break;
11990                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11991                         phy->media_type = ETH_PHY_KR;
11992                         phy->flags |= FLAGS_WC_DUAL_MODE;
11993                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11994                                            SUPPORTED_FIBRE |
11995                                            SUPPORTED_Pause |
11996                                            SUPPORTED_Asym_Pause);
11997                         break;
11998                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11999                         phy->media_type = ETH_PHY_KR;
12000                         phy->flags |= FLAGS_WC_DUAL_MODE;
12001                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
12002                                            SUPPORTED_10000baseT_Full |
12003                                            SUPPORTED_1000baseT_Full |
12004                                            SUPPORTED_Autoneg |
12005                                            SUPPORTED_FIBRE |
12006                                            SUPPORTED_Pause |
12007                                            SUPPORTED_Asym_Pause);
12008                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12009                         break;
12010                 default:
12011                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
12012                                        serdes_net_if);
12013                         break;
12014                 }
12015
12016                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
12017                  * was not set as expected. For B0, ECO will be enabled so there
12018                  * won't be an issue there
12019                  */
12020                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12021                         phy->flags |= FLAGS_MDC_MDIO_WA;
12022                 else
12023                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
12024         } else {
12025                 switch (switch_cfg) {
12026                 case SWITCH_CFG_1G:
12027                         phy_addr = REG_RD(bp,
12028                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
12029                                           port * 0x10);
12030                         *phy = phy_serdes;
12031                         break;
12032                 case SWITCH_CFG_10G:
12033                         phy_addr = REG_RD(bp,
12034                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
12035                                           port * 0x18);
12036                         *phy = phy_xgxs;
12037                         break;
12038                 default:
12039                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
12040                         return -EINVAL;
12041                 }
12042         }
12043         phy->addr = (u8)phy_addr;
12044         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
12045                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
12046                                             port);
12047         if (CHIP_IS_E2(bp))
12048                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
12049         else
12050                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
12051
12052         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
12053                    port, phy->addr, phy->mdio_ctrl);
12054
12055         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
12056         return 0;
12057 }
12058
12059 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
12060                                   u8 phy_index,
12061                                   u32 shmem_base,
12062                                   u32 shmem2_base,
12063                                   u8 port,
12064                                   struct bnx2x_phy *phy)
12065 {
12066         u32 ext_phy_config, phy_type, config2;
12067         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
12068         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
12069                                                   phy_index, port);
12070         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12071         /* Select the phy type */
12072         switch (phy_type) {
12073         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12074                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12075                 *phy = phy_8073;
12076                 break;
12077         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12078                 *phy = phy_8705;
12079                 break;
12080         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12081                 *phy = phy_8706;
12082                 break;
12083         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12084                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12085                 *phy = phy_8726;
12086                 break;
12087         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12088                 /* BCM8727_NOC => BCM8727 no over current */
12089                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12090                 *phy = phy_8727;
12091                 phy->flags |= FLAGS_NOC;
12092                 break;
12093         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12094         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12095                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12096                 *phy = phy_8727;
12097                 break;
12098         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12099                 *phy = phy_8481;
12100                 break;
12101         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12102                 *phy = phy_84823;
12103                 break;
12104         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12105                 *phy = phy_84833;
12106                 break;
12107         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12108                 *phy = phy_84834;
12109                 break;
12110         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12111         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12112                 *phy = phy_54618se;
12113                 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12114                         phy->flags |= FLAGS_EEE;
12115                 break;
12116         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12117                 *phy = phy_7101;
12118                 break;
12119         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12120                 *phy = phy_null;
12121                 return -EINVAL;
12122         default:
12123                 *phy = phy_null;
12124                 /* In case external PHY wasn't found */
12125                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12126                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12127                         return -EINVAL;
12128                 return 0;
12129         }
12130
12131         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12132         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12133
12134         /* The shmem address of the phy version is located on different
12135          * structures. In case this structure is too old, do not set
12136          * the address
12137          */
12138         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12139                                         dev_info.shared_hw_config.config2));
12140         if (phy_index == EXT_PHY1) {
12141                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12142                                 port_mb[port].ext_phy_fw_version);
12143
12144                 /* Check specific mdc mdio settings */
12145                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12146                         mdc_mdio_access = config2 &
12147                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12148         } else {
12149                 u32 size = REG_RD(bp, shmem2_base);
12150
12151                 if (size >
12152                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12153                         phy->ver_addr = shmem2_base +
12154                             offsetof(struct shmem2_region,
12155                                      ext_phy_fw_version2[port]);
12156                 }
12157                 /* Check specific mdc mdio settings */
12158                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12159                         mdc_mdio_access = (config2 &
12160                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12161                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12162                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12163         }
12164         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12165
12166         if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12167              (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12168             (phy->ver_addr)) {
12169                 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12170                  * version lower than or equal to 1.39
12171                  */
12172                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12173                 if (((raw_ver & 0x7F) <= 39) &&
12174                     (((raw_ver & 0xF80) >> 7) <= 1))
12175                         phy->supported &= ~(SUPPORTED_100baseT_Half |
12176                                             SUPPORTED_100baseT_Full);
12177         }
12178
12179         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12180                    phy_type, port, phy_index);
12181         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
12182                    phy->addr, phy->mdio_ctrl);
12183         return 0;
12184 }
12185
12186 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12187                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12188 {
12189         int status = 0;
12190         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12191         if (phy_index == INT_PHY)
12192                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12193         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12194                                         port, phy);
12195         return status;
12196 }
12197
12198 static void bnx2x_phy_def_cfg(struct link_params *params,
12199                               struct bnx2x_phy *phy,
12200                               u8 phy_index)
12201 {
12202         struct bnx2x *bp = params->bp;
12203         u32 link_config;
12204         /* Populate the default phy configuration for MF mode */
12205         if (phy_index == EXT_PHY2) {
12206                 link_config = REG_RD(bp, params->shmem_base +
12207                                      offsetof(struct shmem_region, dev_info.
12208                         port_feature_config[params->port].link_config2));
12209                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12210                                              offsetof(struct shmem_region,
12211                                                       dev_info.
12212                         port_hw_config[params->port].speed_capability_mask2));
12213         } else {
12214                 link_config = REG_RD(bp, params->shmem_base +
12215                                      offsetof(struct shmem_region, dev_info.
12216                                 port_feature_config[params->port].link_config));
12217                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12218                                              offsetof(struct shmem_region,
12219                                                       dev_info.
12220                         port_hw_config[params->port].speed_capability_mask));
12221         }
12222         DP(NETIF_MSG_LINK,
12223            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12224            phy_index, link_config, phy->speed_cap_mask);
12225
12226         phy->req_duplex = DUPLEX_FULL;
12227         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
12228         case PORT_FEATURE_LINK_SPEED_10M_HALF:
12229                 phy->req_duplex = DUPLEX_HALF;
12230         case PORT_FEATURE_LINK_SPEED_10M_FULL:
12231                 phy->req_line_speed = SPEED_10;
12232                 break;
12233         case PORT_FEATURE_LINK_SPEED_100M_HALF:
12234                 phy->req_duplex = DUPLEX_HALF;
12235         case PORT_FEATURE_LINK_SPEED_100M_FULL:
12236                 phy->req_line_speed = SPEED_100;
12237                 break;
12238         case PORT_FEATURE_LINK_SPEED_1G:
12239                 phy->req_line_speed = SPEED_1000;
12240                 break;
12241         case PORT_FEATURE_LINK_SPEED_2_5G:
12242                 phy->req_line_speed = SPEED_2500;
12243                 break;
12244         case PORT_FEATURE_LINK_SPEED_10G_CX4:
12245                 phy->req_line_speed = SPEED_10000;
12246                 break;
12247         default:
12248                 phy->req_line_speed = SPEED_AUTO_NEG;
12249                 break;
12250         }
12251
12252         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
12253         case PORT_FEATURE_FLOW_CONTROL_AUTO:
12254                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12255                 break;
12256         case PORT_FEATURE_FLOW_CONTROL_TX:
12257                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12258                 break;
12259         case PORT_FEATURE_FLOW_CONTROL_RX:
12260                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12261                 break;
12262         case PORT_FEATURE_FLOW_CONTROL_BOTH:
12263                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12264                 break;
12265         default:
12266                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12267                 break;
12268         }
12269 }
12270
12271 u32 bnx2x_phy_selection(struct link_params *params)
12272 {
12273         u32 phy_config_swapped, prio_cfg;
12274         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12275
12276         phy_config_swapped = params->multi_phy_config &
12277                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12278
12279         prio_cfg = params->multi_phy_config &
12280                         PORT_HW_CFG_PHY_SELECTION_MASK;
12281
12282         if (phy_config_swapped) {
12283                 switch (prio_cfg) {
12284                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12285                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12286                      break;
12287                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12288                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12289                      break;
12290                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12291                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12292                      break;
12293                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12294                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12295                      break;
12296                 }
12297         } else
12298                 return_cfg = prio_cfg;
12299
12300         return return_cfg;
12301 }
12302
12303 int bnx2x_phy_probe(struct link_params *params)
12304 {
12305         u8 phy_index, actual_phy_idx;
12306         u32 phy_config_swapped, sync_offset, media_types;
12307         struct bnx2x *bp = params->bp;
12308         struct bnx2x_phy *phy;
12309         params->num_phys = 0;
12310         DP(NETIF_MSG_LINK, "Begin phy probe\n");
12311         phy_config_swapped = params->multi_phy_config &
12312                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12313
12314         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12315               phy_index++) {
12316                 actual_phy_idx = phy_index;
12317                 if (phy_config_swapped) {
12318                         if (phy_index == EXT_PHY1)
12319                                 actual_phy_idx = EXT_PHY2;
12320                         else if (phy_index == EXT_PHY2)
12321                                 actual_phy_idx = EXT_PHY1;
12322                 }
12323                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12324                                " actual_phy_idx %x\n", phy_config_swapped,
12325                            phy_index, actual_phy_idx);
12326                 phy = &params->phy[actual_phy_idx];
12327                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12328                                        params->shmem2_base, params->port,
12329                                        phy) != 0) {
12330                         params->num_phys = 0;
12331                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12332                                    phy_index);
12333                         for (phy_index = INT_PHY;
12334                               phy_index < MAX_PHYS;
12335                               phy_index++)
12336                                 *phy = phy_null;
12337                         return -EINVAL;
12338                 }
12339                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12340                         break;
12341
12342                 if (params->feature_config_flags &
12343                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12344                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12345
12346                 if (!(params->feature_config_flags &
12347                       FEATURE_CONFIG_MT_SUPPORT))
12348                         phy->flags |= FLAGS_MDC_MDIO_WA_G;
12349
12350                 sync_offset = params->shmem_base +
12351                         offsetof(struct shmem_region,
12352                         dev_info.port_hw_config[params->port].media_type);
12353                 media_types = REG_RD(bp, sync_offset);
12354
12355                 /* Update media type for non-PMF sync only for the first time
12356                  * In case the media type changes afterwards, it will be updated
12357                  * using the update_status function
12358                  */
12359                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12360                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12361                                      actual_phy_idx))) == 0) {
12362                         media_types |= ((phy->media_type &
12363                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12364                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12365                                  actual_phy_idx));
12366                 }
12367                 REG_WR(bp, sync_offset, media_types);
12368
12369                 bnx2x_phy_def_cfg(params, phy, phy_index);
12370                 params->num_phys++;
12371         }
12372
12373         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12374         return 0;
12375 }
12376
12377 static void bnx2x_init_bmac_loopback(struct link_params *params,
12378                                      struct link_vars *vars)
12379 {
12380         struct bnx2x *bp = params->bp;
12381                 vars->link_up = 1;
12382                 vars->line_speed = SPEED_10000;
12383                 vars->duplex = DUPLEX_FULL;
12384                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12385                 vars->mac_type = MAC_TYPE_BMAC;
12386
12387                 vars->phy_flags = PHY_XGXS_FLAG;
12388
12389                 bnx2x_xgxs_deassert(params);
12390
12391                 /* Set bmac loopback */
12392                 bnx2x_bmac_enable(params, vars, 1, 1);
12393
12394                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12395 }
12396
12397 static void bnx2x_init_emac_loopback(struct link_params *params,
12398                                      struct link_vars *vars)
12399 {
12400         struct bnx2x *bp = params->bp;
12401                 vars->link_up = 1;
12402                 vars->line_speed = SPEED_1000;
12403                 vars->duplex = DUPLEX_FULL;
12404                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12405                 vars->mac_type = MAC_TYPE_EMAC;
12406
12407                 vars->phy_flags = PHY_XGXS_FLAG;
12408
12409                 bnx2x_xgxs_deassert(params);
12410                 /* Set bmac loopback */
12411                 bnx2x_emac_enable(params, vars, 1);
12412                 bnx2x_emac_program(params, vars);
12413                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12414 }
12415
12416 static void bnx2x_init_xmac_loopback(struct link_params *params,
12417                                      struct link_vars *vars)
12418 {
12419         struct bnx2x *bp = params->bp;
12420         vars->link_up = 1;
12421         if (!params->req_line_speed[0])
12422                 vars->line_speed = SPEED_10000;
12423         else
12424                 vars->line_speed = params->req_line_speed[0];
12425         vars->duplex = DUPLEX_FULL;
12426         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12427         vars->mac_type = MAC_TYPE_XMAC;
12428         vars->phy_flags = PHY_XGXS_FLAG;
12429         /* Set WC to loopback mode since link is required to provide clock
12430          * to the XMAC in 20G mode
12431          */
12432         bnx2x_set_aer_mmd(params, &params->phy[0]);
12433         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12434         params->phy[INT_PHY].config_loopback(
12435                         &params->phy[INT_PHY],
12436                         params);
12437
12438         bnx2x_xmac_enable(params, vars, 1);
12439         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12440 }
12441
12442 static void bnx2x_init_umac_loopback(struct link_params *params,
12443                                      struct link_vars *vars)
12444 {
12445         struct bnx2x *bp = params->bp;
12446         vars->link_up = 1;
12447         vars->line_speed = SPEED_1000;
12448         vars->duplex = DUPLEX_FULL;
12449         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12450         vars->mac_type = MAC_TYPE_UMAC;
12451         vars->phy_flags = PHY_XGXS_FLAG;
12452         bnx2x_umac_enable(params, vars, 1);
12453
12454         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12455 }
12456
12457 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12458                                      struct link_vars *vars)
12459 {
12460         struct bnx2x *bp = params->bp;
12461         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
12462         vars->link_up = 1;
12463         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12464         vars->duplex = DUPLEX_FULL;
12465         if (params->req_line_speed[0] == SPEED_1000)
12466                 vars->line_speed = SPEED_1000;
12467         else if ((params->req_line_speed[0] == SPEED_20000) ||
12468                  (int_phy->flags & FLAGS_WC_DUAL_MODE))
12469                 vars->line_speed = SPEED_20000;
12470         else
12471                 vars->line_speed = SPEED_10000;
12472
12473         if (!USES_WARPCORE(bp))
12474                 bnx2x_xgxs_deassert(params);
12475         bnx2x_link_initialize(params, vars);
12476
12477         if (params->req_line_speed[0] == SPEED_1000) {
12478                 if (USES_WARPCORE(bp))
12479                         bnx2x_umac_enable(params, vars, 0);
12480                 else {
12481                         bnx2x_emac_program(params, vars);
12482                         bnx2x_emac_enable(params, vars, 0);
12483                 }
12484         } else {
12485                 if (USES_WARPCORE(bp))
12486                         bnx2x_xmac_enable(params, vars, 0);
12487                 else
12488                         bnx2x_bmac_enable(params, vars, 0, 1);
12489         }
12490
12491         if (params->loopback_mode == LOOPBACK_XGXS) {
12492                 /* Set 10G XGXS loopback */
12493                 int_phy->config_loopback(int_phy, params);
12494         } else {
12495                 /* Set external phy loopback */
12496                 u8 phy_index;
12497                 for (phy_index = EXT_PHY1;
12498                       phy_index < params->num_phys; phy_index++)
12499                         if (params->phy[phy_index].config_loopback)
12500                                 params->phy[phy_index].config_loopback(
12501                                         &params->phy[phy_index],
12502                                         params);
12503         }
12504         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12505
12506         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12507 }
12508
12509 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12510 {
12511         struct bnx2x *bp = params->bp;
12512         u8 val = en * 0x1F;
12513
12514         /* Open / close the gate between the NIG and the BRB */
12515         if (!CHIP_IS_E1x(bp))
12516                 val |= en * 0x20;
12517         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12518
12519         if (!CHIP_IS_E1(bp)) {
12520                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12521                        en*0x3);
12522         }
12523
12524         REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12525                     NIG_REG_LLH0_BRB1_NOT_MCP), en);
12526 }
12527 static int bnx2x_avoid_link_flap(struct link_params *params,
12528                                             struct link_vars *vars)
12529 {
12530         u32 phy_idx;
12531         u32 dont_clear_stat, lfa_sts;
12532         struct bnx2x *bp = params->bp;
12533
12534         bnx2x_set_mdio_emac_per_phy(bp, params);
12535         /* Sync the link parameters */
12536         bnx2x_link_status_update(params, vars);
12537
12538         /*
12539          * The module verification was already done by previous link owner,
12540          * so this call is meant only to get warning message
12541          */
12542
12543         for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12544                 struct bnx2x_phy *phy = &params->phy[phy_idx];
12545                 if (phy->phy_specific_func) {
12546                         DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12547                         phy->phy_specific_func(phy, params, PHY_INIT);
12548                 }
12549                 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12550                     (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12551                     (phy->media_type == ETH_PHY_DA_TWINAX))
12552                         bnx2x_verify_sfp_module(phy, params);
12553         }
12554         lfa_sts = REG_RD(bp, params->lfa_base +
12555                          offsetof(struct shmem_lfa,
12556                                   lfa_sts));
12557
12558         dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12559
12560         /* Re-enable the NIG/MAC */
12561         if (CHIP_IS_E3(bp)) {
12562                 if (!dont_clear_stat) {
12563                         REG_WR(bp, GRCBASE_MISC +
12564                                MISC_REGISTERS_RESET_REG_2_CLEAR,
12565                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12566                                 params->port));
12567                         REG_WR(bp, GRCBASE_MISC +
12568                                MISC_REGISTERS_RESET_REG_2_SET,
12569                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12570                                 params->port));
12571                 }
12572                 if (vars->line_speed < SPEED_10000)
12573                         bnx2x_umac_enable(params, vars, 0);
12574                 else
12575                         bnx2x_xmac_enable(params, vars, 0);
12576         } else {
12577                 if (vars->line_speed < SPEED_10000)
12578                         bnx2x_emac_enable(params, vars, 0);
12579                 else
12580                         bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12581         }
12582
12583         /* Increment LFA count */
12584         lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12585                    (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12586                        LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12587                     << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12588         /* Clear link flap reason */
12589         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12590
12591         REG_WR(bp, params->lfa_base +
12592                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12593
12594         /* Disable NIG DRAIN */
12595         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12596
12597         /* Enable interrupts */
12598         bnx2x_link_int_enable(params);
12599         return 0;
12600 }
12601
12602 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12603                                          struct link_vars *vars,
12604                                          int lfa_status)
12605 {
12606         u32 lfa_sts, cfg_idx, tmp_val;
12607         struct bnx2x *bp = params->bp;
12608
12609         bnx2x_link_reset(params, vars, 1);
12610
12611         if (!params->lfa_base)
12612                 return;
12613         /* Store the new link parameters */
12614         REG_WR(bp, params->lfa_base +
12615                offsetof(struct shmem_lfa, req_duplex),
12616                params->req_duplex[0] | (params->req_duplex[1] << 16));
12617
12618         REG_WR(bp, params->lfa_base +
12619                offsetof(struct shmem_lfa, req_flow_ctrl),
12620                params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12621
12622         REG_WR(bp, params->lfa_base +
12623                offsetof(struct shmem_lfa, req_line_speed),
12624                params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12625
12626         for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12627                 REG_WR(bp, params->lfa_base +
12628                        offsetof(struct shmem_lfa,
12629                                 speed_cap_mask[cfg_idx]),
12630                        params->speed_cap_mask[cfg_idx]);
12631         }
12632
12633         tmp_val = REG_RD(bp, params->lfa_base +
12634                          offsetof(struct shmem_lfa, additional_config));
12635         tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12636         tmp_val |= params->req_fc_auto_adv;
12637
12638         REG_WR(bp, params->lfa_base +
12639                offsetof(struct shmem_lfa, additional_config), tmp_val);
12640
12641         lfa_sts = REG_RD(bp, params->lfa_base +
12642                          offsetof(struct shmem_lfa, lfa_sts));
12643
12644         /* Clear the "Don't Clear Statistics" bit, and set reason */
12645         lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12646
12647         /* Set link flap reason */
12648         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12649         lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12650                     LFA_LINK_FLAP_REASON_OFFSET);
12651
12652         /* Increment link flap counter */
12653         lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12654                    (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12655                        LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12656                     << LINK_FLAP_COUNT_OFFSET));
12657         REG_WR(bp, params->lfa_base +
12658                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12659         /* Proceed with regular link initialization */
12660 }
12661
12662 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12663 {
12664         int lfa_status;
12665         struct bnx2x *bp = params->bp;
12666         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12667         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12668                    params->req_line_speed[0], params->req_flow_ctrl[0]);
12669         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12670                    params->req_line_speed[1], params->req_flow_ctrl[1]);
12671         DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12672         vars->link_status = 0;
12673         vars->phy_link_up = 0;
12674         vars->link_up = 0;
12675         vars->line_speed = 0;
12676         vars->duplex = DUPLEX_FULL;
12677         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12678         vars->mac_type = MAC_TYPE_NONE;
12679         vars->phy_flags = 0;
12680         vars->check_kr2_recovery_cnt = 0;
12681         params->link_flags = PHY_INITIALIZED;
12682         /* Driver opens NIG-BRB filters */
12683         bnx2x_set_rx_filter(params, 1);
12684         bnx2x_chng_link_count(params, true);
12685         /* Check if link flap can be avoided */
12686         lfa_status = bnx2x_check_lfa(params);
12687
12688         if (lfa_status == 0) {
12689                 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12690                 return bnx2x_avoid_link_flap(params, vars);
12691         }
12692
12693         DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12694                        lfa_status);
12695         bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12696
12697         /* Disable attentions */
12698         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12699                        (NIG_MASK_XGXS0_LINK_STATUS |
12700                         NIG_MASK_XGXS0_LINK10G |
12701                         NIG_MASK_SERDES0_LINK_STATUS |
12702                         NIG_MASK_MI_INT));
12703
12704         bnx2x_emac_init(params, vars);
12705
12706         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12707                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12708
12709         if (params->num_phys == 0) {
12710                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12711                 return -EINVAL;
12712         }
12713         set_phy_vars(params, vars);
12714
12715         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12716         switch (params->loopback_mode) {
12717         case LOOPBACK_BMAC:
12718                 bnx2x_init_bmac_loopback(params, vars);
12719                 break;
12720         case LOOPBACK_EMAC:
12721                 bnx2x_init_emac_loopback(params, vars);
12722                 break;
12723         case LOOPBACK_XMAC:
12724                 bnx2x_init_xmac_loopback(params, vars);
12725                 break;
12726         case LOOPBACK_UMAC:
12727                 bnx2x_init_umac_loopback(params, vars);
12728                 break;
12729         case LOOPBACK_XGXS:
12730         case LOOPBACK_EXT_PHY:
12731                 bnx2x_init_xgxs_loopback(params, vars);
12732                 break;
12733         default:
12734                 if (!CHIP_IS_E3(bp)) {
12735                         if (params->switch_cfg == SWITCH_CFG_10G)
12736                                 bnx2x_xgxs_deassert(params);
12737                         else
12738                                 bnx2x_serdes_deassert(bp, params->port);
12739                 }
12740                 bnx2x_link_initialize(params, vars);
12741                 msleep(30);
12742                 bnx2x_link_int_enable(params);
12743                 break;
12744         }
12745         bnx2x_update_mng(params, vars->link_status);
12746
12747         bnx2x_update_mng_eee(params, vars->eee_status);
12748         return 0;
12749 }
12750
12751 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12752                      u8 reset_ext_phy)
12753 {
12754         struct bnx2x *bp = params->bp;
12755         u8 phy_index, port = params->port, clear_latch_ind = 0;
12756         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12757         /* Disable attentions */
12758         vars->link_status = 0;
12759         bnx2x_chng_link_count(params, true);
12760         bnx2x_update_mng(params, vars->link_status);
12761         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12762                               SHMEM_EEE_ACTIVE_BIT);
12763         bnx2x_update_mng_eee(params, vars->eee_status);
12764         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12765                        (NIG_MASK_XGXS0_LINK_STATUS |
12766                         NIG_MASK_XGXS0_LINK10G |
12767                         NIG_MASK_SERDES0_LINK_STATUS |
12768                         NIG_MASK_MI_INT));
12769
12770         /* Activate nig drain */
12771         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12772
12773         /* Disable nig egress interface */
12774         if (!CHIP_IS_E3(bp)) {
12775                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12776                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12777         }
12778
12779                 if (!CHIP_IS_E3(bp)) {
12780                         bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12781                 } else {
12782                         bnx2x_set_xmac_rxtx(params, 0);
12783                         bnx2x_set_umac_rxtx(params, 0);
12784                 }
12785         /* Disable emac */
12786         if (!CHIP_IS_E3(bp))
12787                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12788
12789         usleep_range(10000, 20000);
12790         /* The PHY reset is controlled by GPIO 1
12791          * Hold it as vars low
12792          */
12793          /* Clear link led */
12794         bnx2x_set_mdio_emac_per_phy(bp, params);
12795         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12796
12797         if (reset_ext_phy) {
12798                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12799                       phy_index++) {
12800                         if (params->phy[phy_index].link_reset) {
12801                                 bnx2x_set_aer_mmd(params,
12802                                                   &params->phy[phy_index]);
12803                                 params->phy[phy_index].link_reset(
12804                                         &params->phy[phy_index],
12805                                         params);
12806                         }
12807                         if (params->phy[phy_index].flags &
12808                             FLAGS_REARM_LATCH_SIGNAL)
12809                                 clear_latch_ind = 1;
12810                 }
12811         }
12812
12813         if (clear_latch_ind) {
12814                 /* Clear latching indication */
12815                 bnx2x_rearm_latch_signal(bp, port, 0);
12816                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12817                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
12818         }
12819         if (params->phy[INT_PHY].link_reset)
12820                 params->phy[INT_PHY].link_reset(
12821                         &params->phy[INT_PHY], params);
12822
12823         /* Disable nig ingress interface */
12824         if (!CHIP_IS_E3(bp)) {
12825                 /* Reset BigMac */
12826                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12827                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12828                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12829                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12830         } else {
12831                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12832                 bnx2x_set_xumac_nig(params, 0, 0);
12833                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12834                     MISC_REGISTERS_RESET_REG_2_XMAC)
12835                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12836                                XMAC_CTRL_REG_SOFT_RESET);
12837         }
12838         vars->link_up = 0;
12839         vars->phy_flags = 0;
12840         return 0;
12841 }
12842 int bnx2x_lfa_reset(struct link_params *params,
12843                                struct link_vars *vars)
12844 {
12845         struct bnx2x *bp = params->bp;
12846         vars->link_up = 0;
12847         vars->phy_flags = 0;
12848         params->link_flags &= ~PHY_INITIALIZED;
12849         if (!params->lfa_base)
12850                 return bnx2x_link_reset(params, vars, 1);
12851         /*
12852          * Activate NIG drain so that during this time the device won't send
12853          * anything while it is unable to response.
12854          */
12855         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12856
12857         /*
12858          * Close gracefully the gate from BMAC to NIG such that no half packets
12859          * are passed.
12860          */
12861         if (!CHIP_IS_E3(bp))
12862                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12863
12864         if (CHIP_IS_E3(bp)) {
12865                 bnx2x_set_xmac_rxtx(params, 0);
12866                 bnx2x_set_umac_rxtx(params, 0);
12867         }
12868         /* Wait 10ms for the pipe to clean up*/
12869         usleep_range(10000, 20000);
12870
12871         /* Clean the NIG-BRB using the network filters in a way that will
12872          * not cut a packet in the middle.
12873          */
12874         bnx2x_set_rx_filter(params, 0);
12875
12876         /*
12877          * Re-open the gate between the BMAC and the NIG, after verifying the
12878          * gate to the BRB is closed, otherwise packets may arrive to the
12879          * firmware before driver had initialized it. The target is to achieve
12880          * minimum management protocol down time.
12881          */
12882         if (!CHIP_IS_E3(bp))
12883                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12884
12885         if (CHIP_IS_E3(bp)) {
12886                 bnx2x_set_xmac_rxtx(params, 1);
12887                 bnx2x_set_umac_rxtx(params, 1);
12888         }
12889         /* Disable NIG drain */
12890         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12891         return 0;
12892 }
12893
12894 /****************************************************************************/
12895 /*                              Common function                             */
12896 /****************************************************************************/
12897 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12898                                       u32 shmem_base_path[],
12899                                       u32 shmem2_base_path[], u8 phy_index,
12900                                       u32 chip_id)
12901 {
12902         struct bnx2x_phy phy[PORT_MAX];
12903         struct bnx2x_phy *phy_blk[PORT_MAX];
12904         u16 val;
12905         s8 port = 0;
12906         s8 port_of_path = 0;
12907         u32 swap_val, swap_override;
12908         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
12909         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
12910         port ^= (swap_val && swap_override);
12911         bnx2x_ext_phy_hw_reset(bp, port);
12912         /* PART1 - Reset both phys */
12913         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12914                 u32 shmem_base, shmem2_base;
12915                 /* In E2, same phy is using for port0 of the two paths */
12916                 if (CHIP_IS_E1x(bp)) {
12917                         shmem_base = shmem_base_path[0];
12918                         shmem2_base = shmem2_base_path[0];
12919                         port_of_path = port;
12920                 } else {
12921                         shmem_base = shmem_base_path[port];
12922                         shmem2_base = shmem2_base_path[port];
12923                         port_of_path = 0;
12924                 }
12925
12926                 /* Extract the ext phy address for the port */
12927                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12928                                        port_of_path, &phy[port]) !=
12929                     0) {
12930                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
12931                         return -EINVAL;
12932                 }
12933                 /* Disable attentions */
12934                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12935                                port_of_path*4,
12936                                (NIG_MASK_XGXS0_LINK_STATUS |
12937                                 NIG_MASK_XGXS0_LINK10G |
12938                                 NIG_MASK_SERDES0_LINK_STATUS |
12939                                 NIG_MASK_MI_INT));
12940
12941                 /* Need to take the phy out of low power mode in order
12942                  * to write to access its registers
12943                  */
12944                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12945                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12946                                port);
12947
12948                 /* Reset the phy */
12949                 bnx2x_cl45_write(bp, &phy[port],
12950                                  MDIO_PMA_DEVAD,
12951                                  MDIO_PMA_REG_CTRL,
12952                                  1<<15);
12953         }
12954
12955         /* Add delay of 150ms after reset */
12956         msleep(150);
12957
12958         if (phy[PORT_0].addr & 0x1) {
12959                 phy_blk[PORT_0] = &(phy[PORT_1]);
12960                 phy_blk[PORT_1] = &(phy[PORT_0]);
12961         } else {
12962                 phy_blk[PORT_0] = &(phy[PORT_0]);
12963                 phy_blk[PORT_1] = &(phy[PORT_1]);
12964         }
12965
12966         /* PART2 - Download firmware to both phys */
12967         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12968                 if (CHIP_IS_E1x(bp))
12969                         port_of_path = port;
12970                 else
12971                         port_of_path = 0;
12972
12973                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12974                            phy_blk[port]->addr);
12975                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12976                                                       port_of_path))
12977                         return -EINVAL;
12978
12979                 /* Only set bit 10 = 1 (Tx power down) */
12980                 bnx2x_cl45_read(bp, phy_blk[port],
12981                                 MDIO_PMA_DEVAD,
12982                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12983
12984                 /* Phase1 of TX_POWER_DOWN reset */
12985                 bnx2x_cl45_write(bp, phy_blk[port],
12986                                  MDIO_PMA_DEVAD,
12987                                  MDIO_PMA_REG_TX_POWER_DOWN,
12988                                  (val | 1<<10));
12989         }
12990
12991         /* Toggle Transmitter: Power down and then up with 600ms delay
12992          * between
12993          */
12994         msleep(600);
12995
12996         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12997         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12998                 /* Phase2 of POWER_DOWN_RESET */
12999                 /* Release bit 10 (Release Tx power down) */
13000                 bnx2x_cl45_read(bp, phy_blk[port],
13001                                 MDIO_PMA_DEVAD,
13002                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13003
13004                 bnx2x_cl45_write(bp, phy_blk[port],
13005                                 MDIO_PMA_DEVAD,
13006                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
13007                 usleep_range(15000, 30000);
13008
13009                 /* Read modify write the SPI-ROM version select register */
13010                 bnx2x_cl45_read(bp, phy_blk[port],
13011                                 MDIO_PMA_DEVAD,
13012                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
13013                 bnx2x_cl45_write(bp, phy_blk[port],
13014                                  MDIO_PMA_DEVAD,
13015                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
13016
13017                 /* set GPIO2 back to LOW */
13018                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
13019                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
13020         }
13021         return 0;
13022 }
13023 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
13024                                       u32 shmem_base_path[],
13025                                       u32 shmem2_base_path[], u8 phy_index,
13026                                       u32 chip_id)
13027 {
13028         u32 val;
13029         s8 port;
13030         struct bnx2x_phy phy;
13031         /* Use port1 because of the static port-swap */
13032         /* Enable the module detection interrupt */
13033         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13034         val |= ((1<<MISC_REGISTERS_GPIO_3)|
13035                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
13036         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13037
13038         bnx2x_ext_phy_hw_reset(bp, 0);
13039         usleep_range(5000, 10000);
13040         for (port = 0; port < PORT_MAX; port++) {
13041                 u32 shmem_base, shmem2_base;
13042
13043                 /* In E2, same phy is using for port0 of the two paths */
13044                 if (CHIP_IS_E1x(bp)) {
13045                         shmem_base = shmem_base_path[0];
13046                         shmem2_base = shmem2_base_path[0];
13047                 } else {
13048                         shmem_base = shmem_base_path[port];
13049                         shmem2_base = shmem2_base_path[port];
13050                 }
13051                 /* Extract the ext phy address for the port */
13052                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13053                                        port, &phy) !=
13054                     0) {
13055                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13056                         return -EINVAL;
13057                 }
13058
13059                 /* Reset phy*/
13060                 bnx2x_cl45_write(bp, &phy,
13061                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
13062
13063
13064                 /* Set fault module detected LED on */
13065                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
13066                                MISC_REGISTERS_GPIO_HIGH,
13067                                port);
13068         }
13069
13070         return 0;
13071 }
13072 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
13073                                          u8 *io_gpio, u8 *io_port)
13074 {
13075
13076         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
13077                                           offsetof(struct shmem_region,
13078                                 dev_info.port_hw_config[PORT_0].default_cfg));
13079         switch (phy_gpio_reset) {
13080         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
13081                 *io_gpio = 0;
13082                 *io_port = 0;
13083                 break;
13084         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
13085                 *io_gpio = 1;
13086                 *io_port = 0;
13087                 break;
13088         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
13089                 *io_gpio = 2;
13090                 *io_port = 0;
13091                 break;
13092         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
13093                 *io_gpio = 3;
13094                 *io_port = 0;
13095                 break;
13096         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
13097                 *io_gpio = 0;
13098                 *io_port = 1;
13099                 break;
13100         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
13101                 *io_gpio = 1;
13102                 *io_port = 1;
13103                 break;
13104         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13105                 *io_gpio = 2;
13106                 *io_port = 1;
13107                 break;
13108         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13109                 *io_gpio = 3;
13110                 *io_port = 1;
13111                 break;
13112         default:
13113                 /* Don't override the io_gpio and io_port */
13114                 break;
13115         }
13116 }
13117
13118 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13119                                       u32 shmem_base_path[],
13120                                       u32 shmem2_base_path[], u8 phy_index,
13121                                       u32 chip_id)
13122 {
13123         s8 port, reset_gpio;
13124         u32 swap_val, swap_override;
13125         struct bnx2x_phy phy[PORT_MAX];
13126         struct bnx2x_phy *phy_blk[PORT_MAX];
13127         s8 port_of_path;
13128         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13129         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13130
13131         reset_gpio = MISC_REGISTERS_GPIO_1;
13132         port = 1;
13133
13134         /* Retrieve the reset gpio/port which control the reset.
13135          * Default is GPIO1, PORT1
13136          */
13137         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13138                                      (u8 *)&reset_gpio, (u8 *)&port);
13139
13140         /* Calculate the port based on port swap */
13141         port ^= (swap_val && swap_override);
13142
13143         /* Initiate PHY reset*/
13144         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13145                        port);
13146         usleep_range(1000, 2000);
13147         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13148                        port);
13149
13150         usleep_range(5000, 10000);
13151
13152         /* PART1 - Reset both phys */
13153         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13154                 u32 shmem_base, shmem2_base;
13155
13156                 /* In E2, same phy is using for port0 of the two paths */
13157                 if (CHIP_IS_E1x(bp)) {
13158                         shmem_base = shmem_base_path[0];
13159                         shmem2_base = shmem2_base_path[0];
13160                         port_of_path = port;
13161                 } else {
13162                         shmem_base = shmem_base_path[port];
13163                         shmem2_base = shmem2_base_path[port];
13164                         port_of_path = 0;
13165                 }
13166
13167                 /* Extract the ext phy address for the port */
13168                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13169                                        port_of_path, &phy[port]) !=
13170                                        0) {
13171                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13172                         return -EINVAL;
13173                 }
13174                 /* disable attentions */
13175                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13176                                port_of_path*4,
13177                                (NIG_MASK_XGXS0_LINK_STATUS |
13178                                 NIG_MASK_XGXS0_LINK10G |
13179                                 NIG_MASK_SERDES0_LINK_STATUS |
13180                                 NIG_MASK_MI_INT));
13181
13182
13183                 /* Reset the phy */
13184                 bnx2x_cl45_write(bp, &phy[port],
13185                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13186         }
13187
13188         /* Add delay of 150ms after reset */
13189         msleep(150);
13190         if (phy[PORT_0].addr & 0x1) {
13191                 phy_blk[PORT_0] = &(phy[PORT_1]);
13192                 phy_blk[PORT_1] = &(phy[PORT_0]);
13193         } else {
13194                 phy_blk[PORT_0] = &(phy[PORT_0]);
13195                 phy_blk[PORT_1] = &(phy[PORT_1]);
13196         }
13197         /* PART2 - Download firmware to both phys */
13198         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13199                 if (CHIP_IS_E1x(bp))
13200                         port_of_path = port;
13201                 else
13202                         port_of_path = 0;
13203                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13204                            phy_blk[port]->addr);
13205                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13206                                                       port_of_path))
13207                         return -EINVAL;
13208                 /* Disable PHY transmitter output */
13209                 bnx2x_cl45_write(bp, phy_blk[port],
13210                                  MDIO_PMA_DEVAD,
13211                                  MDIO_PMA_REG_TX_DISABLE, 1);
13212
13213         }
13214         return 0;
13215 }
13216
13217 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13218                                                 u32 shmem_base_path[],
13219                                                 u32 shmem2_base_path[],
13220                                                 u8 phy_index,
13221                                                 u32 chip_id)
13222 {
13223         u8 reset_gpios;
13224         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13225         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13226         udelay(10);
13227         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13228         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13229                 reset_gpios);
13230         return 0;
13231 }
13232
13233 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13234                                      u32 shmem2_base_path[], u8 phy_index,
13235                                      u32 ext_phy_type, u32 chip_id)
13236 {
13237         int rc = 0;
13238
13239         switch (ext_phy_type) {
13240         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13241                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13242                                                 shmem2_base_path,
13243                                                 phy_index, chip_id);
13244                 break;
13245         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13246         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13247         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13248                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13249                                                 shmem2_base_path,
13250                                                 phy_index, chip_id);
13251                 break;
13252
13253         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13254                 /* GPIO1 affects both ports, so there's need to pull
13255                  * it for single port alone
13256                  */
13257                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13258                                                 shmem2_base_path,
13259                                                 phy_index, chip_id);
13260                 break;
13261         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13262         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13263                 /* GPIO3's are linked, and so both need to be toggled
13264                  * to obtain required 2us pulse.
13265                  */
13266                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13267                                                 shmem2_base_path,
13268                                                 phy_index, chip_id);
13269                 break;
13270         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13271                 rc = -EINVAL;
13272                 break;
13273         default:
13274                 DP(NETIF_MSG_LINK,
13275                            "ext_phy 0x%x common init not required\n",
13276                            ext_phy_type);
13277                 break;
13278         }
13279
13280         if (rc)
13281                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
13282                                       " Port %d\n",
13283                          0);
13284         return rc;
13285 }
13286
13287 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13288                           u32 shmem2_base_path[], u32 chip_id)
13289 {
13290         int rc = 0;
13291         u32 phy_ver, val;
13292         u8 phy_index = 0;
13293         u32 ext_phy_type, ext_phy_config;
13294
13295         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13296         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13297         DP(NETIF_MSG_LINK, "Begin common phy init\n");
13298         if (CHIP_IS_E3(bp)) {
13299                 /* Enable EPIO */
13300                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13301                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13302         }
13303         /* Check if common init was already done */
13304         phy_ver = REG_RD(bp, shmem_base_path[0] +
13305                          offsetof(struct shmem_region,
13306                                   port_mb[PORT_0].ext_phy_fw_version));
13307         if (phy_ver) {
13308                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13309                                phy_ver);
13310                 return 0;
13311         }
13312
13313         /* Read the ext_phy_type for arbitrary port(0) */
13314         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13315               phy_index++) {
13316                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13317                                                           shmem_base_path[0],
13318                                                           phy_index, 0);
13319                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13320                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13321                                                 shmem2_base_path,
13322                                                 phy_index, ext_phy_type,
13323                                                 chip_id);
13324         }
13325         return rc;
13326 }
13327
13328 static void bnx2x_check_over_curr(struct link_params *params,
13329                                   struct link_vars *vars)
13330 {
13331         struct bnx2x *bp = params->bp;
13332         u32 cfg_pin;
13333         u8 port = params->port;
13334         u32 pin_val;
13335
13336         cfg_pin = (REG_RD(bp, params->shmem_base +
13337                           offsetof(struct shmem_region,
13338                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13339                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13340                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13341
13342         /* Ignore check if no external input PIN available */
13343         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13344                 return;
13345
13346         if (!pin_val) {
13347                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13348                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
13349                                             " been detected and the power to "
13350                                             "that SFP+ module has been removed"
13351                                             " to prevent failure of the card."
13352                                             " Please remove the SFP+ module and"
13353                                             " restart the system to clear this"
13354                                             " error.\n",
13355                          params->port);
13356                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13357                         bnx2x_warpcore_power_module(params, 0);
13358                 }
13359         } else
13360                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13361 }
13362
13363 /* Returns 0 if no change occurred since last check; 1 otherwise. */
13364 static u8 bnx2x_analyze_link_error(struct link_params *params,
13365                                     struct link_vars *vars, u32 status,
13366                                     u32 phy_flag, u32 link_flag, u8 notify)
13367 {
13368         struct bnx2x *bp = params->bp;
13369         /* Compare new value with previous value */
13370         u8 led_mode;
13371         u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13372
13373         if ((status ^ old_status) == 0)
13374                 return 0;
13375
13376         /* If values differ */
13377         switch (phy_flag) {
13378         case PHY_HALF_OPEN_CONN_FLAG:
13379                 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13380                 break;
13381         case PHY_SFP_TX_FAULT_FLAG:
13382                 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13383                 break;
13384         default:
13385                 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13386         }
13387         DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13388            old_status, status);
13389
13390         /* Do not touch the link in case physical link down */
13391         if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
13392                 return 1;
13393
13394         /* a. Update shmem->link_status accordingly
13395          * b. Update link_vars->link_up
13396          */
13397         if (status) {
13398                 vars->link_status &= ~LINK_STATUS_LINK_UP;
13399                 vars->link_status |= link_flag;
13400                 vars->link_up = 0;
13401                 vars->phy_flags |= phy_flag;
13402
13403                 /* activate nig drain */
13404                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13405                 /* Set LED mode to off since the PHY doesn't know about these
13406                  * errors
13407                  */
13408                 led_mode = LED_MODE_OFF;
13409         } else {
13410                 vars->link_status |= LINK_STATUS_LINK_UP;
13411                 vars->link_status &= ~link_flag;
13412                 vars->link_up = 1;
13413                 vars->phy_flags &= ~phy_flag;
13414                 led_mode = LED_MODE_OPER;
13415
13416                 /* Clear nig drain */
13417                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13418         }
13419         bnx2x_sync_link(params, vars);
13420         /* Update the LED according to the link state */
13421         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13422
13423         /* Update link status in the shared memory */
13424         bnx2x_update_mng(params, vars->link_status);
13425
13426         /* C. Trigger General Attention */
13427         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13428         if (notify)
13429                 bnx2x_notify_link_changed(bp);
13430
13431         return 1;
13432 }
13433
13434 /******************************************************************************
13435 * Description:
13436 *       This function checks for half opened connection change indication.
13437 *       When such change occurs, it calls the bnx2x_analyze_link_error
13438 *       to check if Remote Fault is set or cleared. Reception of remote fault
13439 *       status message in the MAC indicates that the peer's MAC has detected
13440 *       a fault, for example, due to break in the TX side of fiber.
13441 *
13442 ******************************************************************************/
13443 static int bnx2x_check_half_open_conn(struct link_params *params,
13444                                       struct link_vars *vars,
13445                                       u8 notify)
13446 {
13447         struct bnx2x *bp = params->bp;
13448         u32 lss_status = 0;
13449         u32 mac_base;
13450         /* In case link status is physically up @ 10G do */
13451         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13452             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13453                 return 0;
13454
13455         if (CHIP_IS_E3(bp) &&
13456             (REG_RD(bp, MISC_REG_RESET_REG_2) &
13457               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13458                 /* Check E3 XMAC */
13459                 /* Note that link speed cannot be queried here, since it may be
13460                  * zero while link is down. In case UMAC is active, LSS will
13461                  * simply not be set
13462                  */
13463                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13464
13465                 /* Clear stick bits (Requires rising edge) */
13466                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13467                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13468                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13469                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13470                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13471                         lss_status = 1;
13472
13473                 bnx2x_analyze_link_error(params, vars, lss_status,
13474                                          PHY_HALF_OPEN_CONN_FLAG,
13475                                          LINK_STATUS_NONE, notify);
13476         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13477                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13478                 /* Check E1X / E2 BMAC */
13479                 u32 lss_status_reg;
13480                 u32 wb_data[2];
13481                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13482                         NIG_REG_INGRESS_BMAC0_MEM;
13483                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
13484                 if (CHIP_IS_E2(bp))
13485                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13486                 else
13487                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13488
13489                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13490                 lss_status = (wb_data[0] > 0);
13491
13492                 bnx2x_analyze_link_error(params, vars, lss_status,
13493                                          PHY_HALF_OPEN_CONN_FLAG,
13494                                          LINK_STATUS_NONE, notify);
13495         }
13496         return 0;
13497 }
13498 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13499                                          struct link_params *params,
13500                                          struct link_vars *vars)
13501 {
13502         struct bnx2x *bp = params->bp;
13503         u32 cfg_pin, value = 0;
13504         u8 led_change, port = params->port;
13505
13506         /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13507         cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13508                           dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13509                    PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13510                   PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13511
13512         if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13513                 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13514                 return;
13515         }
13516
13517         led_change = bnx2x_analyze_link_error(params, vars, value,
13518                                               PHY_SFP_TX_FAULT_FLAG,
13519                                               LINK_STATUS_SFP_TX_FAULT, 1);
13520
13521         if (led_change) {
13522                 /* Change TX_Fault led, set link status for further syncs */
13523                 u8 led_mode;
13524
13525                 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13526                         led_mode = MISC_REGISTERS_GPIO_HIGH;
13527                         vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13528                 } else {
13529                         led_mode = MISC_REGISTERS_GPIO_LOW;
13530                         vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13531                 }
13532
13533                 /* If module is unapproved, led should be on regardless */
13534                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13535                         DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13536                            led_mode);
13537                         bnx2x_set_e3_module_fault_led(params, led_mode);
13538                 }
13539         }
13540 }
13541 static void bnx2x_kr2_recovery(struct link_params *params,
13542                                struct link_vars *vars,
13543                                struct bnx2x_phy *phy)
13544 {
13545         struct bnx2x *bp = params->bp;
13546         DP(NETIF_MSG_LINK, "KR2 recovery\n");
13547         bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13548         bnx2x_warpcore_restart_AN_KR(phy, params);
13549 }
13550
13551 static void bnx2x_check_kr2_wa(struct link_params *params,
13552                                struct link_vars *vars,
13553                                struct bnx2x_phy *phy)
13554 {
13555         struct bnx2x *bp = params->bp;
13556         u16 base_page, next_page, not_kr2_device, lane;
13557         int sigdet;
13558
13559         /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13560          * Since some switches tend to reinit the AN process and clear the
13561          * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13562          * and recovered many times
13563          */
13564         if (vars->check_kr2_recovery_cnt > 0) {
13565                 vars->check_kr2_recovery_cnt--;
13566                 return;
13567         }
13568
13569         sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13570         if (!sigdet) {
13571                 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13572                         bnx2x_kr2_recovery(params, vars, phy);
13573                         DP(NETIF_MSG_LINK, "No sigdet\n");
13574                 }
13575                 return;
13576         }
13577
13578         lane = bnx2x_get_warpcore_lane(phy, params);
13579         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13580                           MDIO_AER_BLOCK_AER_REG, lane);
13581         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13582                         MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13583         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13584                         MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13585         bnx2x_set_aer_mmd(params, phy);
13586
13587         /* CL73 has not begun yet */
13588         if (base_page == 0) {
13589                 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13590                         bnx2x_kr2_recovery(params, vars, phy);
13591                         DP(NETIF_MSG_LINK, "No BP\n");
13592                 }
13593                 return;
13594         }
13595
13596         /* In case NP bit is not set in the BasePage, or it is set,
13597          * but only KX is advertised, declare this link partner as non-KR2
13598          * device.
13599          */
13600         not_kr2_device = (((base_page & 0x8000) == 0) ||
13601                           (((base_page & 0x8000) &&
13602                             ((next_page & 0xe0) == 0x20))));
13603
13604         /* In case KR2 is already disabled, check if we need to re-enable it */
13605         if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13606                 if (!not_kr2_device) {
13607                         DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13608                            next_page);
13609                         bnx2x_kr2_recovery(params, vars, phy);
13610                 }
13611                 return;
13612         }
13613         /* KR2 is enabled, but not KR2 device */
13614         if (not_kr2_device) {
13615                 /* Disable KR2 on both lanes */
13616                 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13617                 bnx2x_disable_kr2(params, vars, phy);
13618                 /* Restart AN on leading lane */
13619                 bnx2x_warpcore_restart_AN_KR(phy, params);
13620                 return;
13621         }
13622 }
13623
13624 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13625 {
13626         u16 phy_idx;
13627         struct bnx2x *bp = params->bp;
13628         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13629                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13630                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
13631                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
13632                             0)
13633                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13634                         break;
13635                 }
13636         }
13637
13638         if (CHIP_IS_E3(bp)) {
13639                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13640                 bnx2x_set_aer_mmd(params, phy);
13641                 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
13642                     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
13643                         bnx2x_check_kr2_wa(params, vars, phy);
13644                 bnx2x_check_over_curr(params, vars);
13645                 if (vars->rx_tx_asic_rst)
13646                         bnx2x_warpcore_config_runtime(phy, params, vars);
13647
13648                 if ((REG_RD(bp, params->shmem_base +
13649                             offsetof(struct shmem_region, dev_info.
13650                                 port_hw_config[params->port].default_cfg))
13651                     & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13652                     PORT_HW_CFG_NET_SERDES_IF_SFI) {
13653                         if (bnx2x_is_sfp_module_plugged(phy, params)) {
13654                                 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13655                         } else if (vars->link_status &
13656                                 LINK_STATUS_SFP_TX_FAULT) {
13657                                 /* Clean trail, interrupt corrects the leds */
13658                                 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13659                                 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13660                                 /* Update link status in the shared memory */
13661                                 bnx2x_update_mng(params, vars->link_status);
13662                         }
13663                 }
13664         }
13665 }
13666
13667 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13668                              u32 shmem_base,
13669                              u32 shmem2_base,
13670                              u8 port)
13671 {
13672         u8 phy_index, fan_failure_det_req = 0;
13673         struct bnx2x_phy phy;
13674         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13675               phy_index++) {
13676                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13677                                        port, &phy)
13678                     != 0) {
13679                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13680                         return 0;
13681                 }
13682                 fan_failure_det_req |= (phy.flags &
13683                                         FLAGS_FAN_FAILURE_DET_REQ);
13684         }
13685         return fan_failure_det_req;
13686 }
13687
13688 void bnx2x_hw_reset_phy(struct link_params *params)
13689 {
13690         u8 phy_index;
13691         struct bnx2x *bp = params->bp;
13692         bnx2x_update_mng(params, 0);
13693         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13694                        (NIG_MASK_XGXS0_LINK_STATUS |
13695                         NIG_MASK_XGXS0_LINK10G |
13696                         NIG_MASK_SERDES0_LINK_STATUS |
13697                         NIG_MASK_MI_INT));
13698
13699         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13700               phy_index++) {
13701                 if (params->phy[phy_index].hw_reset) {
13702                         params->phy[phy_index].hw_reset(
13703                                 &params->phy[phy_index],
13704                                 params);
13705                         params->phy[phy_index] = phy_null;
13706                 }
13707         }
13708 }
13709
13710 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13711                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
13712                             u8 port)
13713 {
13714         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13715         u32 val;
13716         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13717         if (CHIP_IS_E3(bp)) {
13718                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13719                                               shmem_base,
13720                                               port,
13721                                               &gpio_num,
13722                                               &gpio_port) != 0)
13723                         return;
13724         } else {
13725                 struct bnx2x_phy phy;
13726                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13727                       phy_index++) {
13728                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13729                                                shmem2_base, port, &phy)
13730                             != 0) {
13731                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
13732                                 return;
13733                         }
13734                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13735                                 gpio_num = MISC_REGISTERS_GPIO_3;
13736                                 gpio_port = port;
13737                                 break;
13738                         }
13739                 }
13740         }
13741
13742         if (gpio_num == 0xff)
13743                 return;
13744
13745         /* Set GPIO3 to trigger SFP+ module insertion/removal */
13746         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13747
13748         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13749         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13750         gpio_port ^= (swap_val && swap_override);
13751
13752         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13753                 (gpio_num + (gpio_port << 2));
13754
13755         sync_offset = shmem_base +
13756                 offsetof(struct shmem_region,
13757                          dev_info.port_hw_config[port].aeu_int_mask);
13758         REG_WR(bp, sync_offset, vars->aeu_int_mask);
13759
13760         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13761                        gpio_num, gpio_port, vars->aeu_int_mask);
13762
13763         if (port == 0)
13764                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13765         else
13766                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13767
13768         /* Open appropriate AEU for interrupts */
13769         aeu_mask = REG_RD(bp, offset);
13770         aeu_mask |= vars->aeu_int_mask;
13771         REG_WR(bp, offset, aeu_mask);
13772
13773         /* Enable the GPIO to trigger interrupt */
13774         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13775         val |= 1 << (gpio_num + (gpio_port << 2));
13776         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13777 }