kernel/drivers/net/can/c_can/c_can.h

   1 /*
   2  * CAN bus driver for Bosch C_CAN controller
   3  *
   4  * Copyright (C) 2010 ST Microelectronics
   5  * Bhupesh Sharma <bhupesh.sharma@st.com>
   6  *
   7  * Borrowed heavily from the C_CAN driver originally written by:
   8  * Copyright (C) 2007
   9  * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
  10  * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
  11  *
  12  * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
  13  * Bosch C_CAN user manual can be obtained from:
  14  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
  15  * users_manual_c_can.pdf
  16  *
  17  * This file is licensed under the terms of the GNU General Public
  18  * License version 2. This program is licensed "as is" without any
  19  * warranty of any kind, whether express or implied.
  20  */
  21
  22 #ifndef C_CAN_H
  23 #define C_CAN_H
  24
  25 /* message object split */
  26 #define C_CAN_NO_OF_OBJECTS     32
  27 #define C_CAN_MSG_OBJ_RX_NUM    16
  28 #define C_CAN_MSG_OBJ_TX_NUM    16
  29
  30 #define C_CAN_MSG_OBJ_RX_FIRST  1
  31 #define C_CAN_MSG_OBJ_RX_LAST   (C_CAN_MSG_OBJ_RX_FIRST + \
  32                                 C_CAN_MSG_OBJ_RX_NUM - 1)
  33
  34 #define C_CAN_MSG_OBJ_TX_FIRST  (C_CAN_MSG_OBJ_RX_LAST + 1)
  35 #define C_CAN_MSG_OBJ_TX_LAST   (C_CAN_MSG_OBJ_TX_FIRST + \
  36                                 C_CAN_MSG_OBJ_TX_NUM - 1)
  37
  38 #define C_CAN_MSG_OBJ_RX_SPLIT  9
  39 #define C_CAN_MSG_RX_LOW_LAST   (C_CAN_MSG_OBJ_RX_SPLIT - 1)
  40 #define RECEIVE_OBJECT_BITS     0x0000ffff
  41
  42 enum reg {
  43         C_CAN_CTRL_REG = 0,
  44         C_CAN_CTRL_EX_REG,
  45         C_CAN_STS_REG,
  46         C_CAN_ERR_CNT_REG,
  47         C_CAN_BTR_REG,
  48         C_CAN_INT_REG,
  49         C_CAN_TEST_REG,
  50         C_CAN_BRPEXT_REG,
  51         C_CAN_IF1_COMREQ_REG,
  52         C_CAN_IF1_COMMSK_REG,
  53         C_CAN_IF1_MASK1_REG,
  54         C_CAN_IF1_MASK2_REG,
  55         C_CAN_IF1_ARB1_REG,
  56         C_CAN_IF1_ARB2_REG,
  57         C_CAN_IF1_MSGCTRL_REG,
  58         C_CAN_IF1_DATA1_REG,
  59         C_CAN_IF1_DATA2_REG,
  60         C_CAN_IF1_DATA3_REG,
  61         C_CAN_IF1_DATA4_REG,
  62         C_CAN_IF2_COMREQ_REG,
  63         C_CAN_IF2_COMMSK_REG,
  64         C_CAN_IF2_MASK1_REG,
  65         C_CAN_IF2_MASK2_REG,
  66         C_CAN_IF2_ARB1_REG,
  67         C_CAN_IF2_ARB2_REG,
  68         C_CAN_IF2_MSGCTRL_REG,
  69         C_CAN_IF2_DATA1_REG,
  70         C_CAN_IF2_DATA2_REG,
  71         C_CAN_IF2_DATA3_REG,
  72         C_CAN_IF2_DATA4_REG,
  73         C_CAN_TXRQST1_REG,
  74         C_CAN_TXRQST2_REG,
  75         C_CAN_NEWDAT1_REG,
  76         C_CAN_NEWDAT2_REG,
  77         C_CAN_INTPND1_REG,
  78         C_CAN_INTPND2_REG,
  79         C_CAN_MSGVAL1_REG,
  80         C_CAN_MSGVAL2_REG,
  81         C_CAN_FUNCTION_REG,
  82 };
  83
  84 static const u16 reg_map_c_can[] = {
  85         [C_CAN_CTRL_REG]        = 0x00,
  86         [C_CAN_STS_REG]         = 0x02,
  87         [C_CAN_ERR_CNT_REG]     = 0x04,
  88         [C_CAN_BTR_REG]         = 0x06,
  89         [C_CAN_INT_REG]         = 0x08,
  90         [C_CAN_TEST_REG]        = 0x0A,
  91         [C_CAN_BRPEXT_REG]      = 0x0C,
  92         [C_CAN_IF1_COMREQ_REG]  = 0x10,
  93         [C_CAN_IF1_COMMSK_REG]  = 0x12,
  94         [C_CAN_IF1_MASK1_REG]   = 0x14,
  95         [C_CAN_IF1_MASK2_REG]   = 0x16,
  96         [C_CAN_IF1_ARB1_REG]    = 0x18,
  97         [C_CAN_IF1_ARB2_REG]    = 0x1A,
  98         [C_CAN_IF1_MSGCTRL_REG] = 0x1C,
  99         [C_CAN_IF1_DATA1_REG]   = 0x1E,
 100         [C_CAN_IF1_DATA2_REG]   = 0x20,
 101         [C_CAN_IF1_DATA3_REG]   = 0x22,
 102         [C_CAN_IF1_DATA4_REG]   = 0x24,
 103         [C_CAN_IF2_COMREQ_REG]  = 0x40,
 104         [C_CAN_IF2_COMMSK_REG]  = 0x42,
 105         [C_CAN_IF2_MASK1_REG]   = 0x44,
 106         [C_CAN_IF2_MASK2_REG]   = 0x46,
 107         [C_CAN_IF2_ARB1_REG]    = 0x48,
 108         [C_CAN_IF2_ARB2_REG]    = 0x4A,
 109         [C_CAN_IF2_MSGCTRL_REG] = 0x4C,
 110         [C_CAN_IF2_DATA1_REG]   = 0x4E,
 111         [C_CAN_IF2_DATA2_REG]   = 0x50,
 112         [C_CAN_IF2_DATA3_REG]   = 0x52,
 113         [C_CAN_IF2_DATA4_REG]   = 0x54,
 114         [C_CAN_TXRQST1_REG]     = 0x80,
 115         [C_CAN_TXRQST2_REG]     = 0x82,
 116         [C_CAN_NEWDAT1_REG]     = 0x90,
 117         [C_CAN_NEWDAT2_REG]     = 0x92,
 118         [C_CAN_INTPND1_REG]     = 0xA0,
 119         [C_CAN_INTPND2_REG]     = 0xA2,
 120         [C_CAN_MSGVAL1_REG]     = 0xB0,
 121         [C_CAN_MSGVAL2_REG]     = 0xB2,
 122 };
 123
 124 static const u16 reg_map_d_can[] = {
 125         [C_CAN_CTRL_REG]        = 0x00,
 126         [C_CAN_CTRL_EX_REG]     = 0x02,
 127         [C_CAN_STS_REG]         = 0x04,
 128         [C_CAN_ERR_CNT_REG]     = 0x08,
 129         [C_CAN_BTR_REG]         = 0x0C,
 130         [C_CAN_BRPEXT_REG]      = 0x0E,
 131         [C_CAN_INT_REG]         = 0x10,
 132         [C_CAN_TEST_REG]        = 0x14,
 133         [C_CAN_FUNCTION_REG]    = 0x18,
 134         [C_CAN_TXRQST1_REG]     = 0x88,
 135         [C_CAN_TXRQST2_REG]     = 0x8A,
 136         [C_CAN_NEWDAT1_REG]     = 0x9C,
 137         [C_CAN_NEWDAT2_REG]     = 0x9E,
 138         [C_CAN_INTPND1_REG]     = 0xB0,
 139         [C_CAN_INTPND2_REG]     = 0xB2,
 140         [C_CAN_MSGVAL1_REG]     = 0xC4,
 141         [C_CAN_MSGVAL2_REG]     = 0xC6,
 142         [C_CAN_IF1_COMREQ_REG]  = 0x100,
 143         [C_CAN_IF1_COMMSK_REG]  = 0x102,
 144         [C_CAN_IF1_MASK1_REG]   = 0x104,
 145         [C_CAN_IF1_MASK2_REG]   = 0x106,
 146         [C_CAN_IF1_ARB1_REG]    = 0x108,
 147         [C_CAN_IF1_ARB2_REG]    = 0x10A,
 148         [C_CAN_IF1_MSGCTRL_REG] = 0x10C,
 149         [C_CAN_IF1_DATA1_REG]   = 0x110,
 150         [C_CAN_IF1_DATA2_REG]   = 0x112,
 151         [C_CAN_IF1_DATA3_REG]   = 0x114,
 152         [C_CAN_IF1_DATA4_REG]   = 0x116,
 153         [C_CAN_IF2_COMREQ_REG]  = 0x120,
 154         [C_CAN_IF2_COMMSK_REG]  = 0x122,
 155         [C_CAN_IF2_MASK1_REG]   = 0x124,
 156         [C_CAN_IF2_MASK2_REG]   = 0x126,
 157         [C_CAN_IF2_ARB1_REG]    = 0x128,
 158         [C_CAN_IF2_ARB2_REG]    = 0x12A,
 159         [C_CAN_IF2_MSGCTRL_REG] = 0x12C,
 160         [C_CAN_IF2_DATA1_REG]   = 0x130,
 161         [C_CAN_IF2_DATA2_REG]   = 0x132,
 162         [C_CAN_IF2_DATA3_REG]   = 0x134,
 163         [C_CAN_IF2_DATA4_REG]   = 0x136,
 164 };
 165
 166 enum c_can_dev_id {
 167         BOSCH_C_CAN_PLATFORM,
 168         BOSCH_C_CAN,
 169         BOSCH_D_CAN,
 170 };
 171
 172 struct raminit_bits {
 173         u8 start;
 174         u8 done;
 175 };
 176
 177 struct c_can_driver_data {
 178         enum c_can_dev_id id;
 179
 180         /* RAMINIT register description. Optional. */
 181         const struct raminit_bits *raminit_bits; /* Array of START/DONE bit positions */
 182         u8 raminit_num;         /* Number of CAN instances on the SoC */
 183         bool raminit_pulse;     /* If set, sets and clears START bit (pulse) */
 184 };
 185
 186 /* Out of band RAMINIT register access via syscon regmap */
 187 struct c_can_raminit {
 188         struct regmap *syscon;  /* for raminit ctrl. reg. access */
 189         unsigned int reg;       /* register index within syscon */
 190         struct raminit_bits bits;
 191         bool needs_pulse;
 192 };
 193
 194 /* c_can private data structure */
 195 struct c_can_priv {
 196         struct can_priv can;    /* must be the first member */
 197         struct napi_struct napi;
 198         struct net_device *dev;
 199         struct device *device;
 200         atomic_t tx_active;
 201         unsigned long tx_dir;
 202         int last_status;
 203         u16 (*read_reg) (const struct c_can_priv *priv, enum reg index);
 204         void (*write_reg) (const struct c_can_priv *priv, enum reg index, u16 val);
 205         u32 (*read_reg32) (const struct c_can_priv *priv, enum reg index);
 206         void (*write_reg32) (const struct c_can_priv *priv, enum reg index, u32 val);
 207         void __iomem *base;
 208         const u16 *regs;
 209         void *priv;             /* for board-specific data */
 210         enum c_can_dev_id type;
 211         struct c_can_raminit raminit_sys;       /* RAMINIT via syscon regmap */
 212         void (*raminit) (const struct c_can_priv *priv, bool enable);
 213         u32 comm_rcv_high;
 214         u32 rxmasked;
 215         u32 dlc[C_CAN_MSG_OBJ_TX_NUM];
 216 };
 217
 218 struct net_device *alloc_c_can_dev(void);
 219 void free_c_can_dev(struct net_device *dev);
 220 int register_c_can_dev(struct net_device *dev);
 221 void unregister_c_can_dev(struct net_device *dev);
 222
 223 #ifdef CONFIG_PM
 224 int c_can_power_up(struct net_device *dev);
 225 int c_can_power_down(struct net_device *dev);
 226 #endif
 227
 228 #endif /* C_CAN_H */