kernel/drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *
   8  *      Additional technical information is available on
   9  *      http://www.linux-mtd.infradead.org/doc/nand.html
  10  *
  11  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  12  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  13  *
  14  *  Credits:
  15  *      David Woodhouse for adding multichip support
  16  *
  17  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  18  *      rework for 2K page size chips
  19  *
  20  *  TODO:
  21  *      Enable cached programming for 2k page size chips
  22  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  23  *      if we have HW ECC support.
  24  *      BBT table is not serialized, has to be fixed
  25  *
  26  * This program is free software; you can redistribute it and/or modify
  27  * it under the terms of the GNU General Public License version 2 as
  28  * published by the Free Software Foundation.
  29  *
  30  */
  31
  32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  33
  34 #include <linux/module.h>
  35 #include <linux/delay.h>
  36 #include <linux/errno.h>
  37 #include <linux/err.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/mm.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/nand_bch.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <linux/io.h>
  50 #include <linux/mtd/partitions.h>
  51
  52 /* Define default oob placement schemes for large and small page devices */
  53 static struct nand_ecclayout nand_oob_8 = {
  54         .eccbytes = 3,
  55         .eccpos = {0, 1, 2},
  56         .oobfree = {
  57                 {.offset = 3,
  58                  .length = 2},
  59                 {.offset = 6,
  60                  .length = 2} }
  61 };
  62
  63 static struct nand_ecclayout nand_oob_16 = {
  64         .eccbytes = 6,
  65         .eccpos = {0, 1, 2, 3, 6, 7},
  66         .oobfree = {
  67                 {.offset = 8,
  68                  . length = 8} }
  69 };
  70
  71 static struct nand_ecclayout nand_oob_64 = {
  72         .eccbytes = 24,
  73         .eccpos = {
  74                    40, 41, 42, 43, 44, 45, 46, 47,
  75                    48, 49, 50, 51, 52, 53, 54, 55,
  76                    56, 57, 58, 59, 60, 61, 62, 63},
  77         .oobfree = {
  78                 {.offset = 2,
  79                  .length = 38} }
  80 };
  81
  82 static struct nand_ecclayout nand_oob_128 = {
  83         .eccbytes = 48,
  84         .eccpos = {
  85                    80, 81, 82, 83, 84, 85, 86, 87,
  86                    88, 89, 90, 91, 92, 93, 94, 95,
  87                    96, 97, 98, 99, 100, 101, 102, 103,
  88                    104, 105, 106, 107, 108, 109, 110, 111,
  89                    112, 113, 114, 115, 116, 117, 118, 119,
  90                    120, 121, 122, 123, 124, 125, 126, 127},
  91         .oobfree = {
  92                 {.offset = 2,
  93                  .length = 78} }
  94 };
  95
  96 static int nand_get_device(struct mtd_info *mtd, int new_state);
  97
  98 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  99                              struct mtd_oob_ops *ops);
 100
 101 /*
 102  * For devices which display every fart in the system on a separate LED. Is
 103  * compiled away when LED support is disabled.
 104  */
 105 DEFINE_LED_TRIGGER(nand_led_trigger);
 106
 107 static int check_offs_len(struct mtd_info *mtd,
 108                                         loff_t ofs, uint64_t len)
 109 {
 110         struct nand_chip *chip = mtd->priv;
 111         int ret = 0;
 112
 113         /* Start address must align on block boundary */
 114         if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
 115                 pr_debug("%s: unaligned address\n", __func__);
 116                 ret = -EINVAL;
 117         }
 118
 119         /* Length must align on block boundary */
 120         if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
 121                 pr_debug("%s: length not block aligned\n", __func__);
 122                 ret = -EINVAL;
 123         }
 124
 125         return ret;
 126 }
 127
 128 /**
 129  * nand_release_device - [GENERIC] release chip
 130  * @mtd: MTD device structure
 131  *
 132  * Release chip lock and wake up anyone waiting on the device.
 133  */
 134 static void nand_release_device(struct mtd_info *mtd)
 135 {
 136         struct nand_chip *chip = mtd->priv;
 137
 138         /* Release the controller and the chip */
 139         spin_lock(&chip->controller->lock);
 140         chip->controller->active = NULL;
 141         chip->state = FL_READY;
 142         wake_up(&chip->controller->wq);
 143         spin_unlock(&chip->controller->lock);
 144 }
 145
 146 /**
 147  * nand_read_byte - [DEFAULT] read one byte from the chip
 148  * @mtd: MTD device structure
 149  *
 150  * Default read function for 8bit buswidth
 151  */
 152 static uint8_t nand_read_byte(struct mtd_info *mtd)
 153 {
 154         struct nand_chip *chip = mtd->priv;
 155         return readb(chip->IO_ADDR_R);
 156 }
 157
 158 /**
 159  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 160  * @mtd: MTD device structure
 161  *
 162  * Default read function for 16bit buswidth with endianness conversion.
 163  *
 164  */
 165 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 166 {
 167         struct nand_chip *chip = mtd->priv;
 168         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 169 }
 170
 171 /**
 172  * nand_read_word - [DEFAULT] read one word from the chip
 173  * @mtd: MTD device structure
 174  *
 175  * Default read function for 16bit buswidth without endianness conversion.
 176  */
 177 static u16 nand_read_word(struct mtd_info *mtd)
 178 {
 179         struct nand_chip *chip = mtd->priv;
 180         return readw(chip->IO_ADDR_R);
 181 }
 182
 183 /**
 184  * nand_select_chip - [DEFAULT] control CE line
 185  * @mtd: MTD device structure
 186  * @chipnr: chipnumber to select, -1 for deselect
 187  *
 188  * Default select function for 1 chip devices.
 189  */
 190 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 191 {
 192         struct nand_chip *chip = mtd->priv;
 193
 194         switch (chipnr) {
 195         case -1:
 196                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 197                 break;
 198         case 0:
 199                 break;
 200
 201         default:
 202                 BUG();
 203         }
 204 }
 205
 206 /**
 207  * nand_write_byte - [DEFAULT] write single byte to chip
 208  * @mtd: MTD device structure
 209  * @byte: value to write
 210  *
 211  * Default function to write a byte to I/O[7:0]
 212  */
 213 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
 214 {
 215         struct nand_chip *chip = mtd->priv;
 216
 217         chip->write_buf(mtd, &byte, 1);
 218 }
 219
 220 /**
 221  * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
 222  * @mtd: MTD device structure
 223  * @byte: value to write
 224  *
 225  * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
 226  */
 227 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
 228 {
 229         struct nand_chip *chip = mtd->priv;
 230         uint16_t word = byte;
 231
 232         /*
 233          * It's not entirely clear what should happen to I/O[15:8] when writing
 234          * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
 235          *
 236          *    When the host supports a 16-bit bus width, only data is
 237          *    transferred at the 16-bit width. All address and command line
 238          *    transfers shall use only the lower 8-bits of the data bus. During
 239          *    command transfers, the host may place any value on the upper
 240          *    8-bits of the data bus. During address transfers, the host shall
 241          *    set the upper 8-bits of the data bus to 00h.
 242          *
 243          * One user of the write_byte callback is nand_onfi_set_features. The
 244          * four parameters are specified to be written to I/O[7:0], but this is
 245          * neither an address nor a command transfer. Let's assume a 0 on the
 246          * upper I/O lines is OK.
 247          */
 248         chip->write_buf(mtd, (uint8_t *)&word, 2);
 249 }
 250
 251 /**
 252  * nand_write_buf - [DEFAULT] write buffer to chip
 253  * @mtd: MTD device structure
 254  * @buf: data buffer
 255  * @len: number of bytes to write
 256  *
 257  * Default write function for 8bit buswidth.
 258  */
 259 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 260 {
 261         struct nand_chip *chip = mtd->priv;
 262
 263         iowrite8_rep(chip->IO_ADDR_W, buf, len);
 264 }
 265
 266 /**
 267  * nand_read_buf - [DEFAULT] read chip data into buffer
 268  * @mtd: MTD device structure
 269  * @buf: buffer to store date
 270  * @len: number of bytes to read
 271  *
 272  * Default read function for 8bit buswidth.
 273  */
 274 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 275 {
 276         struct nand_chip *chip = mtd->priv;
 277
 278         ioread8_rep(chip->IO_ADDR_R, buf, len);
 279 }
 280
 281 /**
 282  * nand_write_buf16 - [DEFAULT] write buffer to chip
 283  * @mtd: MTD device structure
 284  * @buf: data buffer
 285  * @len: number of bytes to write
 286  *
 287  * Default write function for 16bit buswidth.
 288  */
 289 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 290 {
 291         struct nand_chip *chip = mtd->priv;
 292         u16 *p = (u16 *) buf;
 293
 294         iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
 295 }
 296
 297 /**
 298  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 299  * @mtd: MTD device structure
 300  * @buf: buffer to store date
 301  * @len: number of bytes to read
 302  *
 303  * Default read function for 16bit buswidth.
 304  */
 305 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 306 {
 307         struct nand_chip *chip = mtd->priv;
 308         u16 *p = (u16 *) buf;
 309
 310         ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
 311 }
 312
 313 /**
 314  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 315  * @mtd: MTD device structure
 316  * @ofs: offset from device start
 317  * @getchip: 0, if the chip is already selected
 318  *
 319  * Check, if the block is bad.
 320  */
 321 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 322 {
 323         int page, chipnr, res = 0, i = 0;
 324         struct nand_chip *chip = mtd->priv;
 325         u16 bad;
 326
 327         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 328                 ofs += mtd->erasesize - mtd->writesize;
 329
 330         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 331
 332         if (getchip) {
 333                 chipnr = (int)(ofs >> chip->chip_shift);
 334
 335                 nand_get_device(mtd, FL_READING);
 336
 337                 /* Select the NAND device */
 338                 chip->select_chip(mtd, chipnr);
 339         }
 340
 341         do {
 342                 if (chip->options & NAND_BUSWIDTH_16) {
 343                         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 344                                         chip->badblockpos & 0xFE, page);
 345                         bad = cpu_to_le16(chip->read_word(mtd));
 346                         if (chip->badblockpos & 0x1)
 347                                 bad >>= 8;
 348                         else
 349                                 bad &= 0xFF;
 350                 } else {
 351                         chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
 352                                         page);
 353                         bad = chip->read_byte(mtd);
 354                 }
 355
 356                 if (likely(chip->badblockbits == 8))
 357                         res = bad != 0xFF;
 358                 else
 359                         res = hweight8(bad) < chip->badblockbits;
 360                 ofs += mtd->writesize;
 361                 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 362                 i++;
 363         } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
 364
 365         if (getchip) {
 366                 chip->select_chip(mtd, -1);
 367                 nand_release_device(mtd);
 368         }
 369
 370         return res;
 371 }
 372
 373 /**
 374  * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
 375  * @mtd: MTD device structure
 376  * @ofs: offset from device start
 377  *
 378  * This is the default implementation, which can be overridden by a hardware
 379  * specific driver. It provides the details for writing a bad block marker to a
 380  * block.
 381  */
 382 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 383 {
 384         struct nand_chip *chip = mtd->priv;
 385         struct mtd_oob_ops ops;
 386         uint8_t buf[2] = { 0, 0 };
 387         int ret = 0, res, i = 0;
 388
 389         memset(&ops, 0, sizeof(ops));
 390         ops.oobbuf = buf;
 391         ops.ooboffs = chip->badblockpos;
 392         if (chip->options & NAND_BUSWIDTH_16) {
 393                 ops.ooboffs &= ~0x01;
 394                 ops.len = ops.ooblen = 2;
 395         } else {
 396                 ops.len = ops.ooblen = 1;
 397         }
 398         ops.mode = MTD_OPS_PLACE_OOB;
 399
 400         /* Write to first/last page(s) if necessary */
 401         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 402                 ofs += mtd->erasesize - mtd->writesize;
 403         do {
 404                 res = nand_do_write_oob(mtd, ofs, &ops);
 405                 if (!ret)
 406                         ret = res;
 407
 408                 i++;
 409                 ofs += mtd->writesize;
 410         } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
 411
 412         return ret;
 413 }
 414
 415 /**
 416  * nand_block_markbad_lowlevel - mark a block bad
 417  * @mtd: MTD device structure
 418  * @ofs: offset from device start
 419  *
 420  * This function performs the generic NAND bad block marking steps (i.e., bad
 421  * block table(s) and/or marker(s)). We only allow the hardware driver to
 422  * specify how to write bad block markers to OOB (chip->block_markbad).
 423  *
 424  * We try operations in the following order:
 425  *  (1) erase the affected block, to allow OOB marker to be written cleanly
 426  *  (2) write bad block marker to OOB area of affected block (unless flag
 427  *      NAND_BBT_NO_OOB_BBM is present)
 428  *  (3) update the BBT
 429  * Note that we retain the first error encountered in (2) or (3), finish the
 430  * procedures, and dump the error in the end.
 431 */
 432 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
 433 {
 434         struct nand_chip *chip = mtd->priv;
 435         int res, ret = 0;
 436
 437         if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
 438                 struct erase_info einfo;
 439
 440                 /* Attempt erase before marking OOB */
 441                 memset(&einfo, 0, sizeof(einfo));
 442                 einfo.mtd = mtd;
 443                 einfo.addr = ofs;
 444                 einfo.len = 1ULL << chip->phys_erase_shift;
 445                 nand_erase_nand(mtd, &einfo, 0);
 446
 447                 /* Write bad block marker to OOB */
 448                 nand_get_device(mtd, FL_WRITING);
 449                 ret = chip->block_markbad(mtd, ofs);
 450                 nand_release_device(mtd);
 451         }
 452
 453         /* Mark block bad in BBT */
 454         if (chip->bbt) {
 455                 res = nand_markbad_bbt(mtd, ofs);
 456                 if (!ret)
 457                         ret = res;
 458         }
 459
 460         if (!ret)
 461                 mtd->ecc_stats.badblocks++;
 462
 463         return ret;
 464 }
 465
 466 /**
 467  * nand_check_wp - [GENERIC] check if the chip is write protected
 468  * @mtd: MTD device structure
 469  *
 470  * Check, if the device is write protected. The function expects, that the
 471  * device is already selected.
 472  */
 473 static int nand_check_wp(struct mtd_info *mtd)
 474 {
 475         struct nand_chip *chip = mtd->priv;
 476
 477         /* Broken xD cards report WP despite being writable */
 478         if (chip->options & NAND_BROKEN_XD)
 479                 return 0;
 480
 481         /* Check the WP bit */
 482         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 483         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 484 }
 485
 486 /**
 487  * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
 488  * @mtd: MTD device structure
 489  * @ofs: offset from device start
 490  *
 491  * Check if the block is marked as reserved.
 492  */
 493 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
 494 {
 495         struct nand_chip *chip = mtd->priv;
 496
 497         if (!chip->bbt)
 498                 return 0;
 499         /* Return info from the table */
 500         return nand_isreserved_bbt(mtd, ofs);
 501 }
 502
 503 /**
 504  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 505  * @mtd: MTD device structure
 506  * @ofs: offset from device start
 507  * @getchip: 0, if the chip is already selected
 508  * @allowbbt: 1, if its allowed to access the bbt area
 509  *
 510  * Check, if the block is bad. Either by reading the bad block table or
 511  * calling of the scan function.
 512  */
 513 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 514                                int allowbbt)
 515 {
 516         struct nand_chip *chip = mtd->priv;
 517
 518         if (!chip->bbt)
 519                 return chip->block_bad(mtd, ofs, getchip);
 520
 521         /* Return info from the table */
 522         return nand_isbad_bbt(mtd, ofs, allowbbt);
 523 }
 524
 525 /**
 526  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 527  * @mtd: MTD device structure
 528  * @timeo: Timeout
 529  *
 530  * Helper function for nand_wait_ready used when needing to wait in interrupt
 531  * context.
 532  */
 533 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 534 {
 535         struct nand_chip *chip = mtd->priv;
 536         int i;
 537
 538         /* Wait for the device to get ready */
 539         for (i = 0; i < timeo; i++) {
 540                 if (chip->dev_ready(mtd))
 541                         break;
 542                 touch_softlockup_watchdog();
 543                 mdelay(1);
 544         }
 545 }
 546
 547 /* Wait for the ready pin, after a command. The timeout is caught later. */
 548 void nand_wait_ready(struct mtd_info *mtd)
 549 {
 550         struct nand_chip *chip = mtd->priv;
 551         unsigned long timeo = jiffies + msecs_to_jiffies(20);
 552
 553         /* 400ms timeout */
 554         if (in_interrupt() || oops_in_progress)
 555                 return panic_nand_wait_ready(mtd, 400);
 556
 557         led_trigger_event(nand_led_trigger, LED_FULL);
 558         /* Wait until command is processed or timeout occurs */
 559         do {
 560                 if (chip->dev_ready(mtd))
 561                         break;
 562                 touch_softlockup_watchdog();
 563         } while (time_before(jiffies, timeo));
 564         led_trigger_event(nand_led_trigger, LED_OFF);
 565 }
 566 EXPORT_SYMBOL_GPL(nand_wait_ready);
 567
 568 /**
 569  * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
 570  * @mtd: MTD device structure
 571  * @timeo: Timeout in ms
 572  *
 573  * Wait for status ready (i.e. command done) or timeout.
 574  */
 575 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
 576 {
 577         register struct nand_chip *chip = mtd->priv;
 578
 579         timeo = jiffies + msecs_to_jiffies(timeo);
 580         do {
 581                 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
 582                         break;
 583                 touch_softlockup_watchdog();
 584         } while (time_before(jiffies, timeo));
 585 };
 586
 587 /**
 588  * nand_command - [DEFAULT] Send command to NAND device
 589  * @mtd: MTD device structure
 590  * @command: the command to be sent
 591  * @column: the column address for this command, -1 if none
 592  * @page_addr: the page address for this command, -1 if none
 593  *
 594  * Send command to NAND device. This function is used for small page devices
 595  * (512 Bytes per page).
 596  */
 597 static void nand_command(struct mtd_info *mtd, unsigned int command,
 598                          int column, int page_addr)
 599 {
 600         register struct nand_chip *chip = mtd->priv;
 601         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 602
 603         /* Write out the command to the device */
 604         if (command == NAND_CMD_SEQIN) {
 605                 int readcmd;
 606
 607                 if (column >= mtd->writesize) {
 608                         /* OOB area */
 609                         column -= mtd->writesize;
 610                         readcmd = NAND_CMD_READOOB;
 611                 } else if (column < 256) {
 612                         /* First 256 bytes --> READ0 */
 613                         readcmd = NAND_CMD_READ0;
 614                 } else {
 615                         column -= 256;
 616                         readcmd = NAND_CMD_READ1;
 617                 }
 618                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 619                 ctrl &= ~NAND_CTRL_CHANGE;
 620         }
 621         chip->cmd_ctrl(mtd, command, ctrl);
 622
 623         /* Address cycle, when necessary */
 624         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 625         /* Serially input address */
 626         if (column != -1) {
 627                 /* Adjust columns for 16 bit buswidth */
 628                 if (chip->options & NAND_BUSWIDTH_16 &&
 629                                 !nand_opcode_8bits(command))
 630                         column >>= 1;
 631                 chip->cmd_ctrl(mtd, column, ctrl);
 632                 ctrl &= ~NAND_CTRL_CHANGE;
 633         }
 634         if (page_addr != -1) {
 635                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 636                 ctrl &= ~NAND_CTRL_CHANGE;
 637                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 638                 /* One more address cycle for devices > 32MiB */
 639                 if (chip->chipsize > (32 << 20))
 640                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 641         }
 642         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 643
 644         /*
 645          * Program and erase have their own busy handlers status and sequential
 646          * in needs no delay
 647          */
 648         switch (command) {
 649
 650         case NAND_CMD_PAGEPROG:
 651         case NAND_CMD_ERASE1:
 652         case NAND_CMD_ERASE2:
 653         case NAND_CMD_SEQIN:
 654         case NAND_CMD_STATUS:
 655                 return;
 656
 657         case NAND_CMD_RESET:
 658                 if (chip->dev_ready)
 659                         break;
 660                 udelay(chip->chip_delay);
 661                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 662                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 663                 chip->cmd_ctrl(mtd,
 664                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 665                 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
 666                 nand_wait_status_ready(mtd, 250);
 667                 return;
 668
 669                 /* This applies to read commands */
 670         default:
 671                 /*
 672                  * If we don't have access to the busy pin, we apply the given
 673                  * command delay
 674                  */
 675                 if (!chip->dev_ready) {
 676                         udelay(chip->chip_delay);
 677                         return;
 678                 }
 679         }
 680         /*
 681          * Apply this short delay always to ensure that we do wait tWB in
 682          * any case on any machine.
 683          */
 684         ndelay(100);
 685
 686         nand_wait_ready(mtd);
 687 }
 688
 689 /**
 690  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 691  * @mtd: MTD device structure
 692  * @command: the command to be sent
 693  * @column: the column address for this command, -1 if none
 694  * @page_addr: the page address for this command, -1 if none
 695  *
 696  * Send command to NAND device. This is the version for the new large page
 697  * devices. We don't have the separate regions as we have in the small page
 698  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 699  */
 700 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 701                             int column, int page_addr)
 702 {
 703         register struct nand_chip *chip = mtd->priv;
 704
 705         /* Emulate NAND_CMD_READOOB */
 706         if (command == NAND_CMD_READOOB) {
 707                 column += mtd->writesize;
 708                 command = NAND_CMD_READ0;
 709         }
 710
 711         /* Command latch cycle */
 712         chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 713
 714         if (column != -1 || page_addr != -1) {
 715                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 716
 717                 /* Serially input address */
 718                 if (column != -1) {
 719                         /* Adjust columns for 16 bit buswidth */
 720                         if (chip->options & NAND_BUSWIDTH_16 &&
 721                                         !nand_opcode_8bits(command))
 722                                 column >>= 1;
 723                         chip->cmd_ctrl(mtd, column, ctrl);
 724                         ctrl &= ~NAND_CTRL_CHANGE;
 725                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 726                 }
 727                 if (page_addr != -1) {
 728                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 729                         chip->cmd_ctrl(mtd, page_addr >> 8,
 730                                        NAND_NCE | NAND_ALE);
 731                         /* One more address cycle for devices > 128MiB */
 732                         if (chip->chipsize > (128 << 20))
 733                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 734                                                NAND_NCE | NAND_ALE);
 735                 }
 736         }
 737         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 738
 739         /*
 740          * Program and erase have their own busy handlers status, sequential
 741          * in and status need no delay.
 742          */
 743         switch (command) {
 744
 745         case NAND_CMD_CACHEDPROG:
 746         case NAND_CMD_PAGEPROG:
 747         case NAND_CMD_ERASE1:
 748         case NAND_CMD_ERASE2:
 749         case NAND_CMD_SEQIN:
 750         case NAND_CMD_RNDIN:
 751         case NAND_CMD_STATUS:
 752                 return;
 753
 754         case NAND_CMD_RESET:
 755                 if (chip->dev_ready)
 756                         break;
 757                 udelay(chip->chip_delay);
 758                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 759                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 760                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 761                                NAND_NCE | NAND_CTRL_CHANGE);
 762                 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
 763                 nand_wait_status_ready(mtd, 250);
 764                 return;
 765
 766         case NAND_CMD_RNDOUT:
 767                 /* No ready / busy check necessary */
 768                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 769                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 770                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 771                                NAND_NCE | NAND_CTRL_CHANGE);
 772                 return;
 773
 774         case NAND_CMD_READ0:
 775                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 776                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 777                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 778                                NAND_NCE | NAND_CTRL_CHANGE);
 779
 780                 /* This applies to read commands */
 781         default:
 782                 /*
 783                  * If we don't have access to the busy pin, we apply the given
 784                  * command delay.
 785                  */
 786                 if (!chip->dev_ready) {
 787                         udelay(chip->chip_delay);
 788                         return;
 789                 }
 790         }
 791
 792         /*
 793          * Apply this short delay always to ensure that we do wait tWB in
 794          * any case on any machine.
 795          */
 796         ndelay(100);
 797
 798         nand_wait_ready(mtd);
 799 }
 800
 801 /**
 802  * panic_nand_get_device - [GENERIC] Get chip for selected access
 803  * @chip: the nand chip descriptor
 804  * @mtd: MTD device structure
 805  * @new_state: the state which is requested
 806  *
 807  * Used when in panic, no locks are taken.
 808  */
 809 static void panic_nand_get_device(struct nand_chip *chip,
 810                       struct mtd_info *mtd, int new_state)
 811 {
 812         /* Hardware controller shared among independent devices */
 813         chip->controller->active = chip;
 814         chip->state = new_state;
 815 }
 816
 817 /**
 818  * nand_get_device - [GENERIC] Get chip for selected access
 819  * @mtd: MTD device structure
 820  * @new_state: the state which is requested
 821  *
 822  * Get the device and lock it for exclusive access
 823  */
 824 static int
 825 nand_get_device(struct mtd_info *mtd, int new_state)
 826 {
 827         struct nand_chip *chip = mtd->priv;
 828         spinlock_t *lock = &chip->controller->lock;
 829         wait_queue_head_t *wq = &chip->controller->wq;
 830         DECLARE_WAITQUEUE(wait, current);
 831 retry:
 832         spin_lock(lock);
 833
 834         /* Hardware controller shared among independent devices */
 835         if (!chip->controller->active)
 836                 chip->controller->active = chip;
 837
 838         if (chip->controller->active == chip && chip->state == FL_READY) {
 839                 chip->state = new_state;
 840                 spin_unlock(lock);
 841                 return 0;
 842         }
 843         if (new_state == FL_PM_SUSPENDED) {
 844                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 845                         chip->state = FL_PM_SUSPENDED;
 846                         spin_unlock(lock);
 847                         return 0;
 848                 }
 849         }
 850         set_current_state(TASK_UNINTERRUPTIBLE);
 851         add_wait_queue(wq, &wait);
 852         spin_unlock(lock);
 853         schedule();
 854         remove_wait_queue(wq, &wait);
 855         goto retry;
 856 }
 857
 858 /**
 859  * panic_nand_wait - [GENERIC] wait until the command is done
 860  * @mtd: MTD device structure
 861  * @chip: NAND chip structure
 862  * @timeo: timeout
 863  *
 864  * Wait for command done. This is a helper function for nand_wait used when
 865  * we are in interrupt context. May happen when in panic and trying to write
 866  * an oops through mtdoops.
 867  */
 868 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 869                             unsigned long timeo)
 870 {
 871         int i;
 872         for (i = 0; i < timeo; i++) {
 873                 if (chip->dev_ready) {
 874                         if (chip->dev_ready(mtd))
 875                                 break;
 876                 } else {
 877                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 878                                 break;
 879                 }
 880                 mdelay(1);
 881         }
 882 }
 883
 884 /**
 885  * nand_wait - [DEFAULT] wait until the command is done
 886  * @mtd: MTD device structure
 887  * @chip: NAND chip structure
 888  *
 889  * Wait for command done. This applies to erase and program only. Erase can
 890  * take up to 400ms and program up to 20ms according to general NAND and
 891  * SmartMedia specs.
 892  */
 893 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 894 {
 895
 896         int status, state = chip->state;
 897         unsigned long timeo = (state == FL_ERASING ? 400 : 20);
 898
 899         led_trigger_event(nand_led_trigger, LED_FULL);
 900
 901         /*
 902          * Apply this short delay always to ensure that we do wait tWB in any
 903          * case on any machine.
 904          */
 905         ndelay(100);
 906
 907         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 908
 909         if (in_interrupt() || oops_in_progress)
 910                 panic_nand_wait(mtd, chip, timeo);
 911         else {
 912                 timeo = jiffies + msecs_to_jiffies(timeo);
 913                 while (time_before(jiffies, timeo)) {
 914                         if (chip->dev_ready) {
 915                                 if (chip->dev_ready(mtd))
 916                                         break;
 917                         } else {
 918                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 919                                         break;
 920                         }
 921                         cond_resched();
 922                 }
 923         }
 924         led_trigger_event(nand_led_trigger, LED_OFF);
 925
 926         status = (int)chip->read_byte(mtd);
 927         /* This can happen if in case of timeout or buggy dev_ready */
 928         WARN_ON(!(status & NAND_STATUS_READY));
 929         return status;
 930 }
 931
 932 /**
 933  * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 934  * @mtd: mtd info
 935  * @ofs: offset to start unlock from
 936  * @len: length to unlock
 937  * @invert: when = 0, unlock the range of blocks within the lower and
 938  *                    upper boundary address
 939  *          when = 1, unlock the range of blocks outside the boundaries
 940  *                    of the lower and upper boundary address
 941  *
 942  * Returs unlock status.
 943  */
 944 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
 945                                         uint64_t len, int invert)
 946 {
 947         int ret = 0;
 948         int status, page;
 949         struct nand_chip *chip = mtd->priv;
 950
 951         /* Submit address of first page to unlock */
 952         page = ofs >> chip->page_shift;
 953         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 954
 955         /* Submit address of last page to unlock */
 956         page = (ofs + len) >> chip->page_shift;
 957         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
 958                                 (page | invert) & chip->pagemask);
 959
 960         /* Call wait ready function */
 961         status = chip->waitfunc(mtd, chip);
 962         /* See if device thinks it succeeded */
 963         if (status & NAND_STATUS_FAIL) {
 964                 pr_debug("%s: error status = 0x%08x\n",
 965                                         __func__, status);
 966                 ret = -EIO;
 967         }
 968
 969         return ret;
 970 }
 971
 972 /**
 973  * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 974  * @mtd: mtd info
 975  * @ofs: offset to start unlock from
 976  * @len: length to unlock
 977  *
 978  * Returns unlock status.
 979  */
 980 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 981 {
 982         int ret = 0;
 983         int chipnr;
 984         struct nand_chip *chip = mtd->priv;
 985
 986         pr_debug("%s: start = 0x%012llx, len = %llu\n",
 987                         __func__, (unsigned long long)ofs, len);
 988
 989         if (check_offs_len(mtd, ofs, len))
 990                 return -EINVAL;
 991
 992         /* Align to last block address if size addresses end of the device */
 993         if (ofs + len == mtd->size)
 994                 len -= mtd->erasesize;
 995
 996         nand_get_device(mtd, FL_UNLOCKING);
 997
 998         /* Shift to get chip number */
 999         chipnr = ofs >> chip->chip_shift;
1000
1001         chip->select_chip(mtd, chipnr);
1002
1003         /*
1004          * Reset the chip.
1005          * If we want to check the WP through READ STATUS and check the bit 7
1006          * we must reset the chip
1007          * some operation can also clear the bit 7 of status register
1008          * eg. erase/program a locked block
1009          */
1010         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1011
1012         /* Check, if it is write protected */
1013         if (nand_check_wp(mtd)) {
1014                 pr_debug("%s: device is write protected!\n",
1015                                         __func__);
1016                 ret = -EIO;
1017                 goto out;
1018         }
1019
1020         ret = __nand_unlock(mtd, ofs, len, 0);
1021
1022 out:
1023         chip->select_chip(mtd, -1);
1024         nand_release_device(mtd);
1025
1026         return ret;
1027 }
1028 EXPORT_SYMBOL(nand_unlock);
1029
1030 /**
1031  * nand_lock - [REPLACEABLE] locks all blocks present in the device
1032  * @mtd: mtd info
1033  * @ofs: offset to start unlock from
1034  * @len: length to unlock
1035  *
1036  * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1037  * have this feature, but it allows only to lock all blocks, not for specified
1038  * range for block. Implementing 'lock' feature by making use of 'unlock', for
1039  * now.
1040  *
1041  * Returns lock status.
1042  */
1043 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1044 {
1045         int ret = 0;
1046         int chipnr, status, page;
1047         struct nand_chip *chip = mtd->priv;
1048
1049         pr_debug("%s: start = 0x%012llx, len = %llu\n",
1050                         __func__, (unsigned long long)ofs, len);
1051
1052         if (check_offs_len(mtd, ofs, len))
1053                 return -EINVAL;
1054
1055         nand_get_device(mtd, FL_LOCKING);
1056
1057         /* Shift to get chip number */
1058         chipnr = ofs >> chip->chip_shift;
1059
1060         chip->select_chip(mtd, chipnr);
1061
1062         /*
1063          * Reset the chip.
1064          * If we want to check the WP through READ STATUS and check the bit 7
1065          * we must reset the chip
1066          * some operation can also clear the bit 7 of status register
1067          * eg. erase/program a locked block
1068          */
1069         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1070
1071         /* Check, if it is write protected */
1072         if (nand_check_wp(mtd)) {
1073                 pr_debug("%s: device is write protected!\n",
1074                                         __func__);
1075                 status = MTD_ERASE_FAILED;
1076                 ret = -EIO;
1077                 goto out;
1078         }
1079
1080         /* Submit address of first page to lock */
1081         page = ofs >> chip->page_shift;
1082         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1083
1084         /* Call wait ready function */
1085         status = chip->waitfunc(mtd, chip);
1086         /* See if device thinks it succeeded */
1087         if (status & NAND_STATUS_FAIL) {
1088                 pr_debug("%s: error status = 0x%08x\n",
1089                                         __func__, status);
1090                 ret = -EIO;
1091                 goto out;
1092         }
1093
1094         ret = __nand_unlock(mtd, ofs, len, 0x1);
1095
1096 out:
1097         chip->select_chip(mtd, -1);
1098         nand_release_device(mtd);
1099
1100         return ret;
1101 }
1102 EXPORT_SYMBOL(nand_lock);
1103
1104 /**
1105  * nand_read_page_raw - [INTERN] read raw page data without ecc
1106  * @mtd: mtd info structure
1107  * @chip: nand chip info structure
1108  * @buf: buffer to store read data
1109  * @oob_required: caller requires OOB data read to chip->oob_poi
1110  * @page: page number to read
1111  *
1112  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1113  */
1114 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1115                               uint8_t *buf, int oob_required, int page)
1116 {
1117         chip->read_buf(mtd, buf, mtd->writesize);
1118         if (oob_required)
1119                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1120         return 0;
1121 }
1122
1123 /**
1124  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1125  * @mtd: mtd info structure
1126  * @chip: nand chip info structure
1127  * @buf: buffer to store read data
1128  * @oob_required: caller requires OOB data read to chip->oob_poi
1129  * @page: page number to read
1130  *
1131  * We need a special oob layout and handling even when OOB isn't used.
1132  */
1133 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1134                                        struct nand_chip *chip, uint8_t *buf,
1135                                        int oob_required, int page)
1136 {
1137         int eccsize = chip->ecc.size;
1138         int eccbytes = chip->ecc.bytes;
1139         uint8_t *oob = chip->oob_poi;
1140         int steps, size;
1141
1142         for (steps = chip->ecc.steps; steps > 0; steps--) {
1143                 chip->read_buf(mtd, buf, eccsize);
1144                 buf += eccsize;
1145
1146                 if (chip->ecc.prepad) {
1147                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1148                         oob += chip->ecc.prepad;
1149                 }
1150
1151                 chip->read_buf(mtd, oob, eccbytes);
1152                 oob += eccbytes;
1153
1154                 if (chip->ecc.postpad) {
1155                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1156                         oob += chip->ecc.postpad;
1157                 }
1158         }
1159
1160         size = mtd->oobsize - (oob - chip->oob_poi);
1161         if (size)
1162                 chip->read_buf(mtd, oob, size);
1163
1164         return 0;
1165 }
1166
1167 /**
1168  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1169  * @mtd: mtd info structure
1170  * @chip: nand chip info structure
1171  * @buf: buffer to store read data
1172  * @oob_required: caller requires OOB data read to chip->oob_poi
1173  * @page: page number to read
1174  */
1175 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1176                                 uint8_t *buf, int oob_required, int page)
1177 {
1178         int i, eccsize = chip->ecc.size;
1179         int eccbytes = chip->ecc.bytes;
1180         int eccsteps = chip->ecc.steps;
1181         uint8_t *p = buf;
1182         uint8_t *ecc_calc = chip->buffers->ecccalc;
1183         uint8_t *ecc_code = chip->buffers->ecccode;
1184         uint32_t *eccpos = chip->ecc.layout->eccpos;
1185         unsigned int max_bitflips = 0;
1186
1187         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1188
1189         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1190                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1191
1192         for (i = 0; i < chip->ecc.total; i++)
1193                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1194
1195         eccsteps = chip->ecc.steps;
1196         p = buf;
1197
1198         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1199                 int stat;
1200
1201                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1202                 if (stat < 0) {
1203                         mtd->ecc_stats.failed++;
1204                 } else {
1205                         mtd->ecc_stats.corrected += stat;
1206                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1207                 }
1208         }
1209         return max_bitflips;
1210 }
1211
1212 /**
1213  * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1214  * @mtd: mtd info structure
1215  * @chip: nand chip info structure
1216  * @data_offs: offset of requested data within the page
1217  * @readlen: data length
1218  * @bufpoi: buffer to store read data
1219  * @page: page number to read
1220  */
1221 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1222                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1223                         int page)
1224 {
1225         int start_step, end_step, num_steps;
1226         uint32_t *eccpos = chip->ecc.layout->eccpos;
1227         uint8_t *p;
1228         int data_col_addr, i, gaps = 0;
1229         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1230         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1231         int index;
1232         unsigned int max_bitflips = 0;
1233
1234         /* Column address within the page aligned to ECC size (256bytes) */
1235         start_step = data_offs / chip->ecc.size;
1236         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1237         num_steps = end_step - start_step + 1;
1238         index = start_step * chip->ecc.bytes;
1239
1240         /* Data size aligned to ECC ecc.size */
1241         datafrag_len = num_steps * chip->ecc.size;
1242         eccfrag_len = num_steps * chip->ecc.bytes;
1243
1244         data_col_addr = start_step * chip->ecc.size;
1245         /* If we read not a page aligned data */
1246         if (data_col_addr != 0)
1247                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1248
1249         p = bufpoi + data_col_addr;
1250         chip->read_buf(mtd, p, datafrag_len);
1251
1252         /* Calculate ECC */
1253         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1254                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1255
1256         /*
1257          * The performance is faster if we position offsets according to
1258          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1259          */
1260         for (i = 0; i < eccfrag_len - 1; i++) {
1261                 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
1262                         gaps = 1;
1263                         break;
1264                 }
1265         }
1266         if (gaps) {
1267                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1268                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1269         } else {
1270                 /*
1271                  * Send the command to read the particular ECC bytes take care
1272                  * about buswidth alignment in read_buf.
1273                  */
1274                 aligned_pos = eccpos[index] & ~(busw - 1);
1275                 aligned_len = eccfrag_len;
1276                 if (eccpos[index] & (busw - 1))
1277                         aligned_len++;
1278                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1279                         aligned_len++;
1280
1281                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1282                                         mtd->writesize + aligned_pos, -1);
1283                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1284         }
1285
1286         for (i = 0; i < eccfrag_len; i++)
1287                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1288
1289         p = bufpoi + data_col_addr;
1290         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1291                 int stat;
1292
1293                 stat = chip->ecc.correct(mtd, p,
1294                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1295                 if (stat < 0) {
1296                         mtd->ecc_stats.failed++;
1297                 } else {
1298                         mtd->ecc_stats.corrected += stat;
1299                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1300                 }
1301         }
1302         return max_bitflips;
1303 }
1304
1305 /**
1306  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1307  * @mtd: mtd info structure
1308  * @chip: nand chip info structure
1309  * @buf: buffer to store read data
1310  * @oob_required: caller requires OOB data read to chip->oob_poi
1311  * @page: page number to read
1312  *
1313  * Not for syndrome calculating ECC controllers which need a special oob layout.
1314  */
1315 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1316                                 uint8_t *buf, int oob_required, int page)
1317 {
1318         int i, eccsize = chip->ecc.size;
1319         int eccbytes = chip->ecc.bytes;
1320         int eccsteps = chip->ecc.steps;
1321         uint8_t *p = buf;
1322         uint8_t *ecc_calc = chip->buffers->ecccalc;
1323         uint8_t *ecc_code = chip->buffers->ecccode;
1324         uint32_t *eccpos = chip->ecc.layout->eccpos;
1325         unsigned int max_bitflips = 0;
1326
1327         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1328                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1329                 chip->read_buf(mtd, p, eccsize);
1330                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1331         }
1332         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1333
1334         for (i = 0; i < chip->ecc.total; i++)
1335                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1336
1337         eccsteps = chip->ecc.steps;
1338         p = buf;
1339
1340         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1341                 int stat;
1342
1343                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1344                 if (stat < 0) {
1345                         mtd->ecc_stats.failed++;
1346                 } else {
1347                         mtd->ecc_stats.corrected += stat;
1348                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1349                 }
1350         }
1351         return max_bitflips;
1352 }
1353
1354 /**
1355  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1356  * @mtd: mtd info structure
1357  * @chip: nand chip info structure
1358  * @buf: buffer to store read data
1359  * @oob_required: caller requires OOB data read to chip->oob_poi
1360  * @page: page number to read
1361  *
1362  * Hardware ECC for large page chips, require OOB to be read first. For this
1363  * ECC mode, the write_page method is re-used from ECC_HW. These methods
1364  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1365  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1366  * the data area, by overwriting the NAND manufacturer bad block markings.
1367  */
1368 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1369         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1370 {
1371         int i, eccsize = chip->ecc.size;
1372         int eccbytes = chip->ecc.bytes;
1373         int eccsteps = chip->ecc.steps;
1374         uint8_t *p = buf;
1375         uint8_t *ecc_code = chip->buffers->ecccode;
1376         uint32_t *eccpos = chip->ecc.layout->eccpos;
1377         uint8_t *ecc_calc = chip->buffers->ecccalc;
1378         unsigned int max_bitflips = 0;
1379
1380         /* Read the OOB area first */
1381         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1382         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1383         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1384
1385         for (i = 0; i < chip->ecc.total; i++)
1386                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1387
1388         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1389                 int stat;
1390
1391                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1392                 chip->read_buf(mtd, p, eccsize);
1393                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1394
1395                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1396                 if (stat < 0) {
1397                         mtd->ecc_stats.failed++;
1398                 } else {
1399                         mtd->ecc_stats.corrected += stat;
1400                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1401                 }
1402         }
1403         return max_bitflips;
1404 }
1405
1406 /**
1407  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1408  * @mtd: mtd info structure
1409  * @chip: nand chip info structure
1410  * @buf: buffer to store read data
1411  * @oob_required: caller requires OOB data read to chip->oob_poi
1412  * @page: page number to read
1413  *
1414  * The hw generator calculates the error syndrome automatically. Therefore we
1415  * need a special oob layout and handling.
1416  */
1417 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1418                                    uint8_t *buf, int oob_required, int page)
1419 {
1420         int i, eccsize = chip->ecc.size;
1421         int eccbytes = chip->ecc.bytes;
1422         int eccsteps = chip->ecc.steps;
1423         uint8_t *p = buf;
1424         uint8_t *oob = chip->oob_poi;
1425         unsigned int max_bitflips = 0;
1426
1427         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1428                 int stat;
1429
1430                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1431                 chip->read_buf(mtd, p, eccsize);
1432
1433                 if (chip->ecc.prepad) {
1434                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1435                         oob += chip->ecc.prepad;
1436                 }
1437
1438                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1439                 chip->read_buf(mtd, oob, eccbytes);
1440                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1441
1442                 if (stat < 0) {
1443                         mtd->ecc_stats.failed++;
1444                 } else {
1445                         mtd->ecc_stats.corrected += stat;
1446                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1447                 }
1448
1449                 oob += eccbytes;
1450
1451                 if (chip->ecc.postpad) {
1452                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1453                         oob += chip->ecc.postpad;
1454                 }
1455         }
1456
1457         /* Calculate remaining oob bytes */
1458         i = mtd->oobsize - (oob - chip->oob_poi);
1459         if (i)
1460                 chip->read_buf(mtd, oob, i);
1461
1462         return max_bitflips;
1463 }
1464
1465 /**
1466  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1467  * @chip: nand chip structure
1468  * @oob: oob destination address
1469  * @ops: oob ops structure
1470  * @len: size of oob to transfer
1471  */
1472 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1473                                   struct mtd_oob_ops *ops, size_t len)
1474 {
1475         switch (ops->mode) {
1476
1477         case MTD_OPS_PLACE_OOB:
1478         case MTD_OPS_RAW:
1479                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1480                 return oob + len;
1481
1482         case MTD_OPS_AUTO_OOB: {
1483                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1484                 uint32_t boffs = 0, roffs = ops->ooboffs;
1485                 size_t bytes = 0;
1486
1487                 for (; free->length && len; free++, len -= bytes) {
1488                         /* Read request not from offset 0? */
1489                         if (unlikely(roffs)) {
1490                                 if (roffs >= free->length) {
1491                                         roffs -= free->length;
1492                                         continue;
1493                                 }
1494                                 boffs = free->offset + roffs;
1495                                 bytes = min_t(size_t, len,
1496                                               (free->length - roffs));
1497                                 roffs = 0;
1498                         } else {
1499                                 bytes = min_t(size_t, len, free->length);
1500                                 boffs = free->offset;
1501                         }
1502                         memcpy(oob, chip->oob_poi + boffs, bytes);
1503                         oob += bytes;
1504                 }
1505                 return oob;
1506         }
1507         default:
1508                 BUG();
1509         }
1510         return NULL;
1511 }
1512
1513 /**
1514  * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1515  * @mtd: MTD device structure
1516  * @retry_mode: the retry mode to use
1517  *
1518  * Some vendors supply a special command to shift the Vt threshold, to be used
1519  * when there are too many bitflips in a page (i.e., ECC error). After setting
1520  * a new threshold, the host should retry reading the page.
1521  */
1522 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1523 {
1524         struct nand_chip *chip = mtd->priv;
1525
1526         pr_debug("setting READ RETRY mode %d\n", retry_mode);
1527
1528         if (retry_mode >= chip->read_retries)
1529                 return -EINVAL;
1530
1531         if (!chip->setup_read_retry)
1532                 return -EOPNOTSUPP;
1533
1534         return chip->setup_read_retry(mtd, retry_mode);
1535 }
1536
1537 /**
1538  * nand_do_read_ops - [INTERN] Read data with ECC
1539  * @mtd: MTD device structure
1540  * @from: offset to read from
1541  * @ops: oob ops structure
1542  *
1543  * Internal function. Called with chip held.
1544  */
1545 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1546                             struct mtd_oob_ops *ops)
1547 {
1548         int chipnr, page, realpage, col, bytes, aligned, oob_required;
1549         struct nand_chip *chip = mtd->priv;
1550         int ret = 0;
1551         uint32_t readlen = ops->len;
1552         uint32_t oobreadlen = ops->ooblen;
1553         uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1554                 mtd->oobavail : mtd->oobsize;
1555
1556         uint8_t *bufpoi, *oob, *buf;
1557         int use_bufpoi;
1558         unsigned int max_bitflips = 0;
1559         int retry_mode = 0;
1560         bool ecc_fail = false;
1561
1562         chipnr = (int)(from >> chip->chip_shift);
1563         chip->select_chip(mtd, chipnr);
1564
1565         realpage = (int)(from >> chip->page_shift);
1566         page = realpage & chip->pagemask;
1567
1568         col = (int)(from & (mtd->writesize - 1));
1569
1570         buf = ops->datbuf;
1571         oob = ops->oobbuf;
1572         oob_required = oob ? 1 : 0;
1573
1574         while (1) {
1575                 unsigned int ecc_failures = mtd->ecc_stats.failed;
1576
1577                 bytes = min(mtd->writesize - col, readlen);
1578                 aligned = (bytes == mtd->writesize);
1579
1580                 if (!aligned)
1581                         use_bufpoi = 1;
1582                 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
1583                         use_bufpoi = !virt_addr_valid(buf);
1584                 else
1585                         use_bufpoi = 0;
1586
1587                 /* Is the current page in the buffer? */
1588                 if (realpage != chip->pagebuf || oob) {
1589                         bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1590
1591                         if (use_bufpoi && aligned)
1592                                 pr_debug("%s: using read bounce buffer for buf@%p\n",
1593                                                  __func__, buf);
1594
1595 read_retry:
1596                         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1597
1598                         /*
1599                          * Now read the page into the buffer.  Absent an error,
1600                          * the read methods return max bitflips per ecc step.
1601                          */
1602                         if (unlikely(ops->mode == MTD_OPS_RAW))
1603                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1604                                                               oob_required,
1605                                                               page);
1606                         else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1607                                  !oob)
1608                                 ret = chip->ecc.read_subpage(mtd, chip,
1609                                                         col, bytes, bufpoi,
1610                                                         page);
1611                         else
1612                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1613                                                           oob_required, page);
1614                         if (ret < 0) {
1615                                 if (use_bufpoi)
1616                                         /* Invalidate page cache */
1617                                         chip->pagebuf = -1;
1618                                 break;
1619                         }
1620
1621                         max_bitflips = max_t(unsigned int, max_bitflips, ret);
1622
1623                         /* Transfer not aligned data */
1624                         if (use_bufpoi) {
1625                                 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1626                                     !(mtd->ecc_stats.failed - ecc_failures) &&
1627                                     (ops->mode != MTD_OPS_RAW)) {
1628                                         chip->pagebuf = realpage;
1629                                         chip->pagebuf_bitflips = ret;
1630                                 } else {
1631                                         /* Invalidate page cache */
1632                                         chip->pagebuf = -1;
1633                                 }
1634                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1635                         }
1636
1637                         if (unlikely(oob)) {
1638                                 int toread = min(oobreadlen, max_oobsize);
1639
1640                                 if (toread) {
1641                                         oob = nand_transfer_oob(chip,
1642                                                 oob, ops, toread);
1643                                         oobreadlen -= toread;
1644                                 }
1645                         }
1646
1647                         if (chip->options & NAND_NEED_READRDY) {
1648                                 /* Apply delay or wait for ready/busy pin */
1649                                 if (!chip->dev_ready)
1650                                         udelay(chip->chip_delay);
1651                                 else
1652                                         nand_wait_ready(mtd);
1653                         }
1654
1655                         if (mtd->ecc_stats.failed - ecc_failures) {
1656                                 if (retry_mode + 1 < chip->read_retries) {
1657                                         retry_mode++;
1658                                         ret = nand_setup_read_retry(mtd,
1659                                                         retry_mode);
1660                                         if (ret < 0)
1661                                                 break;
1662
1663                                         /* Reset failures; retry */
1664                                         mtd->ecc_stats.failed = ecc_failures;
1665                                         goto read_retry;
1666                                 } else {
1667                                         /* No more retry modes; real failure */
1668                                         ecc_fail = true;
1669                                 }
1670                         }
1671
1672                         buf += bytes;
1673                 } else {
1674                         memcpy(buf, chip->buffers->databuf + col, bytes);
1675                         buf += bytes;
1676                         max_bitflips = max_t(unsigned int, max_bitflips,
1677                                              chip->pagebuf_bitflips);
1678                 }
1679
1680                 readlen -= bytes;
1681
1682                 /* Reset to retry mode 0 */
1683                 if (retry_mode) {
1684                         ret = nand_setup_read_retry(mtd, 0);
1685                         if (ret < 0)
1686                                 break;
1687                         retry_mode = 0;
1688                 }
1689
1690                 if (!readlen)
1691                         break;
1692
1693                 /* For subsequent reads align to page boundary */
1694                 col = 0;
1695                 /* Increment page address */
1696                 realpage++;
1697
1698                 page = realpage & chip->pagemask;
1699                 /* Check, if we cross a chip boundary */
1700                 if (!page) {
1701                         chipnr++;
1702                         chip->select_chip(mtd, -1);
1703                         chip->select_chip(mtd, chipnr);
1704                 }
1705         }
1706         chip->select_chip(mtd, -1);
1707
1708         ops->retlen = ops->len - (size_t) readlen;
1709         if (oob)
1710                 ops->oobretlen = ops->ooblen - oobreadlen;
1711
1712         if (ret < 0)
1713                 return ret;
1714
1715         if (ecc_fail)
1716                 return -EBADMSG;
1717
1718         return max_bitflips;
1719 }
1720
1721 /**
1722  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1723  * @mtd: MTD device structure
1724  * @from: offset to read from
1725  * @len: number of bytes to read
1726  * @retlen: pointer to variable to store the number of read bytes
1727  * @buf: the databuffer to put data
1728  *
1729  * Get hold of the chip and call nand_do_read.
1730  */
1731 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1732                      size_t *retlen, uint8_t *buf)
1733 {
1734         struct mtd_oob_ops ops;
1735         int ret;
1736
1737         nand_get_device(mtd, FL_READING);
1738         memset(&ops, 0, sizeof(ops));
1739         ops.len = len;
1740         ops.datbuf = buf;
1741         ops.mode = MTD_OPS_PLACE_OOB;
1742         ret = nand_do_read_ops(mtd, from, &ops);
1743         *retlen = ops.retlen;
1744         nand_release_device(mtd);
1745         return ret;
1746 }
1747
1748 /**
1749  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1750  * @mtd: mtd info structure
1751  * @chip: nand chip info structure
1752  * @page: page number to read
1753  */
1754 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1755                              int page)
1756 {
1757         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1758         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1759         return 0;
1760 }
1761
1762 /**
1763  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1764  *                          with syndromes
1765  * @mtd: mtd info structure
1766  * @chip: nand chip info structure
1767  * @page: page number to read
1768  */
1769 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1770                                   int page)
1771 {
1772         int length = mtd->oobsize;
1773         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1774         int eccsize = chip->ecc.size;
1775         uint8_t *bufpoi = chip->oob_poi;
1776         int i, toread, sndrnd = 0, pos;
1777
1778         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1779         for (i = 0; i < chip->ecc.steps; i++) {
1780                 if (sndrnd) {
1781                         pos = eccsize + i * (eccsize + chunk);
1782                         if (mtd->writesize > 512)
1783                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1784                         else
1785                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1786                 } else
1787                         sndrnd = 1;
1788                 toread = min_t(int, length, chunk);
1789                 chip->read_buf(mtd, bufpoi, toread);
1790                 bufpoi += toread;
1791                 length -= toread;
1792         }
1793         if (length > 0)
1794                 chip->read_buf(mtd, bufpoi, length);
1795
1796         return 0;
1797 }
1798
1799 /**
1800  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1801  * @mtd: mtd info structure
1802  * @chip: nand chip info structure
1803  * @page: page number to write
1804  */
1805 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1806                               int page)
1807 {
1808         int status = 0;
1809         const uint8_t *buf = chip->oob_poi;
1810         int length = mtd->oobsize;
1811
1812         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1813         chip->write_buf(mtd, buf, length);
1814         /* Send command to program the OOB data */
1815         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1816
1817         status = chip->waitfunc(mtd, chip);
1818
1819         return status & NAND_STATUS_FAIL ? -EIO : 0;
1820 }
1821
1822 /**
1823  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1824  *                           with syndrome - only for large page flash
1825  * @mtd: mtd info structure
1826  * @chip: nand chip info structure
1827  * @page: page number to write
1828  */
1829 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1830                                    struct nand_chip *chip, int page)
1831 {
1832         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1833         int eccsize = chip->ecc.size, length = mtd->oobsize;
1834         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1835         const uint8_t *bufpoi = chip->oob_poi;
1836
1837         /*
1838          * data-ecc-data-ecc ... ecc-oob
1839          * or
1840          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1841          */
1842         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1843                 pos = steps * (eccsize + chunk);
1844                 steps = 0;
1845         } else
1846                 pos = eccsize;
1847
1848         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1849         for (i = 0; i < steps; i++) {
1850                 if (sndcmd) {
1851                         if (mtd->writesize <= 512) {
1852                                 uint32_t fill = 0xFFFFFFFF;
1853
1854                                 len = eccsize;
1855                                 while (len > 0) {
1856                                         int num = min_t(int, len, 4);
1857                                         chip->write_buf(mtd, (uint8_t *)&fill,
1858                                                         num);
1859                                         len -= num;
1860                                 }
1861                         } else {
1862                                 pos = eccsize + i * (eccsize + chunk);
1863                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1864                         }
1865                 } else
1866                         sndcmd = 1;
1867                 len = min_t(int, length, chunk);
1868                 chip->write_buf(mtd, bufpoi, len);
1869                 bufpoi += len;
1870                 length -= len;
1871         }
1872         if (length > 0)
1873                 chip->write_buf(mtd, bufpoi, length);
1874
1875         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1876         status = chip->waitfunc(mtd, chip);
1877
1878         return status & NAND_STATUS_FAIL ? -EIO : 0;
1879 }
1880
1881 /**
1882  * nand_do_read_oob - [INTERN] NAND read out-of-band
1883  * @mtd: MTD device structure
1884  * @from: offset to read from
1885  * @ops: oob operations description structure
1886  *
1887  * NAND read out-of-band data from the spare area.
1888  */
1889 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1890                             struct mtd_oob_ops *ops)
1891 {
1892         int page, realpage, chipnr;
1893         struct nand_chip *chip = mtd->priv;
1894         struct mtd_ecc_stats stats;
1895         int readlen = ops->ooblen;
1896         int len;
1897         uint8_t *buf = ops->oobbuf;
1898         int ret = 0;
1899
1900         pr_debug("%s: from = 0x%08Lx, len = %i\n",
1901                         __func__, (unsigned long long)from, readlen);
1902
1903         stats = mtd->ecc_stats;
1904
1905         if (ops->mode == MTD_OPS_AUTO_OOB)
1906                 len = chip->ecc.layout->oobavail;
1907         else
1908                 len = mtd->oobsize;
1909
1910         if (unlikely(ops->ooboffs >= len)) {
1911                 pr_debug("%s: attempt to start read outside oob\n",
1912                                 __func__);
1913                 return -EINVAL;
1914         }
1915
1916         /* Do not allow reads past end of device */
1917         if (unlikely(from >= mtd->size ||
1918                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1919                                         (from >> chip->page_shift)) * len)) {
1920                 pr_debug("%s: attempt to read beyond end of device\n",
1921                                 __func__);
1922                 return -EINVAL;
1923         }
1924
1925         chipnr = (int)(from >> chip->chip_shift);
1926         chip->select_chip(mtd, chipnr);
1927
1928         /* Shift to get page */
1929         realpage = (int)(from >> chip->page_shift);
1930         page = realpage & chip->pagemask;
1931
1932         while (1) {
1933                 if (ops->mode == MTD_OPS_RAW)
1934                         ret = chip->ecc.read_oob_raw(mtd, chip, page);
1935                 else
1936                         ret = chip->ecc.read_oob(mtd, chip, page);
1937
1938                 if (ret < 0)
1939                         break;
1940
1941                 len = min(len, readlen);
1942                 buf = nand_transfer_oob(chip, buf, ops, len);
1943
1944                 if (chip->options & NAND_NEED_READRDY) {
1945                         /* Apply delay or wait for ready/busy pin */
1946                         if (!chip->dev_ready)
1947                                 udelay(chip->chip_delay);
1948                         else
1949                                 nand_wait_ready(mtd);
1950                 }
1951
1952                 readlen -= len;
1953                 if (!readlen)
1954                         break;
1955
1956                 /* Increment page address */
1957                 realpage++;
1958
1959                 page = realpage & chip->pagemask;
1960                 /* Check, if we cross a chip boundary */
1961                 if (!page) {
1962                         chipnr++;
1963                         chip->select_chip(mtd, -1);
1964                         chip->select_chip(mtd, chipnr);
1965                 }
1966         }
1967         chip->select_chip(mtd, -1);
1968
1969         ops->oobretlen = ops->ooblen - readlen;
1970
1971         if (ret < 0)
1972                 return ret;
1973
1974         if (mtd->ecc_stats.failed - stats.failed)
1975                 return -EBADMSG;
1976
1977         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1978 }
1979
1980 /**
1981  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1982  * @mtd: MTD device structure
1983  * @from: offset to read from
1984  * @ops: oob operation description structure
1985  *
1986  * NAND read data and/or out-of-band data.
1987  */
1988 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1989                          struct mtd_oob_ops *ops)
1990 {
1991         int ret = -ENOTSUPP;
1992
1993         ops->retlen = 0;
1994
1995         /* Do not allow reads past end of device */
1996         if (ops->datbuf && (from + ops->len) > mtd->size) {
1997                 pr_debug("%s: attempt to read beyond end of device\n",
1998                                 __func__);
1999                 return -EINVAL;
2000         }
2001
2002         nand_get_device(mtd, FL_READING);
2003
2004         switch (ops->mode) {
2005         case MTD_OPS_PLACE_OOB:
2006         case MTD_OPS_AUTO_OOB:
2007         case MTD_OPS_RAW:
2008                 break;
2009
2010         default:
2011                 goto out;
2012         }
2013
2014         if (!ops->datbuf)
2015                 ret = nand_do_read_oob(mtd, from, ops);
2016         else
2017                 ret = nand_do_read_ops(mtd, from, ops);
2018
2019 out:
2020         nand_release_device(mtd);
2021         return ret;
2022 }
2023
2024
2025 /**
2026  * nand_write_page_raw - [INTERN] raw page write function
2027  * @mtd: mtd info structure
2028  * @chip: nand chip info structure
2029  * @buf: data buffer
2030  * @oob_required: must write chip->oob_poi to OOB
2031  *
2032  * Not for syndrome calculating ECC controllers, which use a special oob layout.
2033  */
2034 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2035                                 const uint8_t *buf, int oob_required)
2036 {
2037         chip->write_buf(mtd, buf, mtd->writesize);
2038         if (oob_required)
2039                 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2040
2041         return 0;
2042 }
2043
2044 /**
2045  * nand_write_page_raw_syndrome - [INTERN] raw page write function
2046  * @mtd: mtd info structure
2047  * @chip: nand chip info structure
2048  * @buf: data buffer
2049  * @oob_required: must write chip->oob_poi to OOB
2050  *
2051  * We need a special oob layout and handling even when ECC isn't checked.
2052  */
2053 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2054                                         struct nand_chip *chip,
2055                                         const uint8_t *buf, int oob_required)
2056 {
2057         int eccsize = chip->ecc.size;
2058         int eccbytes = chip->ecc.bytes;
2059         uint8_t *oob = chip->oob_poi;
2060         int steps, size;
2061
2062         for (steps = chip->ecc.steps; steps > 0; steps--) {
2063                 chip->write_buf(mtd, buf, eccsize);
2064                 buf += eccsize;
2065
2066                 if (chip->ecc.prepad) {
2067                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2068                         oob += chip->ecc.prepad;
2069                 }
2070
2071                 chip->write_buf(mtd, oob, eccbytes);
2072                 oob += eccbytes;
2073
2074                 if (chip->ecc.postpad) {
2075                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2076                         oob += chip->ecc.postpad;
2077                 }
2078         }
2079
2080         size = mtd->oobsize - (oob - chip->oob_poi);
2081         if (size)
2082                 chip->write_buf(mtd, oob, size);
2083
2084         return 0;
2085 }
2086 /**
2087  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2088  * @mtd: mtd info structure
2089  * @chip: nand chip info structure
2090  * @buf: data buffer
2091  * @oob_required: must write chip->oob_poi to OOB
2092  */
2093 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2094                                   const uint8_t *buf, int oob_required)
2095 {
2096         int i, eccsize = chip->ecc.size;
2097         int eccbytes = chip->ecc.bytes;
2098         int eccsteps = chip->ecc.steps;
2099         uint8_t *ecc_calc = chip->buffers->ecccalc;
2100         const uint8_t *p = buf;
2101         uint32_t *eccpos = chip->ecc.layout->eccpos;
2102
2103         /* Software ECC calculation */
2104         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2105                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2106
2107         for (i = 0; i < chip->ecc.total; i++)
2108                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2109
2110         return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2111 }
2112
2113 /**
2114  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2115  * @mtd: mtd info structure
2116  * @chip: nand chip info structure
2117  * @buf: data buffer
2118  * @oob_required: must write chip->oob_poi to OOB
2119  */
2120 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2121                                   const uint8_t *buf, int oob_required)
2122 {
2123         int i, eccsize = chip->ecc.size;
2124         int eccbytes = chip->ecc.bytes;
2125         int eccsteps = chip->ecc.steps;
2126         uint8_t *ecc_calc = chip->buffers->ecccalc;
2127         const uint8_t *p = buf;
2128         uint32_t *eccpos = chip->ecc.layout->eccpos;
2129
2130         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2131                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2132                 chip->write_buf(mtd, p, eccsize);
2133                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2134         }
2135
2136         for (i = 0; i < chip->ecc.total; i++)
2137                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2138
2139         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2140
2141         return 0;
2142 }
2143
2144
2145 /**
2146  * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2147  * @mtd:        mtd info structure
2148  * @chip:       nand chip info structure
2149  * @offset:     column address of subpage within the page
2150  * @data_len:   data length
2151  * @buf:        data buffer
2152  * @oob_required: must write chip->oob_poi to OOB
2153  */
2154 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2155                                 struct nand_chip *chip, uint32_t offset,
2156                                 uint32_t data_len, const uint8_t *buf,
2157                                 int oob_required)
2158 {
2159         uint8_t *oob_buf  = chip->oob_poi;
2160         uint8_t *ecc_calc = chip->buffers->ecccalc;
2161         int ecc_size      = chip->ecc.size;
2162         int ecc_bytes     = chip->ecc.bytes;
2163         int ecc_steps     = chip->ecc.steps;
2164         uint32_t *eccpos  = chip->ecc.layout->eccpos;
2165         uint32_t start_step = offset / ecc_size;
2166         uint32_t end_step   = (offset + data_len - 1) / ecc_size;
2167         int oob_bytes       = mtd->oobsize / ecc_steps;
2168         int step, i;
2169
2170         for (step = 0; step < ecc_steps; step++) {
2171                 /* configure controller for WRITE access */
2172                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2173
2174                 /* write data (untouched subpages already masked by 0xFF) */
2175                 chip->write_buf(mtd, buf, ecc_size);
2176
2177                 /* mask ECC of un-touched subpages by padding 0xFF */
2178                 if ((step < start_step) || (step > end_step))
2179                         memset(ecc_calc, 0xff, ecc_bytes);
2180                 else
2181                         chip->ecc.calculate(mtd, buf, ecc_calc);
2182
2183                 /* mask OOB of un-touched subpages by padding 0xFF */
2184                 /* if oob_required, preserve OOB metadata of written subpage */
2185                 if (!oob_required || (step < start_step) || (step > end_step))
2186                         memset(oob_buf, 0xff, oob_bytes);
2187
2188                 buf += ecc_size;
2189                 ecc_calc += ecc_bytes;
2190                 oob_buf  += oob_bytes;
2191         }
2192
2193         /* copy calculated ECC for whole page to chip->buffer->oob */
2194         /* this include masked-value(0xFF) for unwritten subpages */
2195         ecc_calc = chip->buffers->ecccalc;
2196         for (i = 0; i < chip->ecc.total; i++)
2197                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2198
2199         /* write OOB buffer to NAND device */
2200         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2201
2202         return 0;
2203 }
2204
2205
2206 /**
2207  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2208  * @mtd: mtd info structure
2209  * @chip: nand chip info structure
2210  * @buf: data buffer
2211  * @oob_required: must write chip->oob_poi to OOB
2212  *
2213  * The hw generator calculates the error syndrome automatically. Therefore we
2214  * need a special oob layout and handling.
2215  */
2216 static int nand_write_page_syndrome(struct mtd_info *mtd,
2217                                     struct nand_chip *chip,
2218                                     const uint8_t *buf, int oob_required)
2219 {
2220         int i, eccsize = chip->ecc.size;
2221         int eccbytes = chip->ecc.bytes;
2222         int eccsteps = chip->ecc.steps;
2223         const uint8_t *p = buf;
2224         uint8_t *oob = chip->oob_poi;
2225
2226         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2227
2228                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2229                 chip->write_buf(mtd, p, eccsize);
2230
2231                 if (chip->ecc.prepad) {
2232                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2233                         oob += chip->ecc.prepad;
2234                 }
2235
2236                 chip->ecc.calculate(mtd, p, oob);
2237                 chip->write_buf(mtd, oob, eccbytes);
2238                 oob += eccbytes;
2239
2240                 if (chip->ecc.postpad) {
2241                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2242                         oob += chip->ecc.postpad;
2243                 }
2244         }
2245
2246         /* Calculate remaining oob bytes */
2247         i = mtd->oobsize - (oob - chip->oob_poi);
2248         if (i)
2249                 chip->write_buf(mtd, oob, i);
2250
2251         return 0;
2252 }
2253
2254 /**
2255  * nand_write_page - [REPLACEABLE] write one page
2256  * @mtd: MTD device structure
2257  * @chip: NAND chip descriptor
2258  * @offset: address offset within the page
2259  * @data_len: length of actual data to be written
2260  * @buf: the data to write
2261  * @oob_required: must write chip->oob_poi to OOB
2262  * @page: page number to write
2263  * @cached: cached programming
2264  * @raw: use _raw version of write_page
2265  */
2266 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2267                 uint32_t offset, int data_len, const uint8_t *buf,
2268                 int oob_required, int page, int cached, int raw)
2269 {
2270         int status, subpage;
2271
2272         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2273                 chip->ecc.write_subpage)
2274                 subpage = offset || (data_len < mtd->writesize);
2275         else
2276                 subpage = 0;
2277
2278         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2279
2280         if (unlikely(raw))
2281                 status = chip->ecc.write_page_raw(mtd, chip, buf,
2282                                                         oob_required);
2283         else if (subpage)
2284                 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2285                                                          buf, oob_required);
2286         else
2287                 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2288
2289         if (status < 0)
2290                 return status;
2291
2292         /*
2293          * Cached progamming disabled for now. Not sure if it's worth the
2294          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2295          */
2296         cached = 0;
2297
2298         if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2299
2300                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2301                 status = chip->waitfunc(mtd, chip);
2302                 /*
2303                  * See if operation failed and additional status checks are
2304                  * available.
2305                  */
2306                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2307                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2308                                                page);
2309
2310                 if (status & NAND_STATUS_FAIL)
2311                         return -EIO;
2312         } else {
2313                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2314                 status = chip->waitfunc(mtd, chip);
2315         }
2316
2317         return 0;
2318 }
2319
2320 /**
2321  * nand_fill_oob - [INTERN] Transfer client buffer to oob
2322  * @mtd: MTD device structure
2323  * @oob: oob data buffer
2324  * @len: oob data write length
2325  * @ops: oob ops structure
2326  */
2327 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2328                               struct mtd_oob_ops *ops)
2329 {
2330         struct nand_chip *chip = mtd->priv;
2331
2332         /*
2333          * Initialise to all 0xFF, to avoid the possibility of left over OOB
2334          * data from a previous OOB read.
2335          */
2336         memset(chip->oob_poi, 0xff, mtd->oobsize);
2337
2338         switch (ops->mode) {
2339
2340         case MTD_OPS_PLACE_OOB:
2341         case MTD_OPS_RAW:
2342                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2343                 return oob + len;
2344
2345         case MTD_OPS_AUTO_OOB: {
2346                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2347                 uint32_t boffs = 0, woffs = ops->ooboffs;
2348                 size_t bytes = 0;
2349
2350                 for (; free->length && len; free++, len -= bytes) {
2351                         /* Write request not from offset 0? */
2352                         if (unlikely(woffs)) {
2353                                 if (woffs >= free->length) {
2354                                         woffs -= free->length;
2355                                         continue;
2356                                 }
2357                                 boffs = free->offset + woffs;
2358                                 bytes = min_t(size_t, len,
2359                                               (free->length - woffs));
2360                                 woffs = 0;
2361                         } else {
2362                                 bytes = min_t(size_t, len, free->length);
2363                                 boffs = free->offset;
2364                         }
2365                         memcpy(chip->oob_poi + boffs, oob, bytes);
2366                         oob += bytes;
2367                 }
2368                 return oob;
2369         }
2370         default:
2371                 BUG();
2372         }
2373         return NULL;
2374 }
2375
2376 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
2377
2378 /**
2379  * nand_do_write_ops - [INTERN] NAND write with ECC
2380  * @mtd: MTD device structure
2381  * @to: offset to write to
2382  * @ops: oob operations description structure
2383  *
2384  * NAND write with ECC.
2385  */
2386 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2387                              struct mtd_oob_ops *ops)
2388 {
2389         int chipnr, realpage, page, blockmask, column;
2390         struct nand_chip *chip = mtd->priv;
2391         uint32_t writelen = ops->len;
2392
2393         uint32_t oobwritelen = ops->ooblen;
2394         uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2395                                 mtd->oobavail : mtd->oobsize;
2396
2397         uint8_t *oob = ops->oobbuf;
2398         uint8_t *buf = ops->datbuf;
2399         int ret;
2400         int oob_required = oob ? 1 : 0;
2401
2402         ops->retlen = 0;
2403         if (!writelen)
2404                 return 0;
2405
2406         /* Reject writes, which are not page aligned */
2407         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2408                 pr_notice("%s: attempt to write non page aligned data\n",
2409                            __func__);
2410                 return -EINVAL;
2411         }
2412
2413         column = to & (mtd->writesize - 1);
2414
2415         chipnr = (int)(to >> chip->chip_shift);
2416         chip->select_chip(mtd, chipnr);
2417
2418         /* Check, if it is write protected */
2419         if (nand_check_wp(mtd)) {
2420                 ret = -EIO;
2421                 goto err_out;
2422         }
2423
2424         realpage = (int)(to >> chip->page_shift);
2425         page = realpage & chip->pagemask;
2426         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2427
2428         /* Invalidate the page cache, when we write to the cached page */
2429         if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2430             ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
2431                 chip->pagebuf = -1;
2432
2433         /* Don't allow multipage oob writes with offset */
2434         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2435                 ret = -EINVAL;
2436                 goto err_out;
2437         }
2438
2439         while (1) {
2440                 int bytes = mtd->writesize;
2441                 int cached = writelen > bytes && page != blockmask;
2442                 uint8_t *wbuf = buf;
2443                 int use_bufpoi;
2444                 int part_pagewr = (column || writelen < (mtd->writesize - 1));
2445
2446                 if (part_pagewr)
2447                         use_bufpoi = 1;
2448                 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2449                         use_bufpoi = !virt_addr_valid(buf);
2450                 else
2451                         use_bufpoi = 0;
2452
2453                 /* Partial page write?, or need to use bounce buffer */
2454                 if (use_bufpoi) {
2455                         pr_debug("%s: using write bounce buffer for buf@%p\n",
2456                                          __func__, buf);
2457                         cached = 0;
2458                         if (part_pagewr)
2459                                 bytes = min_t(int, bytes - column, writelen);
2460                         chip->pagebuf = -1;
2461                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2462                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2463                         wbuf = chip->buffers->databuf;
2464                 }
2465
2466                 if (unlikely(oob)) {
2467                         size_t len = min(oobwritelen, oobmaxlen);
2468                         oob = nand_fill_oob(mtd, oob, len, ops);
2469                         oobwritelen -= len;
2470                 } else {
2471                         /* We still need to erase leftover OOB data */
2472                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2473                 }
2474                 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2475                                         oob_required, page, cached,
2476                                         (ops->mode == MTD_OPS_RAW));
2477                 if (ret)
2478                         break;
2479
2480                 writelen -= bytes;
2481                 if (!writelen)
2482                         break;
2483
2484                 column = 0;
2485                 buf += bytes;
2486                 realpage++;
2487
2488                 page = realpage & chip->pagemask;
2489                 /* Check, if we cross a chip boundary */
2490                 if (!page) {
2491                         chipnr++;
2492                         chip->select_chip(mtd, -1);
2493                         chip->select_chip(mtd, chipnr);
2494                 }
2495         }
2496
2497         ops->retlen = ops->len - writelen;
2498         if (unlikely(oob))
2499                 ops->oobretlen = ops->ooblen;
2500
2501 err_out:
2502         chip->select_chip(mtd, -1);
2503         return ret;
2504 }
2505
2506 /**
2507  * panic_nand_write - [MTD Interface] NAND write with ECC
2508  * @mtd: MTD device structure
2509  * @to: offset to write to
2510  * @len: number of bytes to write
2511  * @retlen: pointer to variable to store the number of written bytes
2512  * @buf: the data to write
2513  *
2514  * NAND write with ECC. Used when performing writes in interrupt context, this
2515  * may for example be called by mtdoops when writing an oops while in panic.
2516  */
2517 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2518                             size_t *retlen, const uint8_t *buf)
2519 {
2520         struct nand_chip *chip = mtd->priv;
2521         struct mtd_oob_ops ops;
2522         int ret;
2523
2524         /* Wait for the device to get ready */
2525         panic_nand_wait(mtd, chip, 400);
2526
2527         /* Grab the device */
2528         panic_nand_get_device(chip, mtd, FL_WRITING);
2529
2530         memset(&ops, 0, sizeof(ops));
2531         ops.len = len;
2532         ops.datbuf = (uint8_t *)buf;
2533         ops.mode = MTD_OPS_PLACE_OOB;
2534
2535         ret = nand_do_write_ops(mtd, to, &ops);
2536
2537         *retlen = ops.retlen;
2538         return ret;
2539 }
2540
2541 /**
2542  * nand_write - [MTD Interface] NAND write with ECC
2543  * @mtd: MTD device structure
2544  * @to: offset to write to
2545  * @len: number of bytes to write
2546  * @retlen: pointer to variable to store the number of written bytes
2547  * @buf: the data to write
2548  *
2549  * NAND write with ECC.
2550  */
2551 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2552                           size_t *retlen, const uint8_t *buf)
2553 {
2554         struct mtd_oob_ops ops;
2555         int ret;
2556
2557         nand_get_device(mtd, FL_WRITING);
2558         memset(&ops, 0, sizeof(ops));
2559         ops.len = len;
2560         ops.datbuf = (uint8_t *)buf;
2561         ops.mode = MTD_OPS_PLACE_OOB;
2562         ret = nand_do_write_ops(mtd, to, &ops);
2563         *retlen = ops.retlen;
2564         nand_release_device(mtd);
2565         return ret;
2566 }
2567
2568 /**
2569  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2570  * @mtd: MTD device structure
2571  * @to: offset to write to
2572  * @ops: oob operation description structure
2573  *
2574  * NAND write out-of-band.
2575  */
2576 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2577                              struct mtd_oob_ops *ops)
2578 {
2579         int chipnr, page, status, len;
2580         struct nand_chip *chip = mtd->priv;
2581
2582         pr_debug("%s: to = 0x%08x, len = %i\n",
2583                          __func__, (unsigned int)to, (int)ops->ooblen);
2584
2585         if (ops->mode == MTD_OPS_AUTO_OOB)
2586                 len = chip->ecc.layout->oobavail;
2587         else
2588                 len = mtd->oobsize;
2589
2590         /* Do not allow write past end of page */
2591         if ((ops->ooboffs + ops->ooblen) > len) {
2592                 pr_debug("%s: attempt to write past end of page\n",
2593                                 __func__);
2594                 return -EINVAL;
2595         }
2596
2597         if (unlikely(ops->ooboffs >= len)) {
2598                 pr_debug("%s: attempt to start write outside oob\n",
2599                                 __func__);
2600                 return -EINVAL;
2601         }
2602
2603         /* Do not allow write past end of device */
2604         if (unlikely(to >= mtd->size ||
2605                      ops->ooboffs + ops->ooblen >
2606                         ((mtd->size >> chip->page_shift) -
2607                          (to >> chip->page_shift)) * len)) {
2608                 pr_debug("%s: attempt to write beyond end of device\n",
2609                                 __func__);
2610                 return -EINVAL;
2611         }
2612
2613         chipnr = (int)(to >> chip->chip_shift);
2614         chip->select_chip(mtd, chipnr);
2615
2616         /* Shift to get page */
2617         page = (int)(to >> chip->page_shift);
2618
2619         /*
2620          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2621          * of my DiskOnChip 2000 test units) will clear the whole data page too
2622          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2623          * it in the doc2000 driver in August 1999.  dwmw2.
2624          */
2625         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2626
2627         /* Check, if it is write protected */
2628         if (nand_check_wp(mtd)) {
2629                 chip->select_chip(mtd, -1);
2630                 return -EROFS;
2631         }
2632
2633         /* Invalidate the page cache, if we write to the cached page */
2634         if (page == chip->pagebuf)
2635                 chip->pagebuf = -1;
2636
2637         nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2638
2639         if (ops->mode == MTD_OPS_RAW)
2640                 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2641         else
2642                 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2643
2644         chip->select_chip(mtd, -1);
2645
2646         if (status)
2647                 return status;
2648
2649         ops->oobretlen = ops->ooblen;
2650
2651         return 0;
2652 }
2653
2654 /**
2655  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2656  * @mtd: MTD device structure
2657  * @to: offset to write to
2658  * @ops: oob operation description structure
2659  */
2660 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2661                           struct mtd_oob_ops *ops)
2662 {
2663         int ret = -ENOTSUPP;
2664
2665         ops->retlen = 0;
2666
2667         /* Do not allow writes past end of device */
2668         if (ops->datbuf && (to + ops->len) > mtd->size) {
2669                 pr_debug("%s: attempt to write beyond end of device\n",
2670                                 __func__);
2671                 return -EINVAL;
2672         }
2673
2674         nand_get_device(mtd, FL_WRITING);
2675
2676         switch (ops->mode) {
2677         case MTD_OPS_PLACE_OOB:
2678         case MTD_OPS_AUTO_OOB:
2679         case MTD_OPS_RAW:
2680                 break;
2681
2682         default:
2683                 goto out;
2684         }
2685
2686         if (!ops->datbuf)
2687                 ret = nand_do_write_oob(mtd, to, ops);
2688         else
2689                 ret = nand_do_write_ops(mtd, to, ops);
2690
2691 out:
2692         nand_release_device(mtd);
2693         return ret;
2694 }
2695
2696 /**
2697  * single_erase - [GENERIC] NAND standard block erase command function
2698  * @mtd: MTD device structure
2699  * @page: the page address of the block which will be erased
2700  *
2701  * Standard erase command for NAND chips. Returns NAND status.
2702  */
2703 static int single_erase(struct mtd_info *mtd, int page)
2704 {
2705         struct nand_chip *chip = mtd->priv;
2706         /* Send commands to erase a block */
2707         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2708         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2709
2710         return chip->waitfunc(mtd, chip);
2711 }
2712
2713 /**
2714  * nand_erase - [MTD Interface] erase block(s)
2715  * @mtd: MTD device structure
2716  * @instr: erase instruction
2717  *
2718  * Erase one ore more blocks.
2719  */
2720 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2721 {
2722         return nand_erase_nand(mtd, instr, 0);
2723 }
2724
2725 /**
2726  * nand_erase_nand - [INTERN] erase block(s)
2727  * @mtd: MTD device structure
2728  * @instr: erase instruction
2729  * @allowbbt: allow erasing the bbt area
2730  *
2731  * Erase one ore more blocks.
2732  */
2733 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2734                     int allowbbt)
2735 {
2736         int page, status, pages_per_block, ret, chipnr;
2737         struct nand_chip *chip = mtd->priv;
2738         loff_t len;
2739
2740         pr_debug("%s: start = 0x%012llx, len = %llu\n",
2741                         __func__, (unsigned long long)instr->addr,
2742                         (unsigned long long)instr->len);
2743
2744         if (check_offs_len(mtd, instr->addr, instr->len))
2745                 return -EINVAL;
2746
2747         /* Grab the lock and see if the device is available */
2748         nand_get_device(mtd, FL_ERASING);
2749
2750         /* Shift to get first page */
2751         page = (int)(instr->addr >> chip->page_shift);
2752         chipnr = (int)(instr->addr >> chip->chip_shift);
2753
2754         /* Calculate pages in each block */
2755         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2756
2757         /* Select the NAND device */
2758         chip->select_chip(mtd, chipnr);
2759
2760         /* Check, if it is write protected */
2761         if (nand_check_wp(mtd)) {
2762                 pr_debug("%s: device is write protected!\n",
2763                                 __func__);
2764                 instr->state = MTD_ERASE_FAILED;
2765                 goto erase_exit;
2766         }
2767
2768         /* Loop through the pages */
2769         len = instr->len;
2770
2771         instr->state = MTD_ERASING;
2772
2773         while (len) {
2774                 /* Check if we have a bad block, we do not erase bad blocks! */
2775                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2776                                         chip->page_shift, 0, allowbbt)) {
2777                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2778                                     __func__, page);
2779                         instr->state = MTD_ERASE_FAILED;
2780                         goto erase_exit;
2781                 }
2782
2783                 /*
2784                  * Invalidate the page cache, if we erase the block which
2785                  * contains the current cached page.
2786                  */
2787                 if (page <= chip->pagebuf && chip->pagebuf <
2788                     (page + pages_per_block))
2789                         chip->pagebuf = -1;
2790
2791                 status = chip->erase(mtd, page & chip->pagemask);
2792
2793                 /*
2794                  * See if operation failed and additional status checks are
2795                  * available
2796                  */
2797                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2798                         status = chip->errstat(mtd, chip, FL_ERASING,
2799                                                status, page);
2800
2801                 /* See if block erase succeeded */
2802                 if (status & NAND_STATUS_FAIL) {
2803                         pr_debug("%s: failed erase, page 0x%08x\n",
2804                                         __func__, page);
2805                         instr->state = MTD_ERASE_FAILED;
2806                         instr->fail_addr =
2807                                 ((loff_t)page << chip->page_shift);
2808                         goto erase_exit;
2809                 }
2810
2811                 /* Increment page address and decrement length */
2812                 len -= (1ULL << chip->phys_erase_shift);
2813                 page += pages_per_block;
2814
2815                 /* Check, if we cross a chip boundary */
2816                 if (len && !(page & chip->pagemask)) {
2817                         chipnr++;
2818                         chip->select_chip(mtd, -1);
2819                         chip->select_chip(mtd, chipnr);
2820                 }
2821         }
2822         instr->state = MTD_ERASE_DONE;
2823
2824 erase_exit:
2825
2826         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2827
2828         /* Deselect and wake up anyone waiting on the device */
2829         chip->select_chip(mtd, -1);
2830         nand_release_device(mtd);
2831
2832         /* Do call back function */
2833         if (!ret)
2834                 mtd_erase_callback(instr);
2835
2836         /* Return more or less happy */
2837         return ret;
2838 }
2839
2840 /**
2841  * nand_sync - [MTD Interface] sync
2842  * @mtd: MTD device structure
2843  *
2844  * Sync is actually a wait for chip ready function.
2845  */
2846 static void nand_sync(struct mtd_info *mtd)
2847 {
2848         pr_debug("%s: called\n", __func__);
2849
2850         /* Grab the lock and see if the device is available */
2851         nand_get_device(mtd, FL_SYNCING);
2852         /* Release it and go back */
2853         nand_release_device(mtd);
2854 }
2855
2856 /**
2857  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2858  * @mtd: MTD device structure
2859  * @offs: offset relative to mtd start
2860  */
2861 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2862 {
2863         return nand_block_checkbad(mtd, offs, 1, 0);
2864 }
2865
2866 /**
2867  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2868  * @mtd: MTD device structure
2869  * @ofs: offset relative to mtd start
2870  */
2871 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2872 {
2873         int ret;
2874
2875         ret = nand_block_isbad(mtd, ofs);
2876         if (ret) {
2877                 /* If it was bad already, return success and do nothing */
2878                 if (ret > 0)
2879                         return 0;
2880                 return ret;
2881         }
2882
2883         return nand_block_markbad_lowlevel(mtd, ofs);
2884 }
2885
2886 /**
2887  * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2888  * @mtd: MTD device structure
2889  * @chip: nand chip info structure
2890  * @addr: feature address.
2891  * @subfeature_param: the subfeature parameters, a four bytes array.
2892  */
2893 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2894                         int addr, uint8_t *subfeature_param)
2895 {
2896         int status;
2897         int i;
2898
2899         if (!chip->onfi_version ||
2900             !(le16_to_cpu(chip->onfi_params.opt_cmd)
2901               & ONFI_OPT_CMD_SET_GET_FEATURES))
2902                 return -EINVAL;
2903
2904         chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2905         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2906                 chip->write_byte(mtd, subfeature_param[i]);
2907
2908         status = chip->waitfunc(mtd, chip);
2909         if (status & NAND_STATUS_FAIL)
2910                 return -EIO;
2911         return 0;
2912 }
2913
2914 /**
2915  * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2916  * @mtd: MTD device structure
2917  * @chip: nand chip info structure
2918  * @addr: feature address.
2919  * @subfeature_param: the subfeature parameters, a four bytes array.
2920  */
2921 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2922                         int addr, uint8_t *subfeature_param)
2923 {
2924         int i;
2925
2926         if (!chip->onfi_version ||
2927             !(le16_to_cpu(chip->onfi_params.opt_cmd)
2928               & ONFI_OPT_CMD_SET_GET_FEATURES))
2929                 return -EINVAL;
2930
2931         /* clear the sub feature parameters */
2932         memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2933
2934         chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2935         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2936                 *subfeature_param++ = chip->read_byte(mtd);
2937         return 0;
2938 }
2939
2940 /**
2941  * nand_suspend - [MTD Interface] Suspend the NAND flash
2942  * @mtd: MTD device structure
2943  */
2944 static int nand_suspend(struct mtd_info *mtd)
2945 {
2946         return nand_get_device(mtd, FL_PM_SUSPENDED);
2947 }
2948
2949 /**
2950  * nand_resume - [MTD Interface] Resume the NAND flash
2951  * @mtd: MTD device structure
2952  */
2953 static void nand_resume(struct mtd_info *mtd)
2954 {
2955         struct nand_chip *chip = mtd->priv;
2956
2957         if (chip->state == FL_PM_SUSPENDED)
2958                 nand_release_device(mtd);
2959         else
2960                 pr_err("%s called for a chip which is not in suspended state\n",
2961                         __func__);
2962 }
2963
2964 /**
2965  * nand_shutdown - [MTD Interface] Finish the current NAND operation and
2966  *                 prevent further operations
2967  * @mtd: MTD device structure
2968  */
2969 static void nand_shutdown(struct mtd_info *mtd)
2970 {
2971         nand_get_device(mtd, FL_SHUTDOWN);
2972 }
2973
2974 /* Set default functions */
2975 static void nand_set_defaults(struct nand_chip *chip, int busw)
2976 {
2977         /* check for proper chip_delay setup, set 20us if not */
2978         if (!chip->chip_delay)
2979                 chip->chip_delay = 20;
2980
2981         /* check, if a user supplied command function given */
2982         if (chip->cmdfunc == NULL)
2983                 chip->cmdfunc = nand_command;
2984
2985         /* check, if a user supplied wait function given */
2986         if (chip->waitfunc == NULL)
2987                 chip->waitfunc = nand_wait;
2988
2989         if (!chip->select_chip)
2990                 chip->select_chip = nand_select_chip;
2991
2992         /* set for ONFI nand */
2993         if (!chip->onfi_set_features)
2994                 chip->onfi_set_features = nand_onfi_set_features;
2995         if (!chip->onfi_get_features)
2996                 chip->onfi_get_features = nand_onfi_get_features;
2997
2998         /* If called twice, pointers that depend on busw may need to be reset */
2999         if (!chip->read_byte || chip->read_byte == nand_read_byte)
3000                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3001         if (!chip->read_word)
3002                 chip->read_word = nand_read_word;
3003         if (!chip->block_bad)
3004                 chip->block_bad = nand_block_bad;
3005         if (!chip->block_markbad)
3006                 chip->block_markbad = nand_default_block_markbad;
3007         if (!chip->write_buf || chip->write_buf == nand_write_buf)
3008                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3009         if (!chip->write_byte || chip->write_byte == nand_write_byte)
3010                 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3011         if (!chip->read_buf || chip->read_buf == nand_read_buf)
3012                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3013         if (!chip->scan_bbt)
3014                 chip->scan_bbt = nand_default_bbt;
3015
3016         if (!chip->controller) {
3017                 chip->controller = &chip->hwcontrol;
3018                 spin_lock_init(&chip->controller->lock);
3019                 init_waitqueue_head(&chip->controller->wq);
3020         }
3021
3022 }
3023
3024 /* Sanitize ONFI strings so we can safely print them */
3025 static void sanitize_string(uint8_t *s, size_t len)
3026 {
3027         ssize_t i;
3028
3029         /* Null terminate */
3030         s[len - 1] = 0;
3031
3032         /* Remove non printable chars */
3033         for (i = 0; i < len - 1; i++) {
3034                 if (s[i] < ' ' || s[i] > 127)
3035                         s[i] = '?';
3036         }
3037
3038         /* Remove trailing spaces */
3039         strim(s);
3040 }
3041
3042 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3043 {
3044         int i;
3045         while (len--) {
3046                 crc ^= *p++ << 8;
3047                 for (i = 0; i < 8; i++)
3048                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3049         }
3050
3051         return crc;
3052 }
3053
3054 /* Parse the Extended Parameter Page. */
3055 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3056                 struct nand_chip *chip, struct nand_onfi_params *p)
3057 {
3058         struct onfi_ext_param_page *ep;
3059         struct onfi_ext_section *s;
3060         struct onfi_ext_ecc_info *ecc;
3061         uint8_t *cursor;
3062         int ret = -EINVAL;
3063         int len;
3064         int i;
3065
3066         len = le16_to_cpu(p->ext_param_page_length) * 16;
3067         ep = kmalloc(len, GFP_KERNEL);
3068         if (!ep)
3069                 return -ENOMEM;
3070
3071         /* Send our own NAND_CMD_PARAM. */
3072         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3073
3074         /* Use the Change Read Column command to skip the ONFI param pages. */
3075         chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3076                         sizeof(*p) * p->num_of_param_pages , -1);
3077
3078         /* Read out the Extended Parameter Page. */
3079         chip->read_buf(mtd, (uint8_t *)ep, len);
3080         if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3081                 != le16_to_cpu(ep->crc))) {
3082                 pr_debug("fail in the CRC.\n");
3083                 goto ext_out;
3084         }
3085
3086         /*
3087          * Check the signature.
3088          * Do not strictly follow the ONFI spec, maybe changed in future.
3089          */
3090         if (strncmp(ep->sig, "EPPS", 4)) {
3091                 pr_debug("The signature is invalid.\n");
3092                 goto ext_out;
3093         }
3094
3095         /* find the ECC section. */
3096         cursor = (uint8_t *)(ep + 1);
3097         for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3098                 s = ep->sections + i;
3099                 if (s->type == ONFI_SECTION_TYPE_2)
3100                         break;
3101                 cursor += s->length * 16;
3102         }
3103         if (i == ONFI_EXT_SECTION_MAX) {
3104                 pr_debug("We can not find the ECC section.\n");
3105                 goto ext_out;
3106         }
3107
3108         /* get the info we want. */
3109         ecc = (struct onfi_ext_ecc_info *)cursor;
3110
3111         if (!ecc->codeword_size) {
3112                 pr_debug("Invalid codeword size\n");
3113                 goto ext_out;
3114         }
3115
3116         chip->ecc_strength_ds = ecc->ecc_bits;
3117         chip->ecc_step_ds = 1 << ecc->codeword_size;
3118         ret = 0;
3119
3120 ext_out:
3121         kfree(ep);
3122         return ret;
3123 }
3124
3125 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3126 {
3127         struct nand_chip *chip = mtd->priv;
3128         uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3129
3130         return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3131                         feature);
3132 }
3133
3134 /*
3135  * Configure chip properties from Micron vendor-specific ONFI table
3136  */
3137 static void nand_onfi_detect_micron(struct nand_chip *chip,
3138                 struct nand_onfi_params *p)
3139 {
3140         struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3141
3142         if (le16_to_cpu(p->vendor_revision) < 1)
3143                 return;
3144
3145         chip->read_retries = micron->read_retry_options;
3146         chip->setup_read_retry = nand_setup_read_retry_micron;
3147 }
3148
3149 /*
3150  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3151  */
3152 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3153                                         int *busw)
3154 {
3155         struct nand_onfi_params *p = &chip->onfi_params;
3156         int i, j;
3157         int val;
3158
3159         /* Try ONFI for unknown chip or LP */
3160         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3161         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3162                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3163                 return 0;
3164
3165         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3166         for (i = 0; i < 3; i++) {
3167                 for (j = 0; j < sizeof(*p); j++)
3168                         ((uint8_t *)p)[j] = chip->read_byte(mtd);
3169                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3170                                 le16_to_cpu(p->crc)) {
3171                         break;
3172                 }
3173         }
3174
3175         if (i == 3) {
3176                 pr_err("Could not find valid ONFI parameter page; aborting\n");
3177                 return 0;
3178         }
3179
3180         /* Check version */
3181         val = le16_to_cpu(p->revision);
3182         if (val & (1 << 5))
3183                 chip->onfi_version = 23;
3184         else if (val & (1 << 4))
3185                 chip->onfi_version = 22;
3186         else if (val & (1 << 3))
3187                 chip->onfi_version = 21;
3188         else if (val & (1 << 2))
3189                 chip->onfi_version = 20;
3190         else if (val & (1 << 1))
3191                 chip->onfi_version = 10;
3192
3193         if (!chip->onfi_version) {
3194                 pr_info("unsupported ONFI version: %d\n", val);
3195                 return 0;
3196         }
3197
3198         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3199         sanitize_string(p->model, sizeof(p->model));
3200         if (!mtd->name)
3201                 mtd->name = p->model;
3202
3203         mtd->writesize = le32_to_cpu(p->byte_per_page);
3204
3205         /*
3206          * pages_per_block and blocks_per_lun may not be a power-of-2 size
3207          * (don't ask me who thought of this...). MTD assumes that these
3208          * dimensions will be power-of-2, so just truncate the remaining area.
3209          */
3210         mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3211         mtd->erasesize *= mtd->writesize;
3212
3213         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3214
3215         /* See erasesize comment */
3216         chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3217         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3218         chip->bits_per_cell = p->bits_per_cell;
3219
3220         if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3221                 *busw = NAND_BUSWIDTH_16;
3222         else
3223                 *busw = 0;
3224
3225         if (p->ecc_bits != 0xff) {
3226                 chip->ecc_strength_ds = p->ecc_bits;
3227                 chip->ecc_step_ds = 512;
3228         } else if (chip->onfi_version >= 21 &&
3229                 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3230
3231                 /*
3232                  * The nand_flash_detect_ext_param_page() uses the
3233                  * Change Read Column command which maybe not supported
3234                  * by the chip->cmdfunc. So try to update the chip->cmdfunc
3235                  * now. We do not replace user supplied command function.
3236                  */
3237                 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3238                         chip->cmdfunc = nand_command_lp;
3239
3240                 /* The Extended Parameter Page is supported since ONFI 2.1. */
3241                 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3242                         pr_warn("Failed to detect ONFI extended param page\n");
3243         } else {
3244                 pr_warn("Could not retrieve ONFI ECC requirements\n");
3245         }
3246
3247         if (p->jedec_id == NAND_MFR_MICRON)
3248                 nand_onfi_detect_micron(chip, p);
3249
3250         return 1;
3251 }
3252
3253 /*
3254  * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3255  */
3256 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3257                                         int *busw)
3258 {
3259         struct nand_jedec_params *p = &chip->jedec_params;
3260         struct jedec_ecc_info *ecc;
3261         int val;
3262         int i, j;
3263
3264         /* Try JEDEC for unknown chip or LP */
3265         chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3266         if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3267                 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3268                 chip->read_byte(mtd) != 'C')
3269                 return 0;
3270
3271         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3272         for (i = 0; i < 3; i++) {
3273                 for (j = 0; j < sizeof(*p); j++)
3274                         ((uint8_t *)p)[j] = chip->read_byte(mtd);
3275
3276                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3277                                 le16_to_cpu(p->crc))
3278                         break;
3279         }
3280
3281         if (i == 3) {
3282                 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3283                 return 0;
3284         }
3285
3286         /* Check version */
3287         val = le16_to_cpu(p->revision);
3288         if (val & (1 << 2))
3289                 chip->jedec_version = 10;
3290         else if (val & (1 << 1))
3291                 chip->jedec_version = 1; /* vendor specific version */
3292
3293         if (!chip->jedec_version) {
3294                 pr_info("unsupported JEDEC version: %d\n", val);
3295                 return 0;
3296         }
3297
3298         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3299         sanitize_string(p->model, sizeof(p->model));
3300         if (!mtd->name)
3301                 mtd->name = p->model;
3302
3303         mtd->writesize = le32_to_cpu(p->byte_per_page);
3304
3305         /* Please reference to the comment for nand_flash_detect_onfi. */
3306         mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3307         mtd->erasesize *= mtd->writesize;
3308
3309         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3310
3311         /* Please reference to the comment for nand_flash_detect_onfi. */
3312         chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3313         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3314         chip->bits_per_cell = p->bits_per_cell;
3315
3316         if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3317                 *busw = NAND_BUSWIDTH_16;
3318         else
3319                 *busw = 0;
3320
3321         /* ECC info */
3322         ecc = &p->ecc_info[0];
3323
3324         if (ecc->codeword_size >= 9) {
3325                 chip->ecc_strength_ds = ecc->ecc_bits;
3326                 chip->ecc_step_ds = 1 << ecc->codeword_size;
3327         } else {
3328                 pr_warn("Invalid codeword size\n");
3329         }
3330
3331         return 1;
3332 }
3333
3334 /*
3335  * nand_id_has_period - Check if an ID string has a given wraparound period
3336  * @id_data: the ID string
3337  * @arrlen: the length of the @id_data array
3338  * @period: the period of repitition
3339  *
3340  * Check if an ID string is repeated within a given sequence of bytes at
3341  * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3342  * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3343  * if the repetition has a period of @period; otherwise, returns zero.
3344  */
3345 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3346 {
3347         int i, j;
3348         for (i = 0; i < period; i++)
3349                 for (j = i + period; j < arrlen; j += period)
3350                         if (id_data[i] != id_data[j])
3351                                 return 0;
3352         return 1;
3353 }
3354
3355 /*
3356  * nand_id_len - Get the length of an ID string returned by CMD_READID
3357  * @id_data: the ID string
3358  * @arrlen: the length of the @id_data array
3359
3360  * Returns the length of the ID string, according to known wraparound/trailing
3361  * zero patterns. If no pattern exists, returns the length of the array.
3362  */
3363 static int nand_id_len(u8 *id_data, int arrlen)
3364 {
3365         int last_nonzero, period;
3366
3367         /* Find last non-zero byte */
3368         for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3369                 if (id_data[last_nonzero])
3370                         break;
3371
3372         /* All zeros */
3373         if (last_nonzero < 0)
3374                 return 0;
3375
3376         /* Calculate wraparound period */
3377         for (period = 1; period < arrlen; period++)
3378                 if (nand_id_has_period(id_data, arrlen, period))
3379                         break;
3380
3381         /* There's a repeated pattern */
3382         if (period < arrlen)
3383                 return period;
3384
3385         /* There are trailing zeros */
3386         if (last_nonzero < arrlen - 1)
3387                 return last_nonzero + 1;
3388
3389         /* No pattern detected */
3390         return arrlen;
3391 }
3392
3393 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3394 static int nand_get_bits_per_cell(u8 cellinfo)
3395 {
3396         int bits;
3397
3398         bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3399         bits >>= NAND_CI_CELLTYPE_SHIFT;
3400         return bits + 1;
3401 }
3402
3403 /*
3404  * Many new NAND share similar device ID codes, which represent the size of the
3405  * chip. The rest of the parameters must be decoded according to generic or
3406  * manufacturer-specific "extended ID" decoding patterns.
3407  */
3408 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3409                                 u8 id_data[8], int *busw)
3410 {
3411         int extid, id_len;
3412         /* The 3rd id byte holds MLC / multichip data */
3413         chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3414         /* The 4th id byte is the important one */
3415         extid = id_data[3];
3416
3417         id_len = nand_id_len(id_data, 8);
3418
3419         /*
3420          * Field definitions are in the following datasheets:
3421          * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3422          * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3423          * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
3424          *
3425          * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3426          * ID to decide what to do.
3427          */
3428         if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3429                         !nand_is_slc(chip) && id_data[5] != 0x00) {
3430                 /* Calc pagesize */
3431                 mtd->writesize = 2048 << (extid & 0x03);
3432                 extid >>= 2;
3433                 /* Calc oobsize */
3434                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3435                 case 1:
3436                         mtd->oobsize = 128;
3437                         break;
3438                 case 2:
3439                         mtd->oobsize = 218;
3440                         break;
3441                 case 3:
3442                         mtd->oobsize = 400;
3443                         break;
3444                 case 4:
3445                         mtd->oobsize = 436;
3446                         break;
3447                 case 5:
3448                         mtd->oobsize = 512;
3449                         break;
3450                 case 6:
3451                         mtd->oobsize = 640;
3452                         break;
3453                 case 7:
3454                 default: /* Other cases are "reserved" (unknown) */
3455                         mtd->oobsize = 1024;
3456                         break;
3457                 }
3458                 extid >>= 2;
3459                 /* Calc blocksize */
3460                 mtd->erasesize = (128 * 1024) <<
3461                         (((extid >> 1) & 0x04) | (extid & 0x03));
3462                 *busw = 0;
3463         } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3464                         !nand_is_slc(chip)) {
3465                 unsigned int tmp;
3466
3467                 /* Calc pagesize */
3468                 mtd->writesize = 2048 << (extid & 0x03);
3469                 extid >>= 2;
3470                 /* Calc oobsize */
3471                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3472                 case 0:
3473                         mtd->oobsize = 128;
3474                         break;
3475                 case 1:
3476                         mtd->oobsize = 224;
3477                         break;
3478                 case 2:
3479                         mtd->oobsize = 448;
3480                         break;
3481                 case 3:
3482                         mtd->oobsize = 64;
3483                         break;
3484                 case 4:
3485                         mtd->oobsize = 32;
3486                         break;
3487                 case 5:
3488                         mtd->oobsize = 16;
3489                         break;
3490                 default:
3491                         mtd->oobsize = 640;
3492                         break;
3493                 }
3494                 extid >>= 2;
3495                 /* Calc blocksize */
3496                 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3497                 if (tmp < 0x03)
3498                         mtd->erasesize = (128 * 1024) << tmp;
3499                 else if (tmp == 0x03)
3500                         mtd->erasesize = 768 * 1024;
3501                 else
3502                         mtd->erasesize = (64 * 1024) << tmp;
3503                 *busw = 0;
3504         } else {
3505                 /* Calc pagesize */
3506                 mtd->writesize = 1024 << (extid & 0x03);
3507                 extid >>= 2;
3508                 /* Calc oobsize */
3509                 mtd->oobsize = (8 << (extid & 0x01)) *
3510                         (mtd->writesize >> 9);
3511                 extid >>= 2;
3512                 /* Calc blocksize. Blocksize is multiples of 64KiB */
3513                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3514                 extid >>= 2;
3515                 /* Get buswidth information */
3516                 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3517
3518                 /*
3519                  * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3520                  * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3521                  * follows:
3522                  * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3523                  *                         110b -> 24nm
3524                  * - ID byte 5, bit[7]:    1 -> BENAND, 0 -> raw SLC
3525                  */
3526                 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3527                                 nand_is_slc(chip) &&
3528                                 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3529                                 !(id_data[4] & 0x80) /* !BENAND */) {
3530                         mtd->oobsize = 32 * mtd->writesize >> 9;
3531                 }
3532
3533         }
3534 }
3535
3536 /*
3537  * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3538  * decodes a matching ID table entry and assigns the MTD size parameters for
3539  * the chip.
3540  */
3541 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3542                                 struct nand_flash_dev *type, u8 id_data[8],
3543                                 int *busw)
3544 {
3545         int maf_id = id_data[0];
3546
3547         mtd->erasesize = type->erasesize;
3548         mtd->writesize = type->pagesize;
3549         mtd->oobsize = mtd->writesize / 32;
3550         *busw = type->options & NAND_BUSWIDTH_16;
3551
3552         /* All legacy ID NAND are small-page, SLC */
3553         chip->bits_per_cell = 1;
3554
3555         /*
3556          * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3557          * some Spansion chips have erasesize that conflicts with size
3558          * listed in nand_ids table.
3559          * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3560          */
3561         if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3562                         && id_data[6] == 0x00 && id_data[7] == 0x00
3563                         && mtd->writesize == 512) {
3564                 mtd->erasesize = 128 * 1024;
3565                 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3566         }
3567 }
3568
3569 /*
3570  * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3571  * heuristic patterns using various detected parameters (e.g., manufacturer,
3572  * page size, cell-type information).
3573  */
3574 static void nand_decode_bbm_options(struct mtd_info *mtd,
3575                                     struct nand_chip *chip, u8 id_data[8])
3576 {
3577         int maf_id = id_data[0];
3578
3579         /* Set the bad block position */
3580         if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3581                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3582         else
3583                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3584
3585         /*
3586          * Bad block marker is stored in the last page of each block on Samsung
3587          * and Hynix MLC devices; stored in first two pages of each block on
3588          * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3589          * AMD/Spansion, and Macronix.  All others scan only the first page.
3590          */
3591         if (!nand_is_slc(chip) &&
3592                         (maf_id == NAND_MFR_SAMSUNG ||
3593                          maf_id == NAND_MFR_HYNIX))
3594                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3595         else if ((nand_is_slc(chip) &&
3596                                 (maf_id == NAND_MFR_SAMSUNG ||
3597                                  maf_id == NAND_MFR_HYNIX ||
3598                                  maf_id == NAND_MFR_TOSHIBA ||
3599                                  maf_id == NAND_MFR_AMD ||
3600                                  maf_id == NAND_MFR_MACRONIX)) ||
3601                         (mtd->writesize == 2048 &&
3602                          maf_id == NAND_MFR_MICRON))
3603                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3604 }
3605
3606 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3607 {
3608         return type->id_len;
3609 }
3610
3611 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3612                    struct nand_flash_dev *type, u8 *id_data, int *busw)
3613 {
3614         if (!strncmp(type->id, id_data, type->id_len)) {
3615                 mtd->writesize = type->pagesize;
3616                 mtd->erasesize = type->erasesize;
3617                 mtd->oobsize = type->oobsize;
3618
3619                 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3620                 chip->chipsize = (uint64_t)type->chipsize << 20;
3621                 chip->options |= type->options;
3622                 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3623                 chip->ecc_step_ds = NAND_ECC_STEP(type);
3624                 chip->onfi_timing_mode_default =
3625                                         type->onfi_timing_mode_default;
3626
3627                 *busw = type->options & NAND_BUSWIDTH_16;
3628
3629                 if (!mtd->name)
3630                         mtd->name = type->name;
3631
3632                 return true;
3633         }
3634         return false;
3635 }
3636
3637 /*
3638  * Get the flash and manufacturer id and lookup if the type is supported.
3639  */
3640 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3641                                                   struct nand_chip *chip,
3642                                                   int *maf_id, int *dev_id,
3643                                                   struct nand_flash_dev *type)
3644 {
3645         int busw;
3646         int i, maf_idx;
3647         u8 id_data[8];
3648
3649         /* Select the device */
3650         chip->select_chip(mtd, 0);
3651
3652         /*
3653          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3654          * after power-up.
3655          */
3656         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3657
3658         /* Send the command for reading device ID */
3659         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3660
3661         /* Read manufacturer and device IDs */
3662         *maf_id = chip->read_byte(mtd);
3663         *dev_id = chip->read_byte(mtd);
3664
3665         /*
3666          * Try again to make sure, as some systems the bus-hold or other
3667          * interface concerns can cause random data which looks like a
3668          * possibly credible NAND flash to appear. If the two results do
3669          * not match, ignore the device completely.
3670          */
3671
3672         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3673
3674         /* Read entire ID string */
3675         for (i = 0; i < 8; i++)
3676                 id_data[i] = chip->read_byte(mtd);
3677
3678         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3679                 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3680                         *maf_id, *dev_id, id_data[0], id_data[1]);
3681                 return ERR_PTR(-ENODEV);
3682         }
3683
3684         if (!type)
3685                 type = nand_flash_ids;
3686
3687         for (; type->name != NULL; type++) {
3688                 if (is_full_id_nand(type)) {
3689                         if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3690                                 goto ident_done;
3691                 } else if (*dev_id == type->dev_id) {
3692                                 break;
3693                 }
3694         }
3695
3696         chip->onfi_version = 0;
3697         if (!type->name || !type->pagesize) {
3698                 /* Check if the chip is ONFI compliant */
3699                 if (nand_flash_detect_onfi(mtd, chip, &busw))
3700                         goto ident_done;
3701
3702                 /* Check if the chip is JEDEC compliant */
3703                 if (nand_flash_detect_jedec(mtd, chip, &busw))
3704                         goto ident_done;
3705         }
3706
3707         if (!type->name)
3708                 return ERR_PTR(-ENODEV);
3709
3710         if (!mtd->name)
3711                 mtd->name = type->name;
3712
3713         chip->chipsize = (uint64_t)type->chipsize << 20;
3714
3715         if (!type->pagesize && chip->init_size) {
3716                 /* Set the pagesize, oobsize, erasesize by the driver */
3717                 busw = chip->init_size(mtd, chip, id_data);
3718         } else if (!type->pagesize) {
3719                 /* Decode parameters from extended ID */
3720                 nand_decode_ext_id(mtd, chip, id_data, &busw);
3721         } else {
3722                 nand_decode_id(mtd, chip, type, id_data, &busw);
3723         }
3724         /* Get chip options */
3725         chip->options |= type->options;
3726
3727         /*
3728          * Check if chip is not a Samsung device. Do not clear the
3729          * options for chips which do not have an extended id.
3730          */
3731         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3732                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3733 ident_done:
3734
3735         /* Try to identify manufacturer */
3736         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3737                 if (nand_manuf_ids[maf_idx].id == *maf_id)
3738                         break;
3739         }
3740
3741         if (chip->options & NAND_BUSWIDTH_AUTO) {
3742                 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3743                 chip->options |= busw;
3744                 nand_set_defaults(chip, busw);
3745         } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3746                 /*
3747                  * Check, if buswidth is correct. Hardware drivers should set
3748                  * chip correct!
3749                  */
3750                 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3751                         *maf_id, *dev_id);
3752                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3753                 pr_warn("bus width %d instead %d bit\n",
3754                            (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3755                            busw ? 16 : 8);
3756                 return ERR_PTR(-EINVAL);
3757         }
3758
3759         nand_decode_bbm_options(mtd, chip, id_data);
3760
3761         /* Calculate the address shift from the page size */
3762         chip->page_shift = ffs(mtd->writesize) - 1;
3763         /* Convert chipsize to number of pages per chip -1 */
3764         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3765
3766         chip->bbt_erase_shift = chip->phys_erase_shift =
3767                 ffs(mtd->erasesize) - 1;
3768         if (chip->chipsize & 0xffffffff)
3769                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3770         else {
3771                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3772                 chip->chip_shift += 32 - 1;
3773         }
3774
3775         chip->badblockbits = 8;
3776         chip->erase = single_erase;
3777
3778         /* Do not replace user supplied command function! */
3779         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3780                 chip->cmdfunc = nand_command_lp;
3781
3782         pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3783                 *maf_id, *dev_id);
3784
3785         if (chip->onfi_version)
3786                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3787                                 chip->onfi_params.model);
3788         else if (chip->jedec_version)
3789                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3790                                 chip->jedec_params.model);
3791         else
3792                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3793                                 type->name);
3794
3795         pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3796                 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3797                 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
3798         return type;
3799 }
3800
3801 /**
3802  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3803  * @mtd: MTD device structure
3804  * @maxchips: number of chips to scan for
3805  * @table: alternative NAND ID table
3806  *
3807  * This is the first phase of the normal nand_scan() function. It reads the
3808  * flash ID and sets up MTD fields accordingly.
3809  *
3810  * The mtd->owner field must be set to the module of the caller.
3811  */
3812 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3813                     struct nand_flash_dev *table)
3814 {
3815         int i, nand_maf_id, nand_dev_id;
3816         struct nand_chip *chip = mtd->priv;
3817         struct nand_flash_dev *type;
3818
3819         /* Set the default functions */
3820         nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
3821
3822         /* Read the flash type */
3823         type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3824                                    &nand_dev_id, table);
3825
3826         if (IS_ERR(type)) {
3827                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3828                         pr_warn("No NAND device found\n");
3829                 chip->select_chip(mtd, -1);
3830                 return PTR_ERR(type);
3831         }
3832
3833         chip->select_chip(mtd, -1);
3834
3835         /* Check for a chip array */
3836         for (i = 1; i < maxchips; i++) {
3837                 chip->select_chip(mtd, i);
3838                 /* See comment in nand_get_flash_type for reset */
3839                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3840                 /* Send the command for reading device ID */
3841                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3842                 /* Read manufacturer and device IDs */
3843                 if (nand_maf_id != chip->read_byte(mtd) ||
3844                     nand_dev_id != chip->read_byte(mtd)) {
3845                         chip->select_chip(mtd, -1);
3846                         break;
3847                 }
3848                 chip->select_chip(mtd, -1);
3849         }
3850         if (i > 1)
3851                 pr_info("%d chips detected\n", i);
3852
3853         /* Store the number of chips and calc total size for mtd */
3854         chip->numchips = i;
3855         mtd->size = i * chip->chipsize;
3856
3857         return 0;
3858 }
3859 EXPORT_SYMBOL(nand_scan_ident);
3860
3861 /*
3862  * Check if the chip configuration meet the datasheet requirements.
3863
3864  * If our configuration corrects A bits per B bytes and the minimum
3865  * required correction level is X bits per Y bytes, then we must ensure
3866  * both of the following are true:
3867  *
3868  * (1) A / B >= X / Y
3869  * (2) A >= X
3870  *
3871  * Requirement (1) ensures we can correct for the required bitflip density.
3872  * Requirement (2) ensures we can correct even when all bitflips are clumped
3873  * in the same sector.
3874  */
3875 static bool nand_ecc_strength_good(struct mtd_info *mtd)
3876 {
3877         struct nand_chip *chip = mtd->priv;
3878         struct nand_ecc_ctrl *ecc = &chip->ecc;
3879         int corr, ds_corr;
3880
3881         if (ecc->size == 0 || chip->ecc_step_ds == 0)
3882                 /* Not enough information */
3883                 return true;
3884
3885         /*
3886          * We get the number of corrected bits per page to compare
3887          * the correction density.
3888          */
3889         corr = (mtd->writesize * ecc->strength) / ecc->size;
3890         ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
3891
3892         return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
3893 }
3894
3895 /**
3896  * nand_scan_tail - [NAND Interface] Scan for the NAND device
3897  * @mtd: MTD device structure
3898  *
3899  * This is the second phase of the normal nand_scan() function. It fills out
3900  * all the uninitialized function pointers with the defaults and scans for a
3901  * bad block table if appropriate.
3902  */
3903 int nand_scan_tail(struct mtd_info *mtd)
3904 {
3905         int i;
3906         struct nand_chip *chip = mtd->priv;
3907         struct nand_ecc_ctrl *ecc = &chip->ecc;
3908         struct nand_buffers *nbuf;
3909
3910         /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3911         BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3912                         !(chip->bbt_options & NAND_BBT_USE_FLASH));
3913
3914         if (!(chip->options & NAND_OWN_BUFFERS)) {
3915                 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
3916                                 + mtd->oobsize * 3, GFP_KERNEL);
3917                 if (!nbuf)
3918                         return -ENOMEM;
3919                 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
3920                 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
3921                 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
3922
3923                 chip->buffers = nbuf;
3924         } else {
3925                 if (!chip->buffers)
3926                         return -ENOMEM;
3927         }
3928
3929         /* Set the internal oob buffer location, just after the page data */
3930         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3931
3932         /*
3933          * If no default placement scheme is given, select an appropriate one.
3934          */
3935         if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
3936                 switch (mtd->oobsize) {
3937                 case 8:
3938                         ecc->layout = &nand_oob_8;
3939                         break;
3940                 case 16:
3941                         ecc->layout = &nand_oob_16;
3942                         break;
3943                 case 64:
3944                         ecc->layout = &nand_oob_64;
3945                         break;
3946                 case 128:
3947                         ecc->layout = &nand_oob_128;
3948                         break;
3949                 default:
3950                         pr_warn("No oob scheme defined for oobsize %d\n",
3951                                    mtd->oobsize);
3952                         BUG();
3953                 }
3954         }
3955
3956         if (!chip->write_page)
3957                 chip->write_page = nand_write_page;
3958
3959         /*
3960          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3961          * selected and we have 256 byte pagesize fallback to software ECC
3962          */
3963
3964         switch (ecc->mode) {
3965         case NAND_ECC_HW_OOB_FIRST:
3966                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3967                 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
3968                         pr_warn("No ECC functions supplied; hardware ECC not possible\n");
3969                         BUG();
3970                 }
3971                 if (!ecc->read_page)
3972                         ecc->read_page = nand_read_page_hwecc_oob_first;
3973
3974         case NAND_ECC_HW:
3975                 /* Use standard hwecc read page function? */
3976                 if (!ecc->read_page)
3977                         ecc->read_page = nand_read_page_hwecc;
3978                 if (!ecc->write_page)
3979                         ecc->write_page = nand_write_page_hwecc;
3980                 if (!ecc->read_page_raw)
3981                         ecc->read_page_raw = nand_read_page_raw;
3982                 if (!ecc->write_page_raw)
3983                         ecc->write_page_raw = nand_write_page_raw;
3984                 if (!ecc->read_oob)
3985                         ecc->read_oob = nand_read_oob_std;
3986                 if (!ecc->write_oob)
3987                         ecc->write_oob = nand_write_oob_std;
3988                 if (!ecc->read_subpage)
3989                         ecc->read_subpage = nand_read_subpage;
3990                 if (!ecc->write_subpage)
3991                         ecc->write_subpage = nand_write_subpage_hwecc;
3992
3993         case NAND_ECC_HW_SYNDROME:
3994                 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
3995                     (!ecc->read_page ||
3996                      ecc->read_page == nand_read_page_hwecc ||
3997                      !ecc->write_page ||
3998                      ecc->write_page == nand_write_page_hwecc)) {
3999                         pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4000                         BUG();
4001                 }
4002                 /* Use standard syndrome read/write page function? */
4003                 if (!ecc->read_page)
4004                         ecc->read_page = nand_read_page_syndrome;
4005                 if (!ecc->write_page)
4006                         ecc->write_page = nand_write_page_syndrome;
4007                 if (!ecc->read_page_raw)
4008                         ecc->read_page_raw = nand_read_page_raw_syndrome;
4009                 if (!ecc->write_page_raw)
4010                         ecc->write_page_raw = nand_write_page_raw_syndrome;
4011                 if (!ecc->read_oob)
4012                         ecc->read_oob = nand_read_oob_syndrome;
4013                 if (!ecc->write_oob)
4014                         ecc->write_oob = nand_write_oob_syndrome;
4015
4016                 if (mtd->writesize >= ecc->size) {
4017                         if (!ecc->strength) {
4018                                 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4019                                 BUG();
4020                         }
4021                         break;
4022                 }
4023                 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4024                         ecc->size, mtd->writesize);
4025                 ecc->mode = NAND_ECC_SOFT;
4026
4027         case NAND_ECC_SOFT:
4028                 ecc->calculate = nand_calculate_ecc;
4029                 ecc->correct = nand_correct_data;
4030                 ecc->read_page = nand_read_page_swecc;
4031                 ecc->read_subpage = nand_read_subpage;
4032                 ecc->write_page = nand_write_page_swecc;
4033                 ecc->read_page_raw = nand_read_page_raw;
4034                 ecc->write_page_raw = nand_write_page_raw;
4035                 ecc->read_oob = nand_read_oob_std;
4036                 ecc->write_oob = nand_write_oob_std;
4037                 if (!ecc->size)
4038                         ecc->size = 256;
4039                 ecc->bytes = 3;
4040                 ecc->strength = 1;
4041                 break;
4042
4043         case NAND_ECC_SOFT_BCH:
4044                 if (!mtd_nand_has_bch()) {
4045                         pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4046                         BUG();
4047                 }
4048                 ecc->calculate = nand_bch_calculate_ecc;
4049                 ecc->correct = nand_bch_correct_data;
4050                 ecc->read_page = nand_read_page_swecc;
4051                 ecc->read_subpage = nand_read_subpage;
4052                 ecc->write_page = nand_write_page_swecc;
4053                 ecc->read_page_raw = nand_read_page_raw;
4054                 ecc->write_page_raw = nand_write_page_raw;
4055                 ecc->read_oob = nand_read_oob_std;
4056                 ecc->write_oob = nand_write_oob_std;
4057                 /*
4058                  * Board driver should supply ecc.size and ecc.strength values
4059                  * to select how many bits are correctable. Otherwise, default
4060                  * to 4 bits for large page devices.
4061                  */
4062                 if (!ecc->size && (mtd->oobsize >= 64)) {
4063                         ecc->size = 512;
4064                         ecc->strength = 4;
4065                 }
4066
4067                 /* See nand_bch_init() for details. */
4068                 ecc->bytes = DIV_ROUND_UP(
4069                                 ecc->strength * fls(8 * ecc->size), 8);
4070                 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4071                                                &ecc->layout);
4072                 if (!ecc->priv) {
4073                         pr_warn("BCH ECC initialization failed!\n");
4074                         BUG();
4075                 }
4076                 break;
4077
4078         case NAND_ECC_NONE:
4079                 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4080                 ecc->read_page = nand_read_page_raw;
4081                 ecc->write_page = nand_write_page_raw;
4082                 ecc->read_oob = nand_read_oob_std;
4083                 ecc->read_page_raw = nand_read_page_raw;
4084                 ecc->write_page_raw = nand_write_page_raw;
4085                 ecc->write_oob = nand_write_oob_std;
4086                 ecc->size = mtd->writesize;
4087                 ecc->bytes = 0;
4088                 ecc->strength = 0;
4089                 break;
4090
4091         default:
4092                 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4093                 BUG();
4094         }
4095
4096         /* For many systems, the standard OOB write also works for raw */
4097         if (!ecc->read_oob_raw)
4098                 ecc->read_oob_raw = ecc->read_oob;
4099         if (!ecc->write_oob_raw)
4100                 ecc->write_oob_raw = ecc->write_oob;
4101
4102         /*
4103          * The number of bytes available for a client to place data into
4104          * the out of band area.
4105          */
4106         ecc->layout->oobavail = 0;
4107         for (i = 0; ecc->layout->oobfree[i].length
4108                         && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4109                 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4110         mtd->oobavail = ecc->layout->oobavail;
4111
4112         /* ECC sanity check: warn if it's too weak */
4113         if (!nand_ecc_strength_good(mtd))
4114                 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4115                         mtd->name);
4116
4117         /*
4118          * Set the number of read / write steps for one page depending on ECC
4119          * mode.
4120          */
4121         ecc->steps = mtd->writesize / ecc->size;
4122         if (ecc->steps * ecc->size != mtd->writesize) {
4123                 pr_warn("Invalid ECC parameters\n");
4124                 BUG();
4125         }
4126         ecc->total = ecc->steps * ecc->bytes;
4127
4128         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4129         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4130                 switch (ecc->steps) {
4131                 case 2:
4132                         mtd->subpage_sft = 1;
4133                         break;
4134                 case 4:
4135                 case 8:
4136                 case 16:
4137                         mtd->subpage_sft = 2;
4138                         break;
4139                 }
4140         }
4141         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4142
4143         /* Initialize state */
4144         chip->state = FL_READY;
4145
4146         /* Invalidate the pagebuffer reference */
4147         chip->pagebuf = -1;
4148
4149         /* Large page NAND with SOFT_ECC should support subpage reads */
4150         switch (ecc->mode) {
4151         case NAND_ECC_SOFT:
4152         case NAND_ECC_SOFT_BCH:
4153                 if (chip->page_shift > 9)
4154                         chip->options |= NAND_SUBPAGE_READ;
4155                 break;
4156
4157         default:
4158                 break;
4159         }
4160
4161         /* Fill in remaining MTD driver data */
4162         mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4163         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4164                                                 MTD_CAP_NANDFLASH;
4165         mtd->_erase = nand_erase;
4166         mtd->_point = NULL;
4167         mtd->_unpoint = NULL;
4168         mtd->_read = nand_read;
4169         mtd->_write = nand_write;
4170         mtd->_panic_write = panic_nand_write;
4171         mtd->_read_oob = nand_read_oob;
4172         mtd->_write_oob = nand_write_oob;
4173         mtd->_sync = nand_sync;
4174         mtd->_lock = NULL;
4175         mtd->_unlock = NULL;
4176         mtd->_suspend = nand_suspend;
4177         mtd->_resume = nand_resume;
4178         mtd->_reboot = nand_shutdown;
4179         mtd->_block_isreserved = nand_block_isreserved;
4180         mtd->_block_isbad = nand_block_isbad;
4181         mtd->_block_markbad = nand_block_markbad;
4182         mtd->writebufsize = mtd->writesize;
4183
4184         /* propagate ecc info to mtd_info */
4185         mtd->ecclayout = ecc->layout;
4186         mtd->ecc_strength = ecc->strength;
4187         mtd->ecc_step_size = ecc->size;
4188         /*
4189          * Initialize bitflip_threshold to its default prior scan_bbt() call.
4190          * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4191          * properly set.
4192          */
4193         if (!mtd->bitflip_threshold)
4194                 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
4195
4196         /* Check, if we should skip the bad block table scan */
4197         if (chip->options & NAND_SKIP_BBTSCAN)
4198                 return 0;
4199
4200         /* Build bad block table */
4201         return chip->scan_bbt(mtd);
4202 }
4203 EXPORT_SYMBOL(nand_scan_tail);
4204
4205 /*
4206  * is_module_text_address() isn't exported, and it's mostly a pointless
4207  * test if this is a module _anyway_ -- they'd have to try _really_ hard
4208  * to call us from in-kernel code if the core NAND support is modular.
4209  */
4210 #ifdef MODULE
4211 #define caller_is_module() (1)
4212 #else
4213 #define caller_is_module() \
4214         is_module_text_address((unsigned long)__builtin_return_address(0))
4215 #endif
4216
4217 /**
4218  * nand_scan - [NAND Interface] Scan for the NAND device
4219  * @mtd: MTD device structure
4220  * @maxchips: number of chips to scan for
4221  *
4222  * This fills out all the uninitialized function pointers with the defaults.
4223  * The flash ID is read and the mtd/chip structures are filled with the
4224  * appropriate values. The mtd->owner field must be set to the module of the
4225  * caller.
4226  */
4227 int nand_scan(struct mtd_info *mtd, int maxchips)
4228 {
4229         int ret;
4230
4231         /* Many callers got this wrong, so check for it for a while... */
4232         if (!mtd->owner && caller_is_module()) {
4233                 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4234                 BUG();
4235         }
4236
4237         ret = nand_scan_ident(mtd, maxchips, NULL);
4238         if (!ret)
4239                 ret = nand_scan_tail(mtd);
4240         return ret;
4241 }
4242 EXPORT_SYMBOL(nand_scan);
4243
4244 /**
4245  * nand_release - [NAND Interface] Free resources held by the NAND device
4246  * @mtd: MTD device structure
4247  */
4248 void nand_release(struct mtd_info *mtd)
4249 {
4250         struct nand_chip *chip = mtd->priv;
4251
4252         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4253                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4254
4255         mtd_device_unregister(mtd);
4256
4257         /* Free bad block table memory */
4258         kfree(chip->bbt);
4259         if (!(chip->options & NAND_OWN_BUFFERS))
4260                 kfree(chip->buffers);
4261
4262         /* Free bad block descriptor memory */
4263         if (chip->badblock_pattern && chip->badblock_pattern->options
4264                         & NAND_BBT_DYNAMICSTRUCT)
4265                 kfree(chip->badblock_pattern);
4266 }
4267 EXPORT_SYMBOL_GPL(nand_release);
4268
4269 static int __init nand_base_init(void)
4270 {
4271         led_trigger_register_simple("nand-disk", &nand_led_trigger);
4272         return 0;
4273 }
4274
4275 static void __exit nand_base_exit(void)
4276 {
4277         led_trigger_unregister_simple(nand_led_trigger);
4278 }
4279
4280 module_init(nand_base_init);
4281 module_exit(nand_base_exit);
4282
4283 MODULE_LICENSE("GPL");
4284 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4285 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4286 MODULE_DESCRIPTION("Generic NAND flash driver code");