kernel/drivers/mtd/nand/fsl_ifc_nand.c

   1 /*
   2  * Freescale Integrated Flash Controller NAND driver
   3  *
   4  * Copyright 2011-2012 Freescale Semiconductor, Inc
   5  *
   6  * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/types.h>
  25 #include <linux/kernel.h>
  26 #include <linux/of_address.h>
  27 #include <linux/slab.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/nand.h>
  30 #include <linux/mtd/partitions.h>
  31 #include <linux/mtd/nand_ecc.h>
  32 #include <linux/fsl_ifc.h>
  33
  34 #define ERR_BYTE                0xFF /* Value returned for read
  35                                         bytes when read failed  */
  36 #define IFC_TIMEOUT_MSECS       500  /* Maximum number of mSecs to wait
  37                                         for IFC NAND Machine    */
  38
  39 struct fsl_ifc_ctrl;
  40
  41 /* mtd information per set */
  42 struct fsl_ifc_mtd {
  43         struct mtd_info mtd;
  44         struct nand_chip chip;
  45         struct fsl_ifc_ctrl *ctrl;
  46
  47         struct device *dev;
  48         int bank;               /* Chip select bank number              */
  49         unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  50         u8 __iomem *vbase;      /* Chip select base virtual address     */
  51 };
  52
  53 /* overview of the fsl ifc controller */
  54 struct fsl_ifc_nand_ctrl {
  55         struct nand_hw_control controller;
  56         struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
  57
  58         void __iomem *addr;     /* Address of assigned IFC buffer       */
  59         unsigned int page;      /* Last page written to / read from     */
  60         unsigned int read_bytes;/* Number of bytes read during command  */
  61         unsigned int column;    /* Saved column from SEQIN              */
  62         unsigned int index;     /* Pointer to next byte to 'read'       */
  63         unsigned int oob;       /* Non zero if operating on OOB data    */
  64         unsigned int eccread;   /* Non zero for a full-page ECC read    */
  65         unsigned int counter;   /* counter for the initializations      */
  66         unsigned int max_bitflips;  /* Saved during READ0 cmd           */
  67 };
  68
  69 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
  70
  71 /* 512-byte page with 4-bit ECC, 8-bit */
  72 static struct nand_ecclayout oob_512_8bit_ecc4 = {
  73         .eccbytes = 8,
  74         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  75         .oobfree = { {0, 5}, {6, 2} },
  76 };
  77
  78 /* 512-byte page with 4-bit ECC, 16-bit */
  79 static struct nand_ecclayout oob_512_16bit_ecc4 = {
  80         .eccbytes = 8,
  81         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  82         .oobfree = { {2, 6}, },
  83 };
  84
  85 /* 2048-byte page size with 4-bit ECC */
  86 static struct nand_ecclayout oob_2048_ecc4 = {
  87         .eccbytes = 32,
  88         .eccpos = {
  89                 8, 9, 10, 11, 12, 13, 14, 15,
  90                 16, 17, 18, 19, 20, 21, 22, 23,
  91                 24, 25, 26, 27, 28, 29, 30, 31,
  92                 32, 33, 34, 35, 36, 37, 38, 39,
  93         },
  94         .oobfree = { {2, 6}, {40, 24} },
  95 };
  96
  97 /* 4096-byte page size with 4-bit ECC */
  98 static struct nand_ecclayout oob_4096_ecc4 = {
  99         .eccbytes = 64,
 100         .eccpos = {
 101                 8, 9, 10, 11, 12, 13, 14, 15,
 102                 16, 17, 18, 19, 20, 21, 22, 23,
 103                 24, 25, 26, 27, 28, 29, 30, 31,
 104                 32, 33, 34, 35, 36, 37, 38, 39,
 105                 40, 41, 42, 43, 44, 45, 46, 47,
 106                 48, 49, 50, 51, 52, 53, 54, 55,
 107                 56, 57, 58, 59, 60, 61, 62, 63,
 108                 64, 65, 66, 67, 68, 69, 70, 71,
 109         },
 110         .oobfree = { {2, 6}, {72, 56} },
 111 };
 112
 113 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
 114 static struct nand_ecclayout oob_4096_ecc8 = {
 115         .eccbytes = 128,
 116         .eccpos = {
 117                 8, 9, 10, 11, 12, 13, 14, 15,
 118                 16, 17, 18, 19, 20, 21, 22, 23,
 119                 24, 25, 26, 27, 28, 29, 30, 31,
 120                 32, 33, 34, 35, 36, 37, 38, 39,
 121                 40, 41, 42, 43, 44, 45, 46, 47,
 122                 48, 49, 50, 51, 52, 53, 54, 55,
 123                 56, 57, 58, 59, 60, 61, 62, 63,
 124                 64, 65, 66, 67, 68, 69, 70, 71,
 125                 72, 73, 74, 75, 76, 77, 78, 79,
 126                 80, 81, 82, 83, 84, 85, 86, 87,
 127                 88, 89, 90, 91, 92, 93, 94, 95,
 128                 96, 97, 98, 99, 100, 101, 102, 103,
 129                 104, 105, 106, 107, 108, 109, 110, 111,
 130                 112, 113, 114, 115, 116, 117, 118, 119,
 131                 120, 121, 122, 123, 124, 125, 126, 127,
 132                 128, 129, 130, 131, 132, 133, 134, 135,
 133         },
 134         .oobfree = { {2, 6}, {136, 82} },
 135 };
 136
 137 /* 8192-byte page size with 4-bit ECC */
 138 static struct nand_ecclayout oob_8192_ecc4 = {
 139         .eccbytes = 128,
 140         .eccpos = {
 141                 8, 9, 10, 11, 12, 13, 14, 15,
 142                 16, 17, 18, 19, 20, 21, 22, 23,
 143                 24, 25, 26, 27, 28, 29, 30, 31,
 144                 32, 33, 34, 35, 36, 37, 38, 39,
 145                 40, 41, 42, 43, 44, 45, 46, 47,
 146                 48, 49, 50, 51, 52, 53, 54, 55,
 147                 56, 57, 58, 59, 60, 61, 62, 63,
 148                 64, 65, 66, 67, 68, 69, 70, 71,
 149                 72, 73, 74, 75, 76, 77, 78, 79,
 150                 80, 81, 82, 83, 84, 85, 86, 87,
 151                 88, 89, 90, 91, 92, 93, 94, 95,
 152                 96, 97, 98, 99, 100, 101, 102, 103,
 153                 104, 105, 106, 107, 108, 109, 110, 111,
 154                 112, 113, 114, 115, 116, 117, 118, 119,
 155                 120, 121, 122, 123, 124, 125, 126, 127,
 156                 128, 129, 130, 131, 132, 133, 134, 135,
 157         },
 158         .oobfree = { {2, 6}, {136, 208} },
 159 };
 160
 161 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
 162 static struct nand_ecclayout oob_8192_ecc8 = {
 163         .eccbytes = 256,
 164         .eccpos = {
 165                 8, 9, 10, 11, 12, 13, 14, 15,
 166                 16, 17, 18, 19, 20, 21, 22, 23,
 167                 24, 25, 26, 27, 28, 29, 30, 31,
 168                 32, 33, 34, 35, 36, 37, 38, 39,
 169                 40, 41, 42, 43, 44, 45, 46, 47,
 170                 48, 49, 50, 51, 52, 53, 54, 55,
 171                 56, 57, 58, 59, 60, 61, 62, 63,
 172                 64, 65, 66, 67, 68, 69, 70, 71,
 173                 72, 73, 74, 75, 76, 77, 78, 79,
 174                 80, 81, 82, 83, 84, 85, 86, 87,
 175                 88, 89, 90, 91, 92, 93, 94, 95,
 176                 96, 97, 98, 99, 100, 101, 102, 103,
 177                 104, 105, 106, 107, 108, 109, 110, 111,
 178                 112, 113, 114, 115, 116, 117, 118, 119,
 179                 120, 121, 122, 123, 124, 125, 126, 127,
 180                 128, 129, 130, 131, 132, 133, 134, 135,
 181                 136, 137, 138, 139, 140, 141, 142, 143,
 182                 144, 145, 146, 147, 148, 149, 150, 151,
 183                 152, 153, 154, 155, 156, 157, 158, 159,
 184                 160, 161, 162, 163, 164, 165, 166, 167,
 185                 168, 169, 170, 171, 172, 173, 174, 175,
 186                 176, 177, 178, 179, 180, 181, 182, 183,
 187                 184, 185, 186, 187, 188, 189, 190, 191,
 188                 192, 193, 194, 195, 196, 197, 198, 199,
 189                 200, 201, 202, 203, 204, 205, 206, 207,
 190                 208, 209, 210, 211, 212, 213, 214, 215,
 191                 216, 217, 218, 219, 220, 221, 222, 223,
 192                 224, 225, 226, 227, 228, 229, 230, 231,
 193                 232, 233, 234, 235, 236, 237, 238, 239,
 194                 240, 241, 242, 243, 244, 245, 246, 247,
 195                 248, 249, 250, 251, 252, 253, 254, 255,
 196                 256, 257, 258, 259, 260, 261, 262, 263,
 197         },
 198         .oobfree = { {2, 6}, {264, 80} },
 199 };
 200
 201 /*
 202  * Generic flash bbt descriptors
 203  */
 204 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 205 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 206
 207 static struct nand_bbt_descr bbt_main_descr = {
 208         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 209                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 210         .offs = 2, /* 0 on 8-bit small page */
 211         .len = 4,
 212         .veroffs = 6,
 213         .maxblocks = 4,
 214         .pattern = bbt_pattern,
 215 };
 216
 217 static struct nand_bbt_descr bbt_mirror_descr = {
 218         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 219                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 220         .offs = 2, /* 0 on 8-bit small page */
 221         .len = 4,
 222         .veroffs = 6,
 223         .maxblocks = 4,
 224         .pattern = mirror_pattern,
 225 };
 226
 227 /*
 228  * Set up the IFC hardware block and page address fields, and the ifc nand
 229  * structure addr field to point to the correct IFC buffer in memory
 230  */
 231 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 232 {
 233         struct nand_chip *chip = mtd->priv;
 234         struct fsl_ifc_mtd *priv = chip->priv;
 235         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 236         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 237         int buf_num;
 238
 239         ifc_nand_ctrl->page = page_addr;
 240         /* Program ROW0/COL0 */
 241         iowrite32be(page_addr, &ifc->ifc_nand.row0);
 242         iowrite32be((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
 243
 244         buf_num = page_addr & priv->bufnum_mask;
 245
 246         ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
 247         ifc_nand_ctrl->index = column;
 248
 249         /* for OOB data point to the second half of the buffer */
 250         if (oob)
 251                 ifc_nand_ctrl->index += mtd->writesize;
 252 }
 253
 254 static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
 255 {
 256         struct nand_chip *chip = mtd->priv;
 257         struct fsl_ifc_mtd *priv = chip->priv;
 258         u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
 259         u32 __iomem *mainarea = (u32 __iomem *)addr;
 260         u8 __iomem *oob = addr + mtd->writesize;
 261         int i;
 262
 263         for (i = 0; i < mtd->writesize / 4; i++) {
 264                 if (__raw_readl(&mainarea[i]) != 0xffffffff)
 265                         return 0;
 266         }
 267
 268         for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
 269                 int pos = chip->ecc.layout->eccpos[i];
 270
 271                 if (__raw_readb(&oob[pos]) != 0xff)
 272                         return 0;
 273         }
 274
 275         return 1;
 276 }
 277
 278 /* returns nonzero if entire page is blank */
 279 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 280                           u32 *eccstat, unsigned int bufnum)
 281 {
 282         u32 reg = eccstat[bufnum / 4];
 283         int errors;
 284
 285         errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
 286
 287         return errors;
 288 }
 289
 290 /*
 291  * execute IFC NAND command and wait for it to complete
 292  */
 293 static void fsl_ifc_run_command(struct mtd_info *mtd)
 294 {
 295         struct nand_chip *chip = mtd->priv;
 296         struct fsl_ifc_mtd *priv = chip->priv;
 297         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 298         struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
 299         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 300         u32 eccstat[4];
 301         int i;
 302
 303         /* set the chip select for NAND Transaction */
 304         iowrite32be(priv->bank << IFC_NAND_CSEL_SHIFT,
 305                     &ifc->ifc_nand.nand_csel);
 306
 307         dev_vdbg(priv->dev,
 308                         "%s: fir0=%08x fcr0=%08x\n",
 309                         __func__,
 310                         ioread32be(&ifc->ifc_nand.nand_fir0),
 311                         ioread32be(&ifc->ifc_nand.nand_fcr0));
 312
 313         ctrl->nand_stat = 0;
 314
 315         /* start read/write seq */
 316         iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
 317
 318         /* wait for command complete flag or timeout */
 319         wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
 320                            msecs_to_jiffies(IFC_TIMEOUT_MSECS));
 321
 322         /* ctrl->nand_stat will be updated from IRQ context */
 323         if (!ctrl->nand_stat)
 324                 dev_err(priv->dev, "Controller is not responding\n");
 325         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
 326                 dev_err(priv->dev, "NAND Flash Timeout Error\n");
 327         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
 328                 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
 329
 330         nctrl->max_bitflips = 0;
 331
 332         if (nctrl->eccread) {
 333                 int errors;
 334                 int bufnum = nctrl->page & priv->bufnum_mask;
 335                 int sector = bufnum * chip->ecc.steps;
 336                 int sector_end = sector + chip->ecc.steps - 1;
 337
 338                 for (i = sector / 4; i <= sector_end / 4; i++)
 339                         eccstat[i] = ioread32be(&ifc->ifc_nand.nand_eccstat[i]);
 340
 341                 for (i = sector; i <= sector_end; i++) {
 342                         errors = check_read_ecc(mtd, ctrl, eccstat, i);
 343
 344                         if (errors == 15) {
 345                                 /*
 346                                  * Uncorrectable error.
 347                                  * OK only if the whole page is blank.
 348                                  *
 349                                  * We disable ECCER reporting due to...
 350                                  * erratum IFC-A002770 -- so report it now if we
 351                                  * see an uncorrectable error in ECCSTAT.
 352                                  */
 353                                 if (!is_blank(mtd, bufnum))
 354                                         ctrl->nand_stat |=
 355                                                 IFC_NAND_EVTER_STAT_ECCER;
 356                                 break;
 357                         }
 358
 359                         mtd->ecc_stats.corrected += errors;
 360                         nctrl->max_bitflips = max_t(unsigned int,
 361                                                     nctrl->max_bitflips,
 362                                                     errors);
 363                 }
 364
 365                 nctrl->eccread = 0;
 366         }
 367 }
 368
 369 static void fsl_ifc_do_read(struct nand_chip *chip,
 370                             int oob,
 371                             struct mtd_info *mtd)
 372 {
 373         struct fsl_ifc_mtd *priv = chip->priv;
 374         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 375         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 376
 377         /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 378         if (mtd->writesize > 512) {
 379                 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 380                             (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 381                             (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 382                             (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
 383                             (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
 384                             &ifc->ifc_nand.nand_fir0);
 385                 iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
 386
 387                 iowrite32be((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
 388                             (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
 389                             &ifc->ifc_nand.nand_fcr0);
 390         } else {
 391                 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 392                             (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 393                             (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
 394                             (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
 395                             &ifc->ifc_nand.nand_fir0);
 396                 iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
 397
 398                 if (oob)
 399                         iowrite32be(NAND_CMD_READOOB <<
 400                                     IFC_NAND_FCR0_CMD0_SHIFT,
 401                                     &ifc->ifc_nand.nand_fcr0);
 402                 else
 403                         iowrite32be(NAND_CMD_READ0 <<
 404                                     IFC_NAND_FCR0_CMD0_SHIFT,
 405                                     &ifc->ifc_nand.nand_fcr0);
 406         }
 407 }
 408
 409 /* cmdfunc send commands to the IFC NAND Machine */
 410 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 411                              int column, int page_addr) {
 412         struct nand_chip *chip = mtd->priv;
 413         struct fsl_ifc_mtd *priv = chip->priv;
 414         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 415         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 416
 417         /* clear the read buffer */
 418         ifc_nand_ctrl->read_bytes = 0;
 419         if (command != NAND_CMD_PAGEPROG)
 420                 ifc_nand_ctrl->index = 0;
 421
 422         switch (command) {
 423         /* READ0 read the entire buffer to use hardware ECC. */
 424         case NAND_CMD_READ0:
 425                 iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
 426                 set_addr(mtd, 0, page_addr, 0);
 427
 428                 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 429                 ifc_nand_ctrl->index += column;
 430
 431                 if (chip->ecc.mode == NAND_ECC_HW)
 432                         ifc_nand_ctrl->eccread = 1;
 433
 434                 fsl_ifc_do_read(chip, 0, mtd);
 435                 fsl_ifc_run_command(mtd);
 436                 return;
 437
 438         /* READOOB reads only the OOB because no ECC is performed. */
 439         case NAND_CMD_READOOB:
 440                 iowrite32be(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
 441                 set_addr(mtd, column, page_addr, 1);
 442
 443                 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 444
 445                 fsl_ifc_do_read(chip, 1, mtd);
 446                 fsl_ifc_run_command(mtd);
 447
 448                 return;
 449
 450         case NAND_CMD_READID:
 451         case NAND_CMD_PARAM: {
 452                 int timing = IFC_FIR_OP_RB;
 453                 if (command == NAND_CMD_PARAM)
 454                         timing = IFC_FIR_OP_RBCD;
 455
 456                 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 457                             (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 458                             (timing << IFC_NAND_FIR0_OP2_SHIFT),
 459                             &ifc->ifc_nand.nand_fir0);
 460                 iowrite32be(command << IFC_NAND_FCR0_CMD0_SHIFT,
 461                             &ifc->ifc_nand.nand_fcr0);
 462                 iowrite32be(column, &ifc->ifc_nand.row3);
 463
 464                 /*
 465                  * although currently it's 8 bytes for READID, we always read
 466                  * the maximum 256 bytes(for PARAM)
 467                  */
 468                 iowrite32be(256, &ifc->ifc_nand.nand_fbcr);
 469                 ifc_nand_ctrl->read_bytes = 256;
 470
 471                 set_addr(mtd, 0, 0, 0);
 472                 fsl_ifc_run_command(mtd);
 473                 return;
 474         }
 475
 476         /* ERASE1 stores the block and page address */
 477         case NAND_CMD_ERASE1:
 478                 set_addr(mtd, 0, page_addr, 0);
 479                 return;
 480
 481         /* ERASE2 uses the block and page address from ERASE1 */
 482         case NAND_CMD_ERASE2:
 483                 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 484                             (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 485                             (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
 486                             &ifc->ifc_nand.nand_fir0);
 487
 488                 iowrite32be((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
 489                             (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
 490                             &ifc->ifc_nand.nand_fcr0);
 491
 492                 iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
 493                 ifc_nand_ctrl->read_bytes = 0;
 494                 fsl_ifc_run_command(mtd);
 495                 return;
 496
 497         /* SEQIN sets up the addr buffer and all registers except the length */
 498         case NAND_CMD_SEQIN: {
 499                 u32 nand_fcr0;
 500                 ifc_nand_ctrl->column = column;
 501                 ifc_nand_ctrl->oob = 0;
 502
 503                 if (mtd->writesize > 512) {
 504                         nand_fcr0 =
 505                                 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
 506                                 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
 507                                 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
 508
 509                         iowrite32be(
 510                                  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 511                                  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 512                                  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 513                                  (IFC_FIR_OP_WBCD  << IFC_NAND_FIR0_OP3_SHIFT) |
 514                                  (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
 515                                  &ifc->ifc_nand.nand_fir0);
 516                         iowrite32be(
 517                                  (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
 518                                  (IFC_FIR_OP_RDSTAT <<
 519                                         IFC_NAND_FIR1_OP6_SHIFT) |
 520                                  (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
 521                                  &ifc->ifc_nand.nand_fir1);
 522                 } else {
 523                         nand_fcr0 = ((NAND_CMD_PAGEPROG <<
 524                                         IFC_NAND_FCR0_CMD1_SHIFT) |
 525                                     (NAND_CMD_SEQIN <<
 526                                         IFC_NAND_FCR0_CMD2_SHIFT) |
 527                                     (NAND_CMD_STATUS <<
 528                                         IFC_NAND_FCR0_CMD3_SHIFT));
 529
 530                         iowrite32be(
 531                                 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 532                                 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
 533                                 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 534                                 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
 535                                 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
 536                                 &ifc->ifc_nand.nand_fir0);
 537                         iowrite32be(
 538                                  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
 539                                  (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
 540                                  (IFC_FIR_OP_RDSTAT <<
 541                                         IFC_NAND_FIR1_OP7_SHIFT) |
 542                                  (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
 543                                   &ifc->ifc_nand.nand_fir1);
 544
 545                         if (column >= mtd->writesize)
 546                                 nand_fcr0 |=
 547                                 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
 548                         else
 549                                 nand_fcr0 |=
 550                                 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
 551                 }
 552
 553                 if (column >= mtd->writesize) {
 554                         /* OOB area --> READOOB */
 555                         column -= mtd->writesize;
 556                         ifc_nand_ctrl->oob = 1;
 557                 }
 558                 iowrite32be(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
 559                 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
 560                 return;
 561         }
 562
 563         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 564         case NAND_CMD_PAGEPROG: {
 565                 if (ifc_nand_ctrl->oob) {
 566                         iowrite32be(ifc_nand_ctrl->index -
 567                                     ifc_nand_ctrl->column,
 568                                     &ifc->ifc_nand.nand_fbcr);
 569                 } else {
 570                         iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
 571                 }
 572
 573                 fsl_ifc_run_command(mtd);
 574                 return;
 575         }
 576
 577         case NAND_CMD_STATUS:
 578                 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 579                             (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
 580                             &ifc->ifc_nand.nand_fir0);
 581                 iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
 582                             &ifc->ifc_nand.nand_fcr0);
 583                 iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
 584                 set_addr(mtd, 0, 0, 0);
 585                 ifc_nand_ctrl->read_bytes = 1;
 586
 587                 fsl_ifc_run_command(mtd);
 588
 589                 /*
 590                  * The chip always seems to report that it is
 591                  * write-protected, even when it is not.
 592                  */
 593                 if (chip->options & NAND_BUSWIDTH_16)
 594                         setbits16(ifc_nand_ctrl->addr, NAND_STATUS_WP);
 595                 else
 596                         setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP);
 597                 return;
 598
 599         case NAND_CMD_RESET:
 600                 iowrite32be(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
 601                             &ifc->ifc_nand.nand_fir0);
 602                 iowrite32be(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
 603                             &ifc->ifc_nand.nand_fcr0);
 604                 fsl_ifc_run_command(mtd);
 605                 return;
 606
 607         default:
 608                 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
 609                                         __func__, command);
 610         }
 611 }
 612
 613 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
 614 {
 615         /* The hardware does not seem to support multiple
 616          * chips per bank.
 617          */
 618 }
 619
 620 /*
 621  * Write buf to the IFC NAND Controller Data Buffer
 622  */
 623 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 624 {
 625         struct nand_chip *chip = mtd->priv;
 626         struct fsl_ifc_mtd *priv = chip->priv;
 627         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 628
 629         if (len <= 0) {
 630                 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
 631                 return;
 632         }
 633
 634         if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
 635                 dev_err(priv->dev,
 636                         "%s: beyond end of buffer (%d requested, %u available)\n",
 637                         __func__, len, bufsize - ifc_nand_ctrl->index);
 638                 len = bufsize - ifc_nand_ctrl->index;
 639         }
 640
 641         memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
 642         ifc_nand_ctrl->index += len;
 643 }
 644
 645 /*
 646  * Read a byte from either the IFC hardware buffer
 647  * read function for 8-bit buswidth
 648  */
 649 static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
 650 {
 651         struct nand_chip *chip = mtd->priv;
 652         struct fsl_ifc_mtd *priv = chip->priv;
 653         unsigned int offset;
 654
 655         /*
 656          * If there are still bytes in the IFC buffer, then use the
 657          * next byte.
 658          */
 659         if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
 660                 offset = ifc_nand_ctrl->index++;
 661                 return in_8(ifc_nand_ctrl->addr + offset);
 662         }
 663
 664         dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
 665         return ERR_BYTE;
 666 }
 667
 668 /*
 669  * Read two bytes from the IFC hardware buffer
 670  * read function for 16-bit buswith
 671  */
 672 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 673 {
 674         struct nand_chip *chip = mtd->priv;
 675         struct fsl_ifc_mtd *priv = chip->priv;
 676         uint16_t data;
 677
 678         /*
 679          * If there are still bytes in the IFC buffer, then use the
 680          * next byte.
 681          */
 682         if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
 683                 data = in_be16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
 684                 ifc_nand_ctrl->index += 2;
 685                 return (uint8_t) data;
 686         }
 687
 688         dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
 689         return ERR_BYTE;
 690 }
 691
 692 /*
 693  * Read from the IFC Controller Data Buffer
 694  */
 695 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 696 {
 697         struct nand_chip *chip = mtd->priv;
 698         struct fsl_ifc_mtd *priv = chip->priv;
 699         int avail;
 700
 701         if (len < 0) {
 702                 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
 703                 return;
 704         }
 705
 706         avail = min((unsigned int)len,
 707                         ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
 708         memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
 709         ifc_nand_ctrl->index += avail;
 710
 711         if (len > avail)
 712                 dev_err(priv->dev,
 713                         "%s: beyond end of buffer (%d requested, %d available)\n",
 714                         __func__, len, avail);
 715 }
 716
 717 /*
 718  * This function is called after Program and Erase Operations to
 719  * check for success or failure.
 720  */
 721 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 722 {
 723         struct fsl_ifc_mtd *priv = chip->priv;
 724         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 725         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 726         u32 nand_fsr;
 727
 728         /* Use READ_STATUS command, but wait for the device to be ready */
 729         iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 730                     (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
 731                     &ifc->ifc_nand.nand_fir0);
 732         iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
 733                     &ifc->ifc_nand.nand_fcr0);
 734         iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
 735         set_addr(mtd, 0, 0, 0);
 736         ifc_nand_ctrl->read_bytes = 1;
 737
 738         fsl_ifc_run_command(mtd);
 739
 740         nand_fsr = ioread32be(&ifc->ifc_nand.nand_fsr);
 741
 742         /*
 743          * The chip always seems to report that it is
 744          * write-protected, even when it is not.
 745          */
 746         return nand_fsr | NAND_STATUS_WP;
 747 }
 748
 749 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 750                              uint8_t *buf, int oob_required, int page)
 751 {
 752         struct fsl_ifc_mtd *priv = chip->priv;
 753         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 754         struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
 755
 756         fsl_ifc_read_buf(mtd, buf, mtd->writesize);
 757         if (oob_required)
 758                 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 759
 760         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
 761                 dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
 762
 763         if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
 764                 mtd->ecc_stats.failed++;
 765
 766         return nctrl->max_bitflips;
 767 }
 768
 769 /* ECC will be calculated automatically, and errors will be detected in
 770  * waitfunc.
 771  */
 772 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 773                                const uint8_t *buf, int oob_required)
 774 {
 775         fsl_ifc_write_buf(mtd, buf, mtd->writesize);
 776         fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 777
 778         return 0;
 779 }
 780
 781 static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
 782 {
 783         struct nand_chip *chip = mtd->priv;
 784         struct fsl_ifc_mtd *priv = chip->priv;
 785
 786         dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
 787                                                         chip->numchips);
 788         dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
 789                                                         chip->chipsize);
 790         dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
 791                                                         chip->pagemask);
 792         dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
 793                                                         chip->chip_delay);
 794         dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
 795                                                         chip->badblockpos);
 796         dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
 797                                                         chip->chip_shift);
 798         dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
 799                                                         chip->page_shift);
 800         dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
 801                                                         chip->phys_erase_shift);
 802         dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
 803                                                         chip->ecc.mode);
 804         dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
 805                                                         chip->ecc.steps);
 806         dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
 807                                                         chip->ecc.bytes);
 808         dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
 809                                                         chip->ecc.total);
 810         dev_dbg(priv->dev, "%s: nand->ecc.layout = %p\n", __func__,
 811                                                         chip->ecc.layout);
 812         dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
 813         dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
 814         dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
 815                                                         mtd->erasesize);
 816         dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
 817                                                         mtd->writesize);
 818         dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
 819                                                         mtd->oobsize);
 820
 821         return 0;
 822 }
 823
 824 static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
 825 {
 826         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 827         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 828         uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
 829         uint32_t cs = priv->bank;
 830
 831         /* Save CSOR and CSOR_ext */
 832         csor = ioread32be(&ifc->csor_cs[cs].csor);
 833         csor_ext = ioread32be(&ifc->csor_cs[cs].csor_ext);
 834
 835         /* chage PageSize 8K and SpareSize 1K*/
 836         csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
 837         iowrite32be(csor_8k, &ifc->csor_cs[cs].csor);
 838         iowrite32be(0x0000400, &ifc->csor_cs[cs].csor_ext);
 839
 840         /* READID */
 841         iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 842                     (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 843                     (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
 844                     &ifc->ifc_nand.nand_fir0);
 845         iowrite32be(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
 846                     &ifc->ifc_nand.nand_fcr0);
 847         iowrite32be(0x0, &ifc->ifc_nand.row3);
 848
 849         iowrite32be(0x0, &ifc->ifc_nand.nand_fbcr);
 850
 851         /* Program ROW0/COL0 */
 852         iowrite32be(0x0, &ifc->ifc_nand.row0);
 853         iowrite32be(0x0, &ifc->ifc_nand.col0);
 854
 855         /* set the chip select for NAND Transaction */
 856         iowrite32be(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
 857
 858         /* start read seq */
 859         iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
 860
 861         /* wait for command complete flag or timeout */
 862         wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
 863                            msecs_to_jiffies(IFC_TIMEOUT_MSECS));
 864
 865         if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
 866                 printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
 867
 868         /* Restore CSOR and CSOR_ext */
 869         iowrite32be(csor, &ifc->csor_cs[cs].csor);
 870         iowrite32be(csor_ext, &ifc->csor_cs[cs].csor_ext);
 871 }
 872
 873 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 874 {
 875         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 876         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 877         struct nand_chip *chip = &priv->chip;
 878         struct nand_ecclayout *layout;
 879         u32 csor;
 880
 881         /* Fill in fsl_ifc_mtd structure */
 882         priv->mtd.priv = chip;
 883         priv->mtd.owner = THIS_MODULE;
 884
 885         /* fill in nand_chip structure */
 886         /* set up function call table */
 887         if ((ioread32be(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
 888                 chip->read_byte = fsl_ifc_read_byte16;
 889         else
 890                 chip->read_byte = fsl_ifc_read_byte;
 891
 892         chip->write_buf = fsl_ifc_write_buf;
 893         chip->read_buf = fsl_ifc_read_buf;
 894         chip->select_chip = fsl_ifc_select_chip;
 895         chip->cmdfunc = fsl_ifc_cmdfunc;
 896         chip->waitfunc = fsl_ifc_wait;
 897
 898         chip->bbt_td = &bbt_main_descr;
 899         chip->bbt_md = &bbt_mirror_descr;
 900
 901         iowrite32be(0x0, &ifc->ifc_nand.ncfgr);
 902
 903         /* set up nand options */
 904         chip->bbt_options = NAND_BBT_USE_FLASH;
 905         chip->options = NAND_NO_SUBPAGE_WRITE;
 906
 907         if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
 908                 chip->read_byte = fsl_ifc_read_byte16;
 909                 chip->options |= NAND_BUSWIDTH_16;
 910         } else {
 911                 chip->read_byte = fsl_ifc_read_byte;
 912         }
 913
 914         chip->controller = &ifc_nand_ctrl->controller;
 915         chip->priv = priv;
 916
 917         chip->ecc.read_page = fsl_ifc_read_page;
 918         chip->ecc.write_page = fsl_ifc_write_page;
 919
 920         csor = ioread32be(&ifc->csor_cs[priv->bank].csor);
 921
 922         /* Hardware generates ECC per 512 Bytes */
 923         chip->ecc.size = 512;
 924         chip->ecc.bytes = 8;
 925         chip->ecc.strength = 4;
 926
 927         switch (csor & CSOR_NAND_PGS_MASK) {
 928         case CSOR_NAND_PGS_512:
 929                 if (chip->options & NAND_BUSWIDTH_16) {
 930                         layout = &oob_512_16bit_ecc4;
 931                 } else {
 932                         layout = &oob_512_8bit_ecc4;
 933
 934                         /* Avoid conflict with bad block marker */
 935                         bbt_main_descr.offs = 0;
 936                         bbt_mirror_descr.offs = 0;
 937                 }
 938
 939                 priv->bufnum_mask = 15;
 940                 break;
 941
 942         case CSOR_NAND_PGS_2K:
 943                 layout = &oob_2048_ecc4;
 944                 priv->bufnum_mask = 3;
 945                 break;
 946
 947         case CSOR_NAND_PGS_4K:
 948                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
 949                     CSOR_NAND_ECC_MODE_4) {
 950                         layout = &oob_4096_ecc4;
 951                 } else {
 952                         layout = &oob_4096_ecc8;
 953                         chip->ecc.bytes = 16;
 954                         chip->ecc.strength = 8;
 955                 }
 956
 957                 priv->bufnum_mask = 1;
 958                 break;
 959
 960         case CSOR_NAND_PGS_8K:
 961                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
 962                     CSOR_NAND_ECC_MODE_4) {
 963                         layout = &oob_8192_ecc4;
 964                 } else {
 965                         layout = &oob_8192_ecc8;
 966                         chip->ecc.bytes = 16;
 967                         chip->ecc.strength = 8;
 968                 }
 969
 970                 priv->bufnum_mask = 0;
 971         break;
 972
 973         default:
 974                 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
 975                 return -ENODEV;
 976         }
 977
 978         /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
 979         if (csor & CSOR_NAND_ECC_DEC_EN) {
 980                 chip->ecc.mode = NAND_ECC_HW;
 981                 chip->ecc.layout = layout;
 982         } else {
 983                 chip->ecc.mode = NAND_ECC_SOFT;
 984         }
 985
 986         if (ctrl->version == FSL_IFC_VERSION_1_1_0)
 987                 fsl_ifc_sram_init(priv);
 988
 989         return 0;
 990 }
 991
 992 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
 993 {
 994         nand_release(&priv->mtd);
 995
 996         kfree(priv->mtd.name);
 997
 998         if (priv->vbase)
 999                 iounmap(priv->vbase);
1000
1001         ifc_nand_ctrl->chips[priv->bank] = NULL;
1002
1003         return 0;
1004 }
1005
1006 static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
1007                       phys_addr_t addr)
1008 {
1009         u32 cspr = ioread32be(&ifc->cspr_cs[bank].cspr);
1010
1011         if (!(cspr & CSPR_V))
1012                 return 0;
1013         if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
1014                 return 0;
1015
1016         return (cspr & CSPR_BA) == convert_ifc_address(addr);
1017 }
1018
1019 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
1020
1021 static int fsl_ifc_nand_probe(struct platform_device *dev)
1022 {
1023         struct fsl_ifc_regs __iomem *ifc;
1024         struct fsl_ifc_mtd *priv;
1025         struct resource res;
1026         static const char *part_probe_types[]
1027                 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
1028         int ret;
1029         int bank;
1030         struct device_node *node = dev->dev.of_node;
1031         struct mtd_part_parser_data ppdata;
1032
1033         ppdata.of_node = dev->dev.of_node;
1034         if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
1035                 return -ENODEV;
1036         ifc = fsl_ifc_ctrl_dev->regs;
1037
1038         /* get, allocate and map the memory resource */
1039         ret = of_address_to_resource(node, 0, &res);
1040         if (ret) {
1041                 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
1042                 return ret;
1043         }
1044
1045         /* find which chip select it is connected to */
1046         for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
1047                 if (match_bank(ifc, bank, res.start))
1048                         break;
1049         }
1050
1051         if (bank >= fsl_ifc_ctrl_dev->banks) {
1052                 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
1053                         __func__);
1054                 return -ENODEV;
1055         }
1056
1057         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1058         if (!priv)
1059                 return -ENOMEM;
1060
1061         mutex_lock(&fsl_ifc_nand_mutex);
1062         if (!fsl_ifc_ctrl_dev->nand) {
1063                 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
1064                 if (!ifc_nand_ctrl) {
1065                         mutex_unlock(&fsl_ifc_nand_mutex);
1066                         return -ENOMEM;
1067                 }
1068
1069                 ifc_nand_ctrl->read_bytes = 0;
1070                 ifc_nand_ctrl->index = 0;
1071                 ifc_nand_ctrl->addr = NULL;
1072                 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
1073
1074                 spin_lock_init(&ifc_nand_ctrl->controller.lock);
1075                 init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
1076         } else {
1077                 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
1078         }
1079         mutex_unlock(&fsl_ifc_nand_mutex);
1080
1081         ifc_nand_ctrl->chips[bank] = priv;
1082         priv->bank = bank;
1083         priv->ctrl = fsl_ifc_ctrl_dev;
1084         priv->dev = &dev->dev;
1085
1086         priv->vbase = ioremap(res.start, resource_size(&res));
1087         if (!priv->vbase) {
1088                 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1089                 ret = -ENOMEM;
1090                 goto err;
1091         }
1092
1093         dev_set_drvdata(priv->dev, priv);
1094
1095         iowrite32be(IFC_NAND_EVTER_EN_OPC_EN |
1096                     IFC_NAND_EVTER_EN_FTOER_EN |
1097                     IFC_NAND_EVTER_EN_WPER_EN,
1098                     &ifc->ifc_nand.nand_evter_en);
1099
1100         /* enable NAND Machine Interrupts */
1101         iowrite32be(IFC_NAND_EVTER_INTR_OPCIR_EN |
1102                     IFC_NAND_EVTER_INTR_FTOERIR_EN |
1103                     IFC_NAND_EVTER_INTR_WPERIR_EN,
1104                     &ifc->ifc_nand.nand_evter_intr_en);
1105         priv->mtd.name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1106         if (!priv->mtd.name) {
1107                 ret = -ENOMEM;
1108                 goto err;
1109         }
1110
1111         ret = fsl_ifc_chip_init(priv);
1112         if (ret)
1113                 goto err;
1114
1115         ret = nand_scan_ident(&priv->mtd, 1, NULL);
1116         if (ret)
1117                 goto err;
1118
1119         ret = fsl_ifc_chip_init_tail(&priv->mtd);
1120         if (ret)
1121                 goto err;
1122
1123         ret = nand_scan_tail(&priv->mtd);
1124         if (ret)
1125                 goto err;
1126
1127         /* First look for RedBoot table or partitions on the command
1128          * line, these take precedence over device tree information */
1129         mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
1130                                                 NULL, 0);
1131
1132         dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1133                  (unsigned long long)res.start, priv->bank);
1134         return 0;
1135
1136 err:
1137         fsl_ifc_chip_remove(priv);
1138         return ret;
1139 }
1140
1141 static int fsl_ifc_nand_remove(struct platform_device *dev)
1142 {
1143         struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1144
1145         fsl_ifc_chip_remove(priv);
1146
1147         mutex_lock(&fsl_ifc_nand_mutex);
1148         ifc_nand_ctrl->counter--;
1149         if (!ifc_nand_ctrl->counter) {
1150                 fsl_ifc_ctrl_dev->nand = NULL;
1151                 kfree(ifc_nand_ctrl);
1152         }
1153         mutex_unlock(&fsl_ifc_nand_mutex);
1154
1155         return 0;
1156 }
1157
1158 static const struct of_device_id fsl_ifc_nand_match[] = {
1159         {
1160                 .compatible = "fsl,ifc-nand",
1161         },
1162         {}
1163 };
1164
1165 static struct platform_driver fsl_ifc_nand_driver = {
1166         .driver = {
1167                 .name   = "fsl,ifc-nand",
1168                 .of_match_table = fsl_ifc_nand_match,
1169         },
1170         .probe       = fsl_ifc_nand_probe,
1171         .remove      = fsl_ifc_nand_remove,
1172 };
1173
1174 module_platform_driver(fsl_ifc_nand_driver);
1175
1176 MODULE_LICENSE("GPL");
1177 MODULE_AUTHOR("Freescale");
1178 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");