kernel/drivers/mtd/nand/brcmnand/brcmnand.c

   1 /*
   2  * Copyright © 2010-2015 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/version.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/err.h>
  21 #include <linux/completion.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/ioport.h>
  26 #include <linux/bug.h>
  27 #include <linux/kernel.h>
  28 #include <linux/bitops.h>
  29 #include <linux/mm.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/partitions.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mtd.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/slab.h>
  37 #include <linux/list.h>
  38 #include <linux/log2.h>
  39
  40 #include "brcmnand.h"
  41
  42 /*
  43  * This flag controls if WP stays on between erase/write commands to mitigate
  44  * flash corruption due to power glitches. Values:
  45  * 0: NAND_WP is not used or not available
  46  * 1: NAND_WP is set by default, cleared for erase/write operations
  47  * 2: NAND_WP is always cleared
  48  */
  49 static int wp_on = 1;
  50 module_param(wp_on, int, 0444);
  51
  52 /***********************************************************************
  53  * Definitions
  54  ***********************************************************************/
  55
  56 #define DRV_NAME                        "brcmnand"
  57
  58 #define CMD_NULL                        0x00
  59 #define CMD_PAGE_READ                   0x01
  60 #define CMD_SPARE_AREA_READ             0x02
  61 #define CMD_STATUS_READ                 0x03
  62 #define CMD_PROGRAM_PAGE                0x04
  63 #define CMD_PROGRAM_SPARE_AREA          0x05
  64 #define CMD_COPY_BACK                   0x06
  65 #define CMD_DEVICE_ID_READ              0x07
  66 #define CMD_BLOCK_ERASE                 0x08
  67 #define CMD_FLASH_RESET                 0x09
  68 #define CMD_BLOCKS_LOCK                 0x0a
  69 #define CMD_BLOCKS_LOCK_DOWN            0x0b
  70 #define CMD_BLOCKS_UNLOCK               0x0c
  71 #define CMD_READ_BLOCKS_LOCK_STATUS     0x0d
  72 #define CMD_PARAMETER_READ              0x0e
  73 #define CMD_PARAMETER_CHANGE_COL        0x0f
  74 #define CMD_LOW_LEVEL_OP                0x10
  75
  76 struct brcm_nand_dma_desc {
  77         u32 next_desc;
  78         u32 next_desc_ext;
  79         u32 cmd_irq;
  80         u32 dram_addr;
  81         u32 dram_addr_ext;
  82         u32 tfr_len;
  83         u32 total_len;
  84         u32 flash_addr;
  85         u32 flash_addr_ext;
  86         u32 cs;
  87         u32 pad2[5];
  88         u32 status_valid;
  89 } __packed;
  90
  91 /* Bitfields for brcm_nand_dma_desc::status_valid */
  92 #define FLASH_DMA_ECC_ERROR     (1 << 8)
  93 #define FLASH_DMA_CORR_ERROR    (1 << 9)
  94
  95 /* 512B flash cache in the NAND controller HW */
  96 #define FC_SHIFT                9U
  97 #define FC_BYTES                512U
  98 #define FC_WORDS                (FC_BYTES >> 2)
  99
 100 #define BRCMNAND_MIN_PAGESIZE   512
 101 #define BRCMNAND_MIN_BLOCKSIZE  (8 * 1024)
 102 #define BRCMNAND_MIN_DEVSIZE    (4ULL * 1024 * 1024)
 103
 104 /* Controller feature flags */
 105 enum {
 106         BRCMNAND_HAS_1K_SECTORS                 = BIT(0),
 107         BRCMNAND_HAS_PREFETCH                   = BIT(1),
 108         BRCMNAND_HAS_CACHE_MODE                 = BIT(2),
 109         BRCMNAND_HAS_WP                         = BIT(3),
 110 };
 111
 112 struct brcmnand_controller {
 113         struct device           *dev;
 114         struct nand_hw_control  controller;
 115         void __iomem            *nand_base;
 116         void __iomem            *nand_fc; /* flash cache */
 117         void __iomem            *flash_dma_base;
 118         unsigned int            irq;
 119         unsigned int            dma_irq;
 120         int                     nand_version;
 121
 122         /* Some SoCs provide custom interrupt status register(s) */
 123         struct brcmnand_soc     *soc;
 124
 125         int                     cmd_pending;
 126         bool                    dma_pending;
 127         struct completion       done;
 128         struct completion       dma_done;
 129
 130         /* List of NAND hosts (one for each chip-select) */
 131         struct list_head host_list;
 132
 133         struct brcm_nand_dma_desc *dma_desc;
 134         dma_addr_t              dma_pa;
 135
 136         /* in-memory cache of the FLASH_CACHE, used only for some commands */
 137         u32                     flash_cache[FC_WORDS];
 138
 139         /* Controller revision details */
 140         const u16               *reg_offsets;
 141         unsigned int            reg_spacing; /* between CS1, CS2, ... regs */
 142         const u8                *cs_offsets; /* within each chip-select */
 143         const u8                *cs0_offsets; /* within CS0, if different */
 144         unsigned int            max_block_size;
 145         const unsigned int      *block_sizes;
 146         unsigned int            max_page_size;
 147         const unsigned int      *page_sizes;
 148         unsigned int            max_oob;
 149         u32                     features;
 150
 151         /* for low-power standby/resume only */
 152         u32                     nand_cs_nand_select;
 153         u32                     nand_cs_nand_xor;
 154         u32                     corr_stat_threshold;
 155         u32                     flash_dma_mode;
 156 };
 157
 158 struct brcmnand_cfg {
 159         u64                     device_size;
 160         unsigned int            block_size;
 161         unsigned int            page_size;
 162         unsigned int            spare_area_size;
 163         unsigned int            device_width;
 164         unsigned int            col_adr_bytes;
 165         unsigned int            blk_adr_bytes;
 166         unsigned int            ful_adr_bytes;
 167         unsigned int            sector_size_1k;
 168         unsigned int            ecc_level;
 169         /* use for low-power standby/resume only */
 170         u32                     acc_control;
 171         u32                     config;
 172         u32                     config_ext;
 173         u32                     timing_1;
 174         u32                     timing_2;
 175 };
 176
 177 struct brcmnand_host {
 178         struct list_head        node;
 179         struct device_node      *of_node;
 180
 181         struct nand_chip        chip;
 182         struct mtd_info         mtd;
 183         struct platform_device  *pdev;
 184         int                     cs;
 185
 186         unsigned int            last_cmd;
 187         unsigned int            last_byte;
 188         u64                     last_addr;
 189         struct brcmnand_cfg     hwcfg;
 190         struct brcmnand_controller *ctrl;
 191 };
 192
 193 enum brcmnand_reg {
 194         BRCMNAND_CMD_START = 0,
 195         BRCMNAND_CMD_EXT_ADDRESS,
 196         BRCMNAND_CMD_ADDRESS,
 197         BRCMNAND_INTFC_STATUS,
 198         BRCMNAND_CS_SELECT,
 199         BRCMNAND_CS_XOR,
 200         BRCMNAND_LL_OP,
 201         BRCMNAND_CS0_BASE,
 202         BRCMNAND_CS1_BASE,              /* CS1 regs, if non-contiguous */
 203         BRCMNAND_CORR_THRESHOLD,
 204         BRCMNAND_CORR_THRESHOLD_EXT,
 205         BRCMNAND_UNCORR_COUNT,
 206         BRCMNAND_CORR_COUNT,
 207         BRCMNAND_CORR_EXT_ADDR,
 208         BRCMNAND_CORR_ADDR,
 209         BRCMNAND_UNCORR_EXT_ADDR,
 210         BRCMNAND_UNCORR_ADDR,
 211         BRCMNAND_SEMAPHORE,
 212         BRCMNAND_ID,
 213         BRCMNAND_ID_EXT,
 214         BRCMNAND_LL_RDATA,
 215         BRCMNAND_OOB_READ_BASE,
 216         BRCMNAND_OOB_READ_10_BASE,      /* offset 0x10, if non-contiguous */
 217         BRCMNAND_OOB_WRITE_BASE,
 218         BRCMNAND_OOB_WRITE_10_BASE,     /* offset 0x10, if non-contiguous */
 219         BRCMNAND_FC_BASE,
 220 };
 221
 222 /* BRCMNAND v4.0 */
 223 static const u16 brcmnand_regs_v40[] = {
 224         [BRCMNAND_CMD_START]            =  0x04,
 225         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 226         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 227         [BRCMNAND_INTFC_STATUS]         =  0x6c,
 228         [BRCMNAND_CS_SELECT]            =  0x14,
 229         [BRCMNAND_CS_XOR]               =  0x18,
 230         [BRCMNAND_LL_OP]                = 0x178,
 231         [BRCMNAND_CS0_BASE]             =  0x40,
 232         [BRCMNAND_CS1_BASE]             =  0xd0,
 233         [BRCMNAND_CORR_THRESHOLD]       =  0x84,
 234         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
 235         [BRCMNAND_UNCORR_COUNT]         =     0,
 236         [BRCMNAND_CORR_COUNT]           =     0,
 237         [BRCMNAND_CORR_EXT_ADDR]        =  0x70,
 238         [BRCMNAND_CORR_ADDR]            =  0x74,
 239         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x78,
 240         [BRCMNAND_UNCORR_ADDR]          =  0x7c,
 241         [BRCMNAND_SEMAPHORE]            =  0x58,
 242         [BRCMNAND_ID]                   =  0x60,
 243         [BRCMNAND_ID_EXT]               =  0x64,
 244         [BRCMNAND_LL_RDATA]             = 0x17c,
 245         [BRCMNAND_OOB_READ_BASE]        =  0x20,
 246         [BRCMNAND_OOB_READ_10_BASE]     = 0x130,
 247         [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
 248         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 249         [BRCMNAND_FC_BASE]              = 0x200,
 250 };
 251
 252 /* BRCMNAND v5.0 */
 253 static const u16 brcmnand_regs_v50[] = {
 254         [BRCMNAND_CMD_START]            =  0x04,
 255         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 256         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 257         [BRCMNAND_INTFC_STATUS]         =  0x6c,
 258         [BRCMNAND_CS_SELECT]            =  0x14,
 259         [BRCMNAND_CS_XOR]               =  0x18,
 260         [BRCMNAND_LL_OP]                = 0x178,
 261         [BRCMNAND_CS0_BASE]             =  0x40,
 262         [BRCMNAND_CS1_BASE]             =  0xd0,
 263         [BRCMNAND_CORR_THRESHOLD]       =  0x84,
 264         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
 265         [BRCMNAND_UNCORR_COUNT]         =     0,
 266         [BRCMNAND_CORR_COUNT]           =     0,
 267         [BRCMNAND_CORR_EXT_ADDR]        =  0x70,
 268         [BRCMNAND_CORR_ADDR]            =  0x74,
 269         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x78,
 270         [BRCMNAND_UNCORR_ADDR]          =  0x7c,
 271         [BRCMNAND_SEMAPHORE]            =  0x58,
 272         [BRCMNAND_ID]                   =  0x60,
 273         [BRCMNAND_ID_EXT]               =  0x64,
 274         [BRCMNAND_LL_RDATA]             = 0x17c,
 275         [BRCMNAND_OOB_READ_BASE]        =  0x20,
 276         [BRCMNAND_OOB_READ_10_BASE]     = 0x130,
 277         [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
 278         [BRCMNAND_OOB_WRITE_10_BASE]    = 0x140,
 279         [BRCMNAND_FC_BASE]              = 0x200,
 280 };
 281
 282 /* BRCMNAND v6.0 - v7.1 */
 283 static const u16 brcmnand_regs_v60[] = {
 284         [BRCMNAND_CMD_START]            =  0x04,
 285         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 286         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 287         [BRCMNAND_INTFC_STATUS]         =  0x14,
 288         [BRCMNAND_CS_SELECT]            =  0x18,
 289         [BRCMNAND_CS_XOR]               =  0x1c,
 290         [BRCMNAND_LL_OP]                =  0x20,
 291         [BRCMNAND_CS0_BASE]             =  0x50,
 292         [BRCMNAND_CS1_BASE]             =     0,
 293         [BRCMNAND_CORR_THRESHOLD]       =  0xc0,
 294         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xc4,
 295         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 296         [BRCMNAND_CORR_COUNT]           = 0x100,
 297         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 298         [BRCMNAND_CORR_ADDR]            = 0x110,
 299         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 300         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 301         [BRCMNAND_SEMAPHORE]            = 0x150,
 302         [BRCMNAND_ID]                   = 0x194,
 303         [BRCMNAND_ID_EXT]               = 0x198,
 304         [BRCMNAND_LL_RDATA]             = 0x19c,
 305         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 306         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 307         [BRCMNAND_OOB_WRITE_BASE]       = 0x280,
 308         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 309         [BRCMNAND_FC_BASE]              = 0x400,
 310 };
 311
 312 /* BRCMNAND v7.1 */
 313 static const u16 brcmnand_regs_v71[] = {
 314         [BRCMNAND_CMD_START]            =  0x04,
 315         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 316         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 317         [BRCMNAND_INTFC_STATUS]         =  0x14,
 318         [BRCMNAND_CS_SELECT]            =  0x18,
 319         [BRCMNAND_CS_XOR]               =  0x1c,
 320         [BRCMNAND_LL_OP]                =  0x20,
 321         [BRCMNAND_CS0_BASE]             =  0x50,
 322         [BRCMNAND_CS1_BASE]             =     0,
 323         [BRCMNAND_CORR_THRESHOLD]       =  0xdc,
 324         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xe0,
 325         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 326         [BRCMNAND_CORR_COUNT]           = 0x100,
 327         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 328         [BRCMNAND_CORR_ADDR]            = 0x110,
 329         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 330         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 331         [BRCMNAND_SEMAPHORE]            = 0x150,
 332         [BRCMNAND_ID]                   = 0x194,
 333         [BRCMNAND_ID_EXT]               = 0x198,
 334         [BRCMNAND_LL_RDATA]             = 0x19c,
 335         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 336         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 337         [BRCMNAND_OOB_WRITE_BASE]       = 0x280,
 338         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 339         [BRCMNAND_FC_BASE]              = 0x400,
 340 };
 341
 342 enum brcmnand_cs_reg {
 343         BRCMNAND_CS_CFG_EXT = 0,
 344         BRCMNAND_CS_CFG,
 345         BRCMNAND_CS_ACC_CONTROL,
 346         BRCMNAND_CS_TIMING1,
 347         BRCMNAND_CS_TIMING2,
 348 };
 349
 350 /* Per chip-select offsets for v7.1 */
 351 static const u8 brcmnand_cs_offsets_v71[] = {
 352         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 353         [BRCMNAND_CS_CFG_EXT]           = 0x04,
 354         [BRCMNAND_CS_CFG]               = 0x08,
 355         [BRCMNAND_CS_TIMING1]           = 0x0c,
 356         [BRCMNAND_CS_TIMING2]           = 0x10,
 357 };
 358
 359 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
 360 static const u8 brcmnand_cs_offsets[] = {
 361         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 362         [BRCMNAND_CS_CFG_EXT]           = 0x04,
 363         [BRCMNAND_CS_CFG]               = 0x04,
 364         [BRCMNAND_CS_TIMING1]           = 0x08,
 365         [BRCMNAND_CS_TIMING2]           = 0x0c,
 366 };
 367
 368 /* Per chip-select offset for <= v5.0 on CS0 only */
 369 static const u8 brcmnand_cs_offsets_cs0[] = {
 370         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 371         [BRCMNAND_CS_CFG_EXT]           = 0x08,
 372         [BRCMNAND_CS_CFG]               = 0x08,
 373         [BRCMNAND_CS_TIMING1]           = 0x10,
 374         [BRCMNAND_CS_TIMING2]           = 0x14,
 375 };
 376
 377 /*
 378  * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
 379  * one config register, but once the bitfields overflowed, newer controllers
 380  * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
 381  */
 382 enum {
 383         CFG_BLK_ADR_BYTES_SHIFT         = 8,
 384         CFG_COL_ADR_BYTES_SHIFT         = 12,
 385         CFG_FUL_ADR_BYTES_SHIFT         = 16,
 386         CFG_BUS_WIDTH_SHIFT             = 23,
 387         CFG_BUS_WIDTH                   = BIT(CFG_BUS_WIDTH_SHIFT),
 388         CFG_DEVICE_SIZE_SHIFT           = 24,
 389
 390         /* Only for pre-v7.1 (with no CFG_EXT register) */
 391         CFG_PAGE_SIZE_SHIFT             = 20,
 392         CFG_BLK_SIZE_SHIFT              = 28,
 393
 394         /* Only for v7.1+ (with CFG_EXT register) */
 395         CFG_EXT_PAGE_SIZE_SHIFT         = 0,
 396         CFG_EXT_BLK_SIZE_SHIFT          = 4,
 397 };
 398
 399 /* BRCMNAND_INTFC_STATUS */
 400 enum {
 401         INTFC_FLASH_STATUS              = GENMASK(7, 0),
 402
 403         INTFC_ERASED                    = BIT(27),
 404         INTFC_OOB_VALID                 = BIT(28),
 405         INTFC_CACHE_VALID               = BIT(29),
 406         INTFC_FLASH_READY               = BIT(30),
 407         INTFC_CTLR_READY                = BIT(31),
 408 };
 409
 410 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
 411 {
 412         return brcmnand_readl(ctrl->nand_base + offs);
 413 }
 414
 415 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
 416                                  u32 val)
 417 {
 418         brcmnand_writel(val, ctrl->nand_base + offs);
 419 }
 420
 421 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
 422 {
 423         static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
 424         static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
 425         static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
 426
 427         ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
 428
 429         /* Only support v4.0+? */
 430         if (ctrl->nand_version < 0x0400) {
 431                 dev_err(ctrl->dev, "version %#x not supported\n",
 432                         ctrl->nand_version);
 433                 return -ENODEV;
 434         }
 435
 436         /* Register offsets */
 437         if (ctrl->nand_version >= 0x0701)
 438                 ctrl->reg_offsets = brcmnand_regs_v71;
 439         else if (ctrl->nand_version >= 0x0600)
 440                 ctrl->reg_offsets = brcmnand_regs_v60;
 441         else if (ctrl->nand_version >= 0x0500)
 442                 ctrl->reg_offsets = brcmnand_regs_v50;
 443         else if (ctrl->nand_version >= 0x0400)
 444                 ctrl->reg_offsets = brcmnand_regs_v40;
 445
 446         /* Chip-select stride */
 447         if (ctrl->nand_version >= 0x0701)
 448                 ctrl->reg_spacing = 0x14;
 449         else
 450                 ctrl->reg_spacing = 0x10;
 451
 452         /* Per chip-select registers */
 453         if (ctrl->nand_version >= 0x0701) {
 454                 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
 455         } else {
 456                 ctrl->cs_offsets = brcmnand_cs_offsets;
 457
 458                 /* v5.0 and earlier has a different CS0 offset layout */
 459                 if (ctrl->nand_version <= 0x0500)
 460                         ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
 461         }
 462
 463         /* Page / block sizes */
 464         if (ctrl->nand_version >= 0x0701) {
 465                 /* >= v7.1 use nice power-of-2 values! */
 466                 ctrl->max_page_size = 16 * 1024;
 467                 ctrl->max_block_size = 2 * 1024 * 1024;
 468         } else {
 469                 ctrl->page_sizes = page_sizes;
 470                 if (ctrl->nand_version >= 0x0600)
 471                         ctrl->block_sizes = block_sizes_v6;
 472                 else
 473                         ctrl->block_sizes = block_sizes_v4;
 474
 475                 if (ctrl->nand_version < 0x0400) {
 476                         ctrl->max_page_size = 4096;
 477                         ctrl->max_block_size = 512 * 1024;
 478                 }
 479         }
 480
 481         /* Maximum spare area sector size (per 512B) */
 482         if (ctrl->nand_version >= 0x0600)
 483                 ctrl->max_oob = 64;
 484         else if (ctrl->nand_version >= 0x0500)
 485                 ctrl->max_oob = 32;
 486         else
 487                 ctrl->max_oob = 16;
 488
 489         /* v6.0 and newer (except v6.1) have prefetch support */
 490         if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
 491                 ctrl->features |= BRCMNAND_HAS_PREFETCH;
 492
 493         /*
 494          * v6.x has cache mode, but it's implemented differently. Ignore it for
 495          * now.
 496          */
 497         if (ctrl->nand_version >= 0x0700)
 498                 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
 499
 500         if (ctrl->nand_version >= 0x0500)
 501                 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
 502
 503         if (ctrl->nand_version >= 0x0700)
 504                 ctrl->features |= BRCMNAND_HAS_WP;
 505         else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
 506                 ctrl->features |= BRCMNAND_HAS_WP;
 507
 508         return 0;
 509 }
 510
 511 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
 512                 enum brcmnand_reg reg)
 513 {
 514         u16 offs = ctrl->reg_offsets[reg];
 515
 516         if (offs)
 517                 return nand_readreg(ctrl, offs);
 518         else
 519                 return 0;
 520 }
 521
 522 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
 523                                       enum brcmnand_reg reg, u32 val)
 524 {
 525         u16 offs = ctrl->reg_offsets[reg];
 526
 527         if (offs)
 528                 nand_writereg(ctrl, offs, val);
 529 }
 530
 531 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
 532                                     enum brcmnand_reg reg, u32 mask, unsigned
 533                                     int shift, u32 val)
 534 {
 535         u32 tmp = brcmnand_read_reg(ctrl, reg);
 536
 537         tmp &= ~mask;
 538         tmp |= val << shift;
 539         brcmnand_write_reg(ctrl, reg, tmp);
 540 }
 541
 542 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
 543 {
 544         return __raw_readl(ctrl->nand_fc + word * 4);
 545 }
 546
 547 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
 548                                      int word, u32 val)
 549 {
 550         __raw_writel(val, ctrl->nand_fc + word * 4);
 551 }
 552
 553 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
 554                                      enum brcmnand_cs_reg reg)
 555 {
 556         u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
 557         u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
 558         u8 cs_offs;
 559
 560         if (cs == 0 && ctrl->cs0_offsets)
 561                 cs_offs = ctrl->cs0_offsets[reg];
 562         else
 563                 cs_offs = ctrl->cs_offsets[reg];
 564
 565         if (cs && offs_cs1)
 566                 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
 567
 568         return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
 569 }
 570
 571 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
 572 {
 573         if (ctrl->nand_version < 0x0600)
 574                 return 1;
 575         return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
 576 }
 577
 578 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
 579 {
 580         struct brcmnand_controller *ctrl = host->ctrl;
 581         unsigned int shift = 0, bits;
 582         enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
 583         int cs = host->cs;
 584
 585         if (ctrl->nand_version >= 0x0600)
 586                 bits = 6;
 587         else if (ctrl->nand_version >= 0x0500)
 588                 bits = 5;
 589         else
 590                 bits = 4;
 591
 592         if (ctrl->nand_version >= 0x0600) {
 593                 if (cs >= 5)
 594                         reg = BRCMNAND_CORR_THRESHOLD_EXT;
 595                 shift = (cs % 5) * bits;
 596         }
 597         brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
 598 }
 599
 600 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
 601 {
 602         if (ctrl->nand_version < 0x0700)
 603                 return 24;
 604         return 0;
 605 }
 606
 607 /***********************************************************************
 608  * NAND ACC CONTROL bitfield
 609  *
 610  * Some bits have remained constant throughout hardware revision, while
 611  * others have shifted around.
 612  ***********************************************************************/
 613
 614 /* Constant for all versions (where supported) */
 615 enum {
 616         /* See BRCMNAND_HAS_CACHE_MODE */
 617         ACC_CONTROL_CACHE_MODE                          = BIT(22),
 618
 619         /* See BRCMNAND_HAS_PREFETCH */
 620         ACC_CONTROL_PREFETCH                            = BIT(23),
 621
 622         ACC_CONTROL_PAGE_HIT                            = BIT(24),
 623         ACC_CONTROL_WR_PREEMPT                          = BIT(25),
 624         ACC_CONTROL_PARTIAL_PAGE                        = BIT(26),
 625         ACC_CONTROL_RD_ERASED                           = BIT(27),
 626         ACC_CONTROL_FAST_PGM_RDIN                       = BIT(28),
 627         ACC_CONTROL_WR_ECC                              = BIT(30),
 628         ACC_CONTROL_RD_ECC                              = BIT(31),
 629 };
 630
 631 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
 632 {
 633         if (ctrl->nand_version >= 0x0600)
 634                 return GENMASK(6, 0);
 635         else
 636                 return GENMASK(5, 0);
 637 }
 638
 639 #define NAND_ACC_CONTROL_ECC_SHIFT      16
 640
 641 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
 642 {
 643         u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
 644
 645         return mask << NAND_ACC_CONTROL_ECC_SHIFT;
 646 }
 647
 648 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
 649 {
 650         struct brcmnand_controller *ctrl = host->ctrl;
 651         u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
 652         u32 acc_control = nand_readreg(ctrl, offs);
 653         u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
 654
 655         if (en) {
 656                 acc_control |= ecc_flags; /* enable RD/WR ECC */
 657                 acc_control |= host->hwcfg.ecc_level
 658                                << NAND_ACC_CONTROL_ECC_SHIFT;
 659         } else {
 660                 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
 661                 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
 662         }
 663
 664         nand_writereg(ctrl, offs, acc_control);
 665 }
 666
 667 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
 668 {
 669         if (ctrl->nand_version >= 0x0600)
 670                 return 7;
 671         else if (ctrl->nand_version >= 0x0500)
 672                 return 6;
 673         else
 674                 return -1;
 675 }
 676
 677 static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
 678 {
 679         struct brcmnand_controller *ctrl = host->ctrl;
 680         int shift = brcmnand_sector_1k_shift(ctrl);
 681         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
 682                                                   BRCMNAND_CS_ACC_CONTROL);
 683
 684         if (shift < 0)
 685                 return 0;
 686
 687         return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
 688 }
 689
 690 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
 691 {
 692         struct brcmnand_controller *ctrl = host->ctrl;
 693         int shift = brcmnand_sector_1k_shift(ctrl);
 694         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
 695                                                   BRCMNAND_CS_ACC_CONTROL);
 696         u32 tmp;
 697
 698         if (shift < 0)
 699                 return;
 700
 701         tmp = nand_readreg(ctrl, acc_control_offs);
 702         tmp &= ~(1 << shift);
 703         tmp |= (!!val) << shift;
 704         nand_writereg(ctrl, acc_control_offs, tmp);
 705 }
 706
 707 /***********************************************************************
 708  * CS_NAND_SELECT
 709  ***********************************************************************/
 710
 711 enum {
 712         CS_SELECT_NAND_WP                       = BIT(29),
 713         CS_SELECT_AUTO_DEVICE_ID_CFG            = BIT(30),
 714 };
 715
 716 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
 717 {
 718         u32 val = en ? CS_SELECT_NAND_WP : 0;
 719
 720         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
 721 }
 722
 723 /***********************************************************************
 724  * Flash DMA
 725  ***********************************************************************/
 726
 727 enum flash_dma_reg {
 728         FLASH_DMA_REVISION              = 0x00,
 729         FLASH_DMA_FIRST_DESC            = 0x04,
 730         FLASH_DMA_FIRST_DESC_EXT        = 0x08,
 731         FLASH_DMA_CTRL                  = 0x0c,
 732         FLASH_DMA_MODE                  = 0x10,
 733         FLASH_DMA_STATUS                = 0x14,
 734         FLASH_DMA_INTERRUPT_DESC        = 0x18,
 735         FLASH_DMA_INTERRUPT_DESC_EXT    = 0x1c,
 736         FLASH_DMA_ERROR_STATUS          = 0x20,
 737         FLASH_DMA_CURRENT_DESC          = 0x24,
 738         FLASH_DMA_CURRENT_DESC_EXT      = 0x28,
 739 };
 740
 741 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
 742 {
 743         return ctrl->flash_dma_base;
 744 }
 745
 746 static inline bool flash_dma_buf_ok(const void *buf)
 747 {
 748         return buf && !is_vmalloc_addr(buf) &&
 749                 likely(IS_ALIGNED((uintptr_t)buf, 4));
 750 }
 751
 752 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
 753                                     u32 val)
 754 {
 755         brcmnand_writel(val, ctrl->flash_dma_base + offs);
 756 }
 757
 758 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
 759 {
 760         return brcmnand_readl(ctrl->flash_dma_base + offs);
 761 }
 762
 763 /* Low-level operation types: command, address, write, or read */
 764 enum brcmnand_llop_type {
 765         LL_OP_CMD,
 766         LL_OP_ADDR,
 767         LL_OP_WR,
 768         LL_OP_RD,
 769 };
 770
 771 /***********************************************************************
 772  * Internal support functions
 773  ***********************************************************************/
 774
 775 static inline bool is_hamming_ecc(struct brcmnand_cfg *cfg)
 776 {
 777         return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
 778                 cfg->ecc_level == 15;
 779 }
 780
 781 /*
 782  * Returns a nand_ecclayout strucutre for the given layout/configuration.
 783  * Returns NULL on failure.
 784  */
 785 static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
 786                                                      struct brcmnand_host *host)
 787 {
 788         struct brcmnand_cfg *cfg = &host->hwcfg;
 789         int i, j;
 790         struct nand_ecclayout *layout;
 791         int req;
 792         int sectors;
 793         int sas;
 794         int idx1, idx2;
 795
 796         layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
 797         if (!layout)
 798                 return NULL;
 799
 800         sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 801         sas = cfg->spare_area_size << cfg->sector_size_1k;
 802
 803         /* Hamming */
 804         if (is_hamming_ecc(cfg)) {
 805                 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
 806                         /* First sector of each page may have BBI */
 807                         if (i == 0) {
 808                                 layout->oobfree[idx2].offset = i * sas + 1;
 809                                 /* Small-page NAND use byte 6 for BBI */
 810                                 if (cfg->page_size == 512)
 811                                         layout->oobfree[idx2].offset--;
 812                                 layout->oobfree[idx2].length = 5;
 813                         } else {
 814                                 layout->oobfree[idx2].offset = i * sas;
 815                                 layout->oobfree[idx2].length = 6;
 816                         }
 817                         idx2++;
 818                         layout->eccpos[idx1++] = i * sas + 6;
 819                         layout->eccpos[idx1++] = i * sas + 7;
 820                         layout->eccpos[idx1++] = i * sas + 8;
 821                         layout->oobfree[idx2].offset = i * sas + 9;
 822                         layout->oobfree[idx2].length = 7;
 823                         idx2++;
 824                         /* Leave zero-terminated entry for OOBFREE */
 825                         if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
 826                                     idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
 827                                 break;
 828                 }
 829                 goto out;
 830         }
 831
 832         /*
 833          * CONTROLLER_VERSION:
 834          *   < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
 835          *  >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
 836          * But we will just be conservative.
 837          */
 838         req = DIV_ROUND_UP(ecc_level * 14, 8);
 839         if (req >= sas) {
 840                 dev_err(&host->pdev->dev,
 841                         "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
 842                         req, sas);
 843                 return NULL;
 844         }
 845
 846         layout->eccbytes = req * sectors;
 847         for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
 848                 for (j = sas - req; j < sas && idx1 <
 849                                 MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
 850                         layout->eccpos[idx1] = i * sas + j;
 851
 852                 /* First sector of each page may have BBI */
 853                 if (i == 0) {
 854                         if (cfg->page_size == 512 && (sas - req >= 6)) {
 855                                 /* Small-page NAND use byte 6 for BBI */
 856                                 layout->oobfree[idx2].offset = 0;
 857                                 layout->oobfree[idx2].length = 5;
 858                                 idx2++;
 859                                 if (sas - req > 6) {
 860                                         layout->oobfree[idx2].offset = 6;
 861                                         layout->oobfree[idx2].length =
 862                                                 sas - req - 6;
 863                                         idx2++;
 864                                 }
 865                         } else if (sas > req + 1) {
 866                                 layout->oobfree[idx2].offset = i * sas + 1;
 867                                 layout->oobfree[idx2].length = sas - req - 1;
 868                                 idx2++;
 869                         }
 870                 } else if (sas > req) {
 871                         layout->oobfree[idx2].offset = i * sas;
 872                         layout->oobfree[idx2].length = sas - req;
 873                         idx2++;
 874                 }
 875                 /* Leave zero-terminated entry for OOBFREE */
 876                 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
 877                                 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
 878                         break;
 879         }
 880 out:
 881         /* Sum available OOB */
 882         for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE; i++)
 883                 layout->oobavail += layout->oobfree[i].length;
 884         return layout;
 885 }
 886
 887 static struct nand_ecclayout *brcmstb_choose_ecc_layout(
 888                 struct brcmnand_host *host)
 889 {
 890         struct nand_ecclayout *layout;
 891         struct brcmnand_cfg *p = &host->hwcfg;
 892         unsigned int ecc_level = p->ecc_level;
 893
 894         if (p->sector_size_1k)
 895                 ecc_level <<= 1;
 896
 897         layout = brcmnand_create_layout(ecc_level, host);
 898         if (!layout) {
 899                 dev_err(&host->pdev->dev,
 900                                 "no proper ecc_layout for this NAND cfg\n");
 901                 return NULL;
 902         }
 903
 904         return layout;
 905 }
 906
 907 static void brcmnand_wp(struct mtd_info *mtd, int wp)
 908 {
 909         struct nand_chip *chip = mtd->priv;
 910         struct brcmnand_host *host = chip->priv;
 911         struct brcmnand_controller *ctrl = host->ctrl;
 912
 913         if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
 914                 static int old_wp = -1;
 915
 916                 if (old_wp != wp) {
 917                         dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
 918                         old_wp = wp;
 919                 }
 920                 brcmnand_set_wp(ctrl, wp);
 921         }
 922 }
 923
 924 /* Helper functions for reading and writing OOB registers */
 925 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
 926 {
 927         u16 offset0, offset10, reg_offs;
 928
 929         offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
 930         offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
 931
 932         if (offs >= ctrl->max_oob)
 933                 return 0x77;
 934
 935         if (offs >= 16 && offset10)
 936                 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
 937         else
 938                 reg_offs = offset0 + (offs & ~0x03);
 939
 940         return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
 941 }
 942
 943 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
 944                                  u32 data)
 945 {
 946         u16 offset0, offset10, reg_offs;
 947
 948         offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
 949         offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
 950
 951         if (offs >= ctrl->max_oob)
 952                 return;
 953
 954         if (offs >= 16 && offset10)
 955                 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
 956         else
 957                 reg_offs = offset0 + (offs & ~0x03);
 958
 959         nand_writereg(ctrl, reg_offs, data);
 960 }
 961
 962 /*
 963  * read_oob_from_regs - read data from OOB registers
 964  * @ctrl: NAND controller
 965  * @i: sub-page sector index
 966  * @oob: buffer to read to
 967  * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
 968  * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
 969  */
 970 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
 971                               int sas, int sector_1k)
 972 {
 973         int tbytes = sas << sector_1k;
 974         int j;
 975
 976         /* Adjust OOB values for 1K sector size */
 977         if (sector_1k && (i & 0x01))
 978                 tbytes = max(0, tbytes - (int)ctrl->max_oob);
 979         tbytes = min_t(int, tbytes, ctrl->max_oob);
 980
 981         for (j = 0; j < tbytes; j++)
 982                 oob[j] = oob_reg_read(ctrl, j);
 983         return tbytes;
 984 }
 985
 986 /*
 987  * write_oob_to_regs - write data to OOB registers
 988  * @i: sub-page sector index
 989  * @oob: buffer to write from
 990  * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
 991  * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
 992  */
 993 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
 994                              const u8 *oob, int sas, int sector_1k)
 995 {
 996         int tbytes = sas << sector_1k;
 997         int j;
 998
 999         /* Adjust OOB values for 1K sector size */
1000         if (sector_1k && (i & 0x01))
1001                 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1002         tbytes = min_t(int, tbytes, ctrl->max_oob);
1003
1004         for (j = 0; j < tbytes; j += 4)
1005                 oob_reg_write(ctrl, j,
1006                                 (oob[j + 0] << 24) |
1007                                 (oob[j + 1] << 16) |
1008                                 (oob[j + 2] <<  8) |
1009                                 (oob[j + 3] <<  0));
1010         return tbytes;
1011 }
1012
1013 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1014 {
1015         struct brcmnand_controller *ctrl = data;
1016
1017         /* Discard all NAND_CTLRDY interrupts during DMA */
1018         if (ctrl->dma_pending)
1019                 return IRQ_HANDLED;
1020
1021         complete(&ctrl->done);
1022         return IRQ_HANDLED;
1023 }
1024
1025 /* Handle SoC-specific interrupt hardware */
1026 static irqreturn_t brcmnand_irq(int irq, void *data)
1027 {
1028         struct brcmnand_controller *ctrl = data;
1029
1030         if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1031                 return brcmnand_ctlrdy_irq(irq, data);
1032
1033         return IRQ_NONE;
1034 }
1035
1036 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1037 {
1038         struct brcmnand_controller *ctrl = data;
1039
1040         complete(&ctrl->dma_done);
1041
1042         return IRQ_HANDLED;
1043 }
1044
1045 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1046 {
1047         struct brcmnand_controller *ctrl = host->ctrl;
1048         u32 intfc;
1049
1050         dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
1051                 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
1052         BUG_ON(ctrl->cmd_pending != 0);
1053         ctrl->cmd_pending = cmd;
1054
1055         intfc = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1056         BUG_ON(!(intfc & INTFC_CTLR_READY));
1057
1058         mb(); /* flush previous writes */
1059         brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1060                            cmd << brcmnand_cmd_shift(ctrl));
1061 }
1062
1063 /***********************************************************************
1064  * NAND MTD API: read/program/erase
1065  ***********************************************************************/
1066
1067 static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1068         unsigned int ctrl)
1069 {
1070         /* intentionally left blank */
1071 }
1072
1073 static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1074 {
1075         struct nand_chip *chip = mtd->priv;
1076         struct brcmnand_host *host = chip->priv;
1077         struct brcmnand_controller *ctrl = host->ctrl;
1078         unsigned long timeo = msecs_to_jiffies(100);
1079
1080         dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1081         if (ctrl->cmd_pending &&
1082                         wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1083                 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1084                                         >> brcmnand_cmd_shift(ctrl);
1085
1086                 dev_err_ratelimited(ctrl->dev,
1087                         "timeout waiting for command %#02x\n", cmd);
1088                 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1089                         brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1090         }
1091         ctrl->cmd_pending = 0;
1092         return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1093                                  INTFC_FLASH_STATUS;
1094 }
1095
1096 enum {
1097         LLOP_RE                         = BIT(16),
1098         LLOP_WE                         = BIT(17),
1099         LLOP_ALE                        = BIT(18),
1100         LLOP_CLE                        = BIT(19),
1101         LLOP_RETURN_IDLE                = BIT(31),
1102
1103         LLOP_DATA_MASK                  = GENMASK(15, 0),
1104 };
1105
1106 static int brcmnand_low_level_op(struct brcmnand_host *host,
1107                                  enum brcmnand_llop_type type, u32 data,
1108                                  bool last_op)
1109 {
1110         struct mtd_info *mtd = &host->mtd;
1111         struct nand_chip *chip = &host->chip;
1112         struct brcmnand_controller *ctrl = host->ctrl;
1113         u32 tmp;
1114
1115         tmp = data & LLOP_DATA_MASK;
1116         switch (type) {
1117         case LL_OP_CMD:
1118                 tmp |= LLOP_WE | LLOP_CLE;
1119                 break;
1120         case LL_OP_ADDR:
1121                 /* WE | ALE */
1122                 tmp |= LLOP_WE | LLOP_ALE;
1123                 break;
1124         case LL_OP_WR:
1125                 /* WE */
1126                 tmp |= LLOP_WE;
1127                 break;
1128         case LL_OP_RD:
1129                 /* RE */
1130                 tmp |= LLOP_RE;
1131                 break;
1132         }
1133         if (last_op)
1134                 /* RETURN_IDLE */
1135                 tmp |= LLOP_RETURN_IDLE;
1136
1137         dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1138
1139         brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1140         (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1141
1142         brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1143         return brcmnand_waitfunc(mtd, chip);
1144 }
1145
1146 static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1147                              int column, int page_addr)
1148 {
1149         struct nand_chip *chip = mtd->priv;
1150         struct brcmnand_host *host = chip->priv;
1151         struct brcmnand_controller *ctrl = host->ctrl;
1152         u64 addr = (u64)page_addr << chip->page_shift;
1153         int native_cmd = 0;
1154
1155         if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1156                         command == NAND_CMD_RNDOUT)
1157                 addr = (u64)column;
1158         /* Avoid propagating a negative, don't-care address */
1159         else if (page_addr < 0)
1160                 addr = 0;
1161
1162         dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1163                 (unsigned long long)addr);
1164
1165         host->last_cmd = command;
1166         host->last_byte = 0;
1167         host->last_addr = addr;
1168
1169         switch (command) {
1170         case NAND_CMD_RESET:
1171                 native_cmd = CMD_FLASH_RESET;
1172                 break;
1173         case NAND_CMD_STATUS:
1174                 native_cmd = CMD_STATUS_READ;
1175                 break;
1176         case NAND_CMD_READID:
1177                 native_cmd = CMD_DEVICE_ID_READ;
1178                 break;
1179         case NAND_CMD_READOOB:
1180                 native_cmd = CMD_SPARE_AREA_READ;
1181                 break;
1182         case NAND_CMD_ERASE1:
1183                 native_cmd = CMD_BLOCK_ERASE;
1184                 brcmnand_wp(mtd, 0);
1185                 break;
1186         case NAND_CMD_PARAM:
1187                 native_cmd = CMD_PARAMETER_READ;
1188                 break;
1189         case NAND_CMD_SET_FEATURES:
1190         case NAND_CMD_GET_FEATURES:
1191                 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1192                 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1193                 break;
1194         case NAND_CMD_RNDOUT:
1195                 native_cmd = CMD_PARAMETER_CHANGE_COL;
1196                 addr &= ~((u64)(FC_BYTES - 1));
1197                 /*
1198                  * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1199                  * NB: hwcfg.sector_size_1k may not be initialized yet
1200                  */
1201                 if (brcmnand_get_sector_size_1k(host)) {
1202                         host->hwcfg.sector_size_1k =
1203                                 brcmnand_get_sector_size_1k(host);
1204                         brcmnand_set_sector_size_1k(host, 0);
1205                 }
1206                 break;
1207         }
1208
1209         if (!native_cmd)
1210                 return;
1211
1212         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1213                 (host->cs << 16) | ((addr >> 32) & 0xffff));
1214         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1215         brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1216         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1217
1218         brcmnand_send_cmd(host, native_cmd);
1219         brcmnand_waitfunc(mtd, chip);
1220
1221         if (native_cmd == CMD_PARAMETER_READ ||
1222                         native_cmd == CMD_PARAMETER_CHANGE_COL) {
1223                 int i;
1224
1225                 brcmnand_soc_data_bus_prepare(ctrl->soc);
1226
1227                 /*
1228                  * Must cache the FLASH_CACHE now, since changes in
1229                  * SECTOR_SIZE_1K may invalidate it
1230                  */
1231                 for (i = 0; i < FC_WORDS; i++)
1232                         ctrl->flash_cache[i] = brcmnand_read_fc(ctrl, i);
1233
1234                 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1235
1236                 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1237                 if (host->hwcfg.sector_size_1k)
1238                         brcmnand_set_sector_size_1k(host,
1239                                                     host->hwcfg.sector_size_1k);
1240         }
1241
1242         /* Re-enable protection is necessary only after erase */
1243         if (command == NAND_CMD_ERASE1)
1244                 brcmnand_wp(mtd, 1);
1245 }
1246
1247 static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1248 {
1249         struct nand_chip *chip = mtd->priv;
1250         struct brcmnand_host *host = chip->priv;
1251         struct brcmnand_controller *ctrl = host->ctrl;
1252         uint8_t ret = 0;
1253         int addr, offs;
1254
1255         switch (host->last_cmd) {
1256         case NAND_CMD_READID:
1257                 if (host->last_byte < 4)
1258                         ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1259                                 (24 - (host->last_byte << 3));
1260                 else if (host->last_byte < 8)
1261                         ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1262                                 (56 - (host->last_byte << 3));
1263                 break;
1264
1265         case NAND_CMD_READOOB:
1266                 ret = oob_reg_read(ctrl, host->last_byte);
1267                 break;
1268
1269         case NAND_CMD_STATUS:
1270                 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1271                                         INTFC_FLASH_STATUS;
1272                 if (wp_on) /* hide WP status */
1273                         ret |= NAND_STATUS_WP;
1274                 break;
1275
1276         case NAND_CMD_PARAM:
1277         case NAND_CMD_RNDOUT:
1278                 addr = host->last_addr + host->last_byte;
1279                 offs = addr & (FC_BYTES - 1);
1280
1281                 /* At FC_BYTES boundary, switch to next column */
1282                 if (host->last_byte > 0 && offs == 0)
1283                         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
1284
1285                 ret = ctrl->flash_cache[offs >> 2] >>
1286                                         (24 - ((offs & 0x03) << 3));
1287                 break;
1288         case NAND_CMD_GET_FEATURES:
1289                 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1290                         ret = 0;
1291                 } else {
1292                         bool last = host->last_byte ==
1293                                 ONFI_SUBFEATURE_PARAM_LEN - 1;
1294                         brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1295                         ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1296                 }
1297         }
1298
1299         dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1300         host->last_byte++;
1301
1302         return ret;
1303 }
1304
1305 static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1306 {
1307         int i;
1308
1309         for (i = 0; i < len; i++, buf++)
1310                 *buf = brcmnand_read_byte(mtd);
1311 }
1312
1313 static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1314                                    int len)
1315 {
1316         int i;
1317         struct nand_chip *chip = mtd->priv;
1318         struct brcmnand_host *host = chip->priv;
1319
1320         switch (host->last_cmd) {
1321         case NAND_CMD_SET_FEATURES:
1322                 for (i = 0; i < len; i++)
1323                         brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1324                                                   (i + 1) == len);
1325                 break;
1326         default:
1327                 BUG();
1328                 break;
1329         }
1330 }
1331
1332 /**
1333  * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1334  * following ahead of time:
1335  *  - Is this descriptor the beginning or end of a linked list?
1336  *  - What is the (DMA) address of the next descriptor in the linked list?
1337  */
1338 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1339                                   struct brcm_nand_dma_desc *desc, u64 addr,
1340                                   dma_addr_t buf, u32 len, u8 dma_cmd,
1341                                   bool begin, bool end,
1342                                   dma_addr_t next_desc)
1343 {
1344         memset(desc, 0, sizeof(*desc));
1345         /* Descriptors are written in native byte order (wordwise) */
1346         desc->next_desc = lower_32_bits(next_desc);
1347         desc->next_desc_ext = upper_32_bits(next_desc);
1348         desc->cmd_irq = (dma_cmd << 24) |
1349                 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1350                 (!!begin) | ((!!end) << 1); /* head, tail */
1351 #ifdef CONFIG_CPU_BIG_ENDIAN
1352         desc->cmd_irq |= 0x01 << 12;
1353 #endif
1354         desc->dram_addr = lower_32_bits(buf);
1355         desc->dram_addr_ext = upper_32_bits(buf);
1356         desc->tfr_len = len;
1357         desc->total_len = len;
1358         desc->flash_addr = lower_32_bits(addr);
1359         desc->flash_addr_ext = upper_32_bits(addr);
1360         desc->cs = host->cs;
1361         desc->status_valid = 0x01;
1362         return 0;
1363 }
1364
1365 /**
1366  * Kick the FLASH_DMA engine, with a given DMA descriptor
1367  */
1368 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1369 {
1370         struct brcmnand_controller *ctrl = host->ctrl;
1371         unsigned long timeo = msecs_to_jiffies(100);
1372
1373         flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1374         (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1375         flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1376         (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1377
1378         /* Start FLASH_DMA engine */
1379         ctrl->dma_pending = true;
1380         mb(); /* flush previous writes */
1381         flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1382
1383         if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1384                 dev_err(ctrl->dev,
1385                                 "timeout waiting for DMA; status %#x, error status %#x\n",
1386                                 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1387                                 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1388         }
1389         ctrl->dma_pending = false;
1390         flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1391 }
1392
1393 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1394                               u32 len, u8 dma_cmd)
1395 {
1396         struct brcmnand_controller *ctrl = host->ctrl;
1397         dma_addr_t buf_pa;
1398         int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1399
1400         buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1401         if (dma_mapping_error(ctrl->dev, buf_pa)) {
1402                 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1403                 return -ENOMEM;
1404         }
1405
1406         brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1407                                    dma_cmd, true, true, 0);
1408
1409         brcmnand_dma_run(host, ctrl->dma_pa);
1410
1411         dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1412
1413         if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1414                 return -EBADMSG;
1415         else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1416                 return -EUCLEAN;
1417
1418         return 0;
1419 }
1420
1421 /*
1422  * Assumes proper CS is already set
1423  */
1424 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1425                                 u64 addr, unsigned int trans, u32 *buf,
1426                                 u8 *oob, u64 *err_addr)
1427 {
1428         struct brcmnand_host *host = chip->priv;
1429         struct brcmnand_controller *ctrl = host->ctrl;
1430         int i, j, ret = 0;
1431
1432         /* Clear error addresses */
1433         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1434         brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1435
1436         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1437                         (host->cs << 16) | ((addr >> 32) & 0xffff));
1438         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1439
1440         for (i = 0; i < trans; i++, addr += FC_BYTES) {
1441                 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1442                                    lower_32_bits(addr));
1443                 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1444                 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1445                 brcmnand_send_cmd(host, CMD_PAGE_READ);
1446                 brcmnand_waitfunc(mtd, chip);
1447
1448                 if (likely(buf)) {
1449                         brcmnand_soc_data_bus_prepare(ctrl->soc);
1450
1451                         for (j = 0; j < FC_WORDS; j++, buf++)
1452                                 *buf = brcmnand_read_fc(ctrl, j);
1453
1454                         brcmnand_soc_data_bus_unprepare(ctrl->soc);
1455                 }
1456
1457                 if (oob)
1458                         oob += read_oob_from_regs(ctrl, i, oob,
1459                                         mtd->oobsize / trans,
1460                                         host->hwcfg.sector_size_1k);
1461
1462                 if (!ret) {
1463                         *err_addr = brcmnand_read_reg(ctrl,
1464                                         BRCMNAND_UNCORR_ADDR) |
1465                                 ((u64)(brcmnand_read_reg(ctrl,
1466                                                 BRCMNAND_UNCORR_EXT_ADDR)
1467                                         & 0xffff) << 32);
1468                         if (*err_addr)
1469                                 ret = -EBADMSG;
1470                 }
1471
1472                 if (!ret) {
1473                         *err_addr = brcmnand_read_reg(ctrl,
1474                                         BRCMNAND_CORR_ADDR) |
1475                                 ((u64)(brcmnand_read_reg(ctrl,
1476                                                 BRCMNAND_CORR_EXT_ADDR)
1477                                         & 0xffff) << 32);
1478                         if (*err_addr)
1479                                 ret = -EUCLEAN;
1480                 }
1481         }
1482
1483         return ret;
1484 }
1485
1486 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1487                          u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1488 {
1489         struct brcmnand_host *host = chip->priv;
1490         struct brcmnand_controller *ctrl = host->ctrl;
1491         u64 err_addr = 0;
1492         int err;
1493
1494         dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1495
1496         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1497
1498         if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1499                 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1500                                              CMD_PAGE_READ);
1501                 if (err) {
1502                         if (mtd_is_bitflip_or_eccerr(err))
1503                                 err_addr = addr;
1504                         else
1505                                 return -EIO;
1506                 }
1507         } else {
1508                 if (oob)
1509                         memset(oob, 0x99, mtd->oobsize);
1510
1511                 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1512                                                oob, &err_addr);
1513         }
1514
1515         if (mtd_is_eccerr(err)) {
1516                 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1517                         (unsigned long long)err_addr);
1518                 mtd->ecc_stats.failed++;
1519                 /* NAND layer expects zero on ECC errors */
1520                 return 0;
1521         }
1522
1523         if (mtd_is_bitflip(err)) {
1524                 unsigned int corrected = brcmnand_count_corrected(ctrl);
1525
1526                 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1527                         (unsigned long long)err_addr);
1528                 mtd->ecc_stats.corrected += corrected;
1529                 /* Always exceed the software-imposed threshold */
1530                 return max(mtd->bitflip_threshold, corrected);
1531         }
1532
1533         return 0;
1534 }
1535
1536 static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1537                               uint8_t *buf, int oob_required, int page)
1538 {
1539         struct brcmnand_host *host = chip->priv;
1540         u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1541
1542         return brcmnand_read(mtd, chip, host->last_addr,
1543                         mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1544 }
1545
1546 static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1547                                   uint8_t *buf, int oob_required, int page)
1548 {
1549         struct brcmnand_host *host = chip->priv;
1550         u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1551         int ret;
1552
1553         brcmnand_set_ecc_enabled(host, 0);
1554         ret = brcmnand_read(mtd, chip, host->last_addr,
1555                         mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1556         brcmnand_set_ecc_enabled(host, 1);
1557         return ret;
1558 }
1559
1560 static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1561                              int page)
1562 {
1563         return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1564                         mtd->writesize >> FC_SHIFT,
1565                         NULL, (u8 *)chip->oob_poi);
1566 }
1567
1568 static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1569                                  int page)
1570 {
1571         struct brcmnand_host *host = chip->priv;
1572
1573         brcmnand_set_ecc_enabled(host, 0);
1574         brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1575                 mtd->writesize >> FC_SHIFT,
1576                 NULL, (u8 *)chip->oob_poi);
1577         brcmnand_set_ecc_enabled(host, 1);
1578         return 0;
1579 }
1580
1581 static int brcmnand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1582                                  uint32_t data_offs, uint32_t readlen,
1583                                  uint8_t *bufpoi, int page)
1584 {
1585         struct brcmnand_host *host = chip->priv;
1586
1587         return brcmnand_read(mtd, chip, host->last_addr + data_offs,
1588                         readlen >> FC_SHIFT, (u32 *)bufpoi, NULL);
1589 }
1590
1591 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1592                           u64 addr, const u32 *buf, u8 *oob)
1593 {
1594         struct brcmnand_host *host = chip->priv;
1595         struct brcmnand_controller *ctrl = host->ctrl;
1596         unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1597         int status, ret = 0;
1598
1599         dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1600
1601         if (unlikely((unsigned long)buf & 0x03)) {
1602                 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
1603                 buf = (u32 *)((unsigned long)buf & ~0x03);
1604         }
1605
1606         brcmnand_wp(mtd, 0);
1607
1608         for (i = 0; i < ctrl->max_oob; i += 4)
1609                 oob_reg_write(ctrl, i, 0xffffffff);
1610
1611         if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1612                 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1613                                         mtd->writesize, CMD_PROGRAM_PAGE))
1614                         ret = -EIO;
1615                 goto out;
1616         }
1617
1618         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1619                         (host->cs << 16) | ((addr >> 32) & 0xffff));
1620         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1621
1622         for (i = 0; i < trans; i++, addr += FC_BYTES) {
1623                 /* full address MUST be set before populating FC */
1624                 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1625                                    lower_32_bits(addr));
1626                 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1627
1628                 if (buf) {
1629                         brcmnand_soc_data_bus_prepare(ctrl->soc);
1630
1631                         for (j = 0; j < FC_WORDS; j++, buf++)
1632                                 brcmnand_write_fc(ctrl, j, *buf);
1633
1634                         brcmnand_soc_data_bus_unprepare(ctrl->soc);
1635                 } else if (oob) {
1636                         for (j = 0; j < FC_WORDS; j++)
1637                                 brcmnand_write_fc(ctrl, j, 0xffffffff);
1638                 }
1639
1640                 if (oob) {
1641                         oob += write_oob_to_regs(ctrl, i, oob,
1642                                         mtd->oobsize / trans,
1643                                         host->hwcfg.sector_size_1k);
1644                 }
1645
1646                 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1647                 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1648                 status = brcmnand_waitfunc(mtd, chip);
1649
1650                 if (status & NAND_STATUS_FAIL) {
1651                         dev_info(ctrl->dev, "program failed at %llx\n",
1652                                 (unsigned long long)addr);
1653                         ret = -EIO;
1654                         goto out;
1655                 }
1656         }
1657 out:
1658         brcmnand_wp(mtd, 1);
1659         return ret;
1660 }
1661
1662 static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1663                                const uint8_t *buf, int oob_required, int page)
1664 {
1665         struct brcmnand_host *host = chip->priv;
1666         void *oob = oob_required ? chip->oob_poi : NULL;
1667
1668         brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1669         return 0;
1670 }
1671
1672 static int brcmnand_write_page_raw(struct mtd_info *mtd,
1673                                    struct nand_chip *chip, const uint8_t *buf,
1674                                    int oob_required, int page)
1675 {
1676         struct brcmnand_host *host = chip->priv;
1677         void *oob = oob_required ? chip->oob_poi : NULL;
1678
1679         brcmnand_set_ecc_enabled(host, 0);
1680         brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1681         brcmnand_set_ecc_enabled(host, 1);
1682         return 0;
1683 }
1684
1685 static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1686                                   int page)
1687 {
1688         return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1689                                   NULL, chip->oob_poi);
1690 }
1691
1692 static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1693                                   int page)
1694 {
1695         struct brcmnand_host *host = chip->priv;
1696         int ret;
1697
1698         brcmnand_set_ecc_enabled(host, 0);
1699         ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1700                                  (u8 *)chip->oob_poi);
1701         brcmnand_set_ecc_enabled(host, 1);
1702
1703         return ret;
1704 }
1705
1706 /***********************************************************************
1707  * Per-CS setup (1 NAND device)
1708  ***********************************************************************/
1709
1710 static int brcmnand_set_cfg(struct brcmnand_host *host,
1711                             struct brcmnand_cfg *cfg)
1712 {
1713         struct brcmnand_controller *ctrl = host->ctrl;
1714         struct nand_chip *chip = &host->chip;
1715         u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1716         u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1717                         BRCMNAND_CS_CFG_EXT);
1718         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1719                         BRCMNAND_CS_ACC_CONTROL);
1720         u8 block_size = 0, page_size = 0, device_size = 0;
1721         u32 tmp;
1722
1723         if (ctrl->block_sizes) {
1724                 int i, found;
1725
1726                 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1727                         if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1728                                 block_size = i;
1729                                 found = 1;
1730                         }
1731                 if (!found) {
1732                         dev_warn(ctrl->dev, "invalid block size %u\n",
1733                                         cfg->block_size);
1734                         return -EINVAL;
1735                 }
1736         } else {
1737                 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
1738         }
1739
1740         if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
1741                                 cfg->block_size > ctrl->max_block_size)) {
1742                 dev_warn(ctrl->dev, "invalid block size %u\n",
1743                                 cfg->block_size);
1744                 block_size = 0;
1745         }
1746
1747         if (ctrl->page_sizes) {
1748                 int i, found;
1749
1750                 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
1751                         if (ctrl->page_sizes[i] == cfg->page_size) {
1752                                 page_size = i;
1753                                 found = 1;
1754                         }
1755                 if (!found) {
1756                         dev_warn(ctrl->dev, "invalid page size %u\n",
1757                                         cfg->page_size);
1758                         return -EINVAL;
1759                 }
1760         } else {
1761                 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
1762         }
1763
1764         if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
1765                                 cfg->page_size > ctrl->max_page_size)) {
1766                 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
1767                 return -EINVAL;
1768         }
1769
1770         if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
1771                 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
1772                         (unsigned long long)cfg->device_size);
1773                 return -EINVAL;
1774         }
1775         device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
1776
1777         tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
1778                 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
1779                 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
1780                 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
1781                 (device_size << CFG_DEVICE_SIZE_SHIFT);
1782         if (cfg_offs == cfg_ext_offs) {
1783                 tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
1784                        (block_size << CFG_BLK_SIZE_SHIFT);
1785                 nand_writereg(ctrl, cfg_offs, tmp);
1786         } else {
1787                 nand_writereg(ctrl, cfg_offs, tmp);
1788                 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
1789                       (block_size << CFG_EXT_BLK_SIZE_SHIFT);
1790                 nand_writereg(ctrl, cfg_ext_offs, tmp);
1791         }
1792
1793         tmp = nand_readreg(ctrl, acc_control_offs);
1794         tmp &= ~brcmnand_ecc_level_mask(ctrl);
1795         tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
1796         tmp &= ~brcmnand_spare_area_mask(ctrl);
1797         tmp |= cfg->spare_area_size;
1798         nand_writereg(ctrl, acc_control_offs, tmp);
1799
1800         brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
1801
1802         /* threshold = ceil(BCH-level * 0.75) */
1803         brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
1804
1805         return 0;
1806 }
1807
1808 static void brcmnand_print_cfg(char *buf, struct brcmnand_cfg *cfg)
1809 {
1810         buf += sprintf(buf,
1811                 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
1812                 (unsigned long long)cfg->device_size >> 20,
1813                 cfg->block_size >> 10,
1814                 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
1815                 cfg->page_size >= 1024 ? "KiB" : "B",
1816                 cfg->spare_area_size, cfg->device_width);
1817
1818         /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
1819         if (is_hamming_ecc(cfg))
1820                 sprintf(buf, ", Hamming ECC");
1821         else if (cfg->sector_size_1k)
1822                 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
1823         else
1824                 sprintf(buf, ", BCH-%u", cfg->ecc_level);
1825 }
1826
1827 /*
1828  * Minimum number of bytes to address a page. Calculated as:
1829  *     roundup(log2(size / page-size) / 8)
1830  *
1831  * NB: the following does not "round up" for non-power-of-2 'size'; but this is
1832  *     OK because many other things will break if 'size' is irregular...
1833  */
1834 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
1835 {
1836         return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
1837 }
1838
1839 static int brcmnand_setup_dev(struct brcmnand_host *host)
1840 {
1841         struct mtd_info *mtd = &host->mtd;
1842         struct nand_chip *chip = &host->chip;
1843         struct brcmnand_controller *ctrl = host->ctrl;
1844         struct brcmnand_cfg *cfg = &host->hwcfg;
1845         char msg[128];
1846         u32 offs, tmp, oob_sector;
1847         int ret;
1848
1849         memset(cfg, 0, sizeof(*cfg));
1850
1851         ret = of_property_read_u32(chip->flash_node,
1852                                    "brcm,nand-oob-sector-size",
1853                                    &oob_sector);
1854         if (ret) {
1855                 /* Use detected size */
1856                 cfg->spare_area_size = mtd->oobsize /
1857                                         (mtd->writesize >> FC_SHIFT);
1858         } else {
1859                 cfg->spare_area_size = oob_sector;
1860         }
1861         if (cfg->spare_area_size > ctrl->max_oob)
1862                 cfg->spare_area_size = ctrl->max_oob;
1863         /*
1864          * Set oobsize to be consistent with controller's spare_area_size, as
1865          * the rest is inaccessible.
1866          */
1867         mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
1868
1869         cfg->device_size = mtd->size;
1870         cfg->block_size = mtd->erasesize;
1871         cfg->page_size = mtd->writesize;
1872         cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
1873         cfg->col_adr_bytes = 2;
1874         cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
1875
1876         switch (chip->ecc.size) {
1877         case 512:
1878                 if (chip->ecc.strength == 1) /* Hamming */
1879                         cfg->ecc_level = 15;
1880                 else
1881                         cfg->ecc_level = chip->ecc.strength;
1882                 cfg->sector_size_1k = 0;
1883                 break;
1884         case 1024:
1885                 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
1886                         dev_err(ctrl->dev, "1KB sectors not supported\n");
1887                         return -EINVAL;
1888                 }
1889                 if (chip->ecc.strength & 0x1) {
1890                         dev_err(ctrl->dev,
1891                                 "odd ECC not supported with 1KB sectors\n");
1892                         return -EINVAL;
1893                 }
1894
1895                 cfg->ecc_level = chip->ecc.strength >> 1;
1896                 cfg->sector_size_1k = 1;
1897                 break;
1898         default:
1899                 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
1900                         chip->ecc.size);
1901                 return -EINVAL;
1902         }
1903
1904         cfg->ful_adr_bytes = cfg->blk_adr_bytes;
1905         if (mtd->writesize > 512)
1906                 cfg->ful_adr_bytes += cfg->col_adr_bytes;
1907         else
1908                 cfg->ful_adr_bytes += 1;
1909
1910         ret = brcmnand_set_cfg(host, cfg);
1911         if (ret)
1912                 return ret;
1913
1914         brcmnand_set_ecc_enabled(host, 1);
1915
1916         brcmnand_print_cfg(msg, cfg);
1917         dev_info(ctrl->dev, "detected %s\n", msg);
1918
1919         /* Configure ACC_CONTROL */
1920         offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
1921         tmp = nand_readreg(ctrl, offs);
1922         tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
1923         tmp &= ~ACC_CONTROL_RD_ERASED;
1924         tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
1925         if (ctrl->features & BRCMNAND_HAS_PREFETCH) {
1926                 /*
1927                  * FIXME: Flash DMA + prefetch may see spurious erased-page ECC
1928                  * errors
1929                  */
1930                 if (has_flash_dma(ctrl))
1931                         tmp &= ~ACC_CONTROL_PREFETCH;
1932                 else
1933                         tmp |= ACC_CONTROL_PREFETCH;
1934         }
1935         nand_writereg(ctrl, offs, tmp);
1936
1937         return 0;
1938 }
1939
1940 static int brcmnand_init_cs(struct brcmnand_host *host)
1941 {
1942         struct brcmnand_controller *ctrl = host->ctrl;
1943         struct device_node *dn = host->of_node;
1944         struct platform_device *pdev = host->pdev;
1945         struct mtd_info *mtd;
1946         struct nand_chip *chip;
1947         int ret;
1948         u16 cfg_offs;
1949         struct mtd_part_parser_data ppdata = { .of_node = dn };
1950
1951         ret = of_property_read_u32(dn, "reg", &host->cs);
1952         if (ret) {
1953                 dev_err(&pdev->dev, "can't get chip-select\n");
1954                 return -ENXIO;
1955         }
1956
1957         mtd = &host->mtd;
1958         chip = &host->chip;
1959
1960         chip->flash_node = dn;
1961         chip->priv = host;
1962         mtd->priv = chip;
1963         mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
1964                                    host->cs);
1965         mtd->owner = THIS_MODULE;
1966         mtd->dev.parent = &pdev->dev;
1967
1968         chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
1969         chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
1970
1971         chip->cmd_ctrl = brcmnand_cmd_ctrl;
1972         chip->cmdfunc = brcmnand_cmdfunc;
1973         chip->waitfunc = brcmnand_waitfunc;
1974         chip->read_byte = brcmnand_read_byte;
1975         chip->read_buf = brcmnand_read_buf;
1976         chip->write_buf = brcmnand_write_buf;
1977
1978         chip->ecc.mode = NAND_ECC_HW;
1979         chip->ecc.read_page = brcmnand_read_page;
1980         chip->ecc.read_subpage = brcmnand_read_subpage;
1981         chip->ecc.write_page = brcmnand_write_page;
1982         chip->ecc.read_page_raw = brcmnand_read_page_raw;
1983         chip->ecc.write_page_raw = brcmnand_write_page_raw;
1984         chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
1985         chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
1986         chip->ecc.read_oob = brcmnand_read_oob;
1987         chip->ecc.write_oob = brcmnand_write_oob;
1988
1989         chip->controller = &ctrl->controller;
1990
1991         /*
1992          * The bootloader might have configured 16bit mode but
1993          * NAND READID command only works in 8bit mode. We force
1994          * 8bit mode here to ensure that NAND READID commands works.
1995          */
1996         cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1997         nand_writereg(ctrl, cfg_offs,
1998                       nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
1999
2000         if (nand_scan_ident(mtd, 1, NULL))
2001                 return -ENXIO;
2002
2003         chip->options |= NAND_NO_SUBPAGE_WRITE;
2004         /*
2005          * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
2006          * to/from, and have nand_base pass us a bounce buffer instead, as
2007          * needed.
2008          */
2009         chip->options |= NAND_USE_BOUNCE_BUFFER;
2010
2011         if (of_get_nand_on_flash_bbt(dn))
2012                 chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
2013
2014         if (brcmnand_setup_dev(host))
2015                 return -ENXIO;
2016
2017         chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2018         /* only use our internal HW threshold */
2019         mtd->bitflip_threshold = 1;
2020
2021         chip->ecc.layout = brcmstb_choose_ecc_layout(host);
2022         if (!chip->ecc.layout)
2023                 return -ENXIO;
2024
2025         if (nand_scan_tail(mtd))
2026                 return -ENXIO;
2027
2028         return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
2029 }
2030
2031 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2032                                             int restore)
2033 {
2034         struct brcmnand_controller *ctrl = host->ctrl;
2035         u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2036         u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2037                         BRCMNAND_CS_CFG_EXT);
2038         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2039                         BRCMNAND_CS_ACC_CONTROL);
2040         u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2041         u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2042
2043         if (restore) {
2044                 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2045                 if (cfg_offs != cfg_ext_offs)
2046                         nand_writereg(ctrl, cfg_ext_offs,
2047                                       host->hwcfg.config_ext);
2048                 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2049                 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2050                 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2051         } else {
2052                 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2053                 if (cfg_offs != cfg_ext_offs)
2054                         host->hwcfg.config_ext =
2055                                 nand_readreg(ctrl, cfg_ext_offs);
2056                 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2057                 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2058                 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2059         }
2060 }
2061
2062 static int brcmnand_suspend(struct device *dev)
2063 {
2064         struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2065         struct brcmnand_host *host;
2066
2067         list_for_each_entry(host, &ctrl->host_list, node)
2068                 brcmnand_save_restore_cs_config(host, 0);
2069
2070         ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2071         ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2072         ctrl->corr_stat_threshold =
2073                 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2074
2075         if (has_flash_dma(ctrl))
2076                 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2077
2078         return 0;
2079 }
2080
2081 static int brcmnand_resume(struct device *dev)
2082 {
2083         struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2084         struct brcmnand_host *host;
2085
2086         if (has_flash_dma(ctrl)) {
2087                 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2088                 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2089         }
2090
2091         brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2092         brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2093         brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2094                         ctrl->corr_stat_threshold);
2095         if (ctrl->soc) {
2096                 /* Clear/re-enable interrupt */
2097                 ctrl->soc->ctlrdy_ack(ctrl->soc);
2098                 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2099         }
2100
2101         list_for_each_entry(host, &ctrl->host_list, node) {
2102                 struct mtd_info *mtd = &host->mtd;
2103                 struct nand_chip *chip = mtd->priv;
2104
2105                 brcmnand_save_restore_cs_config(host, 1);
2106
2107                 /* Reset the chip, required by some chips after power-up */
2108                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2109         }
2110
2111         return 0;
2112 }
2113
2114 const struct dev_pm_ops brcmnand_pm_ops = {
2115         .suspend                = brcmnand_suspend,
2116         .resume                 = brcmnand_resume,
2117 };
2118 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2119
2120 static const struct of_device_id brcmnand_of_match[] = {
2121         { .compatible = "brcm,brcmnand-v4.0" },
2122         { .compatible = "brcm,brcmnand-v5.0" },
2123         { .compatible = "brcm,brcmnand-v6.0" },
2124         { .compatible = "brcm,brcmnand-v6.1" },
2125         { .compatible = "brcm,brcmnand-v7.0" },
2126         { .compatible = "brcm,brcmnand-v7.1" },
2127         {},
2128 };
2129 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2130
2131 /***********************************************************************
2132  * Platform driver setup (per controller)
2133  ***********************************************************************/
2134
2135 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2136 {
2137         struct device *dev = &pdev->dev;
2138         struct device_node *dn = dev->of_node, *child;
2139         struct brcmnand_controller *ctrl;
2140         struct resource *res;
2141         int ret;
2142
2143         /* We only support device-tree instantiation */
2144         if (!dn)
2145                 return -ENODEV;
2146
2147         if (!of_match_node(brcmnand_of_match, dn))
2148                 return -ENODEV;
2149
2150         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2151         if (!ctrl)
2152                 return -ENOMEM;
2153
2154         dev_set_drvdata(dev, ctrl);
2155         ctrl->dev = dev;
2156
2157         init_completion(&ctrl->done);
2158         init_completion(&ctrl->dma_done);
2159         spin_lock_init(&ctrl->controller.lock);
2160         init_waitqueue_head(&ctrl->controller.wq);
2161         INIT_LIST_HEAD(&ctrl->host_list);
2162
2163         /* NAND register range */
2164         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2165         ctrl->nand_base = devm_ioremap_resource(dev, res);
2166         if (IS_ERR(ctrl->nand_base))
2167                 return PTR_ERR(ctrl->nand_base);
2168
2169         /* Initialize NAND revision */
2170         ret = brcmnand_revision_init(ctrl);
2171         if (ret)
2172                 return ret;
2173
2174         /*
2175          * Most chips have this cache at a fixed offset within 'nand' block.
2176          * Some must specify this region separately.
2177          */
2178         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2179         if (res) {
2180                 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2181                 if (IS_ERR(ctrl->nand_fc))
2182                         return PTR_ERR(ctrl->nand_fc);
2183         } else {
2184                 ctrl->nand_fc = ctrl->nand_base +
2185                                 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2186         }
2187
2188         /* FLASH_DMA */
2189         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2190         if (res) {
2191                 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2192                 if (IS_ERR(ctrl->flash_dma_base))
2193                         return PTR_ERR(ctrl->flash_dma_base);
2194
2195                 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2196                 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2197
2198                 /* Allocate descriptor(s) */
2199                 ctrl->dma_desc = dmam_alloc_coherent(dev,
2200                                                      sizeof(*ctrl->dma_desc),
2201                                                      &ctrl->dma_pa, GFP_KERNEL);
2202                 if (!ctrl->dma_desc)
2203                         return -ENOMEM;
2204
2205                 ctrl->dma_irq = platform_get_irq(pdev, 1);
2206                 if ((int)ctrl->dma_irq < 0) {
2207                         dev_err(dev, "missing FLASH_DMA IRQ\n");
2208                         return -ENODEV;
2209                 }
2210
2211                 ret = devm_request_irq(dev, ctrl->dma_irq,
2212                                 brcmnand_dma_irq, 0, DRV_NAME,
2213                                 ctrl);
2214                 if (ret < 0) {
2215                         dev_err(dev, "can't allocate IRQ %d: error %d\n",
2216                                         ctrl->dma_irq, ret);
2217                         return ret;
2218                 }
2219
2220                 dev_info(dev, "enabling FLASH_DMA\n");
2221         }
2222
2223         /* Disable automatic device ID config, direct addressing */
2224         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2225                          CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2226         /* Disable XOR addressing */
2227         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2228
2229         if (ctrl->features & BRCMNAND_HAS_WP) {
2230                 /* Permanently disable write protection */
2231                 if (wp_on == 2)
2232                         brcmnand_set_wp(ctrl, false);
2233         } else {
2234                 wp_on = 0;
2235         }
2236
2237         /* IRQ */
2238         ctrl->irq = platform_get_irq(pdev, 0);
2239         if ((int)ctrl->irq < 0) {
2240                 dev_err(dev, "no IRQ defined\n");
2241                 return -ENODEV;
2242         }
2243
2244         /*
2245          * Some SoCs integrate this controller (e.g., its interrupt bits) in
2246          * interesting ways
2247          */
2248         if (soc) {
2249                 ctrl->soc = soc;
2250
2251                 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2252                                        DRV_NAME, ctrl);
2253
2254                 /* Enable interrupt */
2255                 ctrl->soc->ctlrdy_ack(ctrl->soc);
2256                 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2257         } else {
2258                 /* Use standard interrupt infrastructure */
2259                 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2260                                        DRV_NAME, ctrl);
2261         }
2262         if (ret < 0) {
2263                 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2264                         ctrl->irq, ret);
2265                 return ret;
2266         }
2267
2268         for_each_available_child_of_node(dn, child) {
2269                 if (of_device_is_compatible(child, "brcm,nandcs")) {
2270                         struct brcmnand_host *host;
2271
2272                         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2273                         if (!host)
2274                                 return -ENOMEM;
2275                         host->pdev = pdev;
2276                         host->ctrl = ctrl;
2277                         host->of_node = child;
2278
2279                         ret = brcmnand_init_cs(host);
2280                         if (ret)
2281                                 continue; /* Try all chip-selects */
2282
2283                         list_add_tail(&host->node, &ctrl->host_list);
2284                 }
2285         }
2286
2287         /* No chip-selects could initialize properly */
2288         if (list_empty(&ctrl->host_list))
2289                 return -ENODEV;
2290
2291         return 0;
2292 }
2293 EXPORT_SYMBOL_GPL(brcmnand_probe);
2294
2295 int brcmnand_remove(struct platform_device *pdev)
2296 {
2297         struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2298         struct brcmnand_host *host;
2299
2300         list_for_each_entry(host, &ctrl->host_list, node)
2301                 nand_release(&host->mtd);
2302
2303         dev_set_drvdata(&pdev->dev, NULL);
2304
2305         return 0;
2306 }
2307 EXPORT_SYMBOL_GPL(brcmnand_remove);
2308
2309 MODULE_LICENSE("GPL v2");
2310 MODULE_AUTHOR("Kevin Cernekee");
2311 MODULE_AUTHOR("Brian Norris");
2312 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2313 MODULE_ALIAS("platform:brcmnand");