kernel/drivers/mmc/host/sh_mmcif.c

   1 /*
   2  * MMCIF eMMC driver.
   3  *
   4  * Copyright (C) 2010 Renesas Solutions Corp.
   5  * Yusuke Goda <yusuke.goda.sx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  *
  12  * TODO
  13  *  1. DMA
  14  *  2. Power management
  15  *  3. Handle MMC errors better
  16  *
  17  */
  18
  19 /*
  20  * The MMCIF driver is now processing MMC requests asynchronously, according
  21  * to the Linux MMC API requirement.
  22  *
  23  * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
  24  * data, and optional stop. To achieve asynchronous processing each of these
  25  * stages is split into two halves: a top and a bottom half. The top half
  26  * initialises the hardware, installs a timeout handler to handle completion
  27  * timeouts, and returns. In case of the command stage this immediately returns
  28  * control to the caller, leaving all further processing to run asynchronously.
  29  * All further request processing is performed by the bottom halves.
  30  *
  31  * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
  32  * thread, a DMA completion callback, if DMA is used, a timeout work, and
  33  * request- and stage-specific handler methods.
  34  *
  35  * Each bottom half run begins with either a hardware interrupt, a DMA callback
  36  * invocation, or a timeout work run. In case of an error or a successful
  37  * processing completion, the MMC core is informed and the request processing is
  38  * finished. In case processing has to continue, i.e., if data has to be read
  39  * from or written to the card, or if a stop command has to be sent, the next
  40  * top half is called, which performs the necessary hardware handling and
  41  * reschedules the timeout work. This returns the driver state machine into the
  42  * bottom half waiting state.
  43  */
  44
  45 #include <linux/bitops.h>
  46 #include <linux/clk.h>
  47 #include <linux/completion.h>
  48 #include <linux/delay.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/dmaengine.h>
  51 #include <linux/mmc/card.h>
  52 #include <linux/mmc/core.h>
  53 #include <linux/mmc/host.h>
  54 #include <linux/mmc/mmc.h>
  55 #include <linux/mmc/sdio.h>
  56 #include <linux/mmc/sh_mmcif.h>
  57 #include <linux/mmc/slot-gpio.h>
  58 #include <linux/mod_devicetable.h>
  59 #include <linux/mutex.h>
  60 #include <linux/of_device.h>
  61 #include <linux/pagemap.h>
  62 #include <linux/platform_device.h>
  63 #include <linux/pm_qos.h>
  64 #include <linux/pm_runtime.h>
  65 #include <linux/sh_dma.h>
  66 #include <linux/spinlock.h>
  67 #include <linux/module.h>
  68
  69 #define DRIVER_NAME     "sh_mmcif"
  70 #define DRIVER_VERSION  "2010-04-28"
  71
  72 /* CE_CMD_SET */
  73 #define CMD_MASK                0x3f000000
  74 #define CMD_SET_RTYP_NO         ((0 << 23) | (0 << 22))
  75 #define CMD_SET_RTYP_6B         ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
  76 #define CMD_SET_RTYP_17B        ((1 << 23) | (0 << 22)) /* R2 */
  77 #define CMD_SET_RBSY            (1 << 21) /* R1b */
  78 #define CMD_SET_CCSEN           (1 << 20)
  79 #define CMD_SET_WDAT            (1 << 19) /* 1: on data, 0: no data */
  80 #define CMD_SET_DWEN            (1 << 18) /* 1: write, 0: read */
  81 #define CMD_SET_CMLTE           (1 << 17) /* 1: multi block trans, 0: single */
  82 #define CMD_SET_CMD12EN         (1 << 16) /* 1: CMD12 auto issue */
  83 #define CMD_SET_RIDXC_INDEX     ((0 << 15) | (0 << 14)) /* index check */
  84 #define CMD_SET_RIDXC_BITS      ((0 << 15) | (1 << 14)) /* check bits check */
  85 #define CMD_SET_RIDXC_NO        ((1 << 15) | (0 << 14)) /* no check */
  86 #define CMD_SET_CRC7C           ((0 << 13) | (0 << 12)) /* CRC7 check*/
  87 #define CMD_SET_CRC7C_BITS      ((0 << 13) | (1 << 12)) /* check bits check*/
  88 #define CMD_SET_CRC7C_INTERNAL  ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
  89 #define CMD_SET_CRC16C          (1 << 10) /* 0: CRC16 check*/
  90 #define CMD_SET_CRCSTE          (1 << 8) /* 1: not receive CRC status */
  91 #define CMD_SET_TBIT            (1 << 7) /* 1: tran mission bit "Low" */
  92 #define CMD_SET_OPDM            (1 << 6) /* 1: open/drain */
  93 #define CMD_SET_CCSH            (1 << 5)
  94 #define CMD_SET_DARS            (1 << 2) /* Dual Data Rate */
  95 #define CMD_SET_DATW_1          ((0 << 1) | (0 << 0)) /* 1bit */
  96 #define CMD_SET_DATW_4          ((0 << 1) | (1 << 0)) /* 4bit */
  97 #define CMD_SET_DATW_8          ((1 << 1) | (0 << 0)) /* 8bit */
  98
  99 /* CE_CMD_CTRL */
 100 #define CMD_CTRL_BREAK          (1 << 0)
 101
 102 /* CE_BLOCK_SET */
 103 #define BLOCK_SIZE_MASK         0x0000ffff
 104
 105 /* CE_INT */
 106 #define INT_CCSDE               (1 << 29)
 107 #define INT_CMD12DRE            (1 << 26)
 108 #define INT_CMD12RBE            (1 << 25)
 109 #define INT_CMD12CRE            (1 << 24)
 110 #define INT_DTRANE              (1 << 23)
 111 #define INT_BUFRE               (1 << 22)
 112 #define INT_BUFWEN              (1 << 21)
 113 #define INT_BUFREN              (1 << 20)
 114 #define INT_CCSRCV              (1 << 19)
 115 #define INT_RBSYE               (1 << 17)
 116 #define INT_CRSPE               (1 << 16)
 117 #define INT_CMDVIO              (1 << 15)
 118 #define INT_BUFVIO              (1 << 14)
 119 #define INT_WDATERR             (1 << 11)
 120 #define INT_RDATERR             (1 << 10)
 121 #define INT_RIDXERR             (1 << 9)
 122 #define INT_RSPERR              (1 << 8)
 123 #define INT_CCSTO               (1 << 5)
 124 #define INT_CRCSTO              (1 << 4)
 125 #define INT_WDATTO              (1 << 3)
 126 #define INT_RDATTO              (1 << 2)
 127 #define INT_RBSYTO              (1 << 1)
 128 #define INT_RSPTO               (1 << 0)
 129 #define INT_ERR_STS             (INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
 130                                  INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
 131                                  INT_CCSTO | INT_CRCSTO | INT_WDATTO |    \
 132                                  INT_RDATTO | INT_RBSYTO | INT_RSPTO)
 133
 134 #define INT_ALL                 (INT_RBSYE | INT_CRSPE | INT_BUFREN |    \
 135                                  INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \
 136                                  INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE)
 137
 138 #define INT_CCS                 (INT_CCSTO | INT_CCSRCV | INT_CCSDE)
 139
 140 /* CE_INT_MASK */
 141 #define MASK_ALL                0x00000000
 142 #define MASK_MCCSDE             (1 << 29)
 143 #define MASK_MCMD12DRE          (1 << 26)
 144 #define MASK_MCMD12RBE          (1 << 25)
 145 #define MASK_MCMD12CRE          (1 << 24)
 146 #define MASK_MDTRANE            (1 << 23)
 147 #define MASK_MBUFRE             (1 << 22)
 148 #define MASK_MBUFWEN            (1 << 21)
 149 #define MASK_MBUFREN            (1 << 20)
 150 #define MASK_MCCSRCV            (1 << 19)
 151 #define MASK_MRBSYE             (1 << 17)
 152 #define MASK_MCRSPE             (1 << 16)
 153 #define MASK_MCMDVIO            (1 << 15)
 154 #define MASK_MBUFVIO            (1 << 14)
 155 #define MASK_MWDATERR           (1 << 11)
 156 #define MASK_MRDATERR           (1 << 10)
 157 #define MASK_MRIDXERR           (1 << 9)
 158 #define MASK_MRSPERR            (1 << 8)
 159 #define MASK_MCCSTO             (1 << 5)
 160 #define MASK_MCRCSTO            (1 << 4)
 161 #define MASK_MWDATTO            (1 << 3)
 162 #define MASK_MRDATTO            (1 << 2)
 163 #define MASK_MRBSYTO            (1 << 1)
 164 #define MASK_MRSPTO             (1 << 0)
 165
 166 #define MASK_START_CMD          (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
 167                                  MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
 168                                  MASK_MCRCSTO | MASK_MWDATTO | \
 169                                  MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
 170
 171 #define MASK_CLEAN              (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE |      \
 172                                  MASK_MBUFREN | MASK_MBUFWEN |                  \
 173                                  MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE |  \
 174                                  MASK_MCMD12RBE | MASK_MCMD12CRE)
 175
 176 /* CE_HOST_STS1 */
 177 #define STS1_CMDSEQ             (1 << 31)
 178
 179 /* CE_HOST_STS2 */
 180 #define STS2_CRCSTE             (1 << 31)
 181 #define STS2_CRC16E             (1 << 30)
 182 #define STS2_AC12CRCE           (1 << 29)
 183 #define STS2_RSPCRC7E           (1 << 28)
 184 #define STS2_CRCSTEBE           (1 << 27)
 185 #define STS2_RDATEBE            (1 << 26)
 186 #define STS2_AC12REBE           (1 << 25)
 187 #define STS2_RSPEBE             (1 << 24)
 188 #define STS2_AC12IDXE           (1 << 23)
 189 #define STS2_RSPIDXE            (1 << 22)
 190 #define STS2_CCSTO              (1 << 15)
 191 #define STS2_RDATTO             (1 << 14)
 192 #define STS2_DATBSYTO           (1 << 13)
 193 #define STS2_CRCSTTO            (1 << 12)
 194 #define STS2_AC12BSYTO          (1 << 11)
 195 #define STS2_RSPBSYTO           (1 << 10)
 196 #define STS2_AC12RSPTO          (1 << 9)
 197 #define STS2_RSPTO              (1 << 8)
 198 #define STS2_CRC_ERR            (STS2_CRCSTE | STS2_CRC16E |            \
 199                                  STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
 200 #define STS2_TIMEOUT_ERR        (STS2_CCSTO | STS2_RDATTO |             \
 201                                  STS2_DATBSYTO | STS2_CRCSTTO |         \
 202                                  STS2_AC12BSYTO | STS2_RSPBSYTO |       \
 203                                  STS2_AC12RSPTO | STS2_RSPTO)
 204
 205 #define CLKDEV_EMMC_DATA        52000000 /* 52MHz */
 206 #define CLKDEV_MMC_DATA         20000000 /* 20MHz */
 207 #define CLKDEV_INIT             400000   /* 400 KHz */
 208
 209 enum sh_mmcif_state {
 210         STATE_IDLE,
 211         STATE_REQUEST,
 212         STATE_IOS,
 213         STATE_TIMEOUT,
 214 };
 215
 216 enum sh_mmcif_wait_for {
 217         MMCIF_WAIT_FOR_REQUEST,
 218         MMCIF_WAIT_FOR_CMD,
 219         MMCIF_WAIT_FOR_MREAD,
 220         MMCIF_WAIT_FOR_MWRITE,
 221         MMCIF_WAIT_FOR_READ,
 222         MMCIF_WAIT_FOR_WRITE,
 223         MMCIF_WAIT_FOR_READ_END,
 224         MMCIF_WAIT_FOR_WRITE_END,
 225         MMCIF_WAIT_FOR_STOP,
 226 };
 227
 228 /*
 229  * difference for each SoC
 230  */
 231 struct sh_mmcif_host {
 232         struct mmc_host *mmc;
 233         struct mmc_request *mrq;
 234         struct platform_device *pd;
 235         struct clk *clk;
 236         int bus_width;
 237         unsigned char timing;
 238         bool sd_error;
 239         bool dying;
 240         long timeout;
 241         void __iomem *addr;
 242         u32 *pio_ptr;
 243         spinlock_t lock;                /* protect sh_mmcif_host::state */
 244         enum sh_mmcif_state state;
 245         enum sh_mmcif_wait_for wait_for;
 246         struct delayed_work timeout_work;
 247         size_t blocksize;
 248         int sg_idx;
 249         int sg_blkidx;
 250         bool power;
 251         bool card_present;
 252         bool ccs_enable;                /* Command Completion Signal support */
 253         bool clk_ctrl2_enable;
 254         struct mutex thread_lock;
 255         u32 clkdiv_map;         /* see CE_CLK_CTRL::CLKDIV */
 256
 257         /* DMA support */
 258         struct dma_chan         *chan_rx;
 259         struct dma_chan         *chan_tx;
 260         struct completion       dma_complete;
 261         bool                    dma_active;
 262 };
 263
 264 static const struct of_device_id sh_mmcif_of_match[] = {
 265         { .compatible = "renesas,sh-mmcif" },
 266         { }
 267 };
 268 MODULE_DEVICE_TABLE(of, sh_mmcif_of_match);
 269
 270 #define sh_mmcif_host_to_dev(host) (&host->pd->dev)
 271
 272 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
 273                                         unsigned int reg, u32 val)
 274 {
 275         writel(val | readl(host->addr + reg), host->addr + reg);
 276 }
 277
 278 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
 279                                         unsigned int reg, u32 val)
 280 {
 281         writel(~val & readl(host->addr + reg), host->addr + reg);
 282 }
 283
 284 static void sh_mmcif_dma_complete(void *arg)
 285 {
 286         struct sh_mmcif_host *host = arg;
 287         struct mmc_request *mrq = host->mrq;
 288         struct device *dev = sh_mmcif_host_to_dev(host);
 289
 290         dev_dbg(dev, "Command completed\n");
 291
 292         if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n",
 293                  dev_name(dev)))
 294                 return;
 295
 296         complete(&host->dma_complete);
 297 }
 298
 299 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
 300 {
 301         struct mmc_data *data = host->mrq->data;
 302         struct scatterlist *sg = data->sg;
 303         struct dma_async_tx_descriptor *desc = NULL;
 304         struct dma_chan *chan = host->chan_rx;
 305         struct device *dev = sh_mmcif_host_to_dev(host);
 306         dma_cookie_t cookie = -EINVAL;
 307         int ret;
 308
 309         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 310                          DMA_FROM_DEVICE);
 311         if (ret > 0) {
 312                 host->dma_active = true;
 313                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 314                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 315         }
 316
 317         if (desc) {
 318                 desc->callback = sh_mmcif_dma_complete;
 319                 desc->callback_param = host;
 320                 cookie = dmaengine_submit(desc);
 321                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
 322                 dma_async_issue_pending(chan);
 323         }
 324         dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n",
 325                 __func__, data->sg_len, ret, cookie);
 326
 327         if (!desc) {
 328                 /* DMA failed, fall back to PIO */
 329                 if (ret >= 0)
 330                         ret = -EIO;
 331                 host->chan_rx = NULL;
 332                 host->dma_active = false;
 333                 dma_release_channel(chan);
 334                 /* Free the Tx channel too */
 335                 chan = host->chan_tx;
 336                 if (chan) {
 337                         host->chan_tx = NULL;
 338                         dma_release_channel(chan);
 339                 }
 340                 dev_warn(dev,
 341                          "DMA failed: %d, falling back to PIO\n", ret);
 342                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 343         }
 344
 345         dev_dbg(dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
 346                 desc, cookie, data->sg_len);
 347 }
 348
 349 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
 350 {
 351         struct mmc_data *data = host->mrq->data;
 352         struct scatterlist *sg = data->sg;
 353         struct dma_async_tx_descriptor *desc = NULL;
 354         struct dma_chan *chan = host->chan_tx;
 355         struct device *dev = sh_mmcif_host_to_dev(host);
 356         dma_cookie_t cookie = -EINVAL;
 357         int ret;
 358
 359         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 360                          DMA_TO_DEVICE);
 361         if (ret > 0) {
 362                 host->dma_active = true;
 363                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 364                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 365         }
 366
 367         if (desc) {
 368                 desc->callback = sh_mmcif_dma_complete;
 369                 desc->callback_param = host;
 370                 cookie = dmaengine_submit(desc);
 371                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
 372                 dma_async_issue_pending(chan);
 373         }
 374         dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n",
 375                 __func__, data->sg_len, ret, cookie);
 376
 377         if (!desc) {
 378                 /* DMA failed, fall back to PIO */
 379                 if (ret >= 0)
 380                         ret = -EIO;
 381                 host->chan_tx = NULL;
 382                 host->dma_active = false;
 383                 dma_release_channel(chan);
 384                 /* Free the Rx channel too */
 385                 chan = host->chan_rx;
 386                 if (chan) {
 387                         host->chan_rx = NULL;
 388                         dma_release_channel(chan);
 389                 }
 390                 dev_warn(dev,
 391                          "DMA failed: %d, falling back to PIO\n", ret);
 392                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 393         }
 394
 395         dev_dbg(dev, "%s(): desc %p, cookie %d\n", __func__,
 396                 desc, cookie);
 397 }
 398
 399 static struct dma_chan *
 400 sh_mmcif_request_dma_one(struct sh_mmcif_host *host,
 401                          struct sh_mmcif_plat_data *pdata,
 402                          enum dma_transfer_direction direction)
 403 {
 404         struct dma_slave_config cfg = { 0, };
 405         struct dma_chan *chan;
 406         void *slave_data = NULL;
 407         struct resource *res;
 408         struct device *dev = sh_mmcif_host_to_dev(host);
 409         dma_cap_mask_t mask;
 410         int ret;
 411
 412         dma_cap_zero(mask);
 413         dma_cap_set(DMA_SLAVE, mask);
 414
 415         if (pdata)
 416                 slave_data = direction == DMA_MEM_TO_DEV ?
 417                         (void *)pdata->slave_id_tx :
 418                         (void *)pdata->slave_id_rx;
 419
 420         chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
 421                                 slave_data, dev,
 422                                 direction == DMA_MEM_TO_DEV ? "tx" : "rx");
 423
 424         dev_dbg(dev, "%s: %s: got channel %p\n", __func__,
 425                 direction == DMA_MEM_TO_DEV ? "TX" : "RX", chan);
 426
 427         if (!chan)
 428                 return NULL;
 429
 430         res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
 431
 432         cfg.direction = direction;
 433
 434         if (direction == DMA_DEV_TO_MEM) {
 435                 cfg.src_addr = res->start + MMCIF_CE_DATA;
 436                 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 437         } else {
 438                 cfg.dst_addr = res->start + MMCIF_CE_DATA;
 439                 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 440         }
 441
 442         ret = dmaengine_slave_config(chan, &cfg);
 443         if (ret < 0) {
 444                 dma_release_channel(chan);
 445                 return NULL;
 446         }
 447
 448         return chan;
 449 }
 450
 451 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
 452                                  struct sh_mmcif_plat_data *pdata)
 453 {
 454         struct device *dev = sh_mmcif_host_to_dev(host);
 455         host->dma_active = false;
 456
 457         if (pdata) {
 458                 if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0)
 459                         return;
 460         } else if (!dev->of_node) {
 461                 return;
 462         }
 463
 464         /* We can only either use DMA for both Tx and Rx or not use it at all */
 465         host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV);
 466         if (!host->chan_tx)
 467                 return;
 468
 469         host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM);
 470         if (!host->chan_rx) {
 471                 dma_release_channel(host->chan_tx);
 472                 host->chan_tx = NULL;
 473         }
 474 }
 475
 476 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
 477 {
 478         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 479         /* Descriptors are freed automatically */
 480         if (host->chan_tx) {
 481                 struct dma_chan *chan = host->chan_tx;
 482                 host->chan_tx = NULL;
 483                 dma_release_channel(chan);
 484         }
 485         if (host->chan_rx) {
 486                 struct dma_chan *chan = host->chan_rx;
 487                 host->chan_rx = NULL;
 488                 dma_release_channel(chan);
 489         }
 490
 491         host->dma_active = false;
 492 }
 493
 494 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
 495 {
 496         struct device *dev = sh_mmcif_host_to_dev(host);
 497         struct sh_mmcif_plat_data *p = dev->platform_data;
 498         bool sup_pclk = p ? p->sup_pclk : false;
 499         unsigned int current_clk = clk_get_rate(host->clk);
 500         unsigned int clkdiv;
 501
 502         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 503         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
 504
 505         if (!clk)
 506                 return;
 507
 508         if (host->clkdiv_map) {
 509                 unsigned int freq, best_freq, myclk, div, diff_min, diff;
 510                 int i;
 511
 512                 clkdiv = 0;
 513                 diff_min = ~0;
 514                 best_freq = 0;
 515                 for (i = 31; i >= 0; i--) {
 516                         if (!((1 << i) & host->clkdiv_map))
 517                                 continue;
 518
 519                         /*
 520                          * clk = parent_freq / div
 521                          * -> parent_freq = clk x div
 522                          */
 523
 524                         div = 1 << (i + 1);
 525                         freq = clk_round_rate(host->clk, clk * div);
 526                         myclk = freq / div;
 527                         diff = (myclk > clk) ? myclk - clk : clk - myclk;
 528
 529                         if (diff <= diff_min) {
 530                                 best_freq = freq;
 531                                 clkdiv = i;
 532                                 diff_min = diff;
 533                         }
 534                 }
 535
 536                 dev_dbg(dev, "clk %u/%u (%u, 0x%x)\n",
 537                         (best_freq / (1 << (clkdiv + 1))), clk,
 538                         best_freq, clkdiv);
 539
 540                 clk_set_rate(host->clk, best_freq);
 541                 clkdiv = clkdiv << 16;
 542         } else if (sup_pclk && clk == current_clk) {
 543                 clkdiv = CLK_SUP_PCLK;
 544         } else {
 545                 clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16;
 546         }
 547
 548         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv);
 549         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 550 }
 551
 552 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
 553 {
 554         u32 tmp;
 555
 556         tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
 557
 558         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
 559         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
 560         if (host->ccs_enable)
 561                 tmp |= SCCSTO_29;
 562         if (host->clk_ctrl2_enable)
 563                 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000);
 564         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
 565                 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29);
 566         /* byte swap on */
 567         sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 568 }
 569
 570 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
 571 {
 572         struct device *dev = sh_mmcif_host_to_dev(host);
 573         u32 state1, state2;
 574         int ret, timeout;
 575
 576         host->sd_error = false;
 577
 578         state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
 579         state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
 580         dev_dbg(dev, "ERR HOST_STS1 = %08x\n", state1);
 581         dev_dbg(dev, "ERR HOST_STS2 = %08x\n", state2);
 582
 583         if (state1 & STS1_CMDSEQ) {
 584                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
 585                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
 586                 for (timeout = 10000000; timeout; timeout--) {
 587                         if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
 588                               & STS1_CMDSEQ))
 589                                 break;
 590                         mdelay(1);
 591                 }
 592                 if (!timeout) {
 593                         dev_err(dev,
 594                                 "Forced end of command sequence timeout err\n");
 595                         return -EIO;
 596                 }
 597                 sh_mmcif_sync_reset(host);
 598                 dev_dbg(dev, "Forced end of command sequence\n");
 599                 return -EIO;
 600         }
 601
 602         if (state2 & STS2_CRC_ERR) {
 603                 dev_err(dev, " CRC error: state %u, wait %u\n",
 604                         host->state, host->wait_for);
 605                 ret = -EIO;
 606         } else if (state2 & STS2_TIMEOUT_ERR) {
 607                 dev_err(dev, " Timeout: state %u, wait %u\n",
 608                         host->state, host->wait_for);
 609                 ret = -ETIMEDOUT;
 610         } else {
 611                 dev_dbg(dev, " End/Index error: state %u, wait %u\n",
 612                         host->state, host->wait_for);
 613                 ret = -EIO;
 614         }
 615         return ret;
 616 }
 617
 618 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
 619 {
 620         struct mmc_data *data = host->mrq->data;
 621
 622         host->sg_blkidx += host->blocksize;
 623
 624         /* data->sg->length must be a multiple of host->blocksize? */
 625         BUG_ON(host->sg_blkidx > data->sg->length);
 626
 627         if (host->sg_blkidx == data->sg->length) {
 628                 host->sg_blkidx = 0;
 629                 if (++host->sg_idx < data->sg_len)
 630                         host->pio_ptr = sg_virt(++data->sg);
 631         } else {
 632                 host->pio_ptr = p;
 633         }
 634
 635         return host->sg_idx != data->sg_len;
 636 }
 637
 638 static void sh_mmcif_single_read(struct sh_mmcif_host *host,
 639                                  struct mmc_request *mrq)
 640 {
 641         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 642                            BLOCK_SIZE_MASK) + 3;
 643
 644         host->wait_for = MMCIF_WAIT_FOR_READ;
 645
 646         /* buf read enable */
 647         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 648 }
 649
 650 static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
 651 {
 652         struct device *dev = sh_mmcif_host_to_dev(host);
 653         struct mmc_data *data = host->mrq->data;
 654         u32 *p = sg_virt(data->sg);
 655         int i;
 656
 657         if (host->sd_error) {
 658                 data->error = sh_mmcif_error_manage(host);
 659                 dev_dbg(dev, "%s(): %d\n", __func__, data->error);
 660                 return false;
 661         }
 662
 663         for (i = 0; i < host->blocksize / 4; i++)
 664                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 665
 666         /* buffer read end */
 667         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
 668         host->wait_for = MMCIF_WAIT_FOR_READ_END;
 669
 670         return true;
 671 }
 672
 673 static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
 674                                 struct mmc_request *mrq)
 675 {
 676         struct mmc_data *data = mrq->data;
 677
 678         if (!data->sg_len || !data->sg->length)
 679                 return;
 680
 681         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 682                 BLOCK_SIZE_MASK;
 683
 684         host->wait_for = MMCIF_WAIT_FOR_MREAD;
 685         host->sg_idx = 0;
 686         host->sg_blkidx = 0;
 687         host->pio_ptr = sg_virt(data->sg);
 688
 689         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 690 }
 691
 692 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
 693 {
 694         struct device *dev = sh_mmcif_host_to_dev(host);
 695         struct mmc_data *data = host->mrq->data;
 696         u32 *p = host->pio_ptr;
 697         int i;
 698
 699         if (host->sd_error) {
 700                 data->error = sh_mmcif_error_manage(host);
 701                 dev_dbg(dev, "%s(): %d\n", __func__, data->error);
 702                 return false;
 703         }
 704
 705         BUG_ON(!data->sg->length);
 706
 707         for (i = 0; i < host->blocksize / 4; i++)
 708                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 709
 710         if (!sh_mmcif_next_block(host, p))
 711                 return false;
 712
 713         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 714
 715         return true;
 716 }
 717
 718 static void sh_mmcif_single_write(struct sh_mmcif_host *host,
 719                                         struct mmc_request *mrq)
 720 {
 721         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 722                            BLOCK_SIZE_MASK) + 3;
 723
 724         host->wait_for = MMCIF_WAIT_FOR_WRITE;
 725
 726         /* buf write enable */
 727         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 728 }
 729
 730 static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
 731 {
 732         struct device *dev = sh_mmcif_host_to_dev(host);
 733         struct mmc_data *data = host->mrq->data;
 734         u32 *p = sg_virt(data->sg);
 735         int i;
 736
 737         if (host->sd_error) {
 738                 data->error = sh_mmcif_error_manage(host);
 739                 dev_dbg(dev, "%s(): %d\n", __func__, data->error);
 740                 return false;
 741         }
 742
 743         for (i = 0; i < host->blocksize / 4; i++)
 744                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 745
 746         /* buffer write end */
 747         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
 748         host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
 749
 750         return true;
 751 }
 752
 753 static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
 754                                 struct mmc_request *mrq)
 755 {
 756         struct mmc_data *data = mrq->data;
 757
 758         if (!data->sg_len || !data->sg->length)
 759                 return;
 760
 761         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 762                 BLOCK_SIZE_MASK;
 763
 764         host->wait_for = MMCIF_WAIT_FOR_MWRITE;
 765         host->sg_idx = 0;
 766         host->sg_blkidx = 0;
 767         host->pio_ptr = sg_virt(data->sg);
 768
 769         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 770 }
 771
 772 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
 773 {
 774         struct device *dev = sh_mmcif_host_to_dev(host);
 775         struct mmc_data *data = host->mrq->data;
 776         u32 *p = host->pio_ptr;
 777         int i;
 778
 779         if (host->sd_error) {
 780                 data->error = sh_mmcif_error_manage(host);
 781                 dev_dbg(dev, "%s(): %d\n", __func__, data->error);
 782                 return false;
 783         }
 784
 785         BUG_ON(!data->sg->length);
 786
 787         for (i = 0; i < host->blocksize / 4; i++)
 788                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 789
 790         if (!sh_mmcif_next_block(host, p))
 791                 return false;
 792
 793         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 794
 795         return true;
 796 }
 797
 798 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
 799                                                 struct mmc_command *cmd)
 800 {
 801         if (cmd->flags & MMC_RSP_136) {
 802                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
 803                 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
 804                 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
 805                 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 806         } else
 807                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 808 }
 809
 810 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
 811                                                 struct mmc_command *cmd)
 812 {
 813         cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
 814 }
 815
 816 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
 817                             struct mmc_request *mrq)
 818 {
 819         struct device *dev = sh_mmcif_host_to_dev(host);
 820         struct mmc_data *data = mrq->data;
 821         struct mmc_command *cmd = mrq->cmd;
 822         u32 opc = cmd->opcode;
 823         u32 tmp = 0;
 824
 825         /* Response Type check */
 826         switch (mmc_resp_type(cmd)) {
 827         case MMC_RSP_NONE:
 828                 tmp |= CMD_SET_RTYP_NO;
 829                 break;
 830         case MMC_RSP_R1:
 831         case MMC_RSP_R1B:
 832         case MMC_RSP_R3:
 833                 tmp |= CMD_SET_RTYP_6B;
 834                 break;
 835         case MMC_RSP_R2:
 836                 tmp |= CMD_SET_RTYP_17B;
 837                 break;
 838         default:
 839                 dev_err(dev, "Unsupported response type.\n");
 840                 break;
 841         }
 842         switch (opc) {
 843         /* RBSY */
 844         case MMC_SLEEP_AWAKE:
 845         case MMC_SWITCH:
 846         case MMC_STOP_TRANSMISSION:
 847         case MMC_SET_WRITE_PROT:
 848         case MMC_CLR_WRITE_PROT:
 849         case MMC_ERASE:
 850                 tmp |= CMD_SET_RBSY;
 851                 break;
 852         }
 853         /* WDAT / DATW */
 854         if (data) {
 855                 tmp |= CMD_SET_WDAT;
 856                 switch (host->bus_width) {
 857                 case MMC_BUS_WIDTH_1:
 858                         tmp |= CMD_SET_DATW_1;
 859                         break;
 860                 case MMC_BUS_WIDTH_4:
 861                         tmp |= CMD_SET_DATW_4;
 862                         break;
 863                 case MMC_BUS_WIDTH_8:
 864                         tmp |= CMD_SET_DATW_8;
 865                         break;
 866                 default:
 867                         dev_err(dev, "Unsupported bus width.\n");
 868                         break;
 869                 }
 870                 switch (host->timing) {
 871                 case MMC_TIMING_MMC_DDR52:
 872                         /*
 873                          * MMC core will only set this timing, if the host
 874                          * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR
 875                          * capability. MMCIF implementations with this
 876                          * capability, e.g. sh73a0, will have to set it
 877                          * in their platform data.
 878                          */
 879                         tmp |= CMD_SET_DARS;
 880                         break;
 881                 }
 882         }
 883         /* DWEN */
 884         if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
 885                 tmp |= CMD_SET_DWEN;
 886         /* CMLTE/CMD12EN */
 887         if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
 888                 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
 889                 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
 890                                 data->blocks << 16);
 891         }
 892         /* RIDXC[1:0] check bits */
 893         if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
 894             opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 895                 tmp |= CMD_SET_RIDXC_BITS;
 896         /* RCRC7C[1:0] check bits */
 897         if (opc == MMC_SEND_OP_COND)
 898                 tmp |= CMD_SET_CRC7C_BITS;
 899         /* RCRC7C[1:0] internal CRC7 */
 900         if (opc == MMC_ALL_SEND_CID ||
 901                 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 902                 tmp |= CMD_SET_CRC7C_INTERNAL;
 903
 904         return (opc << 24) | tmp;
 905 }
 906
 907 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
 908                                struct mmc_request *mrq, u32 opc)
 909 {
 910         struct device *dev = sh_mmcif_host_to_dev(host);
 911
 912         switch (opc) {
 913         case MMC_READ_MULTIPLE_BLOCK:
 914                 sh_mmcif_multi_read(host, mrq);
 915                 return 0;
 916         case MMC_WRITE_MULTIPLE_BLOCK:
 917                 sh_mmcif_multi_write(host, mrq);
 918                 return 0;
 919         case MMC_WRITE_BLOCK:
 920                 sh_mmcif_single_write(host, mrq);
 921                 return 0;
 922         case MMC_READ_SINGLE_BLOCK:
 923         case MMC_SEND_EXT_CSD:
 924                 sh_mmcif_single_read(host, mrq);
 925                 return 0;
 926         default:
 927                 dev_err(dev, "Unsupported CMD%d\n", opc);
 928                 return -EINVAL;
 929         }
 930 }
 931
 932 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
 933                                struct mmc_request *mrq)
 934 {
 935         struct mmc_command *cmd = mrq->cmd;
 936         u32 opc = cmd->opcode;
 937         u32 mask;
 938         unsigned long flags;
 939
 940         switch (opc) {
 941         /* response busy check */
 942         case MMC_SLEEP_AWAKE:
 943         case MMC_SWITCH:
 944         case MMC_STOP_TRANSMISSION:
 945         case MMC_SET_WRITE_PROT:
 946         case MMC_CLR_WRITE_PROT:
 947         case MMC_ERASE:
 948                 mask = MASK_START_CMD | MASK_MRBSYE;
 949                 break;
 950         default:
 951                 mask = MASK_START_CMD | MASK_MCRSPE;
 952                 break;
 953         }
 954
 955         if (host->ccs_enable)
 956                 mask |= MASK_MCCSTO;
 957
 958         if (mrq->data) {
 959                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
 960                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
 961                                 mrq->data->blksz);
 962         }
 963         opc = sh_mmcif_set_cmd(host, mrq);
 964
 965         if (host->ccs_enable)
 966                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
 967         else
 968                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS);
 969         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
 970         /* set arg */
 971         sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
 972         /* set cmd */
 973         spin_lock_irqsave(&host->lock, flags);
 974         sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
 975
 976         host->wait_for = MMCIF_WAIT_FOR_CMD;
 977         schedule_delayed_work(&host->timeout_work, host->timeout);
 978         spin_unlock_irqrestore(&host->lock, flags);
 979 }
 980
 981 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
 982                               struct mmc_request *mrq)
 983 {
 984         struct device *dev = sh_mmcif_host_to_dev(host);
 985
 986         switch (mrq->cmd->opcode) {
 987         case MMC_READ_MULTIPLE_BLOCK:
 988                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
 989                 break;
 990         case MMC_WRITE_MULTIPLE_BLOCK:
 991                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
 992                 break;
 993         default:
 994                 dev_err(dev, "unsupported stop cmd\n");
 995                 mrq->stop->error = sh_mmcif_error_manage(host);
 996                 return;
 997         }
 998
 999         host->wait_for = MMCIF_WAIT_FOR_STOP;
1000 }
1001
1002 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
1003 {
1004         struct sh_mmcif_host *host = mmc_priv(mmc);
1005         struct device *dev = sh_mmcif_host_to_dev(host);
1006         unsigned long flags;
1007
1008         spin_lock_irqsave(&host->lock, flags);
1009         if (host->state != STATE_IDLE) {
1010                 dev_dbg(dev, "%s() rejected, state %u\n",
1011                         __func__, host->state);
1012                 spin_unlock_irqrestore(&host->lock, flags);
1013                 mrq->cmd->error = -EAGAIN;
1014                 mmc_request_done(mmc, mrq);
1015                 return;
1016         }
1017
1018         host->state = STATE_REQUEST;
1019         spin_unlock_irqrestore(&host->lock, flags);
1020
1021         switch (mrq->cmd->opcode) {
1022         /* MMCIF does not support SD/SDIO command */
1023         case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
1024         case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
1025                 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
1026                         break;
1027         case MMC_APP_CMD:
1028         case SD_IO_RW_DIRECT:
1029                 host->state = STATE_IDLE;
1030                 mrq->cmd->error = -ETIMEDOUT;
1031                 mmc_request_done(mmc, mrq);
1032                 return;
1033         default:
1034                 break;
1035         }
1036
1037         host->mrq = mrq;
1038
1039         sh_mmcif_start_cmd(host, mrq);
1040 }
1041
1042 static void sh_mmcif_clk_setup(struct sh_mmcif_host *host)
1043 {
1044         struct device *dev = sh_mmcif_host_to_dev(host);
1045
1046         if (host->mmc->f_max) {
1047                 unsigned int f_max, f_min = 0, f_min_old;
1048
1049                 f_max = host->mmc->f_max;
1050                 for (f_min_old = f_max; f_min_old > 2;) {
1051                         f_min = clk_round_rate(host->clk, f_min_old / 2);
1052                         if (f_min == f_min_old)
1053                                 break;
1054                         f_min_old = f_min;
1055                 }
1056
1057                 /*
1058                  * This driver assumes this SoC is R-Car Gen2 or later
1059                  */
1060                 host->clkdiv_map = 0x3ff;
1061
1062                 host->mmc->f_max = f_max / (1 << ffs(host->clkdiv_map));
1063                 host->mmc->f_min = f_min / (1 << fls(host->clkdiv_map));
1064         } else {
1065                 unsigned int clk = clk_get_rate(host->clk);
1066
1067                 host->mmc->f_max = clk / 2;
1068                 host->mmc->f_min = clk / 512;
1069         }
1070
1071         dev_dbg(dev, "clk max/min = %d/%d\n",
1072                 host->mmc->f_max, host->mmc->f_min);
1073 }
1074
1075 static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)
1076 {
1077         struct mmc_host *mmc = host->mmc;
1078
1079         if (!IS_ERR(mmc->supply.vmmc))
1080                 /* Errors ignored... */
1081                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1082                                       ios->power_mode ? ios->vdd : 0);
1083 }
1084
1085 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1086 {
1087         struct sh_mmcif_host *host = mmc_priv(mmc);
1088         struct device *dev = sh_mmcif_host_to_dev(host);
1089         unsigned long flags;
1090
1091         spin_lock_irqsave(&host->lock, flags);
1092         if (host->state != STATE_IDLE) {
1093                 dev_dbg(dev, "%s() rejected, state %u\n",
1094                         __func__, host->state);
1095                 spin_unlock_irqrestore(&host->lock, flags);
1096                 return;
1097         }
1098
1099         host->state = STATE_IOS;
1100         spin_unlock_irqrestore(&host->lock, flags);
1101
1102         if (ios->power_mode == MMC_POWER_UP) {
1103                 if (!host->card_present) {
1104                         /* See if we also get DMA */
1105                         sh_mmcif_request_dma(host, dev->platform_data);
1106                         host->card_present = true;
1107                 }
1108                 sh_mmcif_set_power(host, ios);
1109         } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
1110                 /* clock stop */
1111                 sh_mmcif_clock_control(host, 0);
1112                 if (ios->power_mode == MMC_POWER_OFF) {
1113                         if (host->card_present) {
1114                                 sh_mmcif_release_dma(host);
1115                                 host->card_present = false;
1116                         }
1117                 }
1118                 if (host->power) {
1119                         pm_runtime_put_sync(dev);
1120                         clk_disable_unprepare(host->clk);
1121                         host->power = false;
1122                         if (ios->power_mode == MMC_POWER_OFF)
1123                                 sh_mmcif_set_power(host, ios);
1124                 }
1125                 host->state = STATE_IDLE;
1126                 return;
1127         }
1128
1129         if (ios->clock) {
1130                 if (!host->power) {
1131                         clk_prepare_enable(host->clk);
1132
1133                         pm_runtime_get_sync(dev);
1134                         host->power = true;
1135                         sh_mmcif_sync_reset(host);
1136                 }
1137                 sh_mmcif_clock_control(host, ios->clock);
1138         }
1139
1140         host->timing = ios->timing;
1141         host->bus_width = ios->bus_width;
1142         host->state = STATE_IDLE;
1143 }
1144
1145 static int sh_mmcif_get_cd(struct mmc_host *mmc)
1146 {
1147         struct sh_mmcif_host *host = mmc_priv(mmc);
1148         struct device *dev = sh_mmcif_host_to_dev(host);
1149         struct sh_mmcif_plat_data *p = dev->platform_data;
1150         int ret = mmc_gpio_get_cd(mmc);
1151
1152         if (ret >= 0)
1153                 return ret;
1154
1155         if (!p || !p->get_cd)
1156                 return -ENOSYS;
1157         else
1158                 return p->get_cd(host->pd);
1159 }
1160
1161 static struct mmc_host_ops sh_mmcif_ops = {
1162         .request        = sh_mmcif_request,
1163         .set_ios        = sh_mmcif_set_ios,
1164         .get_cd         = sh_mmcif_get_cd,
1165 };
1166
1167 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1168 {
1169         struct mmc_command *cmd = host->mrq->cmd;
1170         struct mmc_data *data = host->mrq->data;
1171         struct device *dev = sh_mmcif_host_to_dev(host);
1172         long time;
1173
1174         if (host->sd_error) {
1175                 switch (cmd->opcode) {
1176                 case MMC_ALL_SEND_CID:
1177                 case MMC_SELECT_CARD:
1178                 case MMC_APP_CMD:
1179                         cmd->error = -ETIMEDOUT;
1180                         break;
1181                 default:
1182                         cmd->error = sh_mmcif_error_manage(host);
1183                         break;
1184                 }
1185                 dev_dbg(dev, "CMD%d error %d\n",
1186                         cmd->opcode, cmd->error);
1187                 host->sd_error = false;
1188                 return false;
1189         }
1190         if (!(cmd->flags & MMC_RSP_PRESENT)) {
1191                 cmd->error = 0;
1192                 return false;
1193         }
1194
1195         sh_mmcif_get_response(host, cmd);
1196
1197         if (!data)
1198                 return false;
1199
1200         /*
1201          * Completion can be signalled from DMA callback and error, so, have to
1202          * reset here, before setting .dma_active
1203          */
1204         init_completion(&host->dma_complete);
1205
1206         if (data->flags & MMC_DATA_READ) {
1207                 if (host->chan_rx)
1208                         sh_mmcif_start_dma_rx(host);
1209         } else {
1210                 if (host->chan_tx)
1211                         sh_mmcif_start_dma_tx(host);
1212         }
1213
1214         if (!host->dma_active) {
1215                 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1216                 return !data->error;
1217         }
1218
1219         /* Running in the IRQ thread, can sleep */
1220         time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1221                                                          host->timeout);
1222
1223         if (data->flags & MMC_DATA_READ)
1224                 dma_unmap_sg(host->chan_rx->device->dev,
1225                              data->sg, data->sg_len,
1226                              DMA_FROM_DEVICE);
1227         else
1228                 dma_unmap_sg(host->chan_tx->device->dev,
1229                              data->sg, data->sg_len,
1230                              DMA_TO_DEVICE);
1231
1232         if (host->sd_error) {
1233                 dev_err(host->mmc->parent,
1234                         "Error IRQ while waiting for DMA completion!\n");
1235                 /* Woken up by an error IRQ: abort DMA */
1236                 data->error = sh_mmcif_error_manage(host);
1237         } else if (!time) {
1238                 dev_err(host->mmc->parent, "DMA timeout!\n");
1239                 data->error = -ETIMEDOUT;
1240         } else if (time < 0) {
1241                 dev_err(host->mmc->parent,
1242                         "wait_for_completion_...() error %ld!\n", time);
1243                 data->error = time;
1244         }
1245         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1246                         BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1247         host->dma_active = false;
1248
1249         if (data->error) {
1250                 data->bytes_xfered = 0;
1251                 /* Abort DMA */
1252                 if (data->flags & MMC_DATA_READ)
1253                         dmaengine_terminate_all(host->chan_rx);
1254                 else
1255                         dmaengine_terminate_all(host->chan_tx);
1256         }
1257
1258         return false;
1259 }
1260
1261 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1262 {
1263         struct sh_mmcif_host *host = dev_id;
1264         struct mmc_request *mrq;
1265         struct device *dev = sh_mmcif_host_to_dev(host);
1266         bool wait = false;
1267         unsigned long flags;
1268         int wait_work;
1269
1270         spin_lock_irqsave(&host->lock, flags);
1271         wait_work = host->wait_for;
1272         spin_unlock_irqrestore(&host->lock, flags);
1273
1274         cancel_delayed_work_sync(&host->timeout_work);
1275
1276         mutex_lock(&host->thread_lock);
1277
1278         mrq = host->mrq;
1279         if (!mrq) {
1280                 dev_dbg(dev, "IRQ thread state %u, wait %u: NULL mrq!\n",
1281                         host->state, host->wait_for);
1282                 mutex_unlock(&host->thread_lock);
1283                 return IRQ_HANDLED;
1284         }
1285
1286         /*
1287          * All handlers return true, if processing continues, and false, if the
1288          * request has to be completed - successfully or not
1289          */
1290         switch (wait_work) {
1291         case MMCIF_WAIT_FOR_REQUEST:
1292                 /* We're too late, the timeout has already kicked in */
1293                 mutex_unlock(&host->thread_lock);
1294                 return IRQ_HANDLED;
1295         case MMCIF_WAIT_FOR_CMD:
1296                 /* Wait for data? */
1297                 wait = sh_mmcif_end_cmd(host);
1298                 break;
1299         case MMCIF_WAIT_FOR_MREAD:
1300                 /* Wait for more data? */
1301                 wait = sh_mmcif_mread_block(host);
1302                 break;
1303         case MMCIF_WAIT_FOR_READ:
1304                 /* Wait for data end? */
1305                 wait = sh_mmcif_read_block(host);
1306                 break;
1307         case MMCIF_WAIT_FOR_MWRITE:
1308                 /* Wait data to write? */
1309                 wait = sh_mmcif_mwrite_block(host);
1310                 break;
1311         case MMCIF_WAIT_FOR_WRITE:
1312                 /* Wait for data end? */
1313                 wait = sh_mmcif_write_block(host);
1314                 break;
1315         case MMCIF_WAIT_FOR_STOP:
1316                 if (host->sd_error) {
1317                         mrq->stop->error = sh_mmcif_error_manage(host);
1318                         dev_dbg(dev, "%s(): %d\n", __func__, mrq->stop->error);
1319                         break;
1320                 }
1321                 sh_mmcif_get_cmd12response(host, mrq->stop);
1322                 mrq->stop->error = 0;
1323                 break;
1324         case MMCIF_WAIT_FOR_READ_END:
1325         case MMCIF_WAIT_FOR_WRITE_END:
1326                 if (host->sd_error) {
1327                         mrq->data->error = sh_mmcif_error_manage(host);
1328                         dev_dbg(dev, "%s(): %d\n", __func__, mrq->data->error);
1329                 }
1330                 break;
1331         default:
1332                 BUG();
1333         }
1334
1335         if (wait) {
1336                 schedule_delayed_work(&host->timeout_work, host->timeout);
1337                 /* Wait for more data */
1338                 mutex_unlock(&host->thread_lock);
1339                 return IRQ_HANDLED;
1340         }
1341
1342         if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
1343                 struct mmc_data *data = mrq->data;
1344                 if (!mrq->cmd->error && data && !data->error)
1345                         data->bytes_xfered =
1346                                 data->blocks * data->blksz;
1347
1348                 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
1349                         sh_mmcif_stop_cmd(host, mrq);
1350                         if (!mrq->stop->error) {
1351                                 schedule_delayed_work(&host->timeout_work, host->timeout);
1352                                 mutex_unlock(&host->thread_lock);
1353                                 return IRQ_HANDLED;
1354                         }
1355                 }
1356         }
1357
1358         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1359         host->state = STATE_IDLE;
1360         host->mrq = NULL;
1361         mmc_request_done(host->mmc, mrq);
1362
1363         mutex_unlock(&host->thread_lock);
1364
1365         return IRQ_HANDLED;
1366 }
1367
1368 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1369 {
1370         struct sh_mmcif_host *host = dev_id;
1371         struct device *dev = sh_mmcif_host_to_dev(host);
1372         u32 state, mask;
1373
1374         state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1375         mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK);
1376         if (host->ccs_enable)
1377                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask));
1378         else
1379                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask));
1380         sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN);
1381
1382         if (state & ~MASK_CLEAN)
1383                 dev_dbg(dev, "IRQ state = 0x%08x incompletely cleared\n",
1384                         state);
1385
1386         if (state & INT_ERR_STS || state & ~INT_ALL) {
1387                 host->sd_error = true;
1388                 dev_dbg(dev, "int err state = 0x%08x\n", state);
1389         }
1390         if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1391                 if (!host->mrq)
1392                         dev_dbg(dev, "NULL IRQ state = 0x%08x\n", state);
1393                 if (!host->dma_active)
1394                         return IRQ_WAKE_THREAD;
1395                 else if (host->sd_error)
1396                         sh_mmcif_dma_complete(host);
1397         } else {
1398                 dev_dbg(dev, "Unexpected IRQ 0x%x\n", state);
1399         }
1400
1401         return IRQ_HANDLED;
1402 }
1403
1404 static void sh_mmcif_timeout_work(struct work_struct *work)
1405 {
1406         struct delayed_work *d = container_of(work, struct delayed_work, work);
1407         struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1408         struct mmc_request *mrq = host->mrq;
1409         struct device *dev = sh_mmcif_host_to_dev(host);
1410         unsigned long flags;
1411
1412         if (host->dying)
1413                 /* Don't run after mmc_remove_host() */
1414                 return;
1415
1416         spin_lock_irqsave(&host->lock, flags);
1417         if (host->state == STATE_IDLE) {
1418                 spin_unlock_irqrestore(&host->lock, flags);
1419                 return;
1420         }
1421
1422         dev_err(dev, "Timeout waiting for %u on CMD%u\n",
1423                 host->wait_for, mrq->cmd->opcode);
1424
1425         host->state = STATE_TIMEOUT;
1426         spin_unlock_irqrestore(&host->lock, flags);
1427
1428         /*
1429          * Handle races with cancel_delayed_work(), unless
1430          * cancel_delayed_work_sync() is used
1431          */
1432         switch (host->wait_for) {
1433         case MMCIF_WAIT_FOR_CMD:
1434                 mrq->cmd->error = sh_mmcif_error_manage(host);
1435                 break;
1436         case MMCIF_WAIT_FOR_STOP:
1437                 mrq->stop->error = sh_mmcif_error_manage(host);
1438                 break;
1439         case MMCIF_WAIT_FOR_MREAD:
1440         case MMCIF_WAIT_FOR_MWRITE:
1441         case MMCIF_WAIT_FOR_READ:
1442         case MMCIF_WAIT_FOR_WRITE:
1443         case MMCIF_WAIT_FOR_READ_END:
1444         case MMCIF_WAIT_FOR_WRITE_END:
1445                 mrq->data->error = sh_mmcif_error_manage(host);
1446                 break;
1447         default:
1448                 BUG();
1449         }
1450
1451         host->state = STATE_IDLE;
1452         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1453         host->mrq = NULL;
1454         mmc_request_done(host->mmc, mrq);
1455 }
1456
1457 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1458 {
1459         struct device *dev = sh_mmcif_host_to_dev(host);
1460         struct sh_mmcif_plat_data *pd = dev->platform_data;
1461         struct mmc_host *mmc = host->mmc;
1462
1463         mmc_regulator_get_supply(mmc);
1464
1465         if (!pd)
1466                 return;
1467
1468         if (!mmc->ocr_avail)
1469                 mmc->ocr_avail = pd->ocr;
1470         else if (pd->ocr)
1471                 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1472 }
1473
1474 static int sh_mmcif_probe(struct platform_device *pdev)
1475 {
1476         int ret = 0, irq[2];
1477         struct mmc_host *mmc;
1478         struct sh_mmcif_host *host;
1479         struct device *dev = &pdev->dev;
1480         struct sh_mmcif_plat_data *pd = dev->platform_data;
1481         struct resource *res;
1482         void __iomem *reg;
1483         const char *name;
1484
1485         irq[0] = platform_get_irq(pdev, 0);
1486         irq[1] = platform_get_irq(pdev, 1);
1487         if (irq[0] < 0) {
1488                 dev_err(dev, "Get irq error\n");
1489                 return -ENXIO;
1490         }
1491
1492         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1493         reg = devm_ioremap_resource(dev, res);
1494         if (IS_ERR(reg))
1495                 return PTR_ERR(reg);
1496
1497         mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev);
1498         if (!mmc)
1499                 return -ENOMEM;
1500
1501         ret = mmc_of_parse(mmc);
1502         if (ret < 0)
1503                 goto err_host;
1504
1505         host            = mmc_priv(mmc);
1506         host->mmc       = mmc;
1507         host->addr      = reg;
1508         host->timeout   = msecs_to_jiffies(10000);
1509         host->ccs_enable = !pd || !pd->ccs_unsupported;
1510         host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present;
1511
1512         host->pd = pdev;
1513
1514         spin_lock_init(&host->lock);
1515
1516         mmc->ops = &sh_mmcif_ops;
1517         sh_mmcif_init_ocr(host);
1518
1519         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY;
1520         if (pd && pd->caps)
1521                 mmc->caps |= pd->caps;
1522         mmc->max_segs = 32;
1523         mmc->max_blk_size = 512;
1524         mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1525         mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1526         mmc->max_seg_size = mmc->max_req_size;
1527
1528         platform_set_drvdata(pdev, host);
1529
1530         pm_runtime_enable(dev);
1531         host->power = false;
1532
1533         host->clk = devm_clk_get(dev, NULL);
1534         if (IS_ERR(host->clk)) {
1535                 ret = PTR_ERR(host->clk);
1536                 dev_err(dev, "cannot get clock: %d\n", ret);
1537                 goto err_pm;
1538         }
1539
1540         ret = clk_prepare_enable(host->clk);
1541         if (ret < 0)
1542                 goto err_pm;
1543
1544         sh_mmcif_clk_setup(host);
1545
1546         ret = pm_runtime_resume(dev);
1547         if (ret < 0)
1548                 goto err_clk;
1549
1550         INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work);
1551
1552         sh_mmcif_sync_reset(host);
1553         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1554
1555         name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error";
1556         ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr,
1557                                         sh_mmcif_irqt, 0, name, host);
1558         if (ret) {
1559                 dev_err(dev, "request_irq error (%s)\n", name);
1560                 goto err_clk;
1561         }
1562         if (irq[1] >= 0) {
1563                 ret = devm_request_threaded_irq(dev, irq[1],
1564                                                 sh_mmcif_intr, sh_mmcif_irqt,
1565                                                 0, "sh_mmc:int", host);
1566                 if (ret) {
1567                         dev_err(dev, "request_irq error (sh_mmc:int)\n");
1568                         goto err_clk;
1569                 }
1570         }
1571
1572         if (pd && pd->use_cd_gpio) {
1573                 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0);
1574                 if (ret < 0)
1575                         goto err_clk;
1576         }
1577
1578         mutex_init(&host->thread_lock);
1579
1580         ret = mmc_add_host(mmc);
1581         if (ret < 0)
1582                 goto err_clk;
1583
1584         dev_pm_qos_expose_latency_limit(dev, 100);
1585
1586         dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n",
1587                  sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff,
1588                  clk_get_rate(host->clk) / 1000000UL);
1589
1590         clk_disable_unprepare(host->clk);
1591         return ret;
1592
1593 err_clk:
1594         clk_disable_unprepare(host->clk);
1595 err_pm:
1596         pm_runtime_disable(dev);
1597 err_host:
1598         mmc_free_host(mmc);
1599         return ret;
1600 }
1601
1602 static int sh_mmcif_remove(struct platform_device *pdev)
1603 {
1604         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1605
1606         host->dying = true;
1607         clk_prepare_enable(host->clk);
1608         pm_runtime_get_sync(&pdev->dev);
1609
1610         dev_pm_qos_hide_latency_limit(&pdev->dev);
1611
1612         mmc_remove_host(host->mmc);
1613         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1614
1615         /*
1616          * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1617          * mmc_remove_host() call above. But swapping order doesn't help either
1618          * (a query on the linux-mmc mailing list didn't bring any replies).
1619          */
1620         cancel_delayed_work_sync(&host->timeout_work);
1621
1622         clk_disable_unprepare(host->clk);
1623         mmc_free_host(host->mmc);
1624         pm_runtime_put_sync(&pdev->dev);
1625         pm_runtime_disable(&pdev->dev);
1626
1627         return 0;
1628 }
1629
1630 #ifdef CONFIG_PM_SLEEP
1631 static int sh_mmcif_suspend(struct device *dev)
1632 {
1633         struct sh_mmcif_host *host = dev_get_drvdata(dev);
1634
1635         pm_runtime_get_sync(dev);
1636         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1637         pm_runtime_put(dev);
1638
1639         return 0;
1640 }
1641
1642 static int sh_mmcif_resume(struct device *dev)
1643 {
1644         return 0;
1645 }
1646 #endif
1647
1648 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1649         SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume)
1650 };
1651
1652 static struct platform_driver sh_mmcif_driver = {
1653         .probe          = sh_mmcif_probe,
1654         .remove         = sh_mmcif_remove,
1655         .driver         = {
1656                 .name   = DRIVER_NAME,
1657                 .pm     = &sh_mmcif_dev_pm_ops,
1658                 .of_match_table = sh_mmcif_of_match,
1659         },
1660 };
1661
1662 module_platform_driver(sh_mmcif_driver);
1663
1664 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1665 MODULE_LICENSE("GPL");
1666 MODULE_ALIAS("platform:" DRIVER_NAME);
1667 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");