kernel/drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/slot-gpio.h>
  33
  34 #include "sdhci.h"
  35
  36 #define DRIVER_NAME "sdhci"
  37
  38 #define DBG(f, x...) \
  39         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  40
  41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  42         defined(CONFIG_MMC_SDHCI_MODULE))
  43 #define SDHCI_USE_LEDS_CLASS
  44 #endif
  45
  46 #define MAX_TUNING_LOOP 40
  47
  48 static unsigned int debug_quirks = 0;
  49 static unsigned int debug_quirks2;
  50
  51 static void sdhci_finish_data(struct sdhci_host *);
  52
  53 static void sdhci_finish_command(struct sdhci_host *);
  54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  55 static void sdhci_tuning_timer(unsigned long data);
  56 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  57 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
  58                                         struct mmc_data *data,
  59                                         struct sdhci_host_next *next);
  60 static int sdhci_do_get_cd(struct sdhci_host *host);
  61
  62 #ifdef CONFIG_PM
  63 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  64 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  65 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  66 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  67 #else
  68 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  69 {
  70         return 0;
  71 }
  72 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  73 {
  74         return 0;
  75 }
  76 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  77 {
  78 }
  79 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  80 {
  81 }
  82 #endif
  83
  84 static void sdhci_dumpregs(struct sdhci_host *host)
  85 {
  86         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  87                 mmc_hostname(host->mmc));
  88
  89         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  90                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  91                 sdhci_readw(host, SDHCI_HOST_VERSION));
  92         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  93                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  94                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  95         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  96                 sdhci_readl(host, SDHCI_ARGUMENT),
  97                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  98         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  99                 sdhci_readl(host, SDHCI_PRESENT_STATE),
 100                 sdhci_readb(host, SDHCI_HOST_CONTROL));
 101         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 102                 sdhci_readb(host, SDHCI_POWER_CONTROL),
 103                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 104         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 105                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 106                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 107         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 108                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 109                 sdhci_readl(host, SDHCI_INT_STATUS));
 110         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 111                 sdhci_readl(host, SDHCI_INT_ENABLE),
 112                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 113         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 114                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 115                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 116         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 117                 sdhci_readl(host, SDHCI_CAPABILITIES),
 118                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 119         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 120                 sdhci_readw(host, SDHCI_COMMAND),
 121                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 122         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 123                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 124
 125         if (host->flags & SDHCI_USE_ADMA) {
 126                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 127                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
 128                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 129                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
 130                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 131                 else
 132                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 133                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 134                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 135         }
 136
 137         pr_debug(DRIVER_NAME ": ===========================================\n");
 138 }
 139
 140 /*****************************************************************************\
 141  *                                                                           *
 142  * Low level functions                                                       *
 143  *                                                                           *
 144 \*****************************************************************************/
 145
 146 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 147 {
 148         u32 present;
 149
 150         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 151             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 152                 return;
 153
 154         if (enable) {
 155                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 156                                       SDHCI_CARD_PRESENT;
 157
 158                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 159                                        SDHCI_INT_CARD_INSERT;
 160         } else {
 161                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 162         }
 163
 164         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 165         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 166 }
 167
 168 static void sdhci_enable_card_detection(struct sdhci_host *host)
 169 {
 170         sdhci_set_card_detection(host, true);
 171 }
 172
 173 static void sdhci_disable_card_detection(struct sdhci_host *host)
 174 {
 175         sdhci_set_card_detection(host, false);
 176 }
 177
 178 void sdhci_reset(struct sdhci_host *host, u8 mask)
 179 {
 180         unsigned long timeout;
 181
 182         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 183
 184         if (mask & SDHCI_RESET_ALL) {
 185                 host->clock = 0;
 186                 /* Reset-all turns off SD Bus Power */
 187                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 188                         sdhci_runtime_pm_bus_off(host);
 189         }
 190
 191         /* Wait max 100 ms */
 192         timeout = 100;
 193
 194         /* hw clears the bit when it's done */
 195         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 196                 if (timeout == 0) {
 197                         pr_err("%s: Reset 0x%x never completed.\n",
 198                                 mmc_hostname(host->mmc), (int)mask);
 199                         sdhci_dumpregs(host);
 200                         return;
 201                 }
 202                 timeout--;
 203                 mdelay(1);
 204         }
 205 }
 206 EXPORT_SYMBOL_GPL(sdhci_reset);
 207
 208 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 209 {
 210         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 211                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 212                         SDHCI_CARD_PRESENT))
 213                         return;
 214         }
 215
 216         host->ops->reset(host, mask);
 217
 218         if (mask & SDHCI_RESET_ALL) {
 219                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 220                         if (host->ops->enable_dma)
 221                                 host->ops->enable_dma(host);
 222                 }
 223
 224                 /* Resetting the controller clears many */
 225                 host->preset_enabled = false;
 226         }
 227 }
 228
 229 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 230
 231 static void sdhci_init(struct sdhci_host *host, int soft)
 232 {
 233         if (soft)
 234                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 235         else
 236                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 237
 238         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 239                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 240                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 241                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 242                     SDHCI_INT_RESPONSE;
 243
 244         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 245         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 246
 247         if (soft) {
 248                 /* force clock reconfiguration */
 249                 host->clock = 0;
 250                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 251         }
 252 }
 253
 254 static void sdhci_reinit(struct sdhci_host *host)
 255 {
 256         sdhci_init(host, 0);
 257         /*
 258          * Retuning stuffs are affected by different cards inserted and only
 259          * applicable to UHS-I cards. So reset these fields to their initial
 260          * value when card is removed.
 261          */
 262         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
 263                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
 264
 265                 del_timer_sync(&host->tuning_timer);
 266                 host->flags &= ~SDHCI_NEEDS_RETUNING;
 267         }
 268         sdhci_enable_card_detection(host);
 269 }
 270
 271 static void sdhci_activate_led(struct sdhci_host *host)
 272 {
 273         u8 ctrl;
 274
 275         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 276         ctrl |= SDHCI_CTRL_LED;
 277         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 278 }
 279
 280 static void sdhci_deactivate_led(struct sdhci_host *host)
 281 {
 282         u8 ctrl;
 283
 284         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 285         ctrl &= ~SDHCI_CTRL_LED;
 286         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 287 }
 288
 289 #ifdef SDHCI_USE_LEDS_CLASS
 290 static void sdhci_led_control(struct led_classdev *led,
 291         enum led_brightness brightness)
 292 {
 293         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 294         unsigned long flags;
 295
 296         spin_lock_irqsave(&host->lock, flags);
 297
 298         if (host->runtime_suspended)
 299                 goto out;
 300
 301         if (brightness == LED_OFF)
 302                 sdhci_deactivate_led(host);
 303         else
 304                 sdhci_activate_led(host);
 305 out:
 306         spin_unlock_irqrestore(&host->lock, flags);
 307 }
 308 #endif
 309
 310 /*****************************************************************************\
 311  *                                                                           *
 312  * Core functions                                                            *
 313  *                                                                           *
 314 \*****************************************************************************/
 315
 316 static void sdhci_read_block_pio(struct sdhci_host *host)
 317 {
 318         unsigned long flags;
 319         size_t blksize, len, chunk;
 320         u32 uninitialized_var(scratch);
 321         u8 *buf;
 322
 323         DBG("PIO reading\n");
 324
 325         blksize = host->data->blksz;
 326         chunk = 0;
 327
 328         local_irq_save(flags);
 329
 330         while (blksize) {
 331                 if (!sg_miter_next(&host->sg_miter))
 332                         BUG();
 333
 334                 len = min(host->sg_miter.length, blksize);
 335
 336                 blksize -= len;
 337                 host->sg_miter.consumed = len;
 338
 339                 buf = host->sg_miter.addr;
 340
 341                 while (len) {
 342                         if (chunk == 0) {
 343                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 344                                 chunk = 4;
 345                         }
 346
 347                         *buf = scratch & 0xFF;
 348
 349                         buf++;
 350                         scratch >>= 8;
 351                         chunk--;
 352                         len--;
 353                 }
 354         }
 355
 356         sg_miter_stop(&host->sg_miter);
 357
 358         local_irq_restore(flags);
 359 }
 360
 361 static void sdhci_write_block_pio(struct sdhci_host *host)
 362 {
 363         unsigned long flags;
 364         size_t blksize, len, chunk;
 365         u32 scratch;
 366         u8 *buf;
 367
 368         DBG("PIO writing\n");
 369
 370         blksize = host->data->blksz;
 371         chunk = 0;
 372         scratch = 0;
 373
 374         local_irq_save(flags);
 375
 376         while (blksize) {
 377                 if (!sg_miter_next(&host->sg_miter))
 378                         BUG();
 379
 380                 len = min(host->sg_miter.length, blksize);
 381
 382                 blksize -= len;
 383                 host->sg_miter.consumed = len;
 384
 385                 buf = host->sg_miter.addr;
 386
 387                 while (len) {
 388                         scratch |= (u32)*buf << (chunk * 8);
 389
 390                         buf++;
 391                         chunk++;
 392                         len--;
 393
 394                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 395                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 396                                 chunk = 0;
 397                                 scratch = 0;
 398                         }
 399                 }
 400         }
 401
 402         sg_miter_stop(&host->sg_miter);
 403
 404         local_irq_restore(flags);
 405 }
 406
 407 static void sdhci_transfer_pio(struct sdhci_host *host)
 408 {
 409         u32 mask;
 410
 411         BUG_ON(!host->data);
 412
 413         if (host->blocks == 0)
 414                 return;
 415
 416         if (host->data->flags & MMC_DATA_READ)
 417                 mask = SDHCI_DATA_AVAILABLE;
 418         else
 419                 mask = SDHCI_SPACE_AVAILABLE;
 420
 421         /*
 422          * Some controllers (JMicron JMB38x) mess up the buffer bits
 423          * for transfers < 4 bytes. As long as it is just one block,
 424          * we can ignore the bits.
 425          */
 426         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 427                 (host->data->blocks == 1))
 428                 mask = ~0;
 429
 430         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 431                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 432                         udelay(100);
 433
 434                 if (host->data->flags & MMC_DATA_READ)
 435                         sdhci_read_block_pio(host);
 436                 else
 437                         sdhci_write_block_pio(host);
 438
 439                 host->blocks--;
 440                 if (host->blocks == 0)
 441                         break;
 442         }
 443
 444         DBG("PIO transfer complete.\n");
 445 }
 446
 447 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 448 {
 449         local_irq_save(*flags);
 450         return kmap_atomic(sg_page(sg)) + sg->offset;
 451 }
 452
 453 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 454 {
 455         kunmap_atomic(buffer);
 456         local_irq_restore(*flags);
 457 }
 458
 459 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
 460                                   dma_addr_t addr, int len, unsigned cmd)
 461 {
 462         struct sdhci_adma2_64_desc *dma_desc = desc;
 463
 464         /* 32-bit and 64-bit descriptors have these members in same position */
 465         dma_desc->cmd = cpu_to_le16(cmd);
 466         dma_desc->len = cpu_to_le16(len);
 467         dma_desc->addr_lo = cpu_to_le32((u32)addr);
 468
 469         if (host->flags & SDHCI_USE_64_BIT_DMA)
 470                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
 471 }
 472
 473 static void sdhci_adma_mark_end(void *desc)
 474 {
 475         struct sdhci_adma2_64_desc *dma_desc = desc;
 476
 477         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 478         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 479 }
 480
 481 static int sdhci_adma_table_pre(struct sdhci_host *host,
 482         struct mmc_data *data)
 483 {
 484         int direction;
 485
 486         void *desc;
 487         void *align;
 488         dma_addr_t addr;
 489         dma_addr_t align_addr;
 490         int len, offset;
 491
 492         struct scatterlist *sg;
 493         int i;
 494         char *buffer;
 495         unsigned long flags;
 496
 497         /*
 498          * The spec does not specify endianness of descriptor table.
 499          * We currently guess that it is LE.
 500          */
 501
 502         if (data->flags & MMC_DATA_READ)
 503                 direction = DMA_FROM_DEVICE;
 504         else
 505                 direction = DMA_TO_DEVICE;
 506
 507         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 508                 host->align_buffer, host->align_buffer_sz, direction);
 509         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 510                 goto fail;
 511         BUG_ON(host->align_addr & host->align_mask);
 512
 513         host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
 514         if (host->sg_count < 0)
 515                 goto unmap_align;
 516
 517         desc = host->adma_table;
 518         align = host->align_buffer;
 519
 520         align_addr = host->align_addr;
 521
 522         for_each_sg(data->sg, sg, host->sg_count, i) {
 523                 addr = sg_dma_address(sg);
 524                 len = sg_dma_len(sg);
 525
 526                 /*
 527                  * The SDHCI specification states that ADMA
 528                  * addresses must be 32-bit aligned. If they
 529                  * aren't, then we use a bounce buffer for
 530                  * the (up to three) bytes that screw up the
 531                  * alignment.
 532                  */
 533                 offset = (host->align_sz - (addr & host->align_mask)) &
 534                          host->align_mask;
 535                 if (offset) {
 536                         if (data->flags & MMC_DATA_WRITE) {
 537                                 buffer = sdhci_kmap_atomic(sg, &flags);
 538                                 memcpy(align, buffer, offset);
 539                                 sdhci_kunmap_atomic(buffer, &flags);
 540                         }
 541
 542                         /* tran, valid */
 543                         sdhci_adma_write_desc(host, desc, align_addr, offset,
 544                                               ADMA2_TRAN_VALID);
 545
 546                         BUG_ON(offset > 65536);
 547
 548                         align += host->align_sz;
 549                         align_addr += host->align_sz;
 550
 551                         desc += host->desc_sz;
 552
 553                         addr += offset;
 554                         len -= offset;
 555                 }
 556
 557                 BUG_ON(len > 65536);
 558
 559                 /* tran, valid */
 560                 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
 561                 desc += host->desc_sz;
 562
 563                 /*
 564                  * If this triggers then we have a calculation bug
 565                  * somewhere. :/
 566                  */
 567                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 568         }
 569
 570         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 571                 /*
 572                 * Mark the last descriptor as the terminating descriptor
 573                 */
 574                 if (desc != host->adma_table) {
 575                         desc -= host->desc_sz;
 576                         sdhci_adma_mark_end(desc);
 577                 }
 578         } else {
 579                 /*
 580                 * Add a terminating entry.
 581                 */
 582
 583                 /* nop, end, valid */
 584                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
 585         }
 586
 587         /*
 588          * Resync align buffer as we might have changed it.
 589          */
 590         if (data->flags & MMC_DATA_WRITE) {
 591                 dma_sync_single_for_device(mmc_dev(host->mmc),
 592                         host->align_addr, host->align_buffer_sz, direction);
 593         }
 594
 595         return 0;
 596
 597 unmap_align:
 598         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 599                 host->align_buffer_sz, direction);
 600 fail:
 601         return -EINVAL;
 602 }
 603
 604 static void sdhci_adma_table_post(struct sdhci_host *host,
 605         struct mmc_data *data)
 606 {
 607         int direction;
 608
 609         struct scatterlist *sg;
 610         int i, size;
 611         void *align;
 612         char *buffer;
 613         unsigned long flags;
 614         bool has_unaligned;
 615
 616         if (data->flags & MMC_DATA_READ)
 617                 direction = DMA_FROM_DEVICE;
 618         else
 619                 direction = DMA_TO_DEVICE;
 620
 621         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 622                 host->align_buffer_sz, direction);
 623
 624         /* Do a quick scan of the SG list for any unaligned mappings */
 625         has_unaligned = false;
 626         for_each_sg(data->sg, sg, host->sg_count, i)
 627                 if (sg_dma_address(sg) & host->align_mask) {
 628                         has_unaligned = true;
 629                         break;
 630                 }
 631
 632         if (has_unaligned && data->flags & MMC_DATA_READ) {
 633                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 634                         data->sg_len, direction);
 635
 636                 align = host->align_buffer;
 637
 638                 for_each_sg(data->sg, sg, host->sg_count, i) {
 639                         if (sg_dma_address(sg) & host->align_mask) {
 640                                 size = host->align_sz -
 641                                        (sg_dma_address(sg) & host->align_mask);
 642
 643                                 buffer = sdhci_kmap_atomic(sg, &flags);
 644                                 memcpy(buffer, align, size);
 645                                 sdhci_kunmap_atomic(buffer, &flags);
 646
 647                                 align += host->align_sz;
 648                         }
 649                 }
 650         }
 651
 652         if (!data->host_cookie)
 653                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 654                         data->sg_len, direction);
 655 }
 656
 657 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 658 {
 659         u8 count;
 660         struct mmc_data *data = cmd->data;
 661         unsigned target_timeout, current_timeout;
 662
 663         /*
 664          * If the host controller provides us with an incorrect timeout
 665          * value, just skip the check and use 0xE.  The hardware may take
 666          * longer to time out, but that's much better than having a too-short
 667          * timeout value.
 668          */
 669         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 670                 return 0xE;
 671
 672         /* Unspecified timeout, assume max */
 673         if (!data && !cmd->busy_timeout)
 674                 return 0xE;
 675
 676         /* timeout in us */
 677         if (!data)
 678                 target_timeout = cmd->busy_timeout * 1000;
 679         else {
 680                 target_timeout = data->timeout_ns / 1000;
 681                 if (host->clock)
 682                         target_timeout += data->timeout_clks / host->clock;
 683         }
 684
 685         /*
 686          * Figure out needed cycles.
 687          * We do this in steps in order to fit inside a 32 bit int.
 688          * The first step is the minimum timeout, which will have a
 689          * minimum resolution of 6 bits:
 690          * (1) 2^13*1000 > 2^22,
 691          * (2) host->timeout_clk < 2^16
 692          *     =>
 693          *     (1) / (2) > 2^6
 694          */
 695         count = 0;
 696         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 697         while (current_timeout < target_timeout) {
 698                 count++;
 699                 current_timeout <<= 1;
 700                 if (count >= 0xF)
 701                         break;
 702         }
 703
 704         if (count >= 0xF) {
 705                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 706                     mmc_hostname(host->mmc), count, cmd->opcode);
 707                 count = 0xE;
 708         }
 709
 710         return count;
 711 }
 712
 713 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 714 {
 715         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 716         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 717
 718         if (host->flags & SDHCI_REQ_USE_DMA)
 719                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 720         else
 721                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 722
 723         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 724         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 725 }
 726
 727 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 728 {
 729         u8 count;
 730
 731         if (host->ops->set_timeout) {
 732                 host->ops->set_timeout(host, cmd);
 733         } else {
 734                 count = sdhci_calc_timeout(host, cmd);
 735                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 736         }
 737 }
 738
 739 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 740 {
 741         u8 ctrl;
 742         struct mmc_data *data = cmd->data;
 743         int ret;
 744
 745         WARN_ON(host->data);
 746
 747         if (data || (cmd->flags & MMC_RSP_BUSY))
 748                 sdhci_set_timeout(host, cmd);
 749
 750         if (!data)
 751                 return;
 752
 753         /* Sanity checks */
 754         BUG_ON(data->blksz * data->blocks > 524288);
 755         BUG_ON(data->blksz > host->mmc->max_blk_size);
 756         BUG_ON(data->blocks > 65535);
 757
 758         host->data = data;
 759         host->data_early = 0;
 760         host->data->bytes_xfered = 0;
 761
 762         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 763                 host->flags |= SDHCI_REQ_USE_DMA;
 764
 765         /*
 766          * FIXME: This doesn't account for merging when mapping the
 767          * scatterlist.
 768          */
 769         if (host->flags & SDHCI_REQ_USE_DMA) {
 770                 int broken, i;
 771                 struct scatterlist *sg;
 772
 773                 broken = 0;
 774                 if (host->flags & SDHCI_USE_ADMA) {
 775                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 776                                 broken = 1;
 777                 } else {
 778                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 779                                 broken = 1;
 780                 }
 781
 782                 if (unlikely(broken)) {
 783                         for_each_sg(data->sg, sg, data->sg_len, i) {
 784                                 if (sg->length & 0x3) {
 785                                         DBG("Reverting to PIO because of "
 786                                                 "transfer size (%d)\n",
 787                                                 sg->length);
 788                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 789                                         break;
 790                                 }
 791                         }
 792                 }
 793         }
 794
 795         /*
 796          * The assumption here being that alignment is the same after
 797          * translation to device address space.
 798          */
 799         if (host->flags & SDHCI_REQ_USE_DMA) {
 800                 int broken, i;
 801                 struct scatterlist *sg;
 802
 803                 broken = 0;
 804                 if (host->flags & SDHCI_USE_ADMA) {
 805                         /*
 806                          * As we use 3 byte chunks to work around
 807                          * alignment problems, we need to check this
 808                          * quirk.
 809                          */
 810                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 811                                 broken = 1;
 812                 } else {
 813                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 814                                 broken = 1;
 815                 }
 816
 817                 if (unlikely(broken)) {
 818                         for_each_sg(data->sg, sg, data->sg_len, i) {
 819                                 if (sg->offset & 0x3) {
 820                                         DBG("Reverting to PIO because of "
 821                                                 "bad alignment\n");
 822                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 823                                         break;
 824                                 }
 825                         }
 826                 }
 827         }
 828
 829         if (host->flags & SDHCI_REQ_USE_DMA) {
 830                 if (host->flags & SDHCI_USE_ADMA) {
 831                         ret = sdhci_adma_table_pre(host, data);
 832                         if (ret) {
 833                                 /*
 834                                  * This only happens when someone fed
 835                                  * us an invalid request.
 836                                  */
 837                                 WARN_ON(1);
 838                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 839                         } else {
 840                                 sdhci_writel(host, host->adma_addr,
 841                                         SDHCI_ADMA_ADDRESS);
 842                                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 843                                         sdhci_writel(host,
 844                                                      (u64)host->adma_addr >> 32,
 845                                                      SDHCI_ADMA_ADDRESS_HI);
 846                         }
 847                 } else {
 848                         int sg_cnt;
 849
 850                         sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
 851                         if (sg_cnt <= 0) {
 852                                 /*
 853                                  * This only happens when someone fed
 854                                  * us an invalid request.
 855                                  */
 856                                 WARN_ON(1);
 857                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 858                         } else {
 859                                 WARN_ON(sg_cnt != 1);
 860                                 sdhci_writel(host, sg_dma_address(data->sg),
 861                                         SDHCI_DMA_ADDRESS);
 862                         }
 863                 }
 864         }
 865
 866         /*
 867          * Always adjust the DMA selection as some controllers
 868          * (e.g. JMicron) can't do PIO properly when the selection
 869          * is ADMA.
 870          */
 871         if (host->version >= SDHCI_SPEC_200) {
 872                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 873                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 874                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 875                         (host->flags & SDHCI_USE_ADMA)) {
 876                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 877                                 ctrl |= SDHCI_CTRL_ADMA64;
 878                         else
 879                                 ctrl |= SDHCI_CTRL_ADMA32;
 880                 } else {
 881                         ctrl |= SDHCI_CTRL_SDMA;
 882                 }
 883                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 884         }
 885
 886         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 887                 int flags;
 888
 889                 flags = SG_MITER_ATOMIC;
 890                 if (host->data->flags & MMC_DATA_READ)
 891                         flags |= SG_MITER_TO_SG;
 892                 else
 893                         flags |= SG_MITER_FROM_SG;
 894                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 895                 host->blocks = data->blocks;
 896         }
 897
 898         sdhci_set_transfer_irqs(host);
 899
 900         /* Set the DMA boundary value and block size */
 901         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 902                 data->blksz), SDHCI_BLOCK_SIZE);
 903         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 904 }
 905
 906 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 907         struct mmc_command *cmd)
 908 {
 909         u16 mode = 0;
 910         struct mmc_data *data = cmd->data;
 911
 912         if (data == NULL) {
 913                 if (host->quirks2 &
 914                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
 915                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 916                 } else {
 917                 /* clear Auto CMD settings for no data CMDs */
 918                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 919                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 920                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 921                 }
 922                 return;
 923         }
 924
 925         WARN_ON(!host->data);
 926
 927         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
 928                 mode = SDHCI_TRNS_BLK_CNT_EN;
 929
 930         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 931                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
 932                 /*
 933                  * If we are sending CMD23, CMD12 never gets sent
 934                  * on successful completion (so no Auto-CMD12).
 935                  */
 936                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
 937                     (cmd->opcode != SD_IO_RW_EXTENDED))
 938                         mode |= SDHCI_TRNS_AUTO_CMD12;
 939                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 940                         mode |= SDHCI_TRNS_AUTO_CMD23;
 941                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 942                 }
 943         }
 944
 945         if (data->flags & MMC_DATA_READ)
 946                 mode |= SDHCI_TRNS_READ;
 947         if (host->flags & SDHCI_REQ_USE_DMA)
 948                 mode |= SDHCI_TRNS_DMA;
 949
 950         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 951 }
 952
 953 static void sdhci_finish_data(struct sdhci_host *host)
 954 {
 955         struct mmc_data *data;
 956
 957         BUG_ON(!host->data);
 958
 959         data = host->data;
 960         host->data = NULL;
 961
 962         if (host->flags & SDHCI_REQ_USE_DMA) {
 963                 if (host->flags & SDHCI_USE_ADMA)
 964                         sdhci_adma_table_post(host, data);
 965                 else {
 966                         if (!data->host_cookie)
 967                                 dma_unmap_sg(mmc_dev(host->mmc),
 968                                         data->sg, data->sg_len,
 969                                         (data->flags & MMC_DATA_READ) ?
 970                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 971                 }
 972         }
 973
 974         /*
 975          * The specification states that the block count register must
 976          * be updated, but it does not specify at what point in the
 977          * data flow. That makes the register entirely useless to read
 978          * back so we have to assume that nothing made it to the card
 979          * in the event of an error.
 980          */
 981         if (data->error)
 982                 data->bytes_xfered = 0;
 983         else
 984                 data->bytes_xfered = data->blksz * data->blocks;
 985
 986         /*
 987          * Need to send CMD12 if -
 988          * a) open-ended multiblock transfer (no CMD23)
 989          * b) error in multiblock transfer
 990          */
 991         if (data->stop &&
 992             (data->error ||
 993              !host->mrq->sbc)) {
 994
 995                 /*
 996                  * The controller needs a reset of internal state machines
 997                  * upon error conditions.
 998                  */
 999                 if (data->error) {
1000                         sdhci_do_reset(host, SDHCI_RESET_CMD);
1001                         sdhci_do_reset(host, SDHCI_RESET_DATA);
1002                 }
1003
1004                 sdhci_send_command(host, data->stop);
1005         } else
1006                 tasklet_schedule(&host->finish_tasklet);
1007 }
1008
1009 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1010 {
1011         int flags;
1012         u32 mask;
1013         unsigned long timeout;
1014
1015         WARN_ON(host->cmd);
1016
1017         /* Wait max 10 ms */
1018         timeout = 10;
1019
1020         mask = SDHCI_CMD_INHIBIT;
1021         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1022                 mask |= SDHCI_DATA_INHIBIT;
1023
1024         /* We shouldn't wait for data inihibit for stop commands, even
1025            though they might use busy signaling */
1026         if (host->mrq->data && (cmd == host->mrq->data->stop))
1027                 mask &= ~SDHCI_DATA_INHIBIT;
1028
1029         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1030                 if (timeout == 0) {
1031                         pr_err("%s: Controller never released "
1032                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1033                         sdhci_dumpregs(host);
1034                         cmd->error = -EIO;
1035                         tasklet_schedule(&host->finish_tasklet);
1036                         return;
1037                 }
1038                 timeout--;
1039                 mdelay(1);
1040         }
1041
1042         timeout = jiffies;
1043         if (!cmd->data && cmd->busy_timeout > 9000)
1044                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1045         else
1046                 timeout += 10 * HZ;
1047         mod_timer(&host->timer, timeout);
1048
1049         host->cmd = cmd;
1050         host->busy_handle = 0;
1051
1052         sdhci_prepare_data(host, cmd);
1053
1054         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1055
1056         sdhci_set_transfer_mode(host, cmd);
1057
1058         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1059                 pr_err("%s: Unsupported response type!\n",
1060                         mmc_hostname(host->mmc));
1061                 cmd->error = -EINVAL;
1062                 tasklet_schedule(&host->finish_tasklet);
1063                 return;
1064         }
1065
1066         if (!(cmd->flags & MMC_RSP_PRESENT))
1067                 flags = SDHCI_CMD_RESP_NONE;
1068         else if (cmd->flags & MMC_RSP_136)
1069                 flags = SDHCI_CMD_RESP_LONG;
1070         else if (cmd->flags & MMC_RSP_BUSY)
1071                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1072         else
1073                 flags = SDHCI_CMD_RESP_SHORT;
1074
1075         if (cmd->flags & MMC_RSP_CRC)
1076                 flags |= SDHCI_CMD_CRC;
1077         if (cmd->flags & MMC_RSP_OPCODE)
1078                 flags |= SDHCI_CMD_INDEX;
1079
1080         /* CMD19 is special in that the Data Present Select should be set */
1081         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1082             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1083                 flags |= SDHCI_CMD_DATA;
1084
1085         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1086 }
1087 EXPORT_SYMBOL_GPL(sdhci_send_command);
1088
1089 static void sdhci_finish_command(struct sdhci_host *host)
1090 {
1091         int i;
1092
1093         BUG_ON(host->cmd == NULL);
1094
1095         if (host->cmd->flags & MMC_RSP_PRESENT) {
1096                 if (host->cmd->flags & MMC_RSP_136) {
1097                         /* CRC is stripped so we need to do some shifting. */
1098                         for (i = 0;i < 4;i++) {
1099                                 host->cmd->resp[i] = sdhci_readl(host,
1100                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1101                                 if (i != 3)
1102                                         host->cmd->resp[i] |=
1103                                                 sdhci_readb(host,
1104                                                 SDHCI_RESPONSE + (3-i)*4-1);
1105                         }
1106                 } else {
1107                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1108                 }
1109         }
1110
1111         host->cmd->error = 0;
1112
1113         /* Finished CMD23, now send actual command. */
1114         if (host->cmd == host->mrq->sbc) {
1115                 host->cmd = NULL;
1116                 sdhci_send_command(host, host->mrq->cmd);
1117         } else {
1118
1119                 /* Processed actual command. */
1120                 if (host->data && host->data_early)
1121                         sdhci_finish_data(host);
1122
1123                 if (!host->cmd->data)
1124                         tasklet_schedule(&host->finish_tasklet);
1125
1126                 host->cmd = NULL;
1127         }
1128 }
1129
1130 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1131 {
1132         u16 preset = 0;
1133
1134         switch (host->timing) {
1135         case MMC_TIMING_UHS_SDR12:
1136                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1137                 break;
1138         case MMC_TIMING_UHS_SDR25:
1139                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1140                 break;
1141         case MMC_TIMING_UHS_SDR50:
1142                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1143                 break;
1144         case MMC_TIMING_UHS_SDR104:
1145         case MMC_TIMING_MMC_HS200:
1146                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1147                 break;
1148         case MMC_TIMING_UHS_DDR50:
1149         case MMC_TIMING_MMC_DDR52:
1150                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1151                 break;
1152         case MMC_TIMING_MMC_HS400:
1153                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1154                 break;
1155         default:
1156                 pr_warn("%s: Invalid UHS-I mode selected\n",
1157                         mmc_hostname(host->mmc));
1158                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1159                 break;
1160         }
1161         return preset;
1162 }
1163
1164 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1165 {
1166         int div = 0; /* Initialized for compiler warning */
1167         int real_div = div, clk_mul = 1;
1168         u16 clk = 0;
1169         unsigned long timeout;
1170
1171         host->mmc->actual_clock = 0;
1172
1173         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1174
1175         if (clock == 0)
1176                 return;
1177
1178         if (host->version >= SDHCI_SPEC_300) {
1179                 if (host->preset_enabled) {
1180                         u16 pre_val;
1181
1182                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1183                         pre_val = sdhci_get_preset_value(host);
1184                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1185                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1186                         if (host->clk_mul &&
1187                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1188                                 clk = SDHCI_PROG_CLOCK_MODE;
1189                                 real_div = div + 1;
1190                                 clk_mul = host->clk_mul;
1191                         } else {
1192                                 real_div = max_t(int, 1, div << 1);
1193                         }
1194                         goto clock_set;
1195                 }
1196
1197                 /*
1198                  * Check if the Host Controller supports Programmable Clock
1199                  * Mode.
1200                  */
1201                 if (host->clk_mul) {
1202                         for (div = 1; div <= 1024; div++) {
1203                                 if ((host->max_clk * host->clk_mul / div)
1204                                         <= clock)
1205                                         break;
1206                         }
1207                         /*
1208                          * Set Programmable Clock Mode in the Clock
1209                          * Control register.
1210                          */
1211                         clk = SDHCI_PROG_CLOCK_MODE;
1212                         real_div = div;
1213                         clk_mul = host->clk_mul;
1214                         div--;
1215                 } else {
1216                         /* Version 3.00 divisors must be a multiple of 2. */
1217                         if (host->max_clk <= clock)
1218                                 div = 1;
1219                         else {
1220                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1221                                      div += 2) {
1222                                         if ((host->max_clk / div) <= clock)
1223                                                 break;
1224                                 }
1225                         }
1226                         real_div = div;
1227                         div >>= 1;
1228                 }
1229         } else {
1230                 /* Version 2.00 divisors must be a power of 2. */
1231                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1232                         if ((host->max_clk / div) <= clock)
1233                                 break;
1234                 }
1235                 real_div = div;
1236                 div >>= 1;
1237         }
1238
1239 clock_set:
1240         if (real_div)
1241                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1242         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1243         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1244                 << SDHCI_DIVIDER_HI_SHIFT;
1245         clk |= SDHCI_CLOCK_INT_EN;
1246         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1247
1248         /* Wait max 20 ms */
1249         timeout = 20;
1250         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1251                 & SDHCI_CLOCK_INT_STABLE)) {
1252                 if (timeout == 0) {
1253                         pr_err("%s: Internal clock never "
1254                                 "stabilised.\n", mmc_hostname(host->mmc));
1255                         sdhci_dumpregs(host);
1256                         return;
1257                 }
1258                 timeout--;
1259                 mdelay(1);
1260         }
1261
1262         clk |= SDHCI_CLOCK_CARD_EN;
1263         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1264 }
1265 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1266
1267 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1268                             unsigned short vdd)
1269 {
1270         struct mmc_host *mmc = host->mmc;
1271         u8 pwr = 0;
1272
1273         if (!IS_ERR(mmc->supply.vmmc)) {
1274                 spin_unlock_irq(&host->lock);
1275                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1276                 spin_lock_irq(&host->lock);
1277
1278                 if (mode != MMC_POWER_OFF)
1279                         sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1280                 else
1281                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1282
1283                 return;
1284         }
1285
1286         if (mode != MMC_POWER_OFF) {
1287                 switch (1 << vdd) {
1288                 case MMC_VDD_165_195:
1289                         pwr = SDHCI_POWER_180;
1290                         break;
1291                 case MMC_VDD_29_30:
1292                 case MMC_VDD_30_31:
1293                         pwr = SDHCI_POWER_300;
1294                         break;
1295                 case MMC_VDD_32_33:
1296                 case MMC_VDD_33_34:
1297                         pwr = SDHCI_POWER_330;
1298                         break;
1299                 default:
1300                         BUG();
1301                 }
1302         }
1303
1304         if (host->pwr == pwr)
1305                 return;
1306
1307         host->pwr = pwr;
1308
1309         if (pwr == 0) {
1310                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1311                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1312                         sdhci_runtime_pm_bus_off(host);
1313                 vdd = 0;
1314         } else {
1315                 /*
1316                  * Spec says that we should clear the power reg before setting
1317                  * a new value. Some controllers don't seem to like this though.
1318                  */
1319                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1320                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1321
1322                 /*
1323                  * At least the Marvell CaFe chip gets confused if we set the
1324                  * voltage and set turn on power at the same time, so set the
1325                  * voltage first.
1326                  */
1327                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1328                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1329
1330                 pwr |= SDHCI_POWER_ON;
1331
1332                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1333
1334                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1335                         sdhci_runtime_pm_bus_on(host);
1336
1337                 /*
1338                  * Some controllers need an extra 10ms delay of 10ms before
1339                  * they can apply clock after applying power
1340                  */
1341                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1342                         mdelay(10);
1343         }
1344 }
1345
1346 /*****************************************************************************\
1347  *                                                                           *
1348  * MMC callbacks                                                             *
1349  *                                                                           *
1350 \*****************************************************************************/
1351
1352 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1353 {
1354         struct sdhci_host *host;
1355         int present;
1356         unsigned long flags;
1357         u32 tuning_opcode;
1358
1359         host = mmc_priv(mmc);
1360
1361         sdhci_runtime_pm_get(host);
1362
1363         /* Firstly check card presence */
1364         present = sdhci_do_get_cd(host);
1365
1366         spin_lock_irqsave(&host->lock, flags);
1367
1368         WARN_ON(host->mrq != NULL);
1369
1370 #ifndef SDHCI_USE_LEDS_CLASS
1371         sdhci_activate_led(host);
1372 #endif
1373
1374         /*
1375          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1376          * requests if Auto-CMD12 is enabled.
1377          */
1378         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1379                 if (mrq->stop) {
1380                         mrq->data->stop = NULL;
1381                         mrq->stop = NULL;
1382                 }
1383         }
1384
1385         host->mrq = mrq;
1386
1387         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1388                 host->mrq->cmd->error = -ENOMEDIUM;
1389                 tasklet_schedule(&host->finish_tasklet);
1390         } else {
1391                 u32 present_state;
1392
1393                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1394                 /*
1395                  * Check if the re-tuning timer has already expired and there
1396                  * is no on-going data transfer and DAT0 is not busy. If so,
1397                  * we need to execute tuning procedure before sending command.
1398                  */
1399                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1400                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1401                     (present_state & SDHCI_DATA_0_LVL_MASK)) {
1402                         if (mmc->card) {
1403                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1404                                 tuning_opcode =
1405                                         mmc->card->type == MMC_TYPE_MMC ?
1406                                         MMC_SEND_TUNING_BLOCK_HS200 :
1407                                         MMC_SEND_TUNING_BLOCK;
1408
1409                                 /* Here we need to set the host->mrq to NULL,
1410                                  * in case the pending finish_tasklet
1411                                  * finishes it incorrectly.
1412                                  */
1413                                 host->mrq = NULL;
1414
1415                                 spin_unlock_irqrestore(&host->lock, flags);
1416                                 sdhci_execute_tuning(mmc, tuning_opcode);
1417                                 spin_lock_irqsave(&host->lock, flags);
1418
1419                                 /* Restore original mmc_request structure */
1420                                 host->mrq = mrq;
1421                         }
1422                 }
1423
1424                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1425                         sdhci_send_command(host, mrq->sbc);
1426                 else
1427                         sdhci_send_command(host, mrq->cmd);
1428         }
1429
1430         mmiowb();
1431         spin_unlock_irqrestore(&host->lock, flags);
1432 }
1433
1434 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1435 {
1436         u8 ctrl;
1437
1438         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1439         if (width == MMC_BUS_WIDTH_8) {
1440                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1441                 if (host->version >= SDHCI_SPEC_300)
1442                         ctrl |= SDHCI_CTRL_8BITBUS;
1443         } else {
1444                 if (host->version >= SDHCI_SPEC_300)
1445                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1446                 if (width == MMC_BUS_WIDTH_4)
1447                         ctrl |= SDHCI_CTRL_4BITBUS;
1448                 else
1449                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1450         }
1451         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1452 }
1453 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1454
1455 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1456 {
1457         u16 ctrl_2;
1458
1459         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1460         /* Select Bus Speed Mode for host */
1461         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1462         if ((timing == MMC_TIMING_MMC_HS200) ||
1463             (timing == MMC_TIMING_UHS_SDR104))
1464                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1465         else if (timing == MMC_TIMING_UHS_SDR12)
1466                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1467         else if (timing == MMC_TIMING_UHS_SDR25)
1468                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1469         else if (timing == MMC_TIMING_UHS_SDR50)
1470                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1471         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1472                  (timing == MMC_TIMING_MMC_DDR52))
1473                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1474         else if (timing == MMC_TIMING_MMC_HS400)
1475                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1476         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1477 }
1478 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1479
1480 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1481 {
1482         unsigned long flags;
1483         u8 ctrl;
1484         struct mmc_host *mmc = host->mmc;
1485
1486         spin_lock_irqsave(&host->lock, flags);
1487
1488         if (host->flags & SDHCI_DEVICE_DEAD) {
1489                 spin_unlock_irqrestore(&host->lock, flags);
1490                 if (!IS_ERR(mmc->supply.vmmc) &&
1491                     ios->power_mode == MMC_POWER_OFF)
1492                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1493                 return;
1494         }
1495
1496         /*
1497          * Reset the chip on each power off.
1498          * Should clear out any weird states.
1499          */
1500         if (ios->power_mode == MMC_POWER_OFF) {
1501                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1502                 sdhci_reinit(host);
1503         }
1504
1505         if (host->version >= SDHCI_SPEC_300 &&
1506                 (ios->power_mode == MMC_POWER_UP) &&
1507                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1508                 sdhci_enable_preset_value(host, false);
1509
1510         if (!ios->clock || ios->clock != host->clock) {
1511                 host->ops->set_clock(host, ios->clock);
1512                 host->clock = ios->clock;
1513
1514                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1515                     host->clock) {
1516                         host->timeout_clk = host->mmc->actual_clock ?
1517                                                 host->mmc->actual_clock / 1000 :
1518                                                 host->clock / 1000;
1519                         host->mmc->max_busy_timeout =
1520                                 host->ops->get_max_timeout_count ?
1521                                 host->ops->get_max_timeout_count(host) :
1522                                 1 << 27;
1523                         host->mmc->max_busy_timeout /= host->timeout_clk;
1524                 }
1525         }
1526
1527         sdhci_set_power(host, ios->power_mode, ios->vdd);
1528
1529         if (host->ops->platform_send_init_74_clocks)
1530                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1531
1532         host->ops->set_bus_width(host, ios->bus_width);
1533
1534         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1535
1536         if ((ios->timing == MMC_TIMING_SD_HS ||
1537              ios->timing == MMC_TIMING_MMC_HS)
1538             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1539                 ctrl |= SDHCI_CTRL_HISPD;
1540         else
1541                 ctrl &= ~SDHCI_CTRL_HISPD;
1542
1543         if (host->version >= SDHCI_SPEC_300) {
1544                 u16 clk, ctrl_2;
1545
1546                 /* In case of UHS-I modes, set High Speed Enable */
1547                 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1548                     (ios->timing == MMC_TIMING_MMC_HS200) ||
1549                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1550                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1551                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1552                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1553                     (ios->timing == MMC_TIMING_UHS_SDR25))
1554                         ctrl |= SDHCI_CTRL_HISPD;
1555
1556                 if (!host->preset_enabled) {
1557                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1558                         /*
1559                          * We only need to set Driver Strength if the
1560                          * preset value enable is not set.
1561                          */
1562                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1563                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1564                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1565                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1566                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1567                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1568
1569                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1570                 } else {
1571                         /*
1572                          * According to SDHC Spec v3.00, if the Preset Value
1573                          * Enable in the Host Control 2 register is set, we
1574                          * need to reset SD Clock Enable before changing High
1575                          * Speed Enable to avoid generating clock gliches.
1576                          */
1577
1578                         /* Reset SD Clock Enable */
1579                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1580                         clk &= ~SDHCI_CLOCK_CARD_EN;
1581                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1582
1583                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1584
1585                         /* Re-enable SD Clock */
1586                         host->ops->set_clock(host, host->clock);
1587                 }
1588
1589                 /* Reset SD Clock Enable */
1590                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1591                 clk &= ~SDHCI_CLOCK_CARD_EN;
1592                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1593
1594                 host->ops->set_uhs_signaling(host, ios->timing);
1595                 host->timing = ios->timing;
1596
1597                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1598                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1599                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1600                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1601                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1602                                  (ios->timing == MMC_TIMING_UHS_DDR50) ||
1603                                  (ios->timing == MMC_TIMING_MMC_DDR52))) {
1604                         u16 preset;
1605
1606                         sdhci_enable_preset_value(host, true);
1607                         preset = sdhci_get_preset_value(host);
1608                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1609                                 >> SDHCI_PRESET_DRV_SHIFT;
1610                 }
1611
1612                 /* Re-enable SD Clock */
1613                 host->ops->set_clock(host, host->clock);
1614         } else
1615                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1616
1617         /*
1618          * Some (ENE) controllers go apeshit on some ios operation,
1619          * signalling timeout and CRC errors even on CMD0. Resetting
1620          * it on each ios seems to solve the problem.
1621          */
1622         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1623                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1624
1625         mmiowb();
1626         spin_unlock_irqrestore(&host->lock, flags);
1627 }
1628
1629 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1630 {
1631         struct sdhci_host *host = mmc_priv(mmc);
1632
1633         sdhci_runtime_pm_get(host);
1634         sdhci_do_set_ios(host, ios);
1635         sdhci_runtime_pm_put(host);
1636 }
1637
1638 static int sdhci_do_get_cd(struct sdhci_host *host)
1639 {
1640         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1641
1642         if (host->flags & SDHCI_DEVICE_DEAD)
1643                 return 0;
1644
1645         /* If polling/nonremovable, assume that the card is always present. */
1646         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1647             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1648                 return 1;
1649
1650         /* Try slot gpio detect */
1651         if (!IS_ERR_VALUE(gpio_cd))
1652                 return !!gpio_cd;
1653
1654         /* Host native card detect */
1655         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1656 }
1657
1658 static int sdhci_get_cd(struct mmc_host *mmc)
1659 {
1660         struct sdhci_host *host = mmc_priv(mmc);
1661         int ret;
1662
1663         sdhci_runtime_pm_get(host);
1664         ret = sdhci_do_get_cd(host);
1665         sdhci_runtime_pm_put(host);
1666         return ret;
1667 }
1668
1669 static int sdhci_check_ro(struct sdhci_host *host)
1670 {
1671         unsigned long flags;
1672         int is_readonly;
1673
1674         spin_lock_irqsave(&host->lock, flags);
1675
1676         if (host->flags & SDHCI_DEVICE_DEAD)
1677                 is_readonly = 0;
1678         else if (host->ops->get_ro)
1679                 is_readonly = host->ops->get_ro(host);
1680         else
1681                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1682                                 & SDHCI_WRITE_PROTECT);
1683
1684         spin_unlock_irqrestore(&host->lock, flags);
1685
1686         /* This quirk needs to be replaced by a callback-function later */
1687         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1688                 !is_readonly : is_readonly;
1689 }
1690
1691 #define SAMPLE_COUNT    5
1692
1693 static int sdhci_do_get_ro(struct sdhci_host *host)
1694 {
1695         int i, ro_count;
1696
1697         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1698                 return sdhci_check_ro(host);
1699
1700         ro_count = 0;
1701         for (i = 0; i < SAMPLE_COUNT; i++) {
1702                 if (sdhci_check_ro(host)) {
1703                         if (++ro_count > SAMPLE_COUNT / 2)
1704                                 return 1;
1705                 }
1706                 msleep(30);
1707         }
1708         return 0;
1709 }
1710
1711 static void sdhci_hw_reset(struct mmc_host *mmc)
1712 {
1713         struct sdhci_host *host = mmc_priv(mmc);
1714
1715         if (host->ops && host->ops->hw_reset)
1716                 host->ops->hw_reset(host);
1717 }
1718
1719 static int sdhci_get_ro(struct mmc_host *mmc)
1720 {
1721         struct sdhci_host *host = mmc_priv(mmc);
1722         int ret;
1723
1724         sdhci_runtime_pm_get(host);
1725         ret = sdhci_do_get_ro(host);
1726         sdhci_runtime_pm_put(host);
1727         return ret;
1728 }
1729
1730 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1731 {
1732         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1733                 if (enable)
1734                         host->ier |= SDHCI_INT_CARD_INT;
1735                 else
1736                         host->ier &= ~SDHCI_INT_CARD_INT;
1737
1738                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1739                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1740                 mmiowb();
1741         }
1742 }
1743
1744 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1745 {
1746         struct sdhci_host *host = mmc_priv(mmc);
1747         unsigned long flags;
1748
1749         sdhci_runtime_pm_get(host);
1750
1751         spin_lock_irqsave(&host->lock, flags);
1752         if (enable)
1753                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1754         else
1755                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1756
1757         sdhci_enable_sdio_irq_nolock(host, enable);
1758         spin_unlock_irqrestore(&host->lock, flags);
1759
1760         sdhci_runtime_pm_put(host);
1761 }
1762
1763 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1764                                                 struct mmc_ios *ios)
1765 {
1766         struct mmc_host *mmc = host->mmc;
1767         u16 ctrl;
1768         int ret;
1769
1770         /*
1771          * Signal Voltage Switching is only applicable for Host Controllers
1772          * v3.00 and above.
1773          */
1774         if (host->version < SDHCI_SPEC_300)
1775                 return 0;
1776
1777         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1778
1779         switch (ios->signal_voltage) {
1780         case MMC_SIGNAL_VOLTAGE_330:
1781                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1782                 ctrl &= ~SDHCI_CTRL_VDD_180;
1783                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1784
1785                 if (!IS_ERR(mmc->supply.vqmmc)) {
1786                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1787                                                     3600000);
1788                         if (ret) {
1789                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1790                                         mmc_hostname(mmc));
1791                                 return -EIO;
1792                         }
1793                 }
1794                 /* Wait for 5ms */
1795                 usleep_range(5000, 5500);
1796
1797                 /* 3.3V regulator output should be stable within 5 ms */
1798                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1799                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1800                         return 0;
1801
1802                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1803                         mmc_hostname(mmc));
1804
1805                 return -EAGAIN;
1806         case MMC_SIGNAL_VOLTAGE_180:
1807                 if (!IS_ERR(mmc->supply.vqmmc)) {
1808                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1809                                         1700000, 1950000);
1810                         if (ret) {
1811                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1812                                         mmc_hostname(mmc));
1813                                 return -EIO;
1814                         }
1815                 }
1816
1817                 /*
1818                  * Enable 1.8V Signal Enable in the Host Control2
1819                  * register
1820                  */
1821                 ctrl |= SDHCI_CTRL_VDD_180;
1822                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1823
1824                 /* Some controller need to do more when switching */
1825                 if (host->ops->voltage_switch)
1826                         host->ops->voltage_switch(host);
1827
1828                 /* 1.8V regulator output should be stable within 5 ms */
1829                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1830                 if (ctrl & SDHCI_CTRL_VDD_180)
1831                         return 0;
1832
1833                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1834                         mmc_hostname(mmc));
1835
1836                 return -EAGAIN;
1837         case MMC_SIGNAL_VOLTAGE_120:
1838                 if (!IS_ERR(mmc->supply.vqmmc)) {
1839                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1840                                                     1300000);
1841                         if (ret) {
1842                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1843                                         mmc_hostname(mmc));
1844                                 return -EIO;
1845                         }
1846                 }
1847                 return 0;
1848         default:
1849                 /* No signal voltage switch required */
1850                 return 0;
1851         }
1852 }
1853
1854 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1855         struct mmc_ios *ios)
1856 {
1857         struct sdhci_host *host = mmc_priv(mmc);
1858         int err;
1859
1860         if (host->version < SDHCI_SPEC_300)
1861                 return 0;
1862         sdhci_runtime_pm_get(host);
1863         err = sdhci_do_start_signal_voltage_switch(host, ios);
1864         sdhci_runtime_pm_put(host);
1865         return err;
1866 }
1867
1868 static int sdhci_card_busy(struct mmc_host *mmc)
1869 {
1870         struct sdhci_host *host = mmc_priv(mmc);
1871         u32 present_state;
1872
1873         sdhci_runtime_pm_get(host);
1874         /* Check whether DAT[3:0] is 0000 */
1875         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1876         sdhci_runtime_pm_put(host);
1877
1878         return !(present_state & SDHCI_DATA_LVL_MASK);
1879 }
1880
1881 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1882 {
1883         struct sdhci_host *host = mmc_priv(mmc);
1884         unsigned long flags;
1885
1886         spin_lock_irqsave(&host->lock, flags);
1887         host->flags |= SDHCI_HS400_TUNING;
1888         spin_unlock_irqrestore(&host->lock, flags);
1889
1890         return 0;
1891 }
1892
1893 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1894 {
1895         struct sdhci_host *host = mmc_priv(mmc);
1896         u16 ctrl;
1897         int tuning_loop_counter = MAX_TUNING_LOOP;
1898         int err = 0;
1899         unsigned long flags;
1900         unsigned int tuning_count = 0;
1901         bool hs400_tuning;
1902
1903         sdhci_runtime_pm_get(host);
1904         spin_lock_irqsave(&host->lock, flags);
1905
1906         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1907         host->flags &= ~SDHCI_HS400_TUNING;
1908
1909         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1910                 tuning_count = host->tuning_count;
1911
1912         /*
1913          * The Host Controller needs tuning only in case of SDR104 mode
1914          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1915          * Capabilities register.
1916          * If the Host Controller supports the HS200 mode then the
1917          * tuning function has to be executed.
1918          */
1919         switch (host->timing) {
1920         /* HS400 tuning is done in HS200 mode */
1921         case MMC_TIMING_MMC_HS400:
1922                 err = -EINVAL;
1923                 goto out_unlock;
1924
1925         case MMC_TIMING_MMC_HS200:
1926                 /*
1927                  * Periodic re-tuning for HS400 is not expected to be needed, so
1928                  * disable it here.
1929                  */
1930                 if (hs400_tuning)
1931                         tuning_count = 0;
1932                 break;
1933
1934         case MMC_TIMING_UHS_SDR104:
1935                 break;
1936
1937         case MMC_TIMING_UHS_SDR50:
1938                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1939                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1940                         break;
1941                 /* FALLTHROUGH */
1942
1943         default:
1944                 goto out_unlock;
1945         }
1946
1947         if (host->ops->platform_execute_tuning) {
1948                 spin_unlock_irqrestore(&host->lock, flags);
1949                 err = host->ops->platform_execute_tuning(host, opcode);
1950                 sdhci_runtime_pm_put(host);
1951                 return err;
1952         }
1953
1954         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1955         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1956         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1957                 ctrl |= SDHCI_CTRL_TUNED_CLK;
1958         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1959
1960         /*
1961          * As per the Host Controller spec v3.00, tuning command
1962          * generates Buffer Read Ready interrupt, so enable that.
1963          *
1964          * Note: The spec clearly says that when tuning sequence
1965          * is being performed, the controller does not generate
1966          * interrupts other than Buffer Read Ready interrupt. But
1967          * to make sure we don't hit a controller bug, we _only_
1968          * enable Buffer Read Ready interrupt here.
1969          */
1970         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1971         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1972
1973         /*
1974          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1975          * of loops reaches 40 times or a timeout of 150ms occurs.
1976          */
1977         do {
1978                 struct mmc_command cmd = {0};
1979                 struct mmc_request mrq = {NULL};
1980
1981                 cmd.opcode = opcode;
1982                 cmd.arg = 0;
1983                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1984                 cmd.retries = 0;
1985                 cmd.data = NULL;
1986                 cmd.error = 0;
1987
1988                 if (tuning_loop_counter-- == 0)
1989                         break;
1990
1991                 mrq.cmd = &cmd;
1992                 host->mrq = &mrq;
1993
1994                 /*
1995                  * In response to CMD19, the card sends 64 bytes of tuning
1996                  * block to the Host Controller. So we set the block size
1997                  * to 64 here.
1998                  */
1999                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2000                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2001                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2002                                              SDHCI_BLOCK_SIZE);
2003                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2004                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2005                                              SDHCI_BLOCK_SIZE);
2006                 } else {
2007                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2008                                      SDHCI_BLOCK_SIZE);
2009                 }
2010
2011                 /*
2012                  * The tuning block is sent by the card to the host controller.
2013                  * So we set the TRNS_READ bit in the Transfer Mode register.
2014                  * This also takes care of setting DMA Enable and Multi Block
2015                  * Select in the same register to 0.
2016                  */
2017                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2018
2019                 sdhci_send_command(host, &cmd);
2020
2021                 host->cmd = NULL;
2022                 host->mrq = NULL;
2023
2024                 spin_unlock_irqrestore(&host->lock, flags);
2025                 /* Wait for Buffer Read Ready interrupt */
2026                 wait_event_interruptible_timeout(host->buf_ready_int,
2027                                         (host->tuning_done == 1),
2028                                         msecs_to_jiffies(50));
2029                 spin_lock_irqsave(&host->lock, flags);
2030
2031                 if (!host->tuning_done) {
2032                         pr_info(DRIVER_NAME ": Timeout waiting for "
2033                                 "Buffer Read Ready interrupt during tuning "
2034                                 "procedure, falling back to fixed sampling "
2035                                 "clock\n");
2036                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2037                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2038                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2039                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2040
2041                         err = -EIO;
2042                         goto out;
2043                 }
2044
2045                 host->tuning_done = 0;
2046
2047                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2048
2049                 /* eMMC spec does not require a delay between tuning cycles */
2050                 if (opcode == MMC_SEND_TUNING_BLOCK)
2051                         mdelay(1);
2052         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2053
2054         /*
2055          * The Host Driver has exhausted the maximum number of loops allowed,
2056          * so use fixed sampling frequency.
2057          */
2058         if (tuning_loop_counter < 0) {
2059                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2060                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2061         }
2062         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2063                 pr_info(DRIVER_NAME ": Tuning procedure"
2064                         " failed, falling back to fixed sampling"
2065                         " clock\n");
2066                 err = -EIO;
2067         }
2068
2069 out:
2070         host->flags &= ~SDHCI_NEEDS_RETUNING;
2071
2072         if (tuning_count) {
2073                 host->flags |= SDHCI_USING_RETUNING_TIMER;
2074                 mod_timer(&host->tuning_timer, jiffies + tuning_count * HZ);
2075         }
2076
2077         /*
2078          * In case tuning fails, host controllers which support re-tuning can
2079          * try tuning again at a later time, when the re-tuning timer expires.
2080          * So for these controllers, we return 0. Since there might be other
2081          * controllers who do not have this capability, we return error for
2082          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2083          * a retuning timer to do the retuning for the card.
2084          */
2085         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2086                 err = 0;
2087
2088         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2089         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2090 out_unlock:
2091         spin_unlock_irqrestore(&host->lock, flags);
2092         sdhci_runtime_pm_put(host);
2093
2094         return err;
2095 }
2096
2097
2098 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2099 {
2100         /* Host Controller v3.00 defines preset value registers */
2101         if (host->version < SDHCI_SPEC_300)
2102                 return;
2103
2104         /*
2105          * We only enable or disable Preset Value if they are not already
2106          * enabled or disabled respectively. Otherwise, we bail out.
2107          */
2108         if (host->preset_enabled != enable) {
2109                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2110
2111                 if (enable)
2112                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2113                 else
2114                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2115
2116                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2117
2118                 if (enable)
2119                         host->flags |= SDHCI_PV_ENABLED;
2120                 else
2121                         host->flags &= ~SDHCI_PV_ENABLED;
2122
2123                 host->preset_enabled = enable;
2124         }
2125 }
2126
2127 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2128                                 int err)
2129 {
2130         struct sdhci_host *host = mmc_priv(mmc);
2131         struct mmc_data *data = mrq->data;
2132
2133         if (host->flags & SDHCI_REQ_USE_DMA) {
2134                 if (data->host_cookie)
2135                         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2136                                          data->flags & MMC_DATA_WRITE ?
2137                                          DMA_TO_DEVICE : DMA_FROM_DEVICE);
2138                 mrq->data->host_cookie = 0;
2139         }
2140 }
2141
2142 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2143                                        struct mmc_data *data,
2144                                        struct sdhci_host_next *next)
2145 {
2146         int sg_count;
2147
2148         if (!next && data->host_cookie &&
2149             data->host_cookie != host->next_data.cookie) {
2150                 pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
2151                         __func__, data->host_cookie, host->next_data.cookie);
2152                 data->host_cookie = 0;
2153         }
2154
2155         /* Check if next job is already prepared */
2156         if (next ||
2157             (!next && data->host_cookie != host->next_data.cookie)) {
2158                 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
2159                                      data->sg_len,
2160                                      data->flags & MMC_DATA_WRITE ?
2161                                      DMA_TO_DEVICE : DMA_FROM_DEVICE);
2162
2163         } else {
2164                 sg_count = host->next_data.sg_count;
2165                 host->next_data.sg_count = 0;
2166         }
2167
2168
2169         if (sg_count == 0)
2170                 return -EINVAL;
2171
2172         if (next) {
2173                 next->sg_count = sg_count;
2174                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
2175         } else
2176                 host->sg_count = sg_count;
2177
2178         return sg_count;
2179 }
2180
2181 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2182                                bool is_first_req)
2183 {
2184         struct sdhci_host *host = mmc_priv(mmc);
2185
2186         if (mrq->data->host_cookie) {
2187                 mrq->data->host_cookie = 0;
2188                 return;
2189         }
2190
2191         if (host->flags & SDHCI_REQ_USE_DMA)
2192                 if (sdhci_pre_dma_transfer(host,
2193                                         mrq->data,
2194                                         &host->next_data) < 0)
2195                         mrq->data->host_cookie = 0;
2196 }
2197
2198 static void sdhci_card_event(struct mmc_host *mmc)
2199 {
2200         struct sdhci_host *host = mmc_priv(mmc);
2201         unsigned long flags;
2202         int present;
2203
2204         /* First check if client has provided their own card event */
2205         if (host->ops->card_event)
2206                 host->ops->card_event(host);
2207
2208         present = sdhci_do_get_cd(host);
2209
2210         spin_lock_irqsave(&host->lock, flags);
2211
2212         /* Check host->mrq first in case we are runtime suspended */
2213         if (host->mrq && !present) {
2214                 pr_err("%s: Card removed during transfer!\n",
2215                         mmc_hostname(host->mmc));
2216                 pr_err("%s: Resetting controller.\n",
2217                         mmc_hostname(host->mmc));
2218
2219                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2220                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2221
2222                 host->mrq->cmd->error = -ENOMEDIUM;
2223                 tasklet_schedule(&host->finish_tasklet);
2224         }
2225
2226         spin_unlock_irqrestore(&host->lock, flags);
2227 }
2228
2229 static const struct mmc_host_ops sdhci_ops = {
2230         .request        = sdhci_request,
2231         .post_req       = sdhci_post_req,
2232         .pre_req        = sdhci_pre_req,
2233         .set_ios        = sdhci_set_ios,
2234         .get_cd         = sdhci_get_cd,
2235         .get_ro         = sdhci_get_ro,
2236         .hw_reset       = sdhci_hw_reset,
2237         .enable_sdio_irq = sdhci_enable_sdio_irq,
2238         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2239         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2240         .execute_tuning                 = sdhci_execute_tuning,
2241         .card_event                     = sdhci_card_event,
2242         .card_busy      = sdhci_card_busy,
2243 };
2244
2245 /*****************************************************************************\
2246  *                                                                           *
2247  * Tasklets                                                                  *
2248  *                                                                           *
2249 \*****************************************************************************/
2250
2251 static void sdhci_tasklet_finish(unsigned long param)
2252 {
2253         struct sdhci_host *host;
2254         unsigned long flags;
2255         struct mmc_request *mrq;
2256
2257         host = (struct sdhci_host*)param;
2258
2259         spin_lock_irqsave(&host->lock, flags);
2260
2261         /*
2262          * If this tasklet gets rescheduled while running, it will
2263          * be run again afterwards but without any active request.
2264          */
2265         if (!host->mrq) {
2266                 spin_unlock_irqrestore(&host->lock, flags);
2267                 return;
2268         }
2269
2270         del_timer(&host->timer);
2271
2272         mrq = host->mrq;
2273
2274         /*
2275          * The controller needs a reset of internal state machines
2276          * upon error conditions.
2277          */
2278         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2279             ((mrq->cmd && mrq->cmd->error) ||
2280              (mrq->sbc && mrq->sbc->error) ||
2281              (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2282                             (mrq->data->stop && mrq->data->stop->error))) ||
2283              (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2284
2285                 /* Some controllers need this kick or reset won't work here */
2286                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2287                         /* This is to force an update */
2288                         host->ops->set_clock(host, host->clock);
2289
2290                 /* Spec says we should do both at the same time, but Ricoh
2291                    controllers do not like that. */
2292                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2293                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2294         }
2295
2296         host->mrq = NULL;
2297         host->cmd = NULL;
2298         host->data = NULL;
2299
2300 #ifndef SDHCI_USE_LEDS_CLASS
2301         sdhci_deactivate_led(host);
2302 #endif
2303
2304         mmiowb();
2305         spin_unlock_irqrestore(&host->lock, flags);
2306
2307         mmc_request_done(host->mmc, mrq);
2308         sdhci_runtime_pm_put(host);
2309 }
2310
2311 static void sdhci_timeout_timer(unsigned long data)
2312 {
2313         struct sdhci_host *host;
2314         unsigned long flags;
2315
2316         host = (struct sdhci_host*)data;
2317
2318         spin_lock_irqsave(&host->lock, flags);
2319
2320         if (host->mrq) {
2321                 pr_err("%s: Timeout waiting for hardware "
2322                         "interrupt.\n", mmc_hostname(host->mmc));
2323                 sdhci_dumpregs(host);
2324
2325                 if (host->data) {
2326                         host->data->error = -ETIMEDOUT;
2327                         sdhci_finish_data(host);
2328                 } else {
2329                         if (host->cmd)
2330                                 host->cmd->error = -ETIMEDOUT;
2331                         else
2332                                 host->mrq->cmd->error = -ETIMEDOUT;
2333
2334                         tasklet_schedule(&host->finish_tasklet);
2335                 }
2336         }
2337
2338         mmiowb();
2339         spin_unlock_irqrestore(&host->lock, flags);
2340 }
2341
2342 static void sdhci_tuning_timer(unsigned long data)
2343 {
2344         struct sdhci_host *host;
2345         unsigned long flags;
2346
2347         host = (struct sdhci_host *)data;
2348
2349         spin_lock_irqsave(&host->lock, flags);
2350
2351         host->flags |= SDHCI_NEEDS_RETUNING;
2352
2353         spin_unlock_irqrestore(&host->lock, flags);
2354 }
2355
2356 /*****************************************************************************\
2357  *                                                                           *
2358  * Interrupt handling                                                        *
2359  *                                                                           *
2360 \*****************************************************************************/
2361
2362 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2363 {
2364         BUG_ON(intmask == 0);
2365
2366         if (!host->cmd) {
2367                 pr_err("%s: Got command interrupt 0x%08x even "
2368                         "though no command operation was in progress.\n",
2369                         mmc_hostname(host->mmc), (unsigned)intmask);
2370                 sdhci_dumpregs(host);
2371                 return;
2372         }
2373
2374         if (intmask & SDHCI_INT_TIMEOUT)
2375                 host->cmd->error = -ETIMEDOUT;
2376         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2377                         SDHCI_INT_INDEX))
2378                 host->cmd->error = -EILSEQ;
2379
2380         if (host->cmd->error) {
2381                 tasklet_schedule(&host->finish_tasklet);
2382                 return;
2383         }
2384
2385         /*
2386          * The host can send and interrupt when the busy state has
2387          * ended, allowing us to wait without wasting CPU cycles.
2388          * Unfortunately this is overloaded on the "data complete"
2389          * interrupt, so we need to take some care when handling
2390          * it.
2391          *
2392          * Note: The 1.0 specification is a bit ambiguous about this
2393          *       feature so there might be some problems with older
2394          *       controllers.
2395          */
2396         if (host->cmd->flags & MMC_RSP_BUSY) {
2397                 if (host->cmd->data)
2398                         DBG("Cannot wait for busy signal when also "
2399                                 "doing a data transfer");
2400                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2401                                 && !host->busy_handle) {
2402                         /* Mark that command complete before busy is ended */
2403                         host->busy_handle = 1;
2404                         return;
2405                 }
2406
2407                 /* The controller does not support the end-of-busy IRQ,
2408                  * fall through and take the SDHCI_INT_RESPONSE */
2409         } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2410                    host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2411                 *mask &= ~SDHCI_INT_DATA_END;
2412         }
2413
2414         if (intmask & SDHCI_INT_RESPONSE)
2415                 sdhci_finish_command(host);
2416 }
2417
2418 #ifdef CONFIG_MMC_DEBUG
2419 static void sdhci_adma_show_error(struct sdhci_host *host)
2420 {
2421         const char *name = mmc_hostname(host->mmc);
2422         void *desc = host->adma_table;
2423
2424         sdhci_dumpregs(host);
2425
2426         while (true) {
2427                 struct sdhci_adma2_64_desc *dma_desc = desc;
2428
2429                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2430                         DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2431                             name, desc, le32_to_cpu(dma_desc->addr_hi),
2432                             le32_to_cpu(dma_desc->addr_lo),
2433                             le16_to_cpu(dma_desc->len),
2434                             le16_to_cpu(dma_desc->cmd));
2435                 else
2436                         DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2437                             name, desc, le32_to_cpu(dma_desc->addr_lo),
2438                             le16_to_cpu(dma_desc->len),
2439                             le16_to_cpu(dma_desc->cmd));
2440
2441                 desc += host->desc_sz;
2442
2443                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2444                         break;
2445         }
2446 }
2447 #else
2448 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2449 #endif
2450
2451 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2452 {
2453         u32 command;
2454         BUG_ON(intmask == 0);
2455
2456         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2457         if (intmask & SDHCI_INT_DATA_AVAIL) {
2458                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2459                 if (command == MMC_SEND_TUNING_BLOCK ||
2460                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2461                         host->tuning_done = 1;
2462                         wake_up(&host->buf_ready_int);
2463                         return;
2464                 }
2465         }
2466
2467         if (!host->data) {
2468                 /*
2469                  * The "data complete" interrupt is also used to
2470                  * indicate that a busy state has ended. See comment
2471                  * above in sdhci_cmd_irq().
2472                  */
2473                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2474                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2475                                 host->cmd->error = -ETIMEDOUT;
2476                                 tasklet_schedule(&host->finish_tasklet);
2477                                 return;
2478                         }
2479                         if (intmask & SDHCI_INT_DATA_END) {
2480                                 /*
2481                                  * Some cards handle busy-end interrupt
2482                                  * before the command completed, so make
2483                                  * sure we do things in the proper order.
2484                                  */
2485                                 if (host->busy_handle)
2486                                         sdhci_finish_command(host);
2487                                 else
2488                                         host->busy_handle = 1;
2489                                 return;
2490                         }
2491                 }
2492
2493                 pr_err("%s: Got data interrupt 0x%08x even "
2494                         "though no data operation was in progress.\n",
2495                         mmc_hostname(host->mmc), (unsigned)intmask);
2496                 sdhci_dumpregs(host);
2497
2498                 return;
2499         }
2500
2501         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2502                 host->data->error = -ETIMEDOUT;
2503         else if (intmask & SDHCI_INT_DATA_END_BIT)
2504                 host->data->error = -EILSEQ;
2505         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2506                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2507                         != MMC_BUS_TEST_R)
2508                 host->data->error = -EILSEQ;
2509         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2510                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2511                 sdhci_adma_show_error(host);
2512                 host->data->error = -EIO;
2513                 if (host->ops->adma_workaround)
2514                         host->ops->adma_workaround(host, intmask);
2515         }
2516
2517         if (host->data->error)
2518                 sdhci_finish_data(host);
2519         else {
2520                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2521                         sdhci_transfer_pio(host);
2522
2523                 /*
2524                  * We currently don't do anything fancy with DMA
2525                  * boundaries, but as we can't disable the feature
2526                  * we need to at least restart the transfer.
2527                  *
2528                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2529                  * should return a valid address to continue from, but as
2530                  * some controllers are faulty, don't trust them.
2531                  */
2532                 if (intmask & SDHCI_INT_DMA_END) {
2533                         u32 dmastart, dmanow;
2534                         dmastart = sg_dma_address(host->data->sg);
2535                         dmanow = dmastart + host->data->bytes_xfered;
2536                         /*
2537                          * Force update to the next DMA block boundary.
2538                          */
2539                         dmanow = (dmanow &
2540                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2541                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2542                         host->data->bytes_xfered = dmanow - dmastart;
2543                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2544                                 " next 0x%08x\n",
2545                                 mmc_hostname(host->mmc), dmastart,
2546                                 host->data->bytes_xfered, dmanow);
2547                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2548                 }
2549
2550                 if (intmask & SDHCI_INT_DATA_END) {
2551                         if (host->cmd) {
2552                                 /*
2553                                  * Data managed to finish before the
2554                                  * command completed. Make sure we do
2555                                  * things in the proper order.
2556                                  */
2557                                 host->data_early = 1;
2558                         } else {
2559                                 sdhci_finish_data(host);
2560                         }
2561                 }
2562         }
2563 }
2564
2565 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2566 {
2567         irqreturn_t result = IRQ_NONE;
2568         struct sdhci_host *host = dev_id;
2569         u32 intmask, mask, unexpected = 0;
2570         int max_loops = 16;
2571
2572         spin_lock(&host->lock);
2573
2574         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2575                 spin_unlock(&host->lock);
2576                 return IRQ_NONE;
2577         }
2578
2579         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2580         if (!intmask || intmask == 0xffffffff) {
2581                 result = IRQ_NONE;
2582                 goto out;
2583         }
2584
2585         do {
2586                 /* Clear selected interrupts. */
2587                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2588                                   SDHCI_INT_BUS_POWER);
2589                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2590
2591                 DBG("*** %s got interrupt: 0x%08x\n",
2592                         mmc_hostname(host->mmc), intmask);
2593
2594                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2595                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2596                                       SDHCI_CARD_PRESENT;
2597
2598                         /*
2599                          * There is a observation on i.mx esdhc.  INSERT
2600                          * bit will be immediately set again when it gets
2601                          * cleared, if a card is inserted.  We have to mask
2602                          * the irq to prevent interrupt storm which will
2603                          * freeze the system.  And the REMOVE gets the
2604                          * same situation.
2605                          *
2606                          * More testing are needed here to ensure it works
2607                          * for other platforms though.
2608                          */
2609                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2610                                        SDHCI_INT_CARD_REMOVE);
2611                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2612                                                SDHCI_INT_CARD_INSERT;
2613                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2614                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2615
2616                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2617                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2618
2619                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2620                                                        SDHCI_INT_CARD_REMOVE);
2621                         result = IRQ_WAKE_THREAD;
2622                 }
2623
2624                 if (intmask & SDHCI_INT_CMD_MASK)
2625                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2626                                       &intmask);
2627
2628                 if (intmask & SDHCI_INT_DATA_MASK)
2629                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2630
2631                 if (intmask & SDHCI_INT_BUS_POWER)
2632                         pr_err("%s: Card is consuming too much power!\n",
2633                                 mmc_hostname(host->mmc));
2634
2635                 if (intmask & SDHCI_INT_CARD_INT) {
2636                         sdhci_enable_sdio_irq_nolock(host, false);
2637                         host->thread_isr |= SDHCI_INT_CARD_INT;
2638                         result = IRQ_WAKE_THREAD;
2639                 }
2640
2641                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2642                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2643                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2644                              SDHCI_INT_CARD_INT);
2645
2646                 if (intmask) {
2647                         unexpected |= intmask;
2648                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2649                 }
2650
2651                 if (result == IRQ_NONE)
2652                         result = IRQ_HANDLED;
2653
2654                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2655         } while (intmask && --max_loops);
2656 out:
2657         spin_unlock(&host->lock);
2658
2659         if (unexpected) {
2660                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2661                            mmc_hostname(host->mmc), unexpected);
2662                 sdhci_dumpregs(host);
2663         }
2664
2665         return result;
2666 }
2667
2668 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2669 {
2670         struct sdhci_host *host = dev_id;
2671         unsigned long flags;
2672         u32 isr;
2673
2674         spin_lock_irqsave(&host->lock, flags);
2675         isr = host->thread_isr;
2676         host->thread_isr = 0;
2677         spin_unlock_irqrestore(&host->lock, flags);
2678
2679         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2680                 sdhci_card_event(host->mmc);
2681                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2682         }
2683
2684         if (isr & SDHCI_INT_CARD_INT) {
2685                 sdio_run_irqs(host->mmc);
2686
2687                 spin_lock_irqsave(&host->lock, flags);
2688                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2689                         sdhci_enable_sdio_irq_nolock(host, true);
2690                 spin_unlock_irqrestore(&host->lock, flags);
2691         }
2692
2693         return isr ? IRQ_HANDLED : IRQ_NONE;
2694 }
2695
2696 /*****************************************************************************\
2697  *                                                                           *
2698  * Suspend/resume                                                            *
2699  *                                                                           *
2700 \*****************************************************************************/
2701
2702 #ifdef CONFIG_PM
2703 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2704 {
2705         u8 val;
2706         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2707                         | SDHCI_WAKE_ON_INT;
2708
2709         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2710         val |= mask ;
2711         /* Avoid fake wake up */
2712         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2713                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2714         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2715 }
2716 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2717
2718 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2719 {
2720         u8 val;
2721         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2722                         | SDHCI_WAKE_ON_INT;
2723
2724         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2725         val &= ~mask;
2726         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2727 }
2728
2729 int sdhci_suspend_host(struct sdhci_host *host)
2730 {
2731         sdhci_disable_card_detection(host);
2732
2733         /* Disable tuning since we are suspending */
2734         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2735                 del_timer_sync(&host->tuning_timer);
2736                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2737         }
2738
2739         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2740                 host->ier = 0;
2741                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2742                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2743                 free_irq(host->irq, host);
2744         } else {
2745                 sdhci_enable_irq_wakeups(host);
2746                 enable_irq_wake(host->irq);
2747         }
2748         return 0;
2749 }
2750
2751 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2752
2753 int sdhci_resume_host(struct sdhci_host *host)
2754 {
2755         int ret = 0;
2756
2757         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2758                 if (host->ops->enable_dma)
2759                         host->ops->enable_dma(host);
2760         }
2761
2762         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2763                 ret = request_threaded_irq(host->irq, sdhci_irq,
2764                                            sdhci_thread_irq, IRQF_SHARED,
2765                                            mmc_hostname(host->mmc), host);
2766                 if (ret)
2767                         return ret;
2768         } else {
2769                 sdhci_disable_irq_wakeups(host);
2770                 disable_irq_wake(host->irq);
2771         }
2772
2773         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2774             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2775                 /* Card keeps power but host controller does not */
2776                 sdhci_init(host, 0);
2777                 host->pwr = 0;
2778                 host->clock = 0;
2779                 sdhci_do_set_ios(host, &host->mmc->ios);
2780         } else {
2781                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2782                 mmiowb();
2783         }
2784
2785         sdhci_enable_card_detection(host);
2786
2787         /* Set the re-tuning expiration flag */
2788         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2789                 host->flags |= SDHCI_NEEDS_RETUNING;
2790
2791         return ret;
2792 }
2793
2794 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2795
2796 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2797 {
2798         return pm_runtime_get_sync(host->mmc->parent);
2799 }
2800
2801 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2802 {
2803         pm_runtime_mark_last_busy(host->mmc->parent);
2804         return pm_runtime_put_autosuspend(host->mmc->parent);
2805 }
2806
2807 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2808 {
2809         if (host->runtime_suspended || host->bus_on)
2810                 return;
2811         host->bus_on = true;
2812         pm_runtime_get_noresume(host->mmc->parent);
2813 }
2814
2815 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2816 {
2817         if (host->runtime_suspended || !host->bus_on)
2818                 return;
2819         host->bus_on = false;
2820         pm_runtime_put_noidle(host->mmc->parent);
2821 }
2822
2823 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2824 {
2825         unsigned long flags;
2826
2827         /* Disable tuning since we are suspending */
2828         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2829                 del_timer_sync(&host->tuning_timer);
2830                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2831         }
2832
2833         spin_lock_irqsave(&host->lock, flags);
2834         host->ier &= SDHCI_INT_CARD_INT;
2835         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2836         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2837         spin_unlock_irqrestore(&host->lock, flags);
2838
2839         synchronize_hardirq(host->irq);
2840
2841         spin_lock_irqsave(&host->lock, flags);
2842         host->runtime_suspended = true;
2843         spin_unlock_irqrestore(&host->lock, flags);
2844
2845         return 0;
2846 }
2847 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2848
2849 int sdhci_runtime_resume_host(struct sdhci_host *host)
2850 {
2851         unsigned long flags;
2852         int host_flags = host->flags;
2853
2854         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2855                 if (host->ops->enable_dma)
2856                         host->ops->enable_dma(host);
2857         }
2858
2859         sdhci_init(host, 0);
2860
2861         /* Force clock and power re-program */
2862         host->pwr = 0;
2863         host->clock = 0;
2864         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2865         sdhci_do_set_ios(host, &host->mmc->ios);
2866
2867         if ((host_flags & SDHCI_PV_ENABLED) &&
2868                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2869                 spin_lock_irqsave(&host->lock, flags);
2870                 sdhci_enable_preset_value(host, true);
2871                 spin_unlock_irqrestore(&host->lock, flags);
2872         }
2873
2874         /* Set the re-tuning expiration flag */
2875         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2876                 host->flags |= SDHCI_NEEDS_RETUNING;
2877
2878         spin_lock_irqsave(&host->lock, flags);
2879
2880         host->runtime_suspended = false;
2881
2882         /* Enable SDIO IRQ */
2883         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2884                 sdhci_enable_sdio_irq_nolock(host, true);
2885
2886         /* Enable Card Detection */
2887         sdhci_enable_card_detection(host);
2888
2889         spin_unlock_irqrestore(&host->lock, flags);
2890
2891         return 0;
2892 }
2893 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2894
2895 #endif /* CONFIG_PM */
2896
2897 /*****************************************************************************\
2898  *                                                                           *
2899  * Device allocation/registration                                            *
2900  *                                                                           *
2901 \*****************************************************************************/
2902
2903 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2904         size_t priv_size)
2905 {
2906         struct mmc_host *mmc;
2907         struct sdhci_host *host;
2908
2909         WARN_ON(dev == NULL);
2910
2911         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2912         if (!mmc)
2913                 return ERR_PTR(-ENOMEM);
2914
2915         host = mmc_priv(mmc);
2916         host->mmc = mmc;
2917
2918         return host;
2919 }
2920
2921 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2922
2923 int sdhci_add_host(struct sdhci_host *host)
2924 {
2925         struct mmc_host *mmc;
2926         u32 caps[2] = {0, 0};
2927         u32 max_current_caps;
2928         unsigned int ocr_avail;
2929         unsigned int override_timeout_clk;
2930         int ret;
2931
2932         WARN_ON(host == NULL);
2933         if (host == NULL)
2934                 return -EINVAL;
2935
2936         mmc = host->mmc;
2937
2938         if (debug_quirks)
2939                 host->quirks = debug_quirks;
2940         if (debug_quirks2)
2941                 host->quirks2 = debug_quirks2;
2942
2943         override_timeout_clk = host->timeout_clk;
2944
2945         sdhci_do_reset(host, SDHCI_RESET_ALL);
2946
2947         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2948         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2949                                 >> SDHCI_SPEC_VER_SHIFT;
2950         if (host->version > SDHCI_SPEC_300) {
2951                 pr_err("%s: Unknown controller version (%d). "
2952                         "You may experience problems.\n", mmc_hostname(mmc),
2953                         host->version);
2954         }
2955
2956         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2957                 sdhci_readl(host, SDHCI_CAPABILITIES);
2958
2959         if (host->version >= SDHCI_SPEC_300)
2960                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2961                         host->caps1 :
2962                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2963
2964         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2965                 host->flags |= SDHCI_USE_SDMA;
2966         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2967                 DBG("Controller doesn't have SDMA capability\n");
2968         else
2969                 host->flags |= SDHCI_USE_SDMA;
2970
2971         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2972                 (host->flags & SDHCI_USE_SDMA)) {
2973                 DBG("Disabling DMA as it is marked broken\n");
2974                 host->flags &= ~SDHCI_USE_SDMA;
2975         }
2976
2977         if ((host->version >= SDHCI_SPEC_200) &&
2978                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2979                 host->flags |= SDHCI_USE_ADMA;
2980
2981         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2982                 (host->flags & SDHCI_USE_ADMA)) {
2983                 DBG("Disabling ADMA as it is marked broken\n");
2984                 host->flags &= ~SDHCI_USE_ADMA;
2985         }
2986
2987         /*
2988          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2989          * and *must* do 64-bit DMA.  A driver has the opportunity to change
2990          * that during the first call to ->enable_dma().  Similarly
2991          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2992          * implement.
2993          */
2994         if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2995                 host->flags |= SDHCI_USE_64_BIT_DMA;
2996
2997         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2998                 if (host->ops->enable_dma) {
2999                         if (host->ops->enable_dma(host)) {
3000                                 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3001                                         mmc_hostname(mmc));
3002                                 host->flags &=
3003                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3004                         }
3005                 }
3006         }
3007
3008         /* SDMA does not support 64-bit DMA */
3009         if (host->flags & SDHCI_USE_64_BIT_DMA)
3010                 host->flags &= ~SDHCI_USE_SDMA;
3011
3012         if (host->flags & SDHCI_USE_ADMA) {
3013                 /*
3014                  * The DMA descriptor table size is calculated as the maximum
3015                  * number of segments times 2, to allow for an alignment
3016                  * descriptor for each segment, plus 1 for a nop end descriptor,
3017                  * all multipled by the descriptor size.
3018                  */
3019                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3020                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3021                                               SDHCI_ADMA2_64_DESC_SZ;
3022                         host->align_buffer_sz = SDHCI_MAX_SEGS *
3023                                                 SDHCI_ADMA2_64_ALIGN;
3024                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3025                         host->align_sz = SDHCI_ADMA2_64_ALIGN;
3026                         host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
3027                 } else {
3028                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3029                                               SDHCI_ADMA2_32_DESC_SZ;
3030                         host->align_buffer_sz = SDHCI_MAX_SEGS *
3031                                                 SDHCI_ADMA2_32_ALIGN;
3032                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3033                         host->align_sz = SDHCI_ADMA2_32_ALIGN;
3034                         host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
3035                 }
3036                 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
3037                                                       host->adma_table_sz,
3038                                                       &host->adma_addr,
3039                                                       GFP_KERNEL);
3040                 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
3041                 if (!host->adma_table || !host->align_buffer) {
3042                         if (host->adma_table)
3043                                 dma_free_coherent(mmc_dev(mmc),
3044                                                   host->adma_table_sz,
3045                                                   host->adma_table,
3046                                                   host->adma_addr);
3047                         kfree(host->align_buffer);
3048                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3049                                 mmc_hostname(mmc));
3050                         host->flags &= ~SDHCI_USE_ADMA;
3051                         host->adma_table = NULL;
3052                         host->align_buffer = NULL;
3053                 } else if (host->adma_addr & host->align_mask) {
3054                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3055                                 mmc_hostname(mmc));
3056                         host->flags &= ~SDHCI_USE_ADMA;
3057                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3058                                           host->adma_table, host->adma_addr);
3059                         kfree(host->align_buffer);
3060                         host->adma_table = NULL;
3061                         host->align_buffer = NULL;
3062                 }
3063         }
3064
3065         /*
3066          * If we use DMA, then it's up to the caller to set the DMA
3067          * mask, but PIO does not need the hw shim so we set a new
3068          * mask here in that case.
3069          */
3070         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3071                 host->dma_mask = DMA_BIT_MASK(64);
3072                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3073         }
3074
3075         if (host->version >= SDHCI_SPEC_300)
3076                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3077                         >> SDHCI_CLOCK_BASE_SHIFT;
3078         else
3079                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3080                         >> SDHCI_CLOCK_BASE_SHIFT;
3081
3082         host->max_clk *= 1000000;
3083         if (host->max_clk == 0 || host->quirks &
3084                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3085                 if (!host->ops->get_max_clock) {
3086                         pr_err("%s: Hardware doesn't specify base clock "
3087                                "frequency.\n", mmc_hostname(mmc));
3088                         return -ENODEV;
3089                 }
3090                 host->max_clk = host->ops->get_max_clock(host);
3091         }
3092
3093         host->next_data.cookie = 1;
3094         /*
3095          * In case of Host Controller v3.00, find out whether clock
3096          * multiplier is supported.
3097          */
3098         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3099                         SDHCI_CLOCK_MUL_SHIFT;
3100
3101         /*
3102          * In case the value in Clock Multiplier is 0, then programmable
3103          * clock mode is not supported, otherwise the actual clock
3104          * multiplier is one more than the value of Clock Multiplier
3105          * in the Capabilities Register.
3106          */
3107         if (host->clk_mul)
3108                 host->clk_mul += 1;
3109
3110         /*
3111          * Set host parameters.
3112          */
3113         mmc->ops = &sdhci_ops;
3114         mmc->f_max = host->max_clk;
3115         if (host->ops->get_min_clock)
3116                 mmc->f_min = host->ops->get_min_clock(host);
3117         else if (host->version >= SDHCI_SPEC_300) {
3118                 if (host->clk_mul) {
3119                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3120                         mmc->f_max = host->max_clk * host->clk_mul;
3121                 } else
3122                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3123         } else
3124                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3125
3126         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3127                 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3128                                         SDHCI_TIMEOUT_CLK_SHIFT;
3129                 if (host->timeout_clk == 0) {
3130                         if (host->ops->get_timeout_clock) {
3131                                 host->timeout_clk =
3132                                         host->ops->get_timeout_clock(host);
3133                         } else {
3134                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3135                                         mmc_hostname(mmc));
3136                                 return -ENODEV;
3137                         }
3138                 }
3139
3140                 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3141                         host->timeout_clk *= 1000;
3142
3143                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3144                         host->ops->get_max_timeout_count(host) : 1 << 27;
3145                 mmc->max_busy_timeout /= host->timeout_clk;
3146         }
3147
3148         if (override_timeout_clk)
3149                 host->timeout_clk = override_timeout_clk;
3150
3151         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3152         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3153
3154         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3155                 host->flags |= SDHCI_AUTO_CMD12;
3156
3157         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3158         if ((host->version >= SDHCI_SPEC_300) &&
3159             ((host->flags & SDHCI_USE_ADMA) ||
3160              !(host->flags & SDHCI_USE_SDMA)) &&
3161              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3162                 host->flags |= SDHCI_AUTO_CMD23;
3163                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3164         } else {
3165                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3166         }
3167
3168         /*
3169          * A controller may support 8-bit width, but the board itself
3170          * might not have the pins brought out.  Boards that support
3171          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3172          * their platform code before calling sdhci_add_host(), and we
3173          * won't assume 8-bit width for hosts without that CAP.
3174          */
3175         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3176                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3177
3178         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3179                 mmc->caps &= ~MMC_CAP_CMD23;
3180
3181         if (caps[0] & SDHCI_CAN_DO_HISPD)
3182                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3183
3184         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3185             !(mmc->caps & MMC_CAP_NONREMOVABLE))
3186                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3187
3188         /* If there are external regulators, get them */
3189         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3190                 return -EPROBE_DEFER;
3191
3192         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3193         if (!IS_ERR(mmc->supply.vqmmc)) {
3194                 ret = regulator_enable(mmc->supply.vqmmc);
3195                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3196                                                     1950000))
3197                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3198                                         SDHCI_SUPPORT_SDR50 |
3199                                         SDHCI_SUPPORT_DDR50);
3200                 if (ret) {
3201                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3202                                 mmc_hostname(mmc), ret);
3203                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3204                 }
3205         }
3206
3207         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3208                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3209                        SDHCI_SUPPORT_DDR50);
3210
3211         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3212         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3213                        SDHCI_SUPPORT_DDR50))
3214                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3215
3216         /* SDR104 supports also implies SDR50 support */
3217         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3218                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3219                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3220                  * field can be promoted to support HS200.
3221                  */
3222                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3223                         mmc->caps2 |= MMC_CAP2_HS200;
3224         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3225                 mmc->caps |= MMC_CAP_UHS_SDR50;
3226
3227         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3228             (caps[1] & SDHCI_SUPPORT_HS400))
3229                 mmc->caps2 |= MMC_CAP2_HS400;
3230
3231         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3232             (IS_ERR(mmc->supply.vqmmc) ||
3233              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3234                                              1300000)))
3235                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3236
3237         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3238                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3239                 mmc->caps |= MMC_CAP_UHS_DDR50;
3240
3241         /* Does the host need tuning for SDR50? */
3242         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3243                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3244
3245         /* Does the host need tuning for SDR104 / HS200? */
3246         if (mmc->caps2 & MMC_CAP2_HS200)
3247                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3248
3249         /* Driver Type(s) (A, C, D) supported by the host */
3250         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3251                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3252         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3253                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3254         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3255                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3256
3257         /* Initial value for re-tuning timer count */
3258         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3259                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3260
3261         /*
3262          * In case Re-tuning Timer is not disabled, the actual value of
3263          * re-tuning timer will be 2 ^ (n - 1).
3264          */
3265         if (host->tuning_count)
3266                 host->tuning_count = 1 << (host->tuning_count - 1);
3267
3268         /* Re-tuning mode supported by the Host Controller */
3269         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3270                              SDHCI_RETUNING_MODE_SHIFT;
3271
3272         ocr_avail = 0;
3273
3274         /*
3275          * According to SD Host Controller spec v3.00, if the Host System
3276          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3277          * the value is meaningful only if Voltage Support in the Capabilities
3278          * register is set. The actual current value is 4 times the register
3279          * value.
3280          */
3281         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3282         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3283                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3284                 if (curr > 0) {
3285
3286                         /* convert to SDHCI_MAX_CURRENT format */
3287                         curr = curr/1000;  /* convert to mA */
3288                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3289
3290                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3291                         max_current_caps =
3292                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3293                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3294                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3295                 }
3296         }
3297
3298         if (caps[0] & SDHCI_CAN_VDD_330) {
3299                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3300
3301                 mmc->max_current_330 = ((max_current_caps &
3302                                    SDHCI_MAX_CURRENT_330_MASK) >>
3303                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3304                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3305         }
3306         if (caps[0] & SDHCI_CAN_VDD_300) {
3307                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3308
3309                 mmc->max_current_300 = ((max_current_caps &
3310                                    SDHCI_MAX_CURRENT_300_MASK) >>
3311                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3312                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3313         }
3314         if (caps[0] & SDHCI_CAN_VDD_180) {
3315                 ocr_avail |= MMC_VDD_165_195;
3316
3317                 mmc->max_current_180 = ((max_current_caps &
3318                                    SDHCI_MAX_CURRENT_180_MASK) >>
3319                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3320                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3321         }
3322
3323         /* If OCR set by host, use it instead. */
3324         if (host->ocr_mask)
3325                 ocr_avail = host->ocr_mask;
3326
3327         /* If OCR set by external regulators, give it highest prio. */
3328         if (mmc->ocr_avail)
3329                 ocr_avail = mmc->ocr_avail;
3330
3331         mmc->ocr_avail = ocr_avail;
3332         mmc->ocr_avail_sdio = ocr_avail;
3333         if (host->ocr_avail_sdio)
3334                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3335         mmc->ocr_avail_sd = ocr_avail;
3336         if (host->ocr_avail_sd)
3337                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3338         else /* normal SD controllers don't support 1.8V */
3339                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3340         mmc->ocr_avail_mmc = ocr_avail;
3341         if (host->ocr_avail_mmc)
3342                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3343
3344         if (mmc->ocr_avail == 0) {
3345                 pr_err("%s: Hardware doesn't report any "
3346                         "support voltages.\n", mmc_hostname(mmc));
3347                 return -ENODEV;
3348         }
3349
3350         spin_lock_init(&host->lock);
3351
3352         /*
3353          * Maximum number of segments. Depends on if the hardware
3354          * can do scatter/gather or not.
3355          */
3356         if (host->flags & SDHCI_USE_ADMA)
3357                 mmc->max_segs = SDHCI_MAX_SEGS;
3358         else if (host->flags & SDHCI_USE_SDMA)
3359                 mmc->max_segs = 1;
3360         else /* PIO */
3361                 mmc->max_segs = SDHCI_MAX_SEGS;
3362
3363         /*
3364          * Maximum number of sectors in one transfer. Limited by SDMA boundary
3365          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3366          * is less anyway.
3367          */
3368         mmc->max_req_size = 524288;
3369
3370         /*
3371          * Maximum segment size. Could be one segment with the maximum number
3372          * of bytes. When doing hardware scatter/gather, each entry cannot
3373          * be larger than 64 KiB though.
3374          */
3375         if (host->flags & SDHCI_USE_ADMA) {
3376                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3377                         mmc->max_seg_size = 65535;
3378                 else
3379                         mmc->max_seg_size = 65536;
3380         } else {
3381                 mmc->max_seg_size = mmc->max_req_size;
3382         }
3383
3384         /*
3385          * Maximum block size. This varies from controller to controller and
3386          * is specified in the capabilities register.
3387          */
3388         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3389                 mmc->max_blk_size = 2;
3390         } else {
3391                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3392                                 SDHCI_MAX_BLOCK_SHIFT;
3393                 if (mmc->max_blk_size >= 3) {
3394                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3395                                 mmc_hostname(mmc));
3396                         mmc->max_blk_size = 0;
3397                 }
3398         }
3399
3400         mmc->max_blk_size = 512 << mmc->max_blk_size;
3401
3402         /*
3403          * Maximum block count.
3404          */
3405         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3406
3407         /*
3408          * Init tasklets.
3409          */
3410         tasklet_init(&host->finish_tasklet,
3411                 sdhci_tasklet_finish, (unsigned long)host);
3412
3413         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3414
3415         init_waitqueue_head(&host->buf_ready_int);
3416
3417         if (host->version >= SDHCI_SPEC_300) {
3418                 /* Initialize re-tuning timer */
3419                 init_timer(&host->tuning_timer);
3420                 host->tuning_timer.data = (unsigned long)host;
3421                 host->tuning_timer.function = sdhci_tuning_timer;
3422         }
3423
3424         sdhci_init(host, 0);
3425
3426         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3427                                    IRQF_SHARED, mmc_hostname(mmc), host);
3428         if (ret) {
3429                 pr_err("%s: Failed to request IRQ %d: %d\n",
3430                        mmc_hostname(mmc), host->irq, ret);
3431                 goto untasklet;
3432         }
3433
3434 #ifdef CONFIG_MMC_DEBUG
3435         sdhci_dumpregs(host);
3436 #endif
3437
3438 #ifdef SDHCI_USE_LEDS_CLASS
3439         snprintf(host->led_name, sizeof(host->led_name),
3440                 "%s::", mmc_hostname(mmc));
3441         host->led.name = host->led_name;
3442         host->led.brightness = LED_OFF;
3443         host->led.default_trigger = mmc_hostname(mmc);
3444         host->led.brightness_set = sdhci_led_control;
3445
3446         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3447         if (ret) {
3448                 pr_err("%s: Failed to register LED device: %d\n",
3449                        mmc_hostname(mmc), ret);
3450                 goto reset;
3451         }
3452 #endif
3453
3454         mmiowb();
3455
3456         mmc_add_host(mmc);
3457
3458         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3459                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3460                 (host->flags & SDHCI_USE_ADMA) ?
3461                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3462                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3463
3464         sdhci_enable_card_detection(host);
3465
3466         return 0;
3467
3468 #ifdef SDHCI_USE_LEDS_CLASS
3469 reset:
3470         sdhci_do_reset(host, SDHCI_RESET_ALL);
3471         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3472         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3473         free_irq(host->irq, host);
3474 #endif
3475 untasklet:
3476         tasklet_kill(&host->finish_tasklet);
3477
3478         return ret;
3479 }
3480
3481 EXPORT_SYMBOL_GPL(sdhci_add_host);
3482
3483 void sdhci_remove_host(struct sdhci_host *host, int dead)
3484 {
3485         struct mmc_host *mmc = host->mmc;
3486         unsigned long flags;
3487
3488         if (dead) {
3489                 spin_lock_irqsave(&host->lock, flags);
3490
3491                 host->flags |= SDHCI_DEVICE_DEAD;
3492
3493                 if (host->mrq) {
3494                         pr_err("%s: Controller removed during "
3495                                 " transfer!\n", mmc_hostname(mmc));
3496
3497                         host->mrq->cmd->error = -ENOMEDIUM;
3498                         tasklet_schedule(&host->finish_tasklet);
3499                 }
3500
3501                 spin_unlock_irqrestore(&host->lock, flags);
3502         }
3503
3504         sdhci_disable_card_detection(host);
3505
3506         mmc_remove_host(mmc);
3507
3508 #ifdef SDHCI_USE_LEDS_CLASS
3509         led_classdev_unregister(&host->led);
3510 #endif
3511
3512         if (!dead)
3513                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3514
3515         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3516         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3517         free_irq(host->irq, host);
3518
3519         del_timer_sync(&host->timer);
3520
3521         tasklet_kill(&host->finish_tasklet);
3522
3523         if (!IS_ERR(mmc->supply.vqmmc))
3524                 regulator_disable(mmc->supply.vqmmc);
3525
3526         if (host->adma_table)
3527                 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3528                                   host->adma_table, host->adma_addr);
3529         kfree(host->align_buffer);
3530
3531         host->adma_table = NULL;
3532         host->align_buffer = NULL;
3533 }
3534
3535 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3536
3537 void sdhci_free_host(struct sdhci_host *host)
3538 {
3539         mmc_free_host(host->mmc);
3540 }
3541
3542 EXPORT_SYMBOL_GPL(sdhci_free_host);
3543
3544 /*****************************************************************************\
3545  *                                                                           *
3546  * Driver init/exit                                                          *
3547  *                                                                           *
3548 \*****************************************************************************/
3549
3550 static int __init sdhci_drv_init(void)
3551 {
3552         pr_info(DRIVER_NAME
3553                 ": Secure Digital Host Controller Interface driver\n");
3554         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3555
3556         return 0;
3557 }
3558
3559 static void __exit sdhci_drv_exit(void)
3560 {
3561 }
3562
3563 module_init(sdhci_drv_init);
3564 module_exit(sdhci_drv_exit);
3565
3566 module_param(debug_quirks, uint, 0444);
3567 module_param(debug_quirks2, uint, 0444);
3568
3569 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3570 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3571 MODULE_LICENSE("GPL");
3572
3573 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3574 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");