1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
10 * Thanks to the following companies for their support:
12 * - JMicron (hardware and technical support)
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/scatterlist.h>
25 #include <linux/gpio.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/mmc/sdhci-pci-data.h>
31 #include "sdhci-pci.h"
32 #include "sdhci-pci-o2micro.h"
34 /*****************************************************************************\
36 * Hardware specific quirk handling *
38 \*****************************************************************************/
40 static int ricoh_probe(struct sdhci_pci_chip *chip)
42 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
43 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
44 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
48 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
51 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
52 & SDHCI_TIMEOUT_CLK_MASK) |
54 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
55 & SDHCI_CLOCK_BASE_MASK) |
57 SDHCI_TIMEOUT_CLK_UNIT |
64 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
66 /* Apply a delay to allow controller to settle */
67 /* Otherwise it becomes confused if card state changed
73 static const struct sdhci_pci_fixes sdhci_ricoh = {
75 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
76 SDHCI_QUIRK_FORCE_DMA |
77 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
80 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
81 .probe_slot = ricoh_mmc_probe_slot,
82 .resume = ricoh_mmc_resume,
83 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
84 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
85 SDHCI_QUIRK_NO_CARD_NO_RESET |
86 SDHCI_QUIRK_MISSING_CAPS
89 static const struct sdhci_pci_fixes sdhci_ene_712 = {
90 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
91 SDHCI_QUIRK_BROKEN_DMA,
94 static const struct sdhci_pci_fixes sdhci_ene_714 = {
95 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
96 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
97 SDHCI_QUIRK_BROKEN_DMA,
100 static const struct sdhci_pci_fixes sdhci_cafe = {
101 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
102 SDHCI_QUIRK_NO_BUSY_IRQ |
103 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
104 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
107 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
108 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
111 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
113 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
118 * ADMA operation is disabled for Moorestown platform due to
121 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
124 * slots number is fixed here for MRST as SDIO3/5 are never used and
125 * have hardware bugs.
131 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
133 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
139 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
141 struct sdhci_pci_slot *slot = dev_id;
142 struct sdhci_host *host = slot->host;
144 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
148 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
150 int err, irq, gpio = slot->cd_gpio;
152 slot->cd_gpio = -EINVAL;
153 slot->cd_irq = -EINVAL;
155 if (!gpio_is_valid(gpio))
158 err = gpio_request(gpio, "sd_cd");
162 err = gpio_direction_input(gpio);
166 irq = gpio_to_irq(gpio);
170 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
171 IRQF_TRIGGER_FALLING, "sd_cd", slot);
175 slot->cd_gpio = gpio;
183 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
186 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
188 if (slot->cd_irq >= 0)
189 free_irq(slot->cd_irq, slot);
190 if (gpio_is_valid(slot->cd_gpio))
191 gpio_free(slot->cd_gpio);
196 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
200 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
206 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
208 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
209 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
210 MMC_CAP2_HC_ERASE_SZ;
214 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
216 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
220 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
221 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
222 .probe_slot = mrst_hc_probe_slot,
225 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
226 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
227 .probe = mrst_hc_probe,
230 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
231 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
232 .allow_runtime_pm = true,
233 .own_cd_for_runtime_pm = true,
236 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
237 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
238 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
239 .allow_runtime_pm = true,
240 .probe_slot = mfd_sdio_probe_slot,
243 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
244 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
245 .allow_runtime_pm = true,
246 .probe_slot = mfd_emmc_probe_slot,
249 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
250 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
251 .probe_slot = pch_hc_probe_slot,
254 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
258 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
260 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
261 /* For eMMC, minimum is 1us but give it 9us for good measure */
264 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
265 /* For eMMC, minimum is 200us but give it 300us for good measure */
266 usleep_range(300, 1000);
269 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
271 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
272 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
273 MMC_CAP_BUS_WIDTH_TEST |
274 MMC_CAP_WAIT_WHILE_BUSY;
275 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
276 slot->hw_reset = sdhci_pci_int_hw_reset;
277 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
278 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
282 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
284 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
285 MMC_CAP_BUS_WIDTH_TEST |
286 MMC_CAP_WAIT_WHILE_BUSY;
290 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
292 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
293 MMC_CAP_WAIT_WHILE_BUSY;
294 slot->cd_con_id = NULL;
296 slot->cd_override_level = true;
300 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
301 .allow_runtime_pm = true,
302 .probe_slot = byt_emmc_probe_slot,
303 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
304 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
305 SDHCI_QUIRK2_STOP_WITH_TC,
308 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
309 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
310 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
311 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
312 .allow_runtime_pm = true,
313 .probe_slot = byt_sdio_probe_slot,
316 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
317 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
318 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
319 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
320 SDHCI_QUIRK2_STOP_WITH_TC,
321 .allow_runtime_pm = true,
322 .own_cd_for_runtime_pm = true,
323 .probe_slot = byt_sd_probe_slot,
326 /* Define Host controllers for Intel Merrifield platform */
327 #define INTEL_MRFL_EMMC_0 0
328 #define INTEL_MRFL_EMMC_1 1
330 static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
332 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
333 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
334 /* SD support is not ready yet */
337 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
343 static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
344 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
345 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
346 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
347 .allow_runtime_pm = true,
348 .probe_slot = intel_mrfl_mmc_probe_slot,
351 /* O2Micro extra registers */
352 #define O2_SD_LOCK_WP 0xD3
353 #define O2_SD_MULTI_VCC3V 0xEE
354 #define O2_SD_CLKREQ 0xEC
355 #define O2_SD_CAPS 0xE0
356 #define O2_SD_ADMA1 0xE2
357 #define O2_SD_ADMA2 0xE7
358 #define O2_SD_INF_MOD 0xF1
360 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
365 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
370 * Turn PMOS on [bit 0], set over current detection to 2.4 V
371 * [bit 1:2] and enable over current debouncing [bit 6].
378 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
385 static int jmicron_probe(struct sdhci_pci_chip *chip)
390 if (chip->pdev->revision == 0) {
391 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
392 SDHCI_QUIRK_32BIT_DMA_SIZE |
393 SDHCI_QUIRK_32BIT_ADMA_SIZE |
394 SDHCI_QUIRK_RESET_AFTER_REQUEST |
395 SDHCI_QUIRK_BROKEN_SMALL_PIO;
399 * JMicron chips can have two interfaces to the same hardware
400 * in order to work around limitations in Microsoft's driver.
401 * We need to make sure we only bind to one of them.
403 * This code assumes two things:
405 * 1. The PCI code adds subfunctions in order.
407 * 2. The MMC interface has a lower subfunction number
408 * than the SD interface.
410 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
411 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
412 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
413 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
416 struct pci_dev *sd_dev;
419 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
420 mmcdev, sd_dev)) != NULL) {
421 if ((PCI_SLOT(chip->pdev->devfn) ==
422 PCI_SLOT(sd_dev->devfn)) &&
423 (chip->pdev->bus == sd_dev->bus))
429 dev_info(&chip->pdev->dev, "Refusing to bind to "
430 "secondary interface.\n");
436 * JMicron chips need a bit of a nudge to enable the power
439 ret = jmicron_pmos(chip, 1);
441 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
445 /* quirk for unsable RO-detection on JM388 chips */
446 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
447 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
448 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
453 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
457 scratch = readb(host->ioaddr + 0xC0);
464 writeb(scratch, host->ioaddr + 0xC0);
467 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
469 if (slot->chip->pdev->revision == 0) {
472 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
473 version = (version & SDHCI_VENDOR_VER_MASK) >>
474 SDHCI_VENDOR_VER_SHIFT;
477 * Older versions of the chip have lots of nasty glitches
478 * in the ADMA engine. It's best just to avoid it
482 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
485 /* JM388 MMC doesn't support 1.8V while SD supports it */
486 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
487 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
488 MMC_VDD_29_30 | MMC_VDD_30_31 |
489 MMC_VDD_165_195; /* allow 1.8V */
490 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
491 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
495 * The secondary interface requires a bit set to get the
498 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
499 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
500 jmicron_enable_mmc(slot->host, 1);
502 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
507 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
512 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
513 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
514 jmicron_enable_mmc(slot->host, 0);
517 static int jmicron_suspend(struct sdhci_pci_chip *chip)
521 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
522 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
523 for (i = 0; i < chip->num_slots; i++)
524 jmicron_enable_mmc(chip->slots[i]->host, 0);
530 static int jmicron_resume(struct sdhci_pci_chip *chip)
534 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
535 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
536 for (i = 0; i < chip->num_slots; i++)
537 jmicron_enable_mmc(chip->slots[i]->host, 1);
540 ret = jmicron_pmos(chip, 1);
542 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
549 static const struct sdhci_pci_fixes sdhci_o2 = {
550 .probe = sdhci_pci_o2_probe,
551 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
552 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
553 .probe_slot = sdhci_pci_o2_probe_slot,
554 .resume = sdhci_pci_o2_resume,
557 static const struct sdhci_pci_fixes sdhci_jmicron = {
558 .probe = jmicron_probe,
560 .probe_slot = jmicron_probe_slot,
561 .remove_slot = jmicron_remove_slot,
563 .suspend = jmicron_suspend,
564 .resume = jmicron_resume,
567 /* SysKonnect CardBus2SDIO extra registers */
568 #define SYSKT_CTRL 0x200
569 #define SYSKT_RDFIFO_STAT 0x204
570 #define SYSKT_WRFIFO_STAT 0x208
571 #define SYSKT_POWER_DATA 0x20c
572 #define SYSKT_POWER_330 0xef
573 #define SYSKT_POWER_300 0xf8
574 #define SYSKT_POWER_184 0xcc
575 #define SYSKT_POWER_CMD 0x20d
576 #define SYSKT_POWER_START (1 << 7)
577 #define SYSKT_POWER_STATUS 0x20e
578 #define SYSKT_POWER_STATUS_OK (1 << 0)
579 #define SYSKT_BOARD_REV 0x210
580 #define SYSKT_CHIP_REV 0x211
581 #define SYSKT_CONF_DATA 0x212
582 #define SYSKT_CONF_DATA_1V8 (1 << 2)
583 #define SYSKT_CONF_DATA_2V5 (1 << 1)
584 #define SYSKT_CONF_DATA_3V3 (1 << 0)
586 static int syskt_probe(struct sdhci_pci_chip *chip)
588 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
589 chip->pdev->class &= ~0x0000FF;
590 chip->pdev->class |= PCI_SDHCI_IFDMA;
595 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
599 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
600 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
601 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
602 "board rev %d.%d, chip rev %d.%d\n",
603 board_rev >> 4, board_rev & 0xf,
604 chip_rev >> 4, chip_rev & 0xf);
605 if (chip_rev >= 0x20)
606 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
608 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
609 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
611 tm = 10; /* Wait max 1 ms */
613 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
614 if (ps & SYSKT_POWER_STATUS_OK)
619 dev_err(&slot->chip->pdev->dev,
620 "power regulator never stabilized");
621 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
628 static const struct sdhci_pci_fixes sdhci_syskt = {
629 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
630 .probe = syskt_probe,
631 .probe_slot = syskt_probe_slot,
634 static int via_probe(struct sdhci_pci_chip *chip)
636 if (chip->pdev->revision == 0x10)
637 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
642 static const struct sdhci_pci_fixes sdhci_via = {
646 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
648 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
652 static const struct sdhci_pci_fixes sdhci_rtsx = {
653 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
654 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
655 SDHCI_QUIRK2_BROKEN_DDR50,
656 .probe_slot = rtsx_probe_slot,
659 static int amd_probe(struct sdhci_pci_chip *chip)
661 struct pci_dev *smbus_dev;
663 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
664 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
666 if (smbus_dev && (smbus_dev->revision < 0x51)) {
667 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
668 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
674 static const struct sdhci_pci_fixes sdhci_amd = {
678 static const struct pci_device_id pci_ids[] = {
680 .vendor = PCI_VENDOR_ID_RICOH,
681 .device = PCI_DEVICE_ID_RICOH_R5C822,
682 .subvendor = PCI_ANY_ID,
683 .subdevice = PCI_ANY_ID,
684 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
688 .vendor = PCI_VENDOR_ID_RICOH,
690 .subvendor = PCI_ANY_ID,
691 .subdevice = PCI_ANY_ID,
692 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
696 .vendor = PCI_VENDOR_ID_RICOH,
698 .subvendor = PCI_ANY_ID,
699 .subdevice = PCI_ANY_ID,
700 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
704 .vendor = PCI_VENDOR_ID_RICOH,
706 .subvendor = PCI_ANY_ID,
707 .subdevice = PCI_ANY_ID,
708 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
712 .vendor = PCI_VENDOR_ID_ENE,
713 .device = PCI_DEVICE_ID_ENE_CB712_SD,
714 .subvendor = PCI_ANY_ID,
715 .subdevice = PCI_ANY_ID,
716 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
720 .vendor = PCI_VENDOR_ID_ENE,
721 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
722 .subvendor = PCI_ANY_ID,
723 .subdevice = PCI_ANY_ID,
724 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
728 .vendor = PCI_VENDOR_ID_ENE,
729 .device = PCI_DEVICE_ID_ENE_CB714_SD,
730 .subvendor = PCI_ANY_ID,
731 .subdevice = PCI_ANY_ID,
732 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
736 .vendor = PCI_VENDOR_ID_ENE,
737 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
738 .subvendor = PCI_ANY_ID,
739 .subdevice = PCI_ANY_ID,
740 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
744 .vendor = PCI_VENDOR_ID_MARVELL,
745 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
746 .subvendor = PCI_ANY_ID,
747 .subdevice = PCI_ANY_ID,
748 .driver_data = (kernel_ulong_t)&sdhci_cafe,
752 .vendor = PCI_VENDOR_ID_JMICRON,
753 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
754 .subvendor = PCI_ANY_ID,
755 .subdevice = PCI_ANY_ID,
756 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
760 .vendor = PCI_VENDOR_ID_JMICRON,
761 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
762 .subvendor = PCI_ANY_ID,
763 .subdevice = PCI_ANY_ID,
764 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
768 .vendor = PCI_VENDOR_ID_JMICRON,
769 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
770 .subvendor = PCI_ANY_ID,
771 .subdevice = PCI_ANY_ID,
772 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
776 .vendor = PCI_VENDOR_ID_JMICRON,
777 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
778 .subvendor = PCI_ANY_ID,
779 .subdevice = PCI_ANY_ID,
780 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
784 .vendor = PCI_VENDOR_ID_SYSKONNECT,
786 .subvendor = PCI_ANY_ID,
787 .subdevice = PCI_ANY_ID,
788 .driver_data = (kernel_ulong_t)&sdhci_syskt,
792 .vendor = PCI_VENDOR_ID_VIA,
794 .subvendor = PCI_ANY_ID,
795 .subdevice = PCI_ANY_ID,
796 .driver_data = (kernel_ulong_t)&sdhci_via,
800 .vendor = PCI_VENDOR_ID_REALTEK,
802 .subvendor = PCI_ANY_ID,
803 .subdevice = PCI_ANY_ID,
804 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
808 .vendor = PCI_VENDOR_ID_INTEL,
809 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
810 .subvendor = PCI_ANY_ID,
811 .subdevice = PCI_ANY_ID,
812 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
816 .vendor = PCI_VENDOR_ID_INTEL,
817 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
818 .subvendor = PCI_ANY_ID,
819 .subdevice = PCI_ANY_ID,
820 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
824 .vendor = PCI_VENDOR_ID_INTEL,
825 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
826 .subvendor = PCI_ANY_ID,
827 .subdevice = PCI_ANY_ID,
828 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
832 .vendor = PCI_VENDOR_ID_INTEL,
833 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
834 .subvendor = PCI_ANY_ID,
835 .subdevice = PCI_ANY_ID,
836 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
840 .vendor = PCI_VENDOR_ID_INTEL,
841 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
842 .subvendor = PCI_ANY_ID,
843 .subdevice = PCI_ANY_ID,
844 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
848 .vendor = PCI_VENDOR_ID_INTEL,
849 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
850 .subvendor = PCI_ANY_ID,
851 .subdevice = PCI_ANY_ID,
852 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
856 .vendor = PCI_VENDOR_ID_INTEL,
857 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
858 .subvendor = PCI_ANY_ID,
859 .subdevice = PCI_ANY_ID,
860 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
864 .vendor = PCI_VENDOR_ID_INTEL,
865 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
866 .subvendor = PCI_ANY_ID,
867 .subdevice = PCI_ANY_ID,
868 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
872 .vendor = PCI_VENDOR_ID_INTEL,
873 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
874 .subvendor = PCI_ANY_ID,
875 .subdevice = PCI_ANY_ID,
876 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
880 .vendor = PCI_VENDOR_ID_INTEL,
881 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
882 .subvendor = PCI_ANY_ID,
883 .subdevice = PCI_ANY_ID,
884 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
888 .vendor = PCI_VENDOR_ID_INTEL,
889 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
890 .subvendor = PCI_ANY_ID,
891 .subdevice = PCI_ANY_ID,
892 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
896 .vendor = PCI_VENDOR_ID_INTEL,
897 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
898 .subvendor = PCI_ANY_ID,
899 .subdevice = PCI_ANY_ID,
900 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
904 .vendor = PCI_VENDOR_ID_INTEL,
905 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
906 .subvendor = PCI_ANY_ID,
907 .subdevice = PCI_ANY_ID,
908 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
912 .vendor = PCI_VENDOR_ID_INTEL,
913 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
914 .subvendor = PCI_ANY_ID,
915 .subdevice = PCI_ANY_ID,
916 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
920 .vendor = PCI_VENDOR_ID_INTEL,
921 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
922 .subvendor = PCI_ANY_ID,
923 .subdevice = PCI_ANY_ID,
924 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
928 .vendor = PCI_VENDOR_ID_INTEL,
929 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
930 .subvendor = PCI_ANY_ID,
931 .subdevice = PCI_ANY_ID,
932 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
936 .vendor = PCI_VENDOR_ID_INTEL,
937 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
938 .subvendor = PCI_ANY_ID,
939 .subdevice = PCI_ANY_ID,
940 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
944 .vendor = PCI_VENDOR_ID_INTEL,
945 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
946 .subvendor = PCI_ANY_ID,
947 .subdevice = PCI_ANY_ID,
948 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
952 .vendor = PCI_VENDOR_ID_INTEL,
953 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
954 .subvendor = PCI_ANY_ID,
955 .subdevice = PCI_ANY_ID,
956 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
960 .vendor = PCI_VENDOR_ID_INTEL,
961 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
962 .subvendor = PCI_ANY_ID,
963 .subdevice = PCI_ANY_ID,
964 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
968 .vendor = PCI_VENDOR_ID_INTEL,
969 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
970 .subvendor = PCI_ANY_ID,
971 .subdevice = PCI_ANY_ID,
972 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
976 .vendor = PCI_VENDOR_ID_INTEL,
977 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
978 .subvendor = PCI_ANY_ID,
979 .subdevice = PCI_ANY_ID,
980 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
984 .vendor = PCI_VENDOR_ID_INTEL,
985 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
986 .subvendor = PCI_ANY_ID,
987 .subdevice = PCI_ANY_ID,
988 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
992 .vendor = PCI_VENDOR_ID_INTEL,
993 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
994 .subvendor = PCI_ANY_ID,
995 .subdevice = PCI_ANY_ID,
996 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
1000 .vendor = PCI_VENDOR_ID_INTEL,
1001 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1002 .subvendor = PCI_ANY_ID,
1003 .subdevice = PCI_ANY_ID,
1004 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1008 .vendor = PCI_VENDOR_ID_INTEL,
1009 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1010 .subvendor = PCI_ANY_ID,
1011 .subdevice = PCI_ANY_ID,
1012 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1016 .vendor = PCI_VENDOR_ID_INTEL,
1017 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1018 .subvendor = PCI_ANY_ID,
1019 .subdevice = PCI_ANY_ID,
1020 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1024 .vendor = PCI_VENDOR_ID_O2,
1025 .device = PCI_DEVICE_ID_O2_8120,
1026 .subvendor = PCI_ANY_ID,
1027 .subdevice = PCI_ANY_ID,
1028 .driver_data = (kernel_ulong_t)&sdhci_o2,
1032 .vendor = PCI_VENDOR_ID_O2,
1033 .device = PCI_DEVICE_ID_O2_8220,
1034 .subvendor = PCI_ANY_ID,
1035 .subdevice = PCI_ANY_ID,
1036 .driver_data = (kernel_ulong_t)&sdhci_o2,
1040 .vendor = PCI_VENDOR_ID_O2,
1041 .device = PCI_DEVICE_ID_O2_8221,
1042 .subvendor = PCI_ANY_ID,
1043 .subdevice = PCI_ANY_ID,
1044 .driver_data = (kernel_ulong_t)&sdhci_o2,
1048 .vendor = PCI_VENDOR_ID_O2,
1049 .device = PCI_DEVICE_ID_O2_8320,
1050 .subvendor = PCI_ANY_ID,
1051 .subdevice = PCI_ANY_ID,
1052 .driver_data = (kernel_ulong_t)&sdhci_o2,
1056 .vendor = PCI_VENDOR_ID_O2,
1057 .device = PCI_DEVICE_ID_O2_8321,
1058 .subvendor = PCI_ANY_ID,
1059 .subdevice = PCI_ANY_ID,
1060 .driver_data = (kernel_ulong_t)&sdhci_o2,
1064 .vendor = PCI_VENDOR_ID_O2,
1065 .device = PCI_DEVICE_ID_O2_FUJIN2,
1066 .subvendor = PCI_ANY_ID,
1067 .subdevice = PCI_ANY_ID,
1068 .driver_data = (kernel_ulong_t)&sdhci_o2,
1072 .vendor = PCI_VENDOR_ID_O2,
1073 .device = PCI_DEVICE_ID_O2_SDS0,
1074 .subvendor = PCI_ANY_ID,
1075 .subdevice = PCI_ANY_ID,
1076 .driver_data = (kernel_ulong_t)&sdhci_o2,
1080 .vendor = PCI_VENDOR_ID_O2,
1081 .device = PCI_DEVICE_ID_O2_SDS1,
1082 .subvendor = PCI_ANY_ID,
1083 .subdevice = PCI_ANY_ID,
1084 .driver_data = (kernel_ulong_t)&sdhci_o2,
1088 .vendor = PCI_VENDOR_ID_O2,
1089 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1090 .subvendor = PCI_ANY_ID,
1091 .subdevice = PCI_ANY_ID,
1092 .driver_data = (kernel_ulong_t)&sdhci_o2,
1096 .vendor = PCI_VENDOR_ID_O2,
1097 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1098 .subvendor = PCI_ANY_ID,
1099 .subdevice = PCI_ANY_ID,
1100 .driver_data = (kernel_ulong_t)&sdhci_o2,
1103 .vendor = PCI_VENDOR_ID_AMD,
1104 .device = PCI_ANY_ID,
1105 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1106 .class_mask = 0xFFFF00,
1107 .subvendor = PCI_ANY_ID,
1108 .subdevice = PCI_ANY_ID,
1109 .driver_data = (kernel_ulong_t)&sdhci_amd,
1111 { /* Generic SD host controller */
1112 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1115 { /* end: all zeroes */ },
1118 MODULE_DEVICE_TABLE(pci, pci_ids);
1120 /*****************************************************************************\
1122 * SDHCI core callbacks *
1124 \*****************************************************************************/
1126 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1128 struct sdhci_pci_slot *slot;
1129 struct pci_dev *pdev;
1132 slot = sdhci_priv(host);
1133 pdev = slot->chip->pdev;
1135 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1136 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1137 (host->flags & SDHCI_USE_SDMA)) {
1138 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1139 "doesn't fully claim to support it.\n");
1142 if (host->flags & SDHCI_USE_64_BIT_DMA) {
1143 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) {
1144 host->flags &= ~SDHCI_USE_64_BIT_DMA;
1146 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1148 dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n");
1152 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1156 pci_set_master(pdev);
1161 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
1165 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1168 case MMC_BUS_WIDTH_8:
1169 ctrl |= SDHCI_CTRL_8BITBUS;
1170 ctrl &= ~SDHCI_CTRL_4BITBUS;
1172 case MMC_BUS_WIDTH_4:
1173 ctrl |= SDHCI_CTRL_4BITBUS;
1174 ctrl &= ~SDHCI_CTRL_8BITBUS;
1177 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1181 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1184 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1186 struct sdhci_pci_slot *slot = sdhci_priv(host);
1187 int rst_n_gpio = slot->rst_n_gpio;
1189 if (!gpio_is_valid(rst_n_gpio))
1191 gpio_set_value_cansleep(rst_n_gpio, 0);
1192 /* For eMMC, minimum is 1us but give it 10us for good measure */
1194 gpio_set_value_cansleep(rst_n_gpio, 1);
1195 /* For eMMC, minimum is 200us but give it 300us for good measure */
1196 usleep_range(300, 1000);
1199 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1201 struct sdhci_pci_slot *slot = sdhci_priv(host);
1204 slot->hw_reset(host);
1207 static const struct sdhci_ops sdhci_pci_ops = {
1208 .set_clock = sdhci_set_clock,
1209 .enable_dma = sdhci_pci_enable_dma,
1210 .set_bus_width = sdhci_pci_set_bus_width,
1211 .reset = sdhci_reset,
1212 .set_uhs_signaling = sdhci_set_uhs_signaling,
1213 .hw_reset = sdhci_pci_hw_reset,
1216 /*****************************************************************************\
1220 \*****************************************************************************/
1224 static int sdhci_pci_suspend(struct device *dev)
1226 struct pci_dev *pdev = to_pci_dev(dev);
1227 struct sdhci_pci_chip *chip;
1228 struct sdhci_pci_slot *slot;
1229 mmc_pm_flag_t slot_pm_flags;
1230 mmc_pm_flag_t pm_flags = 0;
1233 chip = pci_get_drvdata(pdev);
1237 for (i = 0; i < chip->num_slots; i++) {
1238 slot = chip->slots[i];
1242 ret = sdhci_suspend_host(slot->host);
1245 goto err_pci_suspend;
1247 slot_pm_flags = slot->host->mmc->pm_flags;
1248 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1249 sdhci_enable_irq_wakeups(slot->host);
1251 pm_flags |= slot_pm_flags;
1254 if (chip->fixes && chip->fixes->suspend) {
1255 ret = chip->fixes->suspend(chip);
1257 goto err_pci_suspend;
1260 if (pm_flags & MMC_PM_KEEP_POWER) {
1261 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1262 device_init_wakeup(dev, true);
1264 device_init_wakeup(dev, false);
1266 device_init_wakeup(dev, false);
1272 sdhci_resume_host(chip->slots[i]->host);
1276 static int sdhci_pci_resume(struct device *dev)
1278 struct pci_dev *pdev = to_pci_dev(dev);
1279 struct sdhci_pci_chip *chip;
1280 struct sdhci_pci_slot *slot;
1283 chip = pci_get_drvdata(pdev);
1287 if (chip->fixes && chip->fixes->resume) {
1288 ret = chip->fixes->resume(chip);
1293 for (i = 0; i < chip->num_slots; i++) {
1294 slot = chip->slots[i];
1298 ret = sdhci_resume_host(slot->host);
1306 static int sdhci_pci_runtime_suspend(struct device *dev)
1308 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1309 struct sdhci_pci_chip *chip;
1310 struct sdhci_pci_slot *slot;
1313 chip = pci_get_drvdata(pdev);
1317 for (i = 0; i < chip->num_slots; i++) {
1318 slot = chip->slots[i];
1322 ret = sdhci_runtime_suspend_host(slot->host);
1325 goto err_pci_runtime_suspend;
1328 if (chip->fixes && chip->fixes->suspend) {
1329 ret = chip->fixes->suspend(chip);
1331 goto err_pci_runtime_suspend;
1336 err_pci_runtime_suspend:
1338 sdhci_runtime_resume_host(chip->slots[i]->host);
1342 static int sdhci_pci_runtime_resume(struct device *dev)
1344 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1345 struct sdhci_pci_chip *chip;
1346 struct sdhci_pci_slot *slot;
1349 chip = pci_get_drvdata(pdev);
1353 if (chip->fixes && chip->fixes->resume) {
1354 ret = chip->fixes->resume(chip);
1359 for (i = 0; i < chip->num_slots; i++) {
1360 slot = chip->slots[i];
1364 ret = sdhci_runtime_resume_host(slot->host);
1372 #else /* CONFIG_PM */
1374 #define sdhci_pci_suspend NULL
1375 #define sdhci_pci_resume NULL
1377 #endif /* CONFIG_PM */
1379 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1380 .suspend = sdhci_pci_suspend,
1381 .resume = sdhci_pci_resume,
1382 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1383 sdhci_pci_runtime_resume, NULL)
1386 /*****************************************************************************\
1388 * Device probing/removal *
1390 \*****************************************************************************/
1392 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1393 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1396 struct sdhci_pci_slot *slot;
1397 struct sdhci_host *host;
1398 int ret, bar = first_bar + slotno;
1400 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1401 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1402 return ERR_PTR(-ENODEV);
1405 if (pci_resource_len(pdev, bar) < 0x100) {
1406 dev_err(&pdev->dev, "Invalid iomem size. You may "
1407 "experience problems.\n");
1410 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1411 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1412 return ERR_PTR(-ENODEV);
1415 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1416 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1417 return ERR_PTR(-ENODEV);
1420 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1422 dev_err(&pdev->dev, "cannot allocate host\n");
1423 return ERR_CAST(host);
1426 slot = sdhci_priv(host);
1430 slot->pci_bar = bar;
1431 slot->rst_n_gpio = -EINVAL;
1432 slot->cd_gpio = -EINVAL;
1435 /* Retrieve platform data if there is any */
1436 if (*sdhci_pci_get_data)
1437 slot->data = sdhci_pci_get_data(pdev, slotno);
1440 if (slot->data->setup) {
1441 ret = slot->data->setup(slot->data);
1443 dev_err(&pdev->dev, "platform setup failed\n");
1447 slot->rst_n_gpio = slot->data->rst_n_gpio;
1448 slot->cd_gpio = slot->data->cd_gpio;
1451 host->hw_name = "PCI";
1452 host->ops = &sdhci_pci_ops;
1453 host->quirks = chip->quirks;
1454 host->quirks2 = chip->quirks2;
1456 host->irq = pdev->irq;
1458 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1460 dev_err(&pdev->dev, "cannot request region\n");
1464 host->ioaddr = pci_ioremap_bar(pdev, bar);
1465 if (!host->ioaddr) {
1466 dev_err(&pdev->dev, "failed to remap registers\n");
1471 if (chip->fixes && chip->fixes->probe_slot) {
1472 ret = chip->fixes->probe_slot(slot);
1477 if (gpio_is_valid(slot->rst_n_gpio)) {
1478 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1479 gpio_direction_output(slot->rst_n_gpio, 1);
1480 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1481 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1483 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1484 slot->rst_n_gpio = -EINVAL;
1488 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1489 host->mmc->slotno = slotno;
1490 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1492 if (slot->cd_idx >= 0 &&
1493 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1494 slot->cd_override_level, 0, NULL)) {
1495 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1499 ret = sdhci_add_host(host);
1503 sdhci_pci_add_own_cd(slot);
1506 * Check if the chip needs a separate GPIO for card detect to wake up
1507 * from runtime suspend. If it is not there, don't allow runtime PM.
1508 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1510 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1511 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1512 chip->allow_runtime_pm = false;
1517 if (gpio_is_valid(slot->rst_n_gpio))
1518 gpio_free(slot->rst_n_gpio);
1520 if (chip->fixes && chip->fixes->remove_slot)
1521 chip->fixes->remove_slot(slot, 0);
1524 iounmap(host->ioaddr);
1527 pci_release_region(pdev, bar);
1530 if (slot->data && slot->data->cleanup)
1531 slot->data->cleanup(slot->data);
1534 sdhci_free_host(host);
1536 return ERR_PTR(ret);
1539 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1544 sdhci_pci_remove_own_cd(slot);
1547 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1548 if (scratch == (u32)-1)
1551 sdhci_remove_host(slot->host, dead);
1553 if (gpio_is_valid(slot->rst_n_gpio))
1554 gpio_free(slot->rst_n_gpio);
1556 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1557 slot->chip->fixes->remove_slot(slot, dead);
1559 if (slot->data && slot->data->cleanup)
1560 slot->data->cleanup(slot->data);
1562 pci_release_region(slot->chip->pdev, slot->pci_bar);
1564 sdhci_free_host(slot->host);
1567 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1569 pm_runtime_put_noidle(dev);
1570 pm_runtime_allow(dev);
1571 pm_runtime_set_autosuspend_delay(dev, 50);
1572 pm_runtime_use_autosuspend(dev);
1573 pm_suspend_ignore_children(dev, 1);
1576 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1578 pm_runtime_forbid(dev);
1579 pm_runtime_get_noresume(dev);
1582 static int sdhci_pci_probe(struct pci_dev *pdev,
1583 const struct pci_device_id *ent)
1585 struct sdhci_pci_chip *chip;
1586 struct sdhci_pci_slot *slot;
1588 u8 slots, first_bar;
1591 BUG_ON(pdev == NULL);
1592 BUG_ON(ent == NULL);
1594 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1595 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1597 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1601 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1602 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1606 BUG_ON(slots > MAX_SLOTS);
1608 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1612 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1614 if (first_bar > 5) {
1615 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1619 ret = pci_enable_device(pdev);
1623 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1630 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1632 chip->quirks = chip->fixes->quirks;
1633 chip->quirks2 = chip->fixes->quirks2;
1634 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1636 chip->num_slots = slots;
1638 pci_set_drvdata(pdev, chip);
1640 if (chip->fixes && chip->fixes->probe) {
1641 ret = chip->fixes->probe(chip);
1646 slots = chip->num_slots; /* Quirk may have changed this */
1648 for (i = 0; i < slots; i++) {
1649 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1651 for (i--; i >= 0; i--)
1652 sdhci_pci_remove_slot(chip->slots[i]);
1653 ret = PTR_ERR(slot);
1657 chip->slots[i] = slot;
1660 if (chip->allow_runtime_pm)
1661 sdhci_pci_runtime_pm_allow(&pdev->dev);
1666 pci_set_drvdata(pdev, NULL);
1670 pci_disable_device(pdev);
1674 static void sdhci_pci_remove(struct pci_dev *pdev)
1677 struct sdhci_pci_chip *chip;
1679 chip = pci_get_drvdata(pdev);
1682 if (chip->allow_runtime_pm)
1683 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1685 for (i = 0; i < chip->num_slots; i++)
1686 sdhci_pci_remove_slot(chip->slots[i]);
1688 pci_set_drvdata(pdev, NULL);
1692 pci_disable_device(pdev);
1695 static struct pci_driver sdhci_driver = {
1696 .name = "sdhci-pci",
1697 .id_table = pci_ids,
1698 .probe = sdhci_pci_probe,
1699 .remove = sdhci_pci_remove,
1701 .pm = &sdhci_pci_pm_ops
1705 module_pci_driver(sdhci_driver);
1707 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1708 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1709 MODULE_LICENSE("GPL");