kernel/drivers/memory/tegra/tegra30.c

   1 /*
   2  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/of.h>
  10 #include <linux/mm.h>
  11
  12 #include <dt-bindings/memory/tegra30-mc.h>
  13
  14 #include "mc.h"
  15
  16 static const struct tegra_mc_client tegra30_mc_clients[] = {
  17         {
  18                 .id = 0x00,
  19                 .name = "ptcr",
  20                 .swgroup = TEGRA_SWGROUP_PTC,
  21         }, {
  22                 .id = 0x01,
  23                 .name = "display0a",
  24                 .swgroup = TEGRA_SWGROUP_DC,
  25                 .smmu = {
  26                         .reg = 0x228,
  27                         .bit = 1,
  28                 },
  29                 .la = {
  30                         .reg = 0x2e8,
  31                         .shift = 0,
  32                         .mask = 0xff,
  33                         .def = 0x4e,
  34                 },
  35         }, {
  36                 .id = 0x02,
  37                 .name = "display0ab",
  38                 .swgroup = TEGRA_SWGROUP_DCB,
  39                 .smmu = {
  40                         .reg = 0x228,
  41                         .bit = 2,
  42                 },
  43                 .la = {
  44                         .reg = 0x2f4,
  45                         .shift = 0,
  46                         .mask = 0xff,
  47                         .def = 0x4e,
  48                 },
  49         }, {
  50                 .id = 0x03,
  51                 .name = "display0b",
  52                 .swgroup = TEGRA_SWGROUP_DC,
  53                 .smmu = {
  54                         .reg = 0x228,
  55                         .bit = 3,
  56                 },
  57                 .la = {
  58                         .reg = 0x2e8,
  59                         .shift = 16,
  60                         .mask = 0xff,
  61                         .def = 0x4e,
  62                 },
  63         }, {
  64                 .id = 0x04,
  65                 .name = "display0bb",
  66                 .swgroup = TEGRA_SWGROUP_DCB,
  67                 .smmu = {
  68                         .reg = 0x228,
  69                         .bit = 4,
  70                 },
  71                 .la = {
  72                         .reg = 0x2f4,
  73                         .shift = 16,
  74                         .mask = 0xff,
  75                         .def = 0x4e,
  76                 },
  77         }, {
  78                 .id = 0x05,
  79                 .name = "display0c",
  80                 .swgroup = TEGRA_SWGROUP_DC,
  81                 .smmu = {
  82                         .reg = 0x228,
  83                         .bit = 5,
  84                 },
  85                 .la = {
  86                         .reg = 0x2ec,
  87                         .shift = 0,
  88                         .mask = 0xff,
  89                         .def = 0x4e,
  90                 },
  91         }, {
  92                 .id = 0x06,
  93                 .name = "display0cb",
  94                 .swgroup = TEGRA_SWGROUP_DCB,
  95                 .smmu = {
  96                         .reg = 0x228,
  97                         .bit = 6,
  98                 },
  99                 .la = {
 100                         .reg = 0x2f8,
 101                         .shift = 0,
 102                         .mask = 0xff,
 103                         .def = 0x4e,
 104                 },
 105         }, {
 106                 .id = 0x07,
 107                 .name = "display1b",
 108                 .swgroup = TEGRA_SWGROUP_DC,
 109                 .smmu = {
 110                         .reg = 0x228,
 111                         .bit = 7,
 112                 },
 113                 .la = {
 114                         .reg = 0x2ec,
 115                         .shift = 16,
 116                         .mask = 0xff,
 117                         .def = 0x4e,
 118                 },
 119         }, {
 120                 .id = 0x08,
 121                 .name = "display1bb",
 122                 .swgroup = TEGRA_SWGROUP_DCB,
 123                 .smmu = {
 124                         .reg = 0x228,
 125                         .bit = 8,
 126                 },
 127                 .la = {
 128                         .reg = 0x2f8,
 129                         .shift = 16,
 130                         .mask = 0xff,
 131                         .def = 0x4e,
 132                 },
 133         }, {
 134                 .id = 0x09,
 135                 .name = "eppup",
 136                 .swgroup = TEGRA_SWGROUP_EPP,
 137                 .smmu = {
 138                         .reg = 0x228,
 139                         .bit = 9,
 140                 },
 141                 .la = {
 142                         .reg = 0x300,
 143                         .shift = 0,
 144                         .mask = 0xff,
 145                         .def = 0x17,
 146                 },
 147         }, {
 148                 .id = 0x0a,
 149                 .name = "g2pr",
 150                 .swgroup = TEGRA_SWGROUP_G2,
 151                 .smmu = {
 152                         .reg = 0x228,
 153                         .bit = 10,
 154                 },
 155                 .la = {
 156                         .reg = 0x308,
 157                         .shift = 0,
 158                         .mask = 0xff,
 159                         .def = 0x09,
 160                 },
 161         }, {
 162                 .id = 0x0b,
 163                 .name = "g2sr",
 164                 .swgroup = TEGRA_SWGROUP_G2,
 165                 .smmu = {
 166                         .reg = 0x228,
 167                         .bit = 11,
 168                 },
 169                 .la = {
 170                         .reg = 0x308,
 171                         .shift = 16,
 172                         .mask = 0xff,
 173                         .def = 0x09,
 174                 },
 175         }, {
 176                 .id = 0x0c,
 177                 .name = "mpeunifbr",
 178                 .swgroup = TEGRA_SWGROUP_MPE,
 179                 .smmu = {
 180                         .reg = 0x228,
 181                         .bit = 12,
 182                 },
 183                 .la = {
 184                         .reg = 0x328,
 185                         .shift = 0,
 186                         .mask = 0xff,
 187                         .def = 0x50,
 188                 },
 189         }, {
 190                 .id = 0x0d,
 191                 .name = "viruv",
 192                 .swgroup = TEGRA_SWGROUP_VI,
 193                 .smmu = {
 194                         .reg = 0x228,
 195                         .bit = 13,
 196                 },
 197                 .la = {
 198                         .reg = 0x364,
 199                         .shift = 0,
 200                         .mask = 0xff,
 201                         .def = 0x2c,
 202                 },
 203         }, {
 204                 .id = 0x0e,
 205                 .name = "afir",
 206                 .swgroup = TEGRA_SWGROUP_AFI,
 207                 .smmu = {
 208                         .reg = 0x228,
 209                         .bit = 14,
 210                 },
 211                 .la = {
 212                         .reg = 0x2e0,
 213                         .shift = 0,
 214                         .mask = 0xff,
 215                         .def = 0x10,
 216                 },
 217         }, {
 218                 .id = 0x0f,
 219                 .name = "avpcarm7r",
 220                 .swgroup = TEGRA_SWGROUP_AVPC,
 221                 .smmu = {
 222                         .reg = 0x228,
 223                         .bit = 15,
 224                 },
 225                 .la = {
 226                         .reg = 0x2e4,
 227                         .shift = 0,
 228                         .mask = 0xff,
 229                         .def = 0x04,
 230                 },
 231         }, {
 232                 .id = 0x10,
 233                 .name = "displayhc",
 234                 .swgroup = TEGRA_SWGROUP_DC,
 235                 .smmu = {
 236                         .reg = 0x228,
 237                         .bit = 16,
 238                 },
 239                 .la = {
 240                         .reg = 0x2f0,
 241                         .shift = 0,
 242                         .mask = 0xff,
 243                         .def = 0xff,
 244                 },
 245         }, {
 246                 .id = 0x11,
 247                 .name = "displayhcb",
 248                 .swgroup = TEGRA_SWGROUP_DCB,
 249                 .smmu = {
 250                         .reg = 0x228,
 251                         .bit = 17,
 252                 },
 253                 .la = {
 254                         .reg = 0x2fc,
 255                         .shift = 0,
 256                         .mask = 0xff,
 257                         .def = 0xff,
 258                 },
 259         }, {
 260                 .id = 0x12,
 261                 .name = "fdcdrd",
 262                 .swgroup = TEGRA_SWGROUP_NV,
 263                 .smmu = {
 264                         .reg = 0x228,
 265                         .bit = 18,
 266                 },
 267                 .la = {
 268                         .reg = 0x334,
 269                         .shift = 0,
 270                         .mask = 0xff,
 271                         .def = 0x0a,
 272                 },
 273         }, {
 274                 .id = 0x13,
 275                 .name = "fdcdrd2",
 276                 .swgroup = TEGRA_SWGROUP_NV2,
 277                 .smmu = {
 278                         .reg = 0x228,
 279                         .bit = 19,
 280                 },
 281                 .la = {
 282                         .reg = 0x33c,
 283                         .shift = 0,
 284                         .mask = 0xff,
 285                         .def = 0x0a,
 286                 },
 287         }, {
 288                 .id = 0x14,
 289                 .name = "g2dr",
 290                 .swgroup = TEGRA_SWGROUP_G2,
 291                 .smmu = {
 292                         .reg = 0x228,
 293                         .bit = 20,
 294                 },
 295                 .la = {
 296                         .reg = 0x30c,
 297                         .shift = 0,
 298                         .mask = 0xff,
 299                         .def = 0x0a,
 300                 },
 301         }, {
 302                 .id = 0x15,
 303                 .name = "hdar",
 304                 .swgroup = TEGRA_SWGROUP_HDA,
 305                 .smmu = {
 306                         .reg = 0x228,
 307                         .bit = 21,
 308                 },
 309                 .la = {
 310                         .reg = 0x318,
 311                         .shift = 0,
 312                         .mask = 0xff,
 313                         .def = 0xff,
 314                 },
 315         }, {
 316                 .id = 0x16,
 317                 .name = "host1xdmar",
 318                 .swgroup = TEGRA_SWGROUP_HC,
 319                 .smmu = {
 320                         .reg = 0x228,
 321                         .bit = 22,
 322                 },
 323                 .la = {
 324                         .reg = 0x310,
 325                         .shift = 0,
 326                         .mask = 0xff,
 327                         .def = 0x05,
 328                 },
 329         }, {
 330                 .id = 0x17,
 331                 .name = "host1xr",
 332                 .swgroup = TEGRA_SWGROUP_HC,
 333                 .smmu = {
 334                         .reg = 0x228,
 335                         .bit = 23,
 336                 },
 337                 .la = {
 338                         .reg = 0x310,
 339                         .shift = 16,
 340                         .mask = 0xff,
 341                         .def = 0x50,
 342                 },
 343         }, {
 344                 .id = 0x18,
 345                 .name = "idxsrd",
 346                 .swgroup = TEGRA_SWGROUP_NV,
 347                 .smmu = {
 348                         .reg = 0x228,
 349                         .bit = 24,
 350                 },
 351                 .la = {
 352                         .reg = 0x334,
 353                         .shift = 16,
 354                         .mask = 0xff,
 355                         .def = 0x13,
 356                 },
 357         }, {
 358                 .id = 0x19,
 359                 .name = "idxsrd2",
 360                 .swgroup = TEGRA_SWGROUP_NV2,
 361                 .smmu = {
 362                         .reg = 0x228,
 363                         .bit = 25,
 364                 },
 365                 .la = {
 366                         .reg = 0x33c,
 367                         .shift = 16,
 368                         .mask = 0xff,
 369                         .def = 0x13,
 370                 },
 371         }, {
 372                 .id = 0x1a,
 373                 .name = "mpe_ipred",
 374                 .swgroup = TEGRA_SWGROUP_MPE,
 375                 .smmu = {
 376                         .reg = 0x228,
 377                         .bit = 26,
 378                 },
 379                 .la = {
 380                         .reg = 0x328,
 381                         .shift = 16,
 382                         .mask = 0xff,
 383                         .def = 0x80,
 384                 },
 385         }, {
 386                 .id = 0x1b,
 387                 .name = "mpeamemrd",
 388                 .swgroup = TEGRA_SWGROUP_MPE,
 389                 .smmu = {
 390                         .reg = 0x228,
 391                         .bit = 27,
 392                 },
 393                 .la = {
 394                         .reg = 0x32c,
 395                         .shift = 0,
 396                         .mask = 0xff,
 397                         .def = 0x42,
 398                 },
 399         }, {
 400                 .id = 0x1c,
 401                 .name = "mpecsrd",
 402                 .swgroup = TEGRA_SWGROUP_MPE,
 403                 .smmu = {
 404                         .reg = 0x228,
 405                         .bit = 28,
 406                 },
 407                 .la = {
 408                         .reg = 0x32c,
 409                         .shift = 16,
 410                         .mask = 0xff,
 411                         .def = 0xff,
 412                 },
 413         }, {
 414                 .id = 0x1d,
 415                 .name = "ppcsahbdmar",
 416                 .swgroup = TEGRA_SWGROUP_PPCS,
 417                 .smmu = {
 418                         .reg = 0x228,
 419                         .bit = 29,
 420                 },
 421                 .la = {
 422                         .reg = 0x344,
 423                         .shift = 0,
 424                         .mask = 0xff,
 425                         .def = 0x10,
 426                 },
 427         }, {
 428                 .id = 0x1e,
 429                 .name = "ppcsahbslvr",
 430                 .swgroup = TEGRA_SWGROUP_PPCS,
 431                 .smmu = {
 432                         .reg = 0x228,
 433                         .bit = 30,
 434                 },
 435                 .la = {
 436                         .reg = 0x344,
 437                         .shift = 16,
 438                         .mask = 0xff,
 439                         .def = 0x12,
 440                 },
 441         }, {
 442                 .id = 0x1f,
 443                 .name = "satar",
 444                 .swgroup = TEGRA_SWGROUP_SATA,
 445                 .smmu = {
 446                         .reg = 0x228,
 447                         .bit = 31,
 448                 },
 449                 .la = {
 450                         .reg = 0x350,
 451                         .shift = 0,
 452                         .mask = 0xff,
 453                         .def = 0x33,
 454                 },
 455         }, {
 456                 .id = 0x20,
 457                 .name = "texsrd",
 458                 .swgroup = TEGRA_SWGROUP_NV,
 459                 .smmu = {
 460                         .reg = 0x22c,
 461                         .bit = 0,
 462                 },
 463                 .la = {
 464                         .reg = 0x338,
 465                         .shift = 0,
 466                         .mask = 0xff,
 467                         .def = 0x13,
 468                 },
 469         }, {
 470                 .id = 0x21,
 471                 .name = "texsrd2",
 472                 .swgroup = TEGRA_SWGROUP_NV2,
 473                 .smmu = {
 474                         .reg = 0x22c,
 475                         .bit = 1,
 476                 },
 477                 .la = {
 478                         .reg = 0x340,
 479                         .shift = 0,
 480                         .mask = 0xff,
 481                         .def = 0x13,
 482                 },
 483         }, {
 484                 .id = 0x22,
 485                 .name = "vdebsevr",
 486                 .swgroup = TEGRA_SWGROUP_VDE,
 487                 .smmu = {
 488                         .reg = 0x22c,
 489                         .bit = 2,
 490                 },
 491                 .la = {
 492                         .reg = 0x354,
 493                         .shift = 0,
 494                         .mask = 0xff,
 495                         .def = 0xff,
 496                 },
 497         }, {
 498                 .id = 0x23,
 499                 .name = "vdember",
 500                 .swgroup = TEGRA_SWGROUP_VDE,
 501                 .smmu = {
 502                         .reg = 0x22c,
 503                         .bit = 3,
 504                 },
 505                 .la = {
 506                         .reg = 0x354,
 507                         .shift = 16,
 508                         .mask = 0xff,
 509                         .def = 0xd0,
 510                 },
 511         }, {
 512                 .id = 0x24,
 513                 .name = "vdemcer",
 514                 .swgroup = TEGRA_SWGROUP_VDE,
 515                 .smmu = {
 516                         .reg = 0x22c,
 517                         .bit = 4,
 518                 },
 519                 .la = {
 520                         .reg = 0x358,
 521                         .shift = 0,
 522                         .mask = 0xff,
 523                         .def = 0x2a,
 524                 },
 525         }, {
 526                 .id = 0x25,
 527                 .name = "vdetper",
 528                 .swgroup = TEGRA_SWGROUP_VDE,
 529                 .smmu = {
 530                         .reg = 0x22c,
 531                         .bit = 5,
 532                 },
 533                 .la = {
 534                         .reg = 0x358,
 535                         .shift = 16,
 536                         .mask = 0xff,
 537                         .def = 0x74,
 538                 },
 539         }, {
 540                 .id = 0x26,
 541                 .name = "mpcorelpr",
 542                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 543                 .la = {
 544                         .reg = 0x324,
 545                         .shift = 0,
 546                         .mask = 0xff,
 547                         .def = 0x04,
 548                 },
 549         }, {
 550                 .id = 0x27,
 551                 .name = "mpcorer",
 552                 .swgroup = TEGRA_SWGROUP_MPCORE,
 553                 .la = {
 554                         .reg = 0x320,
 555                         .shift = 0,
 556                         .mask = 0xff,
 557                         .def = 0x04,
 558                 },
 559         }, {
 560                 .id = 0x28,
 561                 .name = "eppu",
 562                 .swgroup = TEGRA_SWGROUP_EPP,
 563                 .smmu = {
 564                         .reg = 0x22c,
 565                         .bit = 8,
 566                 },
 567                 .la = {
 568                         .reg = 0x300,
 569                         .shift = 16,
 570                         .mask = 0xff,
 571                         .def = 0x6c,
 572                 },
 573         }, {
 574                 .id = 0x29,
 575                 .name = "eppv",
 576                 .swgroup = TEGRA_SWGROUP_EPP,
 577                 .smmu = {
 578                         .reg = 0x22c,
 579                         .bit = 9,
 580                 },
 581                 .la = {
 582                         .reg = 0x304,
 583                         .shift = 0,
 584                         .mask = 0xff,
 585                         .def = 0x6c,
 586                 },
 587         }, {
 588                 .id = 0x2a,
 589                 .name = "eppy",
 590                 .swgroup = TEGRA_SWGROUP_EPP,
 591                 .smmu = {
 592                         .reg = 0x22c,
 593                         .bit = 10,
 594                 },
 595                 .la = {
 596                         .reg = 0x304,
 597                         .shift = 16,
 598                         .mask = 0xff,
 599                         .def = 0x6c,
 600                 },
 601         }, {
 602                 .id = 0x2b,
 603                 .name = "mpeunifbw",
 604                 .swgroup = TEGRA_SWGROUP_MPE,
 605                 .smmu = {
 606                         .reg = 0x22c,
 607                         .bit = 11,
 608                 },
 609                 .la = {
 610                         .reg = 0x330,
 611                         .shift = 0,
 612                         .mask = 0xff,
 613                         .def = 0x13,
 614                 },
 615         }, {
 616                 .id = 0x2c,
 617                 .name = "viwsb",
 618                 .swgroup = TEGRA_SWGROUP_VI,
 619                 .smmu = {
 620                         .reg = 0x22c,
 621                         .bit = 12,
 622                 },
 623                 .la = {
 624                         .reg = 0x364,
 625                         .shift = 16,
 626                         .mask = 0xff,
 627                         .def = 0x12,
 628                 },
 629         }, {
 630                 .id = 0x2d,
 631                 .name = "viwu",
 632                 .swgroup = TEGRA_SWGROUP_VI,
 633                 .smmu = {
 634                         .reg = 0x22c,
 635                         .bit = 13,
 636                 },
 637                 .la = {
 638                         .reg = 0x368,
 639                         .shift = 0,
 640                         .mask = 0xff,
 641                         .def = 0xb2,
 642                 },
 643         }, {
 644                 .id = 0x2e,
 645                 .name = "viwv",
 646                 .swgroup = TEGRA_SWGROUP_VI,
 647                 .smmu = {
 648                         .reg = 0x22c,
 649                         .bit = 14,
 650                 },
 651                 .la = {
 652                         .reg = 0x368,
 653                         .shift = 16,
 654                         .mask = 0xff,
 655                         .def = 0xb2,
 656                 },
 657         }, {
 658                 .id = 0x2f,
 659                 .name = "viwy",
 660                 .swgroup = TEGRA_SWGROUP_VI,
 661                 .smmu = {
 662                         .reg = 0x22c,
 663                         .bit = 15,
 664                 },
 665                 .la = {
 666                         .reg = 0x36c,
 667                         .shift = 0,
 668                         .mask = 0xff,
 669                         .def = 0x12,
 670                 },
 671         }, {
 672                 .id = 0x30,
 673                 .name = "g2dw",
 674                 .swgroup = TEGRA_SWGROUP_G2,
 675                 .smmu = {
 676                         .reg = 0x22c,
 677                         .bit = 16,
 678                 },
 679                 .la = {
 680                         .reg = 0x30c,
 681                         .shift = 16,
 682                         .mask = 0xff,
 683                         .def = 0x9,
 684                 },
 685         }, {
 686                 .id = 0x31,
 687                 .name = "afiw",
 688                 .swgroup = TEGRA_SWGROUP_AFI,
 689                 .smmu = {
 690                         .reg = 0x22c,
 691                         .bit = 17,
 692                 },
 693                 .la = {
 694                         .reg = 0x2e0,
 695                         .shift = 16,
 696                         .mask = 0xff,
 697                         .def = 0x0c,
 698                 },
 699         }, {
 700                 .id = 0x32,
 701                 .name = "avpcarm7w",
 702                 .swgroup = TEGRA_SWGROUP_AVPC,
 703                 .smmu = {
 704                         .reg = 0x22c,
 705                         .bit = 18,
 706                 },
 707                 .la = {
 708                         .reg = 0x2e4,
 709                         .shift = 16,
 710                         .mask = 0xff,
 711                         .def = 0x0e,
 712                 },
 713         }, {
 714                 .id = 0x33,
 715                 .name = "fdcdwr",
 716                 .swgroup = TEGRA_SWGROUP_NV,
 717                 .smmu = {
 718                         .reg = 0x22c,
 719                         .bit = 19,
 720                 },
 721                 .la = {
 722                         .reg = 0x338,
 723                         .shift = 16,
 724                         .mask = 0xff,
 725                         .def = 0x0a,
 726                 },
 727         }, {
 728                 .id = 0x34,
 729                 .name = "fdcwr2",
 730                 .swgroup = TEGRA_SWGROUP_NV2,
 731                 .smmu = {
 732                         .reg = 0x22c,
 733                         .bit = 20,
 734                 },
 735                 .la = {
 736                         .reg = 0x340,
 737                         .shift = 16,
 738                         .mask = 0xff,
 739                         .def = 0x0a,
 740                 },
 741         }, {
 742                 .id = 0x35,
 743                 .name = "hdaw",
 744                 .swgroup = TEGRA_SWGROUP_HDA,
 745                 .smmu = {
 746                         .reg = 0x22c,
 747                         .bit = 21,
 748                 },
 749                 .la = {
 750                         .reg = 0x318,
 751                         .shift = 16,
 752                         .mask = 0xff,
 753                         .def = 0xff,
 754                 },
 755         }, {
 756                 .id = 0x36,
 757                 .name = "host1xw",
 758                 .swgroup = TEGRA_SWGROUP_HC,
 759                 .smmu = {
 760                         .reg = 0x22c,
 761                         .bit = 22,
 762                 },
 763                 .la = {
 764                         .reg = 0x314,
 765                         .shift = 0,
 766                         .mask = 0xff,
 767                         .def = 0x10,
 768                 },
 769         }, {
 770                 .id = 0x37,
 771                 .name = "ispw",
 772                 .swgroup = TEGRA_SWGROUP_ISP,
 773                 .smmu = {
 774                         .reg = 0x22c,
 775                         .bit = 23,
 776                 },
 777                 .la = {
 778                         .reg = 0x31c,
 779                         .shift = 0,
 780                         .mask = 0xff,
 781                         .def = 0xff,
 782                 },
 783         }, {
 784                 .id = 0x38,
 785                 .name = "mpcorelpw",
 786                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 787                 .la = {
 788                         .reg = 0x324,
 789                         .shift = 16,
 790                         .mask = 0xff,
 791                         .def = 0x0e,
 792                 },
 793         }, {
 794                 .id = 0x39,
 795                 .name = "mpcorew",
 796                 .swgroup = TEGRA_SWGROUP_MPCORE,
 797                 .la = {
 798                         .reg = 0x320,
 799                         .shift = 16,
 800                         .mask = 0xff,
 801                         .def = 0x0e,
 802                 },
 803         }, {
 804                 .id = 0x3a,
 805                 .name = "mpecswr",
 806                 .swgroup = TEGRA_SWGROUP_MPE,
 807                 .smmu = {
 808                         .reg = 0x22c,
 809                         .bit = 26,
 810                 },
 811                 .la = {
 812                         .reg = 0x330,
 813                         .shift = 16,
 814                         .mask = 0xff,
 815                         .def = 0xff,
 816                 },
 817         }, {
 818                 .id = 0x3b,
 819                 .name = "ppcsahbdmaw",
 820                 .swgroup = TEGRA_SWGROUP_PPCS,
 821                 .smmu = {
 822                         .reg = 0x22c,
 823                         .bit = 27,
 824                 },
 825                 .la = {
 826                         .reg = 0x348,
 827                         .shift = 0,
 828                         .mask = 0xff,
 829                         .def = 0x10,
 830                 },
 831         }, {
 832                 .id = 0x3c,
 833                 .name = "ppcsahbslvw",
 834                 .swgroup = TEGRA_SWGROUP_PPCS,
 835                 .smmu = {
 836                         .reg = 0x22c,
 837                         .bit = 28,
 838                 },
 839                 .la = {
 840                         .reg = 0x348,
 841                         .shift = 16,
 842                         .mask = 0xff,
 843                         .def = 0x06,
 844                 },
 845         }, {
 846                 .id = 0x3d,
 847                 .name = "sataw",
 848                 .swgroup = TEGRA_SWGROUP_SATA,
 849                 .smmu = {
 850                         .reg = 0x22c,
 851                         .bit = 29,
 852                 },
 853                 .la = {
 854                         .reg = 0x350,
 855                         .shift = 16,
 856                         .mask = 0xff,
 857                         .def = 0x33,
 858                 },
 859         }, {
 860                 .id = 0x3e,
 861                 .name = "vdebsevw",
 862                 .swgroup = TEGRA_SWGROUP_VDE,
 863                 .smmu = {
 864                         .reg = 0x22c,
 865                         .bit = 30,
 866                 },
 867                 .la = {
 868                         .reg = 0x35c,
 869                         .shift = 0,
 870                         .mask = 0xff,
 871                         .def = 0xff,
 872                 },
 873         }, {
 874                 .id = 0x3f,
 875                 .name = "vdedbgw",
 876                 .swgroup = TEGRA_SWGROUP_VDE,
 877                 .smmu = {
 878                         .reg = 0x22c,
 879                         .bit = 31,
 880                 },
 881                 .la = {
 882                         .reg = 0x35c,
 883                         .shift = 16,
 884                         .mask = 0xff,
 885                         .def = 0xff,
 886                 },
 887         }, {
 888                 .id = 0x40,
 889                 .name = "vdembew",
 890                 .swgroup = TEGRA_SWGROUP_VDE,
 891                 .smmu = {
 892                         .reg = 0x230,
 893                         .bit = 0,
 894                 },
 895                 .la = {
 896                         .reg = 0x360,
 897                         .shift = 0,
 898                         .mask = 0xff,
 899                         .def = 0x42,
 900                 },
 901         }, {
 902                 .id = 0x41,
 903                 .name = "vdetpmw",
 904                 .swgroup = TEGRA_SWGROUP_VDE,
 905                 .smmu = {
 906                         .reg = 0x230,
 907                         .bit = 1,
 908                 },
 909                 .la = {
 910                         .reg = 0x360,
 911                         .shift = 16,
 912                         .mask = 0xff,
 913                         .def = 0x2a,
 914                 },
 915         },
 916 };
 917
 918 static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
 919         { .name = "dc",   .swgroup = TEGRA_SWGROUP_DC,   .reg = 0x240 },
 920         { .name = "dcb",  .swgroup = TEGRA_SWGROUP_DCB,  .reg = 0x244 },
 921         { .name = "epp",  .swgroup = TEGRA_SWGROUP_EPP,  .reg = 0x248 },
 922         { .name = "g2",   .swgroup = TEGRA_SWGROUP_G2,   .reg = 0x24c },
 923         { .name = "mpe",  .swgroup = TEGRA_SWGROUP_MPE,  .reg = 0x264 },
 924         { .name = "vi",   .swgroup = TEGRA_SWGROUP_VI,   .reg = 0x280 },
 925         { .name = "afi",  .swgroup = TEGRA_SWGROUP_AFI,  .reg = 0x238 },
 926         { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
 927         { .name = "nv",   .swgroup = TEGRA_SWGROUP_NV,   .reg = 0x268 },
 928         { .name = "nv2",  .swgroup = TEGRA_SWGROUP_NV2,  .reg = 0x26c },
 929         { .name = "hda",  .swgroup = TEGRA_SWGROUP_HDA,  .reg = 0x254 },
 930         { .name = "hc",   .swgroup = TEGRA_SWGROUP_HC,   .reg = 0x250 },
 931         { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
 932         { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
 933         { .name = "vde",  .swgroup = TEGRA_SWGROUP_VDE,  .reg = 0x27c },
 934         { .name = "isp",  .swgroup = TEGRA_SWGROUP_ISP,  .reg = 0x258 },
 935 };
 936
 937 static const struct tegra_smmu_soc tegra30_smmu_soc = {
 938         .clients = tegra30_mc_clients,
 939         .num_clients = ARRAY_SIZE(tegra30_mc_clients),
 940         .swgroups = tegra30_swgroups,
 941         .num_swgroups = ARRAY_SIZE(tegra30_swgroups),
 942         .supports_round_robin_arbitration = false,
 943         .supports_request_limit = false,
 944         .num_tlb_lines = 16,
 945         .num_asids = 4,
 946 };
 947
 948 const struct tegra_mc_soc tegra30_mc_soc = {
 949         .clients = tegra30_mc_clients,
 950         .num_clients = ARRAY_SIZE(tegra30_mc_clients),
 951         .num_address_bits = 32,
 952         .atom_size = 16,
 953         .client_id_mask = 0x7f,
 954         .smmu = &tegra30_smmu_soc,
 955 };