kernel/drivers/memory/tegra/tegra124.c

   1 /*
   2  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/of.h>
  10 #include <linux/mm.h>
  11
  12 #include <asm/cacheflush.h>
  13
  14 #include <dt-bindings/memory/tegra124-mc.h>
  15
  16 #include "mc.h"
  17
  18 static const struct tegra_mc_client tegra124_mc_clients[] = {
  19         {
  20                 .id = 0x00,
  21                 .name = "ptcr",
  22                 .swgroup = TEGRA_SWGROUP_PTC,
  23         }, {
  24                 .id = 0x01,
  25                 .name = "display0a",
  26                 .swgroup = TEGRA_SWGROUP_DC,
  27                 .smmu = {
  28                         .reg = 0x228,
  29                         .bit = 1,
  30                 },
  31                 .la = {
  32                         .reg = 0x2e8,
  33                         .shift = 0,
  34                         .mask = 0xff,
  35                         .def = 0xc2,
  36                 },
  37         }, {
  38                 .id = 0x02,
  39                 .name = "display0ab",
  40                 .swgroup = TEGRA_SWGROUP_DCB,
  41                 .smmu = {
  42                         .reg = 0x228,
  43                         .bit = 2,
  44                 },
  45                 .la = {
  46                         .reg = 0x2f4,
  47                         .shift = 0,
  48                         .mask = 0xff,
  49                         .def = 0xc6,
  50                 },
  51         }, {
  52                 .id = 0x03,
  53                 .name = "display0b",
  54                 .swgroup = TEGRA_SWGROUP_DC,
  55                 .smmu = {
  56                         .reg = 0x228,
  57                         .bit = 3,
  58                 },
  59                 .la = {
  60                         .reg = 0x2e8,
  61                         .shift = 16,
  62                         .mask = 0xff,
  63                         .def = 0x50,
  64                 },
  65         }, {
  66                 .id = 0x04,
  67                 .name = "display0bb",
  68                 .swgroup = TEGRA_SWGROUP_DCB,
  69                 .smmu = {
  70                         .reg = 0x228,
  71                         .bit = 4,
  72                 },
  73                 .la = {
  74                         .reg = 0x2f4,
  75                         .shift = 16,
  76                         .mask = 0xff,
  77                         .def = 0x50,
  78                 },
  79         }, {
  80                 .id = 0x05,
  81                 .name = "display0c",
  82                 .swgroup = TEGRA_SWGROUP_DC,
  83                 .smmu = {
  84                         .reg = 0x228,
  85                         .bit = 5,
  86                 },
  87                 .la = {
  88                         .reg = 0x2ec,
  89                         .shift = 0,
  90                         .mask = 0xff,
  91                         .def = 0x50,
  92                 },
  93         }, {
  94                 .id = 0x06,
  95                 .name = "display0cb",
  96                 .swgroup = TEGRA_SWGROUP_DCB,
  97                 .smmu = {
  98                         .reg = 0x228,
  99                         .bit = 6,
 100                 },
 101                 .la = {
 102                         .reg = 0x2f8,
 103                         .shift = 0,
 104                         .mask = 0xff,
 105                         .def = 0x50,
 106                 },
 107         }, {
 108                 .id = 0x0e,
 109                 .name = "afir",
 110                 .swgroup = TEGRA_SWGROUP_AFI,
 111                 .smmu = {
 112                         .reg = 0x228,
 113                         .bit = 14,
 114                 },
 115                 .la = {
 116                         .reg = 0x2e0,
 117                         .shift = 0,
 118                         .mask = 0xff,
 119                         .def = 0x13,
 120                 },
 121         }, {
 122                 .id = 0x0f,
 123                 .name = "avpcarm7r",
 124                 .swgroup = TEGRA_SWGROUP_AVPC,
 125                 .smmu = {
 126                         .reg = 0x228,
 127                         .bit = 15,
 128                 },
 129                 .la = {
 130                         .reg = 0x2e4,
 131                         .shift = 0,
 132                         .mask = 0xff,
 133                         .def = 0x04,
 134                 },
 135         }, {
 136                 .id = 0x10,
 137                 .name = "displayhc",
 138                 .swgroup = TEGRA_SWGROUP_DC,
 139                 .smmu = {
 140                         .reg = 0x228,
 141                         .bit = 16,
 142                 },
 143                 .la = {
 144                         .reg = 0x2f0,
 145                         .shift = 0,
 146                         .mask = 0xff,
 147                         .def = 0x50,
 148                 },
 149         }, {
 150                 .id = 0x11,
 151                 .name = "displayhcb",
 152                 .swgroup = TEGRA_SWGROUP_DCB,
 153                 .smmu = {
 154                         .reg = 0x228,
 155                         .bit = 17,
 156                 },
 157                 .la = {
 158                         .reg = 0x2fc,
 159                         .shift = 0,
 160                         .mask = 0xff,
 161                         .def = 0x50,
 162                 },
 163         }, {
 164                 .id = 0x15,
 165                 .name = "hdar",
 166                 .swgroup = TEGRA_SWGROUP_HDA,
 167                 .smmu = {
 168                         .reg = 0x228,
 169                         .bit = 21,
 170                 },
 171                 .la = {
 172                         .reg = 0x318,
 173                         .shift = 0,
 174                         .mask = 0xff,
 175                         .def = 0x24,
 176                 },
 177         }, {
 178                 .id = 0x16,
 179                 .name = "host1xdmar",
 180                 .swgroup = TEGRA_SWGROUP_HC,
 181                 .smmu = {
 182                         .reg = 0x228,
 183                         .bit = 22,
 184                 },
 185                 .la = {
 186                         .reg = 0x310,
 187                         .shift = 0,
 188                         .mask = 0xff,
 189                         .def = 0x1e,
 190                 },
 191         }, {
 192                 .id = 0x17,
 193                 .name = "host1xr",
 194                 .swgroup = TEGRA_SWGROUP_HC,
 195                 .smmu = {
 196                         .reg = 0x228,
 197                         .bit = 23,
 198                 },
 199                 .la = {
 200                         .reg = 0x310,
 201                         .shift = 16,
 202                         .mask = 0xff,
 203                         .def = 0x50,
 204                 },
 205         }, {
 206                 .id = 0x1c,
 207                 .name = "msencsrd",
 208                 .swgroup = TEGRA_SWGROUP_MSENC,
 209                 .smmu = {
 210                         .reg = 0x228,
 211                         .bit = 28,
 212                 },
 213                 .la = {
 214                         .reg = 0x328,
 215                         .shift = 0,
 216                         .mask = 0xff,
 217                         .def = 0x23,
 218                 },
 219         }, {
 220                 .id = 0x1d,
 221                 .name = "ppcsahbdmar",
 222                 .swgroup = TEGRA_SWGROUP_PPCS,
 223                 .smmu = {
 224                         .reg = 0x228,
 225                         .bit = 29,
 226                 },
 227                 .la = {
 228                         .reg = 0x344,
 229                         .shift = 0,
 230                         .mask = 0xff,
 231                         .def = 0x49,
 232                 },
 233         }, {
 234                 .id = 0x1e,
 235                 .name = "ppcsahbslvr",
 236                 .swgroup = TEGRA_SWGROUP_PPCS,
 237                 .smmu = {
 238                         .reg = 0x228,
 239                         .bit = 30,
 240                 },
 241                 .la = {
 242                         .reg = 0x344,
 243                         .shift = 16,
 244                         .mask = 0xff,
 245                         .def = 0x1a,
 246                 },
 247         }, {
 248                 .id = 0x1f,
 249                 .name = "satar",
 250                 .swgroup = TEGRA_SWGROUP_SATA,
 251                 .smmu = {
 252                         .reg = 0x228,
 253                         .bit = 31,
 254                 },
 255                 .la = {
 256                         .reg = 0x350,
 257                         .shift = 0,
 258                         .mask = 0xff,
 259                         .def = 0x65,
 260                 },
 261         }, {
 262                 .id = 0x22,
 263                 .name = "vdebsevr",
 264                 .swgroup = TEGRA_SWGROUP_VDE,
 265                 .smmu = {
 266                         .reg = 0x22c,
 267                         .bit = 2,
 268                 },
 269                 .la = {
 270                         .reg = 0x354,
 271                         .shift = 0,
 272                         .mask = 0xff,
 273                         .def = 0x4f,
 274                 },
 275         }, {
 276                 .id = 0x23,
 277                 .name = "vdember",
 278                 .swgroup = TEGRA_SWGROUP_VDE,
 279                 .smmu = {
 280                         .reg = 0x22c,
 281                         .bit = 3,
 282                 },
 283                 .la = {
 284                         .reg = 0x354,
 285                         .shift = 16,
 286                         .mask = 0xff,
 287                         .def = 0x3d,
 288                 },
 289         }, {
 290                 .id = 0x24,
 291                 .name = "vdemcer",
 292                 .swgroup = TEGRA_SWGROUP_VDE,
 293                 .smmu = {
 294                         .reg = 0x22c,
 295                         .bit = 4,
 296                 },
 297                 .la = {
 298                         .reg = 0x358,
 299                         .shift = 0,
 300                         .mask = 0xff,
 301                         .def = 0x66,
 302                 },
 303         }, {
 304                 .id = 0x25,
 305                 .name = "vdetper",
 306                 .swgroup = TEGRA_SWGROUP_VDE,
 307                 .smmu = {
 308                         .reg = 0x22c,
 309                         .bit = 5,
 310                 },
 311                 .la = {
 312                         .reg = 0x358,
 313                         .shift = 16,
 314                         .mask = 0xff,
 315                         .def = 0xa5,
 316                 },
 317         }, {
 318                 .id = 0x26,
 319                 .name = "mpcorelpr",
 320                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 321                 .la = {
 322                         .reg = 0x324,
 323                         .shift = 0,
 324                         .mask = 0xff,
 325                         .def = 0x04,
 326                 },
 327         }, {
 328                 .id = 0x27,
 329                 .name = "mpcorer",
 330                 .swgroup = TEGRA_SWGROUP_MPCORE,
 331                 .la = {
 332                         .reg = 0x320,
 333                         .shift = 0,
 334                         .mask = 0xff,
 335                         .def = 0x04,
 336                 },
 337         }, {
 338                 .id = 0x2b,
 339                 .name = "msencswr",
 340                 .swgroup = TEGRA_SWGROUP_MSENC,
 341                 .smmu = {
 342                         .reg = 0x22c,
 343                         .bit = 11,
 344                 },
 345                 .la = {
 346                         .reg = 0x328,
 347                         .shift = 16,
 348                         .mask = 0xff,
 349                         .def = 0x80,
 350                 },
 351         }, {
 352                 .id = 0x31,
 353                 .name = "afiw",
 354                 .swgroup = TEGRA_SWGROUP_AFI,
 355                 .smmu = {
 356                         .reg = 0x22c,
 357                         .bit = 17,
 358                 },
 359                 .la = {
 360                         .reg = 0x2e0,
 361                         .shift = 16,
 362                         .mask = 0xff,
 363                         .def = 0x80,
 364                 },
 365         }, {
 366                 .id = 0x32,
 367                 .name = "avpcarm7w",
 368                 .swgroup = TEGRA_SWGROUP_AVPC,
 369                 .smmu = {
 370                         .reg = 0x22c,
 371                         .bit = 18,
 372                 },
 373                 .la = {
 374                         .reg = 0x2e4,
 375                         .shift = 16,
 376                         .mask = 0xff,
 377                         .def = 0x80,
 378                 },
 379         }, {
 380                 .id = 0x35,
 381                 .name = "hdaw",
 382                 .swgroup = TEGRA_SWGROUP_HDA,
 383                 .smmu = {
 384                         .reg = 0x22c,
 385                         .bit = 21,
 386                 },
 387                 .la = {
 388                         .reg = 0x318,
 389                         .shift = 16,
 390                         .mask = 0xff,
 391                         .def = 0x80,
 392                 },
 393         }, {
 394                 .id = 0x36,
 395                 .name = "host1xw",
 396                 .swgroup = TEGRA_SWGROUP_HC,
 397                 .smmu = {
 398                         .reg = 0x22c,
 399                         .bit = 22,
 400                 },
 401                 .la = {
 402                         .reg = 0x314,
 403                         .shift = 0,
 404                         .mask = 0xff,
 405                         .def = 0x80,
 406                 },
 407         }, {
 408                 .id = 0x38,
 409                 .name = "mpcorelpw",
 410                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 411                 .la = {
 412                         .reg = 0x324,
 413                         .shift = 16,
 414                         .mask = 0xff,
 415                         .def = 0x80,
 416                 },
 417         }, {
 418                 .id = 0x39,
 419                 .name = "mpcorew",
 420                 .swgroup = TEGRA_SWGROUP_MPCORE,
 421                 .la = {
 422                         .reg = 0x320,
 423                         .shift = 16,
 424                         .mask = 0xff,
 425                         .def = 0x80,
 426                 },
 427         }, {
 428                 .id = 0x3b,
 429                 .name = "ppcsahbdmaw",
 430                 .swgroup = TEGRA_SWGROUP_PPCS,
 431                 .smmu = {
 432                         .reg = 0x22c,
 433                         .bit = 27,
 434                 },
 435                 .la = {
 436                         .reg = 0x348,
 437                         .shift = 0,
 438                         .mask = 0xff,
 439                         .def = 0x80,
 440                 },
 441         }, {
 442                 .id = 0x3c,
 443                 .name = "ppcsahbslvw",
 444                 .swgroup = TEGRA_SWGROUP_PPCS,
 445                 .smmu = {
 446                         .reg = 0x22c,
 447                         .bit = 28,
 448                 },
 449                 .la = {
 450                         .reg = 0x348,
 451                         .shift = 16,
 452                         .mask = 0xff,
 453                         .def = 0x80,
 454                 },
 455         }, {
 456                 .id = 0x3d,
 457                 .name = "sataw",
 458                 .swgroup = TEGRA_SWGROUP_SATA,
 459                 .smmu = {
 460                         .reg = 0x22c,
 461                         .bit = 29,
 462                 },
 463                 .la = {
 464                         .reg = 0x350,
 465                         .shift = 16,
 466                         .mask = 0xff,
 467                         .def = 0x65,
 468                 },
 469         }, {
 470                 .id = 0x3e,
 471                 .name = "vdebsevw",
 472                 .swgroup = TEGRA_SWGROUP_VDE,
 473                 .smmu = {
 474                         .reg = 0x22c,
 475                         .bit = 30,
 476                 },
 477                 .la = {
 478                         .reg = 0x35c,
 479                         .shift = 0,
 480                         .mask = 0xff,
 481                         .def = 0x80,
 482                 },
 483         }, {
 484                 .id = 0x3f,
 485                 .name = "vdedbgw",
 486                 .swgroup = TEGRA_SWGROUP_VDE,
 487                 .smmu = {
 488                         .reg = 0x22c,
 489                         .bit = 31,
 490                 },
 491                 .la = {
 492                         .reg = 0x35c,
 493                         .shift = 16,
 494                         .mask = 0xff,
 495                         .def = 0x80,
 496                 },
 497         }, {
 498                 .id = 0x40,
 499                 .name = "vdembew",
 500                 .swgroup = TEGRA_SWGROUP_VDE,
 501                 .smmu = {
 502                         .reg = 0x230,
 503                         .bit = 0,
 504                 },
 505                 .la = {
 506                         .reg = 0x360,
 507                         .shift = 0,
 508                         .mask = 0xff,
 509                         .def = 0x80,
 510                 },
 511         }, {
 512                 .id = 0x41,
 513                 .name = "vdetpmw",
 514                 .swgroup = TEGRA_SWGROUP_VDE,
 515                 .smmu = {
 516                         .reg = 0x230,
 517                         .bit = 1,
 518                 },
 519                 .la = {
 520                         .reg = 0x360,
 521                         .shift = 16,
 522                         .mask = 0xff,
 523                         .def = 0x80,
 524                 },
 525         }, {
 526                 .id = 0x44,
 527                 .name = "ispra",
 528                 .swgroup = TEGRA_SWGROUP_ISP2,
 529                 .smmu = {
 530                         .reg = 0x230,
 531                         .bit = 4,
 532                 },
 533                 .la = {
 534                         .reg = 0x370,
 535                         .shift = 0,
 536                         .mask = 0xff,
 537                         .def = 0x18,
 538                 },
 539         }, {
 540                 .id = 0x46,
 541                 .name = "ispwa",
 542                 .swgroup = TEGRA_SWGROUP_ISP2,
 543                 .smmu = {
 544                         .reg = 0x230,
 545                         .bit = 6,
 546                 },
 547                 .la = {
 548                         .reg = 0x374,
 549                         .shift = 0,
 550                         .mask = 0xff,
 551                         .def = 0x80,
 552                 },
 553         }, {
 554                 .id = 0x47,
 555                 .name = "ispwb",
 556                 .swgroup = TEGRA_SWGROUP_ISP2,
 557                 .smmu = {
 558                         .reg = 0x230,
 559                         .bit = 7,
 560                 },
 561                 .la = {
 562                         .reg = 0x374,
 563                         .shift = 16,
 564                         .mask = 0xff,
 565                         .def = 0x80,
 566                 },
 567         }, {
 568                 .id = 0x4a,
 569                 .name = "xusb_hostr",
 570                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 571                 .smmu = {
 572                         .reg = 0x230,
 573                         .bit = 10,
 574                 },
 575                 .la = {
 576                         .reg = 0x37c,
 577                         .shift = 0,
 578                         .mask = 0xff,
 579                         .def = 0x39,
 580                 },
 581         }, {
 582                 .id = 0x4b,
 583                 .name = "xusb_hostw",
 584                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 585                 .smmu = {
 586                         .reg = 0x230,
 587                         .bit = 11,
 588                 },
 589                 .la = {
 590                         .reg = 0x37c,
 591                         .shift = 16,
 592                         .mask = 0xff,
 593                         .def = 0x80,
 594                 },
 595         }, {
 596                 .id = 0x4c,
 597                 .name = "xusb_devr",
 598                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 599                 .smmu = {
 600                         .reg = 0x230,
 601                         .bit = 12,
 602                 },
 603                 .la = {
 604                         .reg = 0x380,
 605                         .shift = 0,
 606                         .mask = 0xff,
 607                         .def = 0x39,
 608                 },
 609         }, {
 610                 .id = 0x4d,
 611                 .name = "xusb_devw",
 612                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 613                 .smmu = {
 614                         .reg = 0x230,
 615                         .bit = 13,
 616                 },
 617                 .la = {
 618                         .reg = 0x380,
 619                         .shift = 16,
 620                         .mask = 0xff,
 621                         .def = 0x80,
 622                 },
 623         }, {
 624                 .id = 0x4e,
 625                 .name = "isprab",
 626                 .swgroup = TEGRA_SWGROUP_ISP2B,
 627                 .smmu = {
 628                         .reg = 0x230,
 629                         .bit = 14,
 630                 },
 631                 .la = {
 632                         .reg = 0x384,
 633                         .shift = 0,
 634                         .mask = 0xff,
 635                         .def = 0x18,
 636                 },
 637         }, {
 638                 .id = 0x50,
 639                 .name = "ispwab",
 640                 .swgroup = TEGRA_SWGROUP_ISP2B,
 641                 .smmu = {
 642                         .reg = 0x230,
 643                         .bit = 16,
 644                 },
 645                 .la = {
 646                         .reg = 0x388,
 647                         .shift = 0,
 648                         .mask = 0xff,
 649                         .def = 0x80,
 650                 },
 651         }, {
 652                 .id = 0x51,
 653                 .name = "ispwbb",
 654                 .swgroup = TEGRA_SWGROUP_ISP2B,
 655                 .smmu = {
 656                         .reg = 0x230,
 657                         .bit = 17,
 658                 },
 659                 .la = {
 660                         .reg = 0x388,
 661                         .shift = 16,
 662                         .mask = 0xff,
 663                         .def = 0x80,
 664                 },
 665         }, {
 666                 .id = 0x54,
 667                 .name = "tsecsrd",
 668                 .swgroup = TEGRA_SWGROUP_TSEC,
 669                 .smmu = {
 670                         .reg = 0x230,
 671                         .bit = 20,
 672                 },
 673                 .la = {
 674                         .reg = 0x390,
 675                         .shift = 0,
 676                         .mask = 0xff,
 677                         .def = 0x9b,
 678                 },
 679         }, {
 680                 .id = 0x55,
 681                 .name = "tsecswr",
 682                 .swgroup = TEGRA_SWGROUP_TSEC,
 683                 .smmu = {
 684                         .reg = 0x230,
 685                         .bit = 21,
 686                 },
 687                 .la = {
 688                         .reg = 0x390,
 689                         .shift = 16,
 690                         .mask = 0xff,
 691                         .def = 0x80,
 692                 },
 693         }, {
 694                 .id = 0x56,
 695                 .name = "a9avpscr",
 696                 .swgroup = TEGRA_SWGROUP_A9AVP,
 697                 .smmu = {
 698                         .reg = 0x230,
 699                         .bit = 22,
 700                 },
 701                 .la = {
 702                         .reg = 0x3a4,
 703                         .shift = 0,
 704                         .mask = 0xff,
 705                         .def = 0x04,
 706                 },
 707         }, {
 708                 .id = 0x57,
 709                 .name = "a9avpscw",
 710                 .swgroup = TEGRA_SWGROUP_A9AVP,
 711                 .smmu = {
 712                         .reg = 0x230,
 713                         .bit = 23,
 714                 },
 715                 .la = {
 716                         .reg = 0x3a4,
 717                         .shift = 16,
 718                         .mask = 0xff,
 719                         .def = 0x80,
 720                 },
 721         }, {
 722                 .id = 0x58,
 723                 .name = "gpusrd",
 724                 .swgroup = TEGRA_SWGROUP_GPU,
 725                 .smmu = {
 726                         /* read-only */
 727                         .reg = 0x230,
 728                         .bit = 24,
 729                 },
 730                 .la = {
 731                         .reg = 0x3c8,
 732                         .shift = 0,
 733                         .mask = 0xff,
 734                         .def = 0x1a,
 735                 },
 736         }, {
 737                 .id = 0x59,
 738                 .name = "gpuswr",
 739                 .swgroup = TEGRA_SWGROUP_GPU,
 740                 .smmu = {
 741                         /* read-only */
 742                         .reg = 0x230,
 743                         .bit = 25,
 744                 },
 745                 .la = {
 746                         .reg = 0x3c8,
 747                         .shift = 16,
 748                         .mask = 0xff,
 749                         .def = 0x80,
 750                 },
 751         }, {
 752                 .id = 0x5a,
 753                 .name = "displayt",
 754                 .swgroup = TEGRA_SWGROUP_DC,
 755                 .smmu = {
 756                         .reg = 0x230,
 757                         .bit = 26,
 758                 },
 759                 .la = {
 760                         .reg = 0x2f0,
 761                         .shift = 16,
 762                         .mask = 0xff,
 763                         .def = 0x50,
 764                 },
 765         }, {
 766                 .id = 0x60,
 767                 .name = "sdmmcra",
 768                 .swgroup = TEGRA_SWGROUP_SDMMC1A,
 769                 .smmu = {
 770                         .reg = 0x234,
 771                         .bit = 0,
 772                 },
 773                 .la = {
 774                         .reg = 0x3b8,
 775                         .shift = 0,
 776                         .mask = 0xff,
 777                         .def = 0x49,
 778                 },
 779         }, {
 780                 .id = 0x61,
 781                 .name = "sdmmcraa",
 782                 .swgroup = TEGRA_SWGROUP_SDMMC2A,
 783                 .smmu = {
 784                         .reg = 0x234,
 785                         .bit = 1,
 786                 },
 787                 .la = {
 788                         .reg = 0x3bc,
 789                         .shift = 0,
 790                         .mask = 0xff,
 791                         .def = 0x49,
 792                 },
 793         }, {
 794                 .id = 0x62,
 795                 .name = "sdmmcr",
 796                 .swgroup = TEGRA_SWGROUP_SDMMC3A,
 797                 .smmu = {
 798                         .reg = 0x234,
 799                         .bit = 2,
 800                 },
 801                 .la = {
 802                         .reg = 0x3c0,
 803                         .shift = 0,
 804                         .mask = 0xff,
 805                         .def = 0x49,
 806                 },
 807         }, {
 808                 .id = 0x63,
 809                 .swgroup = TEGRA_SWGROUP_SDMMC4A,
 810                 .name = "sdmmcrab",
 811                 .smmu = {
 812                         .reg = 0x234,
 813                         .bit = 3,
 814                 },
 815                 .la = {
 816                         .reg = 0x3c4,
 817                         .shift = 0,
 818                         .mask = 0xff,
 819                         .def = 0x49,
 820                 },
 821         }, {
 822                 .id = 0x64,
 823                 .name = "sdmmcwa",
 824                 .swgroup = TEGRA_SWGROUP_SDMMC1A,
 825                 .smmu = {
 826                         .reg = 0x234,
 827                         .bit = 4,
 828                 },
 829                 .la = {
 830                         .reg = 0x3b8,
 831                         .shift = 16,
 832                         .mask = 0xff,
 833                         .def = 0x80,
 834                 },
 835         }, {
 836                 .id = 0x65,
 837                 .name = "sdmmcwaa",
 838                 .swgroup = TEGRA_SWGROUP_SDMMC2A,
 839                 .smmu = {
 840                         .reg = 0x234,
 841                         .bit = 5,
 842                 },
 843                 .la = {
 844                         .reg = 0x3bc,
 845                         .shift = 16,
 846                         .mask = 0xff,
 847                         .def = 0x80,
 848                 },
 849         }, {
 850                 .id = 0x66,
 851                 .name = "sdmmcw",
 852                 .swgroup = TEGRA_SWGROUP_SDMMC3A,
 853                 .smmu = {
 854                         .reg = 0x234,
 855                         .bit = 6,
 856                 },
 857                 .la = {
 858                         .reg = 0x3c0,
 859                         .shift = 16,
 860                         .mask = 0xff,
 861                         .def = 0x80,
 862                 },
 863         }, {
 864                 .id = 0x67,
 865                 .name = "sdmmcwab",
 866                 .swgroup = TEGRA_SWGROUP_SDMMC4A,
 867                 .smmu = {
 868                         .reg = 0x234,
 869                         .bit = 7,
 870                 },
 871                 .la = {
 872                         .reg = 0x3c4,
 873                         .shift = 16,
 874                         .mask = 0xff,
 875                         .def = 0x80,
 876                 },
 877         }, {
 878                 .id = 0x6c,
 879                 .name = "vicsrd",
 880                 .swgroup = TEGRA_SWGROUP_VIC,
 881                 .smmu = {
 882                         .reg = 0x234,
 883                         .bit = 12,
 884                 },
 885                 .la = {
 886                         .reg = 0x394,
 887                         .shift = 0,
 888                         .mask = 0xff,
 889                         .def = 0x1a,
 890                 },
 891         }, {
 892                 .id = 0x6d,
 893                 .name = "vicswr",
 894                 .swgroup = TEGRA_SWGROUP_VIC,
 895                 .smmu = {
 896                         .reg = 0x234,
 897                         .bit = 13,
 898                 },
 899                 .la = {
 900                         .reg = 0x394,
 901                         .shift = 16,
 902                         .mask = 0xff,
 903                         .def = 0x80,
 904                 },
 905         }, {
 906                 .id = 0x72,
 907                 .name = "viw",
 908                 .swgroup = TEGRA_SWGROUP_VI,
 909                 .smmu = {
 910                         .reg = 0x234,
 911                         .bit = 18,
 912                 },
 913                 .la = {
 914                         .reg = 0x398,
 915                         .shift = 0,
 916                         .mask = 0xff,
 917                         .def = 0x80,
 918                 },
 919         }, {
 920                 .id = 0x73,
 921                 .name = "displayd",
 922                 .swgroup = TEGRA_SWGROUP_DC,
 923                 .smmu = {
 924                         .reg = 0x234,
 925                         .bit = 19,
 926                 },
 927                 .la = {
 928                         .reg = 0x3c8,
 929                         .shift = 0,
 930                         .mask = 0xff,
 931                         .def = 0x50,
 932                 },
 933         },
 934 };
 935
 936 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
 937         { .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
 938         { .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
 939         { .swgroup = TEGRA_SWGROUP_AFI,       .reg = 0x238 },
 940         { .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
 941         { .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
 942         { .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
 943         { .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },
 944         { .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
 945         { .swgroup = TEGRA_SWGROUP_SATA,      .reg = 0x274 },
 946         { .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },
 947         { .swgroup = TEGRA_SWGROUP_ISP2,      .reg = 0x258 },
 948         { .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
 949         { .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
 950         { .swgroup = TEGRA_SWGROUP_ISP2B,     .reg = 0xaa4 },
 951         { .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
 952         { .swgroup = TEGRA_SWGROUP_A9AVP,     .reg = 0x290 },
 953         { .swgroup = TEGRA_SWGROUP_GPU,       .reg = 0xaac },
 954         { .swgroup = TEGRA_SWGROUP_SDMMC1A,   .reg = 0xa94 },
 955         { .swgroup = TEGRA_SWGROUP_SDMMC2A,   .reg = 0xa98 },
 956         { .swgroup = TEGRA_SWGROUP_SDMMC3A,   .reg = 0xa9c },
 957         { .swgroup = TEGRA_SWGROUP_SDMMC4A,   .reg = 0xaa0 },
 958         { .swgroup = TEGRA_SWGROUP_VIC,       .reg = 0x284 },
 959         { .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
 960 };
 961
 962 #ifdef CONFIG_ARCH_TEGRA_124_SOC
 963 static void tegra124_flush_dcache(struct page *page, unsigned long offset,
 964                                   size_t size)
 965 {
 966         phys_addr_t phys = page_to_phys(page) + offset;
 967         void *virt = page_address(page) + offset;
 968
 969         __cpuc_flush_dcache_area(virt, size);
 970         outer_flush_range(phys, phys + size);
 971 }
 972
 973 static const struct tegra_smmu_ops tegra124_smmu_ops = {
 974         .flush_dcache = tegra124_flush_dcache,
 975 };
 976
 977 static const struct tegra_smmu_soc tegra124_smmu_soc = {
 978         .clients = tegra124_mc_clients,
 979         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
 980         .swgroups = tegra124_swgroups,
 981         .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
 982         .supports_round_robin_arbitration = true,
 983         .supports_request_limit = true,
 984         .num_tlb_lines = 32,
 985         .num_asids = 128,
 986         .ops = &tegra124_smmu_ops,
 987 };
 988
 989 const struct tegra_mc_soc tegra124_mc_soc = {
 990         .clients = tegra124_mc_clients,
 991         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
 992         .num_address_bits = 34,
 993         .atom_size = 32,
 994         .smmu = &tegra124_smmu_soc,
 995 };
 996 #endif /* CONFIG_ARCH_TEGRA_124_SOC */