kernel/drivers/media/usb/cx231xx/cx231xx-417.c

   1 /*
   2  *
   3  *  Support for a cx23417 mpeg encoder via cx231xx host port.
   4  *
   5  *    (c) 2004 Jelle Foks <jelle@foks.us>
   6  *    (c) 2004 Gerd Knorr <kraxel@bytesex.org>
   7  *    (c) 2008 Steven Toth <stoth@linuxtv.org>
   8  *      - CX23885/7/8 support
   9  *
  10  *  Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
  11  *
  12  *  This program is free software; you can redistribute it and/or modify
  13  *  it under the terms of the GNU General Public License as published by
  14  *  the Free Software Foundation; either version 2 of the License, or
  15  *  (at your option) any later version.
  16  *
  17  *  This program is distributed in the hope that it will be useful,
  18  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *  GNU General Public License for more details.
  21  *
  22  *  You should have received a copy of the GNU General Public License
  23  *  along with this program; if not, write to the Free Software
  24  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  */
  26
  27 #include "cx231xx.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/init.h>
  32 #include <linux/fs.h>
  33 #include <linux/delay.h>
  34 #include <linux/device.h>
  35 #include <linux/firmware.h>
  36 #include <linux/vmalloc.h>
  37 #include <media/v4l2-common.h>
  38 #include <media/v4l2-ioctl.h>
  39 #include <media/v4l2-event.h>
  40 #include <media/cx2341x.h>
  41 #include <media/tuner.h>
  42
  43 #define CX231xx_FIRM_IMAGE_SIZE 376836
  44 #define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
  45
  46 /* for polaris ITVC */
  47 #define ITVC_WRITE_DIR          0x03FDFC00
  48 #define ITVC_READ_DIR            0x0001FC00
  49
  50 #define  MCI_MEMORY_DATA_BYTE0          0x00
  51 #define  MCI_MEMORY_DATA_BYTE1          0x08
  52 #define  MCI_MEMORY_DATA_BYTE2          0x10
  53 #define  MCI_MEMORY_DATA_BYTE3          0x18
  54
  55 #define  MCI_MEMORY_ADDRESS_BYTE2       0x20
  56 #define  MCI_MEMORY_ADDRESS_BYTE1       0x28
  57 #define  MCI_MEMORY_ADDRESS_BYTE0       0x30
  58
  59 #define  MCI_REGISTER_DATA_BYTE0        0x40
  60 #define  MCI_REGISTER_DATA_BYTE1        0x48
  61 #define  MCI_REGISTER_DATA_BYTE2        0x50
  62 #define  MCI_REGISTER_DATA_BYTE3        0x58
  63
  64 #define  MCI_REGISTER_ADDRESS_BYTE0     0x60
  65 #define  MCI_REGISTER_ADDRESS_BYTE1     0x68
  66
  67 #define  MCI_REGISTER_MODE              0x70
  68
  69 /* Read and write modes for polaris ITVC */
  70 #define  MCI_MODE_REGISTER_READ         0x000
  71 #define  MCI_MODE_REGISTER_WRITE        0x100
  72 #define  MCI_MODE_MEMORY_READ           0x000
  73 #define  MCI_MODE_MEMORY_WRITE          0x4000
  74
  75 static unsigned int mpegbufs = 8;
  76 module_param(mpegbufs, int, 0644);
  77 MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
  78
  79 static unsigned int mpeglines = 128;
  80 module_param(mpeglines, int, 0644);
  81 MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
  82
  83 static unsigned int mpeglinesize = 512;
  84 module_param(mpeglinesize, int, 0644);
  85 MODULE_PARM_DESC(mpeglinesize,
  86         "number of bytes in each line of an MPEG buffer, range 512-1024");
  87
  88 static unsigned int v4l_debug = 1;
  89 module_param(v4l_debug, int, 0644);
  90 MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
  91
  92 #define dprintk(level, fmt, arg...)     \
  93         do {                            \
  94                 if (v4l_debug >= level) \
  95                         printk(KERN_DEBUG pr_fmt(fmt), ## arg); \
  96         } while (0)
  97
  98 static struct cx231xx_tvnorm cx231xx_tvnorms[] = {
  99         {
 100                 .name      = "NTSC-M",
 101                 .id        = V4L2_STD_NTSC_M,
 102         }, {
 103                 .name      = "NTSC-JP",
 104                 .id        = V4L2_STD_NTSC_M_JP,
 105         }, {
 106                 .name      = "PAL-BG",
 107                 .id        = V4L2_STD_PAL_BG,
 108         }, {
 109                 .name      = "PAL-DK",
 110                 .id        = V4L2_STD_PAL_DK,
 111         }, {
 112                 .name      = "PAL-I",
 113                 .id        = V4L2_STD_PAL_I,
 114         }, {
 115                 .name      = "PAL-M",
 116                 .id        = V4L2_STD_PAL_M,
 117         }, {
 118                 .name      = "PAL-N",
 119                 .id        = V4L2_STD_PAL_N,
 120         }, {
 121                 .name      = "PAL-Nc",
 122                 .id        = V4L2_STD_PAL_Nc,
 123         }, {
 124                 .name      = "PAL-60",
 125                 .id        = V4L2_STD_PAL_60,
 126         }, {
 127                 .name      = "SECAM-L",
 128                 .id        = V4L2_STD_SECAM_L,
 129         }, {
 130                 .name      = "SECAM-DK",
 131                 .id        = V4L2_STD_SECAM_DK,
 132         }
 133 };
 134
 135 /* ------------------------------------------------------------------ */
 136
 137 enum cx231xx_capture_type {
 138         CX231xx_MPEG_CAPTURE,
 139         CX231xx_RAW_CAPTURE,
 140         CX231xx_RAW_PASSTHRU_CAPTURE
 141 };
 142
 143 enum cx231xx_capture_bits {
 144         CX231xx_RAW_BITS_NONE             = 0x00,
 145         CX231xx_RAW_BITS_YUV_CAPTURE      = 0x01,
 146         CX231xx_RAW_BITS_PCM_CAPTURE      = 0x02,
 147         CX231xx_RAW_BITS_VBI_CAPTURE      = 0x04,
 148         CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
 149         CX231xx_RAW_BITS_TO_HOST_CAPTURE  = 0x10
 150 };
 151
 152 enum cx231xx_capture_end {
 153         CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */
 154         CX231xx_END_NOW, /* stop immediately, no irq */
 155 };
 156
 157 enum cx231xx_framerate {
 158         CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */
 159         CX231xx_FRAMERATE_PAL_25   /* PAL: 25fps */
 160 };
 161
 162 enum cx231xx_stream_port {
 163         CX231xx_OUTPUT_PORT_MEMORY,
 164         CX231xx_OUTPUT_PORT_STREAMING,
 165         CX231xx_OUTPUT_PORT_SERIAL
 166 };
 167
 168 enum cx231xx_data_xfer_status {
 169         CX231xx_MORE_BUFFERS_FOLLOW,
 170         CX231xx_LAST_BUFFER,
 171 };
 172
 173 enum cx231xx_picture_mask {
 174         CX231xx_PICTURE_MASK_NONE,
 175         CX231xx_PICTURE_MASK_I_FRAMES,
 176         CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3,
 177         CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7,
 178 };
 179
 180 enum cx231xx_vbi_mode_bits {
 181         CX231xx_VBI_BITS_SLICED,
 182         CX231xx_VBI_BITS_RAW,
 183 };
 184
 185 enum cx231xx_vbi_insertion_bits {
 186         CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
 187         CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
 188         CX231xx_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
 189         CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
 190         CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
 191 };
 192
 193 enum cx231xx_dma_unit {
 194         CX231xx_DMA_BYTES,
 195         CX231xx_DMA_FRAMES,
 196 };
 197
 198 enum cx231xx_dma_transfer_status_bits {
 199         CX231xx_DMA_TRANSFER_BITS_DONE = 0x01,
 200         CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04,
 201         CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
 202 };
 203
 204 enum cx231xx_pause {
 205         CX231xx_PAUSE_ENCODING,
 206         CX231xx_RESUME_ENCODING,
 207 };
 208
 209 enum cx231xx_copyright {
 210         CX231xx_COPYRIGHT_OFF,
 211         CX231xx_COPYRIGHT_ON,
 212 };
 213
 214 enum cx231xx_notification_type {
 215         CX231xx_NOTIFICATION_REFRESH,
 216 };
 217
 218 enum cx231xx_notification_status {
 219         CX231xx_NOTIFICATION_OFF,
 220         CX231xx_NOTIFICATION_ON,
 221 };
 222
 223 enum cx231xx_notification_mailbox {
 224         CX231xx_NOTIFICATION_NO_MAILBOX = -1,
 225 };
 226
 227 enum cx231xx_field1_lines {
 228         CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */
 229         CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */
 230         CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */
 231 };
 232
 233 enum cx231xx_field2_lines {
 234         CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */
 235         CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */
 236         CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */
 237 };
 238
 239 enum cx231xx_custom_data_type {
 240         CX231xx_CUSTOM_EXTENSION_USR_DATA,
 241         CX231xx_CUSTOM_PRIVATE_PACKET,
 242 };
 243
 244 enum cx231xx_mute {
 245         CX231xx_UNMUTE,
 246         CX231xx_MUTE,
 247 };
 248
 249 enum cx231xx_mute_video_mask {
 250         CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00,
 251         CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000,
 252         CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000,
 253 };
 254
 255 enum cx231xx_mute_video_shift {
 256         CX231xx_MUTE_VIDEO_V_SHIFT = 8,
 257         CX231xx_MUTE_VIDEO_U_SHIFT = 16,
 258         CX231xx_MUTE_VIDEO_Y_SHIFT = 24,
 259 };
 260
 261 /* defines below are from ivtv-driver.h */
 262 #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
 263
 264 /* Firmware API commands */
 265 #define IVTV_API_STD_TIMEOUT 500
 266
 267 /* Registers */
 268 /* IVTV_REG_OFFSET */
 269 #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
 270 #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
 271 #define IVTV_REG_SPU (0x9050)
 272 #define IVTV_REG_HW_BLOCKS (0x9054)
 273 #define IVTV_REG_VPU (0x9058)
 274 #define IVTV_REG_APU (0xA064)
 275
 276 /*
 277  * Bit definitions for MC417_RWD and MC417_OEN registers
 278  *
 279  * bits 31-16
 280  *+-----------+
 281  *| Reserved  |
 282  *|+-----------+
 283  *|  bit 15  bit 14  bit 13 bit 12  bit 11  bit 10  bit 9   bit 8
 284  *|+-------+-------+-------+-------+-------+-------+-------+-------+
 285  *|| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
 286  *|+-------+-------+-------+-------+-------+-------+-------+-------+
 287  *| bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
 288  *|+-------+-------+-------+-------+-------+-------+-------+-------+
 289  *||MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
 290  *|+-------+-------+-------+-------+-------+-------+-------+-------+
 291  */
 292 #define MC417_MIWR      0x8000
 293 #define MC417_MIRD      0x4000
 294 #define MC417_MICS      0x2000
 295 #define MC417_MIRDY     0x1000
 296 #define MC417_MIADDR    0x0F00
 297 #define MC417_MIDATA    0x00FF
 298
 299
 300 /* Bit definitions for MC417_CTL register ****
 301  *bits 31-6   bits 5-4   bit 3    bits 2-1       Bit 0
 302  *+--------+-------------+--------+--------------+------------+
 303  *|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
 304  *+--------+-------------+--------+--------------+------------+
 305  */
 306 #define MC417_SPD_CTL(x)        (((x) << 4) & 0x00000030)
 307 #define MC417_GPIO_SEL(x)       (((x) << 1) & 0x00000006)
 308 #define MC417_UART_GPIO_EN      0x00000001
 309
 310 /* Values for speed control */
 311 #define MC417_SPD_CTL_SLOW      0x1
 312 #define MC417_SPD_CTL_MEDIUM    0x0
 313 #define MC417_SPD_CTL_FAST      0x3     /* b'1x, but we use b'11 */
 314
 315 /* Values for GPIO select */
 316 #define MC417_GPIO_SEL_GPIO3    0x3
 317 #define MC417_GPIO_SEL_GPIO2    0x2
 318 #define MC417_GPIO_SEL_GPIO1    0x1
 319 #define MC417_GPIO_SEL_GPIO0    0x0
 320
 321
 322 #define CX23417_GPIO_MASK 0xFC0003FF
 323
 324 static int set_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 value)
 325 {
 326         int status = 0;
 327         u32 _gpio_direction = 0;
 328
 329         _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
 330         _gpio_direction = _gpio_direction | gpio_direction;
 331         status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
 332                          (u8 *)&value, 4, 0, 0);
 333         return status;
 334 }
 335
 336 static int get_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 *val_ptr)
 337 {
 338         int status = 0;
 339         u32 _gpio_direction = 0;
 340
 341         _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
 342         _gpio_direction = _gpio_direction | gpio_direction;
 343
 344         status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
 345                  (u8 *)val_ptr, 4, 0, 1);
 346         return status;
 347 }
 348
 349 static int wait_for_mci_complete(struct cx231xx *dev)
 350 {
 351         u32 gpio;
 352         u32 gpio_direction = 0;
 353         u8 count = 0;
 354         get_itvc_reg(dev, gpio_direction, &gpio);
 355
 356         while (!(gpio&0x020000)) {
 357                 msleep(10);
 358
 359                 get_itvc_reg(dev, gpio_direction, &gpio);
 360
 361                 if (count++ > 100) {
 362                         dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio);
 363                         return -1;
 364                 }
 365         }
 366         return 0;
 367 }
 368
 369 static int mc417_register_write(struct cx231xx *dev, u16 address, u32 value)
 370 {
 371         u32 temp;
 372         int status = 0;
 373
 374         temp = 0x82 | MCI_REGISTER_DATA_BYTE0 | ((value & 0x000000FF) << 8);
 375         temp = temp << 10;
 376         status = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 377         if (status < 0)
 378                 return status;
 379         temp = temp | (0x05 << 10);
 380         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 381
 382         /*write data byte 1;*/
 383         temp = 0x82 | MCI_REGISTER_DATA_BYTE1 | (value & 0x0000FF00);
 384         temp = temp << 10;
 385         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 386         temp = temp | (0x05 << 10);
 387         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 388
 389         /*write data byte 2;*/
 390         temp = 0x82 | MCI_REGISTER_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
 391         temp = temp << 10;
 392         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 393         temp = temp | (0x05 << 10);
 394         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 395
 396         /*write data byte 3;*/
 397         temp = 0x82 | MCI_REGISTER_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
 398         temp = temp << 10;
 399         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 400         temp = temp | (0x05 << 10);
 401         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 402
 403         /*write address byte 0;*/
 404         temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x000000FF) << 8);
 405         temp = temp << 10;
 406         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 407         temp = temp | (0x05 << 10);
 408         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 409
 410         /*write address byte 1;*/
 411         temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0x0000FF00);
 412         temp = temp << 10;
 413         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 414         temp = temp | (0x05 << 10);
 415         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 416
 417         /*Write that the mode is write.*/
 418         temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE;
 419         temp = temp << 10;
 420         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 421         temp = temp | (0x05 << 10);
 422         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 423
 424         return wait_for_mci_complete(dev);
 425 }
 426
 427 static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value)
 428 {
 429         /*write address byte 0;*/
 430         u32 temp;
 431         u32 return_value = 0;
 432         int ret = 0;
 433
 434         temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
 435         temp = temp << 10;
 436         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 437         temp = temp | ((0x05) << 10);
 438         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 439
 440         /*write address byte 1;*/
 441         temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00);
 442         temp = temp << 10;
 443         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 444         temp = temp | ((0x05) << 10);
 445         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 446
 447         /*write that the mode is read;*/
 448         temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ;
 449         temp = temp << 10;
 450         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 451         temp = temp | ((0x05) << 10);
 452         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 453
 454         /*wait for the MIRDY line to be asserted ,
 455         signalling that the read is done;*/
 456         ret = wait_for_mci_complete(dev);
 457
 458         /*switch the DATA- GPIO to input mode;*/
 459
 460         /*Read data byte 0;*/
 461         temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10;
 462         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 463         temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10);
 464         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 465         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 466         return_value |= ((temp & 0x03FC0000) >> 18);
 467         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 468
 469         /* Read data byte 1;*/
 470         temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10;
 471         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 472         temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10);
 473         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 474         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 475
 476         return_value |= ((temp & 0x03FC0000) >> 10);
 477         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 478
 479         /*Read data byte 2;*/
 480         temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10;
 481         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 482         temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10);
 483         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 484         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 485         return_value |= ((temp & 0x03FC0000) >> 2);
 486         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 487
 488         /*Read data byte 3;*/
 489         temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10;
 490         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 491         temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10);
 492         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 493         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 494         return_value |= ((temp & 0x03FC0000) << 6);
 495         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 496
 497         *value  = return_value;
 498         return ret;
 499 }
 500
 501 static int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value)
 502 {
 503         /*write data byte 0;*/
 504
 505         u32 temp;
 506         int ret = 0;
 507
 508         temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8);
 509         temp = temp << 10;
 510         ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 511         if (ret < 0)
 512                 return ret;
 513         temp = temp | (0x05 << 10);
 514         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 515
 516         /*write data byte 1;*/
 517         temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
 518         temp = temp << 10;
 519         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 520         temp = temp | (0x05 << 10);
 521         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 522
 523         /*write data byte 2;*/
 524         temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
 525         temp = temp << 10;
 526         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 527         temp = temp | (0x05 << 10);
 528         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 529
 530         /*write data byte 3;*/
 531         temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
 532         temp = temp << 10;
 533         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 534         temp = temp | (0x05 << 10);
 535         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 536
 537         /* write address byte 2;*/
 538         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
 539                 ((address & 0x003F0000) >> 8);
 540         temp = temp << 10;
 541         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 542         temp = temp | (0x05 << 10);
 543         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 544
 545         /* write address byte 1;*/
 546         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
 547         temp = temp << 10;
 548         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 549         temp = temp | (0x05 << 10);
 550         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 551
 552         /* write address byte 0;*/
 553         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
 554         temp = temp << 10;
 555         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 556         temp = temp | (0x05 << 10);
 557         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 558
 559         /*wait for MIRDY line;*/
 560         wait_for_mci_complete(dev);
 561
 562         return 0;
 563 }
 564
 565 static int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value)
 566 {
 567         u32 temp = 0;
 568         u32 return_value = 0;
 569         int ret = 0;
 570
 571         /*write address byte 2;*/
 572         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ |
 573                 ((address & 0x003F0000) >> 8);
 574         temp = temp << 10;
 575         ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 576         if (ret < 0)
 577                 return ret;
 578         temp = temp | (0x05 << 10);
 579         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 580
 581         /*write address byte 1*/
 582         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
 583         temp = temp << 10;
 584         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 585         temp = temp | (0x05 << 10);
 586         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 587
 588         /*write address byte 0*/
 589         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
 590         temp = temp << 10;
 591         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 592         temp = temp | (0x05 << 10);
 593         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 594
 595         /*Wait for MIRDY line*/
 596         ret = wait_for_mci_complete(dev);
 597
 598
 599         /*Read data byte 3;*/
 600         temp = (0x82 | MCI_MEMORY_DATA_BYTE3) << 10;
 601         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 602         temp = ((0x81 | MCI_MEMORY_DATA_BYTE3) << 10);
 603         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 604         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 605         return_value |= ((temp & 0x03FC0000) << 6);
 606         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 607
 608         /*Read data byte 2;*/
 609         temp = (0x82 | MCI_MEMORY_DATA_BYTE2) << 10;
 610         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 611         temp = ((0x81 | MCI_MEMORY_DATA_BYTE2) << 10);
 612         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 613         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 614         return_value |= ((temp & 0x03FC0000) >> 2);
 615         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 616
 617         /* Read data byte 1;*/
 618         temp = (0x82 | MCI_MEMORY_DATA_BYTE1) << 10;
 619         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 620         temp = ((0x81 | MCI_MEMORY_DATA_BYTE1) << 10);
 621         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 622         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 623         return_value |= ((temp & 0x03FC0000) >> 10);
 624         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 625
 626         /*Read data byte 0;*/
 627         temp = (0x82 | MCI_MEMORY_DATA_BYTE0) << 10;
 628         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 629         temp = ((0x81 | MCI_MEMORY_DATA_BYTE0) << 10);
 630         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 631         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 632         return_value |= ((temp & 0x03FC0000) >> 18);
 633         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 634
 635         *value  = return_value;
 636         return ret;
 637 }
 638
 639 /* ------------------------------------------------------------------ */
 640
 641 /* MPEG encoder API */
 642 static char *cmd_to_str(int cmd)
 643 {
 644         switch (cmd) {
 645         case CX2341X_ENC_PING_FW:
 646                 return "PING_FW";
 647         case CX2341X_ENC_START_CAPTURE:
 648                 return "START_CAPTURE";
 649         case CX2341X_ENC_STOP_CAPTURE:
 650                 return "STOP_CAPTURE";
 651         case CX2341X_ENC_SET_AUDIO_ID:
 652                 return "SET_AUDIO_ID";
 653         case CX2341X_ENC_SET_VIDEO_ID:
 654                 return "SET_VIDEO_ID";
 655         case CX2341X_ENC_SET_PCR_ID:
 656                 return "SET_PCR_PID";
 657         case CX2341X_ENC_SET_FRAME_RATE:
 658                 return "SET_FRAME_RATE";
 659         case CX2341X_ENC_SET_FRAME_SIZE:
 660                 return "SET_FRAME_SIZE";
 661         case CX2341X_ENC_SET_BIT_RATE:
 662                 return "SET_BIT_RATE";
 663         case CX2341X_ENC_SET_GOP_PROPERTIES:
 664                 return "SET_GOP_PROPERTIES";
 665         case CX2341X_ENC_SET_ASPECT_RATIO:
 666                 return "SET_ASPECT_RATIO";
 667         case CX2341X_ENC_SET_DNR_FILTER_MODE:
 668                 return "SET_DNR_FILTER_PROPS";
 669         case CX2341X_ENC_SET_DNR_FILTER_PROPS:
 670                 return "SET_DNR_FILTER_PROPS";
 671         case CX2341X_ENC_SET_CORING_LEVELS:
 672                 return "SET_CORING_LEVELS";
 673         case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
 674                 return "SET_SPATIAL_FILTER_TYPE";
 675         case CX2341X_ENC_SET_VBI_LINE:
 676                 return "SET_VBI_LINE";
 677         case CX2341X_ENC_SET_STREAM_TYPE:
 678                 return "SET_STREAM_TYPE";
 679         case CX2341X_ENC_SET_OUTPUT_PORT:
 680                 return "SET_OUTPUT_PORT";
 681         case CX2341X_ENC_SET_AUDIO_PROPERTIES:
 682                 return "SET_AUDIO_PROPERTIES";
 683         case CX2341X_ENC_HALT_FW:
 684                 return "HALT_FW";
 685         case CX2341X_ENC_GET_VERSION:
 686                 return "GET_VERSION";
 687         case CX2341X_ENC_SET_GOP_CLOSURE:
 688                 return "SET_GOP_CLOSURE";
 689         case CX2341X_ENC_GET_SEQ_END:
 690                 return "GET_SEQ_END";
 691         case CX2341X_ENC_SET_PGM_INDEX_INFO:
 692                 return "SET_PGM_INDEX_INFO";
 693         case CX2341X_ENC_SET_VBI_CONFIG:
 694                 return "SET_VBI_CONFIG";
 695         case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
 696                 return "SET_DMA_BLOCK_SIZE";
 697         case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
 698                 return "GET_PREV_DMA_INFO_MB_10";
 699         case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
 700                 return "GET_PREV_DMA_INFO_MB_9";
 701         case CX2341X_ENC_SCHED_DMA_TO_HOST:
 702                 return "SCHED_DMA_TO_HOST";
 703         case CX2341X_ENC_INITIALIZE_INPUT:
 704                 return "INITIALIZE_INPUT";
 705         case CX2341X_ENC_SET_FRAME_DROP_RATE:
 706                 return "SET_FRAME_DROP_RATE";
 707         case CX2341X_ENC_PAUSE_ENCODER:
 708                 return "PAUSE_ENCODER";
 709         case CX2341X_ENC_REFRESH_INPUT:
 710                 return "REFRESH_INPUT";
 711         case CX2341X_ENC_SET_COPYRIGHT:
 712                 return "SET_COPYRIGHT";
 713         case CX2341X_ENC_SET_EVENT_NOTIFICATION:
 714                 return "SET_EVENT_NOTIFICATION";
 715         case CX2341X_ENC_SET_NUM_VSYNC_LINES:
 716                 return "SET_NUM_VSYNC_LINES";
 717         case CX2341X_ENC_SET_PLACEHOLDER:
 718                 return "SET_PLACEHOLDER";
 719         case CX2341X_ENC_MUTE_VIDEO:
 720                 return "MUTE_VIDEO";
 721         case CX2341X_ENC_MUTE_AUDIO:
 722                 return "MUTE_AUDIO";
 723         case CX2341X_ENC_MISC:
 724                 return "MISC";
 725         default:
 726                 return "UNKNOWN";
 727         }
 728 }
 729
 730 static int cx231xx_mbox_func(void *priv, u32 command, int in, int out,
 731                              u32 data[CX2341X_MBOX_MAX_DATA])
 732 {
 733         struct cx231xx *dev = priv;
 734         unsigned long timeout;
 735         u32 value, flag, retval = 0;
 736         int i;
 737
 738         dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
 739                 cmd_to_str(command));
 740
 741         /* this may not be 100% safe if we can't read any memory location
 742            without side effects */
 743         mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
 744         if (value != 0x12345678) {
 745                 dprintk(3, "Firmware and/or mailbox pointer not initialized or corrupted, signature = 0x%x, cmd = %s\n",
 746                         value, cmd_to_str(command));
 747                 return -EIO;
 748         }
 749
 750         /* This read looks at 32 bits, but flag is only 8 bits.
 751          * Seems we also bail if CMD or TIMEOUT bytes are set???
 752          */
 753         mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
 754         if (flag) {
 755                 dprintk(3, "ERROR: Mailbox appears to be in use (%x), cmd = %s\n",
 756                                 flag, cmd_to_str(command));
 757                 return -EBUSY;
 758         }
 759
 760         flag |= 1; /* tell 'em we're working on it */
 761         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 762
 763         /* write command + args + fill remaining with zeros */
 764         /* command code */
 765         mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
 766         mc417_memory_write(dev, dev->cx23417_mailbox + 3,
 767                 IVTV_API_STD_TIMEOUT); /* timeout */
 768         for (i = 0; i < in; i++) {
 769                 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
 770                 dprintk(3, "API Input %d = %d\n", i, data[i]);
 771         }
 772         for (; i < CX2341X_MBOX_MAX_DATA; i++)
 773                 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
 774
 775         flag |= 3; /* tell 'em we're done writing */
 776         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 777
 778         /* wait for firmware to handle the API command */
 779         timeout = jiffies + msecs_to_jiffies(10);
 780         for (;;) {
 781                 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
 782                 if (0 != (flag & 4))
 783                         break;
 784                 if (time_after(jiffies, timeout)) {
 785                         dprintk(3, "ERROR: API Mailbox timeout\n");
 786                         return -EIO;
 787                 }
 788                 udelay(10);
 789         }
 790
 791         /* read output values */
 792         for (i = 0; i < out; i++) {
 793                 mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
 794                 dprintk(3, "API Output %d = %d\n", i, data[i]);
 795         }
 796
 797         mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
 798         dprintk(3, "API result = %d\n", retval);
 799
 800         flag = 0;
 801         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 802
 803         return 0;
 804 }
 805
 806 /* We don't need to call the API often, so using just one
 807  * mailbox will probably suffice
 808  */
 809 static int cx231xx_api_cmd(struct cx231xx *dev, u32 command,
 810                 u32 inputcnt, u32 outputcnt, ...)
 811 {
 812         u32 data[CX2341X_MBOX_MAX_DATA];
 813         va_list vargs;
 814         int i, err;
 815
 816         dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
 817
 818         va_start(vargs, outputcnt);
 819         for (i = 0; i < inputcnt; i++)
 820                 data[i] = va_arg(vargs, int);
 821
 822         err = cx231xx_mbox_func(dev, command, inputcnt, outputcnt, data);
 823         for (i = 0; i < outputcnt; i++) {
 824                 int *vptr = va_arg(vargs, int *);
 825                 *vptr = data[i];
 826         }
 827         va_end(vargs);
 828
 829         return err;
 830 }
 831
 832
 833 static int cx231xx_find_mailbox(struct cx231xx *dev)
 834 {
 835         u32 signature[4] = {
 836                 0x12345678, 0x34567812, 0x56781234, 0x78123456
 837         };
 838         int signaturecnt = 0;
 839         u32 value;
 840         int i;
 841         int ret = 0;
 842
 843         dprintk(2, "%s()\n", __func__);
 844
 845         for (i = 0; i < 0x100; i++) {/*CX231xx_FIRM_IMAGE_SIZE*/
 846                 ret = mc417_memory_read(dev, i, &value);
 847                 if (ret < 0)
 848                         return ret;
 849                 if (value == signature[signaturecnt])
 850                         signaturecnt++;
 851                 else
 852                         signaturecnt = 0;
 853                 if (4 == signaturecnt) {
 854                         dprintk(1, "Mailbox signature found at 0x%x\n", i + 1);
 855                         return i + 1;
 856                 }
 857         }
 858         dprintk(3, "Mailbox signature values not found!\n");
 859         return -1;
 860 }
 861
 862 static void mci_write_memory_to_gpio(struct cx231xx *dev, u32 address, u32 value,
 863                 u32 *p_fw_image)
 864 {
 865         u32 temp = 0;
 866         int i = 0;
 867
 868         temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8);
 869         temp = temp << 10;
 870         *p_fw_image = temp;
 871         p_fw_image++;
 872         temp = temp | (0x05 << 10);
 873         *p_fw_image = temp;
 874         p_fw_image++;
 875
 876         /*write data byte 1;*/
 877         temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
 878         temp = temp << 10;
 879         *p_fw_image = temp;
 880         p_fw_image++;
 881         temp = temp | (0x05 << 10);
 882         *p_fw_image = temp;
 883         p_fw_image++;
 884
 885         /*write data byte 2;*/
 886         temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
 887         temp = temp << 10;
 888         *p_fw_image = temp;
 889         p_fw_image++;
 890         temp = temp | (0x05 << 10);
 891         *p_fw_image = temp;
 892         p_fw_image++;
 893
 894         /*write data byte 3;*/
 895         temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
 896         temp = temp << 10;
 897         *p_fw_image = temp;
 898         p_fw_image++;
 899         temp = temp | (0x05 << 10);
 900         *p_fw_image = temp;
 901         p_fw_image++;
 902
 903         /* write address byte 2;*/
 904         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
 905                 ((address & 0x003F0000) >> 8);
 906         temp = temp << 10;
 907         *p_fw_image = temp;
 908         p_fw_image++;
 909         temp = temp | (0x05 << 10);
 910         *p_fw_image = temp;
 911         p_fw_image++;
 912
 913         /* write address byte 1;*/
 914         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
 915         temp = temp << 10;
 916         *p_fw_image = temp;
 917         p_fw_image++;
 918         temp = temp | (0x05 << 10);
 919         *p_fw_image = temp;
 920         p_fw_image++;
 921
 922         /* write address byte 0;*/
 923         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
 924         temp = temp << 10;
 925         *p_fw_image = temp;
 926         p_fw_image++;
 927         temp = temp | (0x05 << 10);
 928         *p_fw_image = temp;
 929         p_fw_image++;
 930
 931         for (i = 0; i < 6; i++) {
 932                 *p_fw_image = 0xFFFFFFFF;
 933                 p_fw_image++;
 934         }
 935 }
 936
 937
 938 static int cx231xx_load_firmware(struct cx231xx *dev)
 939 {
 940         static const unsigned char magic[8] = {
 941                 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
 942         };
 943         const struct firmware *firmware;
 944         int i, retval = 0;
 945         u32 value = 0;
 946         u32 gpio_output = 0;
 947         /*u32 checksum = 0;*/
 948         /*u32 *dataptr;*/
 949         u32 transfer_size = 0;
 950         u32 fw_data = 0;
 951         u32 address = 0;
 952         /*u32 current_fw[800];*/
 953         u32 *p_current_fw, *p_fw;
 954         u32 *p_fw_data;
 955         int frame = 0;
 956         u16 _buffer_size = 4096;
 957         u8 *p_buffer;
 958
 959         p_current_fw = vmalloc(1884180 * 4);
 960         p_fw = p_current_fw;
 961         if (p_current_fw == NULL) {
 962                 dprintk(2, "FAIL!!!\n");
 963                 return -1;
 964         }
 965
 966         p_buffer = vmalloc(4096);
 967         if (p_buffer == NULL) {
 968                 dprintk(2, "FAIL!!!\n");
 969                 return -1;
 970         }
 971
 972         dprintk(2, "%s()\n", __func__);
 973
 974         /* Save GPIO settings before reset of APU */
 975         retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
 976         retval |= mc417_memory_read(dev, 0x900C, &value);
 977
 978         retval  = mc417_register_write(dev,
 979                 IVTV_REG_VPU, 0xFFFFFFED);
 980         retval |= mc417_register_write(dev,
 981                 IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
 982         retval |= mc417_register_write(dev,
 983                 IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
 984         retval |= mc417_register_write(dev,
 985                 IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
 986         retval |= mc417_register_write(dev,
 987                 IVTV_REG_APU, 0);
 988
 989         if (retval != 0) {
 990                 dev_err(dev->dev,
 991                         "%s: Error with mc417_register_write\n", __func__);
 992                 return -1;
 993         }
 994
 995         retval = request_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME,
 996                                   dev->dev);
 997
 998         if (retval != 0) {
 999                 dev_err(dev->dev,
1000                         "ERROR: Hotplug firmware request failed (%s).\n",
1001                         CX231xx_FIRM_IMAGE_NAME);
1002                 dev_err(dev->dev,
1003                         "Please fix your hotplug setup, the board will not work without firmware loaded!\n");
1004                 return -1;
1005         }
1006
1007         if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) {
1008                 dev_err(dev->dev,
1009                         "ERROR: Firmware size mismatch (have %zd, expected %d)\n",
1010                         firmware->size, CX231xx_FIRM_IMAGE_SIZE);
1011                 release_firmware(firmware);
1012                 return -1;
1013         }
1014
1015         if (0 != memcmp(firmware->data, magic, 8)) {
1016                 dev_err(dev->dev,
1017                         "ERROR: Firmware magic mismatch, wrong file?\n");
1018                 release_firmware(firmware);
1019                 return -1;
1020         }
1021
1022         initGPIO(dev);
1023
1024         /* transfer to the chip */
1025         dprintk(2, "Loading firmware to GPIO...\n");
1026         p_fw_data = (u32 *)firmware->data;
1027         dprintk(2, "firmware->size=%zd\n", firmware->size);
1028         for (transfer_size = 0; transfer_size < firmware->size;
1029                  transfer_size += 4) {
1030                 fw_data = *p_fw_data;
1031
1032                 mci_write_memory_to_gpio(dev, address, fw_data, p_current_fw);
1033                 address = address + 1;
1034                 p_current_fw += 20;
1035                 p_fw_data += 1;
1036         }
1037
1038         /*download the firmware by ep5-out*/
1039
1040         for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size);
1041              frame++) {
1042                 for (i = 0; i < _buffer_size; i++) {
1043                         *(p_buffer + i) = (u8)(*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x000000FF);
1044                         i++;
1045                         *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x0000FF00) >> 8);
1046                         i++;
1047                         *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x00FF0000) >> 16);
1048                         i++;
1049                         *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0xFF000000) >> 24);
1050                 }
1051                 cx231xx_ep5_bulkout(dev, p_buffer, _buffer_size);
1052         }
1053
1054         p_current_fw = p_fw;
1055         vfree(p_current_fw);
1056         p_current_fw = NULL;
1057         uninitGPIO(dev);
1058         release_firmware(firmware);
1059         dprintk(1, "Firmware upload successful.\n");
1060
1061         retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
1062                 IVTV_CMD_HW_BLOCKS_RST);
1063         if (retval < 0) {
1064                 dev_err(dev->dev,
1065                         "%s: Error with mc417_register_write\n",
1066                         __func__);
1067                 return retval;
1068         }
1069         /* F/W power up disturbs the GPIOs, restore state */
1070         retval |= mc417_register_write(dev, 0x9020, gpio_output);
1071         retval |= mc417_register_write(dev, 0x900C, value);
1072
1073         retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
1074         retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
1075
1076         if (retval < 0) {
1077                 dev_err(dev->dev,
1078                         "%s: Error with mc417_register_write\n",
1079                         __func__);
1080                 return retval;
1081         }
1082         return 0;
1083 }
1084
1085 static void cx231xx_417_check_encoder(struct cx231xx *dev)
1086 {
1087         u32 status, seq;
1088
1089         status = 0;
1090         seq = 0;
1091         cx231xx_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
1092         dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
1093 }
1094
1095 static void cx231xx_codec_settings(struct cx231xx *dev)
1096 {
1097         dprintk(1, "%s()\n", __func__);
1098
1099         /* assign frame size */
1100         cx231xx_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1101                                 dev->ts1.height, dev->ts1.width);
1102
1103         dev->mpeg_ctrl_handler.width = dev->ts1.width;
1104         dev->mpeg_ctrl_handler.height = dev->ts1.height;
1105
1106         cx2341x_handler_setup(&dev->mpeg_ctrl_handler);
1107
1108         cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1109         cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1110 }
1111
1112 static int cx231xx_initialize_codec(struct cx231xx *dev)
1113 {
1114         int version;
1115         int retval;
1116         u32 i;
1117         u32 val = 0;
1118
1119         dprintk(1, "%s()\n", __func__);
1120         cx231xx_disable656(dev);
1121         retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1122         if (retval < 0) {
1123                 dprintk(2, "%s: PING OK\n", __func__);
1124                 retval = cx231xx_load_firmware(dev);
1125                 if (retval < 0) {
1126                         dev_err(dev->dev,
1127                                 "%s: f/w load failed\n", __func__);
1128                         return retval;
1129                 }
1130                 retval = cx231xx_find_mailbox(dev);
1131                 if (retval < 0) {
1132                         dev_err(dev->dev, "%s: mailbox < 0, error\n",
1133                                 __func__);
1134                         return -1;
1135                 }
1136                 dev->cx23417_mailbox = retval;
1137                 retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1138                 if (retval < 0) {
1139                         dev_err(dev->dev,
1140                                 "ERROR: cx23417 firmware ping failed!\n");
1141                         return -1;
1142                 }
1143                 retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1144                         &version);
1145                 if (retval < 0) {
1146                         dev_err(dev->dev,
1147                                 "ERROR: cx23417 firmware get encoder: version failed!\n");
1148                         return -1;
1149                 }
1150                 dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1151                 msleep(200);
1152         }
1153
1154         for (i = 0; i < 1; i++) {
1155                 retval = mc417_register_read(dev, 0x20f8, &val);
1156                 dprintk(3, "***before enable656() VIM Capture Lines = %d ***\n",
1157                                  val);
1158                 if (retval < 0)
1159                         return retval;
1160         }
1161
1162         cx231xx_enable656(dev);
1163                         /* stop mpeg capture */
1164                         cx231xx_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE,
1165                                  3, 0, 1, 3, 4);
1166
1167         cx231xx_codec_settings(dev);
1168         msleep(60);
1169
1170 /*      cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1171                 CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115);
1172         cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1173                 CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1174                 0, 0);
1175 */
1176
1177 #if 0
1178         /* TODO */
1179         u32 data[7];
1180
1181         /* Setup to capture VBI */
1182         data[0] = 0x0001BD00;
1183         data[1] = 1;          /* frames per interrupt */
1184         data[2] = 4;          /* total bufs */
1185         data[3] = 0x91559155; /* start codes */
1186         data[4] = 0x206080C0; /* stop codes */
1187         data[5] = 6;          /* lines */
1188         data[6] = 64;         /* BPL */
1189
1190         cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1191                 data[2], data[3], data[4], data[5], data[6]);
1192
1193         for (i = 2; i <= 24; i++) {
1194                 int valid;
1195
1196                 valid = ((i >= 19) && (i <= 21));
1197                 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1198                                 valid, 0 , 0, 0);
1199                 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1200                                 i | 0x80000000, valid, 0, 0, 0);
1201         }
1202 #endif
1203 /*      cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE);
1204         msleep(60);
1205 */
1206         /* initialize the video input */
1207         retval = cx231xx_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1208         if (retval < 0)
1209                 return retval;
1210         msleep(60);
1211
1212         /* Enable VIP style pixel invalidation so we work with scaled mode */
1213         mc417_memory_write(dev, 2120, 0x00000080);
1214
1215         /* start capturing to the host interface */
1216         retval = cx231xx_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1217                 CX231xx_MPEG_CAPTURE, CX231xx_RAW_BITS_NONE);
1218         if (retval < 0)
1219                 return retval;
1220         msleep(10);
1221
1222         for (i = 0; i < 1; i++) {
1223                 mc417_register_read(dev, 0x20f8, &val);
1224                 dprintk(3, "***VIM Capture Lines =%d ***\n", val);
1225         }
1226
1227         return 0;
1228 }
1229
1230 /* ------------------------------------------------------------------ */
1231
1232 static int bb_buf_setup(struct videobuf_queue *q,
1233         unsigned int *count, unsigned int *size)
1234 {
1235         struct cx231xx_fh *fh = q->priv_data;
1236
1237         fh->dev->ts1.ts_packet_size  = mpeglinesize;
1238         fh->dev->ts1.ts_packet_count = mpeglines;
1239
1240         *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1241         *count = mpegbufs;
1242
1243         return 0;
1244 }
1245
1246 static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
1247 {
1248         struct cx231xx_fh *fh = vq->priv_data;
1249         struct cx231xx *dev = fh->dev;
1250         unsigned long flags = 0;
1251
1252         if (in_interrupt())
1253                 BUG();
1254
1255         spin_lock_irqsave(&dev->video_mode.slock, flags);
1256         if (dev->USE_ISO) {
1257                 if (dev->video_mode.isoc_ctl.buf == buf)
1258                         dev->video_mode.isoc_ctl.buf = NULL;
1259         } else {
1260                 if (dev->video_mode.bulk_ctl.buf == buf)
1261                         dev->video_mode.bulk_ctl.buf = NULL;
1262         }
1263         spin_unlock_irqrestore(&dev->video_mode.slock, flags);
1264         videobuf_waiton(vq, &buf->vb, 0, 0);
1265         videobuf_vmalloc_free(&buf->vb);
1266         buf->vb.state = VIDEOBUF_NEEDS_INIT;
1267 }
1268
1269 static void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *urb,
1270                 struct cx231xx_dmaqueue *dma_q)
1271 {
1272         void *vbuf;
1273         struct cx231xx_buffer *buf;
1274         u32 tail_data = 0;
1275         char *p_data;
1276
1277         if (dma_q->mpeg_buffer_done == 0) {
1278                 if (list_empty(&dma_q->active))
1279                         return;
1280
1281                 buf = list_entry(dma_q->active.next,
1282                                 struct cx231xx_buffer, vb.queue);
1283                 dev->video_mode.isoc_ctl.buf = buf;
1284                 dma_q->mpeg_buffer_done = 1;
1285         }
1286         /* Fill buffer */
1287         buf = dev->video_mode.isoc_ctl.buf;
1288         vbuf = videobuf_to_vmalloc(&buf->vb);
1289
1290         if ((dma_q->mpeg_buffer_completed+len) <
1291                         mpeglines*mpeglinesize) {
1292                 if (dma_q->add_ps_package_head ==
1293                                 CX231XX_NEED_ADD_PS_PACKAGE_HEAD) {
1294                         memcpy(vbuf+dma_q->mpeg_buffer_completed,
1295                                         dma_q->ps_head, 3);
1296                         dma_q->mpeg_buffer_completed =
1297                                 dma_q->mpeg_buffer_completed + 3;
1298                         dma_q->add_ps_package_head =
1299                                 CX231XX_NONEED_PS_PACKAGE_HEAD;
1300                 }
1301                 memcpy(vbuf+dma_q->mpeg_buffer_completed, data, len);
1302                 dma_q->mpeg_buffer_completed =
1303                         dma_q->mpeg_buffer_completed + len;
1304         } else {
1305                 dma_q->mpeg_buffer_done = 0;
1306
1307                 tail_data =
1308                         mpeglines*mpeglinesize - dma_q->mpeg_buffer_completed;
1309                 memcpy(vbuf+dma_q->mpeg_buffer_completed,
1310                                 data, tail_data);
1311
1312                 buf->vb.state = VIDEOBUF_DONE;
1313                 buf->vb.field_count++;
1314                 v4l2_get_timestamp(&buf->vb.ts);
1315                 list_del(&buf->vb.queue);
1316                 wake_up(&buf->vb.done);
1317                 dma_q->mpeg_buffer_completed = 0;
1318
1319                 if (len - tail_data > 0) {
1320                         p_data = data + tail_data;
1321                         dma_q->left_data_count = len - tail_data;
1322                         memcpy(dma_q->p_left_data,
1323                                         p_data, len - tail_data);
1324                 }
1325         }
1326 }
1327
1328 static void buffer_filled(char *data, int len, struct urb *urb,
1329                 struct cx231xx_dmaqueue *dma_q)
1330 {
1331         void *vbuf;
1332         struct cx231xx_buffer *buf;
1333
1334         if (list_empty(&dma_q->active))
1335                 return;
1336
1337         buf = list_entry(dma_q->active.next,
1338                         struct cx231xx_buffer, vb.queue);
1339
1340         /* Fill buffer */
1341         vbuf = videobuf_to_vmalloc(&buf->vb);
1342         memcpy(vbuf, data, len);
1343         buf->vb.state = VIDEOBUF_DONE;
1344         buf->vb.field_count++;
1345         v4l2_get_timestamp(&buf->vb.ts);
1346         list_del(&buf->vb.queue);
1347         wake_up(&buf->vb.done);
1348 }
1349
1350 static int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
1351 {
1352         struct cx231xx_dmaqueue *dma_q = urb->context;
1353         unsigned char *p_buffer;
1354         u32 buffer_size = 0;
1355         u32 i = 0;
1356
1357         for (i = 0; i < urb->number_of_packets; i++) {
1358                 if (dma_q->left_data_count > 0) {
1359                         buffer_copy(dev, dma_q->p_left_data,
1360                                     dma_q->left_data_count, urb, dma_q);
1361                         dma_q->mpeg_buffer_completed = dma_q->left_data_count;
1362                         dma_q->left_data_count = 0;
1363                 }
1364
1365                 p_buffer = urb->transfer_buffer +
1366                                 urb->iso_frame_desc[i].offset;
1367                 buffer_size = urb->iso_frame_desc[i].actual_length;
1368
1369                 if (buffer_size > 0)
1370                         buffer_copy(dev, p_buffer, buffer_size, urb, dma_q);
1371         }
1372
1373         return 0;
1374 }
1375
1376 static int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
1377 {
1378         struct cx231xx_dmaqueue *dma_q = urb->context;
1379         unsigned char *p_buffer, *buffer;
1380         u32 buffer_size = 0;
1381
1382         p_buffer = urb->transfer_buffer;
1383         buffer_size = urb->actual_length;
1384
1385         buffer = kmalloc(buffer_size, GFP_ATOMIC);
1386
1387         memcpy(buffer, dma_q->ps_head, 3);
1388         memcpy(buffer+3, p_buffer, buffer_size-3);
1389         memcpy(dma_q->ps_head, p_buffer+buffer_size-3, 3);
1390
1391         p_buffer = buffer;
1392         buffer_filled(p_buffer, buffer_size, urb, dma_q);
1393
1394         kfree(buffer);
1395         return 0;
1396 }
1397
1398 static int bb_buf_prepare(struct videobuf_queue *q,
1399         struct videobuf_buffer *vb, enum v4l2_field field)
1400 {
1401         struct cx231xx_fh *fh = q->priv_data;
1402         struct cx231xx_buffer *buf =
1403             container_of(vb, struct cx231xx_buffer, vb);
1404         struct cx231xx *dev = fh->dev;
1405         int rc = 0, urb_init = 0;
1406         int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1407
1408         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1409                 return -EINVAL;
1410         buf->vb.width = fh->dev->ts1.ts_packet_size;
1411         buf->vb.height = fh->dev->ts1.ts_packet_count;
1412         buf->vb.size = size;
1413         buf->vb.field = field;
1414
1415         if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1416                 rc = videobuf_iolock(q, &buf->vb, NULL);
1417                 if (rc < 0)
1418                         goto fail;
1419         }
1420
1421         if (dev->USE_ISO) {
1422                 if (!dev->video_mode.isoc_ctl.num_bufs)
1423                         urb_init = 1;
1424         } else {
1425                 if (!dev->video_mode.bulk_ctl.num_bufs)
1426                         urb_init = 1;
1427         }
1428         dev_dbg(dev->dev,
1429                 "urb_init=%d dev->video_mode.max_pkt_size=%d\n",
1430                 urb_init, dev->video_mode.max_pkt_size);
1431         dev->mode_tv = 1;
1432
1433         if (urb_init) {
1434                 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1435                 rc = cx231xx_unmute_audio(dev);
1436                 if (dev->USE_ISO) {
1437                         cx231xx_set_alt_setting(dev, INDEX_TS1, 4);
1438                         rc = cx231xx_init_isoc(dev, mpeglines,
1439                                        mpegbufs,
1440                                        dev->ts1_mode.max_pkt_size,
1441                                        cx231xx_isoc_copy);
1442                 } else {
1443                         cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1444                         rc = cx231xx_init_bulk(dev, mpeglines,
1445                                        mpegbufs,
1446                                        dev->ts1_mode.max_pkt_size,
1447                                        cx231xx_bulk_copy);
1448                 }
1449                 if (rc < 0)
1450                         goto fail;
1451         }
1452
1453         buf->vb.state = VIDEOBUF_PREPARED;
1454         return 0;
1455
1456 fail:
1457         free_buffer(q, buf);
1458         return rc;
1459 }
1460
1461 static void bb_buf_queue(struct videobuf_queue *q,
1462         struct videobuf_buffer *vb)
1463 {
1464         struct cx231xx_fh *fh = q->priv_data;
1465
1466         struct cx231xx_buffer *buf =
1467             container_of(vb, struct cx231xx_buffer, vb);
1468         struct cx231xx *dev = fh->dev;
1469         struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq;
1470
1471         buf->vb.state = VIDEOBUF_QUEUED;
1472         list_add_tail(&buf->vb.queue, &vidq->active);
1473
1474 }
1475
1476 static void bb_buf_release(struct videobuf_queue *q,
1477         struct videobuf_buffer *vb)
1478 {
1479         struct cx231xx_buffer *buf =
1480             container_of(vb, struct cx231xx_buffer, vb);
1481         /*struct cx231xx_fh *fh = q->priv_data;*/
1482         /*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/
1483
1484         free_buffer(q, buf);
1485 }
1486
1487 static struct videobuf_queue_ops cx231xx_qops = {
1488         .buf_setup    = bb_buf_setup,
1489         .buf_prepare  = bb_buf_prepare,
1490         .buf_queue    = bb_buf_queue,
1491         .buf_release  = bb_buf_release,
1492 };
1493
1494 /* ------------------------------------------------------------------ */
1495
1496 static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm)
1497 {
1498         struct cx231xx_fh  *fh  = file->private_data;
1499         struct cx231xx *dev = fh->dev;
1500
1501         *norm = dev->encodernorm.id;
1502         return 0;
1503 }
1504
1505 static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id id)
1506 {
1507         struct cx231xx_fh  *fh  = file->private_data;
1508         struct cx231xx *dev = fh->dev;
1509         unsigned int i;
1510
1511         for (i = 0; i < ARRAY_SIZE(cx231xx_tvnorms); i++)
1512                 if (id & cx231xx_tvnorms[i].id)
1513                         break;
1514         if (i == ARRAY_SIZE(cx231xx_tvnorms))
1515                 return -EINVAL;
1516         dev->encodernorm = cx231xx_tvnorms[i];
1517
1518         if (dev->encodernorm.id & 0xb000) {
1519                 dprintk(3, "encodernorm set to NTSC\n");
1520                 dev->norm = V4L2_STD_NTSC;
1521                 dev->ts1.height = 480;
1522                 cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, false);
1523         } else {
1524                 dprintk(3, "encodernorm set to PAL\n");
1525                 dev->norm = V4L2_STD_PAL_B;
1526                 dev->ts1.height = 576;
1527                 cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, true);
1528         }
1529         call_all(dev, video, s_std, dev->norm);
1530         /* do mode control overrides */
1531         cx231xx_do_mode_ctrl_overrides(dev);
1532
1533         dprintk(3, "exit vidioc_s_std() i=0x%x\n", i);
1534         return 0;
1535 }
1536
1537 static int vidioc_s_ctrl(struct file *file, void *priv,
1538                                 struct v4l2_control *ctl)
1539 {
1540         struct cx231xx_fh  *fh  = file->private_data;
1541         struct cx231xx *dev = fh->dev;
1542
1543         dprintk(3, "enter vidioc_s_ctrl()\n");
1544         /* Update the A/V core */
1545         call_all(dev, core, s_ctrl, ctl);
1546         dprintk(3, "exit vidioc_s_ctrl()\n");
1547         return 0;
1548 }
1549
1550 static int vidioc_enum_fmt_vid_cap(struct file *file, void  *priv,
1551                                         struct v4l2_fmtdesc *f)
1552 {
1553         if (f->index != 0)
1554                 return -EINVAL;
1555
1556         strlcpy(f->description, "MPEG", sizeof(f->description));
1557         f->pixelformat = V4L2_PIX_FMT_MPEG;
1558
1559         return 0;
1560 }
1561
1562 static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1563                                 struct v4l2_format *f)
1564 {
1565         struct cx231xx_fh  *fh  = file->private_data;
1566         struct cx231xx *dev = fh->dev;
1567
1568         dprintk(3, "enter vidioc_g_fmt_vid_cap()\n");
1569         f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1570         f->fmt.pix.bytesperline = 0;
1571         f->fmt.pix.sizeimage = mpeglines * mpeglinesize;
1572         f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
1573         f->fmt.pix.width = dev->ts1.width;
1574         f->fmt.pix.height = dev->ts1.height;
1575         f->fmt.pix.field = V4L2_FIELD_INTERLACED;
1576         dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d\n",
1577                 dev->ts1.width, dev->ts1.height);
1578         dprintk(3, "exit vidioc_g_fmt_vid_cap()\n");
1579         return 0;
1580 }
1581
1582 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1583                                 struct v4l2_format *f)
1584 {
1585         struct cx231xx_fh  *fh  = file->private_data;
1586         struct cx231xx *dev = fh->dev;
1587
1588         dprintk(3, "enter vidioc_try_fmt_vid_cap()\n");
1589         f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1590         f->fmt.pix.bytesperline = 0;
1591         f->fmt.pix.sizeimage = mpeglines * mpeglinesize;
1592         f->fmt.pix.field = V4L2_FIELD_INTERLACED;
1593         f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
1594         dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d\n",
1595                 dev->ts1.width, dev->ts1.height);
1596         dprintk(3, "exit vidioc_try_fmt_vid_cap()\n");
1597         return 0;
1598 }
1599
1600 static int vidioc_reqbufs(struct file *file, void *priv,
1601                                 struct v4l2_requestbuffers *p)
1602 {
1603         struct cx231xx_fh  *fh  = file->private_data;
1604
1605         return videobuf_reqbufs(&fh->vidq, p);
1606 }
1607
1608 static int vidioc_querybuf(struct file *file, void *priv,
1609                                 struct v4l2_buffer *p)
1610 {
1611         struct cx231xx_fh  *fh  = file->private_data;
1612
1613         return videobuf_querybuf(&fh->vidq, p);
1614 }
1615
1616 static int vidioc_qbuf(struct file *file, void *priv,
1617                                 struct v4l2_buffer *p)
1618 {
1619         struct cx231xx_fh  *fh  = file->private_data;
1620
1621         return videobuf_qbuf(&fh->vidq, p);
1622 }
1623
1624 static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1625 {
1626         struct cx231xx_fh  *fh  = priv;
1627
1628         return videobuf_dqbuf(&fh->vidq, b, file->f_flags & O_NONBLOCK);
1629 }
1630
1631
1632 static int vidioc_streamon(struct file *file, void *priv,
1633                                 enum v4l2_buf_type i)
1634 {
1635         struct cx231xx_fh  *fh  = file->private_data;
1636         struct cx231xx *dev = fh->dev;
1637
1638         dprintk(3, "enter vidioc_streamon()\n");
1639         cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1640         cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1641         if (dev->USE_ISO)
1642                 cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS,
1643                                 CX231XX_NUM_BUFS,
1644                                 dev->video_mode.max_pkt_size,
1645                                 cx231xx_isoc_copy);
1646         else {
1647                 cx231xx_init_bulk(dev, 320,
1648                                 5,
1649                                 dev->ts1_mode.max_pkt_size,
1650                                 cx231xx_bulk_copy);
1651         }
1652         dprintk(3, "exit vidioc_streamon()\n");
1653         return videobuf_streamon(&fh->vidq);
1654 }
1655
1656 static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1657 {
1658         struct cx231xx_fh  *fh  = file->private_data;
1659
1660         return videobuf_streamoff(&fh->vidq);
1661 }
1662
1663 static int vidioc_log_status(struct file *file, void *priv)
1664 {
1665         struct cx231xx_fh  *fh  = priv;
1666         struct cx231xx *dev = fh->dev;
1667
1668         call_all(dev, core, log_status);
1669         return v4l2_ctrl_log_status(file, priv);
1670 }
1671
1672 static int mpeg_open(struct file *file)
1673 {
1674         struct video_device *vdev = video_devdata(file);
1675         struct cx231xx *dev = video_drvdata(file);
1676         struct cx231xx_fh *fh;
1677
1678         dprintk(2, "%s()\n", __func__);
1679
1680         if (mutex_lock_interruptible(&dev->lock))
1681                 return -ERESTARTSYS;
1682
1683         /* allocate + initialize per filehandle data */
1684         fh = kzalloc(sizeof(*fh), GFP_KERNEL);
1685         if (NULL == fh) {
1686                 mutex_unlock(&dev->lock);
1687                 return -ENOMEM;
1688         }
1689
1690         file->private_data = fh;
1691         v4l2_fh_init(&fh->fh, vdev);
1692         fh->dev = dev;
1693
1694
1695         videobuf_queue_vmalloc_init(&fh->vidq, &cx231xx_qops,
1696                             NULL, &dev->video_mode.slock,
1697                             V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_INTERLACED,
1698                             sizeof(struct cx231xx_buffer), fh, &dev->lock);
1699 /*
1700         videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops,
1701                             dev->dev, &dev->ts1.slock,
1702                             V4L2_BUF_TYPE_VIDEO_CAPTURE,
1703                             V4L2_FIELD_INTERLACED,
1704                             sizeof(struct cx231xx_buffer),
1705                             fh, &dev->lock);
1706 */
1707
1708         cx231xx_set_alt_setting(dev, INDEX_VANC, 1);
1709         cx231xx_set_gpio_value(dev, 2, 0);
1710
1711         cx231xx_initialize_codec(dev);
1712
1713         mutex_unlock(&dev->lock);
1714         v4l2_fh_add(&fh->fh);
1715         cx231xx_start_TS1(dev);
1716
1717         return 0;
1718 }
1719
1720 static int mpeg_release(struct file *file)
1721 {
1722         struct cx231xx_fh  *fh  = file->private_data;
1723         struct cx231xx *dev = fh->dev;
1724
1725         dprintk(3, "mpeg_release()! dev=0x%p\n", dev);
1726
1727         mutex_lock(&dev->lock);
1728
1729         cx231xx_stop_TS1(dev);
1730
1731         /* do this before setting alternate! */
1732         if (dev->USE_ISO)
1733                 cx231xx_uninit_isoc(dev);
1734         else
1735                 cx231xx_uninit_bulk(dev);
1736         cx231xx_set_mode(dev, CX231XX_SUSPEND);
1737
1738         cx231xx_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1739                         CX231xx_END_NOW, CX231xx_MPEG_CAPTURE,
1740                         CX231xx_RAW_BITS_NONE);
1741
1742         /* FIXME: Review this crap */
1743         /* Shut device down on last close */
1744         if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
1745                 if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
1746                         /* stop mpeg capture */
1747
1748                         msleep(500);
1749                         cx231xx_417_check_encoder(dev);
1750
1751                 }
1752         }
1753
1754         if (fh->vidq.streaming)
1755                 videobuf_streamoff(&fh->vidq);
1756         if (fh->vidq.reading)
1757                 videobuf_read_stop(&fh->vidq);
1758
1759         videobuf_mmap_free(&fh->vidq);
1760         v4l2_fh_del(&fh->fh);
1761         v4l2_fh_exit(&fh->fh);
1762         kfree(fh);
1763         mutex_unlock(&dev->lock);
1764         return 0;
1765 }
1766
1767 static ssize_t mpeg_read(struct file *file, char __user *data,
1768         size_t count, loff_t *ppos)
1769 {
1770         struct cx231xx_fh *fh = file->private_data;
1771         struct cx231xx *dev = fh->dev;
1772
1773         /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
1774         /* Start mpeg encoder on first read. */
1775         if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
1776                 if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
1777                         if (cx231xx_initialize_codec(dev) < 0)
1778                                 return -EINVAL;
1779                 }
1780         }
1781
1782         return videobuf_read_stream(&fh->vidq, data, count, ppos, 0,
1783                                     file->f_flags & O_NONBLOCK);
1784 }
1785
1786 static unsigned int mpeg_poll(struct file *file,
1787         struct poll_table_struct *wait)
1788 {
1789         unsigned long req_events = poll_requested_events(wait);
1790         struct cx231xx_fh *fh = file->private_data;
1791         struct cx231xx *dev = fh->dev;
1792         unsigned int res = 0;
1793
1794         if (v4l2_event_pending(&fh->fh))
1795                 res |= POLLPRI;
1796         else
1797                 poll_wait(file, &fh->fh.wait, wait);
1798
1799         if (!(req_events & (POLLIN | POLLRDNORM)))
1800                 return res;
1801
1802         mutex_lock(&dev->lock);
1803         res |= videobuf_poll_stream(file, &fh->vidq, wait);
1804         mutex_unlock(&dev->lock);
1805         return res;
1806 }
1807
1808 static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
1809 {
1810         struct cx231xx_fh *fh = file->private_data;
1811
1812         dprintk(2, "%s()\n", __func__);
1813
1814         return videobuf_mmap_mapper(&fh->vidq, vma);
1815 }
1816
1817 static struct v4l2_file_operations mpeg_fops = {
1818         .owner         = THIS_MODULE,
1819         .open          = mpeg_open,
1820         .release       = mpeg_release,
1821         .read          = mpeg_read,
1822         .poll          = mpeg_poll,
1823         .mmap          = mpeg_mmap,
1824         .unlocked_ioctl = video_ioctl2,
1825 };
1826
1827 static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
1828         .vidioc_s_std            = vidioc_s_std,
1829         .vidioc_g_std            = vidioc_g_std,
1830         .vidioc_g_tuner          = cx231xx_g_tuner,
1831         .vidioc_s_tuner          = cx231xx_s_tuner,
1832         .vidioc_g_frequency      = cx231xx_g_frequency,
1833         .vidioc_s_frequency      = cx231xx_s_frequency,
1834         .vidioc_enum_input       = cx231xx_enum_input,
1835         .vidioc_g_input          = cx231xx_g_input,
1836         .vidioc_s_input          = cx231xx_s_input,
1837         .vidioc_s_ctrl           = vidioc_s_ctrl,
1838         .vidioc_querycap         = cx231xx_querycap,
1839         .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1840         .vidioc_g_fmt_vid_cap    = vidioc_g_fmt_vid_cap,
1841         .vidioc_try_fmt_vid_cap  = vidioc_try_fmt_vid_cap,
1842         .vidioc_s_fmt_vid_cap    = vidioc_try_fmt_vid_cap,
1843         .vidioc_reqbufs          = vidioc_reqbufs,
1844         .vidioc_querybuf         = vidioc_querybuf,
1845         .vidioc_qbuf             = vidioc_qbuf,
1846         .vidioc_dqbuf            = vidioc_dqbuf,
1847         .vidioc_streamon         = vidioc_streamon,
1848         .vidioc_streamoff        = vidioc_streamoff,
1849         .vidioc_log_status       = vidioc_log_status,
1850 #ifdef CONFIG_VIDEO_ADV_DEBUG
1851         .vidioc_g_register       = cx231xx_g_register,
1852         .vidioc_s_register       = cx231xx_s_register,
1853 #endif
1854         .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1855         .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1856 };
1857
1858 static struct video_device cx231xx_mpeg_template = {
1859         .name          = "cx231xx",
1860         .fops          = &mpeg_fops,
1861         .ioctl_ops     = &mpeg_ioctl_ops,
1862         .minor         = -1,
1863         .tvnorms       = V4L2_STD_ALL,
1864 };
1865
1866 void cx231xx_417_unregister(struct cx231xx *dev)
1867 {
1868         dprintk(1, "%s()\n", __func__);
1869         dprintk(3, "%s()\n", __func__);
1870
1871         if (video_is_registered(&dev->v4l_device)) {
1872                 video_unregister_device(&dev->v4l_device);
1873                 v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl);
1874         }
1875 }
1876
1877 static int cx231xx_s_video_encoding(struct cx2341x_handler *cxhdl, u32 val)
1878 {
1879         struct cx231xx *dev = container_of(cxhdl, struct cx231xx, mpeg_ctrl_handler);
1880         int is_mpeg1 = val == V4L2_MPEG_VIDEO_ENCODING_MPEG_1;
1881         struct v4l2_mbus_framefmt fmt;
1882
1883         /* fix videodecoder resolution */
1884         fmt.width = cxhdl->width / (is_mpeg1 ? 2 : 1);
1885         fmt.height = cxhdl->height;
1886         fmt.code = MEDIA_BUS_FMT_FIXED;
1887         v4l2_subdev_call(dev->sd_cx25840, video, s_mbus_fmt, &fmt);
1888         return 0;
1889 }
1890
1891 static int cx231xx_s_audio_sampling_freq(struct cx2341x_handler *cxhdl, u32 idx)
1892 {
1893         static const u32 freqs[3] = { 44100, 48000, 32000 };
1894         struct cx231xx *dev = container_of(cxhdl, struct cx231xx, mpeg_ctrl_handler);
1895
1896         /* The audio clock of the digitizer must match the codec sample
1897            rate otherwise you get some very strange effects. */
1898         if (idx < ARRAY_SIZE(freqs))
1899                 call_all(dev, audio, s_clock_freq, freqs[idx]);
1900         return 0;
1901 }
1902
1903 static struct cx2341x_handler_ops cx231xx_ops = {
1904         /* needed for the video clock freq */
1905         .s_audio_sampling_freq = cx231xx_s_audio_sampling_freq,
1906         /* needed for setting up the video resolution */
1907         .s_video_encoding = cx231xx_s_video_encoding,
1908 };
1909
1910 static void cx231xx_video_dev_init(
1911         struct cx231xx *dev,
1912         struct usb_device *usbdev,
1913         struct video_device *vfd,
1914         const struct video_device *template,
1915         const char *type)
1916 {
1917         dprintk(1, "%s()\n", __func__);
1918         *vfd = *template;
1919         snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
1920                 type, cx231xx_boards[dev->model].name);
1921
1922         vfd->v4l2_dev = &dev->v4l2_dev;
1923         vfd->lock = &dev->lock;
1924         vfd->release = video_device_release_empty;
1925         vfd->ctrl_handler = &dev->mpeg_ctrl_handler.hdl;
1926         video_set_drvdata(vfd, dev);
1927         if (dev->tuner_type == TUNER_ABSENT) {
1928                 v4l2_disable_ioctl(vfd, VIDIOC_G_FREQUENCY);
1929                 v4l2_disable_ioctl(vfd, VIDIOC_S_FREQUENCY);
1930                 v4l2_disable_ioctl(vfd, VIDIOC_G_TUNER);
1931                 v4l2_disable_ioctl(vfd, VIDIOC_S_TUNER);
1932         }
1933 }
1934
1935 int cx231xx_417_register(struct cx231xx *dev)
1936 {
1937         /* FIXME: Port1 hardcoded here */
1938         int err = -ENODEV;
1939         struct cx231xx_tsport *tsport = &dev->ts1;
1940
1941         dprintk(1, "%s()\n", __func__);
1942
1943         /* Set default TV standard */
1944         dev->encodernorm = cx231xx_tvnorms[0];
1945
1946         if (dev->encodernorm.id & V4L2_STD_525_60)
1947                 tsport->height = 480;
1948         else
1949                 tsport->height = 576;
1950
1951         tsport->width = 720;
1952         err = cx2341x_handler_init(&dev->mpeg_ctrl_handler, 50);
1953         if (err) {
1954                 dprintk(3, "%s: can't init cx2341x controls\n", dev->name);
1955                 return err;
1956         }
1957         dev->mpeg_ctrl_handler.func = cx231xx_mbox_func;
1958         dev->mpeg_ctrl_handler.priv = dev;
1959         dev->mpeg_ctrl_handler.ops = &cx231xx_ops;
1960         if (dev->sd_cx25840)
1961                 v4l2_ctrl_add_handler(&dev->mpeg_ctrl_handler.hdl,
1962                                 dev->sd_cx25840->ctrl_handler, NULL);
1963         if (dev->mpeg_ctrl_handler.hdl.error) {
1964                 err = dev->mpeg_ctrl_handler.hdl.error;
1965                 dprintk(3, "%s: can't add cx25840 controls\n", dev->name);
1966                 v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl);
1967                 return err;
1968         }
1969         dev->norm = V4L2_STD_NTSC;
1970
1971         dev->mpeg_ctrl_handler.port = CX2341X_PORT_SERIAL;
1972         cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, false);
1973
1974         /* Allocate and initialize V4L video device */
1975         cx231xx_video_dev_init(dev, dev->udev,
1976                         &dev->v4l_device, &cx231xx_mpeg_template, "mpeg");
1977         err = video_register_device(&dev->v4l_device,
1978                 VFL_TYPE_GRABBER, -1);
1979         if (err < 0) {
1980                 dprintk(3, "%s: can't register mpeg device\n", dev->name);
1981                 v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl);
1982                 return err;
1983         }
1984
1985         dprintk(3, "%s: registered device video%d [mpeg]\n",
1986                dev->name, dev->v4l_device.num);
1987
1988         return 0;
1989 }
1990
1991 MODULE_FIRMWARE(CX231xx_FIRM_IMAGE_NAME);