kernel/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c

   1 /*
   2  * drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
   3  *
   4  * Samsung MFC (Multi Function Codec - FIMV) driver
   5  * This file contains hw related functions.
   6  *
   7  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   8  *              http://www.samsung.com/
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #undef DEBUG
  16
  17 #include <linux/delay.h>
  18 #include <linux/mm.h>
  19 #include <linux/io.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/firmware.h>
  22 #include <linux/err.h>
  23 #include <linux/sched.h>
  24 #include <linux/dma-mapping.h>
  25
  26 #include <asm/cacheflush.h>
  27
  28 #include "s5p_mfc_common.h"
  29 #include "s5p_mfc_cmd.h"
  30 #include "s5p_mfc_intr.h"
  31 #include "s5p_mfc_pm.h"
  32 #include "s5p_mfc_debug.h"
  33 #include "s5p_mfc_opr.h"
  34 #include "s5p_mfc_opr_v6.h"
  35
  36 /* #define S5P_MFC_DEBUG_REGWRITE  */
  37 #ifdef S5P_MFC_DEBUG_REGWRITE
  38 #undef writel
  39 #define writel(v, r)                                                    \
  40         do {                                                            \
  41                 pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v);     \
  42         __raw_writel(v, r);                                             \
  43         } while (0)
  44 #endif /* S5P_MFC_DEBUG_REGWRITE */
  45
  46 #define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2)
  47
  48 /* Allocate temporary buffers for decoding */
  49 static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
  50 {
  51         /* NOP */
  52
  53         return 0;
  54 }
  55
  56 /* Release temproary buffers for decoding */
  57 static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)
  58 {
  59         /* NOP */
  60 }
  61
  62 /* Allocate codec buffers */
  63 static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
  64 {
  65         struct s5p_mfc_dev *dev = ctx->dev;
  66         unsigned int mb_width, mb_height;
  67         int ret;
  68
  69         mb_width = MB_WIDTH(ctx->img_width);
  70         mb_height = MB_HEIGHT(ctx->img_height);
  71
  72         if (ctx->type == MFCINST_DECODER) {
  73                 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
  74                           ctx->luma_size, ctx->chroma_size, ctx->mv_size);
  75                 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
  76         } else if (ctx->type == MFCINST_ENCODER) {
  77                 if (IS_MFCV8(dev))
  78                         ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
  79                         ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),
  80                         S5P_FIMV_TMV_BUFFER_ALIGN_V6);
  81                 else
  82                         ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
  83                         ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
  84                         S5P_FIMV_TMV_BUFFER_ALIGN_V6);
  85
  86                 ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
  87                                 S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
  88                                 S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
  89                 ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
  90                                 S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
  91                                 S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
  92                 if (IS_MFCV8(dev))
  93                         ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8(
  94                                                 ctx->img_width, ctx->img_height,
  95                                                 mb_width, mb_height),
  96                                                 S5P_FIMV_ME_BUFFER_ALIGN_V6);
  97                 else
  98                         ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6(
  99                                                 ctx->img_width, ctx->img_height,
 100                                                 mb_width, mb_height),
 101                                                 S5P_FIMV_ME_BUFFER_ALIGN_V6);
 102
 103                 mfc_debug(2, "recon luma size: %zu chroma size: %zu\n",
 104                           ctx->luma_dpb_size, ctx->chroma_dpb_size);
 105         } else {
 106                 return -EINVAL;
 107         }
 108
 109         /* Codecs have different memory requirements */
 110         switch (ctx->codec_mode) {
 111         case S5P_MFC_CODEC_H264_DEC:
 112         case S5P_MFC_CODEC_H264_MVC_DEC:
 113                 if (IS_MFCV8(dev))
 114                         ctx->scratch_buf_size =
 115                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(
 116                                         mb_width,
 117                                         mb_height);
 118                 else
 119                         ctx->scratch_buf_size =
 120                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(
 121                                         mb_width,
 122                                         mb_height);
 123                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 124                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 125                 ctx->bank1.size =
 126                         ctx->scratch_buf_size +
 127                         (ctx->mv_count * ctx->mv_size);
 128                 break;
 129         case S5P_MFC_CODEC_MPEG4_DEC:
 130                 if (IS_MFCV7_PLUS(dev)) {
 131                         ctx->scratch_buf_size =
 132                                 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(
 133                                                 mb_width,
 134                                                 mb_height);
 135                 } else {
 136                         ctx->scratch_buf_size =
 137                                 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(
 138                                                 mb_width,
 139                                                 mb_height);
 140                 }
 141
 142                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 143                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 144                 ctx->bank1.size = ctx->scratch_buf_size;
 145                 break;
 146         case S5P_MFC_CODEC_VC1RCV_DEC:
 147         case S5P_MFC_CODEC_VC1_DEC:
 148                 ctx->scratch_buf_size =
 149                         S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(
 150                                         mb_width,
 151                                         mb_height);
 152                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 153                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 154                 ctx->bank1.size = ctx->scratch_buf_size;
 155                 break;
 156         case S5P_MFC_CODEC_MPEG2_DEC:
 157                 ctx->bank1.size = 0;
 158                 ctx->bank2.size = 0;
 159                 break;
 160         case S5P_MFC_CODEC_H263_DEC:
 161                 ctx->scratch_buf_size =
 162                         S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(
 163                                         mb_width,
 164                                         mb_height);
 165                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 166                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 167                 ctx->bank1.size = ctx->scratch_buf_size;
 168                 break;
 169         case S5P_MFC_CODEC_VP8_DEC:
 170                 if (IS_MFCV8(dev))
 171                         ctx->scratch_buf_size =
 172                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(
 173                                                 mb_width,
 174                                                 mb_height);
 175                 else
 176                         ctx->scratch_buf_size =
 177                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(
 178                                                 mb_width,
 179                                                 mb_height);
 180                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 181                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 182                 ctx->bank1.size = ctx->scratch_buf_size;
 183                 break;
 184         case S5P_MFC_CODEC_H264_ENC:
 185                 if (IS_MFCV8(dev))
 186                         ctx->scratch_buf_size =
 187                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(
 188                                         mb_width,
 189                                         mb_height);
 190                 else
 191                         ctx->scratch_buf_size =
 192                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(
 193                                                 mb_width,
 194                                                 mb_height);
 195                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 196                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 197                 ctx->bank1.size =
 198                         ctx->scratch_buf_size + ctx->tmv_buffer_size +
 199                         (ctx->pb_count * (ctx->luma_dpb_size +
 200                         ctx->chroma_dpb_size + ctx->me_buffer_size));
 201                 ctx->bank2.size = 0;
 202                 break;
 203         case S5P_MFC_CODEC_MPEG4_ENC:
 204         case S5P_MFC_CODEC_H263_ENC:
 205                 ctx->scratch_buf_size =
 206                         S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
 207                                         mb_width,
 208                                         mb_height);
 209                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 210                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 211                 ctx->bank1.size =
 212                         ctx->scratch_buf_size + ctx->tmv_buffer_size +
 213                         (ctx->pb_count * (ctx->luma_dpb_size +
 214                         ctx->chroma_dpb_size + ctx->me_buffer_size));
 215                 ctx->bank2.size = 0;
 216                 break;
 217         case S5P_MFC_CODEC_VP8_ENC:
 218                 if (IS_MFCV8(dev))
 219                         ctx->scratch_buf_size =
 220                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(
 221                                         mb_width,
 222                                         mb_height);
 223                 else
 224                         ctx->scratch_buf_size =
 225                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7(
 226                                                 mb_width,
 227                                                 mb_height);
 228                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 229                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 230                 ctx->bank1.size =
 231                         ctx->scratch_buf_size + ctx->tmv_buffer_size +
 232                         (ctx->pb_count * (ctx->luma_dpb_size +
 233                         ctx->chroma_dpb_size + ctx->me_buffer_size));
 234                 ctx->bank2.size = 0;
 235                 break;
 236         default:
 237                 break;
 238         }
 239
 240         /* Allocate only if memory from bank 1 is necessary */
 241         if (ctx->bank1.size > 0) {
 242                 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, dev->bank1,
 243                                              &ctx->bank1);
 244                 if (ret) {
 245                         mfc_err("Failed to allocate Bank1 memory\n");
 246                         return ret;
 247                 }
 248                 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
 249         }
 250         return 0;
 251 }
 252
 253 /* Release buffers allocated for codec */
 254 static void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 255 {
 256         s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1);
 257 }
 258
 259 /* Allocate memory for instance data buffer */
 260 static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
 261 {
 262         struct s5p_mfc_dev *dev = ctx->dev;
 263         struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
 264         int ret;
 265
 266         mfc_debug_enter();
 267
 268         switch (ctx->codec_mode) {
 269         case S5P_MFC_CODEC_H264_DEC:
 270         case S5P_MFC_CODEC_H264_MVC_DEC:
 271                 ctx->ctx.size = buf_size->h264_dec_ctx;
 272                 break;
 273         case S5P_MFC_CODEC_MPEG4_DEC:
 274         case S5P_MFC_CODEC_H263_DEC:
 275         case S5P_MFC_CODEC_VC1RCV_DEC:
 276         case S5P_MFC_CODEC_VC1_DEC:
 277         case S5P_MFC_CODEC_MPEG2_DEC:
 278         case S5P_MFC_CODEC_VP8_DEC:
 279                 ctx->ctx.size = buf_size->other_dec_ctx;
 280                 break;
 281         case S5P_MFC_CODEC_H264_ENC:
 282                 ctx->ctx.size = buf_size->h264_enc_ctx;
 283                 break;
 284         case S5P_MFC_CODEC_MPEG4_ENC:
 285         case S5P_MFC_CODEC_H263_ENC:
 286         case S5P_MFC_CODEC_VP8_ENC:
 287                 ctx->ctx.size = buf_size->other_enc_ctx;
 288                 break;
 289         default:
 290                 ctx->ctx.size = 0;
 291                 mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode);
 292                 break;
 293         }
 294
 295         ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, dev->bank1, &ctx->ctx);
 296         if (ret) {
 297                 mfc_err("Failed to allocate instance buffer\n");
 298                 return ret;
 299         }
 300
 301         memset(ctx->ctx.virt, 0, ctx->ctx.size);
 302         wmb();
 303
 304         mfc_debug_leave();
 305
 306         return 0;
 307 }
 308
 309 /* Release instance buffer */
 310 static void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
 311 {
 312         s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx);
 313 }
 314
 315 /* Allocate context buffers for SYS_INIT */
 316 static int s5p_mfc_alloc_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
 317 {
 318         struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
 319         int ret;
 320
 321         mfc_debug_enter();
 322
 323         dev->ctx_buf.size = buf_size->dev_ctx;
 324         ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, dev->bank1,
 325                                      &dev->ctx_buf);
 326         if (ret) {
 327                 mfc_err("Failed to allocate device context buffer\n");
 328                 return ret;
 329         }
 330
 331         memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx);
 332         wmb();
 333
 334         mfc_debug_leave();
 335
 336         return 0;
 337 }
 338
 339 /* Release context buffers for SYS_INIT */
 340 static void s5p_mfc_release_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
 341 {
 342         s5p_mfc_release_priv_buf(dev->mem_dev_l, &dev->ctx_buf);
 343 }
 344
 345 static int calc_plane(int width, int height)
 346 {
 347         int mbX, mbY;
 348
 349         mbX = DIV_ROUND_UP(width, S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
 350         mbY = DIV_ROUND_UP(height, S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6);
 351
 352         if (width * height < S5P_FIMV_MAX_FRAME_SIZE_V6)
 353                 mbY = (mbY + 1) / 2 * 2;
 354
 355         return (mbX * S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6) *
 356                 (mbY * S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
 357 }
 358
 359 static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
 360 {
 361         ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
 362         ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
 363         mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
 364                         "buffer dimensions: %dx%d\n", ctx->img_width,
 365                         ctx->img_height, ctx->buf_width, ctx->buf_height);
 366
 367         ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height);
 368         ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1));
 369         if (IS_MFCV8(ctx->dev)) {
 370                 /* MFCv8 needs additional 64 bytes for luma,chroma dpb*/
 371                 ctx->luma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
 372                 ctx->chroma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
 373         }
 374
 375         if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 376                         ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
 377                 ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
 378                                 ctx->img_height);
 379                 ctx->mv_size = ALIGN(ctx->mv_size, 16);
 380         } else {
 381                 ctx->mv_size = 0;
 382         }
 383 }
 384
 385 static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)
 386 {
 387         unsigned int mb_width, mb_height;
 388
 389         mb_width = MB_WIDTH(ctx->img_width);
 390         mb_height = MB_HEIGHT(ctx->img_height);
 391
 392         ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
 393         ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
 394         ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
 395
 396         /* MFCv7 needs pad bytes for Luma and Chroma */
 397         if (IS_MFCV7_PLUS(ctx->dev)) {
 398                 ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
 399                 ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V7;
 400         }
 401 }
 402
 403 /* Set registers for decoding stream buffer */
 404 static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
 405                         int buf_addr, unsigned int start_num_byte,
 406                         unsigned int strm_size)
 407 {
 408         struct s5p_mfc_dev *dev = ctx->dev;
 409         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 410         struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;
 411
 412         mfc_debug_enter();
 413         mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n"
 414                 "buf_size: 0x%08x (%d)\n",
 415                 ctx->inst_no, buf_addr, strm_size, strm_size);
 416         writel(strm_size, mfc_regs->d_stream_data_size);
 417         writel(buf_addr, mfc_regs->d_cpb_buffer_addr);
 418         writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size);
 419         writel(start_num_byte, mfc_regs->d_cpb_buffer_offset);
 420
 421         mfc_debug_leave();
 422         return 0;
 423 }
 424
 425 /* Set decoding frame buffer */
 426 static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
 427 {
 428         unsigned int frame_size, i;
 429         unsigned int frame_size_ch, frame_size_mv;
 430         struct s5p_mfc_dev *dev = ctx->dev;
 431         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 432         size_t buf_addr1;
 433         int buf_size1;
 434         int align_gap;
 435
 436         buf_addr1 = ctx->bank1.dma;
 437         buf_size1 = ctx->bank1.size;
 438
 439         mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
 440         mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);
 441         mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);
 442
 443         writel(ctx->total_dpb_count, mfc_regs->d_num_dpb);
 444         writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size);
 445         writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size);
 446
 447         writel(buf_addr1, mfc_regs->d_scratch_buffer_addr);
 448         writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size);
 449
 450         if (IS_MFCV8(dev)) {
 451                 writel(ctx->img_width,
 452                         mfc_regs->d_first_plane_dpb_stride_size);
 453                 writel(ctx->img_width,
 454                         mfc_regs->d_second_plane_dpb_stride_size);
 455         }
 456
 457         buf_addr1 += ctx->scratch_buf_size;
 458         buf_size1 -= ctx->scratch_buf_size;
 459
 460         if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
 461                         ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){
 462                 writel(ctx->mv_size, mfc_regs->d_mv_buffer_size);
 463                 writel(ctx->mv_count, mfc_regs->d_num_mv);
 464         }
 465
 466         frame_size = ctx->luma_size;
 467         frame_size_ch = ctx->chroma_size;
 468         frame_size_mv = ctx->mv_size;
 469         mfc_debug(2, "Frame size: %d ch: %d mv: %d\n",
 470                         frame_size, frame_size_ch, frame_size_mv);
 471
 472         for (i = 0; i < ctx->total_dpb_count; i++) {
 473                 /* Bank2 */
 474                 mfc_debug(2, "Luma %d: %zx\n", i,
 475                                         ctx->dst_bufs[i].cookie.raw.luma);
 476                 writel(ctx->dst_bufs[i].cookie.raw.luma,
 477                                 mfc_regs->d_first_plane_dpb + i * 4);
 478                 mfc_debug(2, "\tChroma %d: %zx\n", i,
 479                                         ctx->dst_bufs[i].cookie.raw.chroma);
 480                 writel(ctx->dst_bufs[i].cookie.raw.chroma,
 481                                 mfc_regs->d_second_plane_dpb + i * 4);
 482         }
 483         if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 484                         ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
 485                 for (i = 0; i < ctx->mv_count; i++) {
 486                         /* To test alignment */
 487                         align_gap = buf_addr1;
 488                         buf_addr1 = ALIGN(buf_addr1, 16);
 489                         align_gap = buf_addr1 - align_gap;
 490                         buf_size1 -= align_gap;
 491
 492                         mfc_debug(2, "\tBuf1: %zx, size: %d\n",
 493                                         buf_addr1, buf_size1);
 494                         writel(buf_addr1, mfc_regs->d_mv_buffer + i * 4);
 495                         buf_addr1 += frame_size_mv;
 496                         buf_size1 -= frame_size_mv;
 497                 }
 498         }
 499
 500         mfc_debug(2, "Buf1: %zu, buf_size1: %d (frames %d)\n",
 501                         buf_addr1, buf_size1, ctx->total_dpb_count);
 502         if (buf_size1 < 0) {
 503                 mfc_debug(2, "Not enough memory has been allocated.\n");
 504                 return -ENOMEM;
 505         }
 506
 507         writel(ctx->inst_no, mfc_regs->instance_id);
 508         s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
 509                         S5P_FIMV_CH_INIT_BUFS_V6, NULL);
 510
 511         mfc_debug(2, "After setting buffers.\n");
 512         return 0;
 513 }
 514
 515 /* Set registers for encoding stream buffer */
 516 static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
 517                 unsigned long addr, unsigned int size)
 518 {
 519         struct s5p_mfc_dev *dev = ctx->dev;
 520         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 521
 522         writel(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */
 523         writel(size, mfc_regs->e_stream_buffer_size);
 524
 525         mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%x\n",
 526                   addr, size);
 527
 528         return 0;
 529 }
 530
 531 static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
 532                 unsigned long y_addr, unsigned long c_addr)
 533 {
 534         struct s5p_mfc_dev *dev = ctx->dev;
 535         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 536
 537         writel(y_addr, mfc_regs->e_source_first_plane_addr);
 538         writel(c_addr, mfc_regs->e_source_second_plane_addr);
 539
 540         mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);
 541         mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);
 542 }
 543
 544 static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
 545                 unsigned long *y_addr, unsigned long *c_addr)
 546 {
 547         struct s5p_mfc_dev *dev = ctx->dev;
 548         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 549         unsigned long enc_recon_y_addr, enc_recon_c_addr;
 550
 551         *y_addr = readl(mfc_regs->e_encoded_source_first_plane_addr);
 552         *c_addr = readl(mfc_regs->e_encoded_source_second_plane_addr);
 553
 554         enc_recon_y_addr = readl(mfc_regs->e_recon_luma_dpb_addr);
 555         enc_recon_c_addr = readl(mfc_regs->e_recon_chroma_dpb_addr);
 556
 557         mfc_debug(2, "recon y addr: 0x%08lx y_addr: 0x%08lx\n", enc_recon_y_addr, *y_addr);
 558         mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr);
 559 }
 560
 561 /* Set encoding ref & codec buffer */
 562 static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
 563 {
 564         struct s5p_mfc_dev *dev = ctx->dev;
 565         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 566         size_t buf_addr1;
 567         int i, buf_size1;
 568
 569         mfc_debug_enter();
 570
 571         buf_addr1 = ctx->bank1.dma;
 572         buf_size1 = ctx->bank1.size;
 573
 574         mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
 575
 576         for (i = 0; i < ctx->pb_count; i++) {
 577                 writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
 578                 buf_addr1 += ctx->luma_dpb_size;
 579                 writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
 580                 buf_addr1 += ctx->chroma_dpb_size;
 581                 writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
 582                 buf_addr1 += ctx->me_buffer_size;
 583                 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size +
 584                         ctx->me_buffer_size);
 585         }
 586
 587         writel(buf_addr1, mfc_regs->e_scratch_buffer_addr);
 588         writel(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size);
 589         buf_addr1 += ctx->scratch_buf_size;
 590         buf_size1 -= ctx->scratch_buf_size;
 591
 592         writel(buf_addr1, mfc_regs->e_tmv_buffer0);
 593         buf_addr1 += ctx->tmv_buffer_size >> 1;
 594         writel(buf_addr1, mfc_regs->e_tmv_buffer1);
 595         buf_addr1 += ctx->tmv_buffer_size >> 1;
 596         buf_size1 -= ctx->tmv_buffer_size;
 597
 598         mfc_debug(2, "Buf1: %zu, buf_size1: %d (ref frames %d)\n",
 599                         buf_addr1, buf_size1, ctx->pb_count);
 600         if (buf_size1 < 0) {
 601                 mfc_debug(2, "Not enough memory has been allocated.\n");
 602                 return -ENOMEM;
 603         }
 604
 605         writel(ctx->inst_no, mfc_regs->instance_id);
 606         s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
 607                         S5P_FIMV_CH_INIT_BUFS_V6, NULL);
 608
 609         mfc_debug_leave();
 610
 611         return 0;
 612 }
 613
 614 static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
 615 {
 616         struct s5p_mfc_dev *dev = ctx->dev;
 617         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 618
 619         /* multi-slice control */
 620         /* multi-slice MB number or bit size */
 621         writel(ctx->slice_mode, mfc_regs->e_mslice_mode);
 622         if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
 623                 writel(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb);
 624         } else if (ctx->slice_mode ==
 625                         V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
 626                 writel(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits);
 627         } else {
 628                 writel(0x0, mfc_regs->e_mslice_size_mb);
 629                 writel(0x0, mfc_regs->e_mslice_size_bits);
 630         }
 631
 632         return 0;
 633 }
 634
 635 static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
 636 {
 637         struct s5p_mfc_dev *dev = ctx->dev;
 638         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 639         struct s5p_mfc_enc_params *p = &ctx->enc_params;
 640         unsigned int reg = 0;
 641
 642         mfc_debug_enter();
 643
 644         /* width */
 645         writel(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */
 646         /* height */
 647         writel(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */
 648
 649         /* cropped width */
 650         writel(ctx->img_width, mfc_regs->e_cropped_frame_width);
 651         /* cropped height */
 652         writel(ctx->img_height, mfc_regs->e_cropped_frame_height);
 653         /* cropped offset */
 654         writel(0x0, mfc_regs->e_frame_crop_offset);
 655
 656         /* pictype : IDR period */
 657         reg = 0;
 658         reg |= p->gop_size & 0xFFFF;
 659         writel(reg, mfc_regs->e_gop_config);
 660
 661         /* multi-slice control */
 662         /* multi-slice MB number or bit size */
 663         ctx->slice_mode = p->slice_mode;
 664         reg = 0;
 665         if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
 666                 reg |= (0x1 << 3);
 667                 writel(reg, mfc_regs->e_enc_options);
 668                 ctx->slice_size.mb = p->slice_mb;
 669         } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
 670                 reg |= (0x1 << 3);
 671                 writel(reg, mfc_regs->e_enc_options);
 672                 ctx->slice_size.bits = p->slice_bit;
 673         } else {
 674                 reg &= ~(0x1 << 3);
 675                 writel(reg, mfc_regs->e_enc_options);
 676         }
 677
 678         s5p_mfc_set_slice_mode(ctx);
 679
 680         /* cyclic intra refresh */
 681         writel(p->intra_refresh_mb, mfc_regs->e_ir_size);
 682         reg = readl(mfc_regs->e_enc_options);
 683         if (p->intra_refresh_mb == 0)
 684                 reg &= ~(0x1 << 4);
 685         else
 686                 reg |= (0x1 << 4);
 687         writel(reg, mfc_regs->e_enc_options);
 688
 689         /* 'NON_REFERENCE_STORE_ENABLE' for debugging */
 690         reg = readl(mfc_regs->e_enc_options);
 691         reg &= ~(0x1 << 9);
 692         writel(reg, mfc_regs->e_enc_options);
 693
 694         /* memory structure cur. frame */
 695         if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
 696                 /* 0: Linear, 1: 2D tiled*/
 697                 reg = readl(mfc_regs->e_enc_options);
 698                 reg &= ~(0x1 << 7);
 699                 writel(reg, mfc_regs->e_enc_options);
 700                 /* 0: NV12(CbCr), 1: NV21(CrCb) */
 701                 writel(0x0, mfc_regs->pixel_format);
 702         } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
 703                 /* 0: Linear, 1: 2D tiled*/
 704                 reg = readl(mfc_regs->e_enc_options);
 705                 reg &= ~(0x1 << 7);
 706                 writel(reg, mfc_regs->e_enc_options);
 707                 /* 0: NV12(CbCr), 1: NV21(CrCb) */
 708                 writel(0x1, mfc_regs->pixel_format);
 709         } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
 710                 /* 0: Linear, 1: 2D tiled*/
 711                 reg = readl(mfc_regs->e_enc_options);
 712                 reg |= (0x1 << 7);
 713                 writel(reg, mfc_regs->e_enc_options);
 714                 /* 0: NV12(CbCr), 1: NV21(CrCb) */
 715                 writel(0x0, mfc_regs->pixel_format);
 716         }
 717
 718         /* memory structure recon. frame */
 719         /* 0: Linear, 1: 2D tiled */
 720         reg = readl(mfc_regs->e_enc_options);
 721         reg |= (0x1 << 8);
 722         writel(reg, mfc_regs->e_enc_options);
 723
 724         /* padding control & value */
 725         writel(0x0, mfc_regs->e_padding_ctrl);
 726         if (p->pad) {
 727                 reg = 0;
 728                 /** enable */
 729                 reg |= (1 << 31);
 730                 /** cr value */
 731                 reg |= ((p->pad_cr & 0xFF) << 16);
 732                 /** cb value */
 733                 reg |= ((p->pad_cb & 0xFF) << 8);
 734                 /** y value */
 735                 reg |= p->pad_luma & 0xFF;
 736                 writel(reg, mfc_regs->e_padding_ctrl);
 737         }
 738
 739         /* rate control config. */
 740         reg = 0;
 741         /* frame-level rate control */
 742         reg |= ((p->rc_frame & 0x1) << 9);
 743         writel(reg, mfc_regs->e_rc_config);
 744
 745         /* bit rate */
 746         if (p->rc_frame)
 747                 writel(p->rc_bitrate,
 748                         mfc_regs->e_rc_bit_rate);
 749         else
 750                 writel(1, mfc_regs->e_rc_bit_rate);
 751
 752         /* reaction coefficient */
 753         if (p->rc_frame) {
 754                 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */
 755                         writel(1, mfc_regs->e_rc_mode);
 756                 else                                      /* loose CBR */
 757                         writel(2, mfc_regs->e_rc_mode);
 758         }
 759
 760         /* seq header ctrl */
 761         reg = readl(mfc_regs->e_enc_options);
 762         reg &= ~(0x1 << 2);
 763         reg |= ((p->seq_hdr_mode & 0x1) << 2);
 764
 765         /* frame skip mode */
 766         reg &= ~(0x3);
 767         reg |= (p->frame_skip_mode & 0x3);
 768         writel(reg, mfc_regs->e_enc_options);
 769
 770         /* 'DROP_CONTROL_ENABLE', disable */
 771         reg = readl(mfc_regs->e_rc_config);
 772         reg &= ~(0x1 << 10);
 773         writel(reg, mfc_regs->e_rc_config);
 774
 775         /* setting for MV range [16, 256] */
 776         reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
 777         writel(reg, mfc_regs->e_mv_hor_range);
 778
 779         reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
 780         writel(reg, mfc_regs->e_mv_ver_range);
 781
 782         writel(0x0, mfc_regs->e_frame_insertion);
 783         writel(0x0, mfc_regs->e_roi_buffer_addr);
 784         writel(0x0, mfc_regs->e_param_change);
 785         writel(0x0, mfc_regs->e_rc_roi_ctrl);
 786         writel(0x0, mfc_regs->e_picture_tag);
 787
 788         writel(0x0, mfc_regs->e_bit_count_enable);
 789         writel(0x0, mfc_regs->e_max_bit_count);
 790         writel(0x0, mfc_regs->e_min_bit_count);
 791
 792         writel(0x0, mfc_regs->e_metadata_buffer_addr);
 793         writel(0x0, mfc_regs->e_metadata_buffer_size);
 794
 795         mfc_debug_leave();
 796
 797         return 0;
 798 }
 799
 800 static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
 801 {
 802         struct s5p_mfc_dev *dev = ctx->dev;
 803         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 804         struct s5p_mfc_enc_params *p = &ctx->enc_params;
 805         struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
 806         unsigned int reg = 0;
 807         int i;
 808
 809         mfc_debug_enter();
 810
 811         s5p_mfc_set_enc_params(ctx);
 812
 813         /* pictype : number of B */
 814         reg = readl(mfc_regs->e_gop_config);
 815         reg &= ~(0x3 << 16);
 816         reg |= ((p->num_b_frame & 0x3) << 16);
 817         writel(reg, mfc_regs->e_gop_config);
 818
 819         /* profile & level */
 820         reg = 0;
 821         /** level */
 822         reg |= ((p_h264->level & 0xFF) << 8);
 823         /** profile - 0 ~ 3 */
 824         reg |= p_h264->profile & 0x3F;
 825         writel(reg, mfc_regs->e_picture_profile);
 826
 827         /* rate control config. */
 828         reg = readl(mfc_regs->e_rc_config);
 829         /** macroblock level rate control */
 830         reg &= ~(0x1 << 8);
 831         reg |= ((p->rc_mb & 0x1) << 8);
 832         writel(reg, mfc_regs->e_rc_config);
 833
 834         /** frame QP */
 835         reg &= ~(0x3F);
 836         reg |= p_h264->rc_frame_qp & 0x3F;
 837         writel(reg, mfc_regs->e_rc_config);
 838
 839         /* max & min value of QP */
 840         reg = 0;
 841         /** max QP */
 842         reg |= ((p_h264->rc_max_qp & 0x3F) << 8);
 843         /** min QP */
 844         reg |= p_h264->rc_min_qp & 0x3F;
 845         writel(reg, mfc_regs->e_rc_qp_bound);
 846
 847         /* other QPs */
 848         writel(0x0, mfc_regs->e_fixed_picture_qp);
 849         if (!p->rc_frame && !p->rc_mb) {
 850                 reg = 0;
 851                 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16);
 852                 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8);
 853                 reg |= p_h264->rc_frame_qp & 0x3F;
 854                 writel(reg, mfc_regs->e_fixed_picture_qp);
 855         }
 856
 857         /* frame rate */
 858         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
 859                 reg = 0;
 860                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
 861                 reg |= p->rc_framerate_denom & 0xFFFF;
 862                 writel(reg, mfc_regs->e_rc_frame_rate);
 863         }
 864
 865         /* vbv buffer size */
 866         if (p->frame_skip_mode ==
 867                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
 868                 writel(p_h264->cpb_size & 0xFFFF,
 869                                 mfc_regs->e_vbv_buffer_size);
 870
 871                 if (p->rc_frame)
 872                         writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
 873         }
 874
 875         /* interlace */
 876         reg = 0;
 877         reg |= ((p_h264->interlace & 0x1) << 3);
 878         writel(reg, mfc_regs->e_h264_options);
 879
 880         /* height */
 881         if (p_h264->interlace) {
 882                 writel(ctx->img_height >> 1,
 883                                 mfc_regs->e_frame_height); /* 32 align */
 884                 /* cropped height */
 885                 writel(ctx->img_height >> 1,
 886                                 mfc_regs->e_cropped_frame_height);
 887         }
 888
 889         /* loop filter ctrl */
 890         reg = readl(mfc_regs->e_h264_options);
 891         reg &= ~(0x3 << 1);
 892         reg |= ((p_h264->loop_filter_mode & 0x3) << 1);
 893         writel(reg, mfc_regs->e_h264_options);
 894
 895         /* loopfilter alpha offset */
 896         if (p_h264->loop_filter_alpha < 0) {
 897                 reg = 0x10;
 898                 reg |= (0xFF - p_h264->loop_filter_alpha) + 1;
 899         } else {
 900                 reg = 0x00;
 901                 reg |= (p_h264->loop_filter_alpha & 0xF);
 902         }
 903         writel(reg, mfc_regs->e_h264_lf_alpha_offset);
 904
 905         /* loopfilter beta offset */
 906         if (p_h264->loop_filter_beta < 0) {
 907                 reg = 0x10;
 908                 reg |= (0xFF - p_h264->loop_filter_beta) + 1;
 909         } else {
 910                 reg = 0x00;
 911                 reg |= (p_h264->loop_filter_beta & 0xF);
 912         }
 913         writel(reg, mfc_regs->e_h264_lf_beta_offset);
 914
 915         /* entropy coding mode */
 916         reg = readl(mfc_regs->e_h264_options);
 917         reg &= ~(0x1);
 918         reg |= p_h264->entropy_mode & 0x1;
 919         writel(reg, mfc_regs->e_h264_options);
 920
 921         /* number of ref. picture */
 922         reg = readl(mfc_regs->e_h264_options);
 923         reg &= ~(0x1 << 7);
 924         reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7);
 925         writel(reg, mfc_regs->e_h264_options);
 926
 927         /* 8x8 transform enable */
 928         reg = readl(mfc_regs->e_h264_options);
 929         reg &= ~(0x3 << 12);
 930         reg |= ((p_h264->_8x8_transform & 0x3) << 12);
 931         writel(reg, mfc_regs->e_h264_options);
 932
 933         /* macroblock adaptive scaling features */
 934         writel(0x0, mfc_regs->e_mb_rc_config);
 935         if (p->rc_mb) {
 936                 reg = 0;
 937                 /** dark region */
 938                 reg |= ((p_h264->rc_mb_dark & 0x1) << 3);
 939                 /** smooth region */
 940                 reg |= ((p_h264->rc_mb_smooth & 0x1) << 2);
 941                 /** static region */
 942                 reg |= ((p_h264->rc_mb_static & 0x1) << 1);
 943                 /** high activity region */
 944                 reg |= p_h264->rc_mb_activity & 0x1;
 945                 writel(reg, mfc_regs->e_mb_rc_config);
 946         }
 947
 948         /* aspect ratio VUI */
 949         readl(mfc_regs->e_h264_options);
 950         reg &= ~(0x1 << 5);
 951         reg |= ((p_h264->vui_sar & 0x1) << 5);
 952         writel(reg, mfc_regs->e_h264_options);
 953
 954         writel(0x0, mfc_regs->e_aspect_ratio);
 955         writel(0x0, mfc_regs->e_extended_sar);
 956         if (p_h264->vui_sar) {
 957                 /* aspect ration IDC */
 958                 reg = 0;
 959                 reg |= p_h264->vui_sar_idc & 0xFF;
 960                 writel(reg, mfc_regs->e_aspect_ratio);
 961                 if (p_h264->vui_sar_idc == 0xFF) {
 962                         /* extended SAR */
 963                         reg = 0;
 964                         reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16;
 965                         reg |= p_h264->vui_ext_sar_height & 0xFFFF;
 966                         writel(reg, mfc_regs->e_extended_sar);
 967                 }
 968         }
 969
 970         /* intra picture period for H.264 open GOP */
 971         /* control */
 972         readl(mfc_regs->e_h264_options);
 973         reg &= ~(0x1 << 4);
 974         reg |= ((p_h264->open_gop & 0x1) << 4);
 975         writel(reg, mfc_regs->e_h264_options);
 976
 977         /* value */
 978         writel(0x0, mfc_regs->e_h264_i_period);
 979         if (p_h264->open_gop) {
 980                 reg = 0;
 981                 reg |= p_h264->open_gop_size & 0xFFFF;
 982                 writel(reg, mfc_regs->e_h264_i_period);
 983         }
 984
 985         /* 'WEIGHTED_BI_PREDICTION' for B is disable */
 986         readl(mfc_regs->e_h264_options);
 987         reg &= ~(0x3 << 9);
 988         writel(reg, mfc_regs->e_h264_options);
 989
 990         /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
 991         readl(mfc_regs->e_h264_options);
 992         reg &= ~(0x1 << 14);
 993         writel(reg, mfc_regs->e_h264_options);
 994
 995         /* ASO */
 996         readl(mfc_regs->e_h264_options);
 997         reg &= ~(0x1 << 6);
 998         reg |= ((p_h264->aso & 0x1) << 6);
 999         writel(reg, mfc_regs->e_h264_options);
1000
1001         /* hier qp enable */
1002         readl(mfc_regs->e_h264_options);
1003         reg &= ~(0x1 << 8);
1004         reg |= ((p_h264->open_gop & 0x1) << 8);
1005         writel(reg, mfc_regs->e_h264_options);
1006         reg = 0;
1007         if (p_h264->hier_qp && p_h264->hier_qp_layer) {
1008                 reg |= (p_h264->hier_qp_type & 0x1) << 0x3;
1009                 reg |= p_h264->hier_qp_layer & 0x7;
1010                 writel(reg, mfc_regs->e_h264_num_t_layer);
1011                 /* QP value for each layer */
1012                 for (i = 0; i < p_h264->hier_qp_layer &&
1013                                 i < ARRAY_SIZE(p_h264->hier_qp_layer_qp); i++) {
1014                         writel(p_h264->hier_qp_layer_qp[i],
1015                                 mfc_regs->e_h264_hierarchical_qp_layer0
1016                                 + i * 4);
1017                 }
1018         }
1019         /* number of coding layer should be zero when hierarchical is disable */
1020         writel(reg, mfc_regs->e_h264_num_t_layer);
1021
1022         /* frame packing SEI generation */
1023         readl(mfc_regs->e_h264_options);
1024         reg &= ~(0x1 << 25);
1025         reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
1026         writel(reg, mfc_regs->e_h264_options);
1027         if (p_h264->sei_frame_packing) {
1028                 reg = 0;
1029                 /** current frame0 flag */
1030                 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2);
1031                 /** arrangement type */
1032                 reg |= p_h264->sei_fp_arrangement_type & 0x3;
1033                 writel(reg, mfc_regs->e_h264_frame_packing_sei_info);
1034         }
1035
1036         if (p_h264->fmo) {
1037                 switch (p_h264->fmo_map_type) {
1038                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES:
1039                         if (p_h264->fmo_slice_grp > 4)
1040                                 p_h264->fmo_slice_grp = 4;
1041                         for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++)
1042                                 writel(p_h264->fmo_run_len[i] - 1,
1043                                         mfc_regs->e_h264_fmo_run_length_minus1_0
1044                                         + i * 4);
1045                         break;
1046                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:
1047                         if (p_h264->fmo_slice_grp > 4)
1048                                 p_h264->fmo_slice_grp = 4;
1049                         break;
1050                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN:
1051                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:
1052                         if (p_h264->fmo_slice_grp > 2)
1053                                 p_h264->fmo_slice_grp = 2;
1054                         writel(p_h264->fmo_chg_dir & 0x1,
1055                                 mfc_regs->e_h264_fmo_slice_grp_change_dir);
1056                         /* the valid range is 0 ~ number of macroblocks -1 */
1057                         writel(p_h264->fmo_chg_rate,
1058                         mfc_regs->e_h264_fmo_slice_grp_change_rate_minus1);
1059                         break;
1060                 default:
1061                         mfc_err("Unsupported map type for FMO: %d\n",
1062                                         p_h264->fmo_map_type);
1063                         p_h264->fmo_map_type = 0;
1064                         p_h264->fmo_slice_grp = 1;
1065                         break;
1066                 }
1067
1068                 writel(p_h264->fmo_map_type,
1069                                 mfc_regs->e_h264_fmo_slice_grp_map_type);
1070                 writel(p_h264->fmo_slice_grp - 1,
1071                                 mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1072         } else {
1073                 writel(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1074         }
1075
1076         mfc_debug_leave();
1077
1078         return 0;
1079 }
1080
1081 static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1082 {
1083         struct s5p_mfc_dev *dev = ctx->dev;
1084         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1085         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1086         struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
1087         unsigned int reg = 0;
1088
1089         mfc_debug_enter();
1090
1091         s5p_mfc_set_enc_params(ctx);
1092
1093         /* pictype : number of B */
1094         reg = readl(mfc_regs->e_gop_config);
1095         reg &= ~(0x3 << 16);
1096         reg |= ((p->num_b_frame & 0x3) << 16);
1097         writel(reg, mfc_regs->e_gop_config);
1098
1099         /* profile & level */
1100         reg = 0;
1101         /** level */
1102         reg |= ((p_mpeg4->level & 0xFF) << 8);
1103         /** profile - 0 ~ 1 */
1104         reg |= p_mpeg4->profile & 0x3F;
1105         writel(reg, mfc_regs->e_picture_profile);
1106
1107         /* rate control config. */
1108         reg = readl(mfc_regs->e_rc_config);
1109         /** macroblock level rate control */
1110         reg &= ~(0x1 << 8);
1111         reg |= ((p->rc_mb & 0x1) << 8);
1112         writel(reg, mfc_regs->e_rc_config);
1113
1114         /** frame QP */
1115         reg &= ~(0x3F);
1116         reg |= p_mpeg4->rc_frame_qp & 0x3F;
1117         writel(reg, mfc_regs->e_rc_config);
1118
1119         /* max & min value of QP */
1120         reg = 0;
1121         /** max QP */
1122         reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8);
1123         /** min QP */
1124         reg |= p_mpeg4->rc_min_qp & 0x3F;
1125         writel(reg, mfc_regs->e_rc_qp_bound);
1126
1127         /* other QPs */
1128         writel(0x0, mfc_regs->e_fixed_picture_qp);
1129         if (!p->rc_frame && !p->rc_mb) {
1130                 reg = 0;
1131                 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16);
1132                 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8);
1133                 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1134                 writel(reg, mfc_regs->e_fixed_picture_qp);
1135         }
1136
1137         /* frame rate */
1138         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1139                 reg = 0;
1140                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1141                 reg |= p->rc_framerate_denom & 0xFFFF;
1142                 writel(reg, mfc_regs->e_rc_frame_rate);
1143         }
1144
1145         /* vbv buffer size */
1146         if (p->frame_skip_mode ==
1147                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1148                 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1149
1150                 if (p->rc_frame)
1151                         writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1152         }
1153
1154         /* Disable HEC */
1155         writel(0x0, mfc_regs->e_mpeg4_options);
1156         writel(0x0, mfc_regs->e_mpeg4_hec_period);
1157
1158         mfc_debug_leave();
1159
1160         return 0;
1161 }
1162
1163 static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1164 {
1165         struct s5p_mfc_dev *dev = ctx->dev;
1166         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1167         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1168         struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;
1169         unsigned int reg = 0;
1170
1171         mfc_debug_enter();
1172
1173         s5p_mfc_set_enc_params(ctx);
1174
1175         /* profile & level */
1176         reg = 0;
1177         /** profile */
1178         reg |= (0x1 << 4);
1179         writel(reg, mfc_regs->e_picture_profile);
1180
1181         /* rate control config. */
1182         reg = readl(mfc_regs->e_rc_config);
1183         /** macroblock level rate control */
1184         reg &= ~(0x1 << 8);
1185         reg |= ((p->rc_mb & 0x1) << 8);
1186         writel(reg, mfc_regs->e_rc_config);
1187
1188         /** frame QP */
1189         reg &= ~(0x3F);
1190         reg |= p_h263->rc_frame_qp & 0x3F;
1191         writel(reg, mfc_regs->e_rc_config);
1192
1193         /* max & min value of QP */
1194         reg = 0;
1195         /** max QP */
1196         reg |= ((p_h263->rc_max_qp & 0x3F) << 8);
1197         /** min QP */
1198         reg |= p_h263->rc_min_qp & 0x3F;
1199         writel(reg, mfc_regs->e_rc_qp_bound);
1200
1201         /* other QPs */
1202         writel(0x0, mfc_regs->e_fixed_picture_qp);
1203         if (!p->rc_frame && !p->rc_mb) {
1204                 reg = 0;
1205                 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16);
1206                 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8);
1207                 reg |= p_h263->rc_frame_qp & 0x3F;
1208                 writel(reg, mfc_regs->e_fixed_picture_qp);
1209         }
1210
1211         /* frame rate */
1212         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1213                 reg = 0;
1214                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1215                 reg |= p->rc_framerate_denom & 0xFFFF;
1216                 writel(reg, mfc_regs->e_rc_frame_rate);
1217         }
1218
1219         /* vbv buffer size */
1220         if (p->frame_skip_mode ==
1221                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1222                 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1223
1224                 if (p->rc_frame)
1225                         writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1226         }
1227
1228         mfc_debug_leave();
1229
1230         return 0;
1231 }
1232
1233 static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1234 {
1235         struct s5p_mfc_dev *dev = ctx->dev;
1236         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1237         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1238         struct s5p_mfc_vp8_enc_params *p_vp8 = &p->codec.vp8;
1239         unsigned int reg = 0;
1240         unsigned int val = 0;
1241
1242         mfc_debug_enter();
1243
1244         s5p_mfc_set_enc_params(ctx);
1245
1246         /* pictype : number of B */
1247         reg = readl(mfc_regs->e_gop_config);
1248         reg &= ~(0x3 << 16);
1249         reg |= ((p->num_b_frame & 0x3) << 16);
1250         writel(reg, mfc_regs->e_gop_config);
1251
1252         /* profile - 0 ~ 3 */
1253         reg = p_vp8->profile & 0x3;
1254         writel(reg, mfc_regs->e_picture_profile);
1255
1256         /* rate control config. */
1257         reg = readl(mfc_regs->e_rc_config);
1258         /** macroblock level rate control */
1259         reg &= ~(0x1 << 8);
1260         reg |= ((p->rc_mb & 0x1) << 8);
1261         writel(reg, mfc_regs->e_rc_config);
1262
1263         /* frame rate */
1264         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1265                 reg = 0;
1266                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1267                 reg |= p->rc_framerate_denom & 0xFFFF;
1268                 writel(reg, mfc_regs->e_rc_frame_rate);
1269         }
1270
1271         /* frame QP */
1272         reg &= ~(0x7F);
1273         reg |= p_vp8->rc_frame_qp & 0x7F;
1274         writel(reg, mfc_regs->e_rc_config);
1275
1276         /* other QPs */
1277         writel(0x0, mfc_regs->e_fixed_picture_qp);
1278         if (!p->rc_frame && !p->rc_mb) {
1279                 reg = 0;
1280                 reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8);
1281                 reg |= p_vp8->rc_frame_qp & 0x7F;
1282                 writel(reg, mfc_regs->e_fixed_picture_qp);
1283         }
1284
1285         /* max QP */
1286         reg = ((p_vp8->rc_max_qp & 0x7F) << 8);
1287         /* min QP */
1288         reg |= p_vp8->rc_min_qp & 0x7F;
1289         writel(reg, mfc_regs->e_rc_qp_bound);
1290
1291         /* vbv buffer size */
1292         if (p->frame_skip_mode ==
1293                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1294                 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1295
1296                 if (p->rc_frame)
1297                         writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1298         }
1299
1300         /* VP8 specific params */
1301         reg = 0;
1302         reg |= (p_vp8->imd_4x4 & 0x1) << 10;
1303         switch (p_vp8->num_partitions) {
1304         case V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION:
1305                 val = 0;
1306                 break;
1307         case V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS:
1308                 val = 2;
1309                 break;
1310         case V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS:
1311                 val = 4;
1312                 break;
1313         case V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS:
1314                 val = 8;
1315                 break;
1316         }
1317         reg |= (val & 0xF) << 3;
1318         reg |= (p_vp8->num_ref & 0x2);
1319         writel(reg, mfc_regs->e_vp8_options);
1320
1321         mfc_debug_leave();
1322
1323         return 0;
1324 }
1325
1326 /* Initialize decoding */
1327 static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1328 {
1329         struct s5p_mfc_dev *dev = ctx->dev;
1330         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1331         unsigned int reg = 0;
1332         int fmo_aso_ctrl = 0;
1333
1334         mfc_debug_enter();
1335         mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,
1336                         S5P_FIMV_CH_SEQ_HEADER_V6);
1337         mfc_debug(2, "BUFs: %08x %08x %08x\n",
1338                   readl(mfc_regs->d_cpb_buffer_addr),
1339                   readl(mfc_regs->d_cpb_buffer_addr),
1340                   readl(mfc_regs->d_cpb_buffer_addr));
1341
1342         /* FMO_ASO_CTRL - 0: Enable, 1: Disable */
1343         reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6);
1344
1345         if (ctx->display_delay_enable) {
1346                 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6);
1347                 writel(ctx->display_delay, mfc_regs->d_display_delay);
1348         }
1349
1350         if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) {
1351                 writel(reg, mfc_regs->d_dec_options);
1352                 reg = 0;
1353         }
1354
1355         /* Setup loop filter, for decoding this is only valid for MPEG4 */
1356         if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) {
1357                 mfc_debug(2, "Set loop filter to: %d\n",
1358                                 ctx->loop_filter_mpeg4);
1359                 reg |= (ctx->loop_filter_mpeg4 <<
1360                                 S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6);
1361         }
1362         if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
1363                 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
1364
1365         if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev))
1366                 writel(reg, mfc_regs->d_init_buffer_options);
1367         else
1368                 writel(reg, mfc_regs->d_dec_options);
1369
1370         /* 0: NV12(CbCr), 1: NV21(CrCb) */
1371         if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
1372                 writel(0x1, mfc_regs->pixel_format);
1373         else
1374                 writel(0x0, mfc_regs->pixel_format);
1375
1376
1377         /* sei parse */
1378         writel(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable);
1379
1380         writel(ctx->inst_no, mfc_regs->instance_id);
1381         s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
1382                         S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1383
1384         mfc_debug_leave();
1385         return 0;
1386 }
1387
1388 static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1389 {
1390         struct s5p_mfc_dev *dev = ctx->dev;
1391         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1392
1393         if (flush) {
1394                 dev->curr_ctx = ctx->num;
1395                 writel(ctx->inst_no, mfc_regs->instance_id);
1396                 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
1397                                 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL);
1398         }
1399 }
1400
1401 /* Decode a single frame */
1402 static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
1403                         enum s5p_mfc_decode_arg last_frame)
1404 {
1405         struct s5p_mfc_dev *dev = ctx->dev;
1406         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1407
1408         writel(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower);
1409         writel(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable);
1410
1411         writel(ctx->inst_no, mfc_regs->instance_id);
1412         /* Issue different commands to instance basing on whether it
1413          * is the last frame or not. */
1414         switch (last_frame) {
1415         case 0:
1416                 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
1417                                 S5P_FIMV_CH_FRAME_START_V6, NULL);
1418                 break;
1419         case 1:
1420                 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
1421                                 S5P_FIMV_CH_LAST_FRAME_V6, NULL);
1422                 break;
1423         default:
1424                 mfc_err("Unsupported last frame arg.\n");
1425                 return -EINVAL;
1426         }
1427
1428         mfc_debug(2, "Decoding a usual frame.\n");
1429         return 0;
1430 }
1431
1432 static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1433 {
1434         struct s5p_mfc_dev *dev = ctx->dev;
1435         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1436
1437         if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1438                 s5p_mfc_set_enc_params_h264(ctx);
1439         else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)
1440                 s5p_mfc_set_enc_params_mpeg4(ctx);
1441         else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)
1442                 s5p_mfc_set_enc_params_h263(ctx);
1443         else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
1444                 s5p_mfc_set_enc_params_vp8(ctx);
1445         else {
1446                 mfc_err("Unknown codec for encoding (%x).\n",
1447                         ctx->codec_mode);
1448                 return -EINVAL;
1449         }
1450
1451         /* Set stride lengths for v7 & above */
1452         if (IS_MFCV7_PLUS(dev)) {
1453                 writel(ctx->img_width, mfc_regs->e_source_first_plane_stride);
1454                 writel(ctx->img_width, mfc_regs->e_source_second_plane_stride);
1455         }
1456
1457         writel(ctx->inst_no, mfc_regs->instance_id);
1458         s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
1459                         S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1460
1461         return 0;
1462 }
1463
1464 static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
1465 {
1466         struct s5p_mfc_dev *dev = ctx->dev;
1467         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1468         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1469         struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
1470         int i;
1471
1472         if (p_h264->aso) {
1473                 for (i = 0; i < ARRAY_SIZE(p_h264->aso_slice_order); i++) {
1474                         writel(p_h264->aso_slice_order[i],
1475                                 mfc_regs->e_h264_aso_slice_order_0 + i * 4);
1476                 }
1477         }
1478         return 0;
1479 }
1480
1481 /* Encode a single frame */
1482 static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
1483 {
1484         struct s5p_mfc_dev *dev = ctx->dev;
1485         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1486         int cmd;
1487
1488         mfc_debug(2, "++\n");
1489
1490         /* memory structure cur. frame */
1491
1492         if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1493                 s5p_mfc_h264_set_aso_slice_order_v6(ctx);
1494
1495         s5p_mfc_set_slice_mode(ctx);
1496
1497         if (ctx->state != MFCINST_FINISHING)
1498                 cmd = S5P_FIMV_CH_FRAME_START_V6;
1499         else
1500                 cmd = S5P_FIMV_CH_LAST_FRAME_V6;
1501
1502         writel(ctx->inst_no, mfc_regs->instance_id);
1503         s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, cmd, NULL);
1504
1505         mfc_debug(2, "--\n");
1506
1507         return 0;
1508 }
1509
1510 static inline int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
1511 {
1512         unsigned long flags;
1513         int new_ctx;
1514         int cnt;
1515
1516         spin_lock_irqsave(&dev->condlock, flags);
1517         mfc_debug(2, "Previous context: %d (bits %08lx)\n", dev->curr_ctx,
1518                                                         dev->ctx_work_bits);
1519         new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS;
1520         cnt = 0;
1521         while (!test_bit(new_ctx, &dev->ctx_work_bits)) {
1522                 new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS;
1523                 cnt++;
1524                 if (cnt > MFC_NUM_CONTEXTS) {
1525                         /* No contexts to run */
1526                         spin_unlock_irqrestore(&dev->condlock, flags);
1527                         return -EAGAIN;
1528                 }
1529         }
1530         spin_unlock_irqrestore(&dev->condlock, flags);
1531         return new_ctx;
1532 }
1533
1534 static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)
1535 {
1536         struct s5p_mfc_dev *dev = ctx->dev;
1537
1538         s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1539         dev->curr_ctx = ctx->num;
1540         s5p_mfc_decode_one_frame_v6(ctx, MFC_DEC_LAST_FRAME);
1541 }
1542
1543 static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)
1544 {
1545         struct s5p_mfc_dev *dev = ctx->dev;
1546         struct s5p_mfc_buf *temp_vb;
1547         unsigned long flags;
1548         int last_frame = 0;
1549
1550         if (ctx->state == MFCINST_FINISHING) {
1551                 last_frame = MFC_DEC_LAST_FRAME;
1552                 s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1553                 dev->curr_ctx = ctx->num;
1554                 s5p_mfc_clean_ctx_int_flags(ctx);
1555                 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1556                 return 0;
1557         }
1558
1559         spin_lock_irqsave(&dev->irqlock, flags);
1560         /* Frames are being decoded */
1561         if (list_empty(&ctx->src_queue)) {
1562                 mfc_debug(2, "No src buffers.\n");
1563                 spin_unlock_irqrestore(&dev->irqlock, flags);
1564                 return -EAGAIN;
1565         }
1566         /* Get the next source buffer */
1567         temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1568         temp_vb->flags |= MFC_BUF_FLAG_USED;
1569         s5p_mfc_set_dec_stream_buffer_v6(ctx,
1570                 vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0),
1571                         ctx->consumed_stream,
1572                         temp_vb->b->vb2_buf.planes[0].bytesused);
1573         spin_unlock_irqrestore(&dev->irqlock, flags);
1574
1575         dev->curr_ctx = ctx->num;
1576         if (temp_vb->b->vb2_buf.planes[0].bytesused == 0) {
1577                 last_frame = 1;
1578                 mfc_debug(2, "Setting ctx->state to FINISHING\n");
1579                 ctx->state = MFCINST_FINISHING;
1580         }
1581         s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1582
1583         return 0;
1584 }
1585
1586 static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1587 {
1588         struct s5p_mfc_dev *dev = ctx->dev;
1589         unsigned long flags;
1590         struct s5p_mfc_buf *dst_mb;
1591         struct s5p_mfc_buf *src_mb;
1592         unsigned long src_y_addr, src_c_addr, dst_addr;
1593         /*
1594         unsigned int src_y_size, src_c_size;
1595         */
1596         unsigned int dst_size;
1597
1598         spin_lock_irqsave(&dev->irqlock, flags);
1599
1600         if (list_empty(&ctx->src_queue) && ctx->state != MFCINST_FINISHING) {
1601                 mfc_debug(2, "no src buffers.\n");
1602                 spin_unlock_irqrestore(&dev->irqlock, flags);
1603                 return -EAGAIN;
1604         }
1605
1606         if (list_empty(&ctx->dst_queue)) {
1607                 mfc_debug(2, "no dst buffers.\n");
1608                 spin_unlock_irqrestore(&dev->irqlock, flags);
1609                 return -EAGAIN;
1610         }
1611
1612         if (list_empty(&ctx->src_queue)) {
1613                 /* send null frame */
1614                 s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0);
1615                 src_mb = NULL;
1616         } else {
1617                 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1618                 src_mb->flags |= MFC_BUF_FLAG_USED;
1619                 if (src_mb->b->vb2_buf.planes[0].bytesused == 0) {
1620                         s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0);
1621                         ctx->state = MFCINST_FINISHING;
1622                 } else {
1623                         src_y_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 0);
1624                         src_c_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 1);
1625
1626                         mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr);
1627                         mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr);
1628
1629                         s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr);
1630                         if (src_mb->flags & MFC_BUF_FLAG_EOS)
1631                                 ctx->state = MFCINST_FINISHING;
1632                 }
1633         }
1634
1635         dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1636         dst_mb->flags |= MFC_BUF_FLAG_USED;
1637         dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0);
1638         dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0);
1639
1640         s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1641
1642         spin_unlock_irqrestore(&dev->irqlock, flags);
1643
1644         dev->curr_ctx = ctx->num;
1645         s5p_mfc_encode_one_frame_v6(ctx);
1646
1647         return 0;
1648 }
1649
1650 static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
1651 {
1652         struct s5p_mfc_dev *dev = ctx->dev;
1653         unsigned long flags;
1654         struct s5p_mfc_buf *temp_vb;
1655
1656         /* Initializing decoding - parsing header */
1657         spin_lock_irqsave(&dev->irqlock, flags);
1658         mfc_debug(2, "Preparing to init decoding.\n");
1659         temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1660         mfc_debug(2, "Header size: %d\n", temp_vb->b->vb2_buf.planes[0].bytesused);
1661         s5p_mfc_set_dec_stream_buffer_v6(ctx,
1662                 vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0), 0,
1663                         temp_vb->b->vb2_buf.planes[0].bytesused);
1664         spin_unlock_irqrestore(&dev->irqlock, flags);
1665         dev->curr_ctx = ctx->num;
1666         s5p_mfc_init_decode_v6(ctx);
1667 }
1668
1669 static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
1670 {
1671         struct s5p_mfc_dev *dev = ctx->dev;
1672         unsigned long flags;
1673         struct s5p_mfc_buf *dst_mb;
1674         unsigned long dst_addr;
1675         unsigned int dst_size;
1676
1677         spin_lock_irqsave(&dev->irqlock, flags);
1678
1679         dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1680         dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0);
1681         dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0);
1682         s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1683         spin_unlock_irqrestore(&dev->irqlock, flags);
1684         dev->curr_ctx = ctx->num;
1685         s5p_mfc_init_encode_v6(ctx);
1686 }
1687
1688 static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
1689 {
1690         struct s5p_mfc_dev *dev = ctx->dev;
1691         int ret;
1692         /* Header was parsed now start processing
1693          * First set the output frame buffers
1694          * s5p_mfc_alloc_dec_buffers(ctx); */
1695
1696         if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
1697                 mfc_err("It seems that not all destionation buffers were\n"
1698                         "mmaped.MFC requires that all destination are mmaped\n"
1699                         "before starting processing.\n");
1700                 return -EAGAIN;
1701         }
1702
1703         dev->curr_ctx = ctx->num;
1704         ret = s5p_mfc_set_dec_frame_buffer_v6(ctx);
1705         if (ret) {
1706                 mfc_err("Failed to alloc frame mem.\n");
1707                 ctx->state = MFCINST_ERROR;
1708         }
1709         return ret;
1710 }
1711
1712 static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)
1713 {
1714         struct s5p_mfc_dev *dev = ctx->dev;
1715         int ret;
1716
1717         dev->curr_ctx = ctx->num;
1718         ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);
1719         if (ret) {
1720                 mfc_err("Failed to alloc frame mem.\n");
1721                 ctx->state = MFCINST_ERROR;
1722         }
1723         return ret;
1724 }
1725
1726 /* Try running an operation on hardware */
1727 static void s5p_mfc_try_run_v6(struct s5p_mfc_dev *dev)
1728 {
1729         struct s5p_mfc_ctx *ctx;
1730         int new_ctx;
1731         unsigned int ret = 0;
1732
1733         mfc_debug(1, "Try run dev: %p\n", dev);
1734
1735         /* Check whether hardware is not running */
1736         if (test_and_set_bit(0, &dev->hw_lock) != 0) {
1737                 /* This is perfectly ok, the scheduled ctx should wait */
1738                 mfc_debug(1, "Couldn't lock HW.\n");
1739                 return;
1740         }
1741
1742         /* Choose the context to run */
1743         new_ctx = s5p_mfc_get_new_ctx(dev);
1744         if (new_ctx < 0) {
1745                 /* No contexts to run */
1746                 if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
1747                         mfc_err("Failed to unlock hardware.\n");
1748                         return;
1749                 }
1750
1751                 mfc_debug(1, "No ctx is scheduled to be run.\n");
1752                 return;
1753         }
1754
1755         mfc_debug(1, "New context: %d\n", new_ctx);
1756         ctx = dev->ctx[new_ctx];
1757         mfc_debug(1, "Setting new context to %p\n", ctx);
1758         /* Got context to run in ctx */
1759         mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",
1760                 ctx->dst_queue_cnt, ctx->pb_count, ctx->src_queue_cnt);
1761         mfc_debug(1, "ctx->state=%d\n", ctx->state);
1762         /* Last frame has already been sent to MFC
1763          * Now obtaining frames from MFC buffer */
1764
1765         s5p_mfc_clock_on();
1766         s5p_mfc_clean_ctx_int_flags(ctx);
1767
1768         if (ctx->type == MFCINST_DECODER) {
1769                 switch (ctx->state) {
1770                 case MFCINST_FINISHING:
1771                         s5p_mfc_run_dec_last_frames(ctx);
1772                         break;
1773                 case MFCINST_RUNNING:
1774                         ret = s5p_mfc_run_dec_frame(ctx);
1775                         break;
1776                 case MFCINST_INIT:
1777                         ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1778                                         ctx);
1779                         break;
1780                 case MFCINST_RETURN_INST:
1781                         ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1782                                         ctx);
1783                         break;
1784                 case MFCINST_GOT_INST:
1785                         s5p_mfc_run_init_dec(ctx);
1786                         break;
1787                 case MFCINST_HEAD_PARSED:
1788                         ret = s5p_mfc_run_init_dec_buffers(ctx);
1789                         break;
1790                 case MFCINST_FLUSH:
1791                         s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
1792                         break;
1793                 case MFCINST_RES_CHANGE_INIT:
1794                         s5p_mfc_run_dec_last_frames(ctx);
1795                         break;
1796                 case MFCINST_RES_CHANGE_FLUSH:
1797                         s5p_mfc_run_dec_last_frames(ctx);
1798                         break;
1799                 case MFCINST_RES_CHANGE_END:
1800                         mfc_debug(2, "Finished remaining frames after resolution change.\n");
1801                         ctx->capture_state = QUEUE_FREE;
1802                         mfc_debug(2, "Will re-init the codec`.\n");
1803                         s5p_mfc_run_init_dec(ctx);
1804                         break;
1805                 default:
1806                         ret = -EAGAIN;
1807                 }
1808         } else if (ctx->type == MFCINST_ENCODER) {
1809                 switch (ctx->state) {
1810                 case MFCINST_FINISHING:
1811                 case MFCINST_RUNNING:
1812                         ret = s5p_mfc_run_enc_frame(ctx);
1813                         break;
1814                 case MFCINST_INIT:
1815                         ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1816                                         ctx);
1817                         break;
1818                 case MFCINST_RETURN_INST:
1819                         ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1820                                         ctx);
1821                         break;
1822                 case MFCINST_GOT_INST:
1823                         s5p_mfc_run_init_enc(ctx);
1824                         break;
1825                 case MFCINST_HEAD_PRODUCED:
1826                         ret = s5p_mfc_run_init_enc_buffers(ctx);
1827                         break;
1828                 default:
1829                         ret = -EAGAIN;
1830                 }
1831         } else {
1832                 mfc_err("invalid context type: %d\n", ctx->type);
1833                 ret = -EAGAIN;
1834         }
1835
1836         if (ret) {
1837                 /* Free hardware lock */
1838                 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
1839                         mfc_err("Failed to unlock hardware.\n");
1840
1841                 /* This is in deed imporant, as no operation has been
1842                  * scheduled, reduce the clock count as no one will
1843                  * ever do this, because no interrupt related to this try_run
1844                  * will ever come from hardware. */
1845                 s5p_mfc_clock_off();
1846         }
1847 }
1848
1849
1850 static void s5p_mfc_cleanup_queue_v6(struct list_head *lh, struct vb2_queue *vq)
1851 {
1852         struct s5p_mfc_buf *b;
1853         int i;
1854
1855         while (!list_empty(lh)) {
1856                 b = list_entry(lh->next, struct s5p_mfc_buf, list);
1857                 for (i = 0; i < b->b->vb2_buf.num_planes; i++)
1858                         vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
1859                 vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
1860                 list_del(&b->list);
1861         }
1862 }
1863
1864 static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev)
1865 {
1866         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1867         writel(0, mfc_regs->risc2host_command);
1868         writel(0, mfc_regs->risc2host_int);
1869 }
1870
1871 static void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data,
1872                 unsigned int ofs)
1873 {
1874         s5p_mfc_clock_on();
1875         writel(data, (void __iomem *)((unsigned long)ofs));
1876         s5p_mfc_clock_off();
1877 }
1878
1879 static unsigned int
1880 s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned long ofs)
1881 {
1882         int ret;
1883
1884         s5p_mfc_clock_on();
1885         ret = readl((void __iomem *)ofs);
1886         s5p_mfc_clock_off();
1887
1888         return ret;
1889 }
1890
1891 static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev)
1892 {
1893         return readl(dev->mfc_regs->d_display_first_plane_addr);
1894 }
1895
1896 static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev)
1897 {
1898         return readl(dev->mfc_regs->d_decoded_first_plane_addr);
1899 }
1900
1901 static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev)
1902 {
1903         return readl(dev->mfc_regs->d_display_status);
1904 }
1905
1906 static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev)
1907 {
1908         return readl(dev->mfc_regs->d_decoded_status);
1909 }
1910
1911 static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev)
1912 {
1913         return readl(dev->mfc_regs->d_decoded_frame_type) &
1914                 S5P_FIMV_DECODE_FRAME_MASK_V6;
1915 }
1916
1917 static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)
1918 {
1919         struct s5p_mfc_dev *dev = ctx->dev;
1920         return readl(dev->mfc_regs->d_display_frame_type) &
1921                 S5P_FIMV_DECODE_FRAME_MASK_V6;
1922 }
1923
1924 static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev)
1925 {
1926         return readl(dev->mfc_regs->d_decoded_nal_size);
1927 }
1928
1929 static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev)
1930 {
1931         return readl(dev->mfc_regs->risc2host_command) &
1932                 S5P_FIMV_RISC2HOST_CMD_MASK;
1933 }
1934
1935 static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev)
1936 {
1937         return readl(dev->mfc_regs->error_code);
1938 }
1939
1940 static int s5p_mfc_err_dec_v6(unsigned int err)
1941 {
1942         return (err & S5P_FIMV_ERR_DEC_MASK_V6) >> S5P_FIMV_ERR_DEC_SHIFT_V6;
1943 }
1944
1945 static int s5p_mfc_err_dspl_v6(unsigned int err)
1946 {
1947         return (err & S5P_FIMV_ERR_DSPL_MASK_V6) >> S5P_FIMV_ERR_DSPL_SHIFT_V6;
1948 }
1949
1950 static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev)
1951 {
1952         return readl(dev->mfc_regs->d_display_frame_width);
1953 }
1954
1955 static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev)
1956 {
1957         return readl(dev->mfc_regs->d_display_frame_height);
1958 }
1959
1960 static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev)
1961 {
1962         return readl(dev->mfc_regs->d_min_num_dpb);
1963 }
1964
1965 static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)
1966 {
1967         return readl(dev->mfc_regs->d_min_num_mv);
1968 }
1969
1970 static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)
1971 {
1972         return readl(dev->mfc_regs->ret_instance_id);
1973 }
1974
1975 static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev)
1976 {
1977         return readl(dev->mfc_regs->e_num_dpb);
1978 }
1979
1980 static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev)
1981 {
1982         return readl(dev->mfc_regs->e_stream_size);
1983 }
1984
1985 static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev)
1986 {
1987         return readl(dev->mfc_regs->e_slice_type);
1988 }
1989
1990 static int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev)
1991 {
1992         return readl(dev->mfc_regs->e_picture_count);
1993 }
1994
1995 static int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx)
1996 {
1997         struct s5p_mfc_dev *dev = ctx->dev;
1998         return readl(dev->mfc_regs->d_frame_pack_sei_avail);
1999 }
2000
2001 static int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev)
2002 {
2003         return readl(dev->mfc_regs->d_mvc_num_views);
2004 }
2005
2006 static int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev)
2007 {
2008         return readl(dev->mfc_regs->d_mvc_view_id);
2009 }
2010
2011 static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)
2012 {
2013         return s5p_mfc_read_info_v6(ctx,
2014                 (__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_top);
2015 }
2016
2017 static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx)
2018 {
2019         return s5p_mfc_read_info_v6(ctx,
2020                 (__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_bot);
2021 }
2022
2023 static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx)
2024 {
2025         return s5p_mfc_read_info_v6(ctx,
2026                 (__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info1);
2027 }
2028
2029 static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
2030 {
2031         return s5p_mfc_read_info_v6(ctx,
2032                 (__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info2);
2033 }
2034
2035 static struct s5p_mfc_regs mfc_regs;
2036
2037 /* Initialize registers for MFC v6 onwards */
2038 const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)
2039 {
2040         memset(&mfc_regs, 0, sizeof(mfc_regs));
2041
2042 #define S5P_MFC_REG_ADDR(dev, reg) ((dev)->regs_base + (reg))
2043 #define R(m, r) mfc_regs.m = S5P_MFC_REG_ADDR(dev, r)
2044         /* codec common registers */
2045         R(risc_on, S5P_FIMV_RISC_ON_V6);
2046         R(risc2host_int, S5P_FIMV_RISC2HOST_INT_V6);
2047         R(host2risc_int, S5P_FIMV_HOST2RISC_INT_V6);
2048         R(risc_base_address, S5P_FIMV_RISC_BASE_ADDRESS_V6);
2049         R(mfc_reset, S5P_FIMV_MFC_RESET_V6);
2050         R(host2risc_command, S5P_FIMV_HOST2RISC_CMD_V6);
2051         R(risc2host_command, S5P_FIMV_RISC2HOST_CMD_V6);
2052         R(firmware_version, S5P_FIMV_FW_VERSION_V6);
2053         R(instance_id, S5P_FIMV_INSTANCE_ID_V6);
2054         R(codec_type, S5P_FIMV_CODEC_TYPE_V6);
2055         R(context_mem_addr, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
2056         R(context_mem_size, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
2057         R(pixel_format, S5P_FIMV_PIXEL_FORMAT_V6);
2058         R(ret_instance_id, S5P_FIMV_RET_INSTANCE_ID_V6);
2059         R(error_code, S5P_FIMV_ERROR_CODE_V6);
2060
2061         /* decoder registers */
2062         R(d_crc_ctrl, S5P_FIMV_D_CRC_CTRL_V6);
2063         R(d_dec_options, S5P_FIMV_D_DEC_OPTIONS_V6);
2064         R(d_display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6);
2065         R(d_sei_enable, S5P_FIMV_D_SEI_ENABLE_V6);
2066         R(d_min_num_dpb, S5P_FIMV_D_MIN_NUM_DPB_V6);
2067         R(d_min_num_mv, S5P_FIMV_D_MIN_NUM_MV_V6);
2068         R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V6);
2069         R(d_num_dpb, S5P_FIMV_D_NUM_DPB_V6);
2070         R(d_num_mv, S5P_FIMV_D_NUM_MV_V6);
2071         R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V6);
2072         R(d_first_plane_dpb_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6);
2073         R(d_second_plane_dpb_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6);
2074         R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6);
2075         R(d_first_plane_dpb, S5P_FIMV_D_LUMA_DPB_V6);
2076         R(d_second_plane_dpb, S5P_FIMV_D_CHROMA_DPB_V6);
2077         R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V6);
2078         R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6);
2079         R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6);
2080         R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6);
2081         R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V6);
2082         R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6);
2083         R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6);
2084         R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V6);
2085         R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6);
2086         R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6);
2087         R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6);
2088         R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V6);
2089         R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6);
2090         R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_CHROMA_ADDR_V6);
2091         R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6);
2092         R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V6);
2093         R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V6);
2094         R(d_display_aspect_ratio, S5P_FIMV_D_DISPLAY_ASPECT_RATIO_V6);
2095         R(d_display_extended_ar, S5P_FIMV_D_DISPLAY_EXTENDED_AR_V6);
2096         R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V6);
2097         R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_LUMA_ADDR_V6);
2098         R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_CHROMA_ADDR_V6);
2099         R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V6);
2100         R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V6);
2101         R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V6);
2102         R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V6);
2103         R(d_h264_info, S5P_FIMV_D_H264_INFO_V6);
2104         R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V6);
2105         R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6);
2106
2107         /* encoder registers */
2108         R(e_frame_width, S5P_FIMV_E_FRAME_WIDTH_V6);
2109         R(e_frame_height, S5P_FIMV_E_FRAME_HEIGHT_V6);
2110         R(e_cropped_frame_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6);
2111         R(e_cropped_frame_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
2112         R(e_frame_crop_offset, S5P_FIMV_E_FRAME_CROP_OFFSET_V6);
2113         R(e_enc_options, S5P_FIMV_E_ENC_OPTIONS_V6);
2114         R(e_picture_profile, S5P_FIMV_E_PICTURE_PROFILE_V6);
2115         R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
2116         R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
2117         R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
2118         R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V6);
2119         R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V6);
2120         R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V6);
2121         R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V6);
2122         R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V6);
2123         R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V6);
2124         R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V6);
2125         R(e_num_dpb, S5P_FIMV_E_NUM_DPB_V6);
2126         R(e_luma_dpb, S5P_FIMV_E_LUMA_DPB_V6);
2127         R(e_chroma_dpb, S5P_FIMV_E_CHROMA_DPB_V6);
2128         R(e_me_buffer, S5P_FIMV_E_ME_BUFFER_V6);
2129         R(e_scratch_buffer_addr, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6);
2130         R(e_scratch_buffer_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6);
2131         R(e_tmv_buffer0, S5P_FIMV_E_TMV_BUFFER0_V6);
2132         R(e_tmv_buffer1, S5P_FIMV_E_TMV_BUFFER1_V6);
2133         R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6);
2134         R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6);
2135         R(e_stream_buffer_addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6);
2136         R(e_stream_buffer_size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6);
2137         R(e_roi_buffer_addr, S5P_FIMV_E_ROI_BUFFER_ADDR_V6);
2138         R(e_param_change, S5P_FIMV_E_PARAM_CHANGE_V6);
2139         R(e_ir_size, S5P_FIMV_E_IR_SIZE_V6);
2140         R(e_gop_config, S5P_FIMV_E_GOP_CONFIG_V6);
2141         R(e_mslice_mode, S5P_FIMV_E_MSLICE_MODE_V6);
2142         R(e_mslice_size_mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
2143         R(e_mslice_size_bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
2144         R(e_frame_insertion, S5P_FIMV_E_FRAME_INSERTION_V6);
2145         R(e_rc_frame_rate, S5P_FIMV_E_RC_FRAME_RATE_V6);
2146         R(e_rc_bit_rate, S5P_FIMV_E_RC_BIT_RATE_V6);
2147         R(e_rc_roi_ctrl, S5P_FIMV_E_RC_ROI_CTRL_V6);
2148         R(e_picture_tag, S5P_FIMV_E_PICTURE_TAG_V6);
2149         R(e_bit_count_enable, S5P_FIMV_E_BIT_COUNT_ENABLE_V6);
2150         R(e_max_bit_count, S5P_FIMV_E_MAX_BIT_COUNT_V6);
2151         R(e_min_bit_count, S5P_FIMV_E_MIN_BIT_COUNT_V6);
2152         R(e_metadata_buffer_addr, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6);
2153         R(e_metadata_buffer_size, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6);
2154         R(e_encoded_source_first_plane_addr,
2155                         S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6);
2156         R(e_encoded_source_second_plane_addr,
2157                         S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6);
2158         R(e_stream_size, S5P_FIMV_E_STREAM_SIZE_V6);
2159         R(e_slice_type, S5P_FIMV_E_SLICE_TYPE_V6);
2160         R(e_picture_count, S5P_FIMV_E_PICTURE_COUNT_V6);
2161         R(e_ret_picture_tag, S5P_FIMV_E_RET_PICTURE_TAG_V6);
2162         R(e_recon_luma_dpb_addr, S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6);
2163         R(e_recon_chroma_dpb_addr, S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6);
2164         R(e_mpeg4_options, S5P_FIMV_E_MPEG4_OPTIONS_V6);
2165         R(e_mpeg4_hec_period, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6);
2166         R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V6);
2167         R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V6);
2168         R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V6);
2169         R(e_h264_lf_alpha_offset, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6);
2170         R(e_h264_lf_beta_offset, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6);
2171         R(e_h264_i_period, S5P_FIMV_E_H264_I_PERIOD_V6);
2172         R(e_h264_fmo_slice_grp_map_type,
2173                         S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6);
2174         R(e_h264_fmo_num_slice_grp_minus1,
2175                         S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
2176         R(e_h264_fmo_slice_grp_change_dir,
2177                         S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6);
2178         R(e_h264_fmo_slice_grp_change_rate_minus1,
2179                         S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6);
2180         R(e_h264_fmo_run_length_minus1_0,
2181                         S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6);
2182         R(e_h264_aso_slice_order_0, S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6);
2183         R(e_h264_num_t_layer, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
2184         R(e_h264_hierarchical_qp_layer0,
2185                         S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6);
2186         R(e_h264_frame_packing_sei_info,
2187                         S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6);
2188
2189         if (!IS_MFCV7_PLUS(dev))
2190                 goto done;
2191
2192         /* Initialize registers used in MFC v7+ */
2193         R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_FIRST_ADDR_V7);
2194         R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_SECOND_ADDR_V7);
2195         R(e_source_third_plane_addr, S5P_FIMV_E_SOURCE_THIRD_ADDR_V7);
2196         R(e_source_first_plane_stride, S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7);
2197         R(e_source_second_plane_stride, S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7);
2198         R(e_source_third_plane_stride, S5P_FIMV_E_SOURCE_THIRD_STRIDE_V7);
2199         R(e_encoded_source_first_plane_addr,
2200                         S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7);
2201         R(e_encoded_source_second_plane_addr,
2202                         S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);
2203         R(e_vp8_options, S5P_FIMV_E_VP8_OPTIONS_V7);
2204
2205         if (!IS_MFCV8(dev))
2206                 goto done;
2207
2208         /* Initialize registers used in MFC v8 only.
2209          * Also, over-write the registers which have
2210          * a different offset for MFC v8. */
2211         R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V8);
2212         R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V8);
2213         R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V8);
2214         R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V8);
2215         R(d_first_plane_dpb_size, S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8);
2216         R(d_second_plane_dpb_size, S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8);
2217         R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8);
2218         R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8);
2219         R(d_first_plane_dpb_stride_size,
2220                         S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8);
2221         R(d_second_plane_dpb_stride_size,
2222                         S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8);
2223         R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V8);
2224         R(d_num_mv, S5P_FIMV_D_NUM_MV_V8);
2225         R(d_first_plane_dpb, S5P_FIMV_D_FIRST_PLANE_DPB_V8);
2226         R(d_second_plane_dpb, S5P_FIMV_D_SECOND_PLANE_DPB_V8);
2227         R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V8);
2228         R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8);
2229         R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8);
2230         R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V8);
2231         R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8);
2232         R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8);
2233         R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8);
2234         R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8);
2235         R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V8);
2236         R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V8);
2237         R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V8);
2238         R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8);
2239         R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V8);
2240         R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8);
2241         R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8);
2242         R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8);
2243         R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V8);
2244         R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V8);
2245         R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8);
2246         R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8);
2247         R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V8);
2248         R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V8);
2249
2250         /* encoder registers */
2251         R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V8);
2252         R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V8);
2253         R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V8);
2254         R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V8);
2255         R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V8);
2256         R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V8);
2257         R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V8);
2258         R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V8);
2259         R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V8);
2260         R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V8);
2261         R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V8);
2262         R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V8);
2263         R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8);
2264
2265 done:
2266         return &mfc_regs;
2267 #undef S5P_MFC_REG_ADDR
2268 #undef R
2269 }
2270
2271 /* Initialize opr function pointers for MFC v6 */
2272 static struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = {
2273         .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v6,
2274         .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v6,
2275         .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v6,
2276         .release_codec_buffers = s5p_mfc_release_codec_buffers_v6,
2277         .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v6,
2278         .release_instance_buffer = s5p_mfc_release_instance_buffer_v6,
2279         .alloc_dev_context_buffer =
2280                 s5p_mfc_alloc_dev_context_buffer_v6,
2281         .release_dev_context_buffer =
2282                 s5p_mfc_release_dev_context_buffer_v6,
2283         .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v6,
2284         .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v6,
2285         .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v6,
2286         .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v6,
2287         .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v6,
2288         .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v6,
2289         .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v6,
2290         .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v6,
2291         .init_decode = s5p_mfc_init_decode_v6,
2292         .init_encode = s5p_mfc_init_encode_v6,
2293         .encode_one_frame = s5p_mfc_encode_one_frame_v6,
2294         .try_run = s5p_mfc_try_run_v6,
2295         .cleanup_queue = s5p_mfc_cleanup_queue_v6,
2296         .clear_int_flags = s5p_mfc_clear_int_flags_v6,
2297         .write_info = s5p_mfc_write_info_v6,
2298         .read_info = s5p_mfc_read_info_v6,
2299         .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v6,
2300         .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v6,
2301         .get_dspl_status = s5p_mfc_get_dspl_status_v6,
2302         .get_dec_status = s5p_mfc_get_dec_status_v6,
2303         .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v6,
2304         .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v6,
2305         .get_consumed_stream = s5p_mfc_get_consumed_stream_v6,
2306         .get_int_reason = s5p_mfc_get_int_reason_v6,
2307         .get_int_err = s5p_mfc_get_int_err_v6,
2308         .err_dec = s5p_mfc_err_dec_v6,
2309         .err_dspl = s5p_mfc_err_dspl_v6,
2310         .get_img_width = s5p_mfc_get_img_width_v6,
2311         .get_img_height = s5p_mfc_get_img_height_v6,
2312         .get_dpb_count = s5p_mfc_get_dpb_count_v6,
2313         .get_mv_count = s5p_mfc_get_mv_count_v6,
2314         .get_inst_no = s5p_mfc_get_inst_no_v6,
2315         .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v6,
2316         .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v6,
2317         .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v6,
2318         .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v6,
2319         .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v6,
2320         .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v6,
2321         .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v6,
2322         .get_pic_type_top = s5p_mfc_get_pic_type_top_v6,
2323         .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6,
2324         .get_crop_info_h = s5p_mfc_get_crop_info_h_v6,
2325         .get_crop_info_v = s5p_mfc_get_crop_info_v_v6,
2326 };
2327
2328 struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void)
2329 {
2330         return &s5p_mfc_ops_v6;
2331 }