kernel/drivers/media/platform/s5p-mfc/s5p_mfc.c

   1 /*
   2  * Samsung S5P Multi Format Codec v 5.1
   3  *
   4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   5  * Kamil Debski, <k.debski@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/sched.h>
  20 #include <linux/slab.h>
  21 #include <linux/videodev2.h>
  22 #include <media/v4l2-event.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/of.h>
  25 #include <media/videobuf2-core.h>
  26 #include "s5p_mfc_common.h"
  27 #include "s5p_mfc_ctrl.h"
  28 #include "s5p_mfc_debug.h"
  29 #include "s5p_mfc_dec.h"
  30 #include "s5p_mfc_enc.h"
  31 #include "s5p_mfc_intr.h"
  32 #include "s5p_mfc_opr.h"
  33 #include "s5p_mfc_cmd.h"
  34 #include "s5p_mfc_pm.h"
  35
  36 #define S5P_MFC_NAME            "s5p-mfc"
  37 #define S5P_MFC_DEC_NAME        "s5p-mfc-dec"
  38 #define S5P_MFC_ENC_NAME        "s5p-mfc-enc"
  39
  40 int mfc_debug_level;
  41 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
  42 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
  43
  44 /* Helper functions for interrupt processing */
  45
  46 /* Remove from hw execution round robin */
  47 void clear_work_bit(struct s5p_mfc_ctx *ctx)
  48 {
  49         struct s5p_mfc_dev *dev = ctx->dev;
  50
  51         spin_lock(&dev->condlock);
  52         __clear_bit(ctx->num, &dev->ctx_work_bits);
  53         spin_unlock(&dev->condlock);
  54 }
  55
  56 /* Add to hw execution round robin */
  57 void set_work_bit(struct s5p_mfc_ctx *ctx)
  58 {
  59         struct s5p_mfc_dev *dev = ctx->dev;
  60
  61         spin_lock(&dev->condlock);
  62         __set_bit(ctx->num, &dev->ctx_work_bits);
  63         spin_unlock(&dev->condlock);
  64 }
  65
  66 /* Remove from hw execution round robin */
  67 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
  68 {
  69         struct s5p_mfc_dev *dev = ctx->dev;
  70         unsigned long flags;
  71
  72         spin_lock_irqsave(&dev->condlock, flags);
  73         __clear_bit(ctx->num, &dev->ctx_work_bits);
  74         spin_unlock_irqrestore(&dev->condlock, flags);
  75 }
  76
  77 /* Add to hw execution round robin */
  78 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
  79 {
  80         struct s5p_mfc_dev *dev = ctx->dev;
  81         unsigned long flags;
  82
  83         spin_lock_irqsave(&dev->condlock, flags);
  84         __set_bit(ctx->num, &dev->ctx_work_bits);
  85         spin_unlock_irqrestore(&dev->condlock, flags);
  86 }
  87
  88 /* Wake up context wait_queue */
  89 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
  90                         unsigned int err)
  91 {
  92         ctx->int_cond = 1;
  93         ctx->int_type = reason;
  94         ctx->int_err = err;
  95         wake_up(&ctx->queue);
  96 }
  97
  98 /* Wake up device wait_queue */
  99 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
 100                         unsigned int err)
 101 {
 102         dev->int_cond = 1;
 103         dev->int_type = reason;
 104         dev->int_err = err;
 105         wake_up(&dev->queue);
 106 }
 107
 108 static void s5p_mfc_watchdog(unsigned long arg)
 109 {
 110         struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
 111
 112         if (test_bit(0, &dev->hw_lock))
 113                 atomic_inc(&dev->watchdog_cnt);
 114         if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
 115                 /* This means that hw is busy and no interrupts were
 116                  * generated by hw for the Nth time of running this
 117                  * watchdog timer. This usually means a serious hw
 118                  * error. Now it is time to kill all instances and
 119                  * reset the MFC. */
 120                 mfc_err("Time out during waiting for HW\n");
 121                 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
 122         }
 123         dev->watchdog_timer.expires = jiffies +
 124                                         msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
 125         add_timer(&dev->watchdog_timer);
 126 }
 127
 128 static void s5p_mfc_watchdog_worker(struct work_struct *work)
 129 {
 130         struct s5p_mfc_dev *dev;
 131         struct s5p_mfc_ctx *ctx;
 132         unsigned long flags;
 133         int mutex_locked;
 134         int i, ret;
 135
 136         dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
 137
 138         mfc_err("Driver timeout error handling\n");
 139         /* Lock the mutex that protects open and release.
 140          * This is necessary as they may load and unload firmware. */
 141         mutex_locked = mutex_trylock(&dev->mfc_mutex);
 142         if (!mutex_locked)
 143                 mfc_err("Error: some instance may be closing/opening\n");
 144         spin_lock_irqsave(&dev->irqlock, flags);
 145
 146         s5p_mfc_clock_off();
 147
 148         for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
 149                 ctx = dev->ctx[i];
 150                 if (!ctx)
 151                         continue;
 152                 ctx->state = MFCINST_ERROR;
 153                 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
 154                                                 &ctx->dst_queue, &ctx->vq_dst);
 155                 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
 156                                                 &ctx->src_queue, &ctx->vq_src);
 157                 clear_work_bit(ctx);
 158                 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
 159         }
 160         clear_bit(0, &dev->hw_lock);
 161         spin_unlock_irqrestore(&dev->irqlock, flags);
 162
 163         /* De-init MFC */
 164         s5p_mfc_deinit_hw(dev);
 165
 166         /* Double check if there is at least one instance running.
 167          * If no instance is in memory than no firmware should be present */
 168         if (dev->num_inst > 0) {
 169                 ret = s5p_mfc_load_firmware(dev);
 170                 if (ret) {
 171                         mfc_err("Failed to reload FW\n");
 172                         goto unlock;
 173                 }
 174                 s5p_mfc_clock_on();
 175                 ret = s5p_mfc_init_hw(dev);
 176                 if (ret)
 177                         mfc_err("Failed to reinit FW\n");
 178         }
 179 unlock:
 180         if (mutex_locked)
 181                 mutex_unlock(&dev->mfc_mutex);
 182 }
 183
 184 static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
 185 {
 186         mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
 187         mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
 188         mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
 189 }
 190
 191 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
 192 {
 193         struct s5p_mfc_buf *dst_buf;
 194         struct s5p_mfc_dev *dev = ctx->dev;
 195
 196         ctx->state = MFCINST_FINISHED;
 197         ctx->sequence++;
 198         while (!list_empty(&ctx->dst_queue)) {
 199                 dst_buf = list_entry(ctx->dst_queue.next,
 200                                      struct s5p_mfc_buf, list);
 201                 mfc_debug(2, "Cleaning up buffer: %d\n",
 202                                           dst_buf->b->v4l2_buf.index);
 203                 vb2_set_plane_payload(dst_buf->b, 0, 0);
 204                 vb2_set_plane_payload(dst_buf->b, 1, 0);
 205                 list_del(&dst_buf->list);
 206                 ctx->dst_queue_cnt--;
 207                 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
 208
 209                 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
 210                         s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
 211                         dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
 212                 else
 213                         dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
 214
 215                 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
 216                 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
 217         }
 218 }
 219
 220 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
 221 {
 222         struct s5p_mfc_dev *dev = ctx->dev;
 223         struct s5p_mfc_buf  *dst_buf, *src_buf;
 224         size_t dec_y_addr;
 225         unsigned int frame_type;
 226
 227         /* Make sure we actually have a new frame before continuing. */
 228         frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
 229         if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
 230                 return;
 231         dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
 232
 233         /* Copy timestamp / timecode from decoded src to dst and set
 234            appropriate flags. */
 235         src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
 236         list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
 237                 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
 238                         dst_buf->b->v4l2_buf.timecode =
 239                                                 src_buf->b->v4l2_buf.timecode;
 240                         dst_buf->b->v4l2_buf.timestamp =
 241                                                 src_buf->b->v4l2_buf.timestamp;
 242                         dst_buf->b->v4l2_buf.flags &=
 243                                 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
 244                         dst_buf->b->v4l2_buf.flags |=
 245                                 src_buf->b->v4l2_buf.flags
 246                                 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
 247                         switch (frame_type) {
 248                         case S5P_FIMV_DECODE_FRAME_I_FRAME:
 249                                 dst_buf->b->v4l2_buf.flags |=
 250                                                 V4L2_BUF_FLAG_KEYFRAME;
 251                                 break;
 252                         case S5P_FIMV_DECODE_FRAME_P_FRAME:
 253                                 dst_buf->b->v4l2_buf.flags |=
 254                                                 V4L2_BUF_FLAG_PFRAME;
 255                                 break;
 256                         case S5P_FIMV_DECODE_FRAME_B_FRAME:
 257                                 dst_buf->b->v4l2_buf.flags |=
 258                                                 V4L2_BUF_FLAG_BFRAME;
 259                                 break;
 260                         default:
 261                                 /* Don't know how to handle
 262                                    S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
 263                                 mfc_debug(2, "Unexpected frame type: %d\n",
 264                                                 frame_type);
 265                         }
 266                         break;
 267                 }
 268         }
 269 }
 270
 271 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
 272 {
 273         struct s5p_mfc_dev *dev = ctx->dev;
 274         struct s5p_mfc_buf  *dst_buf;
 275         size_t dspl_y_addr;
 276         unsigned int frame_type;
 277
 278         dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
 279         if (IS_MFCV6_PLUS(dev))
 280                 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
 281                         get_disp_frame_type, ctx);
 282         else
 283                 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
 284                         get_dec_frame_type, dev);
 285
 286         /* If frame is same as previous then skip and do not dequeue */
 287         if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
 288                 if (!ctx->after_packed_pb)
 289                         ctx->sequence++;
 290                 ctx->after_packed_pb = 0;
 291                 return;
 292         }
 293         ctx->sequence++;
 294         /* The MFC returns address of the buffer, now we have to
 295          * check which videobuf does it correspond to */
 296         list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
 297                 /* Check if this is the buffer we're looking for */
 298                 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
 299                         list_del(&dst_buf->list);
 300                         ctx->dst_queue_cnt--;
 301                         dst_buf->b->v4l2_buf.sequence = ctx->sequence;
 302                         if (s5p_mfc_hw_call(dev->mfc_ops,
 303                                         get_pic_type_top, ctx) ==
 304                                 s5p_mfc_hw_call(dev->mfc_ops,
 305                                         get_pic_type_bot, ctx))
 306                                 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
 307                         else
 308                                 dst_buf->b->v4l2_buf.field =
 309                                                         V4L2_FIELD_INTERLACED;
 310                         vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
 311                         vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
 312                         clear_bit(dst_buf->b->v4l2_buf.index,
 313                                                         &ctx->dec_dst_flag);
 314
 315                         vb2_buffer_done(dst_buf->b,
 316                                 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
 317
 318                         break;
 319                 }
 320         }
 321 }
 322
 323 /* Handle frame decoding interrupt */
 324 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
 325                                         unsigned int reason, unsigned int err)
 326 {
 327         struct s5p_mfc_dev *dev = ctx->dev;
 328         unsigned int dst_frame_status;
 329         unsigned int dec_frame_status;
 330         struct s5p_mfc_buf *src_buf;
 331         unsigned long flags;
 332         unsigned int res_change;
 333
 334         dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
 335                                 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
 336         dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
 337                                 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
 338         res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
 339                                 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
 340                                 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
 341         mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
 342         if (ctx->state == MFCINST_RES_CHANGE_INIT)
 343                 ctx->state = MFCINST_RES_CHANGE_FLUSH;
 344         if (res_change == S5P_FIMV_RES_INCREASE ||
 345                 res_change == S5P_FIMV_RES_DECREASE) {
 346                 ctx->state = MFCINST_RES_CHANGE_INIT;
 347                 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 348                 wake_up_ctx(ctx, reason, err);
 349                 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 350                 s5p_mfc_clock_off();
 351                 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 352                 return;
 353         }
 354         if (ctx->dpb_flush_flag)
 355                 ctx->dpb_flush_flag = 0;
 356
 357         spin_lock_irqsave(&dev->irqlock, flags);
 358         /* All frames remaining in the buffer have been extracted  */
 359         if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
 360                 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
 361                         static const struct v4l2_event ev_src_ch = {
 362                                 .type = V4L2_EVENT_SOURCE_CHANGE,
 363                                 .u.src_change.changes =
 364                                         V4L2_EVENT_SRC_CH_RESOLUTION,
 365                         };
 366
 367                         s5p_mfc_handle_frame_all_extracted(ctx);
 368                         ctx->state = MFCINST_RES_CHANGE_END;
 369                         v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
 370
 371                         goto leave_handle_frame;
 372                 } else {
 373                         s5p_mfc_handle_frame_all_extracted(ctx);
 374                 }
 375         }
 376
 377         if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
 378                 s5p_mfc_handle_frame_copy_time(ctx);
 379
 380         /* A frame has been decoded and is in the buffer  */
 381         if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
 382             dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
 383                 s5p_mfc_handle_frame_new(ctx, err);
 384         } else {
 385                 mfc_debug(2, "No frame decode\n");
 386         }
 387         /* Mark source buffer as complete */
 388         if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
 389                 && !list_empty(&ctx->src_queue)) {
 390                 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
 391                                                                 list);
 392                 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
 393                                                 get_consumed_stream, dev);
 394                 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
 395                         ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
 396                         ctx->consumed_stream + STUFF_BYTE <
 397                         src_buf->b->v4l2_planes[0].bytesused) {
 398                         /* Run MFC again on the same buffer */
 399                         mfc_debug(2, "Running again the same buffer\n");
 400                         ctx->after_packed_pb = 1;
 401                 } else {
 402                         mfc_debug(2, "MFC needs next buffer\n");
 403                         ctx->consumed_stream = 0;
 404                         if (src_buf->flags & MFC_BUF_FLAG_EOS)
 405                                 ctx->state = MFCINST_FINISHING;
 406                         list_del(&src_buf->list);
 407                         ctx->src_queue_cnt--;
 408                         if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
 409                                 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
 410                         else
 411                                 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
 412                 }
 413         }
 414 leave_handle_frame:
 415         spin_unlock_irqrestore(&dev->irqlock, flags);
 416         if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
 417                                     || ctx->dst_queue_cnt < ctx->pb_count)
 418                 clear_work_bit(ctx);
 419         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 420         wake_up_ctx(ctx, reason, err);
 421         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 422         s5p_mfc_clock_off();
 423         /* if suspending, wake up device and do not try_run again*/
 424         if (test_bit(0, &dev->enter_suspend))
 425                 wake_up_dev(dev, reason, err);
 426         else
 427                 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 428 }
 429
 430 /* Error handling for interrupt */
 431 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
 432                 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
 433 {
 434         unsigned long flags;
 435
 436         mfc_err("Interrupt Error: %08x\n", err);
 437
 438         if (ctx != NULL) {
 439                 /* Error recovery is dependent on the state of context */
 440                 switch (ctx->state) {
 441                 case MFCINST_RES_CHANGE_INIT:
 442                 case MFCINST_RES_CHANGE_FLUSH:
 443                 case MFCINST_RES_CHANGE_END:
 444                 case MFCINST_FINISHING:
 445                 case MFCINST_FINISHED:
 446                 case MFCINST_RUNNING:
 447                         /* It is highly probable that an error occurred
 448                          * while decoding a frame */
 449                         clear_work_bit(ctx);
 450                         ctx->state = MFCINST_ERROR;
 451                         /* Mark all dst buffers as having an error */
 452                         spin_lock_irqsave(&dev->irqlock, flags);
 453                         s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
 454                                                 &ctx->dst_queue, &ctx->vq_dst);
 455                         /* Mark all src buffers as having an error */
 456                         s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
 457                                                 &ctx->src_queue, &ctx->vq_src);
 458                         spin_unlock_irqrestore(&dev->irqlock, flags);
 459                         wake_up_ctx(ctx, reason, err);
 460                         break;
 461                 default:
 462                         clear_work_bit(ctx);
 463                         ctx->state = MFCINST_ERROR;
 464                         wake_up_ctx(ctx, reason, err);
 465                         break;
 466                 }
 467         }
 468         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 469         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 470         s5p_mfc_clock_off();
 471         wake_up_dev(dev, reason, err);
 472         return;
 473 }
 474
 475 /* Header parsing interrupt handling */
 476 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
 477                                  unsigned int reason, unsigned int err)
 478 {
 479         struct s5p_mfc_dev *dev;
 480
 481         if (ctx == NULL)
 482                 return;
 483         dev = ctx->dev;
 484         if (ctx->c_ops->post_seq_start) {
 485                 if (ctx->c_ops->post_seq_start(ctx))
 486                         mfc_err("post_seq_start() failed\n");
 487         } else {
 488                 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
 489                                 dev);
 490                 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
 491                                 dev);
 492
 493                 s5p_mfc_hw_call_void(dev->mfc_ops, dec_calc_dpb_size, ctx);
 494
 495                 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
 496                                 dev);
 497                 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
 498                                 dev);
 499                 if (ctx->img_width == 0 || ctx->img_height == 0)
 500                         ctx->state = MFCINST_ERROR;
 501                 else
 502                         ctx->state = MFCINST_HEAD_PARSED;
 503
 504                 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 505                         ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
 506                                 !list_empty(&ctx->src_queue)) {
 507                         struct s5p_mfc_buf *src_buf;
 508                         src_buf = list_entry(ctx->src_queue.next,
 509                                         struct s5p_mfc_buf, list);
 510                         if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
 511                                                 dev) <
 512                                         src_buf->b->v4l2_planes[0].bytesused)
 513                                 ctx->head_processed = 0;
 514                         else
 515                                 ctx->head_processed = 1;
 516                 } else {
 517                         ctx->head_processed = 1;
 518                 }
 519         }
 520         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 521         clear_work_bit(ctx);
 522         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 523         s5p_mfc_clock_off();
 524         s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 525         wake_up_ctx(ctx, reason, err);
 526 }
 527
 528 /* Header parsing interrupt handling */
 529 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
 530                                  unsigned int reason, unsigned int err)
 531 {
 532         struct s5p_mfc_buf *src_buf;
 533         struct s5p_mfc_dev *dev;
 534         unsigned long flags;
 535
 536         if (ctx == NULL)
 537                 return;
 538         dev = ctx->dev;
 539         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 540         ctx->int_type = reason;
 541         ctx->int_err = err;
 542         ctx->int_cond = 1;
 543         clear_work_bit(ctx);
 544         if (err == 0) {
 545                 ctx->state = MFCINST_RUNNING;
 546                 if (!ctx->dpb_flush_flag && ctx->head_processed) {
 547                         spin_lock_irqsave(&dev->irqlock, flags);
 548                         if (!list_empty(&ctx->src_queue)) {
 549                                 src_buf = list_entry(ctx->src_queue.next,
 550                                              struct s5p_mfc_buf, list);
 551                                 list_del(&src_buf->list);
 552                                 ctx->src_queue_cnt--;
 553                                 vb2_buffer_done(src_buf->b,
 554                                                 VB2_BUF_STATE_DONE);
 555                         }
 556                         spin_unlock_irqrestore(&dev->irqlock, flags);
 557                 } else {
 558                         ctx->dpb_flush_flag = 0;
 559                 }
 560                 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 561
 562                 s5p_mfc_clock_off();
 563
 564                 wake_up(&ctx->queue);
 565                 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 566         } else {
 567                 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 568
 569                 s5p_mfc_clock_off();
 570
 571                 wake_up(&ctx->queue);
 572         }
 573 }
 574
 575 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
 576                                  unsigned int reason, unsigned int err)
 577 {
 578         struct s5p_mfc_dev *dev = ctx->dev;
 579         struct s5p_mfc_buf *mb_entry;
 580
 581         mfc_debug(2, "Stream completed\n");
 582
 583         s5p_mfc_clear_int_flags(dev);
 584         ctx->int_type = reason;
 585         ctx->int_err = err;
 586         ctx->state = MFCINST_FINISHED;
 587
 588         spin_lock(&dev->irqlock);
 589         if (!list_empty(&ctx->dst_queue)) {
 590                 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
 591                                                                         list);
 592                 list_del(&mb_entry->list);
 593                 ctx->dst_queue_cnt--;
 594                 vb2_set_plane_payload(mb_entry->b, 0, 0);
 595                 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
 596         }
 597         spin_unlock(&dev->irqlock);
 598
 599         clear_work_bit(ctx);
 600
 601         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 602
 603         s5p_mfc_clock_off();
 604         wake_up(&ctx->queue);
 605         s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 606 }
 607
 608 /* Interrupt processing */
 609 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
 610 {
 611         struct s5p_mfc_dev *dev = priv;
 612         struct s5p_mfc_ctx *ctx;
 613         unsigned int reason;
 614         unsigned int err;
 615
 616         mfc_debug_enter();
 617         /* Reset the timeout watchdog */
 618         atomic_set(&dev->watchdog_cnt, 0);
 619         ctx = dev->ctx[dev->curr_ctx];
 620         /* Get the reason of interrupt and the error code */
 621         reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
 622         err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
 623         mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
 624         switch (reason) {
 625         case S5P_MFC_R2H_CMD_ERR_RET:
 626                 /* An error has occurred */
 627                 if (ctx->state == MFCINST_RUNNING &&
 628                         s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
 629                                 dev->warn_start)
 630                         s5p_mfc_handle_frame(ctx, reason, err);
 631                 else
 632                         s5p_mfc_handle_error(dev, ctx, reason, err);
 633                 clear_bit(0, &dev->enter_suspend);
 634                 break;
 635
 636         case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
 637         case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
 638         case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
 639                 if (ctx->c_ops->post_frame_start) {
 640                         if (ctx->c_ops->post_frame_start(ctx))
 641                                 mfc_err("post_frame_start() failed\n");
 642                         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 643                         wake_up_ctx(ctx, reason, err);
 644                         WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
 645                         s5p_mfc_clock_off();
 646                         s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 647                 } else {
 648                         s5p_mfc_handle_frame(ctx, reason, err);
 649                 }
 650                 break;
 651
 652         case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
 653                 s5p_mfc_handle_seq_done(ctx, reason, err);
 654                 break;
 655
 656         case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
 657                 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
 658                 ctx->state = MFCINST_GOT_INST;
 659                 clear_work_bit(ctx);
 660                 wake_up(&ctx->queue);
 661                 goto irq_cleanup_hw;
 662
 663         case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
 664                 clear_work_bit(ctx);
 665                 ctx->inst_no = MFC_NO_INSTANCE_SET;
 666                 ctx->state = MFCINST_FREE;
 667                 wake_up(&ctx->queue);
 668                 goto irq_cleanup_hw;
 669
 670         case S5P_MFC_R2H_CMD_SYS_INIT_RET:
 671         case S5P_MFC_R2H_CMD_FW_STATUS_RET:
 672         case S5P_MFC_R2H_CMD_SLEEP_RET:
 673         case S5P_MFC_R2H_CMD_WAKEUP_RET:
 674                 if (ctx)
 675                         clear_work_bit(ctx);
 676                 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 677                 wake_up_dev(dev, reason, err);
 678                 clear_bit(0, &dev->hw_lock);
 679                 clear_bit(0, &dev->enter_suspend);
 680                 break;
 681
 682         case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
 683                 s5p_mfc_handle_init_buffers(ctx, reason, err);
 684                 break;
 685
 686         case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
 687                 s5p_mfc_handle_stream_complete(ctx, reason, err);
 688                 break;
 689
 690         case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
 691                 clear_work_bit(ctx);
 692                 ctx->state = MFCINST_RUNNING;
 693                 wake_up(&ctx->queue);
 694                 goto irq_cleanup_hw;
 695
 696         default:
 697                 mfc_debug(2, "Unknown int reason\n");
 698                 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 699         }
 700         mfc_debug_leave();
 701         return IRQ_HANDLED;
 702 irq_cleanup_hw:
 703         s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
 704         ctx->int_type = reason;
 705         ctx->int_err = err;
 706         ctx->int_cond = 1;
 707         if (test_and_clear_bit(0, &dev->hw_lock) == 0)
 708                 mfc_err("Failed to unlock hw\n");
 709
 710         s5p_mfc_clock_off();
 711
 712         s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
 713         mfc_debug(2, "Exit via irq_cleanup_hw\n");
 714         return IRQ_HANDLED;
 715 }
 716
 717 /* Open an MFC node */
 718 static int s5p_mfc_open(struct file *file)
 719 {
 720         struct video_device *vdev = video_devdata(file);
 721         struct s5p_mfc_dev *dev = video_drvdata(file);
 722         struct s5p_mfc_ctx *ctx = NULL;
 723         struct vb2_queue *q;
 724         int ret = 0;
 725
 726         mfc_debug_enter();
 727         if (mutex_lock_interruptible(&dev->mfc_mutex))
 728                 return -ERESTARTSYS;
 729         dev->num_inst++;        /* It is guarded by mfc_mutex in vfd */
 730         /* Allocate memory for context */
 731         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
 732         if (!ctx) {
 733                 mfc_err("Not enough memory\n");
 734                 ret = -ENOMEM;
 735                 goto err_alloc;
 736         }
 737         v4l2_fh_init(&ctx->fh, vdev);
 738         file->private_data = &ctx->fh;
 739         v4l2_fh_add(&ctx->fh);
 740         ctx->dev = dev;
 741         INIT_LIST_HEAD(&ctx->src_queue);
 742         INIT_LIST_HEAD(&ctx->dst_queue);
 743         ctx->src_queue_cnt = 0;
 744         ctx->dst_queue_cnt = 0;
 745         /* Get context number */
 746         ctx->num = 0;
 747         while (dev->ctx[ctx->num]) {
 748                 ctx->num++;
 749                 if (ctx->num >= MFC_NUM_CONTEXTS) {
 750                         mfc_err("Too many open contexts\n");
 751                         ret = -EBUSY;
 752                         goto err_no_ctx;
 753                 }
 754         }
 755         /* Mark context as idle */
 756         clear_work_bit_irqsave(ctx);
 757         dev->ctx[ctx->num] = ctx;
 758         if (vdev == dev->vfd_dec) {
 759                 ctx->type = MFCINST_DECODER;
 760                 ctx->c_ops = get_dec_codec_ops();
 761                 s5p_mfc_dec_init(ctx);
 762                 /* Setup ctrl handler */
 763                 ret = s5p_mfc_dec_ctrls_setup(ctx);
 764                 if (ret) {
 765                         mfc_err("Failed to setup mfc controls\n");
 766                         goto err_ctrls_setup;
 767                 }
 768         } else if (vdev == dev->vfd_enc) {
 769                 ctx->type = MFCINST_ENCODER;
 770                 ctx->c_ops = get_enc_codec_ops();
 771                 /* only for encoder */
 772                 INIT_LIST_HEAD(&ctx->ref_queue);
 773                 ctx->ref_queue_cnt = 0;
 774                 s5p_mfc_enc_init(ctx);
 775                 /* Setup ctrl handler */
 776                 ret = s5p_mfc_enc_ctrls_setup(ctx);
 777                 if (ret) {
 778                         mfc_err("Failed to setup mfc controls\n");
 779                         goto err_ctrls_setup;
 780                 }
 781         } else {
 782                 ret = -ENOENT;
 783                 goto err_bad_node;
 784         }
 785         ctx->fh.ctrl_handler = &ctx->ctrl_handler;
 786         ctx->inst_no = MFC_NO_INSTANCE_SET;
 787         /* Load firmware if this is the first instance */
 788         if (dev->num_inst == 1) {
 789                 dev->watchdog_timer.expires = jiffies +
 790                                         msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
 791                 add_timer(&dev->watchdog_timer);
 792                 ret = s5p_mfc_power_on();
 793                 if (ret < 0) {
 794                         mfc_err("power on failed\n");
 795                         goto err_pwr_enable;
 796                 }
 797                 s5p_mfc_clock_on();
 798                 ret = s5p_mfc_load_firmware(dev);
 799                 if (ret) {
 800                         s5p_mfc_clock_off();
 801                         goto err_load_fw;
 802                 }
 803                 /* Init the FW */
 804                 ret = s5p_mfc_init_hw(dev);
 805                 s5p_mfc_clock_off();
 806                 if (ret)
 807                         goto err_init_hw;
 808         }
 809         /* Init videobuf2 queue for CAPTURE */
 810         q = &ctx->vq_dst;
 811         q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
 812         q->drv_priv = &ctx->fh;
 813         q->lock = &dev->mfc_mutex;
 814         if (vdev == dev->vfd_dec) {
 815                 q->io_modes = VB2_MMAP;
 816                 q->ops = get_dec_queue_ops();
 817         } else if (vdev == dev->vfd_enc) {
 818                 q->io_modes = VB2_MMAP | VB2_USERPTR;
 819                 q->ops = get_enc_queue_ops();
 820         } else {
 821                 ret = -ENOENT;
 822                 goto err_queue_init;
 823         }
 824         q->mem_ops = &vb2_dma_contig_memops;
 825         q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
 826         ret = vb2_queue_init(q);
 827         if (ret) {
 828                 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
 829                 goto err_queue_init;
 830         }
 831         /* Init videobuf2 queue for OUTPUT */
 832         q = &ctx->vq_src;
 833         q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
 834         q->io_modes = VB2_MMAP;
 835         q->drv_priv = &ctx->fh;
 836         q->lock = &dev->mfc_mutex;
 837         if (vdev == dev->vfd_dec) {
 838                 q->io_modes = VB2_MMAP;
 839                 q->ops = get_dec_queue_ops();
 840         } else if (vdev == dev->vfd_enc) {
 841                 q->io_modes = VB2_MMAP | VB2_USERPTR;
 842                 q->ops = get_enc_queue_ops();
 843         } else {
 844                 ret = -ENOENT;
 845                 goto err_queue_init;
 846         }
 847         /* One way to indicate end-of-stream for MFC is to set the
 848          * bytesused == 0. However by default videobuf2 handles bytesused
 849          * equal to 0 as a special case and changes its value to the size
 850          * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
 851          * will keep the value of bytesused intact.
 852          */
 853         q->allow_zero_bytesused = 1;
 854         q->mem_ops = &vb2_dma_contig_memops;
 855         q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
 856         ret = vb2_queue_init(q);
 857         if (ret) {
 858                 mfc_err("Failed to initialize videobuf2 queue(output)\n");
 859                 goto err_queue_init;
 860         }
 861         init_waitqueue_head(&ctx->queue);
 862         mutex_unlock(&dev->mfc_mutex);
 863         mfc_debug_leave();
 864         return ret;
 865         /* Deinit when failure occurred */
 866 err_queue_init:
 867         if (dev->num_inst == 1)
 868                 s5p_mfc_deinit_hw(dev);
 869 err_init_hw:
 870 err_load_fw:
 871 err_pwr_enable:
 872         if (dev->num_inst == 1) {
 873                 if (s5p_mfc_power_off() < 0)
 874                         mfc_err("power off failed\n");
 875                 del_timer_sync(&dev->watchdog_timer);
 876         }
 877 err_ctrls_setup:
 878         s5p_mfc_dec_ctrls_delete(ctx);
 879 err_bad_node:
 880         dev->ctx[ctx->num] = NULL;
 881 err_no_ctx:
 882         v4l2_fh_del(&ctx->fh);
 883         v4l2_fh_exit(&ctx->fh);
 884         kfree(ctx);
 885 err_alloc:
 886         dev->num_inst--;
 887         mutex_unlock(&dev->mfc_mutex);
 888         mfc_debug_leave();
 889         return ret;
 890 }
 891
 892 /* Release MFC context */
 893 static int s5p_mfc_release(struct file *file)
 894 {
 895         struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
 896         struct s5p_mfc_dev *dev = ctx->dev;
 897
 898         mfc_debug_enter();
 899         mutex_lock(&dev->mfc_mutex);
 900         s5p_mfc_clock_on();
 901         vb2_queue_release(&ctx->vq_src);
 902         vb2_queue_release(&ctx->vq_dst);
 903         /* Mark context as idle */
 904         clear_work_bit_irqsave(ctx);
 905         /* If instance was initialised and not yet freed,
 906          * return instance and free resources */
 907         if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
 908                 mfc_debug(2, "Has to free instance\n");
 909                 s5p_mfc_close_mfc_inst(dev, ctx);
 910         }
 911         /* hardware locking scheme */
 912         if (dev->curr_ctx == ctx->num)
 913                 clear_bit(0, &dev->hw_lock);
 914         dev->num_inst--;
 915         if (dev->num_inst == 0) {
 916                 mfc_debug(2, "Last instance\n");
 917                 s5p_mfc_deinit_hw(dev);
 918                 del_timer_sync(&dev->watchdog_timer);
 919                 if (s5p_mfc_power_off() < 0)
 920                         mfc_err("Power off failed\n");
 921         }
 922         mfc_debug(2, "Shutting down clock\n");
 923         s5p_mfc_clock_off();
 924         dev->ctx[ctx->num] = NULL;
 925         s5p_mfc_dec_ctrls_delete(ctx);
 926         v4l2_fh_del(&ctx->fh);
 927         v4l2_fh_exit(&ctx->fh);
 928         kfree(ctx);
 929         mfc_debug_leave();
 930         mutex_unlock(&dev->mfc_mutex);
 931         return 0;
 932 }
 933
 934 /* Poll */
 935 static unsigned int s5p_mfc_poll(struct file *file,
 936                                  struct poll_table_struct *wait)
 937 {
 938         struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
 939         struct s5p_mfc_dev *dev = ctx->dev;
 940         struct vb2_queue *src_q, *dst_q;
 941         struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
 942         unsigned int rc = 0;
 943         unsigned long flags;
 944
 945         mutex_lock(&dev->mfc_mutex);
 946         src_q = &ctx->vq_src;
 947         dst_q = &ctx->vq_dst;
 948         /*
 949          * There has to be at least one buffer queued on each queued_list, which
 950          * means either in driver already or waiting for driver to claim it
 951          * and start processing.
 952          */
 953         if ((!src_q->streaming || list_empty(&src_q->queued_list))
 954                 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
 955                 rc = POLLERR;
 956                 goto end;
 957         }
 958         mutex_unlock(&dev->mfc_mutex);
 959         poll_wait(file, &ctx->fh.wait, wait);
 960         poll_wait(file, &src_q->done_wq, wait);
 961         poll_wait(file, &dst_q->done_wq, wait);
 962         mutex_lock(&dev->mfc_mutex);
 963         if (v4l2_event_pending(&ctx->fh))
 964                 rc |= POLLPRI;
 965         spin_lock_irqsave(&src_q->done_lock, flags);
 966         if (!list_empty(&src_q->done_list))
 967                 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
 968                                                                 done_entry);
 969         if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
 970                                 || src_vb->state == VB2_BUF_STATE_ERROR))
 971                 rc |= POLLOUT | POLLWRNORM;
 972         spin_unlock_irqrestore(&src_q->done_lock, flags);
 973         spin_lock_irqsave(&dst_q->done_lock, flags);
 974         if (!list_empty(&dst_q->done_list))
 975                 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
 976                                                                 done_entry);
 977         if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
 978                                 || dst_vb->state == VB2_BUF_STATE_ERROR))
 979                 rc |= POLLIN | POLLRDNORM;
 980         spin_unlock_irqrestore(&dst_q->done_lock, flags);
 981 end:
 982         mutex_unlock(&dev->mfc_mutex);
 983         return rc;
 984 }
 985
 986 /* Mmap */
 987 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
 988 {
 989         struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
 990         struct s5p_mfc_dev *dev = ctx->dev;
 991         unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
 992         int ret;
 993
 994         if (mutex_lock_interruptible(&dev->mfc_mutex))
 995                 return -ERESTARTSYS;
 996         if (offset < DST_QUEUE_OFF_BASE) {
 997                 mfc_debug(2, "mmaping source\n");
 998                 ret = vb2_mmap(&ctx->vq_src, vma);
 999         } else {                /* capture */
1000                 mfc_debug(2, "mmaping destination\n");
1001                 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1002                 ret = vb2_mmap(&ctx->vq_dst, vma);
1003         }
1004         mutex_unlock(&dev->mfc_mutex);
1005         return ret;
1006 }
1007
1008 /* v4l2 ops */
1009 static const struct v4l2_file_operations s5p_mfc_fops = {
1010         .owner = THIS_MODULE,
1011         .open = s5p_mfc_open,
1012         .release = s5p_mfc_release,
1013         .poll = s5p_mfc_poll,
1014         .unlocked_ioctl = video_ioctl2,
1015         .mmap = s5p_mfc_mmap,
1016 };
1017
1018 static int match_child(struct device *dev, void *data)
1019 {
1020         if (!dev_name(dev))
1021                 return 0;
1022         return !strcmp(dev_name(dev), (char *)data);
1023 }
1024
1025 static void *mfc_get_drv_data(struct platform_device *pdev);
1026
1027 static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev)
1028 {
1029         unsigned int mem_info[2] = { };
1030
1031         dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev,
1032                         sizeof(struct device), GFP_KERNEL);
1033         if (!dev->mem_dev_l) {
1034                 mfc_err("Not enough memory\n");
1035                 return -ENOMEM;
1036         }
1037         device_initialize(dev->mem_dev_l);
1038         of_property_read_u32_array(dev->plat_dev->dev.of_node,
1039                         "samsung,mfc-l", mem_info, 2);
1040         if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1041                                 mem_info[0], mem_info[1],
1042                                 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1043                 mfc_err("Failed to declare coherent memory for\n"
1044                 "MFC device\n");
1045                 return -ENOMEM;
1046         }
1047
1048         dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev,
1049                         sizeof(struct device), GFP_KERNEL);
1050         if (!dev->mem_dev_r) {
1051                 mfc_err("Not enough memory\n");
1052                 return -ENOMEM;
1053         }
1054         device_initialize(dev->mem_dev_r);
1055         of_property_read_u32_array(dev->plat_dev->dev.of_node,
1056                         "samsung,mfc-r", mem_info, 2);
1057         if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1058                                 mem_info[0], mem_info[1],
1059                                 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1060                 pr_err("Failed to declare coherent memory for\n"
1061                 "MFC device\n");
1062                 return -ENOMEM;
1063         }
1064         return 0;
1065 }
1066
1067 /* MFC probe function */
1068 static int s5p_mfc_probe(struct platform_device *pdev)
1069 {
1070         struct s5p_mfc_dev *dev;
1071         struct video_device *vfd;
1072         struct resource *res;
1073         int ret;
1074
1075         pr_debug("%s++\n", __func__);
1076         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1077         if (!dev) {
1078                 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1079                 return -ENOMEM;
1080         }
1081
1082         spin_lock_init(&dev->irqlock);
1083         spin_lock_init(&dev->condlock);
1084         dev->plat_dev = pdev;
1085         if (!dev->plat_dev) {
1086                 dev_err(&pdev->dev, "No platform data specified\n");
1087                 return -ENODEV;
1088         }
1089
1090         dev->variant = mfc_get_drv_data(pdev);
1091
1092         ret = s5p_mfc_init_pm(dev);
1093         if (ret < 0) {
1094                 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1095                 return ret;
1096         }
1097
1098         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1099
1100         dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1101         if (IS_ERR(dev->regs_base))
1102                 return PTR_ERR(dev->regs_base);
1103
1104         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1105         if (res == NULL) {
1106                 dev_err(&pdev->dev, "failed to get irq resource\n");
1107                 ret = -ENOENT;
1108                 goto err_res;
1109         }
1110         dev->irq = res->start;
1111         ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1112                                         0, pdev->name, dev);
1113         if (ret) {
1114                 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1115                 goto err_res;
1116         }
1117
1118         if (pdev->dev.of_node) {
1119                 ret = s5p_mfc_alloc_memdevs(dev);
1120                 if (ret < 0)
1121                         goto err_res;
1122         } else {
1123                 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1124                                 "s5p-mfc-l", match_child);
1125                 if (!dev->mem_dev_l) {
1126                         mfc_err("Mem child (L) device get failed\n");
1127                         ret = -ENODEV;
1128                         goto err_res;
1129                 }
1130                 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1131                                 "s5p-mfc-r", match_child);
1132                 if (!dev->mem_dev_r) {
1133                         mfc_err("Mem child (R) device get failed\n");
1134                         ret = -ENODEV;
1135                         goto err_res;
1136                 }
1137         }
1138
1139         dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
1140         if (IS_ERR(dev->alloc_ctx[0])) {
1141                 ret = PTR_ERR(dev->alloc_ctx[0]);
1142                 goto err_res;
1143         }
1144         dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
1145         if (IS_ERR(dev->alloc_ctx[1])) {
1146                 ret = PTR_ERR(dev->alloc_ctx[1]);
1147                 goto err_mem_init_ctx_1;
1148         }
1149
1150         mutex_init(&dev->mfc_mutex);
1151
1152         ret = s5p_mfc_alloc_firmware(dev);
1153         if (ret)
1154                 goto err_alloc_fw;
1155
1156         ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1157         if (ret)
1158                 goto err_v4l2_dev_reg;
1159         init_waitqueue_head(&dev->queue);
1160
1161         /* decoder */
1162         vfd = video_device_alloc();
1163         if (!vfd) {
1164                 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1165                 ret = -ENOMEM;
1166                 goto err_dec_alloc;
1167         }
1168         vfd->fops       = &s5p_mfc_fops;
1169         vfd->ioctl_ops  = get_dec_v4l2_ioctl_ops();
1170         vfd->release    = video_device_release;
1171         vfd->lock       = &dev->mfc_mutex;
1172         vfd->v4l2_dev   = &dev->v4l2_dev;
1173         vfd->vfl_dir    = VFL_DIR_M2M;
1174         snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1175         dev->vfd_dec    = vfd;
1176         ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1177         if (ret) {
1178                 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1179                 video_device_release(vfd);
1180                 goto err_dec_reg;
1181         }
1182         v4l2_info(&dev->v4l2_dev,
1183                   "decoder registered as /dev/video%d\n", vfd->num);
1184         video_set_drvdata(vfd, dev);
1185
1186         /* encoder */
1187         vfd = video_device_alloc();
1188         if (!vfd) {
1189                 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1190                 ret = -ENOMEM;
1191                 goto err_enc_alloc;
1192         }
1193         vfd->fops       = &s5p_mfc_fops;
1194         vfd->ioctl_ops  = get_enc_v4l2_ioctl_ops();
1195         vfd->release    = video_device_release;
1196         vfd->lock       = &dev->mfc_mutex;
1197         vfd->v4l2_dev   = &dev->v4l2_dev;
1198         vfd->vfl_dir    = VFL_DIR_M2M;
1199         snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1200         dev->vfd_enc    = vfd;
1201         ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1202         if (ret) {
1203                 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1204                 video_device_release(vfd);
1205                 goto err_enc_reg;
1206         }
1207         v4l2_info(&dev->v4l2_dev,
1208                   "encoder registered as /dev/video%d\n", vfd->num);
1209         video_set_drvdata(vfd, dev);
1210         platform_set_drvdata(pdev, dev);
1211
1212         dev->hw_lock = 0;
1213         dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1214         INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1215         atomic_set(&dev->watchdog_cnt, 0);
1216         init_timer(&dev->watchdog_timer);
1217         dev->watchdog_timer.data = (unsigned long)dev;
1218         dev->watchdog_timer.function = s5p_mfc_watchdog;
1219
1220         /* Initialize HW ops and commands based on MFC version */
1221         s5p_mfc_init_hw_ops(dev);
1222         s5p_mfc_init_hw_cmds(dev);
1223         s5p_mfc_init_regs(dev);
1224
1225         pr_debug("%s--\n", __func__);
1226         return 0;
1227
1228 /* Deinit MFC if probe had failed */
1229 err_enc_reg:
1230         video_device_release(dev->vfd_enc);
1231 err_enc_alloc:
1232         video_unregister_device(dev->vfd_dec);
1233 err_dec_reg:
1234         video_device_release(dev->vfd_dec);
1235 err_dec_alloc:
1236         v4l2_device_unregister(&dev->v4l2_dev);
1237 err_v4l2_dev_reg:
1238         s5p_mfc_release_firmware(dev);
1239 err_alloc_fw:
1240         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1241 err_mem_init_ctx_1:
1242         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1243 err_res:
1244         s5p_mfc_final_pm(dev);
1245
1246         pr_debug("%s-- with error\n", __func__);
1247         return ret;
1248
1249 }
1250
1251 /* Remove the driver */
1252 static int s5p_mfc_remove(struct platform_device *pdev)
1253 {
1254         struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1255
1256         v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1257
1258         del_timer_sync(&dev->watchdog_timer);
1259         flush_workqueue(dev->watchdog_workqueue);
1260         destroy_workqueue(dev->watchdog_workqueue);
1261
1262         video_unregister_device(dev->vfd_enc);
1263         video_unregister_device(dev->vfd_dec);
1264         v4l2_device_unregister(&dev->v4l2_dev);
1265         s5p_mfc_release_firmware(dev);
1266         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1267         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1268         if (pdev->dev.of_node) {
1269                 put_device(dev->mem_dev_l);
1270                 put_device(dev->mem_dev_r);
1271         }
1272
1273         s5p_mfc_final_pm(dev);
1274         return 0;
1275 }
1276
1277 #ifdef CONFIG_PM_SLEEP
1278
1279 static int s5p_mfc_suspend(struct device *dev)
1280 {
1281         struct platform_device *pdev = to_platform_device(dev);
1282         struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1283         int ret;
1284
1285         if (m_dev->num_inst == 0)
1286                 return 0;
1287
1288         if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1289                 mfc_err("Error: going to suspend for a second time\n");
1290                 return -EIO;
1291         }
1292
1293         /* Check if we're processing then wait if it necessary. */
1294         while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1295                 /* Try and lock the HW */
1296                 /* Wait on the interrupt waitqueue */
1297                 ret = wait_event_interruptible_timeout(m_dev->queue,
1298                         m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1299                 if (ret == 0) {
1300                         mfc_err("Waiting for hardware to finish timed out\n");
1301                         clear_bit(0, &m_dev->enter_suspend);
1302                         return -EIO;
1303                 }
1304         }
1305
1306         ret = s5p_mfc_sleep(m_dev);
1307         if (ret) {
1308                 clear_bit(0, &m_dev->enter_suspend);
1309                 clear_bit(0, &m_dev->hw_lock);
1310         }
1311         return ret;
1312 }
1313
1314 static int s5p_mfc_resume(struct device *dev)
1315 {
1316         struct platform_device *pdev = to_platform_device(dev);
1317         struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1318
1319         if (m_dev->num_inst == 0)
1320                 return 0;
1321         return s5p_mfc_wakeup(m_dev);
1322 }
1323 #endif
1324
1325 #ifdef CONFIG_PM
1326 static int s5p_mfc_runtime_suspend(struct device *dev)
1327 {
1328         struct platform_device *pdev = to_platform_device(dev);
1329         struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1330
1331         atomic_set(&m_dev->pm.power, 0);
1332         return 0;
1333 }
1334
1335 static int s5p_mfc_runtime_resume(struct device *dev)
1336 {
1337         struct platform_device *pdev = to_platform_device(dev);
1338         struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1339
1340         if (!m_dev->alloc_ctx)
1341                 return 0;
1342         atomic_set(&m_dev->pm.power, 1);
1343         return 0;
1344 }
1345 #endif
1346
1347 /* Power management */
1348 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1349         SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1350         SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1351                            NULL)
1352 };
1353
1354 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1355         .h264_ctx       = MFC_H264_CTX_BUF_SIZE,
1356         .non_h264_ctx   = MFC_CTX_BUF_SIZE,
1357         .dsc            = DESC_BUF_SIZE,
1358         .shm            = SHARED_BUF_SIZE,
1359 };
1360
1361 static struct s5p_mfc_buf_size buf_size_v5 = {
1362         .fw     = MAX_FW_SIZE,
1363         .cpb    = MAX_CPB_SIZE,
1364         .priv   = &mfc_buf_size_v5,
1365 };
1366
1367 static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1368         .base = MFC_BASE_ALIGN_ORDER,
1369 };
1370
1371 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1372         .version        = MFC_VERSION,
1373         .version_bit    = MFC_V5_BIT,
1374         .port_num       = MFC_NUM_PORTS,
1375         .buf_size       = &buf_size_v5,
1376         .buf_align      = &mfc_buf_align_v5,
1377         .fw_name[0]     = "s5p-mfc.fw",
1378 };
1379
1380 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1381         .dev_ctx        = MFC_CTX_BUF_SIZE_V6,
1382         .h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1383         .other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1384         .h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1385         .other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1386 };
1387
1388 static struct s5p_mfc_buf_size buf_size_v6 = {
1389         .fw     = MAX_FW_SIZE_V6,
1390         .cpb    = MAX_CPB_SIZE_V6,
1391         .priv   = &mfc_buf_size_v6,
1392 };
1393
1394 static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1395         .base = 0,
1396 };
1397
1398 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1399         .version        = MFC_VERSION_V6,
1400         .version_bit    = MFC_V6_BIT,
1401         .port_num       = MFC_NUM_PORTS_V6,
1402         .buf_size       = &buf_size_v6,
1403         .buf_align      = &mfc_buf_align_v6,
1404         .fw_name[0]     = "s5p-mfc-v6.fw",
1405         /*
1406          * v6-v2 firmware contains bug fixes and interface change
1407          * for init buffer command
1408          */
1409         .fw_name[1]     = "s5p-mfc-v6-v2.fw",
1410 };
1411
1412 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1413         .dev_ctx        = MFC_CTX_BUF_SIZE_V7,
1414         .h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1415         .other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1416         .h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1417         .other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1418 };
1419
1420 static struct s5p_mfc_buf_size buf_size_v7 = {
1421         .fw     = MAX_FW_SIZE_V7,
1422         .cpb    = MAX_CPB_SIZE_V7,
1423         .priv   = &mfc_buf_size_v7,
1424 };
1425
1426 static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1427         .base = 0,
1428 };
1429
1430 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1431         .version        = MFC_VERSION_V7,
1432         .version_bit    = MFC_V7_BIT,
1433         .port_num       = MFC_NUM_PORTS_V7,
1434         .buf_size       = &buf_size_v7,
1435         .buf_align      = &mfc_buf_align_v7,
1436         .fw_name[0]     = "s5p-mfc-v7.fw",
1437 };
1438
1439 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1440         .dev_ctx        = MFC_CTX_BUF_SIZE_V8,
1441         .h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1442         .other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1443         .h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1444         .other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1445 };
1446
1447 static struct s5p_mfc_buf_size buf_size_v8 = {
1448         .fw     = MAX_FW_SIZE_V8,
1449         .cpb    = MAX_CPB_SIZE_V8,
1450         .priv   = &mfc_buf_size_v8,
1451 };
1452
1453 static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
1454         .base = 0,
1455 };
1456
1457 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1458         .version        = MFC_VERSION_V8,
1459         .version_bit    = MFC_V8_BIT,
1460         .port_num       = MFC_NUM_PORTS_V8,
1461         .buf_size       = &buf_size_v8,
1462         .buf_align      = &mfc_buf_align_v8,
1463         .fw_name[0]     = "s5p-mfc-v8.fw",
1464 };
1465
1466 static struct platform_device_id mfc_driver_ids[] = {
1467         {
1468                 .name = "s5p-mfc",
1469                 .driver_data = (unsigned long)&mfc_drvdata_v5,
1470         }, {
1471                 .name = "s5p-mfc-v5",
1472                 .driver_data = (unsigned long)&mfc_drvdata_v5,
1473         }, {
1474                 .name = "s5p-mfc-v6",
1475                 .driver_data = (unsigned long)&mfc_drvdata_v6,
1476         }, {
1477                 .name = "s5p-mfc-v7",
1478                 .driver_data = (unsigned long)&mfc_drvdata_v7,
1479         }, {
1480                 .name = "s5p-mfc-v8",
1481                 .driver_data = (unsigned long)&mfc_drvdata_v8,
1482         },
1483         {},
1484 };
1485 MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1486
1487 static const struct of_device_id exynos_mfc_match[] = {
1488         {
1489                 .compatible = "samsung,mfc-v5",
1490                 .data = &mfc_drvdata_v5,
1491         }, {
1492                 .compatible = "samsung,mfc-v6",
1493                 .data = &mfc_drvdata_v6,
1494         }, {
1495                 .compatible = "samsung,mfc-v7",
1496                 .data = &mfc_drvdata_v7,
1497         }, {
1498                 .compatible = "samsung,mfc-v8",
1499                 .data = &mfc_drvdata_v8,
1500         },
1501         {},
1502 };
1503 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1504
1505 static void *mfc_get_drv_data(struct platform_device *pdev)
1506 {
1507         struct s5p_mfc_variant *driver_data = NULL;
1508
1509         if (pdev->dev.of_node) {
1510                 const struct of_device_id *match;
1511                 match = of_match_node(exynos_mfc_match,
1512                                 pdev->dev.of_node);
1513                 if (match)
1514                         driver_data = (struct s5p_mfc_variant *)match->data;
1515         } else {
1516                 driver_data = (struct s5p_mfc_variant *)
1517                         platform_get_device_id(pdev)->driver_data;
1518         }
1519         return driver_data;
1520 }
1521
1522 static struct platform_driver s5p_mfc_driver = {
1523         .probe          = s5p_mfc_probe,
1524         .remove         = s5p_mfc_remove,
1525         .id_table       = mfc_driver_ids,
1526         .driver = {
1527                 .name   = S5P_MFC_NAME,
1528                 .pm     = &s5p_mfc_pm_ops,
1529                 .of_match_table = exynos_mfc_match,
1530         },
1531 };
1532
1533 module_platform_driver(s5p_mfc_driver);
1534
1535 MODULE_LICENSE("GPL");
1536 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1537 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1538