kernel/drivers/media/platform/blackfin/ppi.c

   1 /*
   2  * ppi.c Analog Devices Parallel Peripheral Interface driver
   3  *
   4  * Copyright (c) 2011 Analog Devices Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_device.h>
  23
  24 #include <asm/bfin_ppi.h>
  25 #include <asm/blackfin.h>
  26 #include <asm/cacheflush.h>
  27 #include <asm/dma.h>
  28 #include <asm/portmux.h>
  29
  30 #include <media/blackfin/ppi.h>
  31
  32 static int ppi_attach_irq(struct ppi_if *ppi, irq_handler_t handler);
  33 static void ppi_detach_irq(struct ppi_if *ppi);
  34 static int ppi_start(struct ppi_if *ppi);
  35 static int ppi_stop(struct ppi_if *ppi);
  36 static int ppi_set_params(struct ppi_if *ppi, struct ppi_params *params);
  37 static void ppi_update_addr(struct ppi_if *ppi, unsigned long addr);
  38
  39 static const struct ppi_ops ppi_ops = {
  40         .attach_irq = ppi_attach_irq,
  41         .detach_irq = ppi_detach_irq,
  42         .start = ppi_start,
  43         .stop = ppi_stop,
  44         .set_params = ppi_set_params,
  45         .update_addr = ppi_update_addr,
  46 };
  47
  48 static irqreturn_t ppi_irq_err(int irq, void *dev_id)
  49 {
  50         struct ppi_if *ppi = dev_id;
  51         const struct ppi_info *info = ppi->info;
  52
  53         switch (info->type) {
  54         case PPI_TYPE_PPI:
  55         {
  56                 struct bfin_ppi_regs *reg = info->base;
  57                 unsigned short status;
  58
  59                 /* register on bf561 is cleared when read
  60                  * others are W1C
  61                  */
  62                 status = bfin_read16(&reg->status);
  63                 if (status & 0x3000)
  64                         ppi->err = true;
  65                 bfin_write16(&reg->status, 0xff00);
  66                 break;
  67         }
  68         case PPI_TYPE_EPPI:
  69         {
  70                 struct bfin_eppi_regs *reg = info->base;
  71                 unsigned short status;
  72
  73                 status = bfin_read16(&reg->status);
  74                 if (status & 0x2)
  75                         ppi->err = true;
  76                 bfin_write16(&reg->status, 0xffff);
  77                 break;
  78         }
  79         case PPI_TYPE_EPPI3:
  80         {
  81                 struct bfin_eppi3_regs *reg = info->base;
  82                 unsigned long stat;
  83
  84                 stat = bfin_read32(&reg->stat);
  85                 if (stat & 0x2)
  86                         ppi->err = true;
  87                 bfin_write32(&reg->stat, 0xc0ff);
  88                 break;
  89         }
  90         default:
  91                 break;
  92         }
  93
  94         return IRQ_HANDLED;
  95 }
  96
  97 static int ppi_attach_irq(struct ppi_if *ppi, irq_handler_t handler)
  98 {
  99         const struct ppi_info *info = ppi->info;
 100         int ret;
 101
 102         ret = request_dma(info->dma_ch, "PPI_DMA");
 103
 104         if (ret) {
 105                 pr_err("Unable to allocate DMA channel for PPI\n");
 106                 return ret;
 107         }
 108         set_dma_callback(info->dma_ch, handler, ppi);
 109
 110         if (ppi->err_int) {
 111                 ret = request_irq(info->irq_err, ppi_irq_err, 0, "PPI ERROR", ppi);
 112                 if (ret) {
 113                         pr_err("Unable to allocate IRQ for PPI\n");
 114                         free_dma(info->dma_ch);
 115                 }
 116         }
 117         return ret;
 118 }
 119
 120 static void ppi_detach_irq(struct ppi_if *ppi)
 121 {
 122         const struct ppi_info *info = ppi->info;
 123
 124         if (ppi->err_int)
 125                 free_irq(info->irq_err, ppi);
 126         free_dma(info->dma_ch);
 127 }
 128
 129 static int ppi_start(struct ppi_if *ppi)
 130 {
 131         const struct ppi_info *info = ppi->info;
 132
 133         /* enable DMA */
 134         enable_dma(info->dma_ch);
 135
 136         /* enable PPI */
 137         ppi->ppi_control |= PORT_EN;
 138         switch (info->type) {
 139         case PPI_TYPE_PPI:
 140         {
 141                 struct bfin_ppi_regs *reg = info->base;
 142                 bfin_write16(&reg->control, ppi->ppi_control);
 143                 break;
 144         }
 145         case PPI_TYPE_EPPI:
 146         {
 147                 struct bfin_eppi_regs *reg = info->base;
 148                 bfin_write32(&reg->control, ppi->ppi_control);
 149                 break;
 150         }
 151         case PPI_TYPE_EPPI3:
 152         {
 153                 struct bfin_eppi3_regs *reg = info->base;
 154                 bfin_write32(&reg->ctl, ppi->ppi_control);
 155                 break;
 156         }
 157         default:
 158                 return -EINVAL;
 159         }
 160
 161         SSYNC();
 162         return 0;
 163 }
 164
 165 static int ppi_stop(struct ppi_if *ppi)
 166 {
 167         const struct ppi_info *info = ppi->info;
 168
 169         /* disable PPI */
 170         ppi->ppi_control &= ~PORT_EN;
 171         switch (info->type) {
 172         case PPI_TYPE_PPI:
 173         {
 174                 struct bfin_ppi_regs *reg = info->base;
 175                 bfin_write16(&reg->control, ppi->ppi_control);
 176                 break;
 177         }
 178         case PPI_TYPE_EPPI:
 179         {
 180                 struct bfin_eppi_regs *reg = info->base;
 181                 bfin_write32(&reg->control, ppi->ppi_control);
 182                 break;
 183         }
 184         case PPI_TYPE_EPPI3:
 185         {
 186                 struct bfin_eppi3_regs *reg = info->base;
 187                 bfin_write32(&reg->ctl, ppi->ppi_control);
 188                 break;
 189         }
 190         default:
 191                 return -EINVAL;
 192         }
 193
 194         /* disable DMA */
 195         clear_dma_irqstat(info->dma_ch);
 196         disable_dma(info->dma_ch);
 197
 198         SSYNC();
 199         return 0;
 200 }
 201
 202 static int ppi_set_params(struct ppi_if *ppi, struct ppi_params *params)
 203 {
 204         const struct ppi_info *info = ppi->info;
 205         int dma32 = 0;
 206         int dma_config, bytes_per_line;
 207         int hcount, hdelay, samples_per_line;
 208
 209 #ifdef CONFIG_PINCTRL
 210         static const char * const pin_state[] = {"8bit", "16bit", "24bit"};
 211         struct pinctrl *pctrl;
 212         struct pinctrl_state *pstate;
 213
 214         if (params->dlen > 24 || params->dlen <= 0)
 215                 return -EINVAL;
 216         pctrl = devm_pinctrl_get(ppi->dev);
 217         if (IS_ERR(pctrl))
 218                 return PTR_ERR(pctrl);
 219         pstate = pinctrl_lookup_state(pctrl,
 220                                       pin_state[(params->dlen + 7) / 8 - 1]);
 221         if (pinctrl_select_state(pctrl, pstate))
 222                 return -EINVAL;
 223 #endif
 224
 225         bytes_per_line = params->width * params->bpp / 8;
 226         /* convert parameters unit from pixels to samples */
 227         hcount = params->width * params->bpp / params->dlen;
 228         hdelay = params->hdelay * params->bpp / params->dlen;
 229         samples_per_line = params->line * params->bpp / params->dlen;
 230         if (params->int_mask == 0xFFFFFFFF)
 231                 ppi->err_int = false;
 232         else
 233                 ppi->err_int = true;
 234
 235         dma_config = (DMA_FLOW_STOP | RESTART | DMA2D | DI_EN_Y);
 236         ppi->ppi_control = params->ppi_control & ~PORT_EN;
 237         if (!(ppi->ppi_control & PORT_DIR))
 238                 dma_config |= WNR;
 239         switch (info->type) {
 240         case PPI_TYPE_PPI:
 241         {
 242                 struct bfin_ppi_regs *reg = info->base;
 243
 244                 if (params->ppi_control & DMA32)
 245                         dma32 = 1;
 246
 247                 bfin_write16(&reg->control, ppi->ppi_control);
 248                 bfin_write16(&reg->count, samples_per_line - 1);
 249                 bfin_write16(&reg->frame, params->frame);
 250                 break;
 251         }
 252         case PPI_TYPE_EPPI:
 253         {
 254                 struct bfin_eppi_regs *reg = info->base;
 255
 256                 if ((params->ppi_control & PACK_EN)
 257                         || (params->ppi_control & 0x38000) > DLEN_16)
 258                         dma32 = 1;
 259
 260                 bfin_write32(&reg->control, ppi->ppi_control);
 261                 bfin_write16(&reg->line, samples_per_line);
 262                 bfin_write16(&reg->frame, params->frame);
 263                 bfin_write16(&reg->hdelay, hdelay);
 264                 bfin_write16(&reg->vdelay, params->vdelay);
 265                 bfin_write16(&reg->hcount, hcount);
 266                 bfin_write16(&reg->vcount, params->height);
 267                 break;
 268         }
 269         case PPI_TYPE_EPPI3:
 270         {
 271                 struct bfin_eppi3_regs *reg = info->base;
 272
 273                 if ((params->ppi_control & PACK_EN)
 274                         || (params->ppi_control & 0x70000) > DLEN_16)
 275                         dma32 = 1;
 276
 277                 bfin_write32(&reg->ctl, ppi->ppi_control);
 278                 bfin_write32(&reg->line, samples_per_line);
 279                 bfin_write32(&reg->frame, params->frame);
 280                 bfin_write32(&reg->hdly, hdelay);
 281                 bfin_write32(&reg->vdly, params->vdelay);
 282                 bfin_write32(&reg->hcnt, hcount);
 283                 bfin_write32(&reg->vcnt, params->height);
 284                 if (params->int_mask)
 285                         bfin_write32(&reg->imsk, params->int_mask & 0xFF);
 286                 if (ppi->ppi_control & PORT_DIR) {
 287                         u32 hsync_width, vsync_width, vsync_period;
 288
 289                         hsync_width = params->hsync
 290                                         * params->bpp / params->dlen;
 291                         vsync_width = params->vsync * samples_per_line;
 292                         vsync_period = samples_per_line * params->frame;
 293                         bfin_write32(&reg->fs1_wlhb, hsync_width);
 294                         bfin_write32(&reg->fs1_paspl, samples_per_line);
 295                         bfin_write32(&reg->fs2_wlvb, vsync_width);
 296                         bfin_write32(&reg->fs2_palpf, vsync_period);
 297                 }
 298                 break;
 299         }
 300         default:
 301                 return -EINVAL;
 302         }
 303
 304         if (dma32) {
 305                 dma_config |= WDSIZE_32 | PSIZE_32;
 306                 set_dma_x_count(info->dma_ch, bytes_per_line >> 2);
 307                 set_dma_x_modify(info->dma_ch, 4);
 308                 set_dma_y_modify(info->dma_ch, 4);
 309         } else {
 310                 dma_config |= WDSIZE_16 | PSIZE_16;
 311                 set_dma_x_count(info->dma_ch, bytes_per_line >> 1);
 312                 set_dma_x_modify(info->dma_ch, 2);
 313                 set_dma_y_modify(info->dma_ch, 2);
 314         }
 315         set_dma_y_count(info->dma_ch, params->height);
 316         set_dma_config(info->dma_ch, dma_config);
 317
 318         SSYNC();
 319         return 0;
 320 }
 321
 322 static void ppi_update_addr(struct ppi_if *ppi, unsigned long addr)
 323 {
 324         set_dma_start_addr(ppi->info->dma_ch, addr);
 325 }
 326
 327 struct ppi_if *ppi_create_instance(struct platform_device *pdev,
 328                         const struct ppi_info *info)
 329 {
 330         struct ppi_if *ppi;
 331
 332         if (!info || !info->pin_req)
 333                 return NULL;
 334
 335 #ifndef CONFIG_PINCTRL
 336         if (peripheral_request_list(info->pin_req, KBUILD_MODNAME)) {
 337                 dev_err(&pdev->dev, "request peripheral failed\n");
 338                 return NULL;
 339         }
 340 #endif
 341
 342         ppi = kzalloc(sizeof(*ppi), GFP_KERNEL);
 343         if (!ppi) {
 344                 peripheral_free_list(info->pin_req);
 345                 dev_err(&pdev->dev, "unable to allocate memory for ppi handle\n");
 346                 return NULL;
 347         }
 348         ppi->ops = &ppi_ops;
 349         ppi->info = info;
 350         ppi->dev = &pdev->dev;
 351
 352         pr_info("ppi probe success\n");
 353         return ppi;
 354 }
 355 EXPORT_SYMBOL(ppi_create_instance);
 356
 357 void ppi_delete_instance(struct ppi_if *ppi)
 358 {
 359         peripheral_free_list(ppi->info->pin_req);
 360         kfree(ppi);
 361 }
 362 EXPORT_SYMBOL(ppi_delete_instance);
 363
 364 MODULE_DESCRIPTION("Analog Devices PPI driver");
 365 MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
 366 MODULE_LICENSE("GPL v2");