kernel/drivers/media/i2c/ths8200.c

   1 /*
   2  * ths8200 - Texas Instruments THS8200 video encoder driver
   3  *
   4  * Copyright 2013 Cisco Systems, Inc. and/or its affiliates.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation version 2.
  13  *
  14  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  15  * kind, whether express or implied; without even the implied warranty
  16  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <linux/i2c.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/v4l2-dv-timings.h>
  24
  25 #include <media/v4l2-dv-timings.h>
  26 #include <media/v4l2-async.h>
  27 #include <media/v4l2-device.h>
  28
  29 #include "ths8200_regs.h"
  30
  31 static int debug;
  32 module_param(debug, int, 0644);
  33 MODULE_PARM_DESC(debug, "debug level (0-2)");
  34
  35 MODULE_DESCRIPTION("Texas Instruments THS8200 video encoder driver");
  36 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  37 MODULE_AUTHOR("Martin Bugge <martin.bugge@cisco.com>");
  38 MODULE_LICENSE("GPL v2");
  39
  40 struct ths8200_state {
  41         struct v4l2_subdev sd;
  42         uint8_t chip_version;
  43         /* Is the ths8200 powered on? */
  44         bool power_on;
  45         struct v4l2_dv_timings dv_timings;
  46 };
  47
  48 static const struct v4l2_dv_timings_cap ths8200_timings_cap = {
  49         .type = V4L2_DV_BT_656_1120,
  50         /* keep this initialization for compatibility with GCC < 4.4.6 */
  51         .reserved = { 0 },
  52         V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1080, 25000000, 148500000,
  53                 V4L2_DV_BT_STD_CEA861, V4L2_DV_BT_CAP_PROGRESSIVE)
  54 };
  55
  56 static inline struct ths8200_state *to_state(struct v4l2_subdev *sd)
  57 {
  58         return container_of(sd, struct ths8200_state, sd);
  59 }
  60
  61 static inline unsigned htotal(const struct v4l2_bt_timings *t)
  62 {
  63         return V4L2_DV_BT_FRAME_WIDTH(t);
  64 }
  65
  66 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
  67 {
  68         return V4L2_DV_BT_FRAME_HEIGHT(t);
  69 }
  70
  71 static int ths8200_read(struct v4l2_subdev *sd, u8 reg)
  72 {
  73         struct i2c_client *client = v4l2_get_subdevdata(sd);
  74
  75         return i2c_smbus_read_byte_data(client, reg);
  76 }
  77
  78 static int ths8200_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  79 {
  80         struct i2c_client *client = v4l2_get_subdevdata(sd);
  81         int ret;
  82         int i;
  83
  84         for (i = 0; i < 3; i++) {
  85                 ret = i2c_smbus_write_byte_data(client, reg, val);
  86                 if (ret == 0)
  87                         return 0;
  88         }
  89         v4l2_err(sd, "I2C Write Problem\n");
  90         return ret;
  91 }
  92
  93 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
  94  * and then the value-mask (to be OR-ed).
  95  */
  96 static inline void
  97 ths8200_write_and_or(struct v4l2_subdev *sd, u8 reg,
  98                      uint8_t clr_mask, uint8_t val_mask)
  99 {
 100         ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask);
 101 }
 102
 103 #ifdef CONFIG_VIDEO_ADV_DEBUG
 104
 105 static int ths8200_g_register(struct v4l2_subdev *sd,
 106                               struct v4l2_dbg_register *reg)
 107 {
 108         reg->val = ths8200_read(sd, reg->reg & 0xff);
 109         reg->size = 1;
 110
 111         return 0;
 112 }
 113
 114 static int ths8200_s_register(struct v4l2_subdev *sd,
 115                               const struct v4l2_dbg_register *reg)
 116 {
 117         ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff);
 118
 119         return 0;
 120 }
 121 #endif
 122
 123 static int ths8200_log_status(struct v4l2_subdev *sd)
 124 {
 125         struct ths8200_state *state = to_state(sd);
 126         uint8_t reg_03 = ths8200_read(sd, THS8200_CHIP_CTL);
 127
 128         v4l2_info(sd, "----- Chip status -----\n");
 129         v4l2_info(sd, "version: %u\n", state->chip_version);
 130         v4l2_info(sd, "power: %s\n", (reg_03 & 0x0c) ? "off" : "on");
 131         v4l2_info(sd, "reset: %s\n", (reg_03 & 0x01) ? "off" : "on");
 132         v4l2_info(sd, "test pattern: %s\n",
 133                   (reg_03 & 0x20) ? "enabled" : "disabled");
 134         v4l2_info(sd, "format: %ux%u\n",
 135                   ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_MSB) * 256 +
 136                   ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_LSB),
 137                   (ths8200_read(sd, THS8200_DTG2_LINE_CNT_MSB) & 0x07) * 256 +
 138                   ths8200_read(sd, THS8200_DTG2_LINE_CNT_LSB));
 139         v4l2_print_dv_timings(sd->name, "Configured format:",
 140                               &state->dv_timings, true);
 141         return 0;
 142 }
 143
 144 /* Power up/down ths8200 */
 145 static int ths8200_s_power(struct v4l2_subdev *sd, int on)
 146 {
 147         struct ths8200_state *state = to_state(sd);
 148
 149         v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
 150
 151         state->power_on = on;
 152
 153         /* Power up/down - leave in reset state until input video is present */
 154         ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xf2, (on ? 0x00 : 0x0c));
 155
 156         return 0;
 157 }
 158
 159 static const struct v4l2_subdev_core_ops ths8200_core_ops = {
 160         .log_status = ths8200_log_status,
 161         .s_power = ths8200_s_power,
 162 #ifdef CONFIG_VIDEO_ADV_DEBUG
 163         .g_register = ths8200_g_register,
 164         .s_register = ths8200_s_register,
 165 #endif
 166 };
 167
 168 /* -----------------------------------------------------------------------------
 169  * V4L2 subdev video operations
 170  */
 171
 172 static int ths8200_s_stream(struct v4l2_subdev *sd, int enable)
 173 {
 174         struct ths8200_state *state = to_state(sd);
 175
 176         if (enable && !state->power_on)
 177                 ths8200_s_power(sd, true);
 178
 179         ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xfe,
 180                              (enable ? 0x01 : 0x00));
 181
 182         v4l2_dbg(1, debug, sd, "%s: %sable\n",
 183                  __func__, (enable ? "en" : "dis"));
 184
 185         return 0;
 186 }
 187
 188 static void ths8200_core_init(struct v4l2_subdev *sd)
 189 {
 190         /* setup clocks */
 191         ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0x3f, 0xc0);
 192
 193         /**** Data path control (DATA) ****/
 194         /* Set FSADJ 700 mV,
 195          * bypass 422-444 interpolation,
 196          * input format 30 bit RGB444
 197          */
 198         ths8200_write(sd, THS8200_DATA_CNTL, 0x70);
 199
 200         /* DTG Mode (Video blocked during blanking
 201          * VESA slave
 202          */
 203         ths8200_write(sd, THS8200_DTG1_MODE, 0x87);
 204
 205         /**** Display Timing Generator Control, Part 1 (DTG1). ****/
 206
 207         /* Disable embedded syncs on the output by setting
 208          * the amplitude to zero for all channels.
 209          */
 210         ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x00);
 211         ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x00);
 212 }
 213
 214 static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt)
 215 {
 216         uint8_t polarity = 0;
 217         uint16_t line_start_active_video = (bt->vsync + bt->vbackporch);
 218         uint16_t line_start_front_porch  = (vtotal(bt) - bt->vfrontporch);
 219
 220         /*** System ****/
 221         /* Set chip in reset while it is configured */
 222         ths8200_s_stream(sd, false);
 223
 224         /* configure video output timings */
 225         ths8200_write(sd, THS8200_DTG1_SPEC_A, bt->hsync);
 226         ths8200_write(sd, THS8200_DTG1_SPEC_B, bt->hfrontporch);
 227
 228         /* Zero for progressive scan formats.*/
 229         if (!bt->interlaced)
 230                 ths8200_write(sd, THS8200_DTG1_SPEC_C, 0x00);
 231
 232         /* Distance from leading edge of h sync to start of active video.
 233          * MSB in 0x2b
 234          */
 235         ths8200_write(sd, THS8200_DTG1_SPEC_D_LSB,
 236                       (bt->hbackporch + bt->hsync) & 0xff);
 237         /* Zero for SDTV-mode. MSB in 0x2b */
 238         ths8200_write(sd, THS8200_DTG1_SPEC_E_LSB, 0x00);
 239         /*
 240          * MSB for dtg1_spec(d/e/h). See comment for
 241          * corresponding LSB registers.
 242          */
 243         ths8200_write(sd, THS8200_DTG1_SPEC_DEH_MSB,
 244                       ((bt->hbackporch + bt->hsync) & 0x100) >> 1);
 245
 246         /* h front porch */
 247         ths8200_write(sd, THS8200_DTG1_SPEC_K_LSB, (bt->hfrontporch) & 0xff);
 248         ths8200_write(sd, THS8200_DTG1_SPEC_K_MSB,
 249                       ((bt->hfrontporch) & 0x700) >> 8);
 250
 251         /* Half the line length. Used to calculate SDTV line types. */
 252         ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff);
 253         ths8200_write(sd, THS8200_DTG1_SPEC_G_MSB,
 254                       ((htotal(bt)/2) >> 8) & 0x0f);
 255
 256         /* Total pixels per line (ex. 720p: 1650) */
 257         ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8);
 258         ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff);
 259
 260         /* Frame height and field height */
 261         /* Field height should be programmed higher than frame_size for
 262          * progressive scan formats
 263          */
 264         ths8200_write(sd, THS8200_DTG1_FRAME_FIELD_SZ_MSB,
 265                       ((vtotal(bt) >> 4) & 0xf0) + 0x7);
 266         ths8200_write(sd, THS8200_DTG1_FRAME_SZ_LSB, vtotal(bt) & 0xff);
 267
 268         /* Should be programmed higher than frame_size
 269          * for progressive formats
 270          */
 271         if (!bt->interlaced)
 272                 ths8200_write(sd, THS8200_DTG1_FIELD_SZ_LSB, 0xff);
 273
 274         /**** Display Timing Generator Control, Part 2 (DTG2). ****/
 275         /* Set breakpoint line numbers and types
 276          * THS8200 generates line types with different properties. A line type
 277          * that sets all the RGB-outputs to zero is used in the blanking areas,
 278          * while a line type that enable the RGB-outputs is used in active video
 279          * area. The line numbers for start of active video, start of front
 280          * porch and after the last line in the frame must be set with the
 281          * corresponding line types.
 282          *
 283          * Line types:
 284          * 0x9 - Full normal sync pulse: Blocks data when dtg1_pass is off.
 285          *       Used in blanking area.
 286          * 0x0 - Active video: Video data is always passed. Used in active
 287          *       video area.
 288          */
 289         ths8200_write_and_or(sd, THS8200_DTG2_BP1_2_MSB, 0x88,
 290                              ((line_start_active_video >> 4) & 0x70) +
 291                              ((line_start_front_porch >> 8) & 0x07));
 292         ths8200_write(sd, THS8200_DTG2_BP3_4_MSB, ((vtotal(bt)) >> 4) & 0x70);
 293         ths8200_write(sd, THS8200_DTG2_BP1_LSB, line_start_active_video & 0xff);
 294         ths8200_write(sd, THS8200_DTG2_BP2_LSB, line_start_front_porch & 0xff);
 295         ths8200_write(sd, THS8200_DTG2_BP3_LSB, (vtotal(bt)) & 0xff);
 296
 297         /* line types */
 298         ths8200_write(sd, THS8200_DTG2_LINETYPE1, 0x90);
 299         ths8200_write(sd, THS8200_DTG2_LINETYPE2, 0x90);
 300
 301         /* h sync width transmitted */
 302         ths8200_write(sd, THS8200_DTG2_HLENGTH_LSB, bt->hsync & 0xff);
 303         ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0x3f,
 304                              (bt->hsync >> 2) & 0xc0);
 305
 306         /* The pixel value h sync is asserted on */
 307         ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0xe0,
 308                              (htotal(bt) >> 8) & 0x1f);
 309         ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt));
 310
 311         /* v sync width transmitted (must add 1 to get correct output) */
 312         ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync + 1) & 0xff);
 313         ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f,
 314                              ((bt->vsync + 1) >> 2) & 0xc0);
 315
 316         /* The pixel value v sync is asserted on (must add 1 to get correct output) */
 317         ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8,
 318                              ((vtotal(bt) + 1) >> 8) & 0x7);
 319         ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt) + 1);
 320
 321         /* For progressive video vlength2 must be set to all 0 and vdly2 must
 322          * be set to all 1.
 323          */
 324         ths8200_write(sd, THS8200_DTG2_VLENGTH2_LSB, 0x00);
 325         ths8200_write(sd, THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB, 0x07);
 326         ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff);
 327
 328         /* Internal delay factors to synchronize the sync pulses and the data */
 329         /* Experimental values delays (hor 0, ver 0) */
 330         ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, 0);
 331         ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, 0);
 332         ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0);
 333         ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 0);
 334
 335         /* Polarity of received and transmitted sync signals */
 336         if (bt->polarities & V4L2_DV_HSYNC_POS_POL) {
 337                 polarity |= 0x01; /* HS_IN */
 338                 polarity |= 0x08; /* HS_OUT */
 339         }
 340         if (bt->polarities & V4L2_DV_VSYNC_POS_POL) {
 341                 polarity |= 0x02; /* VS_IN */
 342                 polarity |= 0x10; /* VS_OUT */
 343         }
 344
 345         /* RGB mode, no embedded timings */
 346         /* Timing of video input bus is derived from HS, VS, and FID dedicated
 347          * inputs
 348          */
 349         ths8200_write(sd, THS8200_DTG2_CNTL, 0x44 | polarity);
 350
 351         /* leave reset */
 352         ths8200_s_stream(sd, true);
 353
 354         v4l2_dbg(1, debug, sd, "%s: frame %dx%d, polarity %d\n"
 355                  "horizontal: front porch %d, back porch %d, sync %d\n"
 356                  "vertical: sync %d\n", __func__, htotal(bt), vtotal(bt),
 357                  polarity, bt->hfrontporch, bt->hbackporch,
 358                  bt->hsync, bt->vsync);
 359 }
 360
 361 static int ths8200_s_dv_timings(struct v4l2_subdev *sd,
 362                                 struct v4l2_dv_timings *timings)
 363 {
 364         struct ths8200_state *state = to_state(sd);
 365
 366         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 367
 368         if (!v4l2_valid_dv_timings(timings, &ths8200_timings_cap,
 369                                 NULL, NULL))
 370                 return -EINVAL;
 371
 372         if (!v4l2_find_dv_timings_cap(timings, &ths8200_timings_cap, 10,
 373                                 NULL, NULL)) {
 374                 v4l2_dbg(1, debug, sd, "Unsupported format\n");
 375                 return -EINVAL;
 376         }
 377
 378         timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
 379
 380         /* save timings */
 381         state->dv_timings = *timings;
 382
 383         ths8200_setup(sd, &timings->bt);
 384
 385         return 0;
 386 }
 387
 388 static int ths8200_g_dv_timings(struct v4l2_subdev *sd,
 389                                 struct v4l2_dv_timings *timings)
 390 {
 391         struct ths8200_state *state = to_state(sd);
 392
 393         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 394
 395         *timings = state->dv_timings;
 396
 397         return 0;
 398 }
 399
 400 static int ths8200_enum_dv_timings(struct v4l2_subdev *sd,
 401                                    struct v4l2_enum_dv_timings *timings)
 402 {
 403         if (timings->pad != 0)
 404                 return -EINVAL;
 405
 406         return v4l2_enum_dv_timings_cap(timings, &ths8200_timings_cap,
 407                         NULL, NULL);
 408 }
 409
 410 static int ths8200_dv_timings_cap(struct v4l2_subdev *sd,
 411                                   struct v4l2_dv_timings_cap *cap)
 412 {
 413         if (cap->pad != 0)
 414                 return -EINVAL;
 415
 416         *cap = ths8200_timings_cap;
 417         return 0;
 418 }
 419
 420 /* Specific video subsystem operation handlers */
 421 static const struct v4l2_subdev_video_ops ths8200_video_ops = {
 422         .s_stream = ths8200_s_stream,
 423         .s_dv_timings = ths8200_s_dv_timings,
 424         .g_dv_timings = ths8200_g_dv_timings,
 425 };
 426
 427 static const struct v4l2_subdev_pad_ops ths8200_pad_ops = {
 428         .enum_dv_timings = ths8200_enum_dv_timings,
 429         .dv_timings_cap = ths8200_dv_timings_cap,
 430 };
 431
 432 /* V4L2 top level operation handlers */
 433 static const struct v4l2_subdev_ops ths8200_ops = {
 434         .core  = &ths8200_core_ops,
 435         .video = &ths8200_video_ops,
 436         .pad = &ths8200_pad_ops,
 437 };
 438
 439 static int ths8200_probe(struct i2c_client *client,
 440                          const struct i2c_device_id *id)
 441 {
 442         struct ths8200_state *state;
 443         struct v4l2_subdev *sd;
 444         int error;
 445
 446         /* Check if the adapter supports the needed features */
 447         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
 448                 return -EIO;
 449
 450         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
 451         if (!state)
 452                 return -ENOMEM;
 453
 454         sd = &state->sd;
 455         v4l2_i2c_subdev_init(sd, client, &ths8200_ops);
 456
 457         state->chip_version = ths8200_read(sd, THS8200_VERSION);
 458         v4l2_dbg(1, debug, sd, "chip version 0x%x\n", state->chip_version);
 459
 460         ths8200_core_init(sd);
 461
 462         error = v4l2_async_register_subdev(&state->sd);
 463         if (error)
 464                 return error;
 465
 466         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
 467                   client->addr << 1, client->adapter->name);
 468
 469         return 0;
 470 }
 471
 472 static int ths8200_remove(struct i2c_client *client)
 473 {
 474         struct v4l2_subdev *sd = i2c_get_clientdata(client);
 475         struct ths8200_state *decoder = to_state(sd);
 476
 477         v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
 478                  client->addr << 1, client->adapter->name);
 479
 480         ths8200_s_power(sd, false);
 481         v4l2_async_unregister_subdev(&decoder->sd);
 482
 483         return 0;
 484 }
 485
 486 static struct i2c_device_id ths8200_id[] = {
 487         { "ths8200", 0 },
 488         {},
 489 };
 490 MODULE_DEVICE_TABLE(i2c, ths8200_id);
 491
 492 #if IS_ENABLED(CONFIG_OF)
 493 static const struct of_device_id ths8200_of_match[] = {
 494         { .compatible = "ti,ths8200", },
 495         { /* sentinel */ },
 496 };
 497 MODULE_DEVICE_TABLE(of, ths8200_of_match);
 498 #endif
 499
 500 static struct i2c_driver ths8200_driver = {
 501         .driver = {
 502                 .owner = THIS_MODULE,
 503                 .name = "ths8200",
 504                 .of_match_table = of_match_ptr(ths8200_of_match),
 505         },
 506         .probe = ths8200_probe,
 507         .remove = ths8200_remove,
 508         .id_table = ths8200_id,
 509 };
 510
 511 module_i2c_driver(ths8200_driver);