kernel/drivers/media/i2c/tc358743.c

   1 /*
   2  * tc358743 - Toshiba HDMI to CSI-2 bridge
   3  *
   4  * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
   5  * reserved.
   6  *
   7  * This program is free software; you may redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  12  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  13  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  14  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  15  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  16  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  17  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  18  * SOFTWARE.
  19  *
  20  */
  21
  22 /*
  23  * References (c = chapter, p = page):
  24  * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
  25  * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/slab.h>
  31 #include <linux/i2c.h>
  32 #include <linux/clk.h>
  33 #include <linux/delay.h>
  34 #include <linux/gpio/consumer.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/videodev2.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/v4l2-dv-timings.h>
  39 #include <linux/hdmi.h>
  40 #include <media/v4l2-dv-timings.h>
  41 #include <media/v4l2-device.h>
  42 #include <media/v4l2-ctrls.h>
  43 #include <media/v4l2-event.h>
  44 #include <media/v4l2-of.h>
  45 #include <media/tc358743.h>
  46
  47 #include "tc358743_regs.h"
  48
  49 static int debug;
  50 module_param(debug, int, 0644);
  51 MODULE_PARM_DESC(debug, "debug level (0-3)");
  52
  53 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
  54 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
  55 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
  56 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
  57 MODULE_LICENSE("GPL");
  58
  59 #define EDID_NUM_BLOCKS_MAX 8
  60 #define EDID_BLOCK_SIZE 128
  61
  62 /* Max transfer size done by I2C transfer functions */
  63 #define MAX_XFER_SIZE  (EDID_NUM_BLOCKS_MAX * EDID_BLOCK_SIZE + 2)
  64
  65 static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
  66         .type = V4L2_DV_BT_656_1120,
  67         /* keep this initialization for compatibility with GCC < 4.4.6 */
  68         .reserved = { 0 },
  69         /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
  70         V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000,
  71                         V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
  72                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
  73                         V4L2_DV_BT_CAP_PROGRESSIVE |
  74                         V4L2_DV_BT_CAP_REDUCED_BLANKING |
  75                         V4L2_DV_BT_CAP_CUSTOM)
  76 };
  77
  78 struct tc358743_state {
  79         struct tc358743_platform_data pdata;
  80         struct v4l2_of_bus_mipi_csi2 bus;
  81         struct v4l2_subdev sd;
  82         struct media_pad pad;
  83         struct v4l2_ctrl_handler hdl;
  84         struct i2c_client *i2c_client;
  85         /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */
  86         struct mutex confctl_mutex;
  87
  88         /* controls */
  89         struct v4l2_ctrl *detect_tx_5v_ctrl;
  90         struct v4l2_ctrl *audio_sampling_rate_ctrl;
  91         struct v4l2_ctrl *audio_present_ctrl;
  92
  93         /* work queues */
  94         struct workqueue_struct *work_queues;
  95         struct delayed_work delayed_work_enable_hotplug;
  96
  97         /* edid  */
  98         u8 edid_blocks_written;
  99
 100         /* used by i2c_wr() */
 101         u8 wr_data[MAX_XFER_SIZE];
 102
 103         struct v4l2_dv_timings timings;
 104         u32 mbus_fmt_code;
 105
 106         struct gpio_desc *reset_gpio;
 107 };
 108
 109 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
 110                 bool cable_connected);
 111 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
 112
 113 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
 114 {
 115         return container_of(sd, struct tc358743_state, sd);
 116 }
 117
 118 /* --------------- I2C --------------- */
 119
 120 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
 121 {
 122         struct tc358743_state *state = to_state(sd);
 123         struct i2c_client *client = state->i2c_client;
 124         int err;
 125         u8 buf[2] = { reg >> 8, reg & 0xff };
 126         struct i2c_msg msgs[] = {
 127                 {
 128                         .addr = client->addr,
 129                         .flags = 0,
 130                         .len = 2,
 131                         .buf = buf,
 132                 },
 133                 {
 134                         .addr = client->addr,
 135                         .flags = I2C_M_RD,
 136                         .len = n,
 137                         .buf = values,
 138                 },
 139         };
 140
 141         err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
 142         if (err != ARRAY_SIZE(msgs)) {
 143                 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
 144                                 __func__, reg, client->addr);
 145         }
 146 }
 147
 148 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
 149 {
 150         struct tc358743_state *state = to_state(sd);
 151         struct i2c_client *client = state->i2c_client;
 152         u8 *data = state->wr_data;
 153         int err, i;
 154         struct i2c_msg msg;
 155
 156         if ((2 + n) > sizeof(state->wr_data))
 157                 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
 158                           reg, 2 + n);
 159
 160         msg.addr = client->addr;
 161         msg.buf = data;
 162         msg.len = 2 + n;
 163         msg.flags = 0;
 164
 165         data[0] = reg >> 8;
 166         data[1] = reg & 0xff;
 167
 168         for (i = 0; i < n; i++)
 169                 data[2 + i] = values[i];
 170
 171         err = i2c_transfer(client->adapter, &msg, 1);
 172         if (err != 1) {
 173                 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
 174                                 __func__, reg, client->addr);
 175                 return;
 176         }
 177
 178         if (debug < 3)
 179                 return;
 180
 181         switch (n) {
 182         case 1:
 183                 v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
 184                                 reg, data[2]);
 185                 break;
 186         case 2:
 187                 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
 188                                 reg, data[3], data[2]);
 189                 break;
 190         case 4:
 191                 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
 192                                 reg, data[5], data[4], data[3], data[2]);
 193                 break;
 194         default:
 195                 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
 196                                 n, reg);
 197         }
 198 }
 199
 200 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
 201 {
 202         u8 val;
 203
 204         i2c_rd(sd, reg, &val, 1);
 205
 206         return val;
 207 }
 208
 209 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
 210 {
 211         i2c_wr(sd, reg, &val, 1);
 212 }
 213
 214 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
 215                 u8 mask, u8 val)
 216 {
 217         i2c_wr8(sd, reg, (i2c_rd8(sd, reg) & mask) | val);
 218 }
 219
 220 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
 221 {
 222         u16 val;
 223
 224         i2c_rd(sd, reg, (u8 *)&val, 2);
 225
 226         return val;
 227 }
 228
 229 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
 230 {
 231         i2c_wr(sd, reg, (u8 *)&val, 2);
 232 }
 233
 234 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
 235 {
 236         i2c_wr16(sd, reg, (i2c_rd16(sd, reg) & mask) | val);
 237 }
 238
 239 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
 240 {
 241         u32 val;
 242
 243         i2c_rd(sd, reg, (u8 *)&val, 4);
 244
 245         return val;
 246 }
 247
 248 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
 249 {
 250         i2c_wr(sd, reg, (u8 *)&val, 4);
 251 }
 252
 253 /* --------------- STATUS --------------- */
 254
 255 static inline bool is_hdmi(struct v4l2_subdev *sd)
 256 {
 257         return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
 258 }
 259
 260 static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
 261 {
 262         return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
 263 }
 264
 265 static inline bool no_signal(struct v4l2_subdev *sd)
 266 {
 267         return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
 268 }
 269
 270 static inline bool no_sync(struct v4l2_subdev *sd)
 271 {
 272         return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
 273 }
 274
 275 static inline bool audio_present(struct v4l2_subdev *sd)
 276 {
 277         return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
 278 }
 279
 280 static int get_audio_sampling_rate(struct v4l2_subdev *sd)
 281 {
 282         static const int code_to_rate[] = {
 283                 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
 284                 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
 285         };
 286
 287         /* Register FS_SET is not cleared when the cable is disconnected */
 288         if (no_signal(sd))
 289                 return 0;
 290
 291         return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
 292 }
 293
 294 static unsigned tc358743_num_csi_lanes_in_use(struct v4l2_subdev *sd)
 295 {
 296         return ((i2c_rd32(sd, CSI_CONTROL) & MASK_NOL) >> 1) + 1;
 297 }
 298
 299 /* --------------- TIMINGS --------------- */
 300
 301 static inline unsigned fps(const struct v4l2_bt_timings *t)
 302 {
 303         if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
 304                 return 0;
 305
 306         return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
 307                         V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
 308 }
 309
 310 static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
 311                                      struct v4l2_dv_timings *timings)
 312 {
 313         struct v4l2_bt_timings *bt = &timings->bt;
 314         unsigned width, height, frame_width, frame_height, frame_interval, fps;
 315
 316         memset(timings, 0, sizeof(struct v4l2_dv_timings));
 317
 318         if (no_signal(sd)) {
 319                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
 320                 return -ENOLINK;
 321         }
 322         if (no_sync(sd)) {
 323                 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
 324                 return -ENOLCK;
 325         }
 326
 327         timings->type = V4L2_DV_BT_656_1120;
 328         bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
 329                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
 330
 331         width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
 332                 i2c_rd8(sd, DE_WIDTH_H_LO);
 333         height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
 334                 i2c_rd8(sd, DE_WIDTH_V_LO);
 335         frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
 336                 i2c_rd8(sd, H_SIZE_LO);
 337         frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
 338                 i2c_rd8(sd, V_SIZE_LO)) / 2;
 339         /* frame interval in milliseconds * 10
 340          * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
 341         frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
 342                 i2c_rd8(sd, FV_CNT_LO);
 343         fps = (frame_interval > 0) ?
 344                 DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
 345
 346         bt->width = width;
 347         bt->height = height;
 348         bt->vsync = frame_height - height;
 349         bt->hsync = frame_width - width;
 350         bt->pixelclock = frame_width * frame_height * fps;
 351         if (bt->interlaced == V4L2_DV_INTERLACED) {
 352                 bt->height *= 2;
 353                 bt->il_vsync = bt->vsync + 1;
 354                 bt->pixelclock /= 2;
 355         }
 356
 357         return 0;
 358 }
 359
 360 /* --------------- HOTPLUG / HDCP / EDID --------------- */
 361
 362 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
 363 {
 364         struct delayed_work *dwork = to_delayed_work(work);
 365         struct tc358743_state *state = container_of(dwork,
 366                         struct tc358743_state, delayed_work_enable_hotplug);
 367         struct v4l2_subdev *sd = &state->sd;
 368
 369         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 370
 371         i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
 372 }
 373
 374 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
 375 {
 376         v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
 377                                 "enable" : "disable");
 378
 379         i2c_wr8_and_or(sd, HDCP_REG1,
 380                         ~(MASK_AUTH_UNAUTH_SEL | MASK_AUTH_UNAUTH),
 381                         MASK_AUTH_UNAUTH_SEL_16_FRAMES | MASK_AUTH_UNAUTH_AUTO);
 382
 383         i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
 384                         SET_AUTO_P3_RESET_FRAMES(0x0f));
 385
 386         /* HDCP is disabled by configuring the receiver as HDCP repeater. The
 387          * repeater mode require software support to work, so HDCP
 388          * authentication will fail.
 389          */
 390         i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, enable ? KEY_RD_CMD : 0);
 391         i2c_wr8_and_or(sd, HDCP_MODE, ~(MASK_AUTO_CLR | MASK_MODE_RST_TN),
 392                         enable ?  (MASK_AUTO_CLR | MASK_MODE_RST_TN) : 0);
 393
 394         /* Apple MacBook Pro gen.8 has a bug that makes it freeze every fifth
 395          * second when HDCP is disabled, but the MAX_EXCED bit is handled
 396          * correctly and HDCP is disabled on the HDMI output.
 397          */
 398         i2c_wr8_and_or(sd, BSTATUS1, ~MASK_MAX_EXCED,
 399                         enable ? 0 : MASK_MAX_EXCED);
 400         i2c_wr8_and_or(sd, BCAPS, ~(MASK_REPEATER | MASK_READY),
 401                         enable ? 0 : MASK_REPEATER | MASK_READY);
 402 }
 403
 404 static void tc358743_disable_edid(struct v4l2_subdev *sd)
 405 {
 406         struct tc358743_state *state = to_state(sd);
 407
 408         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 409
 410         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
 411
 412         /* DDC access to EDID is also disabled when hotplug is disabled. See
 413          * register DDC_CTL */
 414         i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
 415 }
 416
 417 static void tc358743_enable_edid(struct v4l2_subdev *sd)
 418 {
 419         struct tc358743_state *state = to_state(sd);
 420
 421         if (state->edid_blocks_written == 0) {
 422                 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
 423                 return;
 424         }
 425
 426         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 427
 428         /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
 429          * hotplug is enabled. See register DDC_CTL */
 430         queue_delayed_work(state->work_queues,
 431                            &state->delayed_work_enable_hotplug, HZ / 10);
 432
 433         tc358743_enable_interrupts(sd, true);
 434         tc358743_s_ctrl_detect_tx_5v(sd);
 435 }
 436
 437 static void tc358743_erase_bksv(struct v4l2_subdev *sd)
 438 {
 439         int i;
 440
 441         for (i = 0; i < 5; i++)
 442                 i2c_wr8(sd, BKSV + i, 0);
 443 }
 444
 445 /* --------------- AVI infoframe --------------- */
 446
 447 static void print_avi_infoframe(struct v4l2_subdev *sd)
 448 {
 449         struct i2c_client *client = v4l2_get_subdevdata(sd);
 450         struct device *dev = &client->dev;
 451         union hdmi_infoframe frame;
 452         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
 453
 454         if (!is_hdmi(sd)) {
 455                 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
 456                 return;
 457         }
 458
 459         i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
 460
 461         if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
 462                 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
 463                 return;
 464         }
 465
 466         hdmi_infoframe_log(KERN_INFO, dev, &frame);
 467 }
 468
 469 /* --------------- CTRLS --------------- */
 470
 471 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
 472 {
 473         struct tc358743_state *state = to_state(sd);
 474
 475         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 476                         tx_5v_power_present(sd));
 477 }
 478
 479 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
 480 {
 481         struct tc358743_state *state = to_state(sd);
 482
 483         return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
 484                         get_audio_sampling_rate(sd));
 485 }
 486
 487 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
 488 {
 489         struct tc358743_state *state = to_state(sd);
 490
 491         return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
 492                         audio_present(sd));
 493 }
 494
 495 static int tc358743_update_controls(struct v4l2_subdev *sd)
 496 {
 497         int ret = 0;
 498
 499         ret |= tc358743_s_ctrl_detect_tx_5v(sd);
 500         ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
 501         ret |= tc358743_s_ctrl_audio_present(sd);
 502
 503         return ret;
 504 }
 505
 506 /* --------------- INIT --------------- */
 507
 508 static void tc358743_reset_phy(struct v4l2_subdev *sd)
 509 {
 510         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 511
 512         i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
 513         i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
 514 }
 515
 516 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
 517 {
 518         u16 sysctl = i2c_rd16(sd, SYSCTL);
 519
 520         i2c_wr16(sd, SYSCTL, sysctl | mask);
 521         i2c_wr16(sd, SYSCTL, sysctl & ~mask);
 522 }
 523
 524 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
 525 {
 526         i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
 527                         enable ? MASK_SLEEP : 0);
 528 }
 529
 530 static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
 531 {
 532         struct tc358743_state *state = to_state(sd);
 533
 534         v4l2_dbg(3, debug, sd, "%s: %sable\n",
 535                         __func__, enable ? "en" : "dis");
 536
 537         if (enable) {
 538                 /* It is critical for CSI receiver to see lane transition
 539                  * LP11->HS. Set to non-continuous mode to enable clock lane
 540                  * LP11 state. */
 541                 i2c_wr32(sd, TXOPTIONCNTRL, 0);
 542                 /* Set to continuous mode to trigger LP11->HS transition */
 543                 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
 544                 /* Unmute video */
 545                 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
 546         } else {
 547                 /* Mute video so that all data lanes go to LSP11 state.
 548                  * No data is output to CSI Tx block. */
 549                 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
 550         }
 551
 552         mutex_lock(&state->confctl_mutex);
 553         i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
 554                         enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
 555         mutex_unlock(&state->confctl_mutex);
 556 }
 557
 558 static void tc358743_set_pll(struct v4l2_subdev *sd)
 559 {
 560         struct tc358743_state *state = to_state(sd);
 561         struct tc358743_platform_data *pdata = &state->pdata;
 562         u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
 563         u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
 564         u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
 565                 SET_PLL_FBD(pdata->pll_fbd);
 566         u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
 567
 568         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 569
 570         /* Only rewrite when needed (new value or disabled), since rewriting
 571          * triggers another format change event. */
 572         if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
 573                 u16 pll_frs;
 574
 575                 if (hsck > 500000000)
 576                         pll_frs = 0x0;
 577                 else if (hsck > 250000000)
 578                         pll_frs = 0x1;
 579                 else if (hsck > 125000000)
 580                         pll_frs = 0x2;
 581                 else
 582                         pll_frs = 0x3;
 583
 584                 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
 585                 tc358743_sleep_mode(sd, true);
 586                 i2c_wr16(sd, PLLCTL0, pllctl0_new);
 587                 i2c_wr16_and_or(sd, PLLCTL1,
 588                                 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
 589                                 (SET_PLL_FRS(pll_frs) | MASK_RESETB |
 590                                  MASK_PLL_EN));
 591                 udelay(10); /* REF_02, Sheet "Source HDMI" */
 592                 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
 593                 tc358743_sleep_mode(sd, false);
 594         }
 595 }
 596
 597 static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
 598 {
 599         struct tc358743_state *state = to_state(sd);
 600         struct tc358743_platform_data *pdata = &state->pdata;
 601         u32 sys_freq;
 602         u32 lockdet_ref;
 603         u16 fh_min;
 604         u16 fh_max;
 605
 606         BUG_ON(!(pdata->refclk_hz == 26000000 ||
 607                  pdata->refclk_hz == 27000000 ||
 608                  pdata->refclk_hz == 42000000));
 609
 610         sys_freq = pdata->refclk_hz / 10000;
 611         i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
 612         i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
 613
 614         i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
 615                         (pdata->refclk_hz == 42000000) ?
 616                         MASK_PHY_SYSCLK_IND : 0x0);
 617
 618         fh_min = pdata->refclk_hz / 100000;
 619         i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
 620         i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
 621
 622         fh_max = (fh_min * 66) / 10;
 623         i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
 624         i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
 625
 626         lockdet_ref = pdata->refclk_hz / 100;
 627         i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
 628         i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
 629         i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
 630
 631         i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
 632                         (pdata->refclk_hz == 27000000) ?
 633                         MASK_NCO_F0_MOD_27MHZ : 0x0);
 634 }
 635
 636 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
 637 {
 638         struct tc358743_state *state = to_state(sd);
 639
 640         switch (state->mbus_fmt_code) {
 641         case MEDIA_BUS_FMT_UYVY8_1X16:
 642                 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
 643                 i2c_wr8_and_or(sd, VOUT_SET2,
 644                                 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
 645                                 MASK_SEL422 | MASK_VOUT_422FIL_100);
 646                 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
 647                                 MASK_VOUT_COLOR_601_YCBCR_LIMITED);
 648                 mutex_lock(&state->confctl_mutex);
 649                 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
 650                                 MASK_YCBCRFMT_422_8_BIT);
 651                 mutex_unlock(&state->confctl_mutex);
 652                 break;
 653         case MEDIA_BUS_FMT_RGB888_1X24:
 654                 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
 655                 i2c_wr8_and_or(sd, VOUT_SET2,
 656                                 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
 657                                 0x00);
 658                 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
 659                                 MASK_VOUT_COLOR_RGB_FULL);
 660                 mutex_lock(&state->confctl_mutex);
 661                 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
 662                 mutex_unlock(&state->confctl_mutex);
 663                 break;
 664         default:
 665                 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
 666                                 __func__, state->mbus_fmt_code);
 667         }
 668 }
 669
 670 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
 671 {
 672         struct tc358743_state *state = to_state(sd);
 673         struct v4l2_bt_timings *bt = &state->timings.bt;
 674         struct tc358743_platform_data *pdata = &state->pdata;
 675         u32 bits_pr_pixel =
 676                 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ?  16 : 24;
 677         u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
 678         u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
 679
 680         return DIV_ROUND_UP(bps, bps_pr_lane);
 681 }
 682
 683 static void tc358743_set_csi(struct v4l2_subdev *sd)
 684 {
 685         struct tc358743_state *state = to_state(sd);
 686         struct tc358743_platform_data *pdata = &state->pdata;
 687         unsigned lanes = tc358743_num_csi_lanes_needed(sd);
 688
 689         v4l2_dbg(3, debug, sd, "%s:\n", __func__);
 690
 691         tc358743_reset(sd, MASK_CTXRST);
 692
 693         if (lanes < 1)
 694                 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
 695         if (lanes < 1)
 696                 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
 697         if (lanes < 2)
 698                 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
 699         if (lanes < 3)
 700                 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
 701         if (lanes < 4)
 702                 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
 703
 704         i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
 705         i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
 706         i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
 707         i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
 708         i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
 709         i2c_wr32(sd, TWAKEUP, pdata->twakeup);
 710         i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
 711         i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
 712         i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
 713
 714         i2c_wr32(sd, HSTXVREGEN,
 715                         ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
 716                         ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
 717                         ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
 718                         ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
 719                         ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
 720
 721         i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
 722                  V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0);
 723         i2c_wr32(sd, STARTCNTRL, MASK_START);
 724         i2c_wr32(sd, CSI_START, MASK_STRT);
 725
 726         i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
 727                         MASK_ADDRESS_CSI_CONTROL |
 728                         MASK_CSI_MODE |
 729                         MASK_TXHSMD |
 730                         ((lanes == 4) ? MASK_NOL_4 :
 731                          (lanes == 3) ? MASK_NOL_3 :
 732                          (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
 733
 734         i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
 735                         MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
 736                         MASK_WCER | MASK_INER);
 737
 738         i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
 739                         MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
 740
 741         i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
 742                         MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
 743 }
 744
 745 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
 746 {
 747         struct tc358743_state *state = to_state(sd);
 748         struct tc358743_platform_data *pdata = &state->pdata;
 749
 750         /* Default settings from REF_02, sheet "Source HDMI"
 751          * and custom settings as platform data */
 752         i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
 753         i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
 754                         SET_FREQ_RANGE_MODE_CYCLES(1));
 755         i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
 756                         (pdata->hdmi_phy_auto_reset_tmds_detected ?
 757                          MASK_PHY_AUTO_RST2 : 0) |
 758                         (pdata->hdmi_phy_auto_reset_tmds_in_range ?
 759                          MASK_PHY_AUTO_RST3 : 0) |
 760                         (pdata->hdmi_phy_auto_reset_tmds_valid ?
 761                          MASK_PHY_AUTO_RST4 : 0));
 762         i2c_wr8(sd, PHY_BIAS, 0x40);
 763         i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
 764         i2c_wr8(sd, AVM_CTL, 45);
 765         i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
 766                         pdata->hdmi_detection_delay << 4);
 767         i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
 768                         (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
 769                          MASK_H_PI_RST : 0) |
 770                         (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
 771                          MASK_V_PI_RST : 0));
 772         i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
 773 }
 774
 775 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
 776 {
 777         struct tc358743_state *state = to_state(sd);
 778
 779         /* Default settings from REF_02, sheet "Source HDMI" */
 780         i2c_wr8(sd, FORCE_MUTE, 0x00);
 781         i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
 782                         MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
 783                         MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
 784         i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
 785         i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
 786         i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
 787         i2c_wr8(sd, FS_MUTE, 0x00);
 788         i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
 789         i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
 790         i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
 791         i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
 792         i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
 793         i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
 794
 795         mutex_lock(&state->confctl_mutex);
 796         i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
 797                         MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
 798         mutex_unlock(&state->confctl_mutex);
 799 }
 800
 801 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
 802 {
 803         /* Default settings from REF_02, sheet "Source HDMI" */
 804         i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
 805                         MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
 806                         MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
 807                         MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
 808         i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
 809         i2c_wr8(sd, NO_PKT_CLR, 0x53);
 810         i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
 811         i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
 812         i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
 813 }
 814
 815 static void tc358743_initial_setup(struct v4l2_subdev *sd)
 816 {
 817         struct tc358743_state *state = to_state(sd);
 818         struct tc358743_platform_data *pdata = &state->pdata;
 819
 820         /* CEC and IR are not supported by this driver */
 821         i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST),
 822                         (MASK_CECRST | MASK_IRRST));
 823
 824         tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
 825         tc358743_sleep_mode(sd, false);
 826
 827         i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
 828
 829         tc358743_set_ref_clk(sd);
 830
 831         i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
 832                         pdata->ddc5v_delay & MASK_DDC5V_MODE);
 833         i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
 834
 835         tc358743_set_hdmi_phy(sd);
 836         tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
 837         tc358743_set_hdmi_audio(sd);
 838         tc358743_set_hdmi_info_frame_mode(sd);
 839
 840         /* All CE and IT formats are detected as RGB full range in DVI mode */
 841         i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
 842
 843         i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
 844                         MASK_VOUTCOLORMODE_AUTO);
 845         i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
 846 }
 847
 848 /* --------------- IRQ --------------- */
 849
 850 static void tc358743_format_change(struct v4l2_subdev *sd)
 851 {
 852         struct tc358743_state *state = to_state(sd);
 853         struct v4l2_dv_timings timings;
 854         const struct v4l2_event tc358743_ev_fmt = {
 855                 .type = V4L2_EVENT_SOURCE_CHANGE,
 856                 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
 857         };
 858
 859         if (tc358743_get_detected_timings(sd, &timings)) {
 860                 enable_stream(sd, false);
 861
 862                 v4l2_dbg(1, debug, sd, "%s: Format changed. No signal\n",
 863                                 __func__);
 864         } else {
 865                 if (!v4l2_match_dv_timings(&state->timings, &timings, 0))
 866                         enable_stream(sd, false);
 867
 868                 v4l2_print_dv_timings(sd->name,
 869                                 "tc358743_format_change: Format changed. New format: ",
 870                                 &timings, false);
 871         }
 872
 873         if (sd->devnode)
 874                 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
 875 }
 876
 877 static void tc358743_init_interrupts(struct v4l2_subdev *sd)
 878 {
 879         u16 i;
 880
 881         /* clear interrupt status registers */
 882         for (i = SYS_INT; i <= KEY_INT; i++)
 883                 i2c_wr8(sd, i, 0xff);
 884
 885         i2c_wr16(sd, INTSTATUS, 0xffff);
 886 }
 887
 888 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
 889                 bool cable_connected)
 890 {
 891         v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
 892                         cable_connected);
 893
 894         if (cable_connected) {
 895                 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
 896                                         MASK_M_HDMI_DET) & 0xff);
 897                 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
 898                 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
 899                                         MASK_M_AF_UNLOCK) & 0xff);
 900                 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
 901                 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
 902         } else {
 903                 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
 904                 i2c_wr8(sd, CLK_INTM, 0xff);
 905                 i2c_wr8(sd, CBIT_INTM, 0xff);
 906                 i2c_wr8(sd, AUDIO_INTM, 0xff);
 907                 i2c_wr8(sd, MISC_INTM, 0xff);
 908         }
 909 }
 910
 911 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,
 912                 bool *handled)
 913 {
 914         u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
 915         u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
 916
 917         i2c_wr8(sd, AUDIO_INT, audio_int);
 918
 919         v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
 920
 921         tc358743_s_ctrl_audio_sampling_rate(sd);
 922         tc358743_s_ctrl_audio_present(sd);
 923 }
 924
 925 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
 926 {
 927         v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
 928
 929         i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
 930 }
 931
 932 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
 933                 bool *handled)
 934 {
 935         u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
 936         u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
 937
 938         i2c_wr8(sd, MISC_INT, misc_int);
 939
 940         v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
 941
 942         if (misc_int & MASK_I_SYNC_CHG) {
 943                 /* Reset the HDMI PHY to try to trigger proper lock on the
 944                  * incoming video format. Erase BKSV to prevent that old keys
 945                  * are used when a new source is connected. */
 946                 if (no_sync(sd) || no_signal(sd)) {
 947                         tc358743_reset_phy(sd);
 948                         tc358743_erase_bksv(sd);
 949                 }
 950
 951                 tc358743_format_change(sd);
 952
 953                 misc_int &= ~MASK_I_SYNC_CHG;
 954                 if (handled)
 955                         *handled = true;
 956         }
 957
 958         if (misc_int) {
 959                 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
 960                                 __func__, misc_int);
 961         }
 962 }
 963
 964 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
 965                 bool *handled)
 966 {
 967         u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
 968         u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
 969
 970         i2c_wr8(sd, CBIT_INT, cbit_int);
 971
 972         v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
 973
 974         if (cbit_int & MASK_I_CBIT_FS) {
 975
 976                 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
 977                                 __func__);
 978                 tc358743_s_ctrl_audio_sampling_rate(sd);
 979
 980                 cbit_int &= ~MASK_I_CBIT_FS;
 981                 if (handled)
 982                         *handled = true;
 983         }
 984
 985         if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
 986
 987                 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
 988                                 __func__);
 989                 tc358743_s_ctrl_audio_present(sd);
 990
 991                 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
 992                 if (handled)
 993                         *handled = true;
 994         }
 995
 996         if (cbit_int) {
 997                 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
 998                                 __func__, cbit_int);
 999         }
1000 }
1001
1002 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
1003 {
1004         u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
1005         u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
1006
1007         /* Bit 7 and bit 6 are set even when they are masked */
1008         i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
1009
1010         v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
1011
1012         if (clk_int & (MASK_I_IN_DE_CHG)) {
1013
1014                 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1015                                 __func__);
1016
1017                 /* If the source switch to a new resolution with the same pixel
1018                  * frequency as the existing (e.g. 1080p25 -> 720p50), the
1019                  * I_SYNC_CHG interrupt is not always triggered, while the
1020                  * I_IN_DE_CHG interrupt seems to work fine. Format change
1021                  * notifications are only sent when the signal is stable to
1022                  * reduce the number of notifications. */
1023                 if (!no_signal(sd) && !no_sync(sd))
1024                         tc358743_format_change(sd);
1025
1026                 clk_int &= ~(MASK_I_IN_DE_CHG);
1027                 if (handled)
1028                         *handled = true;
1029         }
1030
1031         if (clk_int) {
1032                 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1033                                 __func__, clk_int);
1034         }
1035 }
1036
1037 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1038 {
1039         struct tc358743_state *state = to_state(sd);
1040         u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1041         u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1042
1043         i2c_wr8(sd, SYS_INT, sys_int);
1044
1045         v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1046
1047         if (sys_int & MASK_I_DDC) {
1048                 bool tx_5v = tx_5v_power_present(sd);
1049
1050                 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1051                                 __func__, tx_5v ?  "yes" : "no");
1052
1053                 if (tx_5v) {
1054                         tc358743_enable_edid(sd);
1055                 } else {
1056                         tc358743_enable_interrupts(sd, false);
1057                         tc358743_disable_edid(sd);
1058                         memset(&state->timings, 0, sizeof(state->timings));
1059                         tc358743_erase_bksv(sd);
1060                         tc358743_update_controls(sd);
1061                 }
1062
1063                 sys_int &= ~MASK_I_DDC;
1064                 if (handled)
1065                         *handled = true;
1066         }
1067
1068         if (sys_int & MASK_I_DVI) {
1069                 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1070                                 __func__);
1071
1072                 /* Reset the HDMI PHY to try to trigger proper lock on the
1073                  * incoming video format. Erase BKSV to prevent that old keys
1074                  * are used when a new source is connected. */
1075                 if (no_sync(sd) || no_signal(sd)) {
1076                         tc358743_reset_phy(sd);
1077                         tc358743_erase_bksv(sd);
1078                 }
1079
1080                 sys_int &= ~MASK_I_DVI;
1081                 if (handled)
1082                         *handled = true;
1083         }
1084
1085         if (sys_int & MASK_I_HDMI) {
1086                 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1087                                 __func__);
1088
1089                 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
1090                 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1091
1092                 sys_int &= ~MASK_I_HDMI;
1093                 if (handled)
1094                         *handled = true;
1095         }
1096
1097         if (sys_int) {
1098                 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1099                                 __func__, sys_int);
1100         }
1101 }
1102
1103 /* --------------- CORE OPS --------------- */
1104
1105 static int tc358743_log_status(struct v4l2_subdev *sd)
1106 {
1107         struct tc358743_state *state = to_state(sd);
1108         struct v4l2_dv_timings timings;
1109         uint8_t hdmi_sys_status =  i2c_rd8(sd, SYS_STATUS);
1110         uint16_t sysctl = i2c_rd16(sd, SYSCTL);
1111         u8 vi_status3 =  i2c_rd8(sd, VI_STATUS3);
1112         const int deep_color_mode[4] = { 8, 10, 12, 16 };
1113         static const char * const input_color_space[] = {
1114                 "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)",
1115                 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
1116                 "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"};
1117
1118         v4l2_info(sd, "-----Chip status-----\n");
1119         v4l2_info(sd, "Chip ID: 0x%02x\n",
1120                         (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
1121         v4l2_info(sd, "Chip revision: 0x%02x\n",
1122                         i2c_rd16(sd, CHIPID) & MASK_REVID);
1123         v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1124                         !!(sysctl & MASK_IRRST),
1125                         !!(sysctl & MASK_CECRST),
1126                         !!(sysctl & MASK_CTXRST),
1127                         !!(sysctl & MASK_HDMIRST));
1128         v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1129         v4l2_info(sd, "Cable detected (+5V power): %s\n",
1130                         hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
1131         v4l2_info(sd, "DDC lines enabled: %s\n",
1132                         (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
1133                         "yes" : "no");
1134         v4l2_info(sd, "Hotplug enabled: %s\n",
1135                         (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1136                         "yes" : "no");
1137         v4l2_info(sd, "CEC enabled: %s\n",
1138                         (i2c_rd16(sd, CECEN) & MASK_CECEN) ?  "yes" : "no");
1139         v4l2_info(sd, "-----Signal status-----\n");
1140         v4l2_info(sd, "TMDS signal detected: %s\n",
1141                         hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
1142         v4l2_info(sd, "Stable sync signal: %s\n",
1143                         hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
1144         v4l2_info(sd, "PHY PLL locked: %s\n",
1145                         hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
1146         v4l2_info(sd, "PHY DE detected: %s\n",
1147                         hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
1148
1149         if (tc358743_get_detected_timings(sd, &timings)) {
1150                 v4l2_info(sd, "No video detected\n");
1151         } else {
1152                 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1153                                 true);
1154         }
1155         v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1156                         true);
1157
1158         v4l2_info(sd, "-----CSI-TX status-----\n");
1159         v4l2_info(sd, "Lanes needed: %d\n",
1160                         tc358743_num_csi_lanes_needed(sd));
1161         v4l2_info(sd, "Lanes in use: %d\n",
1162                         tc358743_num_csi_lanes_in_use(sd));
1163         v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1164                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1165                         "yes" : "no");
1166         v4l2_info(sd, "Transmit mode: %s\n",
1167                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1168                         "yes" : "no");
1169         v4l2_info(sd, "Receive mode: %s\n",
1170                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1171                         "yes" : "no");
1172         v4l2_info(sd, "Stopped: %s\n",
1173                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1174                         "yes" : "no");
1175         v4l2_info(sd, "Color space: %s\n",
1176                         state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
1177                         "YCbCr 422 16-bit" :
1178                         state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
1179                         "RGB 888 24-bit" : "Unsupported");
1180
1181         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1182         v4l2_info(sd, "HDCP encrypted content: %s\n",
1183                         hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
1184         v4l2_info(sd, "Input color space: %s %s range\n",
1185                         input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
1186                         (vi_status3 & MASK_LIMITED) ? "limited" : "full");
1187         if (!is_hdmi(sd))
1188                 return 0;
1189         v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1190                         "off");
1191         v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1192                         deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1193                                 MASK_S_DEEPCOLOR) >> 2]);
1194         print_avi_infoframe(sd);
1195
1196         return 0;
1197 }
1198
1199 #ifdef CONFIG_VIDEO_ADV_DEBUG
1200 static void tc358743_print_register_map(struct v4l2_subdev *sd)
1201 {
1202         v4l2_info(sd, "0x0000–0x00FF: Global Control Register\n");
1203         v4l2_info(sd, "0x0100–0x01FF: CSI2-TX PHY Register\n");
1204         v4l2_info(sd, "0x0200–0x03FF: CSI2-TX PPI Register\n");
1205         v4l2_info(sd, "0x0400–0x05FF: Reserved\n");
1206         v4l2_info(sd, "0x0600–0x06FF: CEC Register\n");
1207         v4l2_info(sd, "0x0700–0x84FF: Reserved\n");
1208         v4l2_info(sd, "0x8500–0x85FF: HDMIRX System Control Register\n");
1209         v4l2_info(sd, "0x8600–0x86FF: HDMIRX Audio Control Register\n");
1210         v4l2_info(sd, "0x8700–0x87FF: HDMIRX InfoFrame packet data Register\n");
1211         v4l2_info(sd, "0x8800–0x88FF: HDMIRX HDCP Port Register\n");
1212         v4l2_info(sd, "0x8900–0x89FF: HDMIRX Video Output Port & 3D Register\n");
1213         v4l2_info(sd, "0x8A00–0x8BFF: Reserved\n");
1214         v4l2_info(sd, "0x8C00–0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
1215         v4l2_info(sd, "0x9000–0x90FF: HDMIRX GBD Extraction Control\n");
1216         v4l2_info(sd, "0x9100–0x92FF: HDMIRX GBD RAM read\n");
1217         v4l2_info(sd, "0x9300-      : Reserved\n");
1218 }
1219
1220 static int tc358743_get_reg_size(u16 address)
1221 {
1222         /* REF_01 p. 66-72 */
1223         if (address <= 0x00ff)
1224                 return 2;
1225         else if ((address >= 0x0100) && (address <= 0x06FF))
1226                 return 4;
1227         else if ((address >= 0x0700) && (address <= 0x84ff))
1228                 return 2;
1229         else
1230                 return 1;
1231 }
1232
1233 static int tc358743_g_register(struct v4l2_subdev *sd,
1234                                struct v4l2_dbg_register *reg)
1235 {
1236         if (reg->reg > 0xffff) {
1237                 tc358743_print_register_map(sd);
1238                 return -EINVAL;
1239         }
1240
1241         reg->size = tc358743_get_reg_size(reg->reg);
1242
1243         i2c_rd(sd, reg->reg, (u8 *)&reg->val, reg->size);
1244
1245         return 0;
1246 }
1247
1248 static int tc358743_s_register(struct v4l2_subdev *sd,
1249                                const struct v4l2_dbg_register *reg)
1250 {
1251         if (reg->reg > 0xffff) {
1252                 tc358743_print_register_map(sd);
1253                 return -EINVAL;
1254         }
1255
1256         /* It should not be possible for the user to enable HDCP with a simple
1257          * v4l2-dbg command.
1258          *
1259          * DO NOT REMOVE THIS unless all other issues with HDCP have been
1260          * resolved.
1261          */
1262         if (reg->reg == HDCP_MODE ||
1263             reg->reg == HDCP_REG1 ||
1264             reg->reg == HDCP_REG2 ||
1265             reg->reg == HDCP_REG3 ||
1266             reg->reg == BCAPS)
1267                 return 0;
1268
1269         i2c_wr(sd, (u16)reg->reg, (u8 *)&reg->val,
1270                         tc358743_get_reg_size(reg->reg));
1271
1272         return 0;
1273 }
1274 #endif
1275
1276 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1277 {
1278         u16 intstatus = i2c_rd16(sd, INTSTATUS);
1279
1280         v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
1281
1282         if (intstatus & MASK_HDMI_INT) {
1283                 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1284                 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1285
1286                 if (hdmi_int0 & MASK_I_MISC)
1287                         tc358743_hdmi_misc_int_handler(sd, handled);
1288                 if (hdmi_int1 & MASK_I_CBIT)
1289                         tc358743_hdmi_cbit_int_handler(sd, handled);
1290                 if (hdmi_int1 & MASK_I_CLK)
1291                         tc358743_hdmi_clk_int_handler(sd, handled);
1292                 if (hdmi_int1 & MASK_I_SYS)
1293                         tc358743_hdmi_sys_int_handler(sd, handled);
1294                 if (hdmi_int1 & MASK_I_AUD)
1295                         tc358743_hdmi_audio_int_handler(sd, handled);
1296
1297                 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1298                 intstatus &= ~MASK_HDMI_INT;
1299         }
1300
1301         if (intstatus & MASK_CSI_INT) {
1302                 u32 csi_int = i2c_rd32(sd, CSI_INT);
1303
1304                 if (csi_int & MASK_INTER)
1305                         tc358743_csi_err_int_handler(sd, handled);
1306
1307                 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
1308                 intstatus &= ~MASK_CSI_INT;
1309         }
1310
1311         intstatus = i2c_rd16(sd, INTSTATUS);
1312         if (intstatus) {
1313                 v4l2_dbg(1, debug, sd,
1314                                 "%s: Unhandled IntStatus interrupts: 0x%02x\n",
1315                                 __func__, intstatus);
1316         }
1317
1318         return 0;
1319 }
1320
1321 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
1322 {
1323         struct tc358743_state *state = dev_id;
1324         bool handled;
1325
1326         tc358743_isr(&state->sd, 0, &handled);
1327
1328         return handled ? IRQ_HANDLED : IRQ_NONE;
1329 }
1330
1331 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1332                                     struct v4l2_event_subscription *sub)
1333 {
1334         switch (sub->type) {
1335         case V4L2_EVENT_SOURCE_CHANGE:
1336                 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1337         case V4L2_EVENT_CTRL:
1338                 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1339         default:
1340                 return -EINVAL;
1341         }
1342 }
1343
1344 /* --------------- VIDEO OPS --------------- */
1345
1346 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
1347 {
1348         *status = 0;
1349         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1350         *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1351
1352         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1353
1354         return 0;
1355 }
1356
1357 static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
1358                                  struct v4l2_dv_timings *timings)
1359 {
1360         struct tc358743_state *state = to_state(sd);
1361
1362         if (!timings)
1363                 return -EINVAL;
1364
1365         if (debug)
1366                 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
1367                                 timings, false);
1368
1369         if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1370                 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1371                 return 0;
1372         }
1373
1374         if (!v4l2_valid_dv_timings(timings,
1375                                 &tc358743_timings_cap, NULL, NULL)) {
1376                 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1377                 return -ERANGE;
1378         }
1379
1380         state->timings = *timings;
1381
1382         enable_stream(sd, false);
1383         tc358743_set_pll(sd);
1384         tc358743_set_csi(sd);
1385
1386         return 0;
1387 }
1388
1389 static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
1390                                  struct v4l2_dv_timings *timings)
1391 {
1392         struct tc358743_state *state = to_state(sd);
1393
1394         *timings = state->timings;
1395
1396         return 0;
1397 }
1398
1399 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
1400                                     struct v4l2_enum_dv_timings *timings)
1401 {
1402         if (timings->pad != 0)
1403                 return -EINVAL;
1404
1405         return v4l2_enum_dv_timings_cap(timings,
1406                         &tc358743_timings_cap, NULL, NULL);
1407 }
1408
1409 static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
1410                 struct v4l2_dv_timings *timings)
1411 {
1412         int ret;
1413
1414         ret = tc358743_get_detected_timings(sd, timings);
1415         if (ret)
1416                 return ret;
1417
1418         if (debug)
1419                 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
1420                                 timings, false);
1421
1422         if (!v4l2_valid_dv_timings(timings,
1423                                 &tc358743_timings_cap, NULL, NULL)) {
1424                 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1425                 return -ERANGE;
1426         }
1427
1428         return 0;
1429 }
1430
1431 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
1432                 struct v4l2_dv_timings_cap *cap)
1433 {
1434         if (cap->pad != 0)
1435                 return -EINVAL;
1436
1437         *cap = tc358743_timings_cap;
1438
1439         return 0;
1440 }
1441
1442 static int tc358743_g_mbus_config(struct v4l2_subdev *sd,
1443                              struct v4l2_mbus_config *cfg)
1444 {
1445         cfg->type = V4L2_MBUS_CSI2;
1446
1447         /* Support for non-continuous CSI-2 clock is missing in the driver */
1448         cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1449
1450         switch (tc358743_num_csi_lanes_in_use(sd)) {
1451         case 1:
1452                 cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
1453                 break;
1454         case 2:
1455                 cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
1456                 break;
1457         case 3:
1458                 cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
1459                 break;
1460         case 4:
1461                 cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
1462                 break;
1463         default:
1464                 return -EINVAL;
1465         }
1466
1467         return 0;
1468 }
1469
1470 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
1471 {
1472         enable_stream(sd, enable);
1473
1474         return 0;
1475 }
1476
1477 /* --------------- PAD OPS --------------- */
1478
1479 static int tc358743_get_fmt(struct v4l2_subdev *sd,
1480                 struct v4l2_subdev_pad_config *cfg,
1481                 struct v4l2_subdev_format *format)
1482 {
1483         struct tc358743_state *state = to_state(sd);
1484         u8 vi_rep = i2c_rd8(sd, VI_REP);
1485
1486         if (format->pad != 0)
1487                 return -EINVAL;
1488
1489         format->format.code = state->mbus_fmt_code;
1490         format->format.width = state->timings.bt.width;
1491         format->format.height = state->timings.bt.height;
1492         format->format.field = V4L2_FIELD_NONE;
1493
1494         switch (vi_rep & MASK_VOUT_COLOR_SEL) {
1495         case MASK_VOUT_COLOR_RGB_FULL:
1496         case MASK_VOUT_COLOR_RGB_LIMITED:
1497                 format->format.colorspace = V4L2_COLORSPACE_SRGB;
1498                 break;
1499         case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
1500         case MASK_VOUT_COLOR_601_YCBCR_FULL:
1501                 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1502                 break;
1503         case MASK_VOUT_COLOR_709_YCBCR_FULL:
1504         case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
1505                 format->format.colorspace = V4L2_COLORSPACE_REC709;
1506                 break;
1507         default:
1508                 format->format.colorspace = 0;
1509                 break;
1510         }
1511
1512         return 0;
1513 }
1514
1515 static int tc358743_set_fmt(struct v4l2_subdev *sd,
1516                 struct v4l2_subdev_pad_config *cfg,
1517                 struct v4l2_subdev_format *format)
1518 {
1519         struct tc358743_state *state = to_state(sd);
1520
1521         u32 code = format->format.code; /* is overwritten by get_fmt */
1522         int ret = tc358743_get_fmt(sd, cfg, format);
1523
1524         format->format.code = code;
1525
1526         if (ret)
1527                 return ret;
1528
1529         switch (code) {
1530         case MEDIA_BUS_FMT_RGB888_1X24:
1531         case MEDIA_BUS_FMT_UYVY8_1X16:
1532                 break;
1533         default:
1534                 return -EINVAL;
1535         }
1536
1537         if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1538                 return 0;
1539
1540         state->mbus_fmt_code = format->format.code;
1541
1542         enable_stream(sd, false);
1543         tc358743_set_pll(sd);
1544         tc358743_set_csi(sd);
1545         tc358743_set_csi_color_space(sd);
1546
1547         return 0;
1548 }
1549
1550 static int tc358743_g_edid(struct v4l2_subdev *sd,
1551                 struct v4l2_subdev_edid *edid)
1552 {
1553         struct tc358743_state *state = to_state(sd);
1554
1555         if (edid->pad != 0)
1556                 return -EINVAL;
1557
1558         if (edid->start_block == 0 && edid->blocks == 0) {
1559                 edid->blocks = state->edid_blocks_written;
1560                 return 0;
1561         }
1562
1563         if (state->edid_blocks_written == 0)
1564                 return -ENODATA;
1565
1566         if (edid->start_block >= state->edid_blocks_written ||
1567                         edid->blocks == 0)
1568                 return -EINVAL;
1569
1570         if (edid->start_block + edid->blocks > state->edid_blocks_written)
1571                 edid->blocks = state->edid_blocks_written - edid->start_block;
1572
1573         i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1574                         edid->blocks * EDID_BLOCK_SIZE);
1575
1576         return 0;
1577 }
1578
1579 static int tc358743_s_edid(struct v4l2_subdev *sd,
1580                                 struct v4l2_subdev_edid *edid)
1581 {
1582         struct tc358743_state *state = to_state(sd);
1583         u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
1584
1585         v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1586                  __func__, edid->pad, edid->start_block, edid->blocks);
1587
1588         if (edid->pad != 0)
1589                 return -EINVAL;
1590
1591         if (edid->start_block != 0)
1592                 return -EINVAL;
1593
1594         if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1595                 edid->blocks = EDID_NUM_BLOCKS_MAX;
1596                 return -E2BIG;
1597         }
1598
1599         tc358743_disable_edid(sd);
1600
1601         i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
1602         i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1603
1604         if (edid->blocks == 0) {
1605                 state->edid_blocks_written = 0;
1606                 return 0;
1607         }
1608
1609         i2c_wr(sd, EDID_RAM, edid->edid, edid_len);
1610
1611         state->edid_blocks_written = edid->blocks;
1612
1613         if (tx_5v_power_present(sd))
1614                 tc358743_enable_edid(sd);
1615
1616         return 0;
1617 }
1618
1619 /* -------------------------------------------------------------------------- */
1620
1621 static const struct v4l2_subdev_core_ops tc358743_core_ops = {
1622         .log_status = tc358743_log_status,
1623 #ifdef CONFIG_VIDEO_ADV_DEBUG
1624         .g_register = tc358743_g_register,
1625         .s_register = tc358743_s_register,
1626 #endif
1627         .interrupt_service_routine = tc358743_isr,
1628         .subscribe_event = tc358743_subscribe_event,
1629         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1630 };
1631
1632 static const struct v4l2_subdev_video_ops tc358743_video_ops = {
1633         .g_input_status = tc358743_g_input_status,
1634         .s_dv_timings = tc358743_s_dv_timings,
1635         .g_dv_timings = tc358743_g_dv_timings,
1636         .query_dv_timings = tc358743_query_dv_timings,
1637         .g_mbus_config = tc358743_g_mbus_config,
1638         .s_stream = tc358743_s_stream,
1639 };
1640
1641 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
1642         .set_fmt = tc358743_set_fmt,
1643         .get_fmt = tc358743_get_fmt,
1644         .get_edid = tc358743_g_edid,
1645         .set_edid = tc358743_s_edid,
1646         .enum_dv_timings = tc358743_enum_dv_timings,
1647         .dv_timings_cap = tc358743_dv_timings_cap,
1648 };
1649
1650 static const struct v4l2_subdev_ops tc358743_ops = {
1651         .core = &tc358743_core_ops,
1652         .video = &tc358743_video_ops,
1653         .pad = &tc358743_pad_ops,
1654 };
1655
1656 /* --------------- CUSTOM CTRLS --------------- */
1657
1658 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
1659         .id = TC358743_CID_AUDIO_SAMPLING_RATE,
1660         .name = "Audio sampling rate",
1661         .type = V4L2_CTRL_TYPE_INTEGER,
1662         .min = 0,
1663         .max = 768000,
1664         .step = 1,
1665         .def = 0,
1666         .flags = V4L2_CTRL_FLAG_READ_ONLY,
1667 };
1668
1669 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
1670         .id = TC358743_CID_AUDIO_PRESENT,
1671         .name = "Audio present",
1672         .type = V4L2_CTRL_TYPE_BOOLEAN,
1673         .min = 0,
1674         .max = 1,
1675         .step = 1,
1676         .def = 0,
1677         .flags = V4L2_CTRL_FLAG_READ_ONLY,
1678 };
1679
1680 /* --------------- PROBE / REMOVE --------------- */
1681
1682 #ifdef CONFIG_OF
1683 static void tc358743_gpio_reset(struct tc358743_state *state)
1684 {
1685         usleep_range(5000, 10000);
1686         gpiod_set_value(state->reset_gpio, 1);
1687         usleep_range(1000, 2000);
1688         gpiod_set_value(state->reset_gpio, 0);
1689         msleep(20);
1690 }
1691
1692 static int tc358743_probe_of(struct tc358743_state *state)
1693 {
1694         struct device *dev = &state->i2c_client->dev;
1695         struct v4l2_of_endpoint *endpoint;
1696         struct device_node *ep;
1697         struct clk *refclk;
1698         u32 bps_pr_lane;
1699         int ret = -EINVAL;
1700
1701         refclk = devm_clk_get(dev, "refclk");
1702         if (IS_ERR(refclk)) {
1703                 if (PTR_ERR(refclk) != -EPROBE_DEFER)
1704                         dev_err(dev, "failed to get refclk: %ld\n",
1705                                 PTR_ERR(refclk));
1706                 return PTR_ERR(refclk);
1707         }
1708
1709         ep = of_graph_get_next_endpoint(dev->of_node, NULL);
1710         if (!ep) {
1711                 dev_err(dev, "missing endpoint node\n");
1712                 return -EINVAL;
1713         }
1714
1715         endpoint = v4l2_of_alloc_parse_endpoint(ep);
1716         if (IS_ERR(endpoint)) {
1717                 dev_err(dev, "failed to parse endpoint\n");
1718                 return PTR_ERR(endpoint);
1719         }
1720
1721         if (endpoint->bus_type != V4L2_MBUS_CSI2 ||
1722             endpoint->bus.mipi_csi2.num_data_lanes == 0 ||
1723             endpoint->nr_of_link_frequencies == 0) {
1724                 dev_err(dev, "missing CSI-2 properties in endpoint\n");
1725                 goto free_endpoint;
1726         }
1727
1728         state->bus = endpoint->bus.mipi_csi2;
1729
1730         clk_prepare_enable(refclk);
1731
1732         state->pdata.refclk_hz = clk_get_rate(refclk);
1733         state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
1734         state->pdata.enable_hdcp = false;
1735         /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
1736         state->pdata.fifo_level = 16;
1737         /*
1738          * The PLL input clock is obtained by dividing refclk by pll_prd.
1739          * It must be between 6 MHz and 40 MHz, lower frequency is better.
1740          */
1741         switch (state->pdata.refclk_hz) {
1742         case 26000000:
1743         case 27000000:
1744         case 42000000:
1745                 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
1746                 break;
1747         default:
1748                 dev_err(dev, "unsupported refclk rate: %u Hz\n",
1749                         state->pdata.refclk_hz);
1750                 goto disable_clk;
1751         }
1752
1753         /*
1754          * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
1755          * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
1756          */
1757         bps_pr_lane = 2 * endpoint->link_frequencies[0];
1758         if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
1759                 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
1760                 goto disable_clk;
1761         }
1762
1763         /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
1764         state->pdata.pll_fbd = bps_pr_lane /
1765                                state->pdata.refclk_hz * state->pdata.pll_prd;
1766
1767         /*
1768          * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
1769          * link frequency). In principle it should be possible to calculate
1770          * them based on link frequency and resolution.
1771          */
1772         if (bps_pr_lane != 594000000U)
1773                 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
1774         state->pdata.lineinitcnt = 0xe80;
1775         state->pdata.lptxtimecnt = 0x003;
1776         /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
1777         state->pdata.tclk_headercnt = 0x1403;
1778         state->pdata.tclk_trailcnt = 0x00;
1779         /* ths-preparecnt: 3, ths-zerocnt: 1 */
1780         state->pdata.ths_headercnt = 0x0103;
1781         state->pdata.twakeup = 0x4882;
1782         state->pdata.tclk_postcnt = 0x008;
1783         state->pdata.ths_trailcnt = 0x2;
1784         state->pdata.hstxvregcnt = 0;
1785
1786         state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1787                                                     GPIOD_OUT_LOW);
1788         if (IS_ERR(state->reset_gpio)) {
1789                 dev_err(dev, "failed to get reset gpio\n");
1790                 ret = PTR_ERR(state->reset_gpio);
1791                 goto disable_clk;
1792         }
1793
1794         if (state->reset_gpio)
1795                 tc358743_gpio_reset(state);
1796
1797         ret = 0;
1798         goto free_endpoint;
1799
1800 disable_clk:
1801         clk_disable_unprepare(refclk);
1802 free_endpoint:
1803         v4l2_of_free_endpoint(endpoint);
1804         return ret;
1805 }
1806 #else
1807 static inline int tc358743_probe_of(struct tc358743_state *state)
1808 {
1809         return -ENODEV;
1810 }
1811 #endif
1812
1813 static int tc358743_probe(struct i2c_client *client,
1814                           const struct i2c_device_id *id)
1815 {
1816         static struct v4l2_dv_timings default_timing =
1817                 V4L2_DV_BT_CEA_640X480P59_94;
1818         struct tc358743_state *state;
1819         struct tc358743_platform_data *pdata = client->dev.platform_data;
1820         struct v4l2_subdev *sd;
1821         int err;
1822
1823         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1824                 return -EIO;
1825         v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
1826                 client->addr << 1, client->adapter->name);
1827
1828         state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
1829                         GFP_KERNEL);
1830         if (!state)
1831                 return -ENOMEM;
1832
1833         state->i2c_client = client;
1834
1835         /* platform data */
1836         if (pdata) {
1837                 state->pdata = *pdata;
1838                 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1839         } else {
1840                 err = tc358743_probe_of(state);
1841                 if (err == -ENODEV)
1842                         v4l_err(client, "No platform data!\n");
1843                 if (err)
1844                         return err;
1845         }
1846
1847         sd = &state->sd;
1848         v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
1849         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1850
1851         /* i2c access */
1852         if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {
1853                 v4l2_info(sd, "not a TC358743 on address 0x%x\n",
1854                           client->addr << 1);
1855                 return -ENODEV;
1856         }
1857
1858         /* control handlers */
1859         v4l2_ctrl_handler_init(&state->hdl, 3);
1860
1861         /* private controls */
1862         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
1863                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
1864
1865         /* custom controls */
1866         state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
1867                         &tc358743_ctrl_audio_sampling_rate, NULL);
1868
1869         state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
1870                         &tc358743_ctrl_audio_present, NULL);
1871
1872         sd->ctrl_handler = &state->hdl;
1873         if (state->hdl.error) {
1874                 err = state->hdl.error;
1875                 goto err_hdl;
1876         }
1877
1878         if (tc358743_update_controls(sd)) {
1879                 err = -ENODEV;
1880                 goto err_hdl;
1881         }
1882
1883         /* work queues */
1884         state->work_queues = create_singlethread_workqueue(client->name);
1885         if (!state->work_queues) {
1886                 v4l2_err(sd, "Could not create work queue\n");
1887                 err = -ENOMEM;
1888                 goto err_hdl;
1889         }
1890
1891         state->pad.flags = MEDIA_PAD_FL_SOURCE;
1892         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
1893         if (err < 0)
1894                 goto err_hdl;
1895
1896         sd->dev = &client->dev;
1897         err = v4l2_async_register_subdev(sd);
1898         if (err < 0)
1899                 goto err_hdl;
1900
1901         mutex_init(&state->confctl_mutex);
1902
1903         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
1904                         tc358743_delayed_work_enable_hotplug);
1905
1906         tc358743_initial_setup(sd);
1907
1908         tc358743_s_dv_timings(sd, &default_timing);
1909
1910         state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
1911         tc358743_set_csi_color_space(sd);
1912
1913         tc358743_init_interrupts(sd);
1914
1915         if (state->i2c_client->irq) {
1916                 err = devm_request_threaded_irq(&client->dev,
1917                                                 state->i2c_client->irq,
1918                                                 NULL, tc358743_irq_handler,
1919                                                 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1920                                                 "tc358743", state);
1921                 if (err)
1922                         goto err_work_queues;
1923         }
1924
1925         tc358743_enable_interrupts(sd, tx_5v_power_present(sd));
1926         i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff);
1927
1928         err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
1929         if (err)
1930                 goto err_work_queues;
1931
1932         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1933                   client->addr << 1, client->adapter->name);
1934
1935         return 0;
1936
1937 err_work_queues:
1938         cancel_delayed_work(&state->delayed_work_enable_hotplug);
1939         destroy_workqueue(state->work_queues);
1940         mutex_destroy(&state->confctl_mutex);
1941 err_hdl:
1942         media_entity_cleanup(&sd->entity);
1943         v4l2_ctrl_handler_free(&state->hdl);
1944         return err;
1945 }
1946
1947 static int tc358743_remove(struct i2c_client *client)
1948 {
1949         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1950         struct tc358743_state *state = to_state(sd);
1951
1952         cancel_delayed_work(&state->delayed_work_enable_hotplug);
1953         destroy_workqueue(state->work_queues);
1954         v4l2_async_unregister_subdev(sd);
1955         v4l2_device_unregister_subdev(sd);
1956         mutex_destroy(&state->confctl_mutex);
1957         media_entity_cleanup(&sd->entity);
1958         v4l2_ctrl_handler_free(&state->hdl);
1959
1960         return 0;
1961 }
1962
1963 static struct i2c_device_id tc358743_id[] = {
1964         {"tc358743", 0},
1965         {}
1966 };
1967
1968 MODULE_DEVICE_TABLE(i2c, tc358743_id);
1969
1970 static struct i2c_driver tc358743_driver = {
1971         .driver = {
1972                 .name = "tc358743",
1973         },
1974         .probe = tc358743_probe,
1975         .remove = tc358743_remove,
1976         .id_table = tc358743_id,
1977 };
1978
1979 module_i2c_driver(tc358743_driver);